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drm/i915/gen9: Initialize intel_state->active_crtcs during WM sanitization (v2)
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
936e71e3 968 if (!state->base.visible)
262cd2e1
VS		 969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
936e71e3 1010 if (state->base.visible) {
54f1b6e1
VS		 1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
936e71e3 1026 if (!state->base.visible) {
54f1b6e1
VS		 1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
936e71e3 1126 if (!state->base.visible)
262cd2e1
VS		 1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
936e71e3 1778 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1788 drm_rect_width(&pstate->base.dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
936e71e3 1806 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1812 drm_rect_width(&pstate->base.dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
936e71e3 1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
936e71e3 1849 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1850 return 0;
1851
936e71e3 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
367294be 2129 /*
6f97235b
DL		 2130 * WaWmMemoryReadLatency:skl
2131 *
367294be
VK		 2132 * punit doesn't take into account the read latency so we need
2133 * to add 2us to the various latency levels we retrieve from
2134 * the punit.
2135 * - W0 is a bit special in that it's the only level that
2136 * can't be disabled if we want to have display working, so
2137 * we always add 2us there.
2138 * - For levels >=1, punit returns 0us latency when they are
2139 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2140 *
2141 * Additionally, if a level n (n > 1) has a 0us latency, all
2142 * levels m (m >= n) need to be disabled. We make sure to
2143 * sanitize the values out of the punit to satisfy this
2144 * requirement.
367294be
VK		 2145 */
2146 wm[0] += 2;
2147 for (level = 1; level <= max_level; level++)
2148 if (wm[level] != 0)
2149 wm[level] += 2;
4f947386
VK		 2150 else {
2151 for (i = level + 1; i <= max_level; i++)
2152 wm[i] = 0;
367294be 2153
4f947386
VK		 2154 break;
2155 }
2af30a5c 2156 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2157 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2158
2159 wm[0] = (sskpd >> 56) & 0xFF;
2160 if (wm[0] == 0)
2161 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2162 wm[1] = (sskpd >> 4) & 0xFF;
2163 wm[2] = (sskpd >> 12) & 0xFF;
2164 wm[3] = (sskpd >> 20) & 0x1FF;
2165 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2166 } else if (INTEL_INFO(dev)->gen >= 6) {
2167 uint32_t sskpd = I915_READ(MCH_SSKPD);
2168
2169 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2170 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2171 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2172 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2173 } else if (INTEL_INFO(dev)->gen >= 5) {
2174 uint32_t mltr = I915_READ(MLTR_ILK);
2175
2176 /* ILK primary LP0 latency is 700 ns */
2177 wm[0] = 7;
2178 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2179 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2180 }
2181}
2182
53615a5e
VS		 2183static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184{
2185 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2186 if (IS_GEN5(dev))
53615a5e
VS		 2187 wm[0] = 13;
2188}
2189
2190static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2191{
2192 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2193 if (IS_GEN5(dev))
53615a5e
VS		 2194 wm[0] = 13;
2195
2196 /* WaDoubleCursorLP3Latency:ivb */
2197 if (IS_IVYBRIDGE(dev))
2198 wm[3] *= 2;
2199}
2200
546c81fd 2201int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2202{
26ec971e 2203 /* how many WM levels are we expecting */
b6e742f6 2204 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2205 return 7;
2206 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2207 return 4;
26ec971e 2208 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2209 return 3;
26ec971e 2210 else
ad0d6dc4
VS		 2211 return 2;
2212}
7526ed79 2213
ad0d6dc4
VS		 2214static void intel_print_wm_latency(struct drm_device *dev,
2215 const char *name,
2af30a5c 2216 const uint16_t wm[8])
ad0d6dc4
VS		 2217{
2218 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2219
2220 for (level = 0; level <= max_level; level++) {
2221 unsigned int latency = wm[level];
2222
2223 if (latency == 0) {
2224 DRM_ERROR("%s WM%d latency not provided\n",
2225 name, level);
2226 continue;
2227 }
2228
2af30a5c
PB		 2229 /*
2230 * - latencies are in us on gen9.
2231 * - before then, WM1+ latency values are in 0.5us units
2232 */
2233 if (IS_GEN9(dev))
2234 latency *= 10;
2235 else if (level > 0)
26ec971e
VS		 2236 latency *= 5;
2237
2238 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2239 name, level, wm[level],
2240 latency / 10, latency % 10);
2241 }
2242}
2243
e95a2f75
VS		 2244static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2245 uint16_t wm[5], uint16_t min)
2246{
91c8a326 2247 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2248
2249 if (wm[0] >= min)
2250 return false;
2251
2252 wm[0] = max(wm[0], min);
2253 for (level = 1; level <= max_level; level++)
2254 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2255
2256 return true;
2257}
2258
2259static void snb_wm_latency_quirk(struct drm_device *dev)
2260{
fac5e23e 2261 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2262 bool changed;
2263
2264 /*
2265 * The BIOS provided WM memory latency values are often
2266 * inadequate for high resolution displays. Adjust them.
2267 */
2268 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2269 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2270 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2271
2272 if (!changed)
2273 return;
2274
2275 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2276 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2277 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2278 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2279}
2280
fa50ad61 2281static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2282{
fac5e23e 2283 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2284
2285 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2286
2287 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2288 sizeof(dev_priv->wm.pri_latency));
2289 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291
2292 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2293 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2294
2295 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2296 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2297 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2298
2299 if (IS_GEN6(dev))
2300 snb_wm_latency_quirk(dev);
53615a5e
VS		 2301}
2302
2af30a5c
PB		 2303static void skl_setup_wm_latency(struct drm_device *dev)
2304{
fac5e23e 2305 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2306
2307 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2308 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2309}
2310
ed4a6a7c
MR		 2311static bool ilk_validate_pipe_wm(struct drm_device *dev,
2312 struct intel_pipe_wm *pipe_wm)
2313{
2314 /* LP0 watermark maximums depend on this pipe alone */
2315 const struct intel_wm_config config = {
2316 .num_pipes_active = 1,
2317 .sprites_enabled = pipe_wm->sprites_enabled,
2318 .sprites_scaled = pipe_wm->sprites_scaled,
2319 };
2320 struct ilk_wm_maximums max;
2321
2322 /* LP0 watermarks always use 1/2 DDB partitioning */
2323 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2324
2325 /* At least LP0 must be valid */
2326 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2327 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2328 return false;
2329 }
2330
2331 return true;
2332}
2333
0b2ae6d7 2334/* Compute new watermarks for the pipe */
e3bddded 2335static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2336{
e3bddded
ML		 2337 struct drm_atomic_state *state = cstate->base.state;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2339 struct intel_pipe_wm *pipe_wm;
e3bddded 2340 struct drm_device *dev = state->dev;
fac5e23e 2341 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2342 struct intel_plane *intel_plane;
86c8bbbe 2343 struct intel_plane_state *pristate = NULL;
43d59eda 2344 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2345 struct intel_plane_state *curstate = NULL;
d81f04c5 2346 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2347 struct ilk_wm_maximums max;
0b2ae6d7 2348
e8f1f02e 2349 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2350
43d59eda 2351 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2352 struct intel_plane_state *ps;
2353
2354 ps = intel_atomic_get_existing_plane_state(state,
2355 intel_plane);
2356 if (!ps)
2357 continue;
86c8bbbe
MR		 2358
2359 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2360 pristate = ps;
86c8bbbe 2361 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2362 sprstate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2364 curstate = ps;
43d59eda
MR		 2365 }
2366
ed4a6a7c 2367 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2368 if (sprstate) {
936e71e3
VS		 2369 pipe_wm->sprites_enabled = sprstate->base.visible;
2370 pipe_wm->sprites_scaled = sprstate->base.visible &&
2371 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2372 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2373 }
2374
d81f04c5
ML		 2375 usable_level = max_level;
2376
7b39a0b7 2377 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2378 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2379 usable_level = 1;
7b39a0b7
VS		 2380
2381 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2382 if (pipe_wm->sprites_scaled)
d81f04c5 2383 usable_level = 0;
7b39a0b7 2384
86c8bbbe 2385 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2386 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2387
2388 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2389 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2390
a42a5719 2391 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2392 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2393
ed4a6a7c 2394 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2395 return -EINVAL;
a3cb4048
VS		 2396
2397 ilk_compute_wm_reg_maximums(dev, 1, &max);
2398
2399 for (level = 1; level <= max_level; level++) {
71f0a626 2400 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2401
86c8bbbe 2402 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2403 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2404
2405 /*
2406 * Disable any watermark level that exceeds the
2407 * register maximums since such watermarks are
2408 * always invalid.
2409 */
71f0a626
ML		 2410 if (level > usable_level)
2411 continue;
2412
2413 if (ilk_validate_wm_level(level, &max, wm))
2414 pipe_wm->wm[level] = *wm;
2415 else
d81f04c5 2416 usable_level = level;
a3cb4048
VS		 2417 }
2418
86c8bbbe 2419 return 0;
0b2ae6d7
VS		 2420}
2421
ed4a6a7c
MR		 2422/*
2423 * Build a set of 'intermediate' watermark values that satisfy both the old
2424 * state and the new state. These can be programmed to the hardware
2425 * immediately.
2426 */
2427static int ilk_compute_intermediate_wm(struct drm_device *dev,
2428 struct intel_crtc *intel_crtc,
2429 struct intel_crtc_state *newstate)
2430{
e8f1f02e 2431 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2432 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2433 int level, max_level = ilk_wm_max_level(dev);
2434
2435 /*
2436 * Start with the final, target watermarks, then combine with the
2437 * currently active watermarks to get values that are safe both before
2438 * and after the vblank.
2439 */
e8f1f02e 2440 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2441 a->pipe_enabled |= b->pipe_enabled;
2442 a->sprites_enabled |= b->sprites_enabled;
2443 a->sprites_scaled |= b->sprites_scaled;
2444
2445 for (level = 0; level <= max_level; level++) {
2446 struct intel_wm_level *a_wm = &a->wm[level];
2447 const struct intel_wm_level *b_wm = &b->wm[level];
2448
2449 a_wm->enable &= b_wm->enable;
2450 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2451 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2452 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2453 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2454 }
2455
2456 /*
2457 * We need to make sure that these merged watermark values are
2458 * actually a valid configuration themselves. If they're not,
2459 * there's no safe way to transition from the old state to
2460 * the new state, so we need to fail the atomic transaction.
2461 */
2462 if (!ilk_validate_pipe_wm(dev, a))
2463 return -EINVAL;
2464
2465 /*
2466 * If our intermediate WM are identical to the final WM, then we can
2467 * omit the post-vblank programming; only update if it's different.
2468 */
e8f1f02e 2469 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2470 newstate->wm.need_postvbl_update = false;
2471
2472 return 0;
2473}
2474
0b2ae6d7
VS		 2475/*
2476 * Merge the watermarks from all active pipes for a specific level.
2477 */
2478static void ilk_merge_wm_level(struct drm_device *dev,
2479 int level,
2480 struct intel_wm_level *ret_wm)
2481{
2482 const struct intel_crtc *intel_crtc;
2483
d52fea5b
VS		 2484 ret_wm->enable = true;
2485
d3fcc808 2486 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2487 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2488 const struct intel_wm_level *wm = &active->wm[level];
2489
2490 if (!active->pipe_enabled)
2491 continue;
0b2ae6d7 2492
d52fea5b
VS		 2493 /*
2494 * The watermark values may have been used in the past,
2495 * so we must maintain them in the registers for some
2496 * time even if the level is now disabled.
2497 */
0b2ae6d7 2498 if (!wm->enable)
d52fea5b 2499 ret_wm->enable = false;
0b2ae6d7
VS		 2500
2501 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2502 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2503 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2504 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2505 }
0b2ae6d7
VS		 2506}
2507
2508/*
2509 * Merge all low power watermarks for all active pipes.
2510 */
2511static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2512 const struct intel_wm_config *config,
820c1980 2513 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2514 struct intel_pipe_wm *merged)
2515{
fac5e23e 2516 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2517 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2518 int last_enabled_level = max_level;
0b2ae6d7 2519
0ba22e26
VS		 2520 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2522 config->num_pipes_active > 1)
1204d5ba 2523 last_enabled_level = 0;
0ba22e26 2524
6c8b6c28
VS		 2525 /* ILK: FBC WM must be disabled always */
2526 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2527
2528 /* merge each WM1+ level */
2529 for (level = 1; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 ilk_merge_wm_level(dev, level, wm);
2533
d52fea5b
VS		 2534 if (level > last_enabled_level)
2535 wm->enable = false;
2536 else if (!ilk_validate_wm_level(level, max, wm))
2537 /* make sure all following levels get disabled */
2538 last_enabled_level = level - 1;
0b2ae6d7
VS		 2539
2540 /*
2541 * The spec says it is preferred to disable
2542 * FBC WMs instead of disabling a WM level.
2543 */
2544 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2545 if (wm->enable)
2546 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2547 wm->fbc_val = 0;
2548 }
2549 }
6c8b6c28
VS		 2550
2551 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2552 /*
2553 * FIXME this is racy. FBC might get enabled later.
2554 * What we should check here is whether FBC can be
2555 * enabled sometime later.
2556 */
7733b49b 2557 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2558 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2559 for (level = 2; level <= max_level; level++) {
2560 struct intel_wm_level *wm = &merged->wm[level];
2561
2562 wm->enable = false;
2563 }
2564 }
0b2ae6d7
VS		 2565}
2566
b380ca3c
VS		 2567static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2568{
2569 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2570 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2571}
2572
a68d68ee
VS		 2573/* The value we need to program into the WM_LPx latency field */
2574static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2575{
fac5e23e 2576 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2577
a42a5719 2578 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2579 return 2 * level;
2580 else
2581 return dev_priv->wm.pri_latency[level];
2582}
2583
820c1980 2584static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2585 const struct intel_pipe_wm *merged,
609cedef 2586 enum intel_ddb_partitioning partitioning,
820c1980 2587 struct ilk_wm_values *results)
801bcfff 2588{
0b2ae6d7
VS		 2589 struct intel_crtc *intel_crtc;
2590 int level, wm_lp;
cca32e9a 2591
0362c781 2592 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2593 results->partitioning = partitioning;
cca32e9a 2594
0b2ae6d7 2595 /* LP1+ register values */
cca32e9a 2596 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2597 const struct intel_wm_level *r;
801bcfff 2598
b380ca3c 2599 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2600
0362c781 2601 r = &merged->wm[level];
cca32e9a 2602
d52fea5b
VS		 2603 /*
2604 * Maintain the watermark values even if the level is
2605 * disabled. Doing otherwise could cause underruns.
2606 */
2607 results->wm_lp[wm_lp - 1] =
a68d68ee 2608 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2609 (r->pri_val << WM1_LP_SR_SHIFT) |
2610 r->cur_val;
2611
d52fea5b
VS		 2612 if (r->enable)
2613 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2614
416f4727
VS		 2615 if (INTEL_INFO(dev)->gen >= 8)
2616 results->wm_lp[wm_lp - 1] |=
2617 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2618 else
2619 results->wm_lp[wm_lp - 1] |=
2620 r->fbc_val << WM1_LP_FBC_SHIFT;
2621
d52fea5b
VS		 2622 /*
2623 * Always set WM1S_LP_EN when spr_val != 0, even if the
2624 * level is disabled. Doing otherwise could cause underruns.
2625 */
6cef2b8a
VS		 2626 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2627 WARN_ON(wm_lp != 1);
2628 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2629 } else
2630 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2631 }
801bcfff 2632
0b2ae6d7 2633 /* LP0 register values */
d3fcc808 2634 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2635 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2636 const struct intel_wm_level *r =
2637 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2638
2639 if (WARN_ON(!r->enable))
2640 continue;
2641
ed4a6a7c 2642 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2643
0b2ae6d7
VS		 2644 results->wm_pipe[pipe] =
2645 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2646 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2647 r->cur_val;
801bcfff
PZ		 2648 }
2649}
2650
861f3389
PZ		 2651/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2652 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2653static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2654 struct intel_pipe_wm *r1,
2655 struct intel_pipe_wm *r2)
861f3389 2656{
198a1e9b
VS		 2657 int level, max_level = ilk_wm_max_level(dev);
2658 int level1 = 0, level2 = 0;
861f3389 2659
198a1e9b
VS		 2660 for (level = 1; level <= max_level; level++) {
2661 if (r1->wm[level].enable)
2662 level1 = level;
2663 if (r2->wm[level].enable)
2664 level2 = level;
861f3389
PZ		 2665 }
2666
198a1e9b
VS		 2667 if (level1 == level2) {
2668 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2669 return r2;
2670 else
2671 return r1;
198a1e9b 2672 } else if (level1 > level2) {
861f3389
PZ		 2673 return r1;
2674 } else {
2675 return r2;
2676 }
2677}
2678
49a687c4
VS		 2679/* dirty bits used to track which watermarks need changes */
2680#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2681#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2682#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2683#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2684#define WM_DIRTY_FBC (1 << 24)
2685#define WM_DIRTY_DDB (1 << 25)
2686
055e393f 2687static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2688 const struct ilk_wm_values *old,
2689 const struct ilk_wm_values *new)
49a687c4
VS		 2690{
2691 unsigned int dirty = 0;
2692 enum pipe pipe;
2693 int wm_lp;
2694
055e393f 2695 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2696 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2697 dirty |= WM_DIRTY_LINETIME(pipe);
2698 /* Must disable LP1+ watermarks too */
2699 dirty |= WM_DIRTY_LP_ALL;
2700 }
2701
2702 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2703 dirty |= WM_DIRTY_PIPE(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707 }
2708
2709 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2710 dirty |= WM_DIRTY_FBC;
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714
2715 if (old->partitioning != new->partitioning) {
2716 dirty |= WM_DIRTY_DDB;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 /* LP1+ watermarks already deemed dirty, no need to continue */
2722 if (dirty & WM_DIRTY_LP_ALL)
2723 return dirty;
2724
2725 /* Find the lowest numbered LP1+ watermark in need of an update... */
2726 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2728 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2729 break;
2730 }
2731
2732 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2733 for (; wm_lp <= 3; wm_lp++)
2734 dirty |= WM_DIRTY_LP(wm_lp);
2735
2736 return dirty;
2737}
2738
8553c18e
VS		 2739static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2740 unsigned int dirty)
801bcfff 2741{
820c1980 2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2743 bool changed = false;
801bcfff 2744
facd619b
VS		 2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2746 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2747 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2748 changed = true;
facd619b
VS		 2749 }
2750 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2751 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2752 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2753 changed = true;
facd619b
VS		 2754 }
2755 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2756 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2757 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2758 changed = true;
facd619b 2759 }
801bcfff 2760
facd619b
VS		 2761 /*
2762 * Don't touch WM1S_LP_EN here.
2763 * Doing so could cause underruns.
2764 */
6cef2b8a 2765
8553c18e
VS		 2766 return changed;
2767}
2768
2769/*
2770 * The spec says we shouldn't write when we don't need, because every write
2771 * causes WMs to be re-evaluated, expending some power.
2772 */
820c1980
ID		 2773static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2774 struct ilk_wm_values *results)
8553c18e 2775{
91c8a326 2776 struct drm_device *dev = &dev_priv->drm;
820c1980 2777 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2778 unsigned int dirty;
2779 uint32_t val;
2780
055e393f 2781 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2782 if (!dirty)
2783 return;
2784
2785 _ilk_disable_lp_wm(dev_priv, dirty);
2786
49a687c4 2787 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2788 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2790 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2792 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2793
49a687c4 2794 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2795 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2800
49a687c4 2801 if (dirty & WM_DIRTY_DDB) {
a42a5719 2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2803 val = I915_READ(WM_MISC);
2804 if (results->partitioning == INTEL_DDB_PART_1_2)
2805 val &= ~WM_MISC_DATA_PARTITION_5_6;
2806 else
2807 val |= WM_MISC_DATA_PARTITION_5_6;
2808 I915_WRITE(WM_MISC, val);
2809 } else {
2810 val = I915_READ(DISP_ARB_CTL2);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~DISP_DATA_PARTITION_5_6;
2813 else
2814 val |= DISP_DATA_PARTITION_5_6;
2815 I915_WRITE(DISP_ARB_CTL2, val);
2816 }
1011d8c4
PZ		 2817 }
2818
49a687c4 2819 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2820 val = I915_READ(DISP_ARB_CTL);
2821 if (results->enable_fbc_wm)
2822 val &= ~DISP_FBC_WM_DIS;
2823 else
2824 val |= DISP_FBC_WM_DIS;
2825 I915_WRITE(DISP_ARB_CTL, val);
2826 }
2827
954911eb
ID		 2828 if (dirty & WM_DIRTY_LP(1) &&
2829 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2830 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831
2832 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2833 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2834 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2835 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2836 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2837 }
801bcfff 2838
facd619b 2839 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2840 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2841 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2842 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2843 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2844 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2845
2846 dev_priv->wm.hw = *results;
801bcfff
PZ		 2847}
2848
ed4a6a7c 2849bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2850{
fac5e23e 2851 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2852
2853 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2854}
2855
b9cec075
DL		 2856/*
2857 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2858 * different active planes.
2859 */
2860
2861#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2862#define BXT_DDB_SIZE 512
b9cec075 2863
024c9045
MR		 2864/*
2865 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2866 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867 * other universal planes are in indices 1..n. Note that this may leave unused
2868 * indices between the top "sprite" plane and the cursor.
2869 */
2870static int
2871skl_wm_plane_id(const struct intel_plane *plane)
2872{
2873 switch (plane->base.type) {
2874 case DRM_PLANE_TYPE_PRIMARY:
2875 return 0;
2876 case DRM_PLANE_TYPE_CURSOR:
2877 return PLANE_CURSOR;
2878 case DRM_PLANE_TYPE_OVERLAY:
2879 return plane->plane + 1;
2880 default:
2881 MISSING_CASE(plane->base.type);
2882 return plane->plane;
2883 }
2884}
2885
b9cec075
DL		 2886static void
2887skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2888 const struct intel_crtc_state *cstate,
c107acfe
MR		 2889 struct skl_ddb_entry *alloc, /* out */
2890 int *num_active /* out */)
b9cec075 2891{
c107acfe
MR		 2892 struct drm_atomic_state *state = cstate->base.state;
2893 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2894 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2895 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2896 unsigned int pipe_size, ddb_size;
2897 int nth_active_pipe;
c107acfe
MR		 2898 int pipe = to_intel_crtc(for_crtc)->pipe;
2899
a6d3460e 2900 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 2901 alloc->start = 0;
2902 alloc->end = 0;
a6d3460e 2903 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 2904 return;
2905 }
2906
a6d3460e
MR		 2907 if (intel_state->active_pipe_changes)
2908 *num_active = hweight32(intel_state->active_crtcs);
2909 else
2910 *num_active = hweight32(dev_priv->active_crtcs);
2911
43d735a6
DL		 2912 if (IS_BROXTON(dev))
2913 ddb_size = BXT_DDB_SIZE;
2914 else
2915 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2916
2917 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2918
c107acfe 2919 /*
a6d3460e
MR		 2920 * If the state doesn't change the active CRTC's, then there's
2921 * no need to recalculate; the existing pipe allocation limits
2922 * should remain unchanged. Note that we're safe from racing
2923 * commits since any racing commit that changes the active CRTC
2924 * list would need to grab _all_ crtc locks, including the one
2925 * we currently hold.
c107acfe 2926 */
a6d3460e
MR		 2927 if (!intel_state->active_pipe_changes) {
2928 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2929 return;
c107acfe 2930 }
a6d3460e
MR		 2931
2932 nth_active_pipe = hweight32(intel_state->active_crtcs &
2933 (drm_crtc_mask(for_crtc) - 1));
2934 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2935 alloc->start = nth_active_pipe * ddb_size / *num_active;
2936 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2937}
2938
c107acfe 2939static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2940{
c107acfe 2941 if (num_active == 1)
b9cec075
DL		 2942 return 32;
2943
2944 return 8;
2945}
2946
a269c583
DL		 2947static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2948{
2949 entry->start = reg & 0x3ff;
2950 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2951 if (entry->end)
2952 entry->end += 1;
a269c583
DL		 2953}
2954
08db6652
DL		 2955void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2956 struct skl_ddb_allocation *ddb /* out */)
a269c583 2957{
a269c583
DL		 2958 enum pipe pipe;
2959 int plane;
2960 u32 val;
2961
b10f1b20
ML		 2962 memset(ddb, 0, sizeof(*ddb));
2963
a269c583 2964 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2965 enum intel_display_power_domain power_domain;
2966
2967 power_domain = POWER_DOMAIN_PIPE(pipe);
2968 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2969 continue;
2970
dd740780 2971 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2972 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2973 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2974 val);
2975 }
2976
2977 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2978 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2979 val);
4d800030
ID		 2980
2981 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2982 }
2983}
2984
9c2f7a9d
KM		 2985/*
2986 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2987 * The bspec defines downscale amount as:
2988 *
2989 * """
2990 * Horizontal down scale amount = maximum[1, Horizontal source size /
2991 * Horizontal destination size]
2992 * Vertical down scale amount = maximum[1, Vertical source size /
2993 * Vertical destination size]
2994 * Total down scale amount = Horizontal down scale amount *
2995 * Vertical down scale amount
2996 * """
2997 *
2998 * Return value is provided in 16.16 fixed point form to retain fractional part.
2999 * Caller should take care of dividing & rounding off the value.
3000 */
3001static uint32_t
3002skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3003{
3004 uint32_t downscale_h, downscale_w;
3005 uint32_t src_w, src_h, dst_w, dst_h;
3006
936e71e3 3007 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3008 return DRM_PLANE_HELPER_NO_SCALING;
3009
3010 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3011 src_w = drm_rect_width(&pstate->base.src);
3012 src_h = drm_rect_height(&pstate->base.src);
3013 dst_w = drm_rect_width(&pstate->base.dst);
3014 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3015 if (intel_rotation_90_or_270(pstate->base.rotation))
3016 swap(dst_w, dst_h);
3017
3018 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3019 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3020
3021 /* Provide result in 16.16 fixed point */
3022 return (uint64_t)downscale_w * downscale_h >> 16;
3023}
3024
b9cec075 3025static unsigned int
024c9045
MR		 3026skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3027 const struct drm_plane_state *pstate,
3028 int y)
b9cec075 3029{
a280f7dd 3030 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3031 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3032 uint32_t down_scale_amount, data_rate;
a280f7dd 3033 uint32_t width = 0, height = 0;
a1de91e5
MR		 3034 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3035
936e71e3 3036 if (!intel_pstate->base.visible)
a1de91e5
MR		 3037 return 0;
3038 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3039 return 0;
3040 if (y && format != DRM_FORMAT_NV12)
3041 return 0;
a280f7dd 3042
936e71e3
VS		 3043 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3044 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3045
3046 if (intel_rotation_90_or_270(pstate->rotation))
3047 swap(width, height);
2cd601c6
CK		 3048
3049 /* for planar format */
a1de91e5 3050 if (format == DRM_FORMAT_NV12) {
2cd601c6 3051 if (y) /* y-plane data rate */
8d19d7d9 3052 data_rate = width * height *
a1de91e5 3053 drm_format_plane_cpp(format, 0);
2cd601c6 3054 else /* uv-plane data rate */
8d19d7d9 3055 data_rate = (width / 2) * (height / 2) *
a1de91e5 3056 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3057 } else {
3058 /* for packed formats */
3059 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3060 }
3061
8d19d7d9
KM		 3062 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3063
3064 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3065}
3066
3067/*
3068 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3069 * a 8192x4096@32bpp framebuffer:
3070 * 3 * 4096 * 8192 * 4 < 2^32
3071 */
3072static unsigned int
9c74d826 3073skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3074{
9c74d826
MR		 3075 struct drm_crtc_state *cstate = &intel_cstate->base;
3076 struct drm_atomic_state *state = cstate->state;
3077 struct drm_crtc *crtc = cstate->crtc;
3078 struct drm_device *dev = crtc->dev;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3080 const struct drm_plane *plane;
024c9045 3081 const struct intel_plane *intel_plane;
a6d3460e 3082 struct drm_plane_state *pstate;
a1de91e5 3083 unsigned int rate, total_data_rate = 0;
9c74d826 3084 int id;
a6d3460e
MR		 3085 int i;
3086
3087 if (WARN_ON(!state))
3088 return 0;
b9cec075 3089
a1de91e5 3090 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3091 for_each_plane_in_state(state, plane, pstate, i) {
3092 id = skl_wm_plane_id(to_intel_plane(plane));
3093 intel_plane = to_intel_plane(plane);
3094
3095 if (intel_plane->pipe != intel_crtc->pipe)
3096 continue;
3097
3098 /* packed/uv */
3099 rate = skl_plane_relative_data_rate(intel_cstate,
3100 pstate, 0);
3101 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3102
3103 /* y-plane */
3104 rate = skl_plane_relative_data_rate(intel_cstate,
3105 pstate, 1);
3106 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3107 }
024c9045 3108
a1de91e5
MR		 3109 /* Calculate CRTC's total data rate from cached values */
3110 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3111 int id = skl_wm_plane_id(intel_plane);
024c9045 3112
a1de91e5 3113 /* packed/uv */
9c74d826
MR		 3114 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3115 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3116 }
3117
9c74d826
MR		 3118 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3119
b9cec075
DL		 3120 return total_data_rate;
3121}
3122
cbcfd14b
KM		 3123static uint16_t
3124skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3125 const int y)
3126{
3127 struct drm_framebuffer *fb = pstate->fb;
3128 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3129 uint32_t src_w, src_h;
3130 uint32_t min_scanlines = 8;
3131 uint8_t plane_bpp;
3132
3133 if (WARN_ON(!fb))
3134 return 0;
3135
3136 /* For packed formats, no y-plane, return 0 */
3137 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3138 return 0;
3139
3140 /* For Non Y-tile return 8-blocks */
3141 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3142 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3143 return 8;
3144
936e71e3
VS		 3145 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3146 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3147
3148 if (intel_rotation_90_or_270(pstate->rotation))
3149 swap(src_w, src_h);
3150
3151 /* Halve UV plane width and height for NV12 */
3152 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3153 src_w /= 2;
3154 src_h /= 2;
3155 }
3156
3157 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3158 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3159 else
3160 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3161
3162 if (intel_rotation_90_or_270(pstate->rotation)) {
3163 switch (plane_bpp) {
3164 case 1:
3165 min_scanlines = 32;
3166 break;
3167 case 2:
3168 min_scanlines = 16;
3169 break;
3170 case 4:
3171 min_scanlines = 8;
3172 break;
3173 case 8:
3174 min_scanlines = 4;
3175 break;
3176 default:
3177 WARN(1, "Unsupported pixel depth %u for rotation",
3178 plane_bpp);
3179 min_scanlines = 32;
3180 }
3181 }
3182
3183 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3184}
3185
c107acfe 3186static int
024c9045 3187skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3188 struct skl_ddb_allocation *ddb /* out */)
3189{
c107acfe 3190 struct drm_atomic_state *state = cstate->base.state;
024c9045 3191 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3192 struct drm_device *dev = crtc->dev;
3193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3194 struct intel_plane *intel_plane;
c107acfe
MR		 3195 struct drm_plane *plane;
3196 struct drm_plane_state *pstate;
b9cec075 3197 enum pipe pipe = intel_crtc->pipe;
34bb56af 3198 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3199 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3200 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3201 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3202 unsigned int total_data_rate;
c107acfe
MR		 3203 int num_active;
3204 int id, i;
b9cec075 3205
a6d3460e
MR		 3206 if (WARN_ON(!state))
3207 return 0;
3208
c107acfe
MR		 3209 if (!cstate->base.active) {
3210 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3211 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3212 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3213 return 0;
3214 }
3215
a6d3460e 3216 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3217 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3218 if (alloc_size == 0) {
3219 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3220 return 0;
b9cec075
DL		 3221 }
3222
c107acfe 3223 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3224 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3225 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3226
3227 alloc_size -= cursor_blocks;
b9cec075 3228
80958155 3229 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3230 for_each_plane_in_state(state, plane, pstate, i) {
3231 intel_plane = to_intel_plane(plane);
3232 id = skl_wm_plane_id(intel_plane);
c107acfe 3233
a6d3460e
MR		 3234 if (intel_plane->pipe != pipe)
3235 continue;
c107acfe 3236
936e71e3 3237 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3238 minimum[id] = 0;
3239 y_minimum[id] = 0;
3240 continue;
3241 }
3242 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3243 minimum[id] = 0;
3244 y_minimum[id] = 0;
3245 continue;
c107acfe 3246 }
a6d3460e 3247
cbcfd14b
KM		 3248 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3249 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3250 }
80958155 3251
c107acfe
MR		 3252 for (i = 0; i < PLANE_CURSOR; i++) {
3253 alloc_size -= minimum[i];
3254 alloc_size -= y_minimum[i];
80958155
DL		 3255 }
3256
b9cec075 3257 /*
80958155
DL		 3258 * 2. Distribute the remaining space in proportion to the amount of
3259 * data each plane needs to fetch from memory.
b9cec075
DL		 3260 *
3261 * FIXME: we may not allocate every single block here.
3262 */
024c9045 3263 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3264 if (total_data_rate == 0)
c107acfe 3265 return 0;
b9cec075 3266
34bb56af 3267 start = alloc->start;
024c9045 3268 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3269 unsigned int data_rate, y_data_rate;
3270 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3271 int id = skl_wm_plane_id(intel_plane);
b9cec075 3272
a1de91e5 3273 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3274
3275 /*
2cd601c6 3276 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3277 * promote the expression to 64 bits to avoid overflowing, the
3278 * result is < available as data_rate / total_data_rate < 1
3279 */
024c9045 3280 plane_blocks = minimum[id];
80958155
DL		 3281 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3282 total_data_rate);
b9cec075 3283
c107acfe
MR		 3284 /* Leave disabled planes at (0,0) */
3285 if (data_rate) {
3286 ddb->plane[pipe][id].start = start;
3287 ddb->plane[pipe][id].end = start + plane_blocks;
3288 }
b9cec075
DL		 3289
3290 start += plane_blocks;
2cd601c6
CK		 3291
3292 /*
3293 * allocation for y_plane part of planar format:
3294 */
a1de91e5
MR		 3295 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3296
3297 y_plane_blocks = y_minimum[id];
3298 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3299 total_data_rate);
2cd601c6 3300
c107acfe
MR		 3301 if (y_data_rate) {
3302 ddb->y_plane[pipe][id].start = start;
3303 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3304 }
a1de91e5
MR		 3305
3306 start += y_plane_blocks;
b9cec075
DL		 3307 }
3308
c107acfe 3309 return 0;
b9cec075
DL		 3310}
3311
5cec258b 3312static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3313{
3314 /* TODO: Take into account the scalers once we support them */
2d112de7 3315 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3316}
3317
3318/*
3319 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3320 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3321 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3322 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3323*/
ac484963 3324static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3325{
3326 uint32_t wm_intermediate_val, ret;
3327
3328 if (latency == 0)
3329 return UINT_MAX;
3330
ac484963 3331 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3332 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3333
3334 return ret;
3335}
3336
3337static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3338 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3339 uint64_t tiling, uint32_t latency)
2d41c0b5 3340{
d4c2aa60
TU		 3341 uint32_t ret;
3342 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3343 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3344
3345 if (latency == 0)
3346 return UINT_MAX;
3347
ac484963 3348 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3349
3350 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3351 tiling == I915_FORMAT_MOD_Yf_TILED) {
3352 plane_bytes_per_line *= 4;
3353 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3354 plane_blocks_per_line /= 4;
055c3ff6
MR		 3355 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3356 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
0fda6568
TU		 3357 } else {
3358 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3359 }
3360
2d41c0b5
PB		 3361 wm_intermediate_val = latency * pixel_rate;
3362 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3363 plane_blocks_per_line;
2d41c0b5
PB		 3364
3365 return ret;
3366}
3367
9c2f7a9d
KM		 3368static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3369 struct intel_plane_state *pstate)
3370{
3371 uint64_t adjusted_pixel_rate;
3372 uint64_t downscale_amount;
3373 uint64_t pixel_rate;
3374
3375 /* Shouldn't reach here on disabled planes... */
936e71e3 3376 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3377 return 0;
3378
3379 /*
3380 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3381 * with additional adjustments for plane-specific scaling.
3382 */
3383 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3384 downscale_amount = skl_plane_downscale_amount(pstate);
3385
3386 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3387 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3388
3389 return pixel_rate;
3390}
3391
55994c2c
MR		 3392static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3393 struct intel_crtc_state *cstate,
3394 struct intel_plane_state *intel_pstate,
3395 uint16_t ddb_allocation,
3396 int level,
3397 uint16_t *out_blocks, /* out */
3398 uint8_t *out_lines, /* out */
3399 bool *enabled /* out */)
2d41c0b5 3400{
33815fa5
MR		 3401 struct drm_plane_state *pstate = &intel_pstate->base;
3402 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3403 uint32_t latency = dev_priv->wm.skl_latency[level];
3404 uint32_t method1, method2;
3405 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3406 uint32_t res_blocks, res_lines;
3407 uint32_t selected_result;
ac484963 3408 uint8_t cpp;
a280f7dd 3409 uint32_t width = 0, height = 0;
9c2f7a9d 3410 uint32_t plane_pixel_rate;
2d41c0b5 3411
936e71e3 3412 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3413 *enabled = false;
3414 return 0;
3415 }
2d41c0b5 3416
936e71e3
VS		 3417 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3418 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3419
33815fa5 3420 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3421 swap(width, height);
3422
ac484963 3423 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3424 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3425
3426 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3427 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3428 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3429 width,
3430 cpp,
3431 fb->modifier[0],
d4c2aa60 3432 latency);
2d41c0b5 3433
a280f7dd 3434 plane_bytes_per_line = width * cpp;
d4c2aa60 3435 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3436
024c9045
MR		 3437 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3438 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3439 uint32_t min_scanlines = 4;
3440 uint32_t y_tile_minimum;
33815fa5 3441 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3442 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3443 drm_format_plane_cpp(fb->pixel_format, 1) :
3444 drm_format_plane_cpp(fb->pixel_format, 0);
3445
ac484963 3446 switch (cpp) {
1fc0a8f7
TU		 3447 case 1:
3448 min_scanlines = 16;
3449 break;
3450 case 2:
3451 min_scanlines = 8;
3452 break;
3453 case 8:
3454 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3455 }
1fc0a8f7
TU		 3456 }
3457 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3458 selected_result = max(method2, y_tile_minimum);
3459 } else {
3460 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3461 selected_result = min(method1, method2);
3462 else
3463 selected_result = method1;
3464 }
2d41c0b5 3465
d4c2aa60
TU		 3466 res_blocks = selected_result + 1;
3467 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3468
0fda6568 3469 if (level >= 1 && level <= 7) {
024c9045
MR		 3470 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3471 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3472 res_lines += 4;
3473 else
3474 res_blocks++;
3475 }
e6d66171 3476
55994c2c
MR		 3477 if (res_blocks >= ddb_allocation || res_lines > 31) {
3478 *enabled = false;
6b6bada7
MR		 3479
3480 /*
3481 * If there are no valid level 0 watermarks, then we can't
3482 * support this display configuration.
3483 */
3484 if (level) {
3485 return 0;
3486 } else {
3487 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3488 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3489 to_intel_crtc(cstate->base.crtc)->pipe,
3490 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3491 res_blocks, ddb_allocation, res_lines);
3492
3493 return -EINVAL;
3494 }
55994c2c 3495 }
e6d66171
DL		 3496
3497 *out_blocks = res_blocks;
3498 *out_lines = res_lines;
55994c2c 3499 *enabled = true;
2d41c0b5 3500
55994c2c 3501 return 0;
2d41c0b5
PB		 3502}
3503
f4a96752
MR		 3504static int
3505skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3506 struct skl_ddb_allocation *ddb,
3507 struct intel_crtc_state *cstate,
3508 int level,
3509 struct skl_wm_level *result)
2d41c0b5 3510{
f4a96752 3511 struct drm_atomic_state *state = cstate->base.state;
024c9045 3512 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3513 struct drm_plane *plane;
024c9045 3514 struct intel_plane *intel_plane;
33815fa5 3515 struct intel_plane_state *intel_pstate;
2d41c0b5 3516 uint16_t ddb_blocks;
024c9045 3517 enum pipe pipe = intel_crtc->pipe;
55994c2c 3518 int ret;
024c9045 3519
f4a96752
MR		 3520 /*
3521 * We'll only calculate watermarks for planes that are actually
3522 * enabled, so make sure all other planes are set as disabled.
3523 */
3524 memset(result, 0, sizeof(*result));
3525
91c8a326
CW		 3526 for_each_intel_plane_mask(&dev_priv->drm,
3527 intel_plane,
3528 cstate->base.plane_mask) {
024c9045 3529 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3530
f4a96752
MR		 3531 plane = &intel_plane->base;
3532 intel_pstate = NULL;
3533 if (state)
3534 intel_pstate =
3535 intel_atomic_get_existing_plane_state(state,
3536 intel_plane);
3537
3538 /*
3539 * Note: If we start supporting multiple pending atomic commits
3540 * against the same planes/CRTC's in the future, plane->state
3541 * will no longer be the correct pre-state to use for the
3542 * calculations here and we'll need to change where we get the
3543 * 'unchanged' plane data from.
3544 *
3545 * For now this is fine because we only allow one queued commit
3546 * against a CRTC. Even if the plane isn't modified by this
3547 * transaction and we don't have a plane lock, we still have
3548 * the CRTC's lock, so we know that no other transactions are
3549 * racing with us to update it.
3550 */
3551 if (!intel_pstate)
3552 intel_pstate = to_intel_plane_state(plane->state);
3553
3554 WARN_ON(!intel_pstate->base.fb);
3555
2d41c0b5
PB		 3556 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3557
55994c2c
MR		 3558 ret = skl_compute_plane_wm(dev_priv,
3559 cstate,
3560 intel_pstate,
3561 ddb_blocks,
3562 level,
3563 &result->plane_res_b[i],
3564 &result->plane_res_l[i],
3565 &result->plane_en[i]);
3566 if (ret)
3567 return ret;
2d41c0b5 3568 }
f4a96752
MR		 3569
3570 return 0;
2d41c0b5
PB		 3571}
3572
407b50f3 3573static uint32_t
024c9045 3574skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3575{
024c9045 3576 if (!cstate->base.active)
407b50f3
DL		 3577 return 0;
3578
024c9045 3579 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3580 return 0;
407b50f3 3581
024c9045
MR		 3582 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3583 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3584}
3585
024c9045 3586static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3587 struct skl_wm_level *trans_wm /* out */)
407b50f3 3588{
024c9045 3589 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3591 struct intel_plane *intel_plane;
9414f563 3592
024c9045 3593 if (!cstate->base.active)
407b50f3 3594 return;
9414f563
DL		 3595
3596 /* Until we know more, just disable transition WMs */
024c9045
MR		 3597 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3598 int i = skl_wm_plane_id(intel_plane);
3599
9414f563 3600 trans_wm->plane_en[i] = false;
024c9045 3601 }
407b50f3
DL		 3602}
3603
55994c2c
MR		 3604static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3605 struct skl_ddb_allocation *ddb,
3606 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3607{
024c9045 3608 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3609 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3610 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3611 int ret;
2d41c0b5
PB		 3612
3613 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3614 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3615 level, &pipe_wm->wm[level]);
3616 if (ret)
3617 return ret;
2d41c0b5 3618 }
024c9045 3619 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3620
024c9045 3621 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3622
3623 return 0;
2d41c0b5
PB		 3624}
3625
3626static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3627 struct skl_pipe_wm *p_wm,
3628 struct skl_wm_values *r,
3629 struct intel_crtc *intel_crtc)
3630{
3631 int level, max_level = ilk_wm_max_level(dev);
3632 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3633 uint32_t temp;
3634 int i;
2d41c0b5
PB		 3635
3636 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3637 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3638 temp = 0;
2d41c0b5
PB		 3639
3640 temp |= p_wm->wm[level].plane_res_l[i] <<
3641 PLANE_WM_LINES_SHIFT;
3642 temp |= p_wm->wm[level].plane_res_b[i];
3643 if (p_wm->wm[level].plane_en[i])
3644 temp |= PLANE_WM_EN;
3645
3646 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3647 }
3648
3649 temp = 0;
2d41c0b5 3650
4969d33e
MR		 3651 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3652 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3653
4969d33e 3654 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3655 temp |= PLANE_WM_EN;
3656
4969d33e 3657 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3658
3659 }
3660
9414f563
DL		 3661 /* transition WMs */
3662 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3663 temp = 0;
3664 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3665 temp |= p_wm->trans_wm.plane_res_b[i];
3666 if (p_wm->trans_wm.plane_en[i])
3667 temp |= PLANE_WM_EN;
3668
3669 r->plane_trans[pipe][i] = temp;
3670 }
3671
3672 temp = 0;
4969d33e
MR		 3673 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3674 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3675 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3676 temp |= PLANE_WM_EN;
3677
4969d33e 3678 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3679
2d41c0b5
PB		 3680 r->wm_linetime[pipe] = p_wm->linetime;
3681}
3682
f0f59a00
VS		 3683static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3684 i915_reg_t reg,
16160e3d
DL		 3685 const struct skl_ddb_entry *entry)
3686{
3687 if (entry->end)
3688 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3689 else
3690 I915_WRITE(reg, 0);
3691}
3692
2d41c0b5
PB		 3693static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3694 const struct skl_wm_values *new)
3695{
91c8a326 3696 struct drm_device *dev = &dev_priv->drm;
2d41c0b5
PB		 3697 struct intel_crtc *crtc;
3698
19c8054c 3699 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3700 int i, level, max_level = ilk_wm_max_level(dev);
3701 enum pipe pipe = crtc->pipe;
3702
2b4b9f35 3703 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
5d374d96 3704 continue;
734fa01f
MR		 3705 if (!crtc->active)
3706 continue;
8211bd5b 3707
5d374d96 3708 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3709
5d374d96
DL		 3710 for (level = 0; level <= max_level; level++) {
3711 for (i = 0; i < intel_num_planes(crtc); i++)
3712 I915_WRITE(PLANE_WM(pipe, i, level),
3713 new->plane[pipe][i][level]);
3714 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3715 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3716 }
5d374d96
DL		 3717 for (i = 0; i < intel_num_planes(crtc); i++)
3718 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3719 new->plane_trans[pipe][i]);
4969d33e
MR		 3720 I915_WRITE(CUR_WM_TRANS(pipe),
3721 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3722
2cd601c6 3723 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3724 skl_ddb_entry_write(dev_priv,
3725 PLANE_BUF_CFG(pipe, i),
3726 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3727 skl_ddb_entry_write(dev_priv,
3728 PLANE_NV12_BUF_CFG(pipe, i),
3729 &new->ddb.y_plane[pipe][i]);
3730 }
5d374d96
DL		 3731
3732 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3733 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3734 }
2d41c0b5
PB		 3735}
3736
0e8fb7ba
DL		 3737/*
3738 * When setting up a new DDB allocation arrangement, we need to correctly
3739 * sequence the times at which the new allocations for the pipes are taken into
3740 * account or we'll have pipes fetching from space previously allocated to
3741 * another pipe.
3742 *
3743 * Roughly the sequence looks like:
3744 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3745 * overlapping with a previous light-up pipe (another way to put it is:
3746 * pipes with their new allocation strickly included into their old ones).
3747 * 2. re-allocate the other pipes that get their allocation reduced
3748 * 3. allocate the pipes having their allocation increased
3749 *
3750 * Steps 1. and 2. are here to take care of the following case:
3751 * - Initially DDB looks like this:
3752 * | B | C |
3753 * - enable pipe A.
3754 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3755 * allocation
3756 * | A | B | C |
3757 *
3758 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3759 */
3760
d21b795c
DL		 3761static void
3762skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3763{
0e8fb7ba
DL		 3764 int plane;
3765
d21b795c
DL		 3766 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3767
dd740780 3768 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3769 I915_WRITE(PLANE_SURF(pipe, plane),
3770 I915_READ(PLANE_SURF(pipe, plane)));
3771 }
3772 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3773}
3774
3775static bool
3776skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3777 const struct skl_ddb_allocation *new,
3778 enum pipe pipe)
3779{
3780 uint16_t old_size, new_size;
3781
3782 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3783 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3784
3785 return old_size != new_size &&
3786 new->pipe[pipe].start >= old->pipe[pipe].start &&
3787 new->pipe[pipe].end <= old->pipe[pipe].end;
3788}
3789
3790static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3791 struct skl_wm_values *new_values)
3792{
91c8a326 3793 struct drm_device *dev = &dev_priv->drm;
0e8fb7ba 3794 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3795 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3796 struct intel_crtc *crtc;
3797 enum pipe pipe;
3798
3799 new_ddb = &new_values->ddb;
3800 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3801
3802 /*
3803 * First pass: flush the pipes with the new allocation contained into
3804 * the old space.
3805 *
3806 * We'll wait for the vblank on those pipes to ensure we can safely
3807 * re-allocate the freed space without this pipe fetching from it.
3808 */
3809 for_each_intel_crtc(dev, crtc) {
3810 if (!crtc->active)
3811 continue;
3812
3813 pipe = crtc->pipe;
3814
3815 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3816 continue;
3817
d21b795c 3818 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3819 intel_wait_for_vblank(dev, pipe);
3820
3821 reallocated[pipe] = true;
3822 }
3823
3824
3825 /*
3826 * Second pass: flush the pipes that are having their allocation
3827 * reduced, but overlapping with a previous allocation.
3828 *
3829 * Here as well we need to wait for the vblank to make sure the freed
3830 * space is not used anymore.
3831 */
3832 for_each_intel_crtc(dev, crtc) {
3833 if (!crtc->active)
3834 continue;
3835
3836 pipe = crtc->pipe;
3837
3838 if (reallocated[pipe])
3839 continue;
3840
3841 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3842 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3843 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3844 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3845 reallocated[pipe] = true;
0e8fb7ba 3846 }
0e8fb7ba
DL		 3847 }
3848
3849 /*
3850 * Third pass: flush the pipes that got more space allocated.
3851 *
3852 * We don't need to actively wait for the update here, next vblank
3853 * will just get more DDB space with the correct WM values.
3854 */
3855 for_each_intel_crtc(dev, crtc) {
3856 if (!crtc->active)
3857 continue;
3858
3859 pipe = crtc->pipe;
3860
3861 /*
3862 * At this point, only the pipes more space than before are
3863 * left to re-allocate.
3864 */
3865 if (reallocated[pipe])
3866 continue;
3867
d21b795c 3868 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3869 }
3870}
3871
55994c2c
MR		 3872static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3873 struct skl_ddb_allocation *ddb, /* out */
3874 struct skl_pipe_wm *pipe_wm, /* out */
3875 bool *changed /* out */)
2d41c0b5 3876{
f4a96752
MR		 3877 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3878 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3879 int ret;
2d41c0b5 3880
55994c2c
MR		 3881 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3882 if (ret)
3883 return ret;
2d41c0b5 3884
4e0963c7 3885 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3886 *changed = false;
3887 else
3888 *changed = true;
2d41c0b5 3889
55994c2c 3890 return 0;
2d41c0b5
PB		 3891}
3892
9b613022
MR		 3893static uint32_t
3894pipes_modified(struct drm_atomic_state *state)
3895{
3896 struct drm_crtc *crtc;
3897 struct drm_crtc_state *cstate;
3898 uint32_t i, ret = 0;
3899
3900 for_each_crtc_in_state(state, crtc, cstate, i)
3901 ret |= drm_crtc_mask(crtc);
3902
3903 return ret;
3904}
3905
98d39494
MR		 3906static int
3907skl_compute_ddb(struct drm_atomic_state *state)
3908{
3909 struct drm_device *dev = state->dev;
3910 struct drm_i915_private *dev_priv = to_i915(dev);
3911 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3912 struct intel_crtc *intel_crtc;
734fa01f 3913 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3914 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3915 int ret;
3916
3917 /*
3918 * If this is our first atomic update following hardware readout,
3919 * we can't trust the DDB that the BIOS programmed for us. Let's
3920 * pretend that all pipes switched active status so that we'll
3921 * ensure a full DDB recompute.
3922 */
1b54a880
MR		 3923 if (dev_priv->wm.distrust_bios_wm) {
3924 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3925 state->acquire_ctx);
3926 if (ret)
3927 return ret;
3928
98d39494
MR		 3929 intel_state->active_pipe_changes = ~0;
3930
1b54a880
MR		 3931 /*
3932 * We usually only initialize intel_state->active_crtcs if we
3933 * we're doing a modeset; make sure this field is always
3934 * initialized during the sanitization process that happens
3935 * on the first commit too.
3936 */
3937 if (!intel_state->modeset)
3938 intel_state->active_crtcs = dev_priv->active_crtcs;
3939 }
3940
98d39494
MR		 3941 /*
3942 * If the modeset changes which CRTC's are active, we need to
3943 * recompute the DDB allocation for *all* active pipes, even
3944 * those that weren't otherwise being modified in any way by this
3945 * atomic commit. Due to the shrinking of the per-pipe allocations
3946 * when new active CRTC's are added, it's possible for a pipe that
3947 * we were already using and aren't changing at all here to suddenly
3948 * become invalid if its DDB needs exceeds its new allocation.
3949 *
3950 * Note that if we wind up doing a full DDB recompute, we can't let
3951 * any other display updates race with this transaction, so we need
3952 * to grab the lock on *all* CRTC's.
3953 */
734fa01f 3954 if (intel_state->active_pipe_changes) {
98d39494 3955 realloc_pipes = ~0;
734fa01f
MR		 3956 intel_state->wm_results.dirty_pipes = ~0;
3957 }
98d39494
MR		 3958
3959 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3960 struct intel_crtc_state *cstate;
3961
3962 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3963 if (IS_ERR(cstate))
3964 return PTR_ERR(cstate);
3965
734fa01f 3966 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 3967 if (ret)
3968 return ret;
3969 }
3970
3971 return 0;
3972}
3973
3974static int
3975skl_compute_wm(struct drm_atomic_state *state)
3976{
3977 struct drm_crtc *crtc;
3978 struct drm_crtc_state *cstate;
734fa01f
MR		 3979 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3980 struct skl_wm_values *results = &intel_state->wm_results;
3981 struct skl_pipe_wm *pipe_wm;
98d39494 3982 bool changed = false;
734fa01f 3983 int ret, i;
98d39494
MR		 3984
3985 /*
3986 * If this transaction isn't actually touching any CRTC's, don't
3987 * bother with watermark calculation. Note that if we pass this
3988 * test, we're guaranteed to hold at least one CRTC state mutex,
3989 * which means we can safely use values like dev_priv->active_crtcs
3990 * since any racing commits that want to update them would need to
3991 * hold _all_ CRTC state mutexes.
3992 */
3993 for_each_crtc_in_state(state, crtc, cstate, i)
3994 changed = true;
3995 if (!changed)
3996 return 0;
3997
734fa01f
MR		 3998 /* Clear all dirty flags */
3999 results->dirty_pipes = 0;
4000
98d39494
MR		 4001 ret = skl_compute_ddb(state);
4002 if (ret)
4003 return ret;
4004
734fa01f
MR		 4005 /*
4006 * Calculate WM's for all pipes that are part of this transaction.
4007 * Note that the DDB allocation above may have added more CRTC's that
4008 * weren't otherwise being modified (and set bits in dirty_pipes) if
4009 * pipe allocations had to change.
4010 *
4011 * FIXME: Now that we're doing this in the atomic check phase, we
4012 * should allow skl_update_pipe_wm() to return failure in cases where
4013 * no suitable watermark values can be found.
4014 */
4015 for_each_crtc_in_state(state, crtc, cstate, i) {
4016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017 struct intel_crtc_state *intel_cstate =
4018 to_intel_crtc_state(cstate);
4019
4020 pipe_wm = &intel_cstate->wm.skl.optimal;
4021 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4022 &changed);
4023 if (ret)
4024 return ret;
4025
4026 if (changed)
4027 results->dirty_pipes |= drm_crtc_mask(crtc);
4028
4029 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4030 /* This pipe's WM's did not change */
4031 continue;
4032
4033 intel_cstate->update_wm_pre = true;
4034 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4035 }
4036
98d39494
MR		 4037 return 0;
4038}
4039
2d41c0b5
PB		 4040static void skl_update_wm(struct drm_crtc *crtc)
4041{
4042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4043 struct drm_device *dev = crtc->dev;
fac5e23e 4044 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4045 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 4046 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4047 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
adda50b8 4048
734fa01f 4049 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4050 return;
4051
734fa01f
MR		 4052 intel_crtc->wm.active.skl = *pipe_wm;
4053
4054 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4055
2d41c0b5 4056 skl_write_wm_values(dev_priv, results);
0e8fb7ba 4057 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 4058
4059 /* store the new configuration */
4060 dev_priv->wm.skl_hw = *results;
734fa01f
MR		 4061
4062 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4063}
4064
d890565c
VS		 4065static void ilk_compute_wm_config(struct drm_device *dev,
4066 struct intel_wm_config *config)
4067{
4068 struct intel_crtc *crtc;
4069
4070 /* Compute the currently _active_ config */
4071 for_each_intel_crtc(dev, crtc) {
4072 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4073
4074 if (!wm->pipe_enabled)
4075 continue;
4076
4077 config->sprites_enabled |= wm->sprites_enabled;
4078 config->sprites_scaled |= wm->sprites_scaled;
4079 config->num_pipes_active++;
4080 }
4081}
4082
ed4a6a7c 4083static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4084{
91c8a326 4085 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4086 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4087 struct ilk_wm_maximums max;
d890565c 4088 struct intel_wm_config config = {};
820c1980 4089 struct ilk_wm_values results = {};
77c122bc 4090 enum intel_ddb_partitioning partitioning;
261a27d1 4091
d890565c
VS		 4092 ilk_compute_wm_config(dev, &config);
4093
4094 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4095 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4096
4097 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4098 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4099 config.num_pipes_active == 1 && config.sprites_enabled) {
4100 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4101 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4102
820c1980 4103 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4104 } else {
198a1e9b 4105 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4106 }
4107
198a1e9b 4108 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4109 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4110
820c1980 4111 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4112
820c1980 4113 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4114}
4115
ed4a6a7c 4116static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4117{
ed4a6a7c
MR		 4118 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4119 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4120
ed4a6a7c 4121 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4122 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4123 ilk_program_watermarks(dev_priv);
4124 mutex_unlock(&dev_priv->wm.wm_mutex);
4125}
bf220452 4126
ed4a6a7c
MR		 4127static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4128{
4129 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4130 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4131
ed4a6a7c
MR		 4132 mutex_lock(&dev_priv->wm.wm_mutex);
4133 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4134 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4135 ilk_program_watermarks(dev_priv);
4136 }
4137 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4138}
4139
3078999f
PB		 4140static void skl_pipe_wm_active_state(uint32_t val,
4141 struct skl_pipe_wm *active,
4142 bool is_transwm,
4143 bool is_cursor,
4144 int i,
4145 int level)
4146{
4147 bool is_enabled = (val & PLANE_WM_EN) != 0;
4148
4149 if (!is_transwm) {
4150 if (!is_cursor) {
4151 active->wm[level].plane_en[i] = is_enabled;
4152 active->wm[level].plane_res_b[i] =
4153 val & PLANE_WM_BLOCKS_MASK;
4154 active->wm[level].plane_res_l[i] =
4155 (val >> PLANE_WM_LINES_SHIFT) &
4156 PLANE_WM_LINES_MASK;
4157 } else {
4969d33e
MR		 4158 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4159 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4160 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4161 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4162 (val >> PLANE_WM_LINES_SHIFT) &
4163 PLANE_WM_LINES_MASK;
4164 }
4165 } else {
4166 if (!is_cursor) {
4167 active->trans_wm.plane_en[i] = is_enabled;
4168 active->trans_wm.plane_res_b[i] =
4169 val & PLANE_WM_BLOCKS_MASK;
4170 active->trans_wm.plane_res_l[i] =
4171 (val >> PLANE_WM_LINES_SHIFT) &
4172 PLANE_WM_LINES_MASK;
4173 } else {
4969d33e
MR		 4174 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4175 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4176 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4177 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4178 (val >> PLANE_WM_LINES_SHIFT) &
4179 PLANE_WM_LINES_MASK;
4180 }
4181 }
4182}
4183
4184static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4185{
4186 struct drm_device *dev = crtc->dev;
fac5e23e 4187 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4188 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4190 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4191 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4192 enum pipe pipe = intel_crtc->pipe;
4193 int level, i, max_level;
4194 uint32_t temp;
4195
4196 max_level = ilk_wm_max_level(dev);
4197
4198 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4199
4200 for (level = 0; level <= max_level; level++) {
4201 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4202 hw->plane[pipe][i][level] =
4203 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4204 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4205 }
4206
4207 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4208 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4209 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4210
3ef00284 4211 if (!intel_crtc->active)
3078999f
PB		 4212 return;
4213
2b4b9f35 4214 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4215
4216 active->linetime = hw->wm_linetime[pipe];
4217
4218 for (level = 0; level <= max_level; level++) {
4219 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4220 temp = hw->plane[pipe][i][level];
4221 skl_pipe_wm_active_state(temp, active, false,
4222 false, i, level);
4223 }
4969d33e 4224 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4225 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4226 }
4227
4228 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4229 temp = hw->plane_trans[pipe][i];
4230 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4231 }
4232
4969d33e 4233 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4234 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4235
4236 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4237}
4238
4239void skl_wm_get_hw_state(struct drm_device *dev)
4240{
fac5e23e 4241 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4242 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4243 struct drm_crtc *crtc;
4244
a269c583 4245 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4247 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4248
279e99d7
MR		 4249 if (dev_priv->active_crtcs) {
4250 /* Fully recompute DDB on first atomic commit */
4251 dev_priv->wm.distrust_bios_wm = true;
4252 } else {
4253 /* Easy/common case; just sanitize DDB now if everything off */
4254 memset(ddb, 0, sizeof(*ddb));
4255 }
3078999f
PB		 4256}
4257
243e6a44
VS		 4258static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4259{
4260 struct drm_device *dev = crtc->dev;
fac5e23e 4261 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4262 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4264 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4265 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4266 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4267 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4268 [PIPE_A] = WM0_PIPEA_ILK,
4269 [PIPE_B] = WM0_PIPEB_ILK,
4270 [PIPE_C] = WM0_PIPEC_IVB,
4271 };
4272
4273 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4274 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4275 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4276
15606534
VS		 4277 memset(active, 0, sizeof(*active));
4278
3ef00284 4279 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4280
4281 if (active->pipe_enabled) {
243e6a44
VS		 4282 u32 tmp = hw->wm_pipe[pipe];
4283
4284 /*
4285 * For active pipes LP0 watermark is marked as
4286 * enabled, and LP1+ watermaks as disabled since
4287 * we can't really reverse compute them in case
4288 * multiple pipes are active.
4289 */
4290 active->wm[0].enable = true;
4291 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4292 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4293 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4294 active->linetime = hw->wm_linetime[pipe];
4295 } else {
4296 int level, max_level = ilk_wm_max_level(dev);
4297
4298 /*
4299 * For inactive pipes, all watermark levels
4300 * should be marked as enabled but zeroed,
4301 * which is what we'd compute them to.
4302 */
4303 for (level = 0; level <= max_level; level++)
4304 active->wm[level].enable = true;
4305 }
4e0963c7
MR		 4306
4307 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4308}
4309
6eb1a681
VS		 4310#define _FW_WM(value, plane) \
4311 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4312#define _FW_WM_VLV(value, plane) \
4313 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4314
4315static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4316 struct vlv_wm_values *wm)
4317{
4318 enum pipe pipe;
4319 uint32_t tmp;
4320
4321 for_each_pipe(dev_priv, pipe) {
4322 tmp = I915_READ(VLV_DDL(pipe));
4323
4324 wm->ddl[pipe].primary =
4325 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4326 wm->ddl[pipe].cursor =
4327 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4328 wm->ddl[pipe].sprite[0] =
4329 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4330 wm->ddl[pipe].sprite[1] =
4331 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4332 }
4333
4334 tmp = I915_READ(DSPFW1);
4335 wm->sr.plane = _FW_WM(tmp, SR);
4336 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4337 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4338 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4339
4340 tmp = I915_READ(DSPFW2);
4341 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4342 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4343 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4344
4345 tmp = I915_READ(DSPFW3);
4346 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4347
4348 if (IS_CHERRYVIEW(dev_priv)) {
4349 tmp = I915_READ(DSPFW7_CHV);
4350 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4351 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4352
4353 tmp = I915_READ(DSPFW8_CHV);
4354 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4355 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4356
4357 tmp = I915_READ(DSPFW9_CHV);
4358 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4359 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4360
4361 tmp = I915_READ(DSPHOWM);
4362 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4363 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4364 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4365 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4366 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4367 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4368 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4369 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4370 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4371 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4372 } else {
4373 tmp = I915_READ(DSPFW7);
4374 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4375 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4376
4377 tmp = I915_READ(DSPHOWM);
4378 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4379 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4380 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4381 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4382 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4383 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4384 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4385 }
4386}
4387
4388#undef _FW_WM
4389#undef _FW_WM_VLV
4390
4391void vlv_wm_get_hw_state(struct drm_device *dev)
4392{
4393 struct drm_i915_private *dev_priv = to_i915(dev);
4394 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4395 struct intel_plane *plane;
4396 enum pipe pipe;
4397 u32 val;
4398
4399 vlv_read_wm_values(dev_priv, wm);
4400
4401 for_each_intel_plane(dev, plane) {
4402 switch (plane->base.type) {
4403 int sprite;
4404 case DRM_PLANE_TYPE_CURSOR:
4405 plane->wm.fifo_size = 63;
4406 break;
4407 case DRM_PLANE_TYPE_PRIMARY:
4408 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4409 break;
4410 case DRM_PLANE_TYPE_OVERLAY:
4411 sprite = plane->plane;
4412 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4413 break;
4414 }
4415 }
4416
4417 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4418 wm->level = VLV_WM_LEVEL_PM2;
4419
4420 if (IS_CHERRYVIEW(dev_priv)) {
4421 mutex_lock(&dev_priv->rps.hw_lock);
4422
4423 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4424 if (val & DSP_MAXFIFO_PM5_ENABLE)
4425 wm->level = VLV_WM_LEVEL_PM5;
4426
58590c14
VS		 4427 /*
4428 * If DDR DVFS is disabled in the BIOS, Punit
4429 * will never ack the request. So if that happens
4430 * assume we don't have to enable/disable DDR DVFS
4431 * dynamically. To test that just set the REQ_ACK
4432 * bit to poke the Punit, but don't change the
4433 * HIGH/LOW bits so that we don't actually change
4434 * the current state.
4435 */
6eb1a681 4436 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4437 val |= FORCE_DDR_FREQ_REQ_ACK;
4438 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4439
4440 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4441 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4442 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4443 "assuming DDR DVFS is disabled\n");
4444 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4445 } else {
4446 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4447 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4448 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4449 }
6eb1a681
VS		 4450
4451 mutex_unlock(&dev_priv->rps.hw_lock);
4452 }
4453
4454 for_each_pipe(dev_priv, pipe)
4455 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4456 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4457 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4458
4459 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4460 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4461}
4462
243e6a44
VS		 4463void ilk_wm_get_hw_state(struct drm_device *dev)
4464{
fac5e23e 4465 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4466 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4467 struct drm_crtc *crtc;
4468
70e1e0ec 4469 for_each_crtc(dev, crtc)
243e6a44
VS		 4470 ilk_pipe_wm_get_hw_state(crtc);
4471
4472 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4473 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4474 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4475
4476 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4477 if (INTEL_INFO(dev)->gen >= 7) {
4478 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4479 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4480 }
243e6a44 4481
a42a5719 4482 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4483 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4484 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4485 else if (IS_IVYBRIDGE(dev))
4486 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4487 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4488
4489 hw->enable_fbc_wm =
4490 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4491}
4492
b445e3b0
ED		 4493/**
4494 * intel_update_watermarks - update FIFO watermark values based on current modes
4495 *
4496 * Calculate watermark values for the various WM regs based on current mode
4497 * and plane configuration.
4498 *
4499 * There are several cases to deal with here:
4500 * - normal (i.e. non-self-refresh)
4501 * - self-refresh (SR) mode
4502 * - lines are large relative to FIFO size (buffer can hold up to 2)
4503 * - lines are small relative to FIFO size (buffer can hold more than 2
4504 * lines), so need to account for TLB latency
4505 *
4506 * The normal calculation is:
4507 * watermark = dotclock * bytes per pixel * latency
4508 * where latency is platform & configuration dependent (we assume pessimal
4509 * values here).
4510 *
4511 * The SR calculation is:
4512 * watermark = (trunc(latency/line time)+1) * surface width *
4513 * bytes per pixel
4514 * where
4515 * line time = htotal / dotclock
4516 * surface width = hdisplay for normal plane and 64 for cursor
4517 * and latency is assumed to be high, as above.
4518 *
4519 * The final value programmed to the register should always be rounded up,
4520 * and include an extra 2 entries to account for clock crossings.
4521 *
4522 * We don't use the sprite, so we can ignore that. And on Crestline we have
4523 * to set the non-SR watermarks to 8.
4524 */
46ba614c 4525void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4526{
fac5e23e 4527 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4528
4529 if (dev_priv->display.update_wm)
46ba614c 4530 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4531}
4532
e2828914 4533/*
9270388e 4534 * Lock protecting IPS related data structures
9270388e
DV		 4535 */
4536DEFINE_SPINLOCK(mchdev_lock);
4537
4538/* Global for IPS driver to get at the current i915 device. Protected by
4539 * mchdev_lock. */
4540static struct drm_i915_private *i915_mch_dev;
4541
91d14251 4542bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4543{
2b4e57bd
ED		 4544 u16 rgvswctl;
4545
9270388e
DV		 4546 assert_spin_locked(&mchdev_lock);
4547
2b4e57bd
ED		 4548 rgvswctl = I915_READ16(MEMSWCTL);
4549 if (rgvswctl & MEMCTL_CMD_STS) {
4550 DRM_DEBUG("gpu busy, RCS change rejected\n");
4551 return false; /* still busy with another command */
4552 }
4553
4554 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4555 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4556 I915_WRITE16(MEMSWCTL, rgvswctl);
4557 POSTING_READ16(MEMSWCTL);
4558
4559 rgvswctl |= MEMCTL_CMD_STS;
4560 I915_WRITE16(MEMSWCTL, rgvswctl);
4561
4562 return true;
4563}
4564
91d14251 4565static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4566{
84f1b20f 4567 u32 rgvmodectl;
2b4e57bd
ED		 4568 u8 fmax, fmin, fstart, vstart;
4569
9270388e
DV		 4570 spin_lock_irq(&mchdev_lock);
4571
84f1b20f
TU		 4572 rgvmodectl = I915_READ(MEMMODECTL);
4573
2b4e57bd
ED		 4574 /* Enable temp reporting */
4575 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4576 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4577
4578 /* 100ms RC evaluation intervals */
4579 I915_WRITE(RCUPEI, 100000);
4580 I915_WRITE(RCDNEI, 100000);
4581
4582 /* Set max/min thresholds to 90ms and 80ms respectively */
4583 I915_WRITE(RCBMAXAVG, 90000);
4584 I915_WRITE(RCBMINAVG, 80000);
4585
4586 I915_WRITE(MEMIHYST, 1);
4587
4588 /* Set up min, max, and cur for interrupt handling */
4589 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4590 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4591 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4592 MEMMODE_FSTART_SHIFT;
4593
616847e7 4594 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4595 PXVFREQ_PX_SHIFT;
4596
20e4d407
DV		 4597 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4598 dev_priv->ips.fstart = fstart;
2b4e57bd 4599
20e4d407
DV		 4600 dev_priv->ips.max_delay = fstart;
4601 dev_priv->ips.min_delay = fmin;
4602 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4603
4604 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4605 fmax, fmin, fstart);
4606
4607 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4608
4609 /*
4610 * Interrupts will be enabled in ironlake_irq_postinstall
4611 */
4612
4613 I915_WRITE(VIDSTART, vstart);
4614 POSTING_READ(VIDSTART);
4615
4616 rgvmodectl |= MEMMODE_SWMODE_EN;
4617 I915_WRITE(MEMMODECTL, rgvmodectl);
4618
9270388e 4619 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4620 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4621 mdelay(1);
2b4e57bd 4622
91d14251 4623 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4624
7d81c3e0
VS		 4625 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4626 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4627 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4628 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4629 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4630
4631 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4632}
4633
91d14251 4634static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4635{
9270388e
DV		 4636 u16 rgvswctl;
4637
4638 spin_lock_irq(&mchdev_lock);
4639
4640 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4641
4642 /* Ack interrupts, disable EFC interrupt */
4643 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4644 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4645 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4646 I915_WRITE(DEIIR, DE_PCU_EVENT);
4647 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4648
4649 /* Go back to the starting frequency */
91d14251 4650 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4651 mdelay(1);
2b4e57bd
ED		 4652 rgvswctl |= MEMCTL_CMD_STS;
4653 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4654 mdelay(1);
2b4e57bd 4655
9270388e 4656 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4657}
4658
acbe9475
DV		 4659/* There's a funny hw issue where the hw returns all 0 when reading from
4660 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4661 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4662 * all limits and the gpu stuck at whatever frequency it is at atm).
4663 */
74ef1173 4664static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4665{
7b9e0ae6 4666 u32 limits;
2b4e57bd 4667
20b46e59
DV		 4668 /* Only set the down limit when we've reached the lowest level to avoid
4669 * getting more interrupts, otherwise leave this clear. This prevents a
4670 * race in the hw when coming out of rc6: There's a tiny window where
4671 * the hw runs at the minimal clock before selecting the desired
4672 * frequency, if the down threshold expires in that window we will not
4673 * receive a down interrupt. */
2d1fe073 4674 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4675 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4676 if (val <= dev_priv->rps.min_freq_softlimit)
4677 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4678 } else {
4679 limits = dev_priv->rps.max_freq_softlimit << 24;
4680 if (val <= dev_priv->rps.min_freq_softlimit)
4681 limits |= dev_priv->rps.min_freq_softlimit << 16;
4682 }
20b46e59
DV		 4683
4684 return limits;
4685}
4686
dd75fdc8
CW		 4687static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4688{
4689 int new_power;
8a586437
AG		 4690 u32 threshold_up = 0, threshold_down = 0; /* in % */
4691 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4692
4693 new_power = dev_priv->rps.power;
4694 switch (dev_priv->rps.power) {
4695 case LOW_POWER:
a72b5623
CW		 4696 if (val > dev_priv->rps.efficient_freq + 1 &&
4697 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4698 new_power = BETWEEN;
4699 break;
4700
4701 case BETWEEN:
a72b5623
CW		 4702 if (val <= dev_priv->rps.efficient_freq &&
4703 val < dev_priv->rps.cur_freq)
dd75fdc8 4704 new_power = LOW_POWER;
a72b5623
CW		 4705 else if (val >= dev_priv->rps.rp0_freq &&
4706 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4707 new_power = HIGH_POWER;
4708 break;
4709
4710 case HIGH_POWER:
a72b5623
CW		 4711 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4712 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4713 new_power = BETWEEN;
4714 break;
4715 }
4716 /* Max/min bins are special */
aed242ff 4717 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4718 new_power = LOW_POWER;
aed242ff 4719 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4720 new_power = HIGH_POWER;
4721 if (new_power == dev_priv->rps.power)
4722 return;
4723
4724 /* Note the units here are not exactly 1us, but 1280ns. */
4725 switch (new_power) {
4726 case LOW_POWER:
4727 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4728 ei_up = 16000;
4729 threshold_up = 95;
dd75fdc8
CW		 4730
4731 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4732 ei_down = 32000;
4733 threshold_down = 85;
dd75fdc8
CW		 4734 break;
4735
4736 case BETWEEN:
4737 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4738 ei_up = 13000;
4739 threshold_up = 90;
dd75fdc8
CW		 4740
4741 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4742 ei_down = 32000;
4743 threshold_down = 75;
dd75fdc8
CW		 4744 break;
4745
4746 case HIGH_POWER:
4747 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4748 ei_up = 10000;
4749 threshold_up = 85;
dd75fdc8
CW		 4750
4751 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4752 ei_down = 32000;
4753 threshold_down = 60;
dd75fdc8
CW		 4754 break;
4755 }
4756
8a586437 4757 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4758 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4759 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4760 GT_INTERVAL_FROM_US(dev_priv,
4761 ei_up * threshold_up / 100));
8a586437
AG		 4762
4763 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4764 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4765 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4766 GT_INTERVAL_FROM_US(dev_priv,
4767 ei_down * threshold_down / 100));
4768
4769 I915_WRITE(GEN6_RP_CONTROL,
4770 GEN6_RP_MEDIA_TURBO |
4771 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4772 GEN6_RP_MEDIA_IS_GFX |
4773 GEN6_RP_ENABLE |
4774 GEN6_RP_UP_BUSY_AVG |
4775 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4776
dd75fdc8 4777 dev_priv->rps.power = new_power;
8fb55197
CW		 4778 dev_priv->rps.up_threshold = threshold_up;
4779 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4780 dev_priv->rps.last_adj = 0;
4781}
4782
2876ce73
CW		 4783static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4784{
4785 u32 mask = 0;
4786
4787 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4788 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4789 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4790 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4791
7b3c29f6
CW		 4792 mask &= dev_priv->pm_rps_events;
4793
59d02a1f 4794 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4795}
4796
b8a5ff8d
JM		 4797/* gen6_set_rps is called to update the frequency request, but should also be
4798 * called when the range (min_delay and max_delay) is modified so that we can
4799 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4800static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4801{
23eafea6 4802 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4803 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4804 return;
4805
4fc688ce 4806 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4807 WARN_ON(val > dev_priv->rps.max_freq);
4808 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4809
eb64cad1
CW		 4810 /* min/max delay may still have been modified so be sure to
4811 * write the limits value.
4812 */
4813 if (val != dev_priv->rps.cur_freq) {
4814 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4815
dc97997a 4816 if (IS_GEN9(dev_priv))
5704195c
AG		 4817 I915_WRITE(GEN6_RPNSWREQ,
4818 GEN9_FREQUENCY(val));
dc97997a 4819 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4820 I915_WRITE(GEN6_RPNSWREQ,
4821 HSW_FREQUENCY(val));
4822 else
4823 I915_WRITE(GEN6_RPNSWREQ,
4824 GEN6_FREQUENCY(val) |
4825 GEN6_OFFSET(0) |
4826 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4827 }
7b9e0ae6 4828
7b9e0ae6
CW		 4829 /* Make sure we continue to get interrupts
4830 * until we hit the minimum or maximum frequencies.
4831 */
74ef1173 4832 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4833 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4834
d5570a72
BW		 4835 POSTING_READ(GEN6_RPNSWREQ);
4836
b39fb297 4837 dev_priv->rps.cur_freq = val;
0f94592e 4838 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4839}
4840
dc97997a 4841static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4842{
ffe02b40 4843 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4844 WARN_ON(val > dev_priv->rps.max_freq);
4845 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4846
dc97997a 4847 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4848 "Odd GPU freq value\n"))
4849 val &= ~1;
4850
cd25dd5b
D		 4851 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4852
8fb55197 4853 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4854 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4855 if (!IS_CHERRYVIEW(dev_priv))
4856 gen6_set_rps_thresholds(dev_priv, val);
4857 }
ffe02b40 4858
ffe02b40
VS		 4859 dev_priv->rps.cur_freq = val;
4860 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4861}
4862
a7f6e231 4863/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4864 *
4865 * * If Gfx is Idle, then
a7f6e231
D		 4866 * 1. Forcewake Media well.
4867 * 2. Request idle freq.
4868 * 3. Release Forcewake of Media well.
76c3552f
D		 4869*/
4870static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4871{
aed242ff 4872 u32 val = dev_priv->rps.idle_freq;
5549d25f 4873
aed242ff 4874 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4875 return;
4876
a7f6e231
D		 4877 /* Wake up the media well, as that takes a lot less
4878 * power than the Render well. */
4879 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4880 valleyview_set_rps(dev_priv, val);
a7f6e231 4881 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4882}
4883
43cf3bf0
CW		 4884void gen6_rps_busy(struct drm_i915_private *dev_priv)
4885{
4886 mutex_lock(&dev_priv->rps.hw_lock);
4887 if (dev_priv->rps.enabled) {
4888 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4889 gen6_rps_reset_ei(dev_priv);
4890 I915_WRITE(GEN6_PMINTRMSK,
4891 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 4892
c33d247d
CW		 4893 gen6_enable_rps_interrupts(dev_priv);
4894
2b83c4c4
MW		 4895 /* Ensure we start at the user's desired frequency */
4896 intel_set_rps(dev_priv,
4897 clamp(dev_priv->rps.cur_freq,
4898 dev_priv->rps.min_freq_softlimit,
4899 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 4900 }
4901 mutex_unlock(&dev_priv->rps.hw_lock);
4902}
4903
b29c19b6
CW		 4904void gen6_rps_idle(struct drm_i915_private *dev_priv)
4905{
c33d247d
CW		 4906 /* Flush our bottom-half so that it does not race with us
4907 * setting the idle frequency and so that it is bounded by
4908 * our rpm wakeref. And then disable the interrupts to stop any
4909 * futher RPS reclocking whilst we are asleep.
4910 */
4911 gen6_disable_rps_interrupts(dev_priv);
4912
b29c19b6 4913 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4914 if (dev_priv->rps.enabled) {
dc97997a 4915 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4916 vlv_set_rps_idle(dev_priv);
7526ed79 4917 else
dc97997a 4918 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4919 dev_priv->rps.last_adj = 0;
12c100bf
VS		 4920 I915_WRITE(GEN6_PMINTRMSK,
4921 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 4922 }
8d3afd7d 4923 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4924
8d3afd7d 4925 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4926 while (!list_empty(&dev_priv->rps.clients))
4927 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4928 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4929}
4930
1854d5ca 4931void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4932 struct intel_rps_client *rps,
4933 unsigned long submitted)
b29c19b6 4934{
8d3afd7d
CW		 4935 /* This is intentionally racy! We peek at the state here, then
4936 * validate inside the RPS worker.
4937 */
67d97da3 4938 if (!(dev_priv->gt.awake &&
8d3afd7d 4939 dev_priv->rps.enabled &&
29ecd78d 4940 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 4941 return;
43cf3bf0 4942
e61b9958
CW		 4943 /* Force a RPS boost (and don't count it against the client) if
4944 * the GPU is severely congested.
4945 */
d0bc54f2 4946 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4947 rps = NULL;
4948
8d3afd7d
CW		 4949 spin_lock(&dev_priv->rps.client_lock);
4950 if (rps == NULL || list_empty(&rps->link)) {
4951 spin_lock_irq(&dev_priv->irq_lock);
4952 if (dev_priv->rps.interrupts_enabled) {
4953 dev_priv->rps.client_boost = true;
c33d247d 4954 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 4955 }
4956 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4957
2e1b8730
CW		 4958 if (rps != NULL) {
4959 list_add(&rps->link, &dev_priv->rps.clients);
4960 rps->boosts++;
1854d5ca
CW		 4961 } else
4962 dev_priv->rps.boosts++;
c0951f0c 4963 }
8d3afd7d 4964 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4965}
4966
dc97997a 4967void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4968{
dc97997a
CW		 4969 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4970 valleyview_set_rps(dev_priv, val);
ffe02b40 4971 else
dc97997a 4972 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4973}
4974
dc97997a 4975static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4976{
20e49366 4977 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4978 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4979}
4980
dc97997a 4981static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4982{
2030d684
AG		 4983 I915_WRITE(GEN6_RP_CONTROL, 0);
4984}
4985
dc97997a 4986static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4987{
d20d4f0c 4988 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4989 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4990 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4991}
4992
dc97997a 4993static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4994{
38807746
D		 4995 I915_WRITE(GEN6_RC_CONTROL, 0);
4996}
4997
dc97997a 4998static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4999{
98a2e5f9
D		 5000 /* we're doing forcewake before Disabling RC6,
5001 * This what the BIOS expects when going into suspend */
59bad947 5002 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5003
44fc7d5c 5004 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5005
59bad947 5006 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5007}
5008
dc97997a 5009static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5010{
dc97997a 5011 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5012 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5013 mode = GEN6_RC_CTL_RC6_ENABLE;
5014 else
5015 mode = 0;
5016 }
dc97997a 5017 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5018 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5019 "RC6 %s RC6p %s RC6pp %s\n",
5020 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5021 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5022 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5023
5024 else
b99d49cc
ID		 5025 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5026 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5027}
5028
dc97997a 5029static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5030{
72e96d64 5031 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5032 bool enable_rc6 = true;
5033 unsigned long rc6_ctx_base;
fc619841
ID		 5034 u32 rc_ctl;
5035 int rc_sw_target;
5036
5037 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5038 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5039 RC_SW_TARGET_STATE_SHIFT;
5040 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5041 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5042 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5043 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5044 rc_sw_target);
274008e8
SAK		 5045
5046 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5047 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5048 enable_rc6 = false;
5049 }
5050
5051 /*
5052 * The exact context size is not known for BXT, so assume a page size
5053 * for this check.
5054 */
5055 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5056 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5057 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5058 ggtt->stolen_reserved_size))) {
b99d49cc 5059 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5060 enable_rc6 = false;
5061 }
5062
5063 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5064 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5065 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5066 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5067 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5068 enable_rc6 = false;
5069 }
5070
fc619841
ID		 5071 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5072 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5073 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5074 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5075 enable_rc6 = false;
5076 }
5077
5078 if (!I915_READ(GEN6_GFXPAUSE)) {
5079 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5080 enable_rc6 = false;
5081 }
5082
5083 if (!I915_READ(GEN8_MISC_CTRL0)) {
5084 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5085 enable_rc6 = false;
5086 }
5087
5088 return enable_rc6;
5089}
5090
dc97997a 5091int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5092{
e7d66d89 5093 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5094 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5095 return 0;
5096
274008e8
SAK		 5097 if (!enable_rc6)
5098 return 0;
5099
dc97997a 5100 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5101 DRM_INFO("RC6 disabled by BIOS\n");
5102 return 0;
5103 }
5104
456470eb 5105 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5106 if (enable_rc6 >= 0) {
5107 int mask;
5108
dc97997a 5109 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5110 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5111 INTEL_RC6pp_ENABLE;
5112 else
5113 mask = INTEL_RC6_ENABLE;
5114
5115 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5116 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5117 "(requested %d, valid %d)\n",
5118 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5119
5120 return enable_rc6 & mask;
5121 }
2b4e57bd 5122
dc97997a 5123 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5124 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5125
5126 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5127}
5128
dc97997a 5129static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5130{
5131 /* All of these values are in units of 50MHz */
773ea9a8 5132
93ee2920 5133 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5134 if (IS_BROXTON(dev_priv)) {
773ea9a8 5135 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5136 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5137 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5138 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5139 } else {
773ea9a8 5140 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5141 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5142 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5143 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5144 }
3280e8b0 5145 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5146 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5147
93ee2920 5148 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5149 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5150 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5151 u32 ddcc_status = 0;
5152
5153 if (sandybridge_pcode_read(dev_priv,
5154 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5155 &ddcc_status) == 0)
93ee2920 5156 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5157 clamp_t(u8,
5158 ((ddcc_status >> 8) & 0xff),
5159 dev_priv->rps.min_freq,
5160 dev_priv->rps.max_freq);
93ee2920
TR		 5161 }
5162
dc97997a 5163 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5164 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5165 * the natural hardware unit for SKL
5166 */
c5e0688c
AG		 5167 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5168 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5169 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5170 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5171 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5172 }
3280e8b0
BW		 5173}
5174
3a45b05c
CW		 5175static void reset_rps(struct drm_i915_private *dev_priv,
5176 void (*set)(struct drm_i915_private *, u8))
5177{
5178 u8 freq = dev_priv->rps.cur_freq;
5179
5180 /* force a reset */
5181 dev_priv->rps.power = -1;
5182 dev_priv->rps.cur_freq = -1;
5183
5184 set(dev_priv, freq);
5185}
5186
b6fef0ef 5187/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5188static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5189{
b6fef0ef
JB		 5190 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5191
23eafea6 5192 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5193 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5194 /*
5195 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5196 * clear out the Control register just to avoid inconsitency
5197 * with debugfs interface, which will show Turbo as enabled
5198 * only and that is not expected by the User after adding the
5199 * WaGsvDisableTurbo. Apart from this there is no problem even
5200 * if the Turbo is left enabled in the Control register, as the
5201 * Up/Down interrupts would remain masked.
5202 */
dc97997a 5203 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5204 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5205 return;
5206 }
5207
0beb059a
AG		 5208 /* Program defaults and thresholds for RPS*/
5209 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5210 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5211
5212 /* 1 second timeout*/
5213 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5214 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5215
b6fef0ef 5216 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5217
0beb059a
AG		 5218 /* Leaning on the below call to gen6_set_rps to program/setup the
5219 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5220 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5221 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5222
5223 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5224}
5225
dc97997a 5226static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5227{
e2f80391 5228 struct intel_engine_cs *engine;
20e49366 5229 uint32_t rc6_mask = 0;
20e49366
ZW		 5230
5231 /* 1a: Software RC state - RC0 */
5232 I915_WRITE(GEN6_RC_STATE, 0);
5233
5234 /* 1b: Get forcewake during program sequence. Although the driver
5235 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5236 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5237
5238 /* 2a: Disable RC states. */
5239 I915_WRITE(GEN6_RC_CONTROL, 0);
5240
5241 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5242
5243 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5244 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5245 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5246 else
5247 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5248 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5249 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5250 for_each_engine(engine, dev_priv)
e2f80391 5251 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5252
1a3d1898 5253 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5254 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5255
20e49366 5256 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5257
38c23527
ZW		 5258 /* 2c: Program Coarse Power Gating Policies. */
5259 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5260 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5261
20e49366 5262 /* 3a: Enable RC6 */
dc97997a 5263 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5264 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5265 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5266 /* WaRsUseTimeoutMode */
dc97997a
CW		 5267 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5268 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5269 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5270 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5271 GEN7_RC_CTL_TO_MODE |
5272 rc6_mask);
3e7732a0
SAK		 5273 } else {
5274 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5275 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5276 GEN6_RC_CTL_EI_MODE(1) |
5277 rc6_mask);
3e7732a0 5278 }
20e49366 5279
cb07bae0
SK		 5280 /*
5281 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5282 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5283 */
dc97997a 5284 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5285 I915_WRITE(GEN9_PG_ENABLE, 0);
5286 else
5287 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5288 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5289
59bad947 5290 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5291}
5292
dc97997a 5293static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5294{
e2f80391 5295 struct intel_engine_cs *engine;
93ee2920 5296 uint32_t rc6_mask = 0;
6edee7f3
BW		 5297
5298 /* 1a: Software RC state - RC0 */
5299 I915_WRITE(GEN6_RC_STATE, 0);
5300
5301 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5302 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5303 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5304
5305 /* 2a: Disable RC states. */
5306 I915_WRITE(GEN6_RC_CONTROL, 0);
5307
6edee7f3
BW		 5308 /* 2b: Program RC6 thresholds.*/
5309 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5310 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5311 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5312 for_each_engine(engine, dev_priv)
e2f80391 5313 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5314 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5315 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5316 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5317 else
5318 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5319
5320 /* 3: Enable RC6 */
dc97997a 5321 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5322 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5323 intel_print_rc6_info(dev_priv, rc6_mask);
5324 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5325 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5326 GEN7_RC_CTL_TO_MODE |
5327 rc6_mask);
5328 else
5329 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5330 GEN6_RC_CTL_EI_MODE(1) |
5331 rc6_mask);
6edee7f3
BW		 5332
5333 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5334 I915_WRITE(GEN6_RPNSWREQ,
5335 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5336 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5337 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5338 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5339 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5340
5341 /* Docs recommend 900MHz, and 300 MHz respectively */
5342 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5343 dev_priv->rps.max_freq_softlimit << 24 |
5344 dev_priv->rps.min_freq_softlimit << 16);
5345
5346 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5347 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5348 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5349 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5350
5351 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5352
5353 /* 5: Enable RPS */
7526ed79
DV		 5354 I915_WRITE(GEN6_RP_CONTROL,
5355 GEN6_RP_MEDIA_TURBO |
5356 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5357 GEN6_RP_MEDIA_IS_GFX |
5358 GEN6_RP_ENABLE |
5359 GEN6_RP_UP_BUSY_AVG |
5360 GEN6_RP_DOWN_IDLE_AVG);
5361
5362 /* 6: Ring frequency + overclocking (our driver does this later */
5363
3a45b05c 5364 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5365
59bad947 5366 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5367}
5368
dc97997a 5369static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5370{
e2f80391 5371 struct intel_engine_cs *engine;
99ac9612 5372 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5373 u32 gtfifodbg;
2b4e57bd 5374 int rc6_mode;
b4ac5afc 5375 int ret;
2b4e57bd 5376
4fc688ce 5377 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5378
2b4e57bd
ED		 5379 /* Here begins a magic sequence of register writes to enable
5380 * auto-downclocking.
5381 *
5382 * Perhaps there might be some value in exposing these to
5383 * userspace...
5384 */
5385 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5386
5387 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5388 gtfifodbg = I915_READ(GTFIFODBG);
5389 if (gtfifodbg) {
2b4e57bd
ED		 5390 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5391 I915_WRITE(GTFIFODBG, gtfifodbg);
5392 }
5393
59bad947 5394 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5395
5396 /* disable the counters and set deterministic thresholds */
5397 I915_WRITE(GEN6_RC_CONTROL, 0);
5398
5399 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5400 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5401 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5402 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5403 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5404
b4ac5afc 5405 for_each_engine(engine, dev_priv)
e2f80391 5406 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5407
5408 I915_WRITE(GEN6_RC_SLEEP, 0);
5409 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5410 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5411 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5412 else
5413 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5414 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5415 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5416
5a7dc92a 5417 /* Check if we are enabling RC6 */
dc97997a 5418 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5419 if (rc6_mode & INTEL_RC6_ENABLE)
5420 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5421
5a7dc92a 5422 /* We don't use those on Haswell */
dc97997a 5423 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5424 if (rc6_mode & INTEL_RC6p_ENABLE)
5425 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5426
5a7dc92a
ED		 5427 if (rc6_mode & INTEL_RC6pp_ENABLE)
5428 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5429 }
2b4e57bd 5430
dc97997a 5431 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5432
5433 I915_WRITE(GEN6_RC_CONTROL,
5434 rc6_mask |
5435 GEN6_RC_CTL_EI_MODE(1) |
5436 GEN6_RC_CTL_HW_ENABLE);
5437
dd75fdc8
CW		 5438 /* Power down if completely idle for over 50ms */
5439 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5440 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5441
42c0526c 5442 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5443 if (ret)
42c0526c 5444 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5445
3a45b05c 5446 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5447
31643d54
BW		 5448 rc6vids = 0;
5449 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5450 if (IS_GEN6(dev_priv) && ret) {
31643d54 5451 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5452 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5453 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5454 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5455 rc6vids &= 0xffff00;
5456 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5457 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5458 if (ret)
5459 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5460 }
5461
59bad947 5462 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5463}
5464
fb7404e8 5465static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5466{
5467 int min_freq = 15;
3ebecd07
CW		 5468 unsigned int gpu_freq;
5469 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5470 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5471 int scaling_factor = 180;
eda79642 5472 struct cpufreq_policy *policy;
2b4e57bd 5473
4fc688ce 5474 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5475
eda79642
BW		 5476 policy = cpufreq_cpu_get(0);
5477 if (policy) {
5478 max_ia_freq = policy->cpuinfo.max_freq;
5479 cpufreq_cpu_put(policy);
5480 } else {
5481 /*
5482 * Default to measured freq if none found, PCU will ensure we
5483 * don't go over
5484 */
2b4e57bd 5485 max_ia_freq = tsc_khz;
eda79642 5486 }
2b4e57bd
ED		 5487
5488 /* Convert from kHz to MHz */
5489 max_ia_freq /= 1000;
5490
153b4b95 5491 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5492 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5493 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5494
dc97997a 5495 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5496 /* Convert GT frequency to 50 HZ units */
5497 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5498 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5499 } else {
5500 min_gpu_freq = dev_priv->rps.min_freq;
5501 max_gpu_freq = dev_priv->rps.max_freq;
5502 }
5503
2b4e57bd
ED		 5504 /*
5505 * For each potential GPU frequency, load a ring frequency we'd like
5506 * to use for memory access. We do this by specifying the IA frequency
5507 * the PCU should use as a reference to determine the ring frequency.
5508 */
4c8c7743
AG		 5509 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5510 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5511 unsigned int ia_freq = 0, ring_freq = 0;
5512
dc97997a 5513 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5514 /*
5515 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5516 * No floor required for ring frequency on SKL.
5517 */
5518 ring_freq = gpu_freq;
dc97997a 5519 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5520 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5521 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5522 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5523 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5524 ring_freq = max(min_ring_freq, ring_freq);
5525 /* leave ia_freq as the default, chosen by cpufreq */
5526 } else {
5527 /* On older processors, there is no separate ring
5528 * clock domain, so in order to boost the bandwidth
5529 * of the ring, we need to upclock the CPU (ia_freq).
5530 *
5531 * For GPU frequencies less than 750MHz,
5532 * just use the lowest ring freq.
5533 */
5534 if (gpu_freq < min_freq)
5535 ia_freq = 800;
5536 else
5537 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5538 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5539 }
2b4e57bd 5540
42c0526c
BW		 5541 sandybridge_pcode_write(dev_priv,
5542 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5543 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5544 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5545 gpu_freq);
2b4e57bd 5546 }
2b4e57bd
ED		 5547}
5548
03af2045 5549static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5550{
5551 u32 val, rp0;
5552
5b5929cb 5553 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5554
dc97997a 5555 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5556 case 8:
5557 /* (2 * 4) config */
5558 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5559 break;
5560 case 12:
5561 /* (2 * 6) config */
5562 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5563 break;
5564 case 16:
5565 /* (2 * 8) config */
5566 default:
5567 /* Setting (2 * 8) Min RP0 for any other combination */
5568 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5569 break;
095acd5f 5570 }
5b5929cb
JN		 5571
5572 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5573
2b6b3a09
D		 5574 return rp0;
5575}
5576
5577static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5578{
5579 u32 val, rpe;
5580
5581 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5582 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5583
5584 return rpe;
5585}
5586
7707df4a
D		 5587static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5588{
5589 u32 val, rp1;
5590
5b5929cb
JN		 5591 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5592 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5593
7707df4a
D		 5594 return rp1;
5595}
5596
f8f2b001
D		 5597static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5598{
5599 u32 val, rp1;
5600
5601 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5602
5603 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5604
5605 return rp1;
5606}
5607
03af2045 5608static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5609{
5610 u32 val, rp0;
5611
64936258 5612 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5613
5614 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5615 /* Clamp to max */
5616 rp0 = min_t(u32, rp0, 0xea);
5617
5618 return rp0;
5619}
5620
5621static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5622{
5623 u32 val, rpe;
5624
64936258 5625 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5626 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5627 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5628 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5629
5630 return rpe;
5631}
5632
03af2045 5633static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5634{
36146035
ID		 5635 u32 val;
5636
5637 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5638 /*
5639 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5640 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5641 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5642 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5643 * to make sure it matches what Punit accepts.
5644 */
5645 return max_t(u32, val, 0xc0);
0a073b84
JB		 5646}
5647
ae48434c
ID		 5648/* Check that the pctx buffer wasn't move under us. */
5649static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5650{
5651 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5652
5653 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5654 dev_priv->vlv_pctx->stolen->start);
5655}
5656
38807746
D		 5657
5658/* Check that the pcbr address is not empty. */
5659static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5660{
5661 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5662
5663 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5664}
5665
dc97997a 5666static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5667{
62106b4f 5668 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5669 unsigned long pctx_paddr, paddr;
38807746
D		 5670 u32 pcbr;
5671 int pctx_size = 32*1024;
5672
38807746
D		 5673 pcbr = I915_READ(VLV_PCBR);
5674 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5675 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5676 paddr = (dev_priv->mm.stolen_base +
62106b4f 5677 (ggtt->stolen_size - pctx_size));
38807746
D		 5678
5679 pctx_paddr = (paddr & (~4095));
5680 I915_WRITE(VLV_PCBR, pctx_paddr);
5681 }
ce611ef8
VS		 5682
5683 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5684}
5685
dc97997a 5686static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5687{
c9cddffc
JB		 5688 struct drm_i915_gem_object *pctx;
5689 unsigned long pctx_paddr;
5690 u32 pcbr;
5691 int pctx_size = 24*1024;
5692
5693 pcbr = I915_READ(VLV_PCBR);
5694 if (pcbr) {
5695 /* BIOS set it up already, grab the pre-alloc'd space */
5696 int pcbr_offset;
5697
5698 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5699 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5700 pcbr_offset,
190d6cd5 5701 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5702 pctx_size);
5703 goto out;
5704 }
5705
ce611ef8
VS		 5706 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5707
c9cddffc
JB		 5708 /*
5709 * From the Gunit register HAS:
5710 * The Gfx driver is expected to program this register and ensure
5711 * proper allocation within Gfx stolen memory. For example, this
5712 * register should be programmed such than the PCBR range does not
5713 * overlap with other ranges, such as the frame buffer, protected
5714 * memory, or any other relevant ranges.
5715 */
91c8a326 5716 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5717 if (!pctx) {
5718 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5719 goto out;
c9cddffc
JB		 5720 }
5721
5722 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5723 I915_WRITE(VLV_PCBR, pctx_paddr);
5724
5725out:
ce611ef8 5726 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5727 dev_priv->vlv_pctx = pctx;
5728}
5729
dc97997a 5730static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5731{
ae48434c
ID		 5732 if (WARN_ON(!dev_priv->vlv_pctx))
5733 return;
5734
34911fd3 5735 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5736 dev_priv->vlv_pctx = NULL;
5737}
5738
c30fec65
VS		 5739static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5740{
5741 dev_priv->rps.gpll_ref_freq =
5742 vlv_get_cck_clock(dev_priv, "GPLL ref",
5743 CCK_GPLL_CLOCK_CONTROL,
5744 dev_priv->czclk_freq);
5745
5746 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5747 dev_priv->rps.gpll_ref_freq);
5748}
5749
dc97997a 5750static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5751{
2bb25c17 5752 u32 val;
4e80519e 5753
dc97997a 5754 valleyview_setup_pctx(dev_priv);
4e80519e 5755
c30fec65
VS		 5756 vlv_init_gpll_ref_freq(dev_priv);
5757
2bb25c17
VS		 5758 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5759 switch ((val >> 6) & 3) {
5760 case 0:
5761 case 1:
5762 dev_priv->mem_freq = 800;
5763 break;
5764 case 2:
5765 dev_priv->mem_freq = 1066;
5766 break;
5767 case 3:
5768 dev_priv->mem_freq = 1333;
5769 break;
5770 }
80b83b62 5771 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5772
4e80519e
ID		 5773 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5774 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5775 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5776 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5777 dev_priv->rps.max_freq);
5778
5779 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5780 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5781 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5782 dev_priv->rps.efficient_freq);
5783
f8f2b001
D		 5784 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5785 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5786 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5787 dev_priv->rps.rp1_freq);
5788
4e80519e
ID		 5789 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5790 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5791 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5792 dev_priv->rps.min_freq);
4e80519e
ID		 5793}
5794
dc97997a 5795static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5796{
2bb25c17 5797 u32 val;
2b6b3a09 5798
dc97997a 5799 cherryview_setup_pctx(dev_priv);
2b6b3a09 5800
c30fec65
VS		 5801 vlv_init_gpll_ref_freq(dev_priv);
5802
a580516d 5803 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5804 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5805 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5806
2bb25c17 5807 switch ((val >> 2) & 0x7) {
2bb25c17 5808 case 3:
2bb25c17
VS		 5809 dev_priv->mem_freq = 2000;
5810 break;
bfa7df01 5811 default:
2bb25c17
VS		 5812 dev_priv->mem_freq = 1600;
5813 break;
5814 }
80b83b62 5815 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5816
2b6b3a09
D		 5817 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5818 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5819 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5820 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5821 dev_priv->rps.max_freq);
5822
5823 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5824 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5825 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5826 dev_priv->rps.efficient_freq);
5827
7707df4a
D		 5828 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5829 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5830 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5831 dev_priv->rps.rp1_freq);
5832
5b7c91b7
D		 5833 /* PUnit validated range is only [RPe, RP0] */
5834 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5835 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5836 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5837 dev_priv->rps.min_freq);
5838
1c14762d
VS		 5839 WARN_ONCE((dev_priv->rps.max_freq |
5840 dev_priv->rps.efficient_freq |
5841 dev_priv->rps.rp1_freq |
5842 dev_priv->rps.min_freq) & 1,
5843 "Odd GPU freq values\n");
38807746
D		 5844}
5845
dc97997a 5846static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5847{
dc97997a 5848 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5849}
5850
dc97997a 5851static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5852{
e2f80391 5853 struct intel_engine_cs *engine;
2b6b3a09 5854 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5855
5856 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5857
297b32ec
VS		 5858 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5859 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5860 if (gtfifodbg) {
5861 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5862 gtfifodbg);
5863 I915_WRITE(GTFIFODBG, gtfifodbg);
5864 }
5865
5866 cherryview_check_pctx(dev_priv);
5867
5868 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5869 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5870 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5871
160614a2
VS		 5872 /* Disable RC states. */
5873 I915_WRITE(GEN6_RC_CONTROL, 0);
5874
38807746
D		 5875 /* 2a: Program RC6 thresholds.*/
5876 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5877 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5878 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5879
b4ac5afc 5880 for_each_engine(engine, dev_priv)
e2f80391 5881 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5882 I915_WRITE(GEN6_RC_SLEEP, 0);
5883
f4f71c7d
D		 5884 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5885 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5886
5887 /* allows RC6 residency counter to work */
5888 I915_WRITE(VLV_COUNTER_CONTROL,
5889 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5890 VLV_MEDIA_RC6_COUNT_EN |
5891 VLV_RENDER_RC6_COUNT_EN));
5892
5893 /* For now we assume BIOS is allocating and populating the PCBR */
5894 pcbr = I915_READ(VLV_PCBR);
5895
38807746 5896 /* 3: Enable RC6 */
dc97997a
CW		 5897 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5898 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5899 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5900
5901 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5902
2b6b3a09 5903 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5904 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5905 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5906 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5907 I915_WRITE(GEN6_RP_UP_EI, 66000);
5908 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5909
5910 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5911
5912 /* 5: Enable RPS */
5913 I915_WRITE(GEN6_RP_CONTROL,
5914 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5915 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5916 GEN6_RP_ENABLE |
5917 GEN6_RP_UP_BUSY_AVG |
5918 GEN6_RP_DOWN_IDLE_AVG);
5919
3ef62342
D		 5920 /* Setting Fixed Bias */
5921 val = VLV_OVERRIDE_EN |
5922 VLV_SOC_TDP_EN |
5923 CHV_BIAS_CPU_50_SOC_50;
5924 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5925
2b6b3a09
D		 5926 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5927
8d40c3ae
VS		 5928 /* RPS code assumes GPLL is used */
5929 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5930
742f491d 5931 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5932 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5933
3a45b05c 5934 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 5935
59bad947 5936 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5937}
5938
dc97997a 5939static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5940{
e2f80391 5941 struct intel_engine_cs *engine;
2a5913a8 5942 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5943
5944 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5945
ae48434c
ID		 5946 valleyview_check_pctx(dev_priv);
5947
297b32ec
VS		 5948 gtfifodbg = I915_READ(GTFIFODBG);
5949 if (gtfifodbg) {
f7d85c1e
JB		 5950 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5951 gtfifodbg);
0a073b84
JB		 5952 I915_WRITE(GTFIFODBG, gtfifodbg);
5953 }
5954
c8d9a590 5955 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5956 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5957
160614a2
VS		 5958 /* Disable RC states. */
5959 I915_WRITE(GEN6_RC_CONTROL, 0);
5960
cad725fe 5961 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5962 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5963 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5964 I915_WRITE(GEN6_RP_UP_EI, 66000);
5965 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5966
5967 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5968
5969 I915_WRITE(GEN6_RP_CONTROL,
5970 GEN6_RP_MEDIA_TURBO |
5971 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5972 GEN6_RP_MEDIA_IS_GFX |
5973 GEN6_RP_ENABLE |
5974 GEN6_RP_UP_BUSY_AVG |
5975 GEN6_RP_DOWN_IDLE_CONT);
5976
5977 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5978 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5979 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5980
b4ac5afc 5981 for_each_engine(engine, dev_priv)
e2f80391 5982 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5983
2f0aa304 5984 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5985
5986 /* allows RC6 residency counter to work */
49798eb2 5987 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5988 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5989 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5990 VLV_MEDIA_RC6_COUNT_EN |
5991 VLV_RENDER_RC6_COUNT_EN));
31685c25 5992
dc97997a 5993 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5994 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5995
dc97997a 5996 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5997
a2b23fe0 5998 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5999
3ef62342
D		 6000 /* Setting Fixed Bias */
6001 val = VLV_OVERRIDE_EN |
6002 VLV_SOC_TDP_EN |
6003 VLV_BIAS_CPU_125_SOC_875;
6004 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6005
64936258 6006 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6007
8d40c3ae
VS		 6008 /* RPS code assumes GPLL is used */
6009 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6010
742f491d 6011 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6012 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6013
3a45b05c 6014 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6015
59bad947 6016 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6017}
6018
dde18883
ED		 6019static unsigned long intel_pxfreq(u32 vidfreq)
6020{
6021 unsigned long freq;
6022 int div = (vidfreq & 0x3f0000) >> 16;
6023 int post = (vidfreq & 0x3000) >> 12;
6024 int pre = (vidfreq & 0x7);
6025
6026 if (!pre)
6027 return 0;
6028
6029 freq = ((div * 133333) / ((1<<post) * pre));
6030
6031 return freq;
6032}
6033
eb48eb00
DV		 6034static const struct cparams {
6035 u16 i;
6036 u16 t;
6037 u16 m;
6038 u16 c;
6039} cparams[] = {
6040 { 1, 1333, 301, 28664 },
6041 { 1, 1066, 294, 24460 },
6042 { 1, 800, 294, 25192 },
6043 { 0, 1333, 276, 27605 },
6044 { 0, 1066, 276, 27605 },
6045 { 0, 800, 231, 23784 },
6046};
6047
f531dcb2 6048static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6049{
6050 u64 total_count, diff, ret;
6051 u32 count1, count2, count3, m = 0, c = 0;
6052 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6053 int i;
6054
02d71956
DV		 6055 assert_spin_locked(&mchdev_lock);
6056
20e4d407 6057 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6058
6059 /* Prevent division-by-zero if we are asking too fast.
6060 * Also, we don't get interesting results if we are polling
6061 * faster than once in 10ms, so just return the saved value
6062 * in such cases.
6063 */
6064 if (diff1 <= 10)
20e4d407 6065 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6066
6067 count1 = I915_READ(DMIEC);
6068 count2 = I915_READ(DDREC);
6069 count3 = I915_READ(CSIEC);
6070
6071 total_count = count1 + count2 + count3;
6072
6073 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6074 if (total_count < dev_priv->ips.last_count1) {
6075 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6076 diff += total_count;
6077 } else {
20e4d407 6078 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6079 }
6080
6081 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6082 if (cparams[i].i == dev_priv->ips.c_m &&
6083 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6084 m = cparams[i].m;
6085 c = cparams[i].c;
6086 break;
6087 }
6088 }
6089
6090 diff = div_u64(diff, diff1);
6091 ret = ((m * diff) + c);
6092 ret = div_u64(ret, 10);
6093
20e4d407
DV		 6094 dev_priv->ips.last_count1 = total_count;
6095 dev_priv->ips.last_time1 = now;
eb48eb00 6096
20e4d407 6097 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6098
6099 return ret;
6100}
6101
f531dcb2
CW		 6102unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6103{
6104 unsigned long val;
6105
dc97997a 6106 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6107 return 0;
6108
6109 spin_lock_irq(&mchdev_lock);
6110
6111 val = __i915_chipset_val(dev_priv);
6112
6113 spin_unlock_irq(&mchdev_lock);
6114
6115 return val;
6116}
6117
eb48eb00
DV		 6118unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6119{
6120 unsigned long m, x, b;
6121 u32 tsfs;
6122
6123 tsfs = I915_READ(TSFS);
6124
6125 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6126 x = I915_READ8(TR1);
6127
6128 b = tsfs & TSFS_INTR_MASK;
6129
6130 return ((m * x) / 127) - b;
6131}
6132
d972d6ee
MK		 6133static int _pxvid_to_vd(u8 pxvid)
6134{
6135 if (pxvid == 0)
6136 return 0;
6137
6138 if (pxvid >= 8 && pxvid < 31)
6139 pxvid = 31;
6140
6141 return (pxvid + 2) * 125;
6142}
6143
6144static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6145{
d972d6ee
MK		 6146 const int vd = _pxvid_to_vd(pxvid);
6147 const int vm = vd - 1125;
6148
dc97997a 6149 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6150 return vm > 0 ? vm : 0;
6151
6152 return vd;
eb48eb00
DV		 6153}
6154
02d71956 6155static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6156{
5ed0bdf2 6157 u64 now, diff, diffms;
eb48eb00
DV		 6158 u32 count;
6159
02d71956 6160 assert_spin_locked(&mchdev_lock);
eb48eb00 6161
5ed0bdf2
TG		 6162 now = ktime_get_raw_ns();
6163 diffms = now - dev_priv->ips.last_time2;
6164 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6165
6166 /* Don't divide by 0 */
eb48eb00
DV		 6167 if (!diffms)
6168 return;
6169
6170 count = I915_READ(GFXEC);
6171
20e4d407
DV		 6172 if (count < dev_priv->ips.last_count2) {
6173 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6174 diff += count;
6175 } else {
20e4d407 6176 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6177 }
6178
20e4d407
DV		 6179 dev_priv->ips.last_count2 = count;
6180 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6181
6182 /* More magic constants... */
6183 diff = diff * 1181;
6184 diff = div_u64(diff, diffms * 10);
20e4d407 6185 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6186}
6187
02d71956
DV		 6188void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6189{
dc97997a 6190 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6191 return;
6192
9270388e 6193 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6194
6195 __i915_update_gfx_val(dev_priv);
6196
9270388e 6197 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6198}
6199
f531dcb2 6200static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6201{
6202 unsigned long t, corr, state1, corr2, state2;
6203 u32 pxvid, ext_v;
6204
02d71956
DV		 6205 assert_spin_locked(&mchdev_lock);
6206
616847e7 6207 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6208 pxvid = (pxvid >> 24) & 0x7f;
6209 ext_v = pvid_to_extvid(dev_priv, pxvid);
6210
6211 state1 = ext_v;
6212
6213 t = i915_mch_val(dev_priv);
6214
6215 /* Revel in the empirically derived constants */
6216
6217 /* Correction factor in 1/100000 units */
6218 if (t > 80)
6219 corr = ((t * 2349) + 135940);
6220 else if (t >= 50)
6221 corr = ((t * 964) + 29317);
6222 else /* < 50 */
6223 corr = ((t * 301) + 1004);
6224
6225 corr = corr * ((150142 * state1) / 10000 - 78642);
6226 corr /= 100000;
20e4d407 6227 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6228
6229 state2 = (corr2 * state1) / 10000;
6230 state2 /= 100; /* convert to mW */
6231
02d71956 6232 __i915_update_gfx_val(dev_priv);
eb48eb00 6233
20e4d407 6234 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6235}
6236
f531dcb2
CW		 6237unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6238{
6239 unsigned long val;
6240
dc97997a 6241 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6242 return 0;
6243
6244 spin_lock_irq(&mchdev_lock);
6245
6246 val = __i915_gfx_val(dev_priv);
6247
6248 spin_unlock_irq(&mchdev_lock);
6249
6250 return val;
6251}
6252
eb48eb00
DV		 6253/**
6254 * i915_read_mch_val - return value for IPS use
6255 *
6256 * Calculate and return a value for the IPS driver to use when deciding whether
6257 * we have thermal and power headroom to increase CPU or GPU power budget.
6258 */
6259unsigned long i915_read_mch_val(void)
6260{
6261 struct drm_i915_private *dev_priv;
6262 unsigned long chipset_val, graphics_val, ret = 0;
6263
9270388e 6264 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6265 if (!i915_mch_dev)
6266 goto out_unlock;
6267 dev_priv = i915_mch_dev;
6268
f531dcb2
CW		 6269 chipset_val = __i915_chipset_val(dev_priv);
6270 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6271
6272 ret = chipset_val + graphics_val;
6273
6274out_unlock:
9270388e 6275 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6276
6277 return ret;
6278}
6279EXPORT_SYMBOL_GPL(i915_read_mch_val);
6280
6281/**
6282 * i915_gpu_raise - raise GPU frequency limit
6283 *
6284 * Raise the limit; IPS indicates we have thermal headroom.
6285 */
6286bool i915_gpu_raise(void)
6287{
6288 struct drm_i915_private *dev_priv;
6289 bool ret = true;
6290
9270388e 6291 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6292 if (!i915_mch_dev) {
6293 ret = false;
6294 goto out_unlock;
6295 }
6296 dev_priv = i915_mch_dev;
6297
20e4d407
DV		 6298 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6299 dev_priv->ips.max_delay--;
eb48eb00
DV		 6300
6301out_unlock:
9270388e 6302 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6303
6304 return ret;
6305}
6306EXPORT_SYMBOL_GPL(i915_gpu_raise);
6307
6308/**
6309 * i915_gpu_lower - lower GPU frequency limit
6310 *
6311 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6312 * frequency maximum.
6313 */
6314bool i915_gpu_lower(void)
6315{
6316 struct drm_i915_private *dev_priv;
6317 bool ret = true;
6318
9270388e 6319 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6320 if (!i915_mch_dev) {
6321 ret = false;
6322 goto out_unlock;
6323 }
6324 dev_priv = i915_mch_dev;
6325
20e4d407
DV		 6326 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6327 dev_priv->ips.max_delay++;
eb48eb00
DV		 6328
6329out_unlock:
9270388e 6330 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6331
6332 return ret;
6333}
6334EXPORT_SYMBOL_GPL(i915_gpu_lower);
6335
6336/**
6337 * i915_gpu_busy - indicate GPU business to IPS
6338 *
6339 * Tell the IPS driver whether or not the GPU is busy.
6340 */
6341bool i915_gpu_busy(void)
6342{
eb48eb00
DV		 6343 bool ret = false;
6344
9270388e 6345 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6346 if (i915_mch_dev)
6347 ret = i915_mch_dev->gt.awake;
9270388e 6348 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6349
6350 return ret;
6351}
6352EXPORT_SYMBOL_GPL(i915_gpu_busy);
6353
6354/**
6355 * i915_gpu_turbo_disable - disable graphics turbo
6356 *
6357 * Disable graphics turbo by resetting the max frequency and setting the
6358 * current frequency to the default.
6359 */
6360bool i915_gpu_turbo_disable(void)
6361{
6362 struct drm_i915_private *dev_priv;
6363 bool ret = true;
6364
9270388e 6365 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6366 if (!i915_mch_dev) {
6367 ret = false;
6368 goto out_unlock;
6369 }
6370 dev_priv = i915_mch_dev;
6371
20e4d407 6372 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6373
91d14251 6374 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6375 ret = false;
6376
6377out_unlock:
9270388e 6378 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6379
6380 return ret;
6381}
6382EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6383
6384/**
6385 * Tells the intel_ips driver that the i915 driver is now loaded, if
6386 * IPS got loaded first.
6387 *
6388 * This awkward dance is so that neither module has to depend on the
6389 * other in order for IPS to do the appropriate communication of
6390 * GPU turbo limits to i915.
6391 */
6392static void
6393ips_ping_for_i915_load(void)
6394{
6395 void (*link)(void);
6396
6397 link = symbol_get(ips_link_to_i915_driver);
6398 if (link) {
6399 link();
6400 symbol_put(ips_link_to_i915_driver);
6401 }
6402}
6403
6404void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6405{
02d71956
DV		 6406 /* We only register the i915 ips part with intel-ips once everything is
6407 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6408 spin_lock_irq(&mchdev_lock);
eb48eb00 6409 i915_mch_dev = dev_priv;
9270388e 6410 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6411
6412 ips_ping_for_i915_load();
6413}
6414
6415void intel_gpu_ips_teardown(void)
6416{
9270388e 6417 spin_lock_irq(&mchdev_lock);
eb48eb00 6418 i915_mch_dev = NULL;
9270388e 6419 spin_unlock_irq(&mchdev_lock);
eb48eb00 6420}
76c3552f 6421
dc97997a 6422static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6423{
dde18883
ED		 6424 u32 lcfuse;
6425 u8 pxw[16];
6426 int i;
6427
6428 /* Disable to program */
6429 I915_WRITE(ECR, 0);
6430 POSTING_READ(ECR);
6431
6432 /* Program energy weights for various events */
6433 I915_WRITE(SDEW, 0x15040d00);
6434 I915_WRITE(CSIEW0, 0x007f0000);
6435 I915_WRITE(CSIEW1, 0x1e220004);
6436 I915_WRITE(CSIEW2, 0x04000004);
6437
6438 for (i = 0; i < 5; i++)
616847e7 6439 I915_WRITE(PEW(i), 0);
dde18883 6440 for (i = 0; i < 3; i++)
616847e7 6441 I915_WRITE(DEW(i), 0);
dde18883
ED		 6442
6443 /* Program P-state weights to account for frequency power adjustment */
6444 for (i = 0; i < 16; i++) {
616847e7 6445 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6446 unsigned long freq = intel_pxfreq(pxvidfreq);
6447 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6448 PXVFREQ_PX_SHIFT;
6449 unsigned long val;
6450
6451 val = vid * vid;
6452 val *= (freq / 1000);
6453 val *= 255;
6454 val /= (127*127*900);
6455 if (val > 0xff)
6456 DRM_ERROR("bad pxval: %ld\n", val);
6457 pxw[i] = val;
6458 }
6459 /* Render standby states get 0 weight */
6460 pxw[14] = 0;
6461 pxw[15] = 0;
6462
6463 for (i = 0; i < 4; i++) {
6464 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6465 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6466 I915_WRITE(PXW(i), val);
dde18883
ED		 6467 }
6468
6469 /* Adjust magic regs to magic values (more experimental results) */
6470 I915_WRITE(OGW0, 0);
6471 I915_WRITE(OGW1, 0);
6472 I915_WRITE(EG0, 0x00007f00);
6473 I915_WRITE(EG1, 0x0000000e);
6474 I915_WRITE(EG2, 0x000e0000);
6475 I915_WRITE(EG3, 0x68000300);
6476 I915_WRITE(EG4, 0x42000000);
6477 I915_WRITE(EG5, 0x00140031);
6478 I915_WRITE(EG6, 0);
6479 I915_WRITE(EG7, 0);
6480
6481 for (i = 0; i < 8; i++)
616847e7 6482 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6483
6484 /* Enable PMON + select events */
6485 I915_WRITE(ECR, 0x80000019);
6486
6487 lcfuse = I915_READ(LCFUSE02);
6488
20e4d407 6489 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6490}
6491
dc97997a 6492void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6493{
b268c699
ID		 6494 /*
6495 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6496 * requirement.
6497 */
6498 if (!i915.enable_rc6) {
6499 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6500 intel_runtime_pm_get(dev_priv);
6501 }
e6069ca8 6502
b5163dbb 6503 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6504 mutex_lock(&dev_priv->rps.hw_lock);
6505
6506 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6507 if (IS_CHERRYVIEW(dev_priv))
6508 cherryview_init_gt_powersave(dev_priv);
6509 else if (IS_VALLEYVIEW(dev_priv))
6510 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6511 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6512 gen6_init_rps_frequencies(dev_priv);
6513
6514 /* Derive initial user preferences/limits from the hardware limits */
6515 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6516 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6517
6518 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6519 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6520
6521 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6522 dev_priv->rps.min_freq_softlimit =
6523 max_t(int,
6524 dev_priv->rps.efficient_freq,
6525 intel_freq_opcode(dev_priv, 450));
6526
99ac9612
CW		 6527 /* After setting max-softlimit, find the overclock max freq */
6528 if (IS_GEN6(dev_priv) ||
6529 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6530 u32 params = 0;
6531
6532 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6533 if (params & BIT(31)) { /* OC supported */
6534 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6535 (dev_priv->rps.max_freq & 0xff) * 50,
6536 (params & 0xff) * 50);
6537 dev_priv->rps.max_freq = params & 0xff;
6538 }
6539 }
6540
29ecd78d
CW		 6541 /* Finally allow us to boost to max by default */
6542 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6543
773ea9a8 6544 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6545 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6546
6547 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6548}
6549
dc97997a 6550void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6551{
8dac1e1f 6552 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6553 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6554
6555 if (!i915.enable_rc6)
6556 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6557}
6558
54b4f68f
CW		 6559/**
6560 * intel_suspend_gt_powersave - suspend PM work and helper threads
6561 * @dev_priv: i915 device
6562 *
6563 * We don't want to disable RC6 or other features here, we just want
6564 * to make sure any work we've queued has finished and won't bother
6565 * us while we're suspended.
6566 */
6567void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6568{
6569 if (INTEL_GEN(dev_priv) < 6)
6570 return;
6571
6572 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6573 intel_runtime_pm_put(dev_priv);
6574
6575 /* gen6_rps_idle() will be called later to disable interrupts */
6576}
6577
b7137e0c
CW		 6578void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6579{
6580 dev_priv->rps.enabled = true; /* force disabling */
6581 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6582
6583 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6584}
6585
dc97997a 6586void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6587{
b7137e0c
CW		 6588 if (!READ_ONCE(dev_priv->rps.enabled))
6589 return;
e494837a 6590
b7137e0c 6591 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6592
b7137e0c
CW		 6593 if (INTEL_GEN(dev_priv) >= 9) {
6594 gen9_disable_rc6(dev_priv);
6595 gen9_disable_rps(dev_priv);
6596 } else if (IS_CHERRYVIEW(dev_priv)) {
6597 cherryview_disable_rps(dev_priv);
6598 } else if (IS_VALLEYVIEW(dev_priv)) {
6599 valleyview_disable_rps(dev_priv);
6600 } else if (INTEL_GEN(dev_priv) >= 6) {
6601 gen6_disable_rps(dev_priv);
6602 } else if (IS_IRONLAKE_M(dev_priv)) {
6603 ironlake_disable_drps(dev_priv);
930ebb46 6604 }
b7137e0c
CW		 6605
6606 dev_priv->rps.enabled = false;
6607 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6608}
6609
b7137e0c 6610void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6611{
54b4f68f
CW		 6612 /* We shouldn't be disabling as we submit, so this should be less
6613 * racy than it appears!
6614 */
b7137e0c
CW		 6615 if (READ_ONCE(dev_priv->rps.enabled))
6616 return;
1a01ab3b 6617
b7137e0c
CW		 6618 /* Powersaving is controlled by the host when inside a VM */
6619 if (intel_vgpu_active(dev_priv))
6620 return;
0a073b84 6621
b7137e0c 6622 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6623
6624 if (IS_CHERRYVIEW(dev_priv)) {
6625 cherryview_enable_rps(dev_priv);
6626 } else if (IS_VALLEYVIEW(dev_priv)) {
6627 valleyview_enable_rps(dev_priv);
b7137e0c 6628 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6629 gen9_enable_rc6(dev_priv);
6630 gen9_enable_rps(dev_priv);
6631 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6632 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6633 } else if (IS_BROADWELL(dev_priv)) {
6634 gen8_enable_rps(dev_priv);
fb7404e8 6635 gen6_update_ring_freq(dev_priv);
b7137e0c 6636 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6637 gen6_enable_rps(dev_priv);
fb7404e8 6638 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6639 } else if (IS_IRONLAKE_M(dev_priv)) {
6640 ironlake_enable_drps(dev_priv);
6641 intel_init_emon(dev_priv);
0a073b84 6642 }
aed242ff
CW		 6643
6644 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6645 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6646
6647 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6648 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6649
54b4f68f 6650 dev_priv->rps.enabled = true;
b7137e0c
CW		 6651 mutex_unlock(&dev_priv->rps.hw_lock);
6652}
3cc134e3 6653
54b4f68f
CW		 6654static void __intel_autoenable_gt_powersave(struct work_struct *work)
6655{
6656 struct drm_i915_private *dev_priv =
6657 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6658 struct intel_engine_cs *rcs;
6659 struct drm_i915_gem_request *req;
6660
6661 if (READ_ONCE(dev_priv->rps.enabled))
6662 goto out;
6663
6664 rcs = &dev_priv->engine[RCS];
6665 if (rcs->last_context)
6666 goto out;
6667
6668 if (!rcs->init_context)
6669 goto out;
6670
6671 mutex_lock(&dev_priv->drm.struct_mutex);
6672
6673 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6674 if (IS_ERR(req))
6675 goto unlock;
6676
6677 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6678 rcs->init_context(req);
6679
6680 /* Mark the device busy, calling intel_enable_gt_powersave() */
6681 i915_add_request_no_flush(req);
6682
6683unlock:
6684 mutex_unlock(&dev_priv->drm.struct_mutex);
6685out:
6686 intel_runtime_pm_put(dev_priv);
6687}
6688
6689void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6690{
6691 if (READ_ONCE(dev_priv->rps.enabled))
6692 return;
6693
6694 if (IS_IRONLAKE_M(dev_priv)) {
6695 ironlake_enable_drps(dev_priv);
6696 mutex_lock(&dev_priv->drm.struct_mutex);
6697 intel_init_emon(dev_priv);
6698 mutex_unlock(&dev_priv->drm.struct_mutex);
6699 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6700 /*
6701 * PCU communication is slow and this doesn't need to be
6702 * done at any specific time, so do this out of our fast path
6703 * to make resume and init faster.
6704 *
6705 * We depend on the HW RC6 power context save/restore
6706 * mechanism when entering D3 through runtime PM suspend. So
6707 * disable RPM until RPS/RC6 is properly setup. We can only
6708 * get here via the driver load/system resume/runtime resume
6709 * paths, so the _noresume version is enough (and in case of
6710 * runtime resume it's necessary).
6711 */
6712 if (queue_delayed_work(dev_priv->wq,
6713 &dev_priv->rps.autoenable_work,
6714 round_jiffies_up_relative(HZ)))
6715 intel_runtime_pm_get_noresume(dev_priv);
6716 }
6717}
6718
3107bd48
DV		 6719static void ibx_init_clock_gating(struct drm_device *dev)
6720{
fac5e23e 6721 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6722
6723 /*
6724 * On Ibex Peak and Cougar Point, we need to disable clock
6725 * gating for the panel power sequencer or it will fail to
6726 * start up when no ports are active.
6727 */
6728 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6729}
6730
0e088b8f
VS		 6731static void g4x_disable_trickle_feed(struct drm_device *dev)
6732{
fac5e23e 6733 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6734 enum pipe pipe;
0e088b8f 6735
055e393f 6736 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6737 I915_WRITE(DSPCNTR(pipe),
6738 I915_READ(DSPCNTR(pipe)) |
6739 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6740
6741 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6742 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6743 }
6744}
6745
017636cc
VS		 6746static void ilk_init_lp_watermarks(struct drm_device *dev)
6747{
fac5e23e 6748 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6749
6750 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6751 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6752 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6753
6754 /*
6755 * Don't touch WM1S_LP_EN here.
6756 * Doing so could cause underruns.
6757 */
6758}
6759
1fa61106 6760static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6761{
fac5e23e 6762 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6763 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6764
f1e8fa56
DL		 6765 /*
6766 * Required for FBC
6767 * WaFbcDisableDpfcClockGating:ilk
6768 */
4d47e4f5
DL		 6769 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6770 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6771 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6772
6773 I915_WRITE(PCH_3DCGDIS0,
6774 MARIUNIT_CLOCK_GATE_DISABLE |
6775 SVSMUNIT_CLOCK_GATE_DISABLE);
6776 I915_WRITE(PCH_3DCGDIS1,
6777 VFMUNIT_CLOCK_GATE_DISABLE);
6778
6f1d69b0
ED		 6779 /*
6780 * According to the spec the following bits should be set in
6781 * order to enable memory self-refresh
6782 * The bit 22/21 of 0x42004
6783 * The bit 5 of 0x42020
6784 * The bit 15 of 0x45000
6785 */
6786 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6787 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6788 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6789 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6790 I915_WRITE(DISP_ARB_CTL,
6791 (I915_READ(DISP_ARB_CTL) |
6792 DISP_FBC_WM_DIS));
017636cc
VS		 6793
6794 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6795
6796 /*
6797 * Based on the document from hardware guys the following bits
6798 * should be set unconditionally in order to enable FBC.
6799 * The bit 22 of 0x42000
6800 * The bit 22 of 0x42004
6801 * The bit 7,8,9 of 0x42020.
6802 */
6803 if (IS_IRONLAKE_M(dev)) {
4bb35334 6804 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6805 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6806 I915_READ(ILK_DISPLAY_CHICKEN1) |
6807 ILK_FBCQ_DIS);
6808 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6809 I915_READ(ILK_DISPLAY_CHICKEN2) |
6810 ILK_DPARB_GATE);
6f1d69b0
ED		 6811 }
6812
4d47e4f5
DL		 6813 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6814
6f1d69b0
ED		 6815 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6816 I915_READ(ILK_DISPLAY_CHICKEN2) |
6817 ILK_ELPIN_409_SELECT);
6818 I915_WRITE(_3D_CHICKEN2,
6819 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6820 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6821
ecdb4eb7 6822 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6823 I915_WRITE(CACHE_MODE_0,
6824 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6825
4e04632e
AG		 6826 /* WaDisable_RenderCache_OperationalFlush:ilk */
6827 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6828
0e088b8f 6829 g4x_disable_trickle_feed(dev);
bdad2b2f 6830
3107bd48
DV		 6831 ibx_init_clock_gating(dev);
6832}
6833
6834static void cpt_init_clock_gating(struct drm_device *dev)
6835{
fac5e23e 6836 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6837 int pipe;
3f704fa2 6838 uint32_t val;
3107bd48
DV		 6839
6840 /*
6841 * On Ibex Peak and Cougar Point, we need to disable clock
6842 * gating for the panel power sequencer or it will fail to
6843 * start up when no ports are active.
6844 */
cd664078
JB		 6845 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6846 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6847 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6848 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6849 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6850 /* The below fixes the weird display corruption, a few pixels shifted
6851 * downward, on (only) LVDS of some HP laptops with IVY.
6852 */
055e393f 6853 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6854 val = I915_READ(TRANS_CHICKEN2(pipe));
6855 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6856 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6857 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6858 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6859 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6860 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6861 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6862 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6863 }
3107bd48 6864 /* WADP0ClockGatingDisable */
055e393f 6865 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6866 I915_WRITE(TRANS_CHICKEN1(pipe),
6867 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6868 }
6f1d69b0
ED		 6869}
6870
1d7aaa0c
DV		 6871static void gen6_check_mch_setup(struct drm_device *dev)
6872{
fac5e23e 6873 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 6874 uint32_t tmp;
6875
6876 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6877 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6878 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6879 tmp);
1d7aaa0c
DV		 6880}
6881
1fa61106 6882static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 6883{
fac5e23e 6884 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6885 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6886
231e54f6 6887 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6888
6889 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6890 I915_READ(ILK_DISPLAY_CHICKEN2) |
6891 ILK_ELPIN_409_SELECT);
6892
ecdb4eb7 6893 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6894 I915_WRITE(_3D_CHICKEN,
6895 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6896
4e04632e
AG		 6897 /* WaDisable_RenderCache_OperationalFlush:snb */
6898 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6899
8d85d272
VS		 6900 /*
6901 * BSpec recoomends 8x4 when MSAA is used,
6902 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6903 *
6904 * Note that PS/WM thread counts depend on the WIZ hashing
6905 * disable bit, which we don't touch here, but it's good
6906 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6907 */
6908 I915_WRITE(GEN6_GT_MODE,
98533251 6909 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6910
017636cc 6911 ilk_init_lp_watermarks(dev);
6f1d69b0 6912
6f1d69b0 6913 I915_WRITE(CACHE_MODE_0,
50743298 6914 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6915
6916 I915_WRITE(GEN6_UCGCTL1,
6917 I915_READ(GEN6_UCGCTL1) |
6918 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6919 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6920
6921 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6922 * gating disable must be set. Failure to set it results in
6923 * flickering pixels due to Z write ordering failures after
6924 * some amount of runtime in the Mesa "fire" demo, and Unigine
6925 * Sanctuary and Tropics, and apparently anything else with
6926 * alpha test or pixel discard.
6927 *
6928 * According to the spec, bit 11 (RCCUNIT) must also be set,
6929 * but we didn't debug actual testcases to find it out.
0f846f81 6930 *
ef59318c
VS		 6931 * WaDisableRCCUnitClockGating:snb
6932 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6933 */
6934 I915_WRITE(GEN6_UCGCTL2,
6935 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6936 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6937
5eb146dd 6938 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6939 I915_WRITE(_3D_CHICKEN3,
6940 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6941
e927ecde
VS		 6942 /*
6943 * Bspec says:
6944 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6945 * 3DSTATE_SF number of SF output attributes is more than 16."
6946 */
6947 I915_WRITE(_3D_CHICKEN3,
6948 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6949
6f1d69b0
ED		 6950 /*
6951 * According to the spec the following bits should be
6952 * set in order to enable memory self-refresh and fbc:
6953 * The bit21 and bit22 of 0x42000
6954 * The bit21 and bit22 of 0x42004
6955 * The bit5 and bit7 of 0x42020
6956 * The bit14 of 0x70180
6957 * The bit14 of 0x71180
4bb35334
DL		 6958 *
6959 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6960 */
6961 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6962 I915_READ(ILK_DISPLAY_CHICKEN1) |
6963 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6964 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6965 I915_READ(ILK_DISPLAY_CHICKEN2) |
6966 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6967 I915_WRITE(ILK_DSPCLK_GATE_D,
6968 I915_READ(ILK_DSPCLK_GATE_D) |
6969 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6970 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6971
0e088b8f 6972 g4x_disable_trickle_feed(dev);
f8f2ac9a 6973
3107bd48 6974 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6975
6976 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6977}
6978
6979static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6980{
6981 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6982
3aad9059 6983 /*
46680e0a 6984 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6985 *
6986 * This actually overrides the dispatch
6987 * mode for all thread types.
6988 */
6f1d69b0
ED		 6989 reg &= ~GEN7_FF_SCHED_MASK;
6990 reg |= GEN7_FF_TS_SCHED_HW;
6991 reg |= GEN7_FF_VS_SCHED_HW;
6992 reg |= GEN7_FF_DS_SCHED_HW;
6993
6994 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6995}
6996
17a303ec
PZ		 6997static void lpt_init_clock_gating(struct drm_device *dev)
6998{
fac5e23e 6999 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7000
7001 /*
7002 * TODO: this bit should only be enabled when really needed, then
7003 * disabled when not needed anymore in order to save power.
7004 */
c2699524 7005 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 7006 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7007 I915_READ(SOUTH_DSPCLK_GATE_D) |
7008 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7009
7010 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7011 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7012 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7013 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7014}
7015
7d708ee4
ID		 7016static void lpt_suspend_hw(struct drm_device *dev)
7017{
fac5e23e 7018 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7019
c2699524 7020 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7021 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7022
7023 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7024 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7025 }
7026}
7027
450174fe
ID		 7028static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7029 int general_prio_credits,
7030 int high_prio_credits)
7031{
7032 u32 misccpctl;
7033
7034 /* WaTempDisableDOPClkGating:bdw */
7035 misccpctl = I915_READ(GEN7_MISCCPCTL);
7036 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7037
7038 I915_WRITE(GEN8_L3SQCREG1,
7039 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7040 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7041
7042 /*
7043 * Wait at least 100 clocks before re-enabling clock gating.
7044 * See the definition of L3SQCREG1 in BSpec.
7045 */
7046 POSTING_READ(GEN8_L3SQCREG1);
7047 udelay(1);
7048 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7049}
7050
9498dba7
MK		 7051static void kabylake_init_clock_gating(struct drm_device *dev)
7052{
9146f308 7053 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7054
b033bb6d 7055 gen9_init_clock_gating(dev);
9498dba7
MK		 7056
7057 /* WaDisableSDEUnitClockGating:kbl */
7058 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7059 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7060 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7061
7062 /* WaDisableGamClockGating:kbl */
7063 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7064 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7065 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7066
7067 /* WaFbcNukeOnHostModify:kbl */
7068 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7069 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7070}
7071
dc00b6a0
DV		 7072static void skylake_init_clock_gating(struct drm_device *dev)
7073{
c584e2d3 7074 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7075
b033bb6d 7076 gen9_init_clock_gating(dev);
44fff99f
MK		 7077
7078 /* WAC6entrylatency:skl */
7079 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7080 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7081
7082 /* WaFbcNukeOnHostModify:skl */
7083 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7084 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7085}
7086
47c2bd97 7087static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7088{
fac5e23e 7089 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7090 enum pipe pipe;
1020a5c2 7091
7ad0dbab 7092 ilk_init_lp_watermarks(dev);
50ed5fbd 7093
ab57fff1 7094 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7095 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7096
ab57fff1 7097 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7098 I915_WRITE(CHICKEN_PAR1_1,
7099 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7100
ab57fff1 7101 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7102 for_each_pipe(dev_priv, pipe) {
07d27e20 7103 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7104 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7105 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7106 }
63801f21 7107
ab57fff1
BW		 7108 /* WaVSRefCountFullforceMissDisable:bdw */
7109 /* WaDSRefCountFullforceMissDisable:bdw */
7110 I915_WRITE(GEN7_FF_THREAD_MODE,
7111 I915_READ(GEN7_FF_THREAD_MODE) &
7112 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7113
295e8bb7
VS		 7114 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7115 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7116
7117 /* WaDisableSDEUnitClockGating:bdw */
7118 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7119 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7120
450174fe
ID		 7121 /* WaProgramL3SqcReg1Default:bdw */
7122 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7123
6d50b065
VS		 7124 /*
7125 * WaGttCachingOffByDefault:bdw
7126 * GTT cache may not work with big pages, so if those
7127 * are ever enabled GTT cache may need to be disabled.
7128 */
7129 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7130
17e0adf0
MK		 7131 /* WaKVMNotificationOnConfigChange:bdw */
7132 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7133 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7134
89d6b2b8 7135 lpt_init_clock_gating(dev);
1020a5c2
BW		 7136}
7137
cad2a2d7
ED		 7138static void haswell_init_clock_gating(struct drm_device *dev)
7139{
fac5e23e 7140 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7141
017636cc 7142 ilk_init_lp_watermarks(dev);
cad2a2d7 7143
f3fc4884
FJ		 7144 /* L3 caching of data atomics doesn't work -- disable it. */
7145 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7146 I915_WRITE(HSW_ROW_CHICKEN3,
7147 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7148
ecdb4eb7 7149 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7150 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7151 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7152 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7153
e36ea7ff
VS		 7154 /* WaVSRefCountFullforceMissDisable:hsw */
7155 I915_WRITE(GEN7_FF_THREAD_MODE,
7156 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7157
4e04632e
AG		 7158 /* WaDisable_RenderCache_OperationalFlush:hsw */
7159 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7160
fe27c606
CW		 7161 /* enable HiZ Raw Stall Optimization */
7162 I915_WRITE(CACHE_MODE_0_GEN7,
7163 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7164
ecdb4eb7 7165 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7166 I915_WRITE(CACHE_MODE_1,
7167 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7168
a12c4967
VS		 7169 /*
7170 * BSpec recommends 8x4 when MSAA is used,
7171 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7172 *
7173 * Note that PS/WM thread counts depend on the WIZ hashing
7174 * disable bit, which we don't touch here, but it's good
7175 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7176 */
7177 I915_WRITE(GEN7_GT_MODE,
98533251 7178 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7179
94411593
KG		 7180 /* WaSampleCChickenBitEnable:hsw */
7181 I915_WRITE(HALF_SLICE_CHICKEN3,
7182 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7183
ecdb4eb7 7184 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7185 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7186
90a88643
PZ		 7187 /* WaRsPkgCStateDisplayPMReq:hsw */
7188 I915_WRITE(CHICKEN_PAR1_1,
7189 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7190
17a303ec 7191 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7192}
7193
1fa61106 7194static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7195{
fac5e23e 7196 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7197 uint32_t snpcr;
6f1d69b0 7198
017636cc 7199 ilk_init_lp_watermarks(dev);
6f1d69b0 7200
231e54f6 7201 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7202
ecdb4eb7 7203 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7204 I915_WRITE(_3D_CHICKEN3,
7205 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7206
ecdb4eb7 7207 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7208 I915_WRITE(IVB_CHICKEN3,
7209 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7210 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7211
ecdb4eb7 7212 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7213 if (IS_IVB_GT1(dev))
7214 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7215 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7216
4e04632e
AG		 7217 /* WaDisable_RenderCache_OperationalFlush:ivb */
7218 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7219
ecdb4eb7 7220 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7221 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7222 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7223
ecdb4eb7 7224 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7225 I915_WRITE(GEN7_L3CNTLREG1,
7226 GEN7_WA_FOR_GEN7_L3_CONTROL);
7227 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7228 GEN7_WA_L3_CHICKEN_MODE);
7229 if (IS_IVB_GT1(dev))
7230 I915_WRITE(GEN7_ROW_CHICKEN2,
7231 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7232 else {
7233 /* must write both registers */
7234 I915_WRITE(GEN7_ROW_CHICKEN2,
7235 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7236 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7237 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7238 }
6f1d69b0 7239
ecdb4eb7 7240 /* WaForceL3Serialization:ivb */
61939d97
JB		 7241 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7242 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7243
1b80a19a 7244 /*
0f846f81 7245 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7246 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7247 */
7248 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7249 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7250
ecdb4eb7 7251 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7252 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7253 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7254 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7255
0e088b8f 7256 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7257
7258 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7259
22721343
CW		 7260 if (0) { /* causes HiZ corruption on ivb:gt1 */
7261 /* enable HiZ Raw Stall Optimization */
7262 I915_WRITE(CACHE_MODE_0_GEN7,
7263 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7264 }
116f2b6d 7265
ecdb4eb7 7266 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7267 I915_WRITE(CACHE_MODE_1,
7268 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7269
a607c1a4
VS		 7270 /*
7271 * BSpec recommends 8x4 when MSAA is used,
7272 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7273 *
7274 * Note that PS/WM thread counts depend on the WIZ hashing
7275 * disable bit, which we don't touch here, but it's good
7276 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7277 */
7278 I915_WRITE(GEN7_GT_MODE,
98533251 7279 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7280
20848223
BW		 7281 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7282 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7283 snpcr |= GEN6_MBC_SNPCR_MED;
7284 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7285
ab5c608b
BW		 7286 if (!HAS_PCH_NOP(dev))
7287 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7288
7289 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7290}
7291
1fa61106 7292static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7293{
fac5e23e 7294 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7295
ecdb4eb7 7296 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7297 I915_WRITE(_3D_CHICKEN3,
7298 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7299
ecdb4eb7 7300 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7301 I915_WRITE(IVB_CHICKEN3,
7302 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7303 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7304
fad7d36e 7305 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7306 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7307 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7308 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7309 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7310
4e04632e
AG		 7311 /* WaDisable_RenderCache_OperationalFlush:vlv */
7312 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7313
ecdb4eb7 7314 /* WaForceL3Serialization:vlv */
61939d97
JB		 7315 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7316 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7317
ecdb4eb7 7318 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7319 I915_WRITE(GEN7_ROW_CHICKEN2,
7320 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7321
ecdb4eb7 7322 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7323 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7324 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7325 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7326
46680e0a
VS		 7327 gen7_setup_fixed_func_scheduler(dev_priv);
7328
3c0edaeb 7329 /*
0f846f81 7330 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7331 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7332 */
7333 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7334 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7335
c98f5062
AG		 7336 /* WaDisableL3Bank2xClockGate:vlv
7337 * Disabling L3 clock gating- MMIO 940c[25] = 1
7338 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7339 I915_WRITE(GEN7_UCGCTL4,
7340 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7341
afd58e79
VS		 7342 /*
7343 * BSpec says this must be set, even though
7344 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7345 */
6b26c86d
DV		 7346 I915_WRITE(CACHE_MODE_1,
7347 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7348
da2518f9
VS		 7349 /*
7350 * BSpec recommends 8x4 when MSAA is used,
7351 * however in practice 16x4 seems fastest.
7352 *
7353 * Note that PS/WM thread counts depend on the WIZ hashing
7354 * disable bit, which we don't touch here, but it's good
7355 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7356 */
7357 I915_WRITE(GEN7_GT_MODE,
7358 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7359
031994ee
VS		 7360 /*
7361 * WaIncreaseL3CreditsForVLVB0:vlv
7362 * This is the hardware default actually.
7363 */
7364 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7365
2d809570 7366 /*
ecdb4eb7 7367 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7368 * Disable clock gating on th GCFG unit to prevent a delay
7369 * in the reporting of vblank events.
7370 */
7a0d1eed 7371 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7372}
7373
a4565da8
VS		 7374static void cherryview_init_clock_gating(struct drm_device *dev)
7375{
fac5e23e 7376 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7377
232ce337
VS		 7378 /* WaVSRefCountFullforceMissDisable:chv */
7379 /* WaDSRefCountFullforceMissDisable:chv */
7380 I915_WRITE(GEN7_FF_THREAD_MODE,
7381 I915_READ(GEN7_FF_THREAD_MODE) &
7382 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7383
7384 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7385 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7386 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7387
7388 /* WaDisableCSUnitClockGating:chv */
7389 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7390 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7391
7392 /* WaDisableSDEUnitClockGating:chv */
7393 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7394 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7395
450174fe
ID		 7396 /*
7397 * WaProgramL3SqcReg1Default:chv
7398 * See gfxspecs/Related Documents/Performance Guide/
7399 * LSQC Setting Recommendations.
7400 */
7401 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7402
6d50b065
VS		 7403 /*
7404 * GTT cache may not work with big pages, so if those
7405 * are ever enabled GTT cache may need to be disabled.
7406 */
7407 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7408}
7409
1fa61106 7410static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7411{
fac5e23e 7412 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7413 uint32_t dspclk_gate;
7414
7415 I915_WRITE(RENCLK_GATE_D1, 0);
7416 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7417 GS_UNIT_CLOCK_GATE_DISABLE |
7418 CL_UNIT_CLOCK_GATE_DISABLE);
7419 I915_WRITE(RAMCLK_GATE_D, 0);
7420 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7421 OVRUNIT_CLOCK_GATE_DISABLE |
7422 OVCUNIT_CLOCK_GATE_DISABLE;
7423 if (IS_GM45(dev))
7424 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7425 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7426
7427 /* WaDisableRenderCachePipelinedFlush */
7428 I915_WRITE(CACHE_MODE_0,
7429 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7430
4e04632e
AG		 7431 /* WaDisable_RenderCache_OperationalFlush:g4x */
7432 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7433
0e088b8f 7434 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7435}
7436
1fa61106 7437static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7438{
fac5e23e 7439 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7440
7441 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7442 I915_WRITE(RENCLK_GATE_D2, 0);
7443 I915_WRITE(DSPCLK_GATE_D, 0);
7444 I915_WRITE(RAMCLK_GATE_D, 0);
7445 I915_WRITE16(DEUC, 0);
20f94967
VS		 7446 I915_WRITE(MI_ARB_STATE,
7447 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7448
7449 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7450 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7451}
7452
1fa61106 7453static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7454{
fac5e23e 7455 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7456
7457 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7458 I965_RCC_CLOCK_GATE_DISABLE |
7459 I965_RCPB_CLOCK_GATE_DISABLE |
7460 I965_ISC_CLOCK_GATE_DISABLE |
7461 I965_FBC_CLOCK_GATE_DISABLE);
7462 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7463 I915_WRITE(MI_ARB_STATE,
7464 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7465
7466 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7467 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7468}
7469
1fa61106 7470static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7471{
fac5e23e 7472 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7473 u32 dstate = I915_READ(D_STATE);
7474
7475 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7476 DSTATE_DOT_CLOCK_GATING;
7477 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7478
7479 if (IS_PINEVIEW(dev))
7480 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7481
7482 /* IIR "flip pending" means done if this bit is set */
7483 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7484
7485 /* interrupts should cause a wake up from C3 */
3299254f 7486 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7487
7488 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7489 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7490
7491 I915_WRITE(MI_ARB_STATE,
7492 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7493}
7494
1fa61106 7495static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7496{
fac5e23e 7497 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7498
7499 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7500
7501 /* interrupts should cause a wake up from C3 */
7502 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7503 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7504
7505 I915_WRITE(MEM_MODE,
7506 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7507}
7508
1fa61106 7509static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7510{
fac5e23e 7511 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7512
7513 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7514
7515 I915_WRITE(MEM_MODE,
7516 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7517 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7518}
7519
6f1d69b0
ED		 7520void intel_init_clock_gating(struct drm_device *dev)
7521{
fac5e23e 7522 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7523
bb400da9 7524 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7525}
7526
7d708ee4
ID		 7527void intel_suspend_hw(struct drm_device *dev)
7528{
7529 if (HAS_PCH_LPT(dev))
7530 lpt_suspend_hw(dev);
7531}
7532
bb400da9
ID		 7533static void nop_init_clock_gating(struct drm_device *dev)
7534{
7535 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7536}
7537
7538/**
7539 * intel_init_clock_gating_hooks - setup the clock gating hooks
7540 * @dev_priv: device private
7541 *
7542 * Setup the hooks that configure which clocks of a given platform can be
7543 * gated and also apply various GT and display specific workarounds for these
7544 * platforms. Note that some GT specific workarounds are applied separately
7545 * when GPU contexts or batchbuffers start their execution.
7546 */
7547void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7548{
7549 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7550 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7551 else if (IS_KABYLAKE(dev_priv))
9498dba7 7552 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7553 else if (IS_BROXTON(dev_priv))
7554 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7555 else if (IS_BROADWELL(dev_priv))
7556 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7557 else if (IS_CHERRYVIEW(dev_priv))
7558 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7559 else if (IS_HASWELL(dev_priv))
7560 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7561 else if (IS_IVYBRIDGE(dev_priv))
7562 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7563 else if (IS_VALLEYVIEW(dev_priv))
7564 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7565 else if (IS_GEN6(dev_priv))
7566 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7567 else if (IS_GEN5(dev_priv))
7568 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7569 else if (IS_G4X(dev_priv))
7570 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7571 else if (IS_CRESTLINE(dev_priv))
7572 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7573 else if (IS_BROADWATER(dev_priv))
7574 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7575 else if (IS_GEN3(dev_priv))
7576 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7577 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7578 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7579 else if (IS_GEN2(dev_priv))
7580 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7581 else {
7582 MISSING_CASE(INTEL_DEVID(dev_priv));
7583 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7584 }
7585}
7586
1fa61106
ED		 7587/* Set up chip specific power management-related functions */
7588void intel_init_pm(struct drm_device *dev)
7589{
fac5e23e 7590 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7591
7ff0ebcc 7592 intel_fbc_init(dev_priv);
1fa61106 7593
c921aba8
DV		 7594 /* For cxsr */
7595 if (IS_PINEVIEW(dev))
7596 i915_pineview_get_mem_freq(dev);
7597 else if (IS_GEN5(dev))
7598 i915_ironlake_get_mem_freq(dev);
7599
1fa61106 7600 /* For FIFO watermark updates */
f5ed50cb 7601 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7602 skl_setup_wm_latency(dev);
2d41c0b5 7603 dev_priv->display.update_wm = skl_update_wm;
98d39494 7604 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7605 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7606 ilk_setup_wm_latency(dev);
53615a5e 7607
bd602544
VS		 7608 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7609 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7610 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7611 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7612 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7613 dev_priv->display.compute_intermediate_wm =
7614 ilk_compute_intermediate_wm;
7615 dev_priv->display.initial_watermarks =
7616 ilk_initial_watermarks;
7617 dev_priv->display.optimize_watermarks =
7618 ilk_optimize_watermarks;
bd602544
VS		 7619 } else {
7620 DRM_DEBUG_KMS("Failed to read display plane latency. "
7621 "Disable CxSR\n");
7622 }
a4565da8 7623 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7624 vlv_setup_wm_latency(dev);
262cd2e1 7625 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7626 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7627 vlv_setup_wm_latency(dev);
26e1fe4f 7628 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7629 } else if (IS_PINEVIEW(dev)) {
7630 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7631 dev_priv->is_ddr3,
7632 dev_priv->fsb_freq,
7633 dev_priv->mem_freq)) {
7634 DRM_INFO("failed to find known CxSR latency "
7635 "(found ddr%s fsb freq %d, mem freq %d), "
7636 "disabling CxSR\n",
7637 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7638 dev_priv->fsb_freq, dev_priv->mem_freq);
7639 /* Disable CxSR and never update its watermark again */
5209b1f4 7640 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7641 dev_priv->display.update_wm = NULL;
7642 } else
7643 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7644 } else if (IS_G4X(dev)) {
7645 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7646 } else if (IS_GEN4(dev)) {
7647 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7648 } else if (IS_GEN3(dev)) {
7649 dev_priv->display.update_wm = i9xx_update_wm;
7650 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7651 } else if (IS_GEN2(dev)) {
7652 if (INTEL_INFO(dev)->num_pipes == 1) {
7653 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7654 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7655 } else {
7656 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7657 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7658 }
feb56b93
DV		 7659 } else {
7660 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7661 }
7662}
7663
151a49d0 7664int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7665{
4fc688ce 7666 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7667
3f5582dd
CW		 7668 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7669 * use te fw I915_READ variants to reduce the amount of work
7670 * required when reading/writing.
7671 */
7672
7673 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7674 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7675 return -EAGAIN;
7676 }
7677
3f5582dd
CW		 7678 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7679 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7680 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7681
3f5582dd
CW		 7682 if (intel_wait_for_register_fw(dev_priv,
7683 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7684 500)) {
42c0526c
BW		 7685 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7686 return -ETIMEDOUT;
7687 }
7688
3f5582dd
CW		 7689 *val = I915_READ_FW(GEN6_PCODE_DATA);
7690 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c
BW		 7691
7692 return 0;
7693}
7694
3f5582dd
CW		 7695int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7696 u32 mbox, u32 val)
42c0526c 7697{
4fc688ce 7698 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7699
3f5582dd
CW		 7700 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7701 * use te fw I915_READ variants to reduce the amount of work
7702 * required when reading/writing.
7703 */
7704
7705 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7706 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7707 return -EAGAIN;
7708 }
7709
3f5582dd
CW		 7710 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7711 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7712
3f5582dd
CW		 7713 if (intel_wait_for_register_fw(dev_priv,
7714 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7715 500)) {
42c0526c
BW		 7716 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7717 return -ETIMEDOUT;
7718 }
7719
3f5582dd 7720 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c
BW		 7721
7722 return 0;
7723}
a0e4e199 7724
dd06f88c
VS		 7725static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7726{
c30fec65
VS		 7727 /*
7728 * N = val - 0xb7
7729 * Slow = Fast = GPLL ref * N
7730 */
7731 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7732}
7733
b55dd647 7734static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7735{
c30fec65 7736 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7737}
7738
b55dd647 7739static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7740{
c30fec65
VS		 7741 /*
7742 * N = val / 2
7743 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7744 */
7745 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7746}
7747
b55dd647 7748static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7749{
1c14762d 7750 /* CHV needs even values */
c30fec65 7751 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7752}
7753
616bc820 7754int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7755{
2d1fe073 7756 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7757 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7758 GEN9_FREQ_SCALER);
2d1fe073 7759 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7760 return chv_gpu_freq(dev_priv, val);
2d1fe073 7761 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7762 return byt_gpu_freq(dev_priv, val);
7763 else
7764 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7765}
7766
616bc820
VS		 7767int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7768{
2d1fe073 7769 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7770 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7771 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7772 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7773 return chv_freq_opcode(dev_priv, val);
2d1fe073 7774 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7775 return byt_freq_opcode(dev_priv, val);
7776 else
500a3d2e 7777 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7778}
22b1b2f8 7779
6ad790c0
CW		 7780struct request_boost {
7781 struct work_struct work;
eed29a5b 7782 struct drm_i915_gem_request *req;
6ad790c0
CW		 7783};
7784
7785static void __intel_rps_boost_work(struct work_struct *work)
7786{
7787 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7788 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7789
f69a02c9 7790 if (!i915_gem_request_completed(req))
c033666a 7791 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7792
e8a261ea 7793 i915_gem_request_put(req);
6ad790c0
CW		 7794 kfree(boost);
7795}
7796
91d14251 7797void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7798{
7799 struct request_boost *boost;
7800
91d14251 7801 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7802 return;
7803
f69a02c9 7804 if (i915_gem_request_completed(req))
e61b9958
CW		 7805 return;
7806
6ad790c0
CW		 7807 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7808 if (boost == NULL)
7809 return;
7810
e8a261ea 7811 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7812
7813 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7814 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7815}
7816
f742a552 7817void intel_pm_setup(struct drm_device *dev)
907b28c5 7818{
fac5e23e 7819 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7820
f742a552 7821 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7822 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7823
54b4f68f
CW		 7824 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7825 __intel_autoenable_gt_powersave);
1854d5ca 7826 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7827
33688d95 7828 dev_priv->pm.suspended = false;
1f814dac 7829 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7830 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7831}
Linux kernel - Deliverables
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