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drm/i915: Store the watermark latency values in dev_priv
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
3490ea5d
CW		 46static bool intel_crtc_active(struct drm_crtc *crtc)
47{
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
50 */
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
52}
53
1fa61106 54static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 fbc_ctl;
58
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
62 return;
63
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
66
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
70 return;
71 }
72
73 DRM_DEBUG_KMS("disabled FBC\n");
74}
75
1fa61106 76static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 77{
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84 int cfb_pitch;
85 int plane, i;
86 u32 fbc_ctl, fbc_ctl2;
87
5c3fe8b0 88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
91
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
95
96 /* Clear old tags */
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
99
100 /* Set it up... */
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
102 fbc_ctl2 |= plane;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
105
106 /* enable it... */
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
108 if (IS_I945GM(dev))
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
114
84f44ce7
VS		 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 117}
118
1fa61106 119static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
124}
125
1fa61106 126static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 127{
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
136 u32 dpfc_ctl;
137
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
141
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
146
147 /* enable it... */
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
149
84f44ce7 150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 151}
152
1fa61106 153static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 u32 dpfc_ctl;
157
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
163
164 DRM_DEBUG_KMS("disabled FBC\n");
165 }
166}
167
1fa61106 168static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
173}
174
175static void sandybridge_blit_fbc_update(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 blt_ecoskpd;
179
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
193}
194
1fa61106 195static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 196{
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
205 u32 dpfc_ctl;
206
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
214
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 220 /* enable it... */
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
222
223 if (IS_GEN6(dev)) {
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
228 }
229
84f44ce7 230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 231}
232
1fa61106 233static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 u32 dpfc_ctl;
237
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
243
b74ea102 244 if (IS_IVYBRIDGE(dev))
7dd23ba0 245 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
249
d89f2071 250 if (IS_HASWELL(dev))
7dd23ba0 251 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
255
85208be0
ED		 256 DRM_DEBUG_KMS("disabled FBC\n");
257 }
258}
259
1fa61106 260static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
265}
266
abe959c7
RV		 267static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
268{
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
275
f343c5f6 276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 277
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
281
891348b2 282 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 289 } else {
7dd23ba0 290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 293 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
381 work = kzalloc(sizeof *work, GFP_KERNEL);
382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
f85da868 461 unsigned int max_hdisplay, max_vdisplay;
85208be0 462
29ebf90f
CW		 463 if (!I915_HAS_FBC(dev)) {
464 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 465 return;
29ebf90f 466 }
85208be0 467
29ebf90f
CW		 468 if (!i915_powersave) {
469 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 471 return;
29ebf90f 472 }
85208be0
ED		 473
474 /*
475 * If FBC is already on, we just have to verify that we can
476 * keep it that way...
477 * Need to disable if:
478 * - more than one pipe is active
479 * - changing FBC params (stride, fence, mode)
480 * - new fb is too large to fit in compressed buffer
481 * - going to an unsupported config (interlace, pixel multiply, etc.)
482 */
483 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 484 if (intel_crtc_active(tmp_crtc) &&
485 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 486 if (crtc) {
29ebf90f
CW		 487 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
488 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 489 goto out_disable;
490 }
491 crtc = tmp_crtc;
492 }
493 }
494
495 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 496 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
497 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 498 goto out_disable;
499 }
500
501 intel_crtc = to_intel_crtc(crtc);
502 fb = crtc->fb;
503 intel_fb = to_intel_framebuffer(fb);
504 obj = intel_fb->obj;
505
8a5729a3
DL		 506 if (i915_enable_fbc < 0 &&
507 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
509 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 510 goto out_disable;
85208be0 511 }
8a5729a3 512 if (!i915_enable_fbc) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
514 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 515 goto out_disable;
516 }
85208be0
ED		 517 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
518 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 519 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
520 DRM_DEBUG_KMS("mode incompatible with compression, "
521 "disabling\n");
85208be0
ED		 522 goto out_disable;
523 }
f85da868
PZ		 524
525 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 max_hdisplay = 4096;
527 max_vdisplay = 2048;
528 } else {
529 max_hdisplay = 2048;
530 max_vdisplay = 1536;
531 }
532 if ((crtc->mode.hdisplay > max_hdisplay) ||
533 (crtc->mode.vdisplay > max_vdisplay)) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
535 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 536 goto out_disable;
537 }
891348b2
RV		 538 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
539 intel_crtc->plane != 0) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
541 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 542 goto out_disable;
543 }
544
545 /* The use of a CPU fence is mandatory in order to detect writes
546 * by the CPU to the scanout and trigger updates to the FBC.
547 */
548 if (obj->tiling_mode != I915_TILING_X ||
549 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 550 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
551 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 552 goto out_disable;
553 }
554
555 /* If the kernel debugger is active, always disable compression */
556 if (in_dbg_master())
557 goto out_disable;
558
11be49eb 559 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
561 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 562 goto out_disable;
563 }
564
85208be0
ED		 565 /* If the scanout has not changed, don't modify the FBC settings.
566 * Note that we make the fundamental assumption that the fb->obj
567 * cannot be unpinned (and have its GTT offset and fence revoked)
568 * without first being decoupled from the scanout and FBC disabled.
569 */
5c3fe8b0
BW		 570 if (dev_priv->fbc.plane == intel_crtc->plane &&
571 dev_priv->fbc.fb_id == fb->base.id &&
572 dev_priv->fbc.y == crtc->y)
85208be0
ED		 573 return;
574
575 if (intel_fbc_enabled(dev)) {
576 /* We update FBC along two paths, after changing fb/crtc
577 * configuration (modeswitching) and after page-flipping
578 * finishes. For the latter, we know that not only did
579 * we disable the FBC at the start of the page-flip
580 * sequence, but also more than one vblank has passed.
581 *
582 * For the former case of modeswitching, it is possible
583 * to switch between two FBC valid configurations
584 * instantaneously so we do need to disable the FBC
585 * before we can modify its control registers. We also
586 * have to wait for the next vblank for that to take
587 * effect. However, since we delay enabling FBC we can
588 * assume that a vblank has passed since disabling and
589 * that we can safely alter the registers in the deferred
590 * callback.
591 *
592 * In the scenario that we go from a valid to invalid
593 * and then back to valid FBC configuration we have
594 * no strict enforcement that a vblank occurred since
595 * disabling the FBC. However, along all current pipe
596 * disabling paths we do need to wait for a vblank at
597 * some point. And we wait before enabling FBC anyway.
598 */
599 DRM_DEBUG_KMS("disabling active FBC for update\n");
600 intel_disable_fbc(dev);
601 }
602
603 intel_enable_fbc(crtc, 500);
29ebf90f 604 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 605 return;
606
607out_disable:
608 /* Multiple disables should be harmless */
609 if (intel_fbc_enabled(dev)) {
610 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
611 intel_disable_fbc(dev);
612 }
11be49eb 613 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 614}
615
c921aba8
DV		 616static void i915_pineview_get_mem_freq(struct drm_device *dev)
617{
618 drm_i915_private_t *dev_priv = dev->dev_private;
619 u32 tmp;
620
621 tmp = I915_READ(CLKCFG);
622
623 switch (tmp & CLKCFG_FSB_MASK) {
624 case CLKCFG_FSB_533:
625 dev_priv->fsb_freq = 533; /* 133*4 */
626 break;
627 case CLKCFG_FSB_800:
628 dev_priv->fsb_freq = 800; /* 200*4 */
629 break;
630 case CLKCFG_FSB_667:
631 dev_priv->fsb_freq = 667; /* 167*4 */
632 break;
633 case CLKCFG_FSB_400:
634 dev_priv->fsb_freq = 400; /* 100*4 */
635 break;
636 }
637
638 switch (tmp & CLKCFG_MEM_MASK) {
639 case CLKCFG_MEM_533:
640 dev_priv->mem_freq = 533;
641 break;
642 case CLKCFG_MEM_667:
643 dev_priv->mem_freq = 667;
644 break;
645 case CLKCFG_MEM_800:
646 dev_priv->mem_freq = 800;
647 break;
648 }
649
650 /* detect pineview DDR3 setting */
651 tmp = I915_READ(CSHRDDR3CTL);
652 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
653}
654
655static void i915_ironlake_get_mem_freq(struct drm_device *dev)
656{
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 u16 ddrpll, csipll;
659
660 ddrpll = I915_READ16(DDRMPLL1);
661 csipll = I915_READ16(CSIPLL0);
662
663 switch (ddrpll & 0xff) {
664 case 0xc:
665 dev_priv->mem_freq = 800;
666 break;
667 case 0x10:
668 dev_priv->mem_freq = 1066;
669 break;
670 case 0x14:
671 dev_priv->mem_freq = 1333;
672 break;
673 case 0x18:
674 dev_priv->mem_freq = 1600;
675 break;
676 default:
677 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
678 ddrpll & 0xff);
679 dev_priv->mem_freq = 0;
680 break;
681 }
682
20e4d407 683 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 684
685 switch (csipll & 0x3ff) {
686 case 0x00c:
687 dev_priv->fsb_freq = 3200;
688 break;
689 case 0x00e:
690 dev_priv->fsb_freq = 3733;
691 break;
692 case 0x010:
693 dev_priv->fsb_freq = 4266;
694 break;
695 case 0x012:
696 dev_priv->fsb_freq = 4800;
697 break;
698 case 0x014:
699 dev_priv->fsb_freq = 5333;
700 break;
701 case 0x016:
702 dev_priv->fsb_freq = 5866;
703 break;
704 case 0x018:
705 dev_priv->fsb_freq = 6400;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
709 csipll & 0x3ff);
710 dev_priv->fsb_freq = 0;
711 break;
712 }
713
714 if (dev_priv->fsb_freq == 3200) {
20e4d407 715 dev_priv->ips.c_m = 0;
c921aba8 716 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 717 dev_priv->ips.c_m = 1;
c921aba8 718 } else {
20e4d407 719 dev_priv->ips.c_m = 2;
c921aba8
DV		 720 }
721}
722
b445e3b0
ED		 723static const struct cxsr_latency cxsr_latency_table[] = {
724 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
725 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
726 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
727 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
728 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
729
730 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
731 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
732 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
733 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
734 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
735
736 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
737 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
738 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
739 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
740 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
741
742 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
743 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
744 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
745 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
746 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
747
748 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
749 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
750 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
751 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
752 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
753
754 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
755 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
756 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
757 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
758 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
759};
760
63c62275 761static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 762 int is_ddr3,
763 int fsb,
764 int mem)
765{
766 const struct cxsr_latency *latency;
767 int i;
768
769 if (fsb == 0 || mem == 0)
770 return NULL;
771
772 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
773 latency = &cxsr_latency_table[i];
774 if (is_desktop == latency->is_desktop &&
775 is_ddr3 == latency->is_ddr3 &&
776 fsb == latency->fsb_freq && mem == latency->mem_freq)
777 return latency;
778 }
779
780 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
781
782 return NULL;
783}
784
1fa61106 785static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
788
789 /* deactivate cxsr */
790 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
791}
792
793/*
794 * Latency for FIFO fetches is dependent on several factors:
795 * - memory configuration (speed, channels)
796 * - chipset
797 * - current MCH state
798 * It can be fairly high in some situations, so here we assume a fairly
799 * pessimal value. It's a tradeoff between extra memory fetches (if we
800 * set this value too high, the FIFO will fetch frequently to stay full)
801 * and power consumption (set it too low to save power and we might see
802 * FIFO underruns and display "flicker").
803 *
804 * A value of 5us seems to be a good balance; safe for very low end
805 * platforms but not overly aggressive on lower latency configs.
806 */
807static const int latency_ns = 5000;
808
1fa61106 809static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 uint32_t dsparb = I915_READ(DSPARB);
813 int size;
814
815 size = dsparb & 0x7f;
816 if (plane)
817 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
818
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
821
822 return size;
823}
824
1fa61106 825static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
829 int size;
830
831 size = dsparb & 0x1ff;
832 if (plane)
833 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
834 size >>= 1; /* Convert to cachelines */
835
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A", size);
838
839 return size;
840}
841
1fa61106 842static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 843{
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 uint32_t dsparb = I915_READ(DSPARB);
846 int size;
847
848 size = dsparb & 0x7f;
849 size >>= 2; /* Convert to cachelines */
850
851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 plane ? "B" : "A",
853 size);
854
855 return size;
856}
857
1fa61106 858static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 size >>= 1; /* Convert to cachelines */
866
867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
868 plane ? "B" : "A", size);
869
870 return size;
871}
872
873/* Pineview has different values for various configs */
874static const struct intel_watermark_params pineview_display_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_display_hplloff_wm = {
882 PINEVIEW_DISPLAY_FIFO,
883 PINEVIEW_MAX_WM,
884 PINEVIEW_DFT_HPLLOFF_WM,
885 PINEVIEW_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params pineview_cursor_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE,
894};
895static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
896 PINEVIEW_CURSOR_FIFO,
897 PINEVIEW_CURSOR_MAX_WM,
898 PINEVIEW_CURSOR_DFT_WM,
899 PINEVIEW_CURSOR_GUARD_WM,
900 PINEVIEW_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params g4x_wm_info = {
903 G4X_FIFO_SIZE,
904 G4X_MAX_WM,
905 G4X_MAX_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params g4x_cursor_wm_info = {
910 I965_CURSOR_FIFO,
911 I965_CURSOR_MAX_WM,
912 I965_CURSOR_DFT_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_wm_info = {
917 VALLEYVIEW_FIFO_SIZE,
918 VALLEYVIEW_MAX_WM,
919 VALLEYVIEW_MAX_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params valleyview_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 VALLEYVIEW_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 G4X_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i965_cursor_wm_info = {
931 I965_CURSOR_FIFO,
932 I965_CURSOR_MAX_WM,
933 I965_CURSOR_DFT_WM,
934 2,
935 I915_FIFO_LINE_SIZE,
936};
937static const struct intel_watermark_params i945_wm_info = {
938 I945_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
944static const struct intel_watermark_params i915_wm_info = {
945 I915_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I915_FIFO_LINE_SIZE
950};
951static const struct intel_watermark_params i855_wm_info = {
952 I855GM_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958static const struct intel_watermark_params i830_wm_info = {
959 I830_FIFO_SIZE,
960 I915_MAX_WM,
961 1,
962 2,
963 I830_FIFO_LINE_SIZE
964};
965
966static const struct intel_watermark_params ironlake_display_wm_info = {
967 ILK_DISPLAY_FIFO,
968 ILK_DISPLAY_MAXWM,
969 ILK_DISPLAY_DFTWM,
970 2,
971 ILK_FIFO_LINE_SIZE
972};
973static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 ILK_CURSOR_FIFO,
975 ILK_CURSOR_MAXWM,
976 ILK_CURSOR_DFTWM,
977 2,
978 ILK_FIFO_LINE_SIZE
979};
980static const struct intel_watermark_params ironlake_display_srwm_info = {
981 ILK_DISPLAY_SR_FIFO,
982 ILK_DISPLAY_MAX_SRWM,
983 ILK_DISPLAY_DFT_SRWM,
984 2,
985 ILK_FIFO_LINE_SIZE
986};
987static const struct intel_watermark_params ironlake_cursor_srwm_info = {
988 ILK_CURSOR_SR_FIFO,
989 ILK_CURSOR_MAX_SRWM,
990 ILK_CURSOR_DFT_SRWM,
991 2,
992 ILK_FIFO_LINE_SIZE
993};
994
995static const struct intel_watermark_params sandybridge_display_wm_info = {
996 SNB_DISPLAY_FIFO,
997 SNB_DISPLAY_MAXWM,
998 SNB_DISPLAY_DFTWM,
999 2,
1000 SNB_FIFO_LINE_SIZE
1001};
1002static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 SNB_CURSOR_FIFO,
1004 SNB_CURSOR_MAXWM,
1005 SNB_CURSOR_DFTWM,
1006 2,
1007 SNB_FIFO_LINE_SIZE
1008};
1009static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010 SNB_DISPLAY_SR_FIFO,
1011 SNB_DISPLAY_MAX_SRWM,
1012 SNB_DISPLAY_DFT_SRWM,
1013 2,
1014 SNB_FIFO_LINE_SIZE
1015};
1016static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1017 SNB_CURSOR_SR_FIFO,
1018 SNB_CURSOR_MAX_SRWM,
1019 SNB_CURSOR_DFT_SRWM,
1020 2,
1021 SNB_FIFO_LINE_SIZE
1022};
1023
1024
1025/**
1026 * intel_calculate_wm - calculate watermark level
1027 * @clock_in_khz: pixel clock
1028 * @wm: chip FIFO params
1029 * @pixel_size: display pixel size
1030 * @latency_ns: memory latency for the platform
1031 *
1032 * Calculate the watermark level (the level at which the display plane will
1033 * start fetching from memory again). Each chip has a different display
1034 * FIFO size and allocation, so the caller needs to figure that out and pass
1035 * in the correct intel_watermark_params structure.
1036 *
1037 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038 * on the pixel size. When it reaches the watermark level, it'll start
1039 * fetching FIFO line sized based chunks from memory until the FIFO fills
1040 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1041 * will occur, and a display engine hang could result.
1042 */
1043static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044 const struct intel_watermark_params *wm,
1045 int fifo_size,
1046 int pixel_size,
1047 unsigned long latency_ns)
1048{
1049 long entries_required, wm_size;
1050
1051 /*
1052 * Note: we need to make sure we don't overflow for various clock &
1053 * latency values.
1054 * clocks go from a few thousand to several hundred thousand.
1055 * latency is usually a few thousand
1056 */
1057 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1058 1000;
1059 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1060
1061 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1062
1063 wm_size = fifo_size - (entries_required + wm->guard_size);
1064
1065 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1066
1067 /* Don't promote wm_size to unsigned... */
1068 if (wm_size > (long)wm->max_wm)
1069 wm_size = wm->max_wm;
1070 if (wm_size <= 0)
1071 wm_size = wm->default_wm;
1072 return wm_size;
1073}
1074
1075static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1076{
1077 struct drm_crtc *crtc, *enabled = NULL;
1078
1079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1080 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1081 if (enabled)
1082 return NULL;
1083 enabled = crtc;
1084 }
1085 }
1086
1087 return enabled;
1088}
1089
1fa61106 1090static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1091{
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc;
1094 const struct cxsr_latency *latency;
1095 u32 reg;
1096 unsigned long wm;
1097
1098 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099 dev_priv->fsb_freq, dev_priv->mem_freq);
1100 if (!latency) {
1101 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102 pineview_disable_cxsr(dev);
1103 return;
1104 }
1105
1106 crtc = single_enabled_crtc(dev);
1107 if (crtc) {
1108 int clock = crtc->mode.clock;
1109 int pixel_size = crtc->fb->bits_per_pixel / 8;
1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157}
1158
1159static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167{
1168 struct drm_crtc *crtc;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1174 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
1180 htotal = crtc->mode.htotal;
1181 hdisplay = crtc->mode.hdisplay;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 /* Use the small buffer method to calculate plane watermark */
1186 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1187 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1188 if (tlb_miss > 0)
1189 entries += tlb_miss;
1190 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1191 *plane_wm = entries + display->guard_size;
1192 if (*plane_wm > (int)display->max_wm)
1193 *plane_wm = display->max_wm;
1194
1195 /* Use the large buffer method to calculate cursor watermark */
1196 line_time_us = ((htotal * 1000) / clock);
1197 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1198 entries = line_count * 64 * pixel_size;
1199 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1200 if (tlb_miss > 0)
1201 entries += tlb_miss;
1202 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1203 *cursor_wm = entries + cursor->guard_size;
1204 if (*cursor_wm > (int)cursor->max_wm)
1205 *cursor_wm = (int)cursor->max_wm;
1206
1207 return true;
1208}
1209
1210/*
1211 * Check the wm result.
1212 *
1213 * If any calculated watermark values is larger than the maximum value that
1214 * can be programmed into the associated watermark register, that watermark
1215 * must be disabled.
1216 */
1217static bool g4x_check_srwm(struct drm_device *dev,
1218 int display_wm, int cursor_wm,
1219 const struct intel_watermark_params *display,
1220 const struct intel_watermark_params *cursor)
1221{
1222 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1223 display_wm, cursor_wm);
1224
1225 if (display_wm > display->max_wm) {
1226 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1227 display_wm, display->max_wm);
1228 return false;
1229 }
1230
1231 if (cursor_wm > cursor->max_wm) {
1232 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1233 cursor_wm, cursor->max_wm);
1234 return false;
1235 }
1236
1237 if (!(display_wm || cursor_wm)) {
1238 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1239 return false;
1240 }
1241
1242 return true;
1243}
1244
1245static bool g4x_compute_srwm(struct drm_device *dev,
1246 int plane,
1247 int latency_ns,
1248 const struct intel_watermark_params *display,
1249 const struct intel_watermark_params *cursor,
1250 int *display_wm, int *cursor_wm)
1251{
1252 struct drm_crtc *crtc;
1253 int hdisplay, htotal, pixel_size, clock;
1254 unsigned long line_time_us;
1255 int line_count, line_size;
1256 int small, large;
1257 int entries;
1258
1259 if (!latency_ns) {
1260 *display_wm = *cursor_wm = 0;
1261 return false;
1262 }
1263
1264 crtc = intel_get_crtc_for_plane(dev, plane);
1265 hdisplay = crtc->mode.hdisplay;
1266 htotal = crtc->mode.htotal;
1267 clock = crtc->mode.clock;
1268 pixel_size = crtc->fb->bits_per_pixel / 8;
1269
1270 line_time_us = (htotal * 1000) / clock;
1271 line_count = (latency_ns / line_time_us + 1000) / 1000;
1272 line_size = hdisplay * pixel_size;
1273
1274 /* Use the minimum of the small and large buffer method for primary */
1275 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1276 large = line_count * line_size;
1277
1278 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1279 *display_wm = entries + display->guard_size;
1280
1281 /* calculate the self-refresh watermark for display cursor */
1282 entries = line_count * pixel_size * 64;
1283 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1284 *cursor_wm = entries + cursor->guard_size;
1285
1286 return g4x_check_srwm(dev,
1287 *display_wm, *cursor_wm,
1288 display, cursor);
1289}
1290
1291static bool vlv_compute_drain_latency(struct drm_device *dev,
1292 int plane,
1293 int *plane_prec_mult,
1294 int *plane_dl,
1295 int *cursor_prec_mult,
1296 int *cursor_dl)
1297{
1298 struct drm_crtc *crtc;
1299 int clock, pixel_size;
1300 int entries;
1301
1302 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1303 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1304 return false;
1305
1306 clock = crtc->mode.clock; /* VESA DOT Clock */
1307 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1308
1309 entries = (clock / 1000) * pixel_size;
1310 *plane_prec_mult = (entries > 256) ?
1311 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1312 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1313 pixel_size);
1314
1315 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1316 *cursor_prec_mult = (entries > 256) ?
1317 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1318 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1319
1320 return true;
1321}
1322
1323/*
1324 * Update drain latency registers of memory arbiter
1325 *
1326 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1327 * to be programmed. Each plane has a drain latency multiplier and a drain
1328 * latency value.
1329 */
1330
1331static void vlv_update_drain_latency(struct drm_device *dev)
1332{
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1335 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1336 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1337 either 16 or 32 */
1338
1339 /* For plane A, Cursor A */
1340 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1341 &cursor_prec_mult, &cursora_dl)) {
1342 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1344 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1346
1347 I915_WRITE(VLV_DDL1, cursora_prec |
1348 (cursora_dl << DDL_CURSORA_SHIFT) |
1349 planea_prec | planea_dl);
1350 }
1351
1352 /* For plane B, Cursor B */
1353 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1354 &cursor_prec_mult, &cursorb_dl)) {
1355 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1357 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1359
1360 I915_WRITE(VLV_DDL2, cursorb_prec |
1361 (cursorb_dl << DDL_CURSORB_SHIFT) |
1362 planeb_prec | planeb_dl);
1363 }
1364}
1365
1366#define single_plane_enabled(mask) is_power_of_2(mask)
1367
1fa61106 1368static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1369{
1370 static const int sr_latency_ns = 12000;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373 int plane_sr, cursor_sr;
af6c4575 1374 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1375 unsigned int enabled = 0;
1376
1377 vlv_update_drain_latency(dev);
1378
51cea1f4 1379 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1380 &valleyview_wm_info, latency_ns,
1381 &valleyview_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
51cea1f4 1383 enabled |= 1 << PIPE_A;
b445e3b0 1384
51cea1f4 1385 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1386 &valleyview_wm_info, latency_ns,
1387 &valleyview_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
51cea1f4 1389 enabled |= 1 << PIPE_B;
b445e3b0 1390
b445e3b0
ED		 1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1393 sr_latency_ns,
1394 &valleyview_wm_info,
1395 &valleyview_cursor_wm_info,
af6c4575
CW		 1396 &plane_sr, &ignore_cursor_sr) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 2*sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
52bd02d8 1401 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1402 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1403 } else {
b445e3b0
ED		 1404 I915_WRITE(FW_BLC_SELF_VLV,
1405 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1406 plane_sr = cursor_sr = 0;
1407 }
b445e3b0
ED		 1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1413
1414 I915_WRITE(DSPFW1,
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418 planea_wm);
1419 I915_WRITE(DSPFW2,
8c919b28 1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1422 I915_WRITE(DSPFW3,
8c919b28
CW		 1423 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1425}
1426
1fa61106 1427static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1428{
1429 static const int sr_latency_ns = 12000;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1432 int plane_sr, cursor_sr;
1433 unsigned int enabled = 0;
1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1436 &g4x_wm_info, latency_ns,
1437 &g4x_cursor_wm_info, latency_ns,
1438 &planea_wm, &cursora_wm))
51cea1f4 1439 enabled |= 1 << PIPE_A;
b445e3b0 1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planeb_wm, &cursorb_wm))
51cea1f4 1445 enabled |= 1 << PIPE_B;
b445e3b0 1446
b445e3b0
ED		 1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1449 sr_latency_ns,
1450 &g4x_wm_info,
1451 &g4x_cursor_wm_info,
52bd02d8 1452 &plane_sr, &cursor_sr)) {
b445e3b0 1453 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1454 } else {
b445e3b0
ED		 1455 I915_WRITE(FW_BLC_SELF,
1456 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1457 plane_sr = cursor_sr = 0;
1458 }
b445e3b0
ED		 1459
1460 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1461 planea_wm, cursora_wm,
1462 planeb_wm, cursorb_wm,
1463 plane_sr, cursor_sr);
1464
1465 I915_WRITE(DSPFW1,
1466 (plane_sr << DSPFW_SR_SHIFT) |
1467 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1468 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1469 planea_wm);
1470 I915_WRITE(DSPFW2,
8c919b28 1471 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1472 (cursora_wm << DSPFW_CURSORA_SHIFT));
1473 /* HPLL off in SR has some issues on G4x... disable it */
1474 I915_WRITE(DSPFW3,
8c919b28 1475 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1476 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1477}
1478
1fa61106 1479static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct drm_crtc *crtc;
1483 int srwm = 1;
1484 int cursor_sr = 16;
1485
1486 /* Calc sr entries for one plane configs */
1487 crtc = single_enabled_crtc(dev);
1488 if (crtc) {
1489 /* self-refresh has much higher latency */
1490 static const int sr_latency_ns = 12000;
1491 int clock = crtc->mode.clock;
1492 int htotal = crtc->mode.htotal;
1493 int hdisplay = crtc->mode.hdisplay;
1494 int pixel_size = crtc->fb->bits_per_pixel / 8;
1495 unsigned long line_time_us;
1496 int entries;
1497
1498 line_time_us = ((htotal * 1000) / clock);
1499
1500 /* Use ns/us then divide to preserve precision */
1501 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1502 pixel_size * hdisplay;
1503 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1504 srwm = I965_FIFO_SIZE - entries;
1505 if (srwm < 0)
1506 srwm = 1;
1507 srwm &= 0x1ff;
1508 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1509 entries, srwm);
1510
1511 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1512 pixel_size * 64;
1513 entries = DIV_ROUND_UP(entries,
1514 i965_cursor_wm_info.cacheline_size);
1515 cursor_sr = i965_cursor_wm_info.fifo_size -
1516 (entries + i965_cursor_wm_info.guard_size);
1517
1518 if (cursor_sr > i965_cursor_wm_info.max_wm)
1519 cursor_sr = i965_cursor_wm_info.max_wm;
1520
1521 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1522 "cursor %d\n", srwm, cursor_sr);
1523
1524 if (IS_CRESTLINE(dev))
1525 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1526 } else {
1527 /* Turn off self refresh if both pipes are enabled */
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1530 & ~FW_BLC_SELF_EN);
1531 }
1532
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1534 srwm);
1535
1536 /* 965 has limitations... */
1537 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1538 (8 << 16) | (8 << 8) | (8 << 0));
1539 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1540 /* update cursor SR watermark */
1541 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1542}
1543
1fa61106 1544static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1545{
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 const struct intel_watermark_params *wm_info;
1548 uint32_t fwater_lo;
1549 uint32_t fwater_hi;
1550 int cwm, srwm = 1;
1551 int fifo_size;
1552 int planea_wm, planeb_wm;
1553 struct drm_crtc *crtc, *enabled = NULL;
1554
1555 if (IS_I945GM(dev))
1556 wm_info = &i945_wm_info;
1557 else if (!IS_GEN2(dev))
1558 wm_info = &i915_wm_info;
1559 else
1560 wm_info = &i855_wm_info;
1561
1562 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1563 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1564 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1565 int cpp = crtc->fb->bits_per_pixel / 8;
1566 if (IS_GEN2(dev))
1567 cpp = 4;
1568
b445e3b0 1569 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
b445e3b0
ED		 1571 latency_ns);
1572 enabled = crtc;
1573 } else
1574 planea_wm = fifo_size - wm_info->guard_size;
1575
1576 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1577 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1578 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1579 int cpp = crtc->fb->bits_per_pixel / 8;
1580 if (IS_GEN2(dev))
1581 cpp = 4;
1582
b445e3b0 1583 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1584 wm_info, fifo_size, cpp,
b445e3b0
ED		 1585 latency_ns);
1586 if (enabled == NULL)
1587 enabled = crtc;
1588 else
1589 enabled = NULL;
1590 } else
1591 planeb_wm = fifo_size - wm_info->guard_size;
1592
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1594
1595 /*
1596 * Overlay gets an aggressive default since video jitter is bad.
1597 */
1598 cwm = 2;
1599
1600 /* Play safe and disable self-refresh before adjusting watermarks. */
1601 if (IS_I945G(dev) || IS_I945GM(dev))
1602 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1603 else if (IS_I915GM(dev))
1604 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1605
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 int clock = enabled->mode.clock;
1611 int htotal = enabled->mode.htotal;
1612 int hdisplay = enabled->mode.hdisplay;
1613 int pixel_size = enabled->fb->bits_per_pixel / 8;
1614 unsigned long line_time_us;
1615 int entries;
1616
1617 line_time_us = (htotal * 1000) / clock;
1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621 pixel_size * hdisplay;
1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
1628 if (IS_I945G(dev) || IS_I945GM(dev))
1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631 else if (IS_I915GM(dev))
1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
1648 if (HAS_FW_BLC(dev)) {
1649 if (enabled) {
1650 if (IS_I945G(dev) || IS_I945GM(dev))
1651 I915_WRITE(FW_BLC_SELF,
1652 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1653 else if (IS_I915GM(dev))
1654 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1655 DRM_DEBUG_KMS("memory self refresh enabled\n");
1656 } else
1657 DRM_DEBUG_KMS("memory self refresh disabled\n");
1658 }
1659}
1660
1fa61106 1661static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct drm_crtc *crtc;
1665 uint32_t fwater_lo;
1666 int planea_wm;
1667
1668 crtc = single_enabled_crtc(dev);
1669 if (crtc == NULL)
1670 return;
1671
1672 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1673 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1674 4, latency_ns);
b445e3b0
ED		 1675 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1676 fwater_lo |= (3<<8) | planea_wm;
1677
1678 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1679
1680 I915_WRITE(FW_BLC, fwater_lo);
1681}
1682
1683#define ILK_LP0_PLANE_LATENCY 700
1684#define ILK_LP0_CURSOR_LATENCY 1300
1685
1686/*
1687 * Check the wm result.
1688 *
1689 * If any calculated watermark values is larger than the maximum value that
1690 * can be programmed into the associated watermark register, that watermark
1691 * must be disabled.
1692 */
1693static bool ironlake_check_srwm(struct drm_device *dev, int level,
1694 int fbc_wm, int display_wm, int cursor_wm,
1695 const struct intel_watermark_params *display,
1696 const struct intel_watermark_params *cursor)
1697{
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1701 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1702
1703 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1704 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1705 fbc_wm, SNB_FBC_MAX_SRWM, level);
1706
1707 /* fbc has it's own way to disable FBC WM */
1708 I915_WRITE(DISP_ARB_CTL,
1709 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1710 return false;
615aaa5f
VS		 1711 } else if (INTEL_INFO(dev)->gen >= 6) {
1712 /* enable FBC WM (except on ILK, where it must remain off) */
1713 I915_WRITE(DISP_ARB_CTL,
1714 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1715 }
1716
1717 if (display_wm > display->max_wm) {
1718 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1719 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1720 return false;
1721 }
1722
1723 if (cursor_wm > cursor->max_wm) {
1724 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1725 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1726 return false;
1727 }
1728
1729 if (!(fbc_wm || display_wm || cursor_wm)) {
1730 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1731 return false;
1732 }
1733
1734 return true;
1735}
1736
1737/*
1738 * Compute watermark values of WM[1-3],
1739 */
1740static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1741 int latency_ns,
1742 const struct intel_watermark_params *display,
1743 const struct intel_watermark_params *cursor,
1744 int *fbc_wm, int *display_wm, int *cursor_wm)
1745{
1746 struct drm_crtc *crtc;
1747 unsigned long line_time_us;
1748 int hdisplay, htotal, pixel_size, clock;
1749 int line_count, line_size;
1750 int small, large;
1751 int entries;
1752
1753 if (!latency_ns) {
1754 *fbc_wm = *display_wm = *cursor_wm = 0;
1755 return false;
1756 }
1757
1758 crtc = intel_get_crtc_for_plane(dev, plane);
1759 hdisplay = crtc->mode.hdisplay;
1760 htotal = crtc->mode.htotal;
1761 clock = crtc->mode.clock;
1762 pixel_size = crtc->fb->bits_per_pixel / 8;
1763
1764 line_time_us = (htotal * 1000) / clock;
1765 line_count = (latency_ns / line_time_us + 1000) / 1000;
1766 line_size = hdisplay * pixel_size;
1767
1768 /* Use the minimum of the small and large buffer method for primary */
1769 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1770 large = line_count * line_size;
1771
1772 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1773 *display_wm = entries + display->guard_size;
1774
1775 /*
1776 * Spec says:
1777 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1778 */
1779 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1780
1781 /* calculate the self-refresh watermark for display cursor */
1782 entries = line_count * pixel_size * 64;
1783 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1784 *cursor_wm = entries + cursor->guard_size;
1785
1786 return ironlake_check_srwm(dev, level,
1787 *fbc_wm, *display_wm, *cursor_wm,
1788 display, cursor);
1789}
1790
1fa61106 1791static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1792{
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 int fbc_wm, plane_wm, cursor_wm;
1795 unsigned int enabled;
1796
1797 enabled = 0;
51cea1f4 1798 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1799 &ironlake_display_wm_info,
1800 ILK_LP0_PLANE_LATENCY,
1801 &ironlake_cursor_wm_info,
1802 ILK_LP0_CURSOR_LATENCY,
1803 &plane_wm, &cursor_wm)) {
1804 I915_WRITE(WM0_PIPEA_ILK,
1805 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1806 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1807 " plane %d, " "cursor: %d\n",
1808 plane_wm, cursor_wm);
51cea1f4 1809 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1810 }
1811
51cea1f4 1812 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1813 &ironlake_display_wm_info,
1814 ILK_LP0_PLANE_LATENCY,
1815 &ironlake_cursor_wm_info,
1816 ILK_LP0_CURSOR_LATENCY,
1817 &plane_wm, &cursor_wm)) {
1818 I915_WRITE(WM0_PIPEB_ILK,
1819 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1820 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1821 " plane %d, cursor: %d\n",
1822 plane_wm, cursor_wm);
51cea1f4 1823 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1824 }
1825
1826 /*
1827 * Calculate and update the self-refresh watermark only when one
1828 * display plane is used.
1829 */
1830 I915_WRITE(WM3_LP_ILK, 0);
1831 I915_WRITE(WM2_LP_ILK, 0);
1832 I915_WRITE(WM1_LP_ILK, 0);
1833
1834 if (!single_plane_enabled(enabled))
1835 return;
1836 enabled = ffs(enabled) - 1;
1837
1838 /* WM1 */
1839 if (!ironlake_compute_srwm(dev, 1, enabled,
1840 ILK_READ_WM1_LATENCY() * 500,
1841 &ironlake_display_srwm_info,
1842 &ironlake_cursor_srwm_info,
1843 &fbc_wm, &plane_wm, &cursor_wm))
1844 return;
1845
1846 I915_WRITE(WM1_LP_ILK,
1847 WM1_LP_SR_EN |
1848 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1849 (fbc_wm << WM1_LP_FBC_SHIFT) |
1850 (plane_wm << WM1_LP_SR_SHIFT) |
1851 cursor_wm);
1852
1853 /* WM2 */
1854 if (!ironlake_compute_srwm(dev, 2, enabled,
1855 ILK_READ_WM2_LATENCY() * 500,
1856 &ironlake_display_srwm_info,
1857 &ironlake_cursor_srwm_info,
1858 &fbc_wm, &plane_wm, &cursor_wm))
1859 return;
1860
1861 I915_WRITE(WM2_LP_ILK,
1862 WM2_LP_EN |
1863 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1864 (fbc_wm << WM1_LP_FBC_SHIFT) |
1865 (plane_wm << WM1_LP_SR_SHIFT) |
1866 cursor_wm);
1867
1868 /*
1869 * WM3 is unsupported on ILK, probably because we don't have latency
1870 * data for that power state
1871 */
1872}
1873
1fa61106 1874static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1875{
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1878 u32 val;
1879 int fbc_wm, plane_wm, cursor_wm;
1880 unsigned int enabled;
1881
1882 enabled = 0;
51cea1f4 1883 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1884 &sandybridge_display_wm_info, latency,
1885 &sandybridge_cursor_wm_info, latency,
1886 &plane_wm, &cursor_wm)) {
1887 val = I915_READ(WM0_PIPEA_ILK);
1888 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1889 I915_WRITE(WM0_PIPEA_ILK, val |
1890 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1891 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1892 " plane %d, " "cursor: %d\n",
1893 plane_wm, cursor_wm);
51cea1f4 1894 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1895 }
1896
51cea1f4 1897 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1898 &sandybridge_display_wm_info, latency,
1899 &sandybridge_cursor_wm_info, latency,
1900 &plane_wm, &cursor_wm)) {
1901 val = I915_READ(WM0_PIPEB_ILK);
1902 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1903 I915_WRITE(WM0_PIPEB_ILK, val |
1904 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1905 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1906 " plane %d, cursor: %d\n",
1907 plane_wm, cursor_wm);
51cea1f4 1908 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1909 }
1910
c43d0188
CW		 1911 /*
1912 * Calculate and update the self-refresh watermark only when one
1913 * display plane is used.
1914 *
1915 * SNB support 3 levels of watermark.
1916 *
1917 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1918 * and disabled in the descending order
1919 *
1920 */
1921 I915_WRITE(WM3_LP_ILK, 0);
1922 I915_WRITE(WM2_LP_ILK, 0);
1923 I915_WRITE(WM1_LP_ILK, 0);
1924
1925 if (!single_plane_enabled(enabled) ||
1926 dev_priv->sprite_scaling_enabled)
1927 return;
1928 enabled = ffs(enabled) - 1;
1929
1930 /* WM1 */
1931 if (!ironlake_compute_srwm(dev, 1, enabled,
1932 SNB_READ_WM1_LATENCY() * 500,
1933 &sandybridge_display_srwm_info,
1934 &sandybridge_cursor_srwm_info,
1935 &fbc_wm, &plane_wm, &cursor_wm))
1936 return;
1937
1938 I915_WRITE(WM1_LP_ILK,
1939 WM1_LP_SR_EN |
1940 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1941 (fbc_wm << WM1_LP_FBC_SHIFT) |
1942 (plane_wm << WM1_LP_SR_SHIFT) |
1943 cursor_wm);
1944
1945 /* WM2 */
1946 if (!ironlake_compute_srwm(dev, 2, enabled,
1947 SNB_READ_WM2_LATENCY() * 500,
1948 &sandybridge_display_srwm_info,
1949 &sandybridge_cursor_srwm_info,
1950 &fbc_wm, &plane_wm, &cursor_wm))
1951 return;
1952
1953 I915_WRITE(WM2_LP_ILK,
1954 WM2_LP_EN |
1955 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1956 (fbc_wm << WM1_LP_FBC_SHIFT) |
1957 (plane_wm << WM1_LP_SR_SHIFT) |
1958 cursor_wm);
1959
1960 /* WM3 */
1961 if (!ironlake_compute_srwm(dev, 3, enabled,
1962 SNB_READ_WM3_LATENCY() * 500,
1963 &sandybridge_display_srwm_info,
1964 &sandybridge_cursor_srwm_info,
1965 &fbc_wm, &plane_wm, &cursor_wm))
1966 return;
1967
1968 I915_WRITE(WM3_LP_ILK,
1969 WM3_LP_EN |
1970 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1971 (fbc_wm << WM1_LP_FBC_SHIFT) |
1972 (plane_wm << WM1_LP_SR_SHIFT) |
1973 cursor_wm);
1974}
1975
1976static void ivybridge_update_wm(struct drm_device *dev)
1977{
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1980 u32 val;
1981 int fbc_wm, plane_wm, cursor_wm;
1982 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1983 unsigned int enabled;
1984
1985 enabled = 0;
51cea1f4 1986 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1987 &sandybridge_display_wm_info, latency,
1988 &sandybridge_cursor_wm_info, latency,
1989 &plane_wm, &cursor_wm)) {
1990 val = I915_READ(WM0_PIPEA_ILK);
1991 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1992 I915_WRITE(WM0_PIPEA_ILK, val |
1993 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1994 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1995 " plane %d, " "cursor: %d\n",
1996 plane_wm, cursor_wm);
51cea1f4 1997 enabled |= 1 << PIPE_A;
c43d0188
CW		 1998 }
1999
51cea1f4 2000 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2001 &sandybridge_display_wm_info, latency,
2002 &sandybridge_cursor_wm_info, latency,
2003 &plane_wm, &cursor_wm)) {
2004 val = I915_READ(WM0_PIPEB_ILK);
2005 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2006 I915_WRITE(WM0_PIPEB_ILK, val |
2007 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2008 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2009 " plane %d, cursor: %d\n",
2010 plane_wm, cursor_wm);
51cea1f4 2011 enabled |= 1 << PIPE_B;
c43d0188
CW		 2012 }
2013
51cea1f4 2014 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2015 &sandybridge_display_wm_info, latency,
2016 &sandybridge_cursor_wm_info, latency,
2017 &plane_wm, &cursor_wm)) {
2018 val = I915_READ(WM0_PIPEC_IVB);
2019 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2020 I915_WRITE(WM0_PIPEC_IVB, val |
2021 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2022 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2023 " plane %d, cursor: %d\n",
2024 plane_wm, cursor_wm);
51cea1f4 2025 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2026 }
2027
2028 /*
2029 * Calculate and update the self-refresh watermark only when one
2030 * display plane is used.
2031 *
2032 * SNB support 3 levels of watermark.
2033 *
2034 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2035 * and disabled in the descending order
2036 *
2037 */
2038 I915_WRITE(WM3_LP_ILK, 0);
2039 I915_WRITE(WM2_LP_ILK, 0);
2040 I915_WRITE(WM1_LP_ILK, 0);
2041
2042 if (!single_plane_enabled(enabled) ||
2043 dev_priv->sprite_scaling_enabled)
2044 return;
2045 enabled = ffs(enabled) - 1;
2046
2047 /* WM1 */
2048 if (!ironlake_compute_srwm(dev, 1, enabled,
2049 SNB_READ_WM1_LATENCY() * 500,
2050 &sandybridge_display_srwm_info,
2051 &sandybridge_cursor_srwm_info,
2052 &fbc_wm, &plane_wm, &cursor_wm))
2053 return;
2054
2055 I915_WRITE(WM1_LP_ILK,
2056 WM1_LP_SR_EN |
2057 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2058 (fbc_wm << WM1_LP_FBC_SHIFT) |
2059 (plane_wm << WM1_LP_SR_SHIFT) |
2060 cursor_wm);
2061
2062 /* WM2 */
2063 if (!ironlake_compute_srwm(dev, 2, enabled,
2064 SNB_READ_WM2_LATENCY() * 500,
2065 &sandybridge_display_srwm_info,
2066 &sandybridge_cursor_srwm_info,
2067 &fbc_wm, &plane_wm, &cursor_wm))
2068 return;
2069
2070 I915_WRITE(WM2_LP_ILK,
2071 WM2_LP_EN |
2072 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2073 (fbc_wm << WM1_LP_FBC_SHIFT) |
2074 (plane_wm << WM1_LP_SR_SHIFT) |
2075 cursor_wm);
2076
c43d0188 2077 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2078 if (!ironlake_compute_srwm(dev, 3, enabled,
2079 SNB_READ_WM3_LATENCY() * 500,
2080 &sandybridge_display_srwm_info,
2081 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2082 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2083 !ironlake_compute_srwm(dev, 3, enabled,
2084 2 * SNB_READ_WM3_LATENCY() * 500,
2085 &sandybridge_display_srwm_info,
2086 &sandybridge_cursor_srwm_info,
2087 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2088 return;
2089
2090 I915_WRITE(WM3_LP_ILK,
2091 WM3_LP_EN |
2092 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2093 (fbc_wm << WM1_LP_FBC_SHIFT) |
2094 (plane_wm << WM1_LP_SR_SHIFT) |
2095 cursor_wm);
2096}
2097
3658729a
VS		 2098static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2099 struct drm_crtc *crtc)
801bcfff
PZ		 2100{
2101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2102 uint32_t pixel_rate, pfit_size;
2103
ff9a6750 2104 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2105
2106 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2107 * adjust the pixel_rate here. */
2108
2109 pfit_size = intel_crtc->config.pch_pfit.size;
2110 if (pfit_size) {
2111 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2112
2113 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2114 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2115 pfit_w = (pfit_size >> 16) & 0xFFFF;
2116 pfit_h = pfit_size & 0xFFFF;
2117 if (pipe_w < pfit_w)
2118 pipe_w = pfit_w;
2119 if (pipe_h < pfit_h)
2120 pipe_h = pfit_h;
2121
2122 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2123 pfit_w * pfit_h);
2124 }
2125
2126 return pixel_rate;
2127}
2128
23297044 2129static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2130 uint32_t latency)
2131{
2132 uint64_t ret;
2133
2134 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2135 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2136
2137 return ret;
2138}
2139
23297044 2140static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2141 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2142 uint32_t latency)
2143{
2144 uint32_t ret;
2145
2146 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2147 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2148 ret = DIV_ROUND_UP(ret, 64) + 2;
2149 return ret;
2150}
2151
23297044 2152static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2153 uint8_t bytes_per_pixel)
2154{
2155 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2156}
2157
801bcfff
PZ		 2158struct hsw_pipe_wm_parameters {
2159 bool active;
2160 bool sprite_enabled;
2161 uint8_t pri_bytes_per_pixel;
2162 uint8_t spr_bytes_per_pixel;
2163 uint8_t cur_bytes_per_pixel;
2164 uint32_t pri_horiz_pixels;
2165 uint32_t spr_horiz_pixels;
2166 uint32_t cur_horiz_pixels;
2167 uint32_t pipe_htotal;
2168 uint32_t pixel_rate;
2169};
2170
cca32e9a
PZ		 2171struct hsw_wm_maximums {
2172 uint16_t pri;
2173 uint16_t spr;
2174 uint16_t cur;
2175 uint16_t fbc;
2176};
2177
2178struct hsw_lp_wm_result {
2179 bool enable;
2180 bool fbc_enable;
2181 uint32_t pri_val;
2182 uint32_t spr_val;
2183 uint32_t cur_val;
2184 uint32_t fbc_val;
2185};
2186
801bcfff
PZ		 2187struct hsw_wm_values {
2188 uint32_t wm_pipe[3];
2189 uint32_t wm_lp[3];
2190 uint32_t wm_lp_spr[3];
2191 uint32_t wm_linetime[3];
cca32e9a 2192 bool enable_fbc_wm;
801bcfff
PZ		 2193};
2194
2195enum hsw_data_buf_partitioning {
2196 HSW_DATA_BUF_PART_1_2,
2197 HSW_DATA_BUF_PART_5_6,
2198};
2199
cca32e9a 2200/* For both WM_PIPE and WM_LP. */
23297044 2201static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2202 uint32_t mem_value,
2203 bool is_lp)
801bcfff 2204{
cca32e9a
PZ		 2205 uint32_t method1, method2;
2206
801bcfff
PZ		 2207 /* TODO: for now, assume the primary plane is always enabled. */
2208 if (!params->active)
2209 return 0;
2210
23297044 2211 method1 = ilk_wm_method1(params->pixel_rate,
cca32e9a
PZ		 2212 params->pri_bytes_per_pixel,
2213 mem_value);
2214
2215 if (!is_lp)
2216 return method1;
2217
23297044 2218 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a
PZ		 2219 params->pipe_htotal,
2220 params->pri_horiz_pixels,
2221 params->pri_bytes_per_pixel,
2222 mem_value);
2223
2224 return min(method1, method2);
801bcfff
PZ		 2225}
2226
2227/* For both WM_PIPE and WM_LP. */
23297044 2228static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2229 uint32_t mem_value)
2230{
2231 uint32_t method1, method2;
2232
2233 if (!params->active || !params->sprite_enabled)
2234 return 0;
2235
23297044 2236 method1 = ilk_wm_method1(params->pixel_rate,
801bcfff
PZ		 2237 params->spr_bytes_per_pixel,
2238 mem_value);
23297044 2239 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff
PZ		 2240 params->pipe_htotal,
2241 params->spr_horiz_pixels,
2242 params->spr_bytes_per_pixel,
2243 mem_value);
2244 return min(method1, method2);
2245}
2246
2247/* For both WM_PIPE and WM_LP. */
23297044 2248static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2249 uint32_t mem_value)
2250{
2251 if (!params->active)
2252 return 0;
2253
23297044 2254 return ilk_wm_method2(params->pixel_rate,
801bcfff
PZ		 2255 params->pipe_htotal,
2256 params->cur_horiz_pixels,
2257 params->cur_bytes_per_pixel,
2258 mem_value);
2259}
2260
cca32e9a 2261/* Only for WM_LP. */
23297044 2262static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
1fda9882 2263 uint32_t pri_val)
cca32e9a
PZ		 2264{
2265 if (!params->active)
2266 return 0;
2267
23297044 2268 return ilk_wm_fbc(pri_val,
cca32e9a
PZ		 2269 params->pri_horiz_pixels,
2270 params->pri_bytes_per_pixel);
2271}
2272
2273static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2274 struct hsw_pipe_wm_parameters *params,
2275 struct hsw_lp_wm_result *result)
2276{
2277 enum pipe pipe;
2278 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2279
2280 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2281 struct hsw_pipe_wm_parameters *p = &params[pipe];
2282
23297044
VS		 2283 pri_val[pipe] = ilk_compute_pri_wm(p, mem_value, true);
2284 spr_val[pipe] = ilk_compute_spr_wm(p, mem_value);
2285 cur_val[pipe] = ilk_compute_cur_wm(p, mem_value);
1fda9882 2286 fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
cca32e9a
PZ		 2287 }
2288
2289 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2290 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2291 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2292 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2293
2294 if (result->fbc_val > max->fbc) {
2295 result->fbc_enable = false;
2296 result->fbc_val = 0;
2297 } else {
2298 result->fbc_enable = true;
2299 }
2300
2301 result->enable = result->pri_val <= max->pri &&
2302 result->spr_val <= max->spr &&
2303 result->cur_val <= max->cur;
2304 return result->enable;
2305}
2306
801bcfff
PZ		 2307static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2308 uint32_t mem_value, enum pipe pipe,
2309 struct hsw_pipe_wm_parameters *params)
2310{
2311 uint32_t pri_val, cur_val, spr_val;
2312
23297044
VS		 2313 pri_val = ilk_compute_pri_wm(params, mem_value, false);
2314 spr_val = ilk_compute_spr_wm(params, mem_value);
2315 cur_val = ilk_compute_cur_wm(params, mem_value);
801bcfff
PZ		 2316
2317 WARN(pri_val > 127,
2318 "Primary WM error, mode not supported for pipe %c\n",
2319 pipe_name(pipe));
2320 WARN(spr_val > 127,
2321 "Sprite WM error, mode not supported for pipe %c\n",
2322 pipe_name(pipe));
2323 WARN(cur_val > 63,
2324 "Cursor WM error, mode not supported for pipe %c\n",
2325 pipe_name(pipe));
2326
2327 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2328 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2329 cur_val;
2330}
2331
2332static uint32_t
2333hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2334{
2335 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2337 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2338 u32 linetime, ips_linetime;
1f8eeabf 2339
801bcfff
PZ		 2340 if (!intel_crtc_active(crtc))
2341 return 0;
1011d8c4 2342
1f8eeabf
ED		 2343 /* The WM are computed with base on how long it takes to fill a single
2344 * row at the given clock rate, multiplied by 8.
2345 * */
85a02deb
PZ		 2346 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2347 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2348 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2349
801bcfff
PZ		 2350 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2351 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2352}
2353
12b134df
VS		 2354static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2355{
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357
2358 if (IS_HASWELL(dev)) {
2359 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2360
2361 wm[0] = (sskpd >> 56) & 0xFF;
2362 if (wm[0] == 0)
2363 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2364 wm[1] = (sskpd >> 4) & 0xFF;
2365 wm[2] = (sskpd >> 12) & 0xFF;
2366 wm[3] = (sskpd >> 20) & 0x1FF;
2367 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2368 } else if (INTEL_INFO(dev)->gen >= 6) {
2369 uint32_t sskpd = I915_READ(MCH_SSKPD);
2370
2371 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2372 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2373 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2374 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2375 } else if (INTEL_INFO(dev)->gen >= 5) {
2376 uint32_t mltr = I915_READ(MLTR_ILK);
2377
2378 /* ILK primary LP0 latency is 700 ns */
2379 wm[0] = 7;
2380 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2381 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2382 }
2383}
2384
53615a5e
VS		 2385static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2386{
2387 /* ILK sprite LP0 latency is 1300 ns */
2388 if (INTEL_INFO(dev)->gen == 5)
2389 wm[0] = 13;
2390}
2391
2392static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2393{
2394 /* ILK cursor LP0 latency is 1300 ns */
2395 if (INTEL_INFO(dev)->gen == 5)
2396 wm[0] = 13;
2397
2398 /* WaDoubleCursorLP3Latency:ivb */
2399 if (IS_IVYBRIDGE(dev))
2400 wm[3] *= 2;
2401}
2402
2403static void intel_setup_wm_latency(struct drm_device *dev)
2404{
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406
2407 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2408
2409 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2410 sizeof(dev_priv->wm.pri_latency));
2411 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2412 sizeof(dev_priv->wm.pri_latency));
2413
2414 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2415 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2416}
2417
801bcfff
PZ		 2418static void hsw_compute_wm_parameters(struct drm_device *dev,
2419 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2420 struct hsw_wm_maximums *lp_max_1_2,
2421 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2422{
1011d8c4 2423 struct drm_crtc *crtc;
801bcfff 2424 struct drm_plane *plane;
1011d8c4 2425 enum pipe pipe;
cca32e9a 2426 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2427
801bcfff
PZ		 2428 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 struct hsw_pipe_wm_parameters *p;
2431
2432 pipe = intel_crtc->pipe;
2433 p = &params[pipe];
2434
2435 p->active = intel_crtc_active(crtc);
2436 if (!p->active)
2437 continue;
2438
cca32e9a
PZ		 2439 pipes_active++;
2440
801bcfff 2441 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2442 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
801bcfff
PZ		 2443 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2444 p->cur_bytes_per_pixel = 4;
2445 p->pri_horiz_pixels =
2446 intel_crtc->config.requested_mode.hdisplay;
2447 p->cur_horiz_pixels = 64;
2448 }
2449
2450 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2451 struct intel_plane *intel_plane = to_intel_plane(plane);
2452 struct hsw_pipe_wm_parameters *p;
2453
2454 pipe = intel_plane->pipe;
2455 p = &params[pipe];
2456
bdd57d03 2457 p->sprite_enabled = intel_plane->wm.enabled;
801bcfff
PZ		 2458 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2459 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2460
2461 if (p->sprite_enabled)
2462 sprites_enabled++;
2463 }
2464
2465 if (pipes_active > 1) {
861f3389
PZ		 2466 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2467 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2468 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2469 } else {
2470 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2471 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2472 lp_max_1_2->spr = 384;
861f3389
PZ		 2473 lp_max_5_6->spr = 640;
2474 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2475 }
861f3389 2476 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2477}
2478
2479static void hsw_compute_wm_results(struct drm_device *dev,
2480 struct hsw_pipe_wm_parameters *params,
888fd159 2481 uint16_t *wm,
cca32e9a 2482 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2483 struct hsw_wm_values *results)
2484{
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct drm_crtc *crtc;
cca32e9a 2487 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2488 enum pipe pipe;
cca32e9a
PZ		 2489 int level, max_level, wm_lp;
2490
2491 for (level = 1; level <= 4; level++)
e5d5019e 2492 if (!hsw_compute_lp_wm(wm[level] * 5, lp_maximums, params,
cca32e9a
PZ		 2493 &lp_results[level - 1]))
2494 break;
2495 max_level = level - 1;
2496
2497 /* The spec says it is preferred to disable FBC WMs instead of disabling
2498 * a WM level. */
2499 results->enable_fbc_wm = true;
2500 for (level = 1; level <= max_level; level++) {
2501 if (!lp_results[level - 1].fbc_enable) {
2502 results->enable_fbc_wm = false;
2503 break;
2504 }
2505 }
2506
2507 memset(results, 0, sizeof(*results));
2508 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2509 const struct hsw_lp_wm_result *r;
801bcfff 2510
cca32e9a
PZ		 2511 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2512 if (level > max_level)
2513 break;
2514
2515 r = &lp_results[level - 1];
2516 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2517 r->fbc_val,
2518 r->pri_val,
2519 r->cur_val);
2520 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2521 }
801bcfff
PZ		 2522
2523 for_each_pipe(pipe)
2524 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2525 pipe,
2526 &params[pipe]);
1011d8c4
PZ		 2527
2528 for_each_pipe(pipe) {
2529 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2530 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2531 }
2532}
2533
861f3389
PZ		 2534/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2535 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2536static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2537 struct hsw_wm_values *r2)
861f3389
PZ		 2538{
2539 int i, val_r1 = 0, val_r2 = 0;
2540
2541 for (i = 0; i < 3; i++) {
2542 if (r1->wm_lp[i] & WM3_LP_EN)
2543 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2544 if (r2->wm_lp[i] & WM3_LP_EN)
2545 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2546 }
2547
2548 if (val_r1 == val_r2) {
2549 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2550 return r2;
2551 else
2552 return r1;
2553 } else if (val_r1 > val_r2) {
2554 return r1;
2555 } else {
2556 return r2;
2557 }
2558}
2559
801bcfff
PZ		 2560/*
2561 * The spec says we shouldn't write when we don't need, because every write
2562 * causes WMs to be re-evaluated, expending some power.
2563 */
2564static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2565 struct hsw_wm_values *results,
2566 enum hsw_data_buf_partitioning partitioning)
2567{
2568 struct hsw_wm_values previous;
2569 uint32_t val;
2570 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2571 bool prev_enable_fbc_wm;
801bcfff
PZ		 2572
2573 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2574 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2575 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2576 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2577 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2578 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2579 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2580 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2581 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2582 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2583 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2584 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2585
2586 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2587 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2588
cca32e9a
PZ		 2589 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2590
801bcfff
PZ		 2591 if (memcmp(results->wm_pipe, previous.wm_pipe,
2592 sizeof(results->wm_pipe)) == 0 &&
2593 memcmp(results->wm_lp, previous.wm_lp,
2594 sizeof(results->wm_lp)) == 0 &&
2595 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2596 sizeof(results->wm_lp_spr)) == 0 &&
2597 memcmp(results->wm_linetime, previous.wm_linetime,
2598 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2599 partitioning == prev_partitioning &&
2600 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2601 return;
2602
2603 if (previous.wm_lp[2] != 0)
2604 I915_WRITE(WM3_LP_ILK, 0);
2605 if (previous.wm_lp[1] != 0)
2606 I915_WRITE(WM2_LP_ILK, 0);
2607 if (previous.wm_lp[0] != 0)
2608 I915_WRITE(WM1_LP_ILK, 0);
2609
2610 if (previous.wm_pipe[0] != results->wm_pipe[0])
2611 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2612 if (previous.wm_pipe[1] != results->wm_pipe[1])
2613 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2614 if (previous.wm_pipe[2] != results->wm_pipe[2])
2615 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2616
2617 if (previous.wm_linetime[0] != results->wm_linetime[0])
2618 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2619 if (previous.wm_linetime[1] != results->wm_linetime[1])
2620 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2621 if (previous.wm_linetime[2] != results->wm_linetime[2])
2622 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2623
2624 if (prev_partitioning != partitioning) {
2625 val = I915_READ(WM_MISC);
2626 if (partitioning == HSW_DATA_BUF_PART_1_2)
2627 val &= ~WM_MISC_DATA_PARTITION_5_6;
2628 else
2629 val |= WM_MISC_DATA_PARTITION_5_6;
2630 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2631 }
2632
cca32e9a
PZ		 2633 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2634 val = I915_READ(DISP_ARB_CTL);
2635 if (results->enable_fbc_wm)
2636 val &= ~DISP_FBC_WM_DIS;
2637 else
2638 val |= DISP_FBC_WM_DIS;
2639 I915_WRITE(DISP_ARB_CTL, val);
2640 }
2641
801bcfff
PZ		 2642 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2643 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2644 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2645 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2646 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2647 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2648
2649 if (results->wm_lp[0] != 0)
2650 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2651 if (results->wm_lp[1] != 0)
2652 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2653 if (results->wm_lp[2] != 0)
2654 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2655}
2656
2657static void haswell_update_wm(struct drm_device *dev)
2658{
2659 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2660 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2661 struct hsw_pipe_wm_parameters params[3];
861f3389 2662 struct hsw_wm_values results_1_2, results_5_6, *best_results;
861f3389
PZ		 2663 enum hsw_data_buf_partitioning partitioning;
2664
12b134df 2665 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2666
53615a5e
VS		 2667 hsw_compute_wm_results(dev, params,
2668 dev_priv->wm.pri_latency,
2669 &lp_max_1_2, &results_1_2);
861f3389 2670 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e
VS		 2671 hsw_compute_wm_results(dev, params,
2672 dev_priv->wm.pri_latency,
2673 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2674 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2675 } else {
2676 best_results = &results_1_2;
2677 }
2678
2679 partitioning = (best_results == &results_1_2) ?
2680 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2681
861f3389 2682 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2683}
2684
526682e9
PZ		 2685static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2686 uint32_t sprite_width, int pixel_size,
bdd57d03 2687 bool enabled, bool scaled)
526682e9
PZ		 2688{
2689 struct drm_plane *plane;
2690
2691 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2692 struct intel_plane *intel_plane = to_intel_plane(plane);
2693
2694 if (intel_plane->pipe == pipe) {
bdd57d03
VS		 2695 intel_plane->wm.enabled = enabled;
2696 intel_plane->wm.scaled = scaled;
67ca28f3 2697 intel_plane->wm.horiz_pixels = sprite_width;
526682e9
PZ		 2698 intel_plane->wm.bytes_per_pixel = pixel_size;
2699 break;
2700 }
2701 }
2702
2703 haswell_update_wm(dev);
2704}
2705
b445e3b0
ED		 2706static bool
2707sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2708 uint32_t sprite_width, int pixel_size,
2709 const struct intel_watermark_params *display,
2710 int display_latency_ns, int *sprite_wm)
2711{
2712 struct drm_crtc *crtc;
2713 int clock;
2714 int entries, tlb_miss;
2715
2716 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2717 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2718 *sprite_wm = display->guard_size;
2719 return false;
2720 }
2721
2722 clock = crtc->mode.clock;
2723
2724 /* Use the small buffer method to calculate the sprite watermark */
2725 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2726 tlb_miss = display->fifo_size*display->cacheline_size -
2727 sprite_width * 8;
2728 if (tlb_miss > 0)
2729 entries += tlb_miss;
2730 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2731 *sprite_wm = entries + display->guard_size;
2732 if (*sprite_wm > (int)display->max_wm)
2733 *sprite_wm = display->max_wm;
2734
2735 return true;
2736}
2737
2738static bool
2739sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2740 uint32_t sprite_width, int pixel_size,
2741 const struct intel_watermark_params *display,
2742 int latency_ns, int *sprite_wm)
2743{
2744 struct drm_crtc *crtc;
2745 unsigned long line_time_us;
2746 int clock;
2747 int line_count, line_size;
2748 int small, large;
2749 int entries;
2750
2751 if (!latency_ns) {
2752 *sprite_wm = 0;
2753 return false;
2754 }
2755
2756 crtc = intel_get_crtc_for_plane(dev, plane);
2757 clock = crtc->mode.clock;
2758 if (!clock) {
2759 *sprite_wm = 0;
2760 return false;
2761 }
2762
2763 line_time_us = (sprite_width * 1000) / clock;
2764 if (!line_time_us) {
2765 *sprite_wm = 0;
2766 return false;
2767 }
2768
2769 line_count = (latency_ns / line_time_us + 1000) / 1000;
2770 line_size = sprite_width * pixel_size;
2771
2772 /* Use the minimum of the small and large buffer method for primary */
2773 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2774 large = line_count * line_size;
2775
2776 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2777 *sprite_wm = entries + display->guard_size;
2778
2779 return *sprite_wm > 0x3ff ? false : true;
2780}
2781
1fa61106 2782static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a 2783 uint32_t sprite_width, int pixel_size,
bdd57d03 2784 bool enable, bool scaled)
b445e3b0
ED		 2785{
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2788 u32 val;
2789 int sprite_wm, reg;
2790 int ret;
2791
4c4ff43a
PZ		 2792 if (!enable)
2793 return;
2794
b445e3b0
ED		 2795 switch (pipe) {
2796 case 0:
2797 reg = WM0_PIPEA_ILK;
2798 break;
2799 case 1:
2800 reg = WM0_PIPEB_ILK;
2801 break;
2802 case 2:
2803 reg = WM0_PIPEC_IVB;
2804 break;
2805 default:
2806 return; /* bad pipe */
2807 }
2808
2809 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2810 &sandybridge_display_wm_info,
2811 latency, &sprite_wm);
2812 if (!ret) {
84f44ce7
VS		 2813 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2814 pipe_name(pipe));
b445e3b0
ED		 2815 return;
2816 }
2817
2818 val = I915_READ(reg);
2819 val &= ~WM0_PIPE_SPRITE_MASK;
2820 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2821 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2822
2823
2824 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2825 pixel_size,
2826 &sandybridge_display_srwm_info,
2827 SNB_READ_WM1_LATENCY() * 500,
2828 &sprite_wm);
2829 if (!ret) {
84f44ce7
VS		 2830 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2831 pipe_name(pipe));
b445e3b0
ED		 2832 return;
2833 }
2834 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2835
2836 /* Only IVB has two more LP watermarks for sprite */
2837 if (!IS_IVYBRIDGE(dev))
2838 return;
2839
2840 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2841 pixel_size,
2842 &sandybridge_display_srwm_info,
2843 SNB_READ_WM2_LATENCY() * 500,
2844 &sprite_wm);
2845 if (!ret) {
84f44ce7
VS		 2846 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2847 pipe_name(pipe));
b445e3b0
ED		 2848 return;
2849 }
2850 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2851
2852 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2853 pixel_size,
2854 &sandybridge_display_srwm_info,
2855 SNB_READ_WM3_LATENCY() * 500,
2856 &sprite_wm);
2857 if (!ret) {
84f44ce7
VS		 2858 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2859 pipe_name(pipe));
b445e3b0
ED		 2860 return;
2861 }
2862 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2863}
2864
2865/**
2866 * intel_update_watermarks - update FIFO watermark values based on current modes
2867 *
2868 * Calculate watermark values for the various WM regs based on current mode
2869 * and plane configuration.
2870 *
2871 * There are several cases to deal with here:
2872 * - normal (i.e. non-self-refresh)
2873 * - self-refresh (SR) mode
2874 * - lines are large relative to FIFO size (buffer can hold up to 2)
2875 * - lines are small relative to FIFO size (buffer can hold more than 2
2876 * lines), so need to account for TLB latency
2877 *
2878 * The normal calculation is:
2879 * watermark = dotclock * bytes per pixel * latency
2880 * where latency is platform & configuration dependent (we assume pessimal
2881 * values here).
2882 *
2883 * The SR calculation is:
2884 * watermark = (trunc(latency/line time)+1) * surface width *
2885 * bytes per pixel
2886 * where
2887 * line time = htotal / dotclock
2888 * surface width = hdisplay for normal plane and 64 for cursor
2889 * and latency is assumed to be high, as above.
2890 *
2891 * The final value programmed to the register should always be rounded up,
2892 * and include an extra 2 entries to account for clock crossings.
2893 *
2894 * We don't use the sprite, so we can ignore that. And on Crestline we have
2895 * to set the non-SR watermarks to 8.
2896 */
2897void intel_update_watermarks(struct drm_device *dev)
2898{
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900
2901 if (dev_priv->display.update_wm)
2902 dev_priv->display.update_wm(dev);
2903}
2904
2905void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a 2906 uint32_t sprite_width, int pixel_size,
bdd57d03 2907 bool enable, bool scaled)
b445e3b0
ED		 2908{
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910
2911 if (dev_priv->display.update_sprite_wm)
2912 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
bdd57d03 2913 pixel_size, enable, scaled);
b445e3b0
ED		 2914}
2915
2b4e57bd
ED		 2916static struct drm_i915_gem_object *
2917intel_alloc_context_page(struct drm_device *dev)
2918{
2919 struct drm_i915_gem_object *ctx;
2920 int ret;
2921
2922 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2923
2924 ctx = i915_gem_alloc_object(dev, 4096);
2925 if (!ctx) {
2926 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2927 return NULL;
2928 }
2929
c37e2204 2930 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2931 if (ret) {
2932 DRM_ERROR("failed to pin power context: %d\n", ret);
2933 goto err_unref;
2934 }
2935
2936 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2937 if (ret) {
2938 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2939 goto err_unpin;
2940 }
2941
2942 return ctx;
2943
2944err_unpin:
2945 i915_gem_object_unpin(ctx);
2946err_unref:
2947 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2948 return NULL;
2949}
2950
9270388e
DV		 2951/**
2952 * Lock protecting IPS related data structures
9270388e
DV		 2953 */
2954DEFINE_SPINLOCK(mchdev_lock);
2955
2956/* Global for IPS driver to get at the current i915 device. Protected by
2957 * mchdev_lock. */
2958static struct drm_i915_private *i915_mch_dev;
2959
2b4e57bd
ED		 2960bool ironlake_set_drps(struct drm_device *dev, u8 val)
2961{
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 u16 rgvswctl;
2964
9270388e
DV		 2965 assert_spin_locked(&mchdev_lock);
2966
2b4e57bd
ED		 2967 rgvswctl = I915_READ16(MEMSWCTL);
2968 if (rgvswctl & MEMCTL_CMD_STS) {
2969 DRM_DEBUG("gpu busy, RCS change rejected\n");
2970 return false; /* still busy with another command */
2971 }
2972
2973 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2974 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2975 I915_WRITE16(MEMSWCTL, rgvswctl);
2976 POSTING_READ16(MEMSWCTL);
2977
2978 rgvswctl |= MEMCTL_CMD_STS;
2979 I915_WRITE16(MEMSWCTL, rgvswctl);
2980
2981 return true;
2982}
2983
8090c6b9 2984static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2985{
2986 struct drm_i915_private *dev_priv = dev->dev_private;
2987 u32 rgvmodectl = I915_READ(MEMMODECTL);
2988 u8 fmax, fmin, fstart, vstart;
2989
9270388e
DV		 2990 spin_lock_irq(&mchdev_lock);
2991
2b4e57bd
ED		 2992 /* Enable temp reporting */
2993 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2994 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2995
2996 /* 100ms RC evaluation intervals */
2997 I915_WRITE(RCUPEI, 100000);
2998 I915_WRITE(RCDNEI, 100000);
2999
3000 /* Set max/min thresholds to 90ms and 80ms respectively */
3001 I915_WRITE(RCBMAXAVG, 90000);
3002 I915_WRITE(RCBMINAVG, 80000);
3003
3004 I915_WRITE(MEMIHYST, 1);
3005
3006 /* Set up min, max, and cur for interrupt handling */
3007 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3008 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3009 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3010 MEMMODE_FSTART_SHIFT;
3011
3012 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3013 PXVFREQ_PX_SHIFT;
3014
20e4d407
DV		 3015 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3016 dev_priv->ips.fstart = fstart;
2b4e57bd 3017
20e4d407
DV		 3018 dev_priv->ips.max_delay = fstart;
3019 dev_priv->ips.min_delay = fmin;
3020 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3021
3022 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3023 fmax, fmin, fstart);
3024
3025 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3026
3027 /*
3028 * Interrupts will be enabled in ironlake_irq_postinstall
3029 */
3030
3031 I915_WRITE(VIDSTART, vstart);
3032 POSTING_READ(VIDSTART);
3033
3034 rgvmodectl |= MEMMODE_SWMODE_EN;
3035 I915_WRITE(MEMMODECTL, rgvmodectl);
3036
9270388e 3037 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3038 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3039 mdelay(1);
2b4e57bd
ED		 3040
3041 ironlake_set_drps(dev, fstart);
3042
20e4d407 3043 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3044 I915_READ(0x112e0);
20e4d407
DV		 3045 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3046 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3047 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3048
3049 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3050}
3051
8090c6b9 3052static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3053{
3054 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3055 u16 rgvswctl;
3056
3057 spin_lock_irq(&mchdev_lock);
3058
3059 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3060
3061 /* Ack interrupts, disable EFC interrupt */
3062 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3063 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3064 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3065 I915_WRITE(DEIIR, DE_PCU_EVENT);
3066 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3067
3068 /* Go back to the starting frequency */
20e4d407 3069 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3070 mdelay(1);
2b4e57bd
ED		 3071 rgvswctl |= MEMCTL_CMD_STS;
3072 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3073 mdelay(1);
2b4e57bd 3074
9270388e 3075 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3076}
3077
acbe9475
DV		 3078/* There's a funny hw issue where the hw returns all 0 when reading from
3079 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3080 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3081 * all limits and the gpu stuck at whatever frequency it is at atm).
3082 */
65bccb5c 3083static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3084{
7b9e0ae6 3085 u32 limits;
2b4e57bd 3086
7b9e0ae6 3087 limits = 0;
c6a828d3
DV		 3088
3089 if (*val >= dev_priv->rps.max_delay)
3090 *val = dev_priv->rps.max_delay;
3091 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3092
3093 /* Only set the down limit when we've reached the lowest level to avoid
3094 * getting more interrupts, otherwise leave this clear. This prevents a
3095 * race in the hw when coming out of rc6: There's a tiny window where
3096 * the hw runs at the minimal clock before selecting the desired
3097 * frequency, if the down threshold expires in that window we will not
3098 * receive a down interrupt. */
c6a828d3
DV		 3099 if (*val <= dev_priv->rps.min_delay) {
3100 *val = dev_priv->rps.min_delay;
3101 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3102 }
3103
3104 return limits;
3105}
3106
3107void gen6_set_rps(struct drm_device *dev, u8 val)
3108{
3109 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3110 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3111
4fc688ce 3112 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3113 WARN_ON(val > dev_priv->rps.max_delay);
3114 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3115
c6a828d3 3116 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3117 return;
3118
92bd1bf0
RV		 3119 if (IS_HASWELL(dev))
3120 I915_WRITE(GEN6_RPNSWREQ,
3121 HSW_FREQUENCY(val));
3122 else
3123 I915_WRITE(GEN6_RPNSWREQ,
3124 GEN6_FREQUENCY(val) |
3125 GEN6_OFFSET(0) |
3126 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3127
3128 /* Make sure we continue to get interrupts
3129 * until we hit the minimum or maximum frequencies.
3130 */
3131 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3132
d5570a72
BW		 3133 POSTING_READ(GEN6_RPNSWREQ);
3134
c6a828d3 3135 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3136
3137 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3138}
3139
80814ae4
VS		 3140/*
3141 * Wait until the previous freq change has completed,
3142 * or the timeout elapsed, and then update our notion
3143 * of the current GPU frequency.
3144 */
3145static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3146{
80814ae4
VS		 3147 u32 pval;
3148
3149 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3150
e8474409
VS		 3151 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3152 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3153
3154 pval >>= 8;
3155
3156 if (pval != dev_priv->rps.cur_delay)
3157 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3158 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3159 dev_priv->rps.cur_delay,
3160 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3161
3162 dev_priv->rps.cur_delay = pval;
3163}
3164
0a073b84
JB		 3165void valleyview_set_rps(struct drm_device *dev, u8 val)
3166{
3167 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3168
3169 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3170
3171 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3172 WARN_ON(val > dev_priv->rps.max_delay);
3173 WARN_ON(val < dev_priv->rps.min_delay);
3174
80814ae4
VS		 3175 vlv_update_rps_cur_delay(dev_priv);
3176
73008b98 3177 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3178 vlv_gpu_freq(dev_priv->mem_freq,
3179 dev_priv->rps.cur_delay),
73008b98
VS		 3180 dev_priv->rps.cur_delay,
3181 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3182
3183 if (val == dev_priv->rps.cur_delay)
3184 return;
3185
ae99258f 3186 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3187
80814ae4 3188 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3189
3190 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3191}
3192
44fc7d5c 3193static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3194{
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196
2b4e57bd 3197 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3198 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3199 /* Complete PM interrupt masking here doesn't race with the rps work
3200 * item again unmasking PM interrupts because that is using a different
3201 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3202 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3203
59cdb63d 3204 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3205 dev_priv->rps.pm_iir = 0;
59cdb63d 3206 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3207
4848405c 3208 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3209}
3210
44fc7d5c 3211static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3212{
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214
3215 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3216 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3217
44fc7d5c
DV		 3218 gen6_disable_rps_interrupts(dev);
3219}
3220
3221static void valleyview_disable_rps(struct drm_device *dev)
3222{
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224
3225 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3226
44fc7d5c 3227 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3228
3229 if (dev_priv->vlv_pctx) {
3230 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3231 dev_priv->vlv_pctx = NULL;
3232 }
d20d4f0c
JB		 3233}
3234
2b4e57bd
ED		 3235int intel_enable_rc6(const struct drm_device *dev)
3236{
eb4926e4
DL		 3237 /* No RC6 before Ironlake */
3238 if (INTEL_INFO(dev)->gen < 5)
3239 return 0;
3240
456470eb 3241 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3242 if (i915_enable_rc6 >= 0)
3243 return i915_enable_rc6;
3244
6567d748
CW		 3245 /* Disable RC6 on Ironlake */
3246 if (INTEL_INFO(dev)->gen == 5)
3247 return 0;
2b4e57bd 3248
456470eb
DV		 3249 if (IS_HASWELL(dev)) {
3250 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3251 return INTEL_RC6_ENABLE;
456470eb 3252 }
2b4e57bd 3253
456470eb 3254 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3255 if (INTEL_INFO(dev)->gen == 6) {
3256 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3257 return INTEL_RC6_ENABLE;
3258 }
456470eb 3259
2b4e57bd
ED		 3260 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3261 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3262}
3263
44fc7d5c
DV		 3264static void gen6_enable_rps_interrupts(struct drm_device *dev)
3265{
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267
3268 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3269 WARN_ON(dev_priv->rps.pm_iir);
44fc7d5c
DV		 3270 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3271 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273 /* unmask all PM interrupts */
3274 I915_WRITE(GEN6_PMINTRMSK, 0);
3275}
3276
79f5b2c7 3277static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3278{
79f5b2c7 3279 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3280 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3281 u32 rp_state_cap;
3282 u32 gt_perf_status;
31643d54 3283 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3284 u32 gtfifodbg;
2b4e57bd 3285 int rc6_mode;
42c0526c 3286 int i, ret;
2b4e57bd 3287
4fc688ce 3288 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3289
2b4e57bd
ED		 3290 /* Here begins a magic sequence of register writes to enable
3291 * auto-downclocking.
3292 *
3293 * Perhaps there might be some value in exposing these to
3294 * userspace...
3295 */
3296 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3297
3298 /* Clear the DBG now so we don't confuse earlier errors */
3299 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3300 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3301 I915_WRITE(GTFIFODBG, gtfifodbg);
3302 }
3303
3304 gen6_gt_force_wake_get(dev_priv);
3305
7b9e0ae6
CW		 3306 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3307 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3308
31c77388
BW		 3309 /* In units of 50MHz */
3310 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3311 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3312 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3313
2b4e57bd
ED		 3314 /* disable the counters and set deterministic thresholds */
3315 I915_WRITE(GEN6_RC_CONTROL, 0);
3316
3317 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3318 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3319 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3320 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3321 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3322
b4519513
CW		 3323 for_each_ring(ring, dev_priv, i)
3324 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3325
3326 I915_WRITE(GEN6_RC_SLEEP, 0);
3327 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3328 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3329 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3330 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3331
5a7dc92a 3332 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3333 rc6_mode = intel_enable_rc6(dev_priv->dev);
3334 if (rc6_mode & INTEL_RC6_ENABLE)
3335 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3336
5a7dc92a
ED		 3337 /* We don't use those on Haswell */
3338 if (!IS_HASWELL(dev)) {
3339 if (rc6_mode & INTEL_RC6p_ENABLE)
3340 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3341
5a7dc92a
ED		 3342 if (rc6_mode & INTEL_RC6pp_ENABLE)
3343 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3344 }
2b4e57bd
ED		 3345
3346 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3347 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3348 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3349 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3350
3351 I915_WRITE(GEN6_RC_CONTROL,
3352 rc6_mask |
3353 GEN6_RC_CTL_EI_MODE(1) |
3354 GEN6_RC_CTL_HW_ENABLE);
3355
92bd1bf0
RV		 3356 if (IS_HASWELL(dev)) {
3357 I915_WRITE(GEN6_RPNSWREQ,
3358 HSW_FREQUENCY(10));
3359 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3360 HSW_FREQUENCY(12));
3361 } else {
3362 I915_WRITE(GEN6_RPNSWREQ,
3363 GEN6_FREQUENCY(10) |
3364 GEN6_OFFSET(0) |
3365 GEN6_AGGRESSIVE_TURBO);
3366 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3367 GEN6_FREQUENCY(12));
3368 }
2b4e57bd
ED		 3369
3370 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3371 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3372 dev_priv->rps.max_delay << 24 |
3373 dev_priv->rps.min_delay << 16);
5a7dc92a 3374
1ee9ae32
DV		 3375 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3376 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3377 I915_WRITE(GEN6_RP_UP_EI, 66000);
3378 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3379
2b4e57bd
ED		 3380 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3381 I915_WRITE(GEN6_RP_CONTROL,
3382 GEN6_RP_MEDIA_TURBO |
89ba829e 3383 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3384 GEN6_RP_MEDIA_IS_GFX |
3385 GEN6_RP_ENABLE |
3386 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3387 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3388
42c0526c 3389 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3390 if (!ret) {
42c0526c
BW		 3391 pcu_mbox = 0;
3392 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3393 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3394 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3395 (dev_priv->rps.max_delay & 0xff) * 50,
3396 (pcu_mbox & 0xff) * 50);
31c77388 3397 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3398 }
3399 } else {
3400 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3401 }
3402
7b9e0ae6 3403 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3404
44fc7d5c 3405 gen6_enable_rps_interrupts(dev);
2b4e57bd 3406
31643d54
BW		 3407 rc6vids = 0;
3408 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3409 if (IS_GEN6(dev) && ret) {
3410 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3411 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3412 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3413 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3414 rc6vids &= 0xffff00;
3415 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3416 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3417 if (ret)
3418 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3419 }
3420
2b4e57bd 3421 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3422}
3423
79f5b2c7 3424static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3425{
79f5b2c7 3426 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3427 int min_freq = 15;
3ebecd07
CW		 3428 unsigned int gpu_freq;
3429 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3430 int scaling_factor = 180;
3431
4fc688ce 3432 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3433
2b4e57bd
ED		 3434 max_ia_freq = cpufreq_quick_get_max(0);
3435 /*
3436 * Default to measured freq if none found, PCU will ensure we don't go
3437 * over
3438 */
3439 if (!max_ia_freq)
3440 max_ia_freq = tsc_khz;
3441
3442 /* Convert from kHz to MHz */
3443 max_ia_freq /= 1000;
3444
3ebecd07
CW		 3445 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3446 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3447 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3448
2b4e57bd
ED		 3449 /*
3450 * For each potential GPU frequency, load a ring frequency we'd like
3451 * to use for memory access. We do this by specifying the IA frequency
3452 * the PCU should use as a reference to determine the ring frequency.
3453 */
c6a828d3 3454 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3455 gpu_freq--) {
c6a828d3 3456 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3457 unsigned int ia_freq = 0, ring_freq = 0;
3458
3459 if (IS_HASWELL(dev)) {
3460 ring_freq = (gpu_freq * 5 + 3) / 4;
3461 ring_freq = max(min_ring_freq, ring_freq);
3462 /* leave ia_freq as the default, chosen by cpufreq */
3463 } else {
3464 /* On older processors, there is no separate ring
3465 * clock domain, so in order to boost the bandwidth
3466 * of the ring, we need to upclock the CPU (ia_freq).
3467 *
3468 * For GPU frequencies less than 750MHz,
3469 * just use the lowest ring freq.
3470 */
3471 if (gpu_freq < min_freq)
3472 ia_freq = 800;
3473 else
3474 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3475 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3476 }
2b4e57bd 3477
42c0526c
BW		 3478 sandybridge_pcode_write(dev_priv,
3479 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3480 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3481 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3482 gpu_freq);
2b4e57bd 3483 }
2b4e57bd
ED		 3484}
3485
0a073b84
JB		 3486int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3487{
3488 u32 val, rp0;
3489
64936258 3490 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3491
3492 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3493 /* Clamp to max */
3494 rp0 = min_t(u32, rp0, 0xea);
3495
3496 return rp0;
3497}
3498
3499static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3500{
3501 u32 val, rpe;
3502
64936258 3503 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3504 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3505 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3506 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3507
3508 return rpe;
3509}
3510
3511int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3512{
64936258 3513 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3514}
3515
52ceb908
JB		 3516static void vlv_rps_timer_work(struct work_struct *work)
3517{
3518 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3519 rps.vlv_work.work);
3520
3521 /*
3522 * Timer fired, we must be idle. Drop to min voltage state.
3523 * Note: we use RPe here since it should match the
3524 * Vmin we were shooting for. That should give us better
3525 * perf when we come back out of RC6 than if we used the
3526 * min freq available.
3527 */
3528 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3529 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3530 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3531 mutex_unlock(&dev_priv->rps.hw_lock);
3532}
3533
c9cddffc
JB		 3534static void valleyview_setup_pctx(struct drm_device *dev)
3535{
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 struct drm_i915_gem_object *pctx;
3538 unsigned long pctx_paddr;
3539 u32 pcbr;
3540 int pctx_size = 24*1024;
3541
3542 pcbr = I915_READ(VLV_PCBR);
3543 if (pcbr) {
3544 /* BIOS set it up already, grab the pre-alloc'd space */
3545 int pcbr_offset;
3546
3547 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3548 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3549 pcbr_offset,
190d6cd5 3550 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3551 pctx_size);
3552 goto out;
3553 }
3554
3555 /*
3556 * From the Gunit register HAS:
3557 * The Gfx driver is expected to program this register and ensure
3558 * proper allocation within Gfx stolen memory. For example, this
3559 * register should be programmed such than the PCBR range does not
3560 * overlap with other ranges, such as the frame buffer, protected
3561 * memory, or any other relevant ranges.
3562 */
3563 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3564 if (!pctx) {
3565 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3566 return;
3567 }
3568
3569 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3570 I915_WRITE(VLV_PCBR, pctx_paddr);
3571
3572out:
3573 dev_priv->vlv_pctx = pctx;
3574}
3575
0a073b84
JB		 3576static void valleyview_enable_rps(struct drm_device *dev)
3577{
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 struct intel_ring_buffer *ring;
73008b98 3580 u32 gtfifodbg, val;
0a073b84
JB		 3581 int i;
3582
3583 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3584
3585 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3586 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3587 I915_WRITE(GTFIFODBG, gtfifodbg);
3588 }
3589
c9cddffc
JB		 3590 valleyview_setup_pctx(dev);
3591
0a073b84
JB		 3592 gen6_gt_force_wake_get(dev_priv);
3593
3594 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3595 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3596 I915_WRITE(GEN6_RP_UP_EI, 66000);
3597 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3598
3599 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3600
3601 I915_WRITE(GEN6_RP_CONTROL,
3602 GEN6_RP_MEDIA_TURBO |
3603 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3604 GEN6_RP_MEDIA_IS_GFX |
3605 GEN6_RP_ENABLE |
3606 GEN6_RP_UP_BUSY_AVG |
3607 GEN6_RP_DOWN_IDLE_CONT);
3608
3609 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3610 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3611 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3612
3613 for_each_ring(ring, dev_priv, i)
3614 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3615
3616 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3617
3618 /* allows RC6 residency counter to work */
3619 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3620 I915_WRITE(GEN6_RC_CONTROL,
3621 GEN7_RC_CTL_TO_MODE);
3622
64936258 3623 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3624 switch ((val >> 6) & 3) {
3625 case 0:
3626 case 1:
3627 dev_priv->mem_freq = 800;
3628 break;
3629 case 2:
3630 dev_priv->mem_freq = 1066;
3631 break;
3632 case 3:
3633 dev_priv->mem_freq = 1333;
3634 break;
3635 }
0a073b84
JB		 3636 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3637
3638 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3639 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3640
0a073b84 3641 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3642 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3643 vlv_gpu_freq(dev_priv->mem_freq,
3644 dev_priv->rps.cur_delay),
3645 dev_priv->rps.cur_delay);
0a073b84
JB		 3646
3647 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3648 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3649 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3650 vlv_gpu_freq(dev_priv->mem_freq,
3651 dev_priv->rps.max_delay),
3652 dev_priv->rps.max_delay);
0a073b84 3653
73008b98
VS		 3654 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3655 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3656 vlv_gpu_freq(dev_priv->mem_freq,
3657 dev_priv->rps.rpe_delay),
3658 dev_priv->rps.rpe_delay);
0a073b84 3659
73008b98
VS		 3660 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3661 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3662 vlv_gpu_freq(dev_priv->mem_freq,
3663 dev_priv->rps.min_delay),
3664 dev_priv->rps.min_delay);
0a073b84 3665
73008b98
VS		 3666 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3667 vlv_gpu_freq(dev_priv->mem_freq,
3668 dev_priv->rps.rpe_delay),
3669 dev_priv->rps.rpe_delay);
0a073b84 3670
52ceb908
JB		 3671 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3672
73008b98 3673 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3674
44fc7d5c 3675 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3676
3677 gen6_gt_force_wake_put(dev_priv);
3678}
3679
930ebb46 3680void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3681{
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683
3e373948
DV		 3684 if (dev_priv->ips.renderctx) {
3685 i915_gem_object_unpin(dev_priv->ips.renderctx);
3686 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3687 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3688 }
3689
3e373948
DV		 3690 if (dev_priv->ips.pwrctx) {
3691 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3692 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3693 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3694 }
3695}
3696
930ebb46 3697static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3698{
3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700
3701 if (I915_READ(PWRCTXA)) {
3702 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3703 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3704 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3705 50);
3706
3707 I915_WRITE(PWRCTXA, 0);
3708 POSTING_READ(PWRCTXA);
3709
3710 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3711 POSTING_READ(RSTDBYCTL);
3712 }
2b4e57bd
ED		 3713}
3714
3715static int ironlake_setup_rc6(struct drm_device *dev)
3716{
3717 struct drm_i915_private *dev_priv = dev->dev_private;
3718
3e373948
DV		 3719 if (dev_priv->ips.renderctx == NULL)
3720 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3721 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3722 return -ENOMEM;
3723
3e373948
DV		 3724 if (dev_priv->ips.pwrctx == NULL)
3725 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3726 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3727 ironlake_teardown_rc6(dev);
3728 return -ENOMEM;
3729 }
3730
3731 return 0;
3732}
3733
930ebb46 3734static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3735{
3736 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3737 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3738 bool was_interruptible;
2b4e57bd
ED		 3739 int ret;
3740
3741 /* rc6 disabled by default due to repeated reports of hanging during
3742 * boot and resume.
3743 */
3744 if (!intel_enable_rc6(dev))
3745 return;
3746
79f5b2c7
DV		 3747 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3748
2b4e57bd 3749 ret = ironlake_setup_rc6(dev);
79f5b2c7 3750 if (ret)
2b4e57bd 3751 return;
2b4e57bd 3752
3e960501
CW		 3753 was_interruptible = dev_priv->mm.interruptible;
3754 dev_priv->mm.interruptible = false;
3755
2b4e57bd
ED		 3756 /*
3757 * GPU can automatically power down the render unit if given a page
3758 * to save state.
3759 */
6d90c952 3760 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3761 if (ret) {
3762 ironlake_teardown_rc6(dev);
3e960501 3763 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3764 return;
3765 }
3766
6d90c952
DV		 3767 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3768 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3769 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3770 MI_MM_SPACE_GTT |
3771 MI_SAVE_EXT_STATE_EN |
3772 MI_RESTORE_EXT_STATE_EN |
3773 MI_RESTORE_INHIBIT);
3774 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3775 intel_ring_emit(ring, MI_NOOP);
3776 intel_ring_emit(ring, MI_FLUSH);
3777 intel_ring_advance(ring);
2b4e57bd
ED		 3778
3779 /*
3780 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3781 * does an implicit flush, combined with MI_FLUSH above, it should be
3782 * safe to assume that renderctx is valid
3783 */
3e960501
CW		 3784 ret = intel_ring_idle(ring);
3785 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3786 if (ret) {
def27a58 3787 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3788 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3789 return;
3790 }
3791
f343c5f6 3792 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3793 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3794}
3795
dde18883
ED		 3796static unsigned long intel_pxfreq(u32 vidfreq)
3797{
3798 unsigned long freq;
3799 int div = (vidfreq & 0x3f0000) >> 16;
3800 int post = (vidfreq & 0x3000) >> 12;
3801 int pre = (vidfreq & 0x7);
3802
3803 if (!pre)
3804 return 0;
3805
3806 freq = ((div * 133333) / ((1<<post) * pre));
3807
3808 return freq;
3809}
3810
eb48eb00
DV		 3811static const struct cparams {
3812 u16 i;
3813 u16 t;
3814 u16 m;
3815 u16 c;
3816} cparams[] = {
3817 { 1, 1333, 301, 28664 },
3818 { 1, 1066, 294, 24460 },
3819 { 1, 800, 294, 25192 },
3820 { 0, 1333, 276, 27605 },
3821 { 0, 1066, 276, 27605 },
3822 { 0, 800, 231, 23784 },
3823};
3824
f531dcb2 3825static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3826{
3827 u64 total_count, diff, ret;
3828 u32 count1, count2, count3, m = 0, c = 0;
3829 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3830 int i;
3831
02d71956
DV		 3832 assert_spin_locked(&mchdev_lock);
3833
20e4d407 3834 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3835
3836 /* Prevent division-by-zero if we are asking too fast.
3837 * Also, we don't get interesting results if we are polling
3838 * faster than once in 10ms, so just return the saved value
3839 * in such cases.
3840 */
3841 if (diff1 <= 10)
20e4d407 3842 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3843
3844 count1 = I915_READ(DMIEC);
3845 count2 = I915_READ(DDREC);
3846 count3 = I915_READ(CSIEC);
3847
3848 total_count = count1 + count2 + count3;
3849
3850 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3851 if (total_count < dev_priv->ips.last_count1) {
3852 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3853 diff += total_count;
3854 } else {
20e4d407 3855 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3856 }
3857
3858 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3859 if (cparams[i].i == dev_priv->ips.c_m &&
3860 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3861 m = cparams[i].m;
3862 c = cparams[i].c;
3863 break;
3864 }
3865 }
3866
3867 diff = div_u64(diff, diff1);
3868 ret = ((m * diff) + c);
3869 ret = div_u64(ret, 10);
3870
20e4d407
DV		 3871 dev_priv->ips.last_count1 = total_count;
3872 dev_priv->ips.last_time1 = now;
eb48eb00 3873
20e4d407 3874 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3875
3876 return ret;
3877}
3878
f531dcb2
CW		 3879unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3880{
3881 unsigned long val;
3882
3883 if (dev_priv->info->gen != 5)
3884 return 0;
3885
3886 spin_lock_irq(&mchdev_lock);
3887
3888 val = __i915_chipset_val(dev_priv);
3889
3890 spin_unlock_irq(&mchdev_lock);
3891
3892 return val;
3893}
3894
eb48eb00
DV		 3895unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3896{
3897 unsigned long m, x, b;
3898 u32 tsfs;
3899
3900 tsfs = I915_READ(TSFS);
3901
3902 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3903 x = I915_READ8(TR1);
3904
3905 b = tsfs & TSFS_INTR_MASK;
3906
3907 return ((m * x) / 127) - b;
3908}
3909
3910static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3911{
3912 static const struct v_table {
3913 u16 vd; /* in .1 mil */
3914 u16 vm; /* in .1 mil */
3915 } v_table[] = {
3916 { 0, 0, },
3917 { 375, 0, },
3918 { 500, 0, },
3919 { 625, 0, },
3920 { 750, 0, },
3921 { 875, 0, },
3922 { 1000, 0, },
3923 { 1125, 0, },
3924 { 4125, 3000, },
3925 { 4125, 3000, },
3926 { 4125, 3000, },
3927 { 4125, 3000, },
3928 { 4125, 3000, },
3929 { 4125, 3000, },
3930 { 4125, 3000, },
3931 { 4125, 3000, },
3932 { 4125, 3000, },
3933 { 4125, 3000, },
3934 { 4125, 3000, },
3935 { 4125, 3000, },
3936 { 4125, 3000, },
3937 { 4125, 3000, },
3938 { 4125, 3000, },
3939 { 4125, 3000, },
3940 { 4125, 3000, },
3941 { 4125, 3000, },
3942 { 4125, 3000, },
3943 { 4125, 3000, },
3944 { 4125, 3000, },
3945 { 4125, 3000, },
3946 { 4125, 3000, },
3947 { 4125, 3000, },
3948 { 4250, 3125, },
3949 { 4375, 3250, },
3950 { 4500, 3375, },
3951 { 4625, 3500, },
3952 { 4750, 3625, },
3953 { 4875, 3750, },
3954 { 5000, 3875, },
3955 { 5125, 4000, },
3956 { 5250, 4125, },
3957 { 5375, 4250, },
3958 { 5500, 4375, },
3959 { 5625, 4500, },
3960 { 5750, 4625, },
3961 { 5875, 4750, },
3962 { 6000, 4875, },
3963 { 6125, 5000, },
3964 { 6250, 5125, },
3965 { 6375, 5250, },
3966 { 6500, 5375, },
3967 { 6625, 5500, },
3968 { 6750, 5625, },
3969 { 6875, 5750, },
3970 { 7000, 5875, },
3971 { 7125, 6000, },
3972 { 7250, 6125, },
3973 { 7375, 6250, },
3974 { 7500, 6375, },
3975 { 7625, 6500, },
3976 { 7750, 6625, },
3977 { 7875, 6750, },
3978 { 8000, 6875, },
3979 { 8125, 7000, },
3980 { 8250, 7125, },
3981 { 8375, 7250, },
3982 { 8500, 7375, },
3983 { 8625, 7500, },
3984 { 8750, 7625, },
3985 { 8875, 7750, },
3986 { 9000, 7875, },
3987 { 9125, 8000, },
3988 { 9250, 8125, },
3989 { 9375, 8250, },
3990 { 9500, 8375, },
3991 { 9625, 8500, },
3992 { 9750, 8625, },
3993 { 9875, 8750, },
3994 { 10000, 8875, },
3995 { 10125, 9000, },
3996 { 10250, 9125, },
3997 { 10375, 9250, },
3998 { 10500, 9375, },
3999 { 10625, 9500, },
4000 { 10750, 9625, },
4001 { 10875, 9750, },
4002 { 11000, 9875, },
4003 { 11125, 10000, },
4004 { 11250, 10125, },
4005 { 11375, 10250, },
4006 { 11500, 10375, },
4007 { 11625, 10500, },
4008 { 11750, 10625, },
4009 { 11875, 10750, },
4010 { 12000, 10875, },
4011 { 12125, 11000, },
4012 { 12250, 11125, },
4013 { 12375, 11250, },
4014 { 12500, 11375, },
4015 { 12625, 11500, },
4016 { 12750, 11625, },
4017 { 12875, 11750, },
4018 { 13000, 11875, },
4019 { 13125, 12000, },
4020 { 13250, 12125, },
4021 { 13375, 12250, },
4022 { 13500, 12375, },
4023 { 13625, 12500, },
4024 { 13750, 12625, },
4025 { 13875, 12750, },
4026 { 14000, 12875, },
4027 { 14125, 13000, },
4028 { 14250, 13125, },
4029 { 14375, 13250, },
4030 { 14500, 13375, },
4031 { 14625, 13500, },
4032 { 14750, 13625, },
4033 { 14875, 13750, },
4034 { 15000, 13875, },
4035 { 15125, 14000, },
4036 { 15250, 14125, },
4037 { 15375, 14250, },
4038 { 15500, 14375, },
4039 { 15625, 14500, },
4040 { 15750, 14625, },
4041 { 15875, 14750, },
4042 { 16000, 14875, },
4043 { 16125, 15000, },
4044 };
4045 if (dev_priv->info->is_mobile)
4046 return v_table[pxvid].vm;
4047 else
4048 return v_table[pxvid].vd;
4049}
4050
02d71956 4051static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4052{
4053 struct timespec now, diff1;
4054 u64 diff;
4055 unsigned long diffms;
4056 u32 count;
4057
02d71956 4058 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4059
4060 getrawmonotonic(&now);
20e4d407 4061 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4062
4063 /* Don't divide by 0 */
4064 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4065 if (!diffms)
4066 return;
4067
4068 count = I915_READ(GFXEC);
4069
20e4d407
DV		 4070 if (count < dev_priv->ips.last_count2) {
4071 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4072 diff += count;
4073 } else {
20e4d407 4074 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4075 }
4076
20e4d407
DV		 4077 dev_priv->ips.last_count2 = count;
4078 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4079
4080 /* More magic constants... */
4081 diff = diff * 1181;
4082 diff = div_u64(diff, diffms * 10);
20e4d407 4083 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4084}
4085
02d71956
DV		 4086void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4087{
4088 if (dev_priv->info->gen != 5)
4089 return;
4090
9270388e 4091 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4092
4093 __i915_update_gfx_val(dev_priv);
4094
9270388e 4095 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4096}
4097
f531dcb2 4098static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4099{
4100 unsigned long t, corr, state1, corr2, state2;
4101 u32 pxvid, ext_v;
4102
02d71956
DV		 4103 assert_spin_locked(&mchdev_lock);
4104
c6a828d3 4105 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4106 pxvid = (pxvid >> 24) & 0x7f;
4107 ext_v = pvid_to_extvid(dev_priv, pxvid);
4108
4109 state1 = ext_v;
4110
4111 t = i915_mch_val(dev_priv);
4112
4113 /* Revel in the empirically derived constants */
4114
4115 /* Correction factor in 1/100000 units */
4116 if (t > 80)
4117 corr = ((t * 2349) + 135940);
4118 else if (t >= 50)
4119 corr = ((t * 964) + 29317);
4120 else /* < 50 */
4121 corr = ((t * 301) + 1004);
4122
4123 corr = corr * ((150142 * state1) / 10000 - 78642);
4124 corr /= 100000;
20e4d407 4125 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4126
4127 state2 = (corr2 * state1) / 10000;
4128 state2 /= 100; /* convert to mW */
4129
02d71956 4130 __i915_update_gfx_val(dev_priv);
eb48eb00 4131
20e4d407 4132 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4133}
4134
f531dcb2
CW		 4135unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4136{
4137 unsigned long val;
4138
4139 if (dev_priv->info->gen != 5)
4140 return 0;
4141
4142 spin_lock_irq(&mchdev_lock);
4143
4144 val = __i915_gfx_val(dev_priv);
4145
4146 spin_unlock_irq(&mchdev_lock);
4147
4148 return val;
4149}
4150
eb48eb00
DV		 4151/**
4152 * i915_read_mch_val - return value for IPS use
4153 *
4154 * Calculate and return a value for the IPS driver to use when deciding whether
4155 * we have thermal and power headroom to increase CPU or GPU power budget.
4156 */
4157unsigned long i915_read_mch_val(void)
4158{
4159 struct drm_i915_private *dev_priv;
4160 unsigned long chipset_val, graphics_val, ret = 0;
4161
9270388e 4162 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4163 if (!i915_mch_dev)
4164 goto out_unlock;
4165 dev_priv = i915_mch_dev;
4166
f531dcb2
CW		 4167 chipset_val = __i915_chipset_val(dev_priv);
4168 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4169
4170 ret = chipset_val + graphics_val;
4171
4172out_unlock:
9270388e 4173 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4174
4175 return ret;
4176}
4177EXPORT_SYMBOL_GPL(i915_read_mch_val);
4178
4179/**
4180 * i915_gpu_raise - raise GPU frequency limit
4181 *
4182 * Raise the limit; IPS indicates we have thermal headroom.
4183 */
4184bool i915_gpu_raise(void)
4185{
4186 struct drm_i915_private *dev_priv;
4187 bool ret = true;
4188
9270388e 4189 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4190 if (!i915_mch_dev) {
4191 ret = false;
4192 goto out_unlock;
4193 }
4194 dev_priv = i915_mch_dev;
4195
20e4d407
DV		 4196 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4197 dev_priv->ips.max_delay--;
eb48eb00
DV		 4198
4199out_unlock:
9270388e 4200 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4201
4202 return ret;
4203}
4204EXPORT_SYMBOL_GPL(i915_gpu_raise);
4205
4206/**
4207 * i915_gpu_lower - lower GPU frequency limit
4208 *
4209 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4210 * frequency maximum.
4211 */
4212bool i915_gpu_lower(void)
4213{
4214 struct drm_i915_private *dev_priv;
4215 bool ret = true;
4216
9270388e 4217 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4218 if (!i915_mch_dev) {
4219 ret = false;
4220 goto out_unlock;
4221 }
4222 dev_priv = i915_mch_dev;
4223
20e4d407
DV		 4224 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4225 dev_priv->ips.max_delay++;
eb48eb00
DV		 4226
4227out_unlock:
9270388e 4228 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4229
4230 return ret;
4231}
4232EXPORT_SYMBOL_GPL(i915_gpu_lower);
4233
4234/**
4235 * i915_gpu_busy - indicate GPU business to IPS
4236 *
4237 * Tell the IPS driver whether or not the GPU is busy.
4238 */
4239bool i915_gpu_busy(void)
4240{
4241 struct drm_i915_private *dev_priv;
f047e395 4242 struct intel_ring_buffer *ring;
eb48eb00 4243 bool ret = false;
f047e395 4244 int i;
eb48eb00 4245
9270388e 4246 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4247 if (!i915_mch_dev)
4248 goto out_unlock;
4249 dev_priv = i915_mch_dev;
4250
f047e395
CW		 4251 for_each_ring(ring, dev_priv, i)
4252 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4253
4254out_unlock:
9270388e 4255 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4256
4257 return ret;
4258}
4259EXPORT_SYMBOL_GPL(i915_gpu_busy);
4260
4261/**
4262 * i915_gpu_turbo_disable - disable graphics turbo
4263 *
4264 * Disable graphics turbo by resetting the max frequency and setting the
4265 * current frequency to the default.
4266 */
4267bool i915_gpu_turbo_disable(void)
4268{
4269 struct drm_i915_private *dev_priv;
4270 bool ret = true;
4271
9270388e 4272 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4273 if (!i915_mch_dev) {
4274 ret = false;
4275 goto out_unlock;
4276 }
4277 dev_priv = i915_mch_dev;
4278
20e4d407 4279 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4280
20e4d407 4281 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4282 ret = false;
4283
4284out_unlock:
9270388e 4285 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4286
4287 return ret;
4288}
4289EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4290
4291/**
4292 * Tells the intel_ips driver that the i915 driver is now loaded, if
4293 * IPS got loaded first.
4294 *
4295 * This awkward dance is so that neither module has to depend on the
4296 * other in order for IPS to do the appropriate communication of
4297 * GPU turbo limits to i915.
4298 */
4299static void
4300ips_ping_for_i915_load(void)
4301{
4302 void (*link)(void);
4303
4304 link = symbol_get(ips_link_to_i915_driver);
4305 if (link) {
4306 link();
4307 symbol_put(ips_link_to_i915_driver);
4308 }
4309}
4310
4311void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4312{
02d71956
DV		 4313 /* We only register the i915 ips part with intel-ips once everything is
4314 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4315 spin_lock_irq(&mchdev_lock);
eb48eb00 4316 i915_mch_dev = dev_priv;
9270388e 4317 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4318
4319 ips_ping_for_i915_load();
4320}
4321
4322void intel_gpu_ips_teardown(void)
4323{
9270388e 4324 spin_lock_irq(&mchdev_lock);
eb48eb00 4325 i915_mch_dev = NULL;
9270388e 4326 spin_unlock_irq(&mchdev_lock);
eb48eb00 4327}
8090c6b9 4328static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4329{
4330 struct drm_i915_private *dev_priv = dev->dev_private;
4331 u32 lcfuse;
4332 u8 pxw[16];
4333 int i;
4334
4335 /* Disable to program */
4336 I915_WRITE(ECR, 0);
4337 POSTING_READ(ECR);
4338
4339 /* Program energy weights for various events */
4340 I915_WRITE(SDEW, 0x15040d00);
4341 I915_WRITE(CSIEW0, 0x007f0000);
4342 I915_WRITE(CSIEW1, 0x1e220004);
4343 I915_WRITE(CSIEW2, 0x04000004);
4344
4345 for (i = 0; i < 5; i++)
4346 I915_WRITE(PEW + (i * 4), 0);
4347 for (i = 0; i < 3; i++)
4348 I915_WRITE(DEW + (i * 4), 0);
4349
4350 /* Program P-state weights to account for frequency power adjustment */
4351 for (i = 0; i < 16; i++) {
4352 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4353 unsigned long freq = intel_pxfreq(pxvidfreq);
4354 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4355 PXVFREQ_PX_SHIFT;
4356 unsigned long val;
4357
4358 val = vid * vid;
4359 val *= (freq / 1000);
4360 val *= 255;
4361 val /= (127*127*900);
4362 if (val > 0xff)
4363 DRM_ERROR("bad pxval: %ld\n", val);
4364 pxw[i] = val;
4365 }
4366 /* Render standby states get 0 weight */
4367 pxw[14] = 0;
4368 pxw[15] = 0;
4369
4370 for (i = 0; i < 4; i++) {
4371 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4372 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4373 I915_WRITE(PXW + (i * 4), val);
4374 }
4375
4376 /* Adjust magic regs to magic values (more experimental results) */
4377 I915_WRITE(OGW0, 0);
4378 I915_WRITE(OGW1, 0);
4379 I915_WRITE(EG0, 0x00007f00);
4380 I915_WRITE(EG1, 0x0000000e);
4381 I915_WRITE(EG2, 0x000e0000);
4382 I915_WRITE(EG3, 0x68000300);
4383 I915_WRITE(EG4, 0x42000000);
4384 I915_WRITE(EG5, 0x00140031);
4385 I915_WRITE(EG6, 0);
4386 I915_WRITE(EG7, 0);
4387
4388 for (i = 0; i < 8; i++)
4389 I915_WRITE(PXWL + (i * 4), 0);
4390
4391 /* Enable PMON + select events */
4392 I915_WRITE(ECR, 0x80000019);
4393
4394 lcfuse = I915_READ(LCFUSE02);
4395
20e4d407 4396 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4397}
4398
8090c6b9
DV		 4399void intel_disable_gt_powersave(struct drm_device *dev)
4400{
1a01ab3b
JB		 4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402
fd0c0642
DV		 4403 /* Interrupts should be disabled already to avoid re-arming. */
4404 WARN_ON(dev->irq_enabled);
4405
930ebb46 4406 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4407 ironlake_disable_drps(dev);
930ebb46 4408 ironlake_disable_rc6(dev);
0a073b84 4409 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4410 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4411 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4412 if (IS_VALLEYVIEW(dev))
4413 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4414 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4415 if (IS_VALLEYVIEW(dev))
4416 valleyview_disable_rps(dev);
4417 else
4418 gen6_disable_rps(dev);
4fc688ce 4419 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4420 }
8090c6b9
DV		 4421}
4422
1a01ab3b
JB		 4423static void intel_gen6_powersave_work(struct work_struct *work)
4424{
4425 struct drm_i915_private *dev_priv =
4426 container_of(work, struct drm_i915_private,
4427 rps.delayed_resume_work.work);
4428 struct drm_device *dev = dev_priv->dev;
4429
4fc688ce 4430 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4431
4432 if (IS_VALLEYVIEW(dev)) {
4433 valleyview_enable_rps(dev);
4434 } else {
4435 gen6_enable_rps(dev);
4436 gen6_update_ring_freq(dev);
4437 }
4fc688ce 4438 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4439}
4440
8090c6b9
DV		 4441void intel_enable_gt_powersave(struct drm_device *dev)
4442{
1a01ab3b
JB		 4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444
8090c6b9
DV		 4445 if (IS_IRONLAKE_M(dev)) {
4446 ironlake_enable_drps(dev);
4447 ironlake_enable_rc6(dev);
4448 intel_init_emon(dev);
0a073b84 4449 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4450 /*
4451 * PCU communication is slow and this doesn't need to be
4452 * done at any specific time, so do this out of our fast path
4453 * to make resume and init faster.
4454 */
4455 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4456 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4457 }
4458}
4459
3107bd48
DV		 4460static void ibx_init_clock_gating(struct drm_device *dev)
4461{
4462 struct drm_i915_private *dev_priv = dev->dev_private;
4463
4464 /*
4465 * On Ibex Peak and Cougar Point, we need to disable clock
4466 * gating for the panel power sequencer or it will fail to
4467 * start up when no ports are active.
4468 */
4469 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4470}
4471
0e088b8f
VS		 4472static void g4x_disable_trickle_feed(struct drm_device *dev)
4473{
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 int pipe;
4476
4477 for_each_pipe(pipe) {
4478 I915_WRITE(DSPCNTR(pipe),
4479 I915_READ(DSPCNTR(pipe)) |
4480 DISPPLANE_TRICKLE_FEED_DISABLE);
4481 intel_flush_display_plane(dev_priv, pipe);
4482 }
4483}
4484
1fa61106 4485static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4486{
4487 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4488 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4489
f1e8fa56
DL		 4490 /*
4491 * Required for FBC
4492 * WaFbcDisableDpfcClockGating:ilk
4493 */
4d47e4f5
DL		 4494 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4495 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4496 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4497
4498 I915_WRITE(PCH_3DCGDIS0,
4499 MARIUNIT_CLOCK_GATE_DISABLE |
4500 SVSMUNIT_CLOCK_GATE_DISABLE);
4501 I915_WRITE(PCH_3DCGDIS1,
4502 VFMUNIT_CLOCK_GATE_DISABLE);
4503
6f1d69b0
ED		 4504 /*
4505 * According to the spec the following bits should be set in
4506 * order to enable memory self-refresh
4507 * The bit 22/21 of 0x42004
4508 * The bit 5 of 0x42020
4509 * The bit 15 of 0x45000
4510 */
4511 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4512 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4513 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4514 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4515 I915_WRITE(DISP_ARB_CTL,
4516 (I915_READ(DISP_ARB_CTL) |
4517 DISP_FBC_WM_DIS));
4518 I915_WRITE(WM3_LP_ILK, 0);
4519 I915_WRITE(WM2_LP_ILK, 0);
4520 I915_WRITE(WM1_LP_ILK, 0);
4521
4522 /*
4523 * Based on the document from hardware guys the following bits
4524 * should be set unconditionally in order to enable FBC.
4525 * The bit 22 of 0x42000
4526 * The bit 22 of 0x42004
4527 * The bit 7,8,9 of 0x42020.
4528 */
4529 if (IS_IRONLAKE_M(dev)) {
4bb35334 4530 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4531 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4532 I915_READ(ILK_DISPLAY_CHICKEN1) |
4533 ILK_FBCQ_DIS);
4534 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4535 I915_READ(ILK_DISPLAY_CHICKEN2) |
4536 ILK_DPARB_GATE);
6f1d69b0
ED		 4537 }
4538
4d47e4f5
DL		 4539 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4540
6f1d69b0
ED		 4541 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4542 I915_READ(ILK_DISPLAY_CHICKEN2) |
4543 ILK_ELPIN_409_SELECT);
4544 I915_WRITE(_3D_CHICKEN2,
4545 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4546 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4547
ecdb4eb7 4548 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4549 I915_WRITE(CACHE_MODE_0,
4550 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4551
0e088b8f 4552 g4x_disable_trickle_feed(dev);
bdad2b2f 4553
3107bd48
DV		 4554 ibx_init_clock_gating(dev);
4555}
4556
4557static void cpt_init_clock_gating(struct drm_device *dev)
4558{
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 int pipe;
3f704fa2 4561 uint32_t val;
3107bd48
DV		 4562
4563 /*
4564 * On Ibex Peak and Cougar Point, we need to disable clock
4565 * gating for the panel power sequencer or it will fail to
4566 * start up when no ports are active.
4567 */
4568 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4569 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4570 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4571 /* The below fixes the weird display corruption, a few pixels shifted
4572 * downward, on (only) LVDS of some HP laptops with IVY.
4573 */
3f704fa2 4574 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4575 val = I915_READ(TRANS_CHICKEN2(pipe));
4576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4577 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4578 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4579 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4580 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4581 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4582 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4583 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4584 }
3107bd48
DV		 4585 /* WADP0ClockGatingDisable */
4586 for_each_pipe(pipe) {
4587 I915_WRITE(TRANS_CHICKEN1(pipe),
4588 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4589 }
6f1d69b0
ED		 4590}
4591
1d7aaa0c
DV		 4592static void gen6_check_mch_setup(struct drm_device *dev)
4593{
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 uint32_t tmp;
4596
4597 tmp = I915_READ(MCH_SSKPD);
4598 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4599 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4600 DRM_INFO("This can cause pipe underruns and display issues.\n");
4601 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4602 }
4603}
4604
1fa61106 4605static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4606{
4607 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4608 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4609
231e54f6 4610 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4611
4612 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4613 I915_READ(ILK_DISPLAY_CHICKEN2) |
4614 ILK_ELPIN_409_SELECT);
4615
ecdb4eb7 4616 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4617 I915_WRITE(_3D_CHICKEN,
4618 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4619
ecdb4eb7 4620 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4621 if (IS_SNB_GT1(dev))
4622 I915_WRITE(GEN6_GT_MODE,
4623 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4624
6f1d69b0
ED		 4625 I915_WRITE(WM3_LP_ILK, 0);
4626 I915_WRITE(WM2_LP_ILK, 0);
4627 I915_WRITE(WM1_LP_ILK, 0);
4628
6f1d69b0 4629 I915_WRITE(CACHE_MODE_0,
50743298 4630 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4631
4632 I915_WRITE(GEN6_UCGCTL1,
4633 I915_READ(GEN6_UCGCTL1) |
4634 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4635 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4636
4637 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4638 * gating disable must be set. Failure to set it results in
4639 * flickering pixels due to Z write ordering failures after
4640 * some amount of runtime in the Mesa "fire" demo, and Unigine
4641 * Sanctuary and Tropics, and apparently anything else with
4642 * alpha test or pixel discard.
4643 *
4644 * According to the spec, bit 11 (RCCUNIT) must also be set,
4645 * but we didn't debug actual testcases to find it out.
0f846f81 4646 *
ecdb4eb7
DL		 4647 * Also apply WaDisableVDSUnitClockGating:snb and
4648 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4649 */
4650 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4651 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4652 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4653 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4654
4655 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4656 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4657 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4658
4659 /*
4660 * According to the spec the following bits should be
4661 * set in order to enable memory self-refresh and fbc:
4662 * The bit21 and bit22 of 0x42000
4663 * The bit21 and bit22 of 0x42004
4664 * The bit5 and bit7 of 0x42020
4665 * The bit14 of 0x70180
4666 * The bit14 of 0x71180
4bb35334
DL		 4667 *
4668 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4669 */
4670 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4671 I915_READ(ILK_DISPLAY_CHICKEN1) |
4672 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4673 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4674 I915_READ(ILK_DISPLAY_CHICKEN2) |
4675 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4676 I915_WRITE(ILK_DSPCLK_GATE_D,
4677 I915_READ(ILK_DSPCLK_GATE_D) |
4678 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4679 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4680
ecdb4eb7 4681 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4682 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4683 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4684
0e088b8f 4685 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4686
4687 /* The default value should be 0x200 according to docs, but the two
4688 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4689 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4690 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4691
4692 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4693
4694 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4695}
4696
4697static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4698{
4699 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4700
4701 reg &= ~GEN7_FF_SCHED_MASK;
4702 reg |= GEN7_FF_TS_SCHED_HW;
4703 reg |= GEN7_FF_VS_SCHED_HW;
4704 reg |= GEN7_FF_DS_SCHED_HW;
4705
41c0b3a8
BW		 4706 if (IS_HASWELL(dev_priv->dev))
4707 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4708
6f1d69b0
ED		 4709 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4710}
4711
17a303ec
PZ		 4712static void lpt_init_clock_gating(struct drm_device *dev)
4713{
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715
4716 /*
4717 * TODO: this bit should only be enabled when really needed, then
4718 * disabled when not needed anymore in order to save power.
4719 */
4720 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4721 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4722 I915_READ(SOUTH_DSPCLK_GATE_D) |
4723 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4724
4725 /* WADPOClockGatingDisable:hsw */
4726 I915_WRITE(_TRANSA_CHICKEN1,
4727 I915_READ(_TRANSA_CHICKEN1) |
4728 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4729}
4730
7d708ee4
ID		 4731static void lpt_suspend_hw(struct drm_device *dev)
4732{
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734
4735 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4736 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4737
4738 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4739 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4740 }
4741}
4742
cad2a2d7
ED		 4743static void haswell_init_clock_gating(struct drm_device *dev)
4744{
4745 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4746
4747 I915_WRITE(WM3_LP_ILK, 0);
4748 I915_WRITE(WM2_LP_ILK, 0);
4749 I915_WRITE(WM1_LP_ILK, 0);
4750
4751 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4752 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4753 */
4754 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4755
ecdb4eb7 4756 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4757 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4758 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4759
ecdb4eb7 4760 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4761 I915_WRITE(GEN7_L3CNTLREG1,
4762 GEN7_WA_FOR_GEN7_L3_CONTROL);
4763 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4764 GEN7_WA_L3_CHICKEN_MODE);
4765
ecdb4eb7 4766 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4767 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4768 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4769 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4770
0e088b8f 4771 g4x_disable_trickle_feed(dev);
cad2a2d7 4772
ecdb4eb7 4773 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4774 gen7_setup_fixed_func_scheduler(dev_priv);
4775
ecdb4eb7 4776 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4777 I915_WRITE(CACHE_MODE_1,
4778 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4779
ecdb4eb7 4780 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4781 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4782 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4783
ecdb4eb7 4784 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4785 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4786
90a88643
PZ		 4787 /* WaRsPkgCStateDisplayPMReq:hsw */
4788 I915_WRITE(CHICKEN_PAR1_1,
4789 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4790
17a303ec 4791 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4792}
4793
1fa61106 4794static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4795{
4796 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4797 uint32_t snpcr;
6f1d69b0 4798
6f1d69b0
ED		 4799 I915_WRITE(WM3_LP_ILK, 0);
4800 I915_WRITE(WM2_LP_ILK, 0);
4801 I915_WRITE(WM1_LP_ILK, 0);
4802
231e54f6 4803 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4804
ecdb4eb7 4805 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4806 I915_WRITE(_3D_CHICKEN3,
4807 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4808
ecdb4eb7 4809 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4810 I915_WRITE(IVB_CHICKEN3,
4811 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4812 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4813
ecdb4eb7 4814 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4815 if (IS_IVB_GT1(dev))
4816 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4817 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4818 else
4819 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4820 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4821
ecdb4eb7 4822 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4823 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4824 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4825
ecdb4eb7 4826 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4827 I915_WRITE(GEN7_L3CNTLREG1,
4828 GEN7_WA_FOR_GEN7_L3_CONTROL);
4829 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4830 GEN7_WA_L3_CHICKEN_MODE);
4831 if (IS_IVB_GT1(dev))
4832 I915_WRITE(GEN7_ROW_CHICKEN2,
4833 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4834 else
4835 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4836 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4837
6f1d69b0 4838
ecdb4eb7 4839 /* WaForceL3Serialization:ivb */
61939d97
JB		 4840 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4841 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4842
0f846f81
JB		 4843 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4844 * gating disable must be set. Failure to set it results in
4845 * flickering pixels due to Z write ordering failures after
4846 * some amount of runtime in the Mesa "fire" demo, and Unigine
4847 * Sanctuary and Tropics, and apparently anything else with
4848 * alpha test or pixel discard.
4849 *
4850 * According to the spec, bit 11 (RCCUNIT) must also be set,
4851 * but we didn't debug actual testcases to find it out.
4852 *
4853 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4854 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4855 */
4856 I915_WRITE(GEN6_UCGCTL2,
4857 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4858 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4859
ecdb4eb7 4860 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4861 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4862 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4863 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4864
0e088b8f 4865 g4x_disable_trickle_feed(dev);
6f1d69b0 4866
ecdb4eb7 4867 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4868 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4869 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4870
ecdb4eb7 4871 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4872 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4873
ecdb4eb7 4874 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4875 I915_WRITE(CACHE_MODE_1,
4876 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4877
4878 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4879 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4880 snpcr |= GEN6_MBC_SNPCR_MED;
4881 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4882
ab5c608b
BW		 4883 if (!HAS_PCH_NOP(dev))
4884 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4885
4886 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4887}
4888
1fa61106 4889static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4890{
4891 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4892
d7fe0cc0 4893 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4894
ecdb4eb7 4895 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4896 I915_WRITE(_3D_CHICKEN3,
4897 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4898
ecdb4eb7 4899 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4900 I915_WRITE(IVB_CHICKEN3,
4901 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4902 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4903
ecdb4eb7 4904 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4905 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4906 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4907 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4908
ecdb4eb7 4909 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4910 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4911 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4912
ecdb4eb7 4913 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4914 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4915 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4916
ecdb4eb7 4917 /* WaForceL3Serialization:vlv */
61939d97
JB		 4918 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4919 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4920
ecdb4eb7 4921 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4922 I915_WRITE(GEN7_ROW_CHICKEN2,
4923 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4924
ecdb4eb7 4925 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4926 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4927 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4928 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4929
ecdb4eb7 4930 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4931 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4932 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4933
0f846f81
JB		 4934
4935 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4936 * gating disable must be set. Failure to set it results in
4937 * flickering pixels due to Z write ordering failures after
4938 * some amount of runtime in the Mesa "fire" demo, and Unigine
4939 * Sanctuary and Tropics, and apparently anything else with
4940 * alpha test or pixel discard.
4941 *
4942 * According to the spec, bit 11 (RCCUNIT) must also be set,
4943 * but we didn't debug actual testcases to find it out.
4944 *
4945 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4946 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4947 *
ecdb4eb7
DL		 4948 * Also apply WaDisableVDSUnitClockGating:vlv and
4949 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4950 */
4951 I915_WRITE(GEN6_UCGCTL2,
4952 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4953 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4954 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4955 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4956 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4957
e3f33d46
JB		 4958 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4959
e0d8d59b 4960 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4961
6b26c86d
DV		 4962 I915_WRITE(CACHE_MODE_1,
4963 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4964
2d809570 4965 /*
ecdb4eb7 4966 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4967 * Disable clock gating on th GCFG unit to prevent a delay
4968 * in the reporting of vblank events.
4969 */
4e8c84a5
JB		 4970 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4971
4972 /* Conservative clock gating settings for now */
4973 I915_WRITE(0x9400, 0xffffffff);
4974 I915_WRITE(0x9404, 0xffffffff);
4975 I915_WRITE(0x9408, 0xffffffff);
4976 I915_WRITE(0x940c, 0xffffffff);
4977 I915_WRITE(0x9410, 0xffffffff);
4978 I915_WRITE(0x9414, 0xffffffff);
4979 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4980}
4981
1fa61106 4982static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 uint32_t dspclk_gate;
4986
4987 I915_WRITE(RENCLK_GATE_D1, 0);
4988 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4989 GS_UNIT_CLOCK_GATE_DISABLE |
4990 CL_UNIT_CLOCK_GATE_DISABLE);
4991 I915_WRITE(RAMCLK_GATE_D, 0);
4992 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4993 OVRUNIT_CLOCK_GATE_DISABLE |
4994 OVCUNIT_CLOCK_GATE_DISABLE;
4995 if (IS_GM45(dev))
4996 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4997 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4998
4999 /* WaDisableRenderCachePipelinedFlush */
5000 I915_WRITE(CACHE_MODE_0,
5001 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5002
0e088b8f 5003 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5004}
5005
1fa61106 5006static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5007{
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009
5010 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5011 I915_WRITE(RENCLK_GATE_D2, 0);
5012 I915_WRITE(DSPCLK_GATE_D, 0);
5013 I915_WRITE(RAMCLK_GATE_D, 0);
5014 I915_WRITE16(DEUC, 0);
20f94967
VS		 5015 I915_WRITE(MI_ARB_STATE,
5016 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5017}
5018
1fa61106 5019static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5020{
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022
5023 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5024 I965_RCC_CLOCK_GATE_DISABLE |
5025 I965_RCPB_CLOCK_GATE_DISABLE |
5026 I965_ISC_CLOCK_GATE_DISABLE |
5027 I965_FBC_CLOCK_GATE_DISABLE);
5028 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5029 I915_WRITE(MI_ARB_STATE,
5030 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5031}
5032
1fa61106 5033static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5034{
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 u32 dstate = I915_READ(D_STATE);
5037
5038 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5039 DSTATE_DOT_CLOCK_GATING;
5040 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5041
5042 if (IS_PINEVIEW(dev))
5043 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5044
5045 /* IIR "flip pending" means done if this bit is set */
5046 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5047}
5048
1fa61106 5049static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5050{
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052
5053 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5054}
5055
1fa61106 5056static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5057{
5058 struct drm_i915_private *dev_priv = dev->dev_private;
5059
5060 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5061}
5062
6f1d69b0
ED		 5063void intel_init_clock_gating(struct drm_device *dev)
5064{
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066
5067 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5068}
5069
7d708ee4
ID		 5070void intel_suspend_hw(struct drm_device *dev)
5071{
5072 if (HAS_PCH_LPT(dev))
5073 lpt_suspend_hw(dev);
5074}
5075
15d199ea
PZ		 5076/**
5077 * We should only use the power well if we explicitly asked the hardware to
5078 * enable it, so check if it's enabled and also check if we've requested it to
5079 * be enabled.
5080 */
b97186f0
PZ		 5081bool intel_display_power_enabled(struct drm_device *dev,
5082 enum intel_display_power_domain domain)
15d199ea
PZ		 5083{
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085
b97186f0
PZ		 5086 if (!HAS_POWER_WELL(dev))
5087 return true;
5088
5089 switch (domain) {
5090 case POWER_DOMAIN_PIPE_A:
5091 case POWER_DOMAIN_TRANSCODER_EDP:
5092 return true;
5093 case POWER_DOMAIN_PIPE_B:
5094 case POWER_DOMAIN_PIPE_C:
5095 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5096 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5097 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5098 case POWER_DOMAIN_TRANSCODER_A:
5099 case POWER_DOMAIN_TRANSCODER_B:
5100 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5101 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5102 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5103 default:
5104 BUG();
5105 }
15d199ea
PZ		 5106}
5107
a38911a3 5108static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5109{
5110 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5111 bool is_enabled, enable_requested;
5112 uint32_t tmp;
d0d3e513 5113
fa42e23c
PZ		 5114 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5115 is_enabled = tmp & HSW_PWR_WELL_STATE;
5116 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5117
fa42e23c
PZ		 5118 if (enable) {
5119 if (!enable_requested)
5120 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5121
fa42e23c
PZ		 5122 if (!is_enabled) {
5123 DRM_DEBUG_KMS("Enabling power well\n");
5124 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5125 HSW_PWR_WELL_STATE), 20))
5126 DRM_ERROR("Timeout enabling power well\n");
5127 }
5128 } else {
5129 if (enable_requested) {
5130 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5131 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5132 }
5133 }
fa42e23c 5134}
d0d3e513 5135
a38911a3
WX		 5136static struct i915_power_well *hsw_pwr;
5137
5138/* Display audio driver power well request */
5139void i915_request_power_well(void)
5140{
5141 if (WARN_ON(!hsw_pwr))
5142 return;
5143
5144 spin_lock_irq(&hsw_pwr->lock);
5145 if (!hsw_pwr->count++ &&
5146 !hsw_pwr->i915_request)
5147 __intel_set_power_well(hsw_pwr->device, true);
5148 spin_unlock_irq(&hsw_pwr->lock);
5149}
5150EXPORT_SYMBOL_GPL(i915_request_power_well);
5151
5152/* Display audio driver power well release */
5153void i915_release_power_well(void)
5154{
5155 if (WARN_ON(!hsw_pwr))
5156 return;
5157
5158 spin_lock_irq(&hsw_pwr->lock);
5159 WARN_ON(!hsw_pwr->count);
5160 if (!--hsw_pwr->count &&
5161 !hsw_pwr->i915_request)
5162 __intel_set_power_well(hsw_pwr->device, false);
5163 spin_unlock_irq(&hsw_pwr->lock);
5164}
5165EXPORT_SYMBOL_GPL(i915_release_power_well);
5166
5167int i915_init_power_well(struct drm_device *dev)
5168{
5169 struct drm_i915_private *dev_priv = dev->dev_private;
5170
5171 hsw_pwr = &dev_priv->power_well;
5172
5173 hsw_pwr->device = dev;
5174 spin_lock_init(&hsw_pwr->lock);
5175 hsw_pwr->count = 0;
5176
5177 return 0;
5178}
5179
5180void i915_remove_power_well(struct drm_device *dev)
5181{
5182 hsw_pwr = NULL;
5183}
5184
5185void intel_set_power_well(struct drm_device *dev, bool enable)
5186{
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5188 struct i915_power_well *power_well = &dev_priv->power_well;
5189
5190 if (!HAS_POWER_WELL(dev))
5191 return;
5192
5193 if (!i915_disable_power_well && !enable)
5194 return;
5195
5196 spin_lock_irq(&power_well->lock);
5197 power_well->i915_request = enable;
5198
5199 /* only reject "disable" power well request */
5200 if (power_well->count && !enable) {
5201 spin_unlock_irq(&power_well->lock);
5202 return;
5203 }
5204
5205 __intel_set_power_well(dev, enable);
5206 spin_unlock_irq(&power_well->lock);
5207}
5208
fa42e23c
PZ		 5209/*
5210 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5211 * when not needed anymore. We have 4 registers that can request the power well
5212 * to be enabled, and it will only be disabled if none of the registers is
5213 * requesting it to be enabled.
d0d3e513 5214 */
fa42e23c 5215void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5216{
5217 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5218
86d52df6 5219 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5220 return;
5221
fa42e23c
PZ		 5222 /* For now, we need the power well to be always enabled. */
5223 intel_set_power_well(dev, true);
d0d3e513 5224
fa42e23c
PZ		 5225 /* We're taking over the BIOS, so clear any requests made by it since
5226 * the driver is in charge now. */
5227 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5228 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5229}
5230
1fa61106
ED		 5231/* Set up chip specific power management-related functions */
5232void intel_init_pm(struct drm_device *dev)
5233{
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235
5236 if (I915_HAS_FBC(dev)) {
5237 if (HAS_PCH_SPLIT(dev)) {
5238 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5239 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5240 dev_priv->display.enable_fbc =
5241 gen7_enable_fbc;
5242 else
5243 dev_priv->display.enable_fbc =
5244 ironlake_enable_fbc;
1fa61106
ED		 5245 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5246 } else if (IS_GM45(dev)) {
5247 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5248 dev_priv->display.enable_fbc = g4x_enable_fbc;
5249 dev_priv->display.disable_fbc = g4x_disable_fbc;
5250 } else if (IS_CRESTLINE(dev)) {
5251 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5252 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5253 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5254 }
5255 /* 855GM needs testing */
5256 }
5257
c921aba8
DV		 5258 /* For cxsr */
5259 if (IS_PINEVIEW(dev))
5260 i915_pineview_get_mem_freq(dev);
5261 else if (IS_GEN5(dev))
5262 i915_ironlake_get_mem_freq(dev);
5263
1fa61106
ED		 5264 /* For FIFO watermark updates */
5265 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5266 intel_setup_wm_latency(dev);
5267
1fa61106 5268 if (IS_GEN5(dev)) {
53615a5e
VS		 5269 if (dev_priv->wm.pri_latency[1] &&
5270 dev_priv->wm.spr_latency[1] &&
5271 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5272 dev_priv->display.update_wm = ironlake_update_wm;
5273 else {
5274 DRM_DEBUG_KMS("Failed to get proper latency. "
5275 "Disable CxSR\n");
5276 dev_priv->display.update_wm = NULL;
5277 }
5278 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5279 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5280 if (dev_priv->wm.pri_latency[0] &&
5281 dev_priv->wm.spr_latency[0] &&
5282 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5283 dev_priv->display.update_wm = sandybridge_update_wm;
5284 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5285 } else {
5286 DRM_DEBUG_KMS("Failed to read display plane latency. "
5287 "Disable CxSR\n");
5288 dev_priv->display.update_wm = NULL;
5289 }
5290 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5291 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5292 if (dev_priv->wm.pri_latency[0] &&
5293 dev_priv->wm.spr_latency[0] &&
5294 dev_priv->wm.cur_latency[0]) {
c43d0188 5295 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5296 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5297 } else {
5298 DRM_DEBUG_KMS("Failed to read display plane latency. "
5299 "Disable CxSR\n");
5300 dev_priv->display.update_wm = NULL;
5301 }
5302 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5303 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5304 if (dev_priv->wm.pri_latency[0] &&
5305 dev_priv->wm.spr_latency[0] &&
5306 dev_priv->wm.cur_latency[0]) {
1011d8c4 5307 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5308 dev_priv->display.update_sprite_wm =
5309 haswell_update_sprite_wm;
6b8a5eeb
ED		 5310 } else {
5311 DRM_DEBUG_KMS("Failed to read display plane latency. "
5312 "Disable CxSR\n");
5313 dev_priv->display.update_wm = NULL;
5314 }
cad2a2d7 5315 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5316 } else
5317 dev_priv->display.update_wm = NULL;
5318 } else if (IS_VALLEYVIEW(dev)) {
5319 dev_priv->display.update_wm = valleyview_update_wm;
5320 dev_priv->display.init_clock_gating =
5321 valleyview_init_clock_gating;
1fa61106
ED		 5322 } else if (IS_PINEVIEW(dev)) {
5323 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5324 dev_priv->is_ddr3,
5325 dev_priv->fsb_freq,
5326 dev_priv->mem_freq)) {
5327 DRM_INFO("failed to find known CxSR latency "
5328 "(found ddr%s fsb freq %d, mem freq %d), "
5329 "disabling CxSR\n",
5330 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5331 dev_priv->fsb_freq, dev_priv->mem_freq);
5332 /* Disable CxSR and never update its watermark again */
5333 pineview_disable_cxsr(dev);
5334 dev_priv->display.update_wm = NULL;
5335 } else
5336 dev_priv->display.update_wm = pineview_update_wm;
5337 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5338 } else if (IS_G4X(dev)) {
5339 dev_priv->display.update_wm = g4x_update_wm;
5340 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5341 } else if (IS_GEN4(dev)) {
5342 dev_priv->display.update_wm = i965_update_wm;
5343 if (IS_CRESTLINE(dev))
5344 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5345 else if (IS_BROADWATER(dev))
5346 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5347 } else if (IS_GEN3(dev)) {
5348 dev_priv->display.update_wm = i9xx_update_wm;
5349 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5350 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5351 } else if (IS_I865G(dev)) {
5352 dev_priv->display.update_wm = i830_update_wm;
5353 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5354 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5355 } else if (IS_I85X(dev)) {
5356 dev_priv->display.update_wm = i9xx_update_wm;
5357 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5358 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5359 } else {
5360 dev_priv->display.update_wm = i830_update_wm;
5361 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5362 if (IS_845G(dev))
5363 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5364 else
5365 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5366 }
5367}
5368
42c0526c
BW		 5369int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5370{
4fc688ce 5371 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5372
5373 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5374 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5375 return -EAGAIN;
5376 }
5377
5378 I915_WRITE(GEN6_PCODE_DATA, *val);
5379 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5380
5381 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5382 500)) {
5383 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5384 return -ETIMEDOUT;
5385 }
5386
5387 *val = I915_READ(GEN6_PCODE_DATA);
5388 I915_WRITE(GEN6_PCODE_DATA, 0);
5389
5390 return 0;
5391}
5392
5393int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5394{
4fc688ce 5395 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5396
5397 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5398 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5399 return -EAGAIN;
5400 }
5401
5402 I915_WRITE(GEN6_PCODE_DATA, val);
5403 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5404
5405 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5406 500)) {
5407 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5408 return -ETIMEDOUT;
5409 }
5410
5411 I915_WRITE(GEN6_PCODE_DATA, 0);
5412
5413 return 0;
5414}
a0e4e199 5415
855ba3be
JB		 5416int vlv_gpu_freq(int ddr_freq, int val)
5417{
5418 int mult, base;
5419
5420 switch (ddr_freq) {
5421 case 800:
5422 mult = 20;
5423 base = 120;
5424 break;
5425 case 1066:
5426 mult = 22;
5427 base = 133;
5428 break;
5429 case 1333:
5430 mult = 21;
5431 base = 125;
5432 break;
5433 default:
5434 return -1;
5435 }
5436
5437 return ((val - 0xbd) * mult) + base;
5438}
5439
5440int vlv_freq_opcode(int ddr_freq, int val)
5441{
5442 int mult, base;
5443
5444 switch (ddr_freq) {
5445 case 800:
5446 mult = 20;
5447 base = 120;
5448 break;
5449 case 1066:
5450 mult = 22;
5451 base = 133;
5452 break;
5453 case 1333:
5454 mult = 21;
5455 base = 125;
5456 break;
5457 default:
5458 return -1;
5459 }
5460
5461 val /= mult;
5462 val -= base / mult;
5463 val += 0xbd;
5464
5465 if (val > 0xea)
5466 val = 0xea;
5467
5468 return val;
5469}
5470
907b28c5
CW		 5471void intel_pm_init(struct drm_device *dev)
5472{
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474
5475 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5476 intel_gen6_powersave_work);
5477}
5478
Linux kernel - Deliverables
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