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drm/i915: hw state readout support for pixel_multiplier
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
3490ea5d
CW		 47static bool intel_crtc_active(struct drm_crtc *crtc)
48{
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53}
54
1fa61106 55static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 56{
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75}
76
1fa61106 77static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 78{
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
84f44ce7
VS		 116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 118}
119
1fa61106 120static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125}
126
1fa61106 127static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 128{
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
84f44ce7 151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 152}
153
1fa61106 154static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 155{
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167}
168
1fa61106 169static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 170{
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174}
175
176static void sandybridge_blit_fbc_update(struct drm_device *dev)
177{
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194}
195
1fa61106 196static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 197{
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
84f44ce7 231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 232}
233
1fa61106 234static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
b74ea102 245 if (IS_IVYBRIDGE(dev))
7dd23ba0 246 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 247 I915_WRITE(ILK_DSPCLK_GATE_D,
248 I915_READ(ILK_DSPCLK_GATE_D) &
249 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
250
d89f2071 251 if (IS_HASWELL(dev))
7dd23ba0 252 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 253 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
254 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
255 ~HSW_DPFC_GATING_DISABLE);
256
85208be0
ED		 257 DRM_DEBUG_KMS("disabled FBC\n");
258 }
259}
260
1fa61106 261static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266}
267
abe959c7
RV		 268static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269{
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
277 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
891348b2 283 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 286 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 287 I915_WRITE(ILK_DSPCLK_GATE_D,
288 I915_READ(ILK_DSPCLK_GATE_D) |
289 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 290 } else {
7dd23ba0 291 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 292 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
293 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 294 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 295 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
296 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
297 HSW_DPFC_GATING_DISABLE);
891348b2 298 }
b74ea102 299
abe959c7
RV		 300 I915_WRITE(SNB_DPFC_CTL_SA,
301 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
302 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
303
304 sandybridge_blit_fbc_update(dev);
305
306 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
307}
308
85208be0
ED		 309bool intel_fbc_enabled(struct drm_device *dev)
310{
311 struct drm_i915_private *dev_priv = dev->dev_private;
312
313 if (!dev_priv->display.fbc_enabled)
314 return false;
315
316 return dev_priv->display.fbc_enabled(dev);
317}
318
319static void intel_fbc_work_fn(struct work_struct *__work)
320{
321 struct intel_fbc_work *work =
322 container_of(to_delayed_work(__work),
323 struct intel_fbc_work, work);
324 struct drm_device *dev = work->crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
327 mutex_lock(&dev->struct_mutex);
328 if (work == dev_priv->fbc_work) {
329 /* Double check that we haven't switched fb without cancelling
330 * the prior work.
331 */
332 if (work->crtc->fb == work->fb) {
333 dev_priv->display.enable_fbc(work->crtc,
334 work->interval);
335
336 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->cfb_fb = work->crtc->fb->base.id;
338 dev_priv->cfb_y = work->crtc->y;
339 }
340
341 dev_priv->fbc_work = NULL;
342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346}
347
348static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349{
350 if (dev_priv->fbc_work == NULL)
351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
358 */
359 if (cancel_delayed_work(&dev_priv->fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc_work);
362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
368 dev_priv->fbc_work = NULL;
369}
370
371void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
372{
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
382 work = kzalloc(sizeof *work, GFP_KERNEL);
383 if (work == NULL) {
384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
393 dev_priv->fbc_work = work;
394
395 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
396
397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
402 *
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
421 dev_priv->cfb_plane = -1;
422}
423
424/**
425 * intel_update_fbc - enable/disable FBC as needed
426 * @dev: the drm_device
427 *
428 * Set up the framebuffer compression hardware at mode set time. We
429 * enable it if possible:
430 * - plane A only (on pre-965)
431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard
433 * - no dual wide
434 * - framebuffer <= 2048 in width, 1536 in height
435 *
436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed
438 * one. It also must reside (along with the line length buffer) in
439 * stolen memory.
440 *
441 * We need to enable/disable FBC on a global basis.
442 */
443void intel_update_fbc(struct drm_device *dev)
444{
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 struct drm_crtc *crtc = NULL, *tmp_crtc;
447 struct intel_crtc *intel_crtc;
448 struct drm_framebuffer *fb;
449 struct intel_framebuffer *intel_fb;
450 struct drm_i915_gem_object *obj;
451 int enable_fbc;
452
85208be0
ED		 453 if (!i915_powersave)
454 return;
455
456 if (!I915_HAS_FBC(dev))
457 return;
458
459 /*
460 * If FBC is already on, we just have to verify that we can
461 * keep it that way...
462 * Need to disable if:
463 * - more than one pipe is active
464 * - changing FBC params (stride, fence, mode)
465 * - new fb is too large to fit in compressed buffer
466 * - going to an unsupported config (interlace, pixel multiply, etc.)
467 */
468 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 469 if (intel_crtc_active(tmp_crtc) &&
470 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 471 if (crtc) {
472 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
473 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
474 goto out_disable;
475 }
476 crtc = tmp_crtc;
477 }
478 }
479
480 if (!crtc || crtc->fb == NULL) {
481 DRM_DEBUG_KMS("no output, disabling\n");
482 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
483 goto out_disable;
484 }
485
486 intel_crtc = to_intel_crtc(crtc);
487 fb = crtc->fb;
488 intel_fb = to_intel_framebuffer(fb);
489 obj = intel_fb->obj;
490
491 enable_fbc = i915_enable_fbc;
492 if (enable_fbc < 0) {
493 DRM_DEBUG_KMS("fbc set to per-chip default\n");
494 enable_fbc = 1;
891348b2 495 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
85208be0
ED		 496 enable_fbc = 0;
497 }
498 if (!enable_fbc) {
499 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
501 goto out_disable;
502 }
85208be0
ED		 503 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
504 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
505 DRM_DEBUG_KMS("mode incompatible with compression, "
506 "disabling\n");
507 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
508 goto out_disable;
509 }
510 if ((crtc->mode.hdisplay > 2048) ||
511 (crtc->mode.vdisplay > 1536)) {
512 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
513 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
514 goto out_disable;
515 }
891348b2
RV		 516 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
517 intel_crtc->plane != 0) {
85208be0
ED		 518 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
519 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
520 goto out_disable;
521 }
522
523 /* The use of a CPU fence is mandatory in order to detect writes
524 * by the CPU to the scanout and trigger updates to the FBC.
525 */
526 if (obj->tiling_mode != I915_TILING_X ||
527 obj->fence_reg == I915_FENCE_REG_NONE) {
528 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
529 dev_priv->no_fbc_reason = FBC_NOT_TILED;
530 goto out_disable;
531 }
532
533 /* If the kernel debugger is active, always disable compression */
534 if (in_dbg_master())
535 goto out_disable;
536
11be49eb 537 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
11be49eb
CW		 538 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
539 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
540 goto out_disable;
541 }
542
85208be0
ED		 543 /* If the scanout has not changed, don't modify the FBC settings.
544 * Note that we make the fundamental assumption that the fb->obj
545 * cannot be unpinned (and have its GTT offset and fence revoked)
546 * without first being decoupled from the scanout and FBC disabled.
547 */
548 if (dev_priv->cfb_plane == intel_crtc->plane &&
549 dev_priv->cfb_fb == fb->base.id &&
550 dev_priv->cfb_y == crtc->y)
551 return;
552
553 if (intel_fbc_enabled(dev)) {
554 /* We update FBC along two paths, after changing fb/crtc
555 * configuration (modeswitching) and after page-flipping
556 * finishes. For the latter, we know that not only did
557 * we disable the FBC at the start of the page-flip
558 * sequence, but also more than one vblank has passed.
559 *
560 * For the former case of modeswitching, it is possible
561 * to switch between two FBC valid configurations
562 * instantaneously so we do need to disable the FBC
563 * before we can modify its control registers. We also
564 * have to wait for the next vblank for that to take
565 * effect. However, since we delay enabling FBC we can
566 * assume that a vblank has passed since disabling and
567 * that we can safely alter the registers in the deferred
568 * callback.
569 *
570 * In the scenario that we go from a valid to invalid
571 * and then back to valid FBC configuration we have
572 * no strict enforcement that a vblank occurred since
573 * disabling the FBC. However, along all current pipe
574 * disabling paths we do need to wait for a vblank at
575 * some point. And we wait before enabling FBC anyway.
576 */
577 DRM_DEBUG_KMS("disabling active FBC for update\n");
578 intel_disable_fbc(dev);
579 }
580
581 intel_enable_fbc(crtc, 500);
582 return;
583
584out_disable:
585 /* Multiple disables should be harmless */
586 if (intel_fbc_enabled(dev)) {
587 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
588 intel_disable_fbc(dev);
589 }
11be49eb 590 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 591}
592
c921aba8
DV		 593static void i915_pineview_get_mem_freq(struct drm_device *dev)
594{
595 drm_i915_private_t *dev_priv = dev->dev_private;
596 u32 tmp;
597
598 tmp = I915_READ(CLKCFG);
599
600 switch (tmp & CLKCFG_FSB_MASK) {
601 case CLKCFG_FSB_533:
602 dev_priv->fsb_freq = 533; /* 133*4 */
603 break;
604 case CLKCFG_FSB_800:
605 dev_priv->fsb_freq = 800; /* 200*4 */
606 break;
607 case CLKCFG_FSB_667:
608 dev_priv->fsb_freq = 667; /* 167*4 */
609 break;
610 case CLKCFG_FSB_400:
611 dev_priv->fsb_freq = 400; /* 100*4 */
612 break;
613 }
614
615 switch (tmp & CLKCFG_MEM_MASK) {
616 case CLKCFG_MEM_533:
617 dev_priv->mem_freq = 533;
618 break;
619 case CLKCFG_MEM_667:
620 dev_priv->mem_freq = 667;
621 break;
622 case CLKCFG_MEM_800:
623 dev_priv->mem_freq = 800;
624 break;
625 }
626
627 /* detect pineview DDR3 setting */
628 tmp = I915_READ(CSHRDDR3CTL);
629 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
630}
631
632static void i915_ironlake_get_mem_freq(struct drm_device *dev)
633{
634 drm_i915_private_t *dev_priv = dev->dev_private;
635 u16 ddrpll, csipll;
636
637 ddrpll = I915_READ16(DDRMPLL1);
638 csipll = I915_READ16(CSIPLL0);
639
640 switch (ddrpll & 0xff) {
641 case 0xc:
642 dev_priv->mem_freq = 800;
643 break;
644 case 0x10:
645 dev_priv->mem_freq = 1066;
646 break;
647 case 0x14:
648 dev_priv->mem_freq = 1333;
649 break;
650 case 0x18:
651 dev_priv->mem_freq = 1600;
652 break;
653 default:
654 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
655 ddrpll & 0xff);
656 dev_priv->mem_freq = 0;
657 break;
658 }
659
20e4d407 660 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 661
662 switch (csipll & 0x3ff) {
663 case 0x00c:
664 dev_priv->fsb_freq = 3200;
665 break;
666 case 0x00e:
667 dev_priv->fsb_freq = 3733;
668 break;
669 case 0x010:
670 dev_priv->fsb_freq = 4266;
671 break;
672 case 0x012:
673 dev_priv->fsb_freq = 4800;
674 break;
675 case 0x014:
676 dev_priv->fsb_freq = 5333;
677 break;
678 case 0x016:
679 dev_priv->fsb_freq = 5866;
680 break;
681 case 0x018:
682 dev_priv->fsb_freq = 6400;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
686 csipll & 0x3ff);
687 dev_priv->fsb_freq = 0;
688 break;
689 }
690
691 if (dev_priv->fsb_freq == 3200) {
20e4d407 692 dev_priv->ips.c_m = 0;
c921aba8 693 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 694 dev_priv->ips.c_m = 1;
c921aba8 695 } else {
20e4d407 696 dev_priv->ips.c_m = 2;
c921aba8
DV		 697 }
698}
699
b445e3b0
ED		 700static const struct cxsr_latency cxsr_latency_table[] = {
701 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
702 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
703 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
704 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
705 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
706
707 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
708 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
709 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
710 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
711 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
712
713 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
714 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
715 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
716 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
717 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
718
719 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
720 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
721 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
722 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
723 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
724
725 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
726 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
727 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
728 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
729 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
730
731 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
732 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
733 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
734 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
735 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
736};
737
63c62275 738static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 739 int is_ddr3,
740 int fsb,
741 int mem)
742{
743 const struct cxsr_latency *latency;
744 int i;
745
746 if (fsb == 0 || mem == 0)
747 return NULL;
748
749 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
750 latency = &cxsr_latency_table[i];
751 if (is_desktop == latency->is_desktop &&
752 is_ddr3 == latency->is_ddr3 &&
753 fsb == latency->fsb_freq && mem == latency->mem_freq)
754 return latency;
755 }
756
757 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
758
759 return NULL;
760}
761
1fa61106 762static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765
766 /* deactivate cxsr */
767 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
768}
769
770/*
771 * Latency for FIFO fetches is dependent on several factors:
772 * - memory configuration (speed, channels)
773 * - chipset
774 * - current MCH state
775 * It can be fairly high in some situations, so here we assume a fairly
776 * pessimal value. It's a tradeoff between extra memory fetches (if we
777 * set this value too high, the FIFO will fetch frequently to stay full)
778 * and power consumption (set it too low to save power and we might see
779 * FIFO underruns and display "flicker").
780 *
781 * A value of 5us seems to be a good balance; safe for very low end
782 * platforms but not overly aggressive on lower latency configs.
783 */
784static const int latency_ns = 5000;
785
1fa61106 786static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 787{
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 uint32_t dsparb = I915_READ(DSPARB);
790 int size;
791
792 size = dsparb & 0x7f;
793 if (plane)
794 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
795
796 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
797 plane ? "B" : "A", size);
798
799 return size;
800}
801
1fa61106 802static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 803{
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 uint32_t dsparb = I915_READ(DSPARB);
806 int size;
807
808 size = dsparb & 0x1ff;
809 if (plane)
810 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
811 size >>= 1; /* Convert to cachelines */
812
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
815
816 return size;
817}
818
1fa61106 819static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 820{
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
823 int size;
824
825 size = dsparb & 0x7f;
826 size >>= 2; /* Convert to cachelines */
827
828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
829 plane ? "B" : "A",
830 size);
831
832 return size;
833}
834
1fa61106 835static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 836{
837 struct drm_i915_private *dev_priv = dev->dev_private;
838 uint32_t dsparb = I915_READ(DSPARB);
839 int size;
840
841 size = dsparb & 0x7f;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
850/* Pineview has different values for various configs */
851static const struct intel_watermark_params pineview_display_wm = {
852 PINEVIEW_DISPLAY_FIFO,
853 PINEVIEW_MAX_WM,
854 PINEVIEW_DFT_WM,
855 PINEVIEW_GUARD_WM,
856 PINEVIEW_FIFO_LINE_SIZE
857};
858static const struct intel_watermark_params pineview_display_hplloff_wm = {
859 PINEVIEW_DISPLAY_FIFO,
860 PINEVIEW_MAX_WM,
861 PINEVIEW_DFT_HPLLOFF_WM,
862 PINEVIEW_GUARD_WM,
863 PINEVIEW_FIFO_LINE_SIZE
864};
865static const struct intel_watermark_params pineview_cursor_wm = {
866 PINEVIEW_CURSOR_FIFO,
867 PINEVIEW_CURSOR_MAX_WM,
868 PINEVIEW_CURSOR_DFT_WM,
869 PINEVIEW_CURSOR_GUARD_WM,
870 PINEVIEW_FIFO_LINE_SIZE,
871};
872static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
873 PINEVIEW_CURSOR_FIFO,
874 PINEVIEW_CURSOR_MAX_WM,
875 PINEVIEW_CURSOR_DFT_WM,
876 PINEVIEW_CURSOR_GUARD_WM,
877 PINEVIEW_FIFO_LINE_SIZE
878};
879static const struct intel_watermark_params g4x_wm_info = {
880 G4X_FIFO_SIZE,
881 G4X_MAX_WM,
882 G4X_MAX_WM,
883 2,
884 G4X_FIFO_LINE_SIZE,
885};
886static const struct intel_watermark_params g4x_cursor_wm_info = {
887 I965_CURSOR_FIFO,
888 I965_CURSOR_MAX_WM,
889 I965_CURSOR_DFT_WM,
890 2,
891 G4X_FIFO_LINE_SIZE,
892};
893static const struct intel_watermark_params valleyview_wm_info = {
894 VALLEYVIEW_FIFO_SIZE,
895 VALLEYVIEW_MAX_WM,
896 VALLEYVIEW_MAX_WM,
897 2,
898 G4X_FIFO_LINE_SIZE,
899};
900static const struct intel_watermark_params valleyview_cursor_wm_info = {
901 I965_CURSOR_FIFO,
902 VALLEYVIEW_CURSOR_MAX_WM,
903 I965_CURSOR_DFT_WM,
904 2,
905 G4X_FIFO_LINE_SIZE,
906};
907static const struct intel_watermark_params i965_cursor_wm_info = {
908 I965_CURSOR_FIFO,
909 I965_CURSOR_MAX_WM,
910 I965_CURSOR_DFT_WM,
911 2,
912 I915_FIFO_LINE_SIZE,
913};
914static const struct intel_watermark_params i945_wm_info = {
915 I945_FIFO_SIZE,
916 I915_MAX_WM,
917 1,
918 2,
919 I915_FIFO_LINE_SIZE
920};
921static const struct intel_watermark_params i915_wm_info = {
922 I915_FIFO_SIZE,
923 I915_MAX_WM,
924 1,
925 2,
926 I915_FIFO_LINE_SIZE
927};
928static const struct intel_watermark_params i855_wm_info = {
929 I855GM_FIFO_SIZE,
930 I915_MAX_WM,
931 1,
932 2,
933 I830_FIFO_LINE_SIZE
934};
935static const struct intel_watermark_params i830_wm_info = {
936 I830_FIFO_SIZE,
937 I915_MAX_WM,
938 1,
939 2,
940 I830_FIFO_LINE_SIZE
941};
942
943static const struct intel_watermark_params ironlake_display_wm_info = {
944 ILK_DISPLAY_FIFO,
945 ILK_DISPLAY_MAXWM,
946 ILK_DISPLAY_DFTWM,
947 2,
948 ILK_FIFO_LINE_SIZE
949};
950static const struct intel_watermark_params ironlake_cursor_wm_info = {
951 ILK_CURSOR_FIFO,
952 ILK_CURSOR_MAXWM,
953 ILK_CURSOR_DFTWM,
954 2,
955 ILK_FIFO_LINE_SIZE
956};
957static const struct intel_watermark_params ironlake_display_srwm_info = {
958 ILK_DISPLAY_SR_FIFO,
959 ILK_DISPLAY_MAX_SRWM,
960 ILK_DISPLAY_DFT_SRWM,
961 2,
962 ILK_FIFO_LINE_SIZE
963};
964static const struct intel_watermark_params ironlake_cursor_srwm_info = {
965 ILK_CURSOR_SR_FIFO,
966 ILK_CURSOR_MAX_SRWM,
967 ILK_CURSOR_DFT_SRWM,
968 2,
969 ILK_FIFO_LINE_SIZE
970};
971
972static const struct intel_watermark_params sandybridge_display_wm_info = {
973 SNB_DISPLAY_FIFO,
974 SNB_DISPLAY_MAXWM,
975 SNB_DISPLAY_DFTWM,
976 2,
977 SNB_FIFO_LINE_SIZE
978};
979static const struct intel_watermark_params sandybridge_cursor_wm_info = {
980 SNB_CURSOR_FIFO,
981 SNB_CURSOR_MAXWM,
982 SNB_CURSOR_DFTWM,
983 2,
984 SNB_FIFO_LINE_SIZE
985};
986static const struct intel_watermark_params sandybridge_display_srwm_info = {
987 SNB_DISPLAY_SR_FIFO,
988 SNB_DISPLAY_MAX_SRWM,
989 SNB_DISPLAY_DFT_SRWM,
990 2,
991 SNB_FIFO_LINE_SIZE
992};
993static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
994 SNB_CURSOR_SR_FIFO,
995 SNB_CURSOR_MAX_SRWM,
996 SNB_CURSOR_DFT_SRWM,
997 2,
998 SNB_FIFO_LINE_SIZE
999};
1000
1001
1002/**
1003 * intel_calculate_wm - calculate watermark level
1004 * @clock_in_khz: pixel clock
1005 * @wm: chip FIFO params
1006 * @pixel_size: display pixel size
1007 * @latency_ns: memory latency for the platform
1008 *
1009 * Calculate the watermark level (the level at which the display plane will
1010 * start fetching from memory again). Each chip has a different display
1011 * FIFO size and allocation, so the caller needs to figure that out and pass
1012 * in the correct intel_watermark_params structure.
1013 *
1014 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015 * on the pixel size. When it reaches the watermark level, it'll start
1016 * fetching FIFO line sized based chunks from memory until the FIFO fills
1017 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1018 * will occur, and a display engine hang could result.
1019 */
1020static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1021 const struct intel_watermark_params *wm,
1022 int fifo_size,
1023 int pixel_size,
1024 unsigned long latency_ns)
1025{
1026 long entries_required, wm_size;
1027
1028 /*
1029 * Note: we need to make sure we don't overflow for various clock &
1030 * latency values.
1031 * clocks go from a few thousand to several hundred thousand.
1032 * latency is usually a few thousand
1033 */
1034 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1035 1000;
1036 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1037
1038 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1039
1040 wm_size = fifo_size - (entries_required + wm->guard_size);
1041
1042 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1043
1044 /* Don't promote wm_size to unsigned... */
1045 if (wm_size > (long)wm->max_wm)
1046 wm_size = wm->max_wm;
1047 if (wm_size <= 0)
1048 wm_size = wm->default_wm;
1049 return wm_size;
1050}
1051
1052static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1053{
1054 struct drm_crtc *crtc, *enabled = NULL;
1055
1056 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1057 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1058 if (enabled)
1059 return NULL;
1060 enabled = crtc;
1061 }
1062 }
1063
1064 return enabled;
1065}
1066
1fa61106 1067static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1068{
1069 struct drm_i915_private *dev_priv = dev->dev_private;
1070 struct drm_crtc *crtc;
1071 const struct cxsr_latency *latency;
1072 u32 reg;
1073 unsigned long wm;
1074
1075 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1076 dev_priv->fsb_freq, dev_priv->mem_freq);
1077 if (!latency) {
1078 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079 pineview_disable_cxsr(dev);
1080 return;
1081 }
1082
1083 crtc = single_enabled_crtc(dev);
1084 if (crtc) {
1085 int clock = crtc->mode.clock;
1086 int pixel_size = crtc->fb->bits_per_pixel / 8;
1087
1088 /* Display SR */
1089 wm = intel_calculate_wm(clock, &pineview_display_wm,
1090 pineview_display_wm.fifo_size,
1091 pixel_size, latency->display_sr);
1092 reg = I915_READ(DSPFW1);
1093 reg &= ~DSPFW_SR_MASK;
1094 reg |= wm << DSPFW_SR_SHIFT;
1095 I915_WRITE(DSPFW1, reg);
1096 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1097
1098 /* cursor SR */
1099 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1100 pineview_display_wm.fifo_size,
1101 pixel_size, latency->cursor_sr);
1102 reg = I915_READ(DSPFW3);
1103 reg &= ~DSPFW_CURSOR_SR_MASK;
1104 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1105 I915_WRITE(DSPFW3, reg);
1106
1107 /* Display HPLL off SR */
1108 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1109 pineview_display_hplloff_wm.fifo_size,
1110 pixel_size, latency->display_hpll_disable);
1111 reg = I915_READ(DSPFW3);
1112 reg &= ~DSPFW_HPLL_SR_MASK;
1113 reg |= wm & DSPFW_HPLL_SR_MASK;
1114 I915_WRITE(DSPFW3, reg);
1115
1116 /* cursor HPLL off SR */
1117 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1118 pineview_display_hplloff_wm.fifo_size,
1119 pixel_size, latency->cursor_hpll_disable);
1120 reg = I915_READ(DSPFW3);
1121 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1122 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1123 I915_WRITE(DSPFW3, reg);
1124 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1125
1126 /* activate cxsr */
1127 I915_WRITE(DSPFW3,
1128 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1129 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1130 } else {
1131 pineview_disable_cxsr(dev);
1132 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1133 }
1134}
1135
1136static bool g4x_compute_wm0(struct drm_device *dev,
1137 int plane,
1138 const struct intel_watermark_params *display,
1139 int display_latency_ns,
1140 const struct intel_watermark_params *cursor,
1141 int cursor_latency_ns,
1142 int *plane_wm,
1143 int *cursor_wm)
1144{
1145 struct drm_crtc *crtc;
1146 int htotal, hdisplay, clock, pixel_size;
1147 int line_time_us, line_count;
1148 int entries, tlb_miss;
1149
1150 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1151 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1152 *cursor_wm = cursor->guard_size;
1153 *plane_wm = display->guard_size;
1154 return false;
1155 }
1156
1157 htotal = crtc->mode.htotal;
1158 hdisplay = crtc->mode.hdisplay;
1159 clock = crtc->mode.clock;
1160 pixel_size = crtc->fb->bits_per_pixel / 8;
1161
1162 /* Use the small buffer method to calculate plane watermark */
1163 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1164 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1165 if (tlb_miss > 0)
1166 entries += tlb_miss;
1167 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1168 *plane_wm = entries + display->guard_size;
1169 if (*plane_wm > (int)display->max_wm)
1170 *plane_wm = display->max_wm;
1171
1172 /* Use the large buffer method to calculate cursor watermark */
1173 line_time_us = ((htotal * 1000) / clock);
1174 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1175 entries = line_count * 64 * pixel_size;
1176 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1177 if (tlb_miss > 0)
1178 entries += tlb_miss;
1179 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1180 *cursor_wm = entries + cursor->guard_size;
1181 if (*cursor_wm > (int)cursor->max_wm)
1182 *cursor_wm = (int)cursor->max_wm;
1183
1184 return true;
1185}
1186
1187/*
1188 * Check the wm result.
1189 *
1190 * If any calculated watermark values is larger than the maximum value that
1191 * can be programmed into the associated watermark register, that watermark
1192 * must be disabled.
1193 */
1194static bool g4x_check_srwm(struct drm_device *dev,
1195 int display_wm, int cursor_wm,
1196 const struct intel_watermark_params *display,
1197 const struct intel_watermark_params *cursor)
1198{
1199 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200 display_wm, cursor_wm);
1201
1202 if (display_wm > display->max_wm) {
1203 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204 display_wm, display->max_wm);
1205 return false;
1206 }
1207
1208 if (cursor_wm > cursor->max_wm) {
1209 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210 cursor_wm, cursor->max_wm);
1211 return false;
1212 }
1213
1214 if (!(display_wm || cursor_wm)) {
1215 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1216 return false;
1217 }
1218
1219 return true;
1220}
1221
1222static bool g4x_compute_srwm(struct drm_device *dev,
1223 int plane,
1224 int latency_ns,
1225 const struct intel_watermark_params *display,
1226 const struct intel_watermark_params *cursor,
1227 int *display_wm, int *cursor_wm)
1228{
1229 struct drm_crtc *crtc;
1230 int hdisplay, htotal, pixel_size, clock;
1231 unsigned long line_time_us;
1232 int line_count, line_size;
1233 int small, large;
1234 int entries;
1235
1236 if (!latency_ns) {
1237 *display_wm = *cursor_wm = 0;
1238 return false;
1239 }
1240
1241 crtc = intel_get_crtc_for_plane(dev, plane);
1242 hdisplay = crtc->mode.hdisplay;
1243 htotal = crtc->mode.htotal;
1244 clock = crtc->mode.clock;
1245 pixel_size = crtc->fb->bits_per_pixel / 8;
1246
1247 line_time_us = (htotal * 1000) / clock;
1248 line_count = (latency_ns / line_time_us + 1000) / 1000;
1249 line_size = hdisplay * pixel_size;
1250
1251 /* Use the minimum of the small and large buffer method for primary */
1252 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1253 large = line_count * line_size;
1254
1255 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1256 *display_wm = entries + display->guard_size;
1257
1258 /* calculate the self-refresh watermark for display cursor */
1259 entries = line_count * pixel_size * 64;
1260 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1261 *cursor_wm = entries + cursor->guard_size;
1262
1263 return g4x_check_srwm(dev,
1264 *display_wm, *cursor_wm,
1265 display, cursor);
1266}
1267
1268static bool vlv_compute_drain_latency(struct drm_device *dev,
1269 int plane,
1270 int *plane_prec_mult,
1271 int *plane_dl,
1272 int *cursor_prec_mult,
1273 int *cursor_dl)
1274{
1275 struct drm_crtc *crtc;
1276 int clock, pixel_size;
1277 int entries;
1278
1279 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1280 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1281 return false;
1282
1283 clock = crtc->mode.clock; /* VESA DOT Clock */
1284 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1285
1286 entries = (clock / 1000) * pixel_size;
1287 *plane_prec_mult = (entries > 256) ?
1288 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1289 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1290 pixel_size);
1291
1292 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1293 *cursor_prec_mult = (entries > 256) ?
1294 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1296
1297 return true;
1298}
1299
1300/*
1301 * Update drain latency registers of memory arbiter
1302 *
1303 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304 * to be programmed. Each plane has a drain latency multiplier and a drain
1305 * latency value.
1306 */
1307
1308static void vlv_update_drain_latency(struct drm_device *dev)
1309{
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1312 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1313 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1314 either 16 or 32 */
1315
1316 /* For plane A, Cursor A */
1317 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1318 &cursor_prec_mult, &cursora_dl)) {
1319 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1320 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1321 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1322 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1323
1324 I915_WRITE(VLV_DDL1, cursora_prec |
1325 (cursora_dl << DDL_CURSORA_SHIFT) |
1326 planea_prec | planea_dl);
1327 }
1328
1329 /* For plane B, Cursor B */
1330 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1331 &cursor_prec_mult, &cursorb_dl)) {
1332 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1333 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1334 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1335 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1336
1337 I915_WRITE(VLV_DDL2, cursorb_prec |
1338 (cursorb_dl << DDL_CURSORB_SHIFT) |
1339 planeb_prec | planeb_dl);
1340 }
1341}
1342
1343#define single_plane_enabled(mask) is_power_of_2(mask)
1344
1fa61106 1345static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1346{
1347 static const int sr_latency_ns = 12000;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350 int plane_sr, cursor_sr;
af6c4575 1351 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1352 unsigned int enabled = 0;
1353
1354 vlv_update_drain_latency(dev);
1355
51cea1f4 1356 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1357 &valleyview_wm_info, latency_ns,
1358 &valleyview_cursor_wm_info, latency_ns,
1359 &planea_wm, &cursora_wm))
51cea1f4 1360 enabled |= 1 << PIPE_A;
b445e3b0 1361
51cea1f4 1362 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1363 &valleyview_wm_info, latency_ns,
1364 &valleyview_cursor_wm_info, latency_ns,
1365 &planeb_wm, &cursorb_wm))
51cea1f4 1366 enabled |= 1 << PIPE_B;
b445e3b0 1367
b445e3b0
ED		 1368 if (single_plane_enabled(enabled) &&
1369 g4x_compute_srwm(dev, ffs(enabled) - 1,
1370 sr_latency_ns,
1371 &valleyview_wm_info,
1372 &valleyview_cursor_wm_info,
af6c4575
CW		 1373 &plane_sr, &ignore_cursor_sr) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 2*sr_latency_ns,
1376 &valleyview_wm_info,
1377 &valleyview_cursor_wm_info,
52bd02d8 1378 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1379 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1380 } else {
b445e3b0
ED		 1381 I915_WRITE(FW_BLC_SELF_VLV,
1382 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0
ED		 1385
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm, cursora_wm,
1388 planeb_wm, cursorb_wm,
1389 plane_sr, cursor_sr);
1390
1391 I915_WRITE(DSPFW1,
1392 (plane_sr << DSPFW_SR_SHIFT) |
1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1395 planea_wm);
1396 I915_WRITE(DSPFW2,
8c919b28 1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1398 (cursora_wm << DSPFW_CURSORA_SHIFT));
1399 I915_WRITE(DSPFW3,
8c919b28
CW		 1400 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1401 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1402}
1403
1fa61106 1404static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1405{
1406 static const int sr_latency_ns = 12000;
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1409 int plane_sr, cursor_sr;
1410 unsigned int enabled = 0;
1411
51cea1f4 1412 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1413 &g4x_wm_info, latency_ns,
1414 &g4x_cursor_wm_info, latency_ns,
1415 &planea_wm, &cursora_wm))
51cea1f4 1416 enabled |= 1 << PIPE_A;
b445e3b0 1417
51cea1f4 1418 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1419 &g4x_wm_info, latency_ns,
1420 &g4x_cursor_wm_info, latency_ns,
1421 &planeb_wm, &cursorb_wm))
51cea1f4 1422 enabled |= 1 << PIPE_B;
b445e3b0 1423
b445e3b0
ED		 1424 if (single_plane_enabled(enabled) &&
1425 g4x_compute_srwm(dev, ffs(enabled) - 1,
1426 sr_latency_ns,
1427 &g4x_wm_info,
1428 &g4x_cursor_wm_info,
52bd02d8 1429 &plane_sr, &cursor_sr)) {
b445e3b0 1430 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1431 } else {
b445e3b0
ED		 1432 I915_WRITE(FW_BLC_SELF,
1433 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1434 plane_sr = cursor_sr = 0;
1435 }
b445e3b0
ED		 1436
1437 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438 planea_wm, cursora_wm,
1439 planeb_wm, cursorb_wm,
1440 plane_sr, cursor_sr);
1441
1442 I915_WRITE(DSPFW1,
1443 (plane_sr << DSPFW_SR_SHIFT) |
1444 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1445 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1446 planea_wm);
1447 I915_WRITE(DSPFW2,
8c919b28 1448 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1449 (cursora_wm << DSPFW_CURSORA_SHIFT));
1450 /* HPLL off in SR has some issues on G4x... disable it */
1451 I915_WRITE(DSPFW3,
8c919b28 1452 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1453 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1454}
1455
1fa61106 1456static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1457{
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1459 struct drm_crtc *crtc;
1460 int srwm = 1;
1461 int cursor_sr = 16;
1462
1463 /* Calc sr entries for one plane configs */
1464 crtc = single_enabled_crtc(dev);
1465 if (crtc) {
1466 /* self-refresh has much higher latency */
1467 static const int sr_latency_ns = 12000;
1468 int clock = crtc->mode.clock;
1469 int htotal = crtc->mode.htotal;
1470 int hdisplay = crtc->mode.hdisplay;
1471 int pixel_size = crtc->fb->bits_per_pixel / 8;
1472 unsigned long line_time_us;
1473 int entries;
1474
1475 line_time_us = ((htotal * 1000) / clock);
1476
1477 /* Use ns/us then divide to preserve precision */
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479 pixel_size * hdisplay;
1480 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481 srwm = I965_FIFO_SIZE - entries;
1482 if (srwm < 0)
1483 srwm = 1;
1484 srwm &= 0x1ff;
1485 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1486 entries, srwm);
1487
1488 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1489 pixel_size * 64;
1490 entries = DIV_ROUND_UP(entries,
1491 i965_cursor_wm_info.cacheline_size);
1492 cursor_sr = i965_cursor_wm_info.fifo_size -
1493 (entries + i965_cursor_wm_info.guard_size);
1494
1495 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496 cursor_sr = i965_cursor_wm_info.max_wm;
1497
1498 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499 "cursor %d\n", srwm, cursor_sr);
1500
1501 if (IS_CRESTLINE(dev))
1502 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1503 } else {
1504 /* Turn off self refresh if both pipes are enabled */
1505 if (IS_CRESTLINE(dev))
1506 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1507 & ~FW_BLC_SELF_EN);
1508 }
1509
1510 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1511 srwm);
1512
1513 /* 965 has limitations... */
1514 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1515 (8 << 16) | (8 << 8) | (8 << 0));
1516 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1517 /* update cursor SR watermark */
1518 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1519}
1520
1fa61106 1521static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1522{
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 const struct intel_watermark_params *wm_info;
1525 uint32_t fwater_lo;
1526 uint32_t fwater_hi;
1527 int cwm, srwm = 1;
1528 int fifo_size;
1529 int planea_wm, planeb_wm;
1530 struct drm_crtc *crtc, *enabled = NULL;
1531
1532 if (IS_I945GM(dev))
1533 wm_info = &i945_wm_info;
1534 else if (!IS_GEN2(dev))
1535 wm_info = &i915_wm_info;
1536 else
1537 wm_info = &i855_wm_info;
1538
1539 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1541 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1542 int cpp = crtc->fb->bits_per_pixel / 8;
1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
b445e3b0 1546 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
b445e3b0
ED		 1548 latency_ns);
1549 enabled = crtc;
1550 } else
1551 planea_wm = fifo_size - wm_info->guard_size;
1552
1553 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1555 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1556 int cpp = crtc->fb->bits_per_pixel / 8;
1557 if (IS_GEN2(dev))
1558 cpp = 4;
1559
b445e3b0 1560 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1561 wm_info, fifo_size, cpp,
b445e3b0
ED		 1562 latency_ns);
1563 if (enabled == NULL)
1564 enabled = crtc;
1565 else
1566 enabled = NULL;
1567 } else
1568 planeb_wm = fifo_size - wm_info->guard_size;
1569
1570 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1571
1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
1578 if (IS_I945G(dev) || IS_I945GM(dev))
1579 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1580 else if (IS_I915GM(dev))
1581 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1582
1583 /* Calc sr entries for one plane configs */
1584 if (HAS_FW_BLC(dev) && enabled) {
1585 /* self-refresh has much higher latency */
1586 static const int sr_latency_ns = 6000;
1587 int clock = enabled->mode.clock;
1588 int htotal = enabled->mode.htotal;
1589 int hdisplay = enabled->mode.hdisplay;
1590 int pixel_size = enabled->fb->bits_per_pixel / 8;
1591 unsigned long line_time_us;
1592 int entries;
1593
1594 line_time_us = (htotal * 1000) / clock;
1595
1596 /* Use ns/us then divide to preserve precision */
1597 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598 pixel_size * hdisplay;
1599 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601 srwm = wm_info->fifo_size - entries;
1602 if (srwm < 0)
1603 srwm = 1;
1604
1605 if (IS_I945G(dev) || IS_I945GM(dev))
1606 I915_WRITE(FW_BLC_SELF,
1607 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608 else if (IS_I915GM(dev))
1609 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1610 }
1611
1612 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613 planea_wm, planeb_wm, cwm, srwm);
1614
1615 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616 fwater_hi = (cwm & 0x1f);
1617
1618 /* Set request length to 8 cachelines per fetch */
1619 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620 fwater_hi = fwater_hi | (1 << 8);
1621
1622 I915_WRITE(FW_BLC, fwater_lo);
1623 I915_WRITE(FW_BLC2, fwater_hi);
1624
1625 if (HAS_FW_BLC(dev)) {
1626 if (enabled) {
1627 if (IS_I945G(dev) || IS_I945GM(dev))
1628 I915_WRITE(FW_BLC_SELF,
1629 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1630 else if (IS_I915GM(dev))
1631 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1632 DRM_DEBUG_KMS("memory self refresh enabled\n");
1633 } else
1634 DRM_DEBUG_KMS("memory self refresh disabled\n");
1635 }
1636}
1637
1fa61106 1638static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1639{
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 struct drm_crtc *crtc;
1642 uint32_t fwater_lo;
1643 int planea_wm;
1644
1645 crtc = single_enabled_crtc(dev);
1646 if (crtc == NULL)
1647 return;
1648
1649 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1650 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1651 4, latency_ns);
b445e3b0
ED		 1652 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1653 fwater_lo |= (3<<8) | planea_wm;
1654
1655 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1656
1657 I915_WRITE(FW_BLC, fwater_lo);
1658}
1659
1660#define ILK_LP0_PLANE_LATENCY 700
1661#define ILK_LP0_CURSOR_LATENCY 1300
1662
1663/*
1664 * Check the wm result.
1665 *
1666 * If any calculated watermark values is larger than the maximum value that
1667 * can be programmed into the associated watermark register, that watermark
1668 * must be disabled.
1669 */
1670static bool ironlake_check_srwm(struct drm_device *dev, int level,
1671 int fbc_wm, int display_wm, int cursor_wm,
1672 const struct intel_watermark_params *display,
1673 const struct intel_watermark_params *cursor)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1679
1680 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1681 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682 fbc_wm, SNB_FBC_MAX_SRWM, level);
1683
1684 /* fbc has it's own way to disable FBC WM */
1685 I915_WRITE(DISP_ARB_CTL,
1686 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1687 return false;
615aaa5f
VS		 1688 } else if (INTEL_INFO(dev)->gen >= 6) {
1689 /* enable FBC WM (except on ILK, where it must remain off) */
1690 I915_WRITE(DISP_ARB_CTL,
1691 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1692 }
1693
1694 if (display_wm > display->max_wm) {
1695 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1697 return false;
1698 }
1699
1700 if (cursor_wm > cursor->max_wm) {
1701 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1703 return false;
1704 }
1705
1706 if (!(fbc_wm || display_wm || cursor_wm)) {
1707 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1708 return false;
1709 }
1710
1711 return true;
1712}
1713
1714/*
1715 * Compute watermark values of WM[1-3],
1716 */
1717static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1718 int latency_ns,
1719 const struct intel_watermark_params *display,
1720 const struct intel_watermark_params *cursor,
1721 int *fbc_wm, int *display_wm, int *cursor_wm)
1722{
1723 struct drm_crtc *crtc;
1724 unsigned long line_time_us;
1725 int hdisplay, htotal, pixel_size, clock;
1726 int line_count, line_size;
1727 int small, large;
1728 int entries;
1729
1730 if (!latency_ns) {
1731 *fbc_wm = *display_wm = *cursor_wm = 0;
1732 return false;
1733 }
1734
1735 crtc = intel_get_crtc_for_plane(dev, plane);
1736 hdisplay = crtc->mode.hdisplay;
1737 htotal = crtc->mode.htotal;
1738 clock = crtc->mode.clock;
1739 pixel_size = crtc->fb->bits_per_pixel / 8;
1740
1741 line_time_us = (htotal * 1000) / clock;
1742 line_count = (latency_ns / line_time_us + 1000) / 1000;
1743 line_size = hdisplay * pixel_size;
1744
1745 /* Use the minimum of the small and large buffer method for primary */
1746 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1747 large = line_count * line_size;
1748
1749 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1750 *display_wm = entries + display->guard_size;
1751
1752 /*
1753 * Spec says:
1754 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1755 */
1756 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1757
1758 /* calculate the self-refresh watermark for display cursor */
1759 entries = line_count * pixel_size * 64;
1760 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1761 *cursor_wm = entries + cursor->guard_size;
1762
1763 return ironlake_check_srwm(dev, level,
1764 *fbc_wm, *display_wm, *cursor_wm,
1765 display, cursor);
1766}
1767
1fa61106 1768static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1769{
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 int fbc_wm, plane_wm, cursor_wm;
1772 unsigned int enabled;
1773
1774 enabled = 0;
51cea1f4 1775 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1776 &ironlake_display_wm_info,
1777 ILK_LP0_PLANE_LATENCY,
1778 &ironlake_cursor_wm_info,
1779 ILK_LP0_CURSOR_LATENCY,
1780 &plane_wm, &cursor_wm)) {
1781 I915_WRITE(WM0_PIPEA_ILK,
1782 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1783 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784 " plane %d, " "cursor: %d\n",
1785 plane_wm, cursor_wm);
51cea1f4 1786 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1787 }
1788
51cea1f4 1789 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1790 &ironlake_display_wm_info,
1791 ILK_LP0_PLANE_LATENCY,
1792 &ironlake_cursor_wm_info,
1793 ILK_LP0_CURSOR_LATENCY,
1794 &plane_wm, &cursor_wm)) {
1795 I915_WRITE(WM0_PIPEB_ILK,
1796 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1797 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798 " plane %d, cursor: %d\n",
1799 plane_wm, cursor_wm);
51cea1f4 1800 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1801 }
1802
1803 /*
1804 * Calculate and update the self-refresh watermark only when one
1805 * display plane is used.
1806 */
1807 I915_WRITE(WM3_LP_ILK, 0);
1808 I915_WRITE(WM2_LP_ILK, 0);
1809 I915_WRITE(WM1_LP_ILK, 0);
1810
1811 if (!single_plane_enabled(enabled))
1812 return;
1813 enabled = ffs(enabled) - 1;
1814
1815 /* WM1 */
1816 if (!ironlake_compute_srwm(dev, 1, enabled,
1817 ILK_READ_WM1_LATENCY() * 500,
1818 &ironlake_display_srwm_info,
1819 &ironlake_cursor_srwm_info,
1820 &fbc_wm, &plane_wm, &cursor_wm))
1821 return;
1822
1823 I915_WRITE(WM1_LP_ILK,
1824 WM1_LP_SR_EN |
1825 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1826 (fbc_wm << WM1_LP_FBC_SHIFT) |
1827 (plane_wm << WM1_LP_SR_SHIFT) |
1828 cursor_wm);
1829
1830 /* WM2 */
1831 if (!ironlake_compute_srwm(dev, 2, enabled,
1832 ILK_READ_WM2_LATENCY() * 500,
1833 &ironlake_display_srwm_info,
1834 &ironlake_cursor_srwm_info,
1835 &fbc_wm, &plane_wm, &cursor_wm))
1836 return;
1837
1838 I915_WRITE(WM2_LP_ILK,
1839 WM2_LP_EN |
1840 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1841 (fbc_wm << WM1_LP_FBC_SHIFT) |
1842 (plane_wm << WM1_LP_SR_SHIFT) |
1843 cursor_wm);
1844
1845 /*
1846 * WM3 is unsupported on ILK, probably because we don't have latency
1847 * data for that power state
1848 */
1849}
1850
1fa61106 1851static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1852{
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1855 u32 val;
1856 int fbc_wm, plane_wm, cursor_wm;
1857 unsigned int enabled;
1858
1859 enabled = 0;
51cea1f4 1860 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1861 &sandybridge_display_wm_info, latency,
1862 &sandybridge_cursor_wm_info, latency,
1863 &plane_wm, &cursor_wm)) {
1864 val = I915_READ(WM0_PIPEA_ILK);
1865 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1866 I915_WRITE(WM0_PIPEA_ILK, val |
1867 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1868 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869 " plane %d, " "cursor: %d\n",
1870 plane_wm, cursor_wm);
51cea1f4 1871 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1872 }
1873
51cea1f4 1874 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1875 &sandybridge_display_wm_info, latency,
1876 &sandybridge_cursor_wm_info, latency,
1877 &plane_wm, &cursor_wm)) {
1878 val = I915_READ(WM0_PIPEB_ILK);
1879 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1880 I915_WRITE(WM0_PIPEB_ILK, val |
1881 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1882 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883 " plane %d, cursor: %d\n",
1884 plane_wm, cursor_wm);
51cea1f4 1885 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1886 }
1887
c43d0188
CW		 1888 /*
1889 * Calculate and update the self-refresh watermark only when one
1890 * display plane is used.
1891 *
1892 * SNB support 3 levels of watermark.
1893 *
1894 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895 * and disabled in the descending order
1896 *
1897 */
1898 I915_WRITE(WM3_LP_ILK, 0);
1899 I915_WRITE(WM2_LP_ILK, 0);
1900 I915_WRITE(WM1_LP_ILK, 0);
1901
1902 if (!single_plane_enabled(enabled) ||
1903 dev_priv->sprite_scaling_enabled)
1904 return;
1905 enabled = ffs(enabled) - 1;
1906
1907 /* WM1 */
1908 if (!ironlake_compute_srwm(dev, 1, enabled,
1909 SNB_READ_WM1_LATENCY() * 500,
1910 &sandybridge_display_srwm_info,
1911 &sandybridge_cursor_srwm_info,
1912 &fbc_wm, &plane_wm, &cursor_wm))
1913 return;
1914
1915 I915_WRITE(WM1_LP_ILK,
1916 WM1_LP_SR_EN |
1917 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918 (fbc_wm << WM1_LP_FBC_SHIFT) |
1919 (plane_wm << WM1_LP_SR_SHIFT) |
1920 cursor_wm);
1921
1922 /* WM2 */
1923 if (!ironlake_compute_srwm(dev, 2, enabled,
1924 SNB_READ_WM2_LATENCY() * 500,
1925 &sandybridge_display_srwm_info,
1926 &sandybridge_cursor_srwm_info,
1927 &fbc_wm, &plane_wm, &cursor_wm))
1928 return;
1929
1930 I915_WRITE(WM2_LP_ILK,
1931 WM2_LP_EN |
1932 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1933 (fbc_wm << WM1_LP_FBC_SHIFT) |
1934 (plane_wm << WM1_LP_SR_SHIFT) |
1935 cursor_wm);
1936
1937 /* WM3 */
1938 if (!ironlake_compute_srwm(dev, 3, enabled,
1939 SNB_READ_WM3_LATENCY() * 500,
1940 &sandybridge_display_srwm_info,
1941 &sandybridge_cursor_srwm_info,
1942 &fbc_wm, &plane_wm, &cursor_wm))
1943 return;
1944
1945 I915_WRITE(WM3_LP_ILK,
1946 WM3_LP_EN |
1947 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1948 (fbc_wm << WM1_LP_FBC_SHIFT) |
1949 (plane_wm << WM1_LP_SR_SHIFT) |
1950 cursor_wm);
1951}
1952
1953static void ivybridge_update_wm(struct drm_device *dev)
1954{
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1957 u32 val;
1958 int fbc_wm, plane_wm, cursor_wm;
1959 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1960 unsigned int enabled;
1961
1962 enabled = 0;
51cea1f4 1963 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1964 &sandybridge_display_wm_info, latency,
1965 &sandybridge_cursor_wm_info, latency,
1966 &plane_wm, &cursor_wm)) {
1967 val = I915_READ(WM0_PIPEA_ILK);
1968 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969 I915_WRITE(WM0_PIPEA_ILK, val |
1970 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972 " plane %d, " "cursor: %d\n",
1973 plane_wm, cursor_wm);
51cea1f4 1974 enabled |= 1 << PIPE_A;
c43d0188
CW		 1975 }
1976
51cea1f4 1977 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1978 &sandybridge_display_wm_info, latency,
1979 &sandybridge_cursor_wm_info, latency,
1980 &plane_wm, &cursor_wm)) {
1981 val = I915_READ(WM0_PIPEB_ILK);
1982 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1983 I915_WRITE(WM0_PIPEB_ILK, val |
1984 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1985 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986 " plane %d, cursor: %d\n",
1987 plane_wm, cursor_wm);
51cea1f4 1988 enabled |= 1 << PIPE_B;
c43d0188
CW		 1989 }
1990
51cea1f4 1991 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 1992 &sandybridge_display_wm_info, latency,
1993 &sandybridge_cursor_wm_info, latency,
1994 &plane_wm, &cursor_wm)) {
1995 val = I915_READ(WM0_PIPEC_IVB);
1996 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1997 I915_WRITE(WM0_PIPEC_IVB, val |
1998 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1999 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000 " plane %d, cursor: %d\n",
2001 plane_wm, cursor_wm);
51cea1f4 2002 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2003 }
2004
2005 /*
2006 * Calculate and update the self-refresh watermark only when one
2007 * display plane is used.
2008 *
2009 * SNB support 3 levels of watermark.
2010 *
2011 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012 * and disabled in the descending order
2013 *
2014 */
2015 I915_WRITE(WM3_LP_ILK, 0);
2016 I915_WRITE(WM2_LP_ILK, 0);
2017 I915_WRITE(WM1_LP_ILK, 0);
2018
2019 if (!single_plane_enabled(enabled) ||
2020 dev_priv->sprite_scaling_enabled)
2021 return;
2022 enabled = ffs(enabled) - 1;
2023
2024 /* WM1 */
2025 if (!ironlake_compute_srwm(dev, 1, enabled,
2026 SNB_READ_WM1_LATENCY() * 500,
2027 &sandybridge_display_srwm_info,
2028 &sandybridge_cursor_srwm_info,
2029 &fbc_wm, &plane_wm, &cursor_wm))
2030 return;
2031
2032 I915_WRITE(WM1_LP_ILK,
2033 WM1_LP_SR_EN |
2034 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2035 (fbc_wm << WM1_LP_FBC_SHIFT) |
2036 (plane_wm << WM1_LP_SR_SHIFT) |
2037 cursor_wm);
2038
2039 /* WM2 */
2040 if (!ironlake_compute_srwm(dev, 2, enabled,
2041 SNB_READ_WM2_LATENCY() * 500,
2042 &sandybridge_display_srwm_info,
2043 &sandybridge_cursor_srwm_info,
2044 &fbc_wm, &plane_wm, &cursor_wm))
2045 return;
2046
2047 I915_WRITE(WM2_LP_ILK,
2048 WM2_LP_EN |
2049 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2050 (fbc_wm << WM1_LP_FBC_SHIFT) |
2051 (plane_wm << WM1_LP_SR_SHIFT) |
2052 cursor_wm);
2053
c43d0188 2054 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2055 if (!ironlake_compute_srwm(dev, 3, enabled,
2056 SNB_READ_WM3_LATENCY() * 500,
2057 &sandybridge_display_srwm_info,
2058 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2059 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2060 !ironlake_compute_srwm(dev, 3, enabled,
2061 2 * SNB_READ_WM3_LATENCY() * 500,
2062 &sandybridge_display_srwm_info,
2063 &sandybridge_cursor_srwm_info,
2064 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2065 return;
2066
2067 I915_WRITE(WM3_LP_ILK,
2068 WM3_LP_EN |
2069 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2070 (fbc_wm << WM1_LP_FBC_SHIFT) |
2071 (plane_wm << WM1_LP_SR_SHIFT) |
2072 cursor_wm);
2073}
2074
801bcfff
PZ		 2075static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2076 struct drm_crtc *crtc)
2077{
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 uint32_t pixel_rate, pfit_size;
2080
ff9a6750 2081 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2082
2083 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2084 * adjust the pixel_rate here. */
2085
2086 pfit_size = intel_crtc->config.pch_pfit.size;
2087 if (pfit_size) {
2088 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2089
2090 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2091 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2092 pfit_w = (pfit_size >> 16) & 0xFFFF;
2093 pfit_h = pfit_size & 0xFFFF;
2094 if (pipe_w < pfit_w)
2095 pipe_w = pfit_w;
2096 if (pipe_h < pfit_h)
2097 pipe_h = pfit_h;
2098
2099 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2100 pfit_w * pfit_h);
2101 }
2102
2103 return pixel_rate;
2104}
2105
2106static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2107 uint32_t latency)
2108{
2109 uint64_t ret;
2110
2111 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2112 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2113
2114 return ret;
2115}
2116
2117static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2118 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2119 uint32_t latency)
2120{
2121 uint32_t ret;
2122
2123 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2124 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2125 ret = DIV_ROUND_UP(ret, 64) + 2;
2126 return ret;
2127}
2128
cca32e9a
PZ		 2129static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2130 uint8_t bytes_per_pixel)
2131{
2132 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2133}
2134
801bcfff
PZ		 2135struct hsw_pipe_wm_parameters {
2136 bool active;
2137 bool sprite_enabled;
2138 uint8_t pri_bytes_per_pixel;
2139 uint8_t spr_bytes_per_pixel;
2140 uint8_t cur_bytes_per_pixel;
2141 uint32_t pri_horiz_pixels;
2142 uint32_t spr_horiz_pixels;
2143 uint32_t cur_horiz_pixels;
2144 uint32_t pipe_htotal;
2145 uint32_t pixel_rate;
2146};
2147
cca32e9a
PZ		 2148struct hsw_wm_maximums {
2149 uint16_t pri;
2150 uint16_t spr;
2151 uint16_t cur;
2152 uint16_t fbc;
2153};
2154
2155struct hsw_lp_wm_result {
2156 bool enable;
2157 bool fbc_enable;
2158 uint32_t pri_val;
2159 uint32_t spr_val;
2160 uint32_t cur_val;
2161 uint32_t fbc_val;
2162};
2163
801bcfff
PZ		 2164struct hsw_wm_values {
2165 uint32_t wm_pipe[3];
2166 uint32_t wm_lp[3];
2167 uint32_t wm_lp_spr[3];
2168 uint32_t wm_linetime[3];
cca32e9a 2169 bool enable_fbc_wm;
801bcfff
PZ		 2170};
2171
2172enum hsw_data_buf_partitioning {
2173 HSW_DATA_BUF_PART_1_2,
2174 HSW_DATA_BUF_PART_5_6,
2175};
2176
cca32e9a
PZ		 2177/* For both WM_PIPE and WM_LP. */
2178static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2179 uint32_t mem_value,
2180 bool is_lp)
801bcfff 2181{
cca32e9a
PZ		 2182 uint32_t method1, method2;
2183
801bcfff
PZ		 2184 /* TODO: for now, assume the primary plane is always enabled. */
2185 if (!params->active)
2186 return 0;
2187
cca32e9a
PZ		 2188 method1 = hsw_wm_method1(params->pixel_rate,
2189 params->pri_bytes_per_pixel,
2190 mem_value);
2191
2192 if (!is_lp)
2193 return method1;
2194
2195 method2 = hsw_wm_method2(params->pixel_rate,
2196 params->pipe_htotal,
2197 params->pri_horiz_pixels,
2198 params->pri_bytes_per_pixel,
2199 mem_value);
2200
2201 return min(method1, method2);
801bcfff
PZ		 2202}
2203
2204/* For both WM_PIPE and WM_LP. */
2205static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2206 uint32_t mem_value)
2207{
2208 uint32_t method1, method2;
2209
2210 if (!params->active || !params->sprite_enabled)
2211 return 0;
2212
2213 method1 = hsw_wm_method1(params->pixel_rate,
2214 params->spr_bytes_per_pixel,
2215 mem_value);
2216 method2 = hsw_wm_method2(params->pixel_rate,
2217 params->pipe_htotal,
2218 params->spr_horiz_pixels,
2219 params->spr_bytes_per_pixel,
2220 mem_value);
2221 return min(method1, method2);
2222}
2223
2224/* For both WM_PIPE and WM_LP. */
2225static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2226 uint32_t mem_value)
2227{
2228 if (!params->active)
2229 return 0;
2230
2231 return hsw_wm_method2(params->pixel_rate,
2232 params->pipe_htotal,
2233 params->cur_horiz_pixels,
2234 params->cur_bytes_per_pixel,
2235 mem_value);
2236}
2237
cca32e9a
PZ		 2238/* Only for WM_LP. */
2239static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2240 uint32_t pri_val,
2241 uint32_t mem_value)
2242{
2243 if (!params->active)
2244 return 0;
2245
2246 return hsw_wm_fbc(pri_val,
2247 params->pri_horiz_pixels,
2248 params->pri_bytes_per_pixel);
2249}
2250
2251static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2252 struct hsw_pipe_wm_parameters *params,
2253 struct hsw_lp_wm_result *result)
2254{
2255 enum pipe pipe;
2256 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2257
2258 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2259 struct hsw_pipe_wm_parameters *p = &params[pipe];
2260
2261 pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2262 spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2263 cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2264 fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2265 }
2266
2267 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2268 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2269 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2270 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2271
2272 if (result->fbc_val > max->fbc) {
2273 result->fbc_enable = false;
2274 result->fbc_val = 0;
2275 } else {
2276 result->fbc_enable = true;
2277 }
2278
2279 result->enable = result->pri_val <= max->pri &&
2280 result->spr_val <= max->spr &&
2281 result->cur_val <= max->cur;
2282 return result->enable;
2283}
2284
801bcfff
PZ		 2285static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2286 uint32_t mem_value, enum pipe pipe,
2287 struct hsw_pipe_wm_parameters *params)
2288{
2289 uint32_t pri_val, cur_val, spr_val;
2290
cca32e9a 2291 pri_val = hsw_compute_pri_wm(params, mem_value, false);
801bcfff
PZ		 2292 spr_val = hsw_compute_spr_wm(params, mem_value);
2293 cur_val = hsw_compute_cur_wm(params, mem_value);
2294
2295 WARN(pri_val > 127,
2296 "Primary WM error, mode not supported for pipe %c\n",
2297 pipe_name(pipe));
2298 WARN(spr_val > 127,
2299 "Sprite WM error, mode not supported for pipe %c\n",
2300 pipe_name(pipe));
2301 WARN(cur_val > 63,
2302 "Cursor WM error, mode not supported for pipe %c\n",
2303 pipe_name(pipe));
2304
2305 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2306 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2307 cur_val;
2308}
2309
2310static uint32_t
2311hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2312{
2313 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2315 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2316 u32 linetime, ips_linetime;
1f8eeabf 2317
801bcfff
PZ		 2318 if (!intel_crtc_active(crtc))
2319 return 0;
1011d8c4 2320
1f8eeabf
ED		 2321 /* The WM are computed with base on how long it takes to fill a single
2322 * row at the given clock rate, multiplied by 8.
2323 * */
85a02deb
PZ		 2324 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2325 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2326 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2327
801bcfff
PZ		 2328 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2329 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2330}
2331
801bcfff
PZ		 2332static void hsw_compute_wm_parameters(struct drm_device *dev,
2333 struct hsw_pipe_wm_parameters *params,
cca32e9a 2334 uint32_t *wm,
861f3389
PZ		 2335 struct hsw_wm_maximums *lp_max_1_2,
2336 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4
PZ		 2337{
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_crtc *crtc;
801bcfff
PZ		 2340 struct drm_plane *plane;
2341 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1011d8c4 2342 enum pipe pipe;
cca32e9a 2343 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2344
801bcfff
PZ		 2345 if ((sskpd >> 56) & 0xFF)
2346 wm[0] = (sskpd >> 56) & 0xFF;
2347 else
2348 wm[0] = sskpd & 0xF;
2349 wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2350 wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2351 wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2352 wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2353
2354 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2356 struct hsw_pipe_wm_parameters *p;
2357
2358 pipe = intel_crtc->pipe;
2359 p = &params[pipe];
2360
2361 p->active = intel_crtc_active(crtc);
2362 if (!p->active)
2363 continue;
2364
cca32e9a
PZ		 2365 pipes_active++;
2366
801bcfff
PZ		 2367 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2368 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2369 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2370 p->cur_bytes_per_pixel = 4;
2371 p->pri_horiz_pixels =
2372 intel_crtc->config.requested_mode.hdisplay;
2373 p->cur_horiz_pixels = 64;
2374 }
2375
2376 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2377 struct intel_plane *intel_plane = to_intel_plane(plane);
2378 struct hsw_pipe_wm_parameters *p;
2379
2380 pipe = intel_plane->pipe;
2381 p = &params[pipe];
2382
2383 p->sprite_enabled = intel_plane->wm.enable;
2384 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2385 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2386
2387 if (p->sprite_enabled)
2388 sprites_enabled++;
2389 }
2390
2391 if (pipes_active > 1) {
861f3389
PZ		 2392 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2393 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2394 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2395 } else {
2396 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2397 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2398 lp_max_1_2->spr = 384;
861f3389
PZ		 2399 lp_max_5_6->spr = 640;
2400 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2401 }
861f3389 2402 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2403}
2404
2405static void hsw_compute_wm_results(struct drm_device *dev,
2406 struct hsw_pipe_wm_parameters *params,
2407 uint32_t *wm,
cca32e9a 2408 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2409 struct hsw_wm_values *results)
2410{
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 struct drm_crtc *crtc;
cca32e9a 2413 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2414 enum pipe pipe;
cca32e9a
PZ		 2415 int level, max_level, wm_lp;
2416
2417 for (level = 1; level <= 4; level++)
2418 if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
2419 &lp_results[level - 1]))
2420 break;
2421 max_level = level - 1;
2422
2423 /* The spec says it is preferred to disable FBC WMs instead of disabling
2424 * a WM level. */
2425 results->enable_fbc_wm = true;
2426 for (level = 1; level <= max_level; level++) {
2427 if (!lp_results[level - 1].fbc_enable) {
2428 results->enable_fbc_wm = false;
2429 break;
2430 }
2431 }
2432
2433 memset(results, 0, sizeof(*results));
2434 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2435 const struct hsw_lp_wm_result *r;
801bcfff 2436
cca32e9a
PZ		 2437 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2438 if (level > max_level)
2439 break;
2440
2441 r = &lp_results[level - 1];
2442 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2443 r->fbc_val,
2444 r->pri_val,
2445 r->cur_val);
2446 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2447 }
801bcfff
PZ		 2448
2449 for_each_pipe(pipe)
2450 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2451 pipe,
2452 &params[pipe]);
1011d8c4
PZ		 2453
2454 for_each_pipe(pipe) {
2455 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2456 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2457 }
2458}
2459
861f3389
PZ		 2460/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2461 * case both are at the same level. Prefer r1 in case they're the same. */
2462struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2463 struct hsw_wm_values *r2)
2464{
2465 int i, val_r1 = 0, val_r2 = 0;
2466
2467 for (i = 0; i < 3; i++) {
2468 if (r1->wm_lp[i] & WM3_LP_EN)
2469 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2470 if (r2->wm_lp[i] & WM3_LP_EN)
2471 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2472 }
2473
2474 if (val_r1 == val_r2) {
2475 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2476 return r2;
2477 else
2478 return r1;
2479 } else if (val_r1 > val_r2) {
2480 return r1;
2481 } else {
2482 return r2;
2483 }
2484}
2485
801bcfff
PZ		 2486/*
2487 * The spec says we shouldn't write when we don't need, because every write
2488 * causes WMs to be re-evaluated, expending some power.
2489 */
2490static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2491 struct hsw_wm_values *results,
2492 enum hsw_data_buf_partitioning partitioning)
2493{
2494 struct hsw_wm_values previous;
2495 uint32_t val;
2496 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2497 bool prev_enable_fbc_wm;
801bcfff
PZ		 2498
2499 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2500 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2501 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2502 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2503 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2504 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2505 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2506 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2507 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2508 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2509 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2510 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2511
2512 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2513 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2514
cca32e9a
PZ		 2515 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2516
801bcfff
PZ		 2517 if (memcmp(results->wm_pipe, previous.wm_pipe,
2518 sizeof(results->wm_pipe)) == 0 &&
2519 memcmp(results->wm_lp, previous.wm_lp,
2520 sizeof(results->wm_lp)) == 0 &&
2521 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2522 sizeof(results->wm_lp_spr)) == 0 &&
2523 memcmp(results->wm_linetime, previous.wm_linetime,
2524 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2525 partitioning == prev_partitioning &&
2526 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2527 return;
2528
2529 if (previous.wm_lp[2] != 0)
2530 I915_WRITE(WM3_LP_ILK, 0);
2531 if (previous.wm_lp[1] != 0)
2532 I915_WRITE(WM2_LP_ILK, 0);
2533 if (previous.wm_lp[0] != 0)
2534 I915_WRITE(WM1_LP_ILK, 0);
2535
2536 if (previous.wm_pipe[0] != results->wm_pipe[0])
2537 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2538 if (previous.wm_pipe[1] != results->wm_pipe[1])
2539 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2540 if (previous.wm_pipe[2] != results->wm_pipe[2])
2541 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2542
2543 if (previous.wm_linetime[0] != results->wm_linetime[0])
2544 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2545 if (previous.wm_linetime[1] != results->wm_linetime[1])
2546 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2547 if (previous.wm_linetime[2] != results->wm_linetime[2])
2548 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2549
2550 if (prev_partitioning != partitioning) {
2551 val = I915_READ(WM_MISC);
2552 if (partitioning == HSW_DATA_BUF_PART_1_2)
2553 val &= ~WM_MISC_DATA_PARTITION_5_6;
2554 else
2555 val |= WM_MISC_DATA_PARTITION_5_6;
2556 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2557 }
2558
cca32e9a
PZ		 2559 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2560 val = I915_READ(DISP_ARB_CTL);
2561 if (results->enable_fbc_wm)
2562 val &= ~DISP_FBC_WM_DIS;
2563 else
2564 val |= DISP_FBC_WM_DIS;
2565 I915_WRITE(DISP_ARB_CTL, val);
2566 }
2567
801bcfff
PZ		 2568 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2569 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2570 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2571 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2572 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2573 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2574
2575 if (results->wm_lp[0] != 0)
2576 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2577 if (results->wm_lp[1] != 0)
2578 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2579 if (results->wm_lp[2] != 0)
2580 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2581}
2582
2583static void haswell_update_wm(struct drm_device *dev)
2584{
2585 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2586 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2587 struct hsw_pipe_wm_parameters params[3];
861f3389 2588 struct hsw_wm_values results_1_2, results_5_6, *best_results;
801bcfff 2589 uint32_t wm[5];
861f3389
PZ		 2590 enum hsw_data_buf_partitioning partitioning;
2591
2592 hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
2593
2594 hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
2595 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2596 hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
2597 &results_5_6);
2598 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2599 } else {
2600 best_results = &results_1_2;
2601 }
2602
2603 partitioning = (best_results == &results_1_2) ?
2604 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2605
861f3389 2606 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2607}
2608
526682e9
PZ		 2609static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2610 uint32_t sprite_width, int pixel_size,
2611 bool enable)
2612{
2613 struct drm_plane *plane;
2614
2615 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2616 struct intel_plane *intel_plane = to_intel_plane(plane);
2617
2618 if (intel_plane->pipe == pipe) {
2619 intel_plane->wm.enable = enable;
2620 intel_plane->wm.horiz_pixels = sprite_width + 1;
2621 intel_plane->wm.bytes_per_pixel = pixel_size;
2622 break;
2623 }
2624 }
2625
2626 haswell_update_wm(dev);
2627}
2628
b445e3b0
ED		 2629static bool
2630sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2631 uint32_t sprite_width, int pixel_size,
2632 const struct intel_watermark_params *display,
2633 int display_latency_ns, int *sprite_wm)
2634{
2635 struct drm_crtc *crtc;
2636 int clock;
2637 int entries, tlb_miss;
2638
2639 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2640 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2641 *sprite_wm = display->guard_size;
2642 return false;
2643 }
2644
2645 clock = crtc->mode.clock;
2646
2647 /* Use the small buffer method to calculate the sprite watermark */
2648 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2649 tlb_miss = display->fifo_size*display->cacheline_size -
2650 sprite_width * 8;
2651 if (tlb_miss > 0)
2652 entries += tlb_miss;
2653 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2654 *sprite_wm = entries + display->guard_size;
2655 if (*sprite_wm > (int)display->max_wm)
2656 *sprite_wm = display->max_wm;
2657
2658 return true;
2659}
2660
2661static bool
2662sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2663 uint32_t sprite_width, int pixel_size,
2664 const struct intel_watermark_params *display,
2665 int latency_ns, int *sprite_wm)
2666{
2667 struct drm_crtc *crtc;
2668 unsigned long line_time_us;
2669 int clock;
2670 int line_count, line_size;
2671 int small, large;
2672 int entries;
2673
2674 if (!latency_ns) {
2675 *sprite_wm = 0;
2676 return false;
2677 }
2678
2679 crtc = intel_get_crtc_for_plane(dev, plane);
2680 clock = crtc->mode.clock;
2681 if (!clock) {
2682 *sprite_wm = 0;
2683 return false;
2684 }
2685
2686 line_time_us = (sprite_width * 1000) / clock;
2687 if (!line_time_us) {
2688 *sprite_wm = 0;
2689 return false;
2690 }
2691
2692 line_count = (latency_ns / line_time_us + 1000) / 1000;
2693 line_size = sprite_width * pixel_size;
2694
2695 /* Use the minimum of the small and large buffer method for primary */
2696 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2697 large = line_count * line_size;
2698
2699 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2700 *sprite_wm = entries + display->guard_size;
2701
2702 return *sprite_wm > 0x3ff ? false : true;
2703}
2704
1fa61106 2705static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2706 uint32_t sprite_width, int pixel_size,
2707 bool enable)
b445e3b0
ED		 2708{
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2711 u32 val;
2712 int sprite_wm, reg;
2713 int ret;
2714
4c4ff43a
PZ		 2715 if (!enable)
2716 return;
2717
b445e3b0
ED		 2718 switch (pipe) {
2719 case 0:
2720 reg = WM0_PIPEA_ILK;
2721 break;
2722 case 1:
2723 reg = WM0_PIPEB_ILK;
2724 break;
2725 case 2:
2726 reg = WM0_PIPEC_IVB;
2727 break;
2728 default:
2729 return; /* bad pipe */
2730 }
2731
2732 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2733 &sandybridge_display_wm_info,
2734 latency, &sprite_wm);
2735 if (!ret) {
84f44ce7
VS		 2736 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2737 pipe_name(pipe));
b445e3b0
ED		 2738 return;
2739 }
2740
2741 val = I915_READ(reg);
2742 val &= ~WM0_PIPE_SPRITE_MASK;
2743 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2744 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2745
2746
2747 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2748 pixel_size,
2749 &sandybridge_display_srwm_info,
2750 SNB_READ_WM1_LATENCY() * 500,
2751 &sprite_wm);
2752 if (!ret) {
84f44ce7
VS		 2753 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2754 pipe_name(pipe));
b445e3b0
ED		 2755 return;
2756 }
2757 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2758
2759 /* Only IVB has two more LP watermarks for sprite */
2760 if (!IS_IVYBRIDGE(dev))
2761 return;
2762
2763 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2764 pixel_size,
2765 &sandybridge_display_srwm_info,
2766 SNB_READ_WM2_LATENCY() * 500,
2767 &sprite_wm);
2768 if (!ret) {
84f44ce7
VS		 2769 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2770 pipe_name(pipe));
b445e3b0
ED		 2771 return;
2772 }
2773 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2774
2775 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2776 pixel_size,
2777 &sandybridge_display_srwm_info,
2778 SNB_READ_WM3_LATENCY() * 500,
2779 &sprite_wm);
2780 if (!ret) {
84f44ce7
VS		 2781 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2782 pipe_name(pipe));
b445e3b0
ED		 2783 return;
2784 }
2785 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2786}
2787
2788/**
2789 * intel_update_watermarks - update FIFO watermark values based on current modes
2790 *
2791 * Calculate watermark values for the various WM regs based on current mode
2792 * and plane configuration.
2793 *
2794 * There are several cases to deal with here:
2795 * - normal (i.e. non-self-refresh)
2796 * - self-refresh (SR) mode
2797 * - lines are large relative to FIFO size (buffer can hold up to 2)
2798 * - lines are small relative to FIFO size (buffer can hold more than 2
2799 * lines), so need to account for TLB latency
2800 *
2801 * The normal calculation is:
2802 * watermark = dotclock * bytes per pixel * latency
2803 * where latency is platform & configuration dependent (we assume pessimal
2804 * values here).
2805 *
2806 * The SR calculation is:
2807 * watermark = (trunc(latency/line time)+1) * surface width *
2808 * bytes per pixel
2809 * where
2810 * line time = htotal / dotclock
2811 * surface width = hdisplay for normal plane and 64 for cursor
2812 * and latency is assumed to be high, as above.
2813 *
2814 * The final value programmed to the register should always be rounded up,
2815 * and include an extra 2 entries to account for clock crossings.
2816 *
2817 * We don't use the sprite, so we can ignore that. And on Crestline we have
2818 * to set the non-SR watermarks to 8.
2819 */
2820void intel_update_watermarks(struct drm_device *dev)
2821{
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823
2824 if (dev_priv->display.update_wm)
2825 dev_priv->display.update_wm(dev);
2826}
2827
2828void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2829 uint32_t sprite_width, int pixel_size,
2830 bool enable)
b445e3b0
ED		 2831{
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833
2834 if (dev_priv->display.update_sprite_wm)
2835 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4c4ff43a 2836 pixel_size, enable);
b445e3b0
ED		 2837}
2838
2b4e57bd
ED		 2839static struct drm_i915_gem_object *
2840intel_alloc_context_page(struct drm_device *dev)
2841{
2842 struct drm_i915_gem_object *ctx;
2843 int ret;
2844
2845 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2846
2847 ctx = i915_gem_alloc_object(dev, 4096);
2848 if (!ctx) {
2849 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2850 return NULL;
2851 }
2852
86a1ee26 2853 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2854 if (ret) {
2855 DRM_ERROR("failed to pin power context: %d\n", ret);
2856 goto err_unref;
2857 }
2858
2859 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2860 if (ret) {
2861 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2862 goto err_unpin;
2863 }
2864
2865 return ctx;
2866
2867err_unpin:
2868 i915_gem_object_unpin(ctx);
2869err_unref:
2870 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2871 return NULL;
2872}
2873
9270388e
DV		 2874/**
2875 * Lock protecting IPS related data structures
9270388e
DV		 2876 */
2877DEFINE_SPINLOCK(mchdev_lock);
2878
2879/* Global for IPS driver to get at the current i915 device. Protected by
2880 * mchdev_lock. */
2881static struct drm_i915_private *i915_mch_dev;
2882
2b4e57bd
ED		 2883bool ironlake_set_drps(struct drm_device *dev, u8 val)
2884{
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886 u16 rgvswctl;
2887
9270388e
DV		 2888 assert_spin_locked(&mchdev_lock);
2889
2b4e57bd
ED		 2890 rgvswctl = I915_READ16(MEMSWCTL);
2891 if (rgvswctl & MEMCTL_CMD_STS) {
2892 DRM_DEBUG("gpu busy, RCS change rejected\n");
2893 return false; /* still busy with another command */
2894 }
2895
2896 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2897 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2898 I915_WRITE16(MEMSWCTL, rgvswctl);
2899 POSTING_READ16(MEMSWCTL);
2900
2901 rgvswctl |= MEMCTL_CMD_STS;
2902 I915_WRITE16(MEMSWCTL, rgvswctl);
2903
2904 return true;
2905}
2906
8090c6b9 2907static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2908{
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 u32 rgvmodectl = I915_READ(MEMMODECTL);
2911 u8 fmax, fmin, fstart, vstart;
2912
9270388e
DV		 2913 spin_lock_irq(&mchdev_lock);
2914
2b4e57bd
ED		 2915 /* Enable temp reporting */
2916 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2917 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2918
2919 /* 100ms RC evaluation intervals */
2920 I915_WRITE(RCUPEI, 100000);
2921 I915_WRITE(RCDNEI, 100000);
2922
2923 /* Set max/min thresholds to 90ms and 80ms respectively */
2924 I915_WRITE(RCBMAXAVG, 90000);
2925 I915_WRITE(RCBMINAVG, 80000);
2926
2927 I915_WRITE(MEMIHYST, 1);
2928
2929 /* Set up min, max, and cur for interrupt handling */
2930 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2931 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2932 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2933 MEMMODE_FSTART_SHIFT;
2934
2935 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2936 PXVFREQ_PX_SHIFT;
2937
20e4d407
DV		 2938 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2939 dev_priv->ips.fstart = fstart;
2b4e57bd 2940
20e4d407
DV		 2941 dev_priv->ips.max_delay = fstart;
2942 dev_priv->ips.min_delay = fmin;
2943 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2944
2945 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2946 fmax, fmin, fstart);
2947
2948 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2949
2950 /*
2951 * Interrupts will be enabled in ironlake_irq_postinstall
2952 */
2953
2954 I915_WRITE(VIDSTART, vstart);
2955 POSTING_READ(VIDSTART);
2956
2957 rgvmodectl |= MEMMODE_SWMODE_EN;
2958 I915_WRITE(MEMMODECTL, rgvmodectl);
2959
9270388e 2960 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2961 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2962 mdelay(1);
2b4e57bd
ED		 2963
2964 ironlake_set_drps(dev, fstart);
2965
20e4d407 2966 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2967 I915_READ(0x112e0);
20e4d407
DV		 2968 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2969 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2970 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2971
2972 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2973}
2974
8090c6b9 2975static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2976{
2977 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2978 u16 rgvswctl;
2979
2980 spin_lock_irq(&mchdev_lock);
2981
2982 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2983
2984 /* Ack interrupts, disable EFC interrupt */
2985 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2986 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2987 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2988 I915_WRITE(DEIIR, DE_PCU_EVENT);
2989 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2990
2991 /* Go back to the starting frequency */
20e4d407 2992 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2993 mdelay(1);
2b4e57bd
ED		 2994 rgvswctl |= MEMCTL_CMD_STS;
2995 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2996 mdelay(1);
2b4e57bd 2997
9270388e 2998 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2999}
3000
acbe9475
DV		 3001/* There's a funny hw issue where the hw returns all 0 when reading from
3002 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3003 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3004 * all limits and the gpu stuck at whatever frequency it is at atm).
3005 */
65bccb5c 3006static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3007{
7b9e0ae6 3008 u32 limits;
2b4e57bd 3009
7b9e0ae6 3010 limits = 0;
c6a828d3
DV		 3011
3012 if (*val >= dev_priv->rps.max_delay)
3013 *val = dev_priv->rps.max_delay;
3014 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3015
3016 /* Only set the down limit when we've reached the lowest level to avoid
3017 * getting more interrupts, otherwise leave this clear. This prevents a
3018 * race in the hw when coming out of rc6: There's a tiny window where
3019 * the hw runs at the minimal clock before selecting the desired
3020 * frequency, if the down threshold expires in that window we will not
3021 * receive a down interrupt. */
c6a828d3
DV		 3022 if (*val <= dev_priv->rps.min_delay) {
3023 *val = dev_priv->rps.min_delay;
3024 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3025 }
3026
3027 return limits;
3028}
3029
3030void gen6_set_rps(struct drm_device *dev, u8 val)
3031{
3032 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3033 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3034
4fc688ce 3035 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3036 WARN_ON(val > dev_priv->rps.max_delay);
3037 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3038
c6a828d3 3039 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3040 return;
3041
92bd1bf0
RV		 3042 if (IS_HASWELL(dev))
3043 I915_WRITE(GEN6_RPNSWREQ,
3044 HSW_FREQUENCY(val));
3045 else
3046 I915_WRITE(GEN6_RPNSWREQ,
3047 GEN6_FREQUENCY(val) |
3048 GEN6_OFFSET(0) |
3049 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3050
3051 /* Make sure we continue to get interrupts
3052 * until we hit the minimum or maximum frequencies.
3053 */
3054 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3055
d5570a72
BW		 3056 POSTING_READ(GEN6_RPNSWREQ);
3057
c6a828d3 3058 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3059
3060 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3061}
3062
0a073b84
JB		 3063void valleyview_set_rps(struct drm_device *dev, u8 val)
3064{
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 unsigned long timeout = jiffies + msecs_to_jiffies(10);
3067 u32 limits = gen6_rps_limits(dev_priv, &val);
3068 u32 pval;
3069
3070 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3071 WARN_ON(val > dev_priv->rps.max_delay);
3072 WARN_ON(val < dev_priv->rps.min_delay);
3073
3074 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
3075 vlv_gpu_freq(dev_priv->mem_freq,
3076 dev_priv->rps.cur_delay),
3077 vlv_gpu_freq(dev_priv->mem_freq, val));
3078
3079 if (val == dev_priv->rps.cur_delay)
3080 return;
3081
ae99258f 3082 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84
JB		 3083
3084 do {
64936258 3085 pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3086 if (time_after(jiffies, timeout)) {
3087 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3088 break;
3089 }
3090 udelay(10);
3091 } while (pval & 1);
3092
64936258 3093 pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3094 if ((pval >> 8) != val)
3095 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
3096 val, pval >> 8);
3097
3098 /* Make sure we continue to get interrupts
3099 * until we hit the minimum or maximum frequencies.
3100 */
3101 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3102
3103 dev_priv->rps.cur_delay = pval >> 8;
3104
3105 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3106}
3107
3108
8090c6b9 3109static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 3110{
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112
88509484 3113 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 3114 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3115 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3116 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3117 /* Complete PM interrupt masking here doesn't race with the rps work
3118 * item again unmasking PM interrupts because that is using a different
3119 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3120 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3121
c6a828d3
DV		 3122 spin_lock_irq(&dev_priv->rps.lock);
3123 dev_priv->rps.pm_iir = 0;
3124 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd 3125
4848405c 3126 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3127}
3128
d20d4f0c
JB		 3129static void valleyview_disable_rps(struct drm_device *dev)
3130{
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132
3133 I915_WRITE(GEN6_RC_CONTROL, 0);
3134 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3135 I915_WRITE(GEN6_PMIER, 0);
3136 /* Complete PM interrupt masking here doesn't race with the rps work
3137 * item again unmasking PM interrupts because that is using a different
3138 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3139 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3140
3141 spin_lock_irq(&dev_priv->rps.lock);
3142 dev_priv->rps.pm_iir = 0;
3143 spin_unlock_irq(&dev_priv->rps.lock);
3144
3145 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
c9cddffc
JB		 3146
3147 if (dev_priv->vlv_pctx) {
3148 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3149 dev_priv->vlv_pctx = NULL;
3150 }
d20d4f0c
JB		 3151}
3152
2b4e57bd
ED		 3153int intel_enable_rc6(const struct drm_device *dev)
3154{
456470eb 3155 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3156 if (i915_enable_rc6 >= 0)
3157 return i915_enable_rc6;
3158
6567d748
CW		 3159 /* Disable RC6 on Ironlake */
3160 if (INTEL_INFO(dev)->gen == 5)
3161 return 0;
2b4e57bd 3162
456470eb
DV		 3163 if (IS_HASWELL(dev)) {
3164 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3165 return INTEL_RC6_ENABLE;
456470eb 3166 }
2b4e57bd 3167
456470eb 3168 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3169 if (INTEL_INFO(dev)->gen == 6) {
3170 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3171 return INTEL_RC6_ENABLE;
3172 }
456470eb 3173
2b4e57bd
ED		 3174 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3175 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3176}
3177
79f5b2c7 3178static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3179{
79f5b2c7 3180 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3181 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3182 u32 rp_state_cap;
3183 u32 gt_perf_status;
31643d54 3184 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3185 u32 gtfifodbg;
2b4e57bd 3186 int rc6_mode;
42c0526c 3187 int i, ret;
2b4e57bd 3188
4fc688ce 3189 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3190
2b4e57bd
ED		 3191 /* Here begins a magic sequence of register writes to enable
3192 * auto-downclocking.
3193 *
3194 * Perhaps there might be some value in exposing these to
3195 * userspace...
3196 */
3197 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3198
3199 /* Clear the DBG now so we don't confuse earlier errors */
3200 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3201 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3202 I915_WRITE(GTFIFODBG, gtfifodbg);
3203 }
3204
3205 gen6_gt_force_wake_get(dev_priv);
3206
7b9e0ae6
CW		 3207 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3208 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3209
31c77388
BW		 3210 /* In units of 50MHz */
3211 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3212 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3213 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3214
2b4e57bd
ED		 3215 /* disable the counters and set deterministic thresholds */
3216 I915_WRITE(GEN6_RC_CONTROL, 0);
3217
3218 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3219 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3220 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3221 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3222 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3223
b4519513
CW		 3224 for_each_ring(ring, dev_priv, i)
3225 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3226
3227 I915_WRITE(GEN6_RC_SLEEP, 0);
3228 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3229 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3230 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3231 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3232
5a7dc92a 3233 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3234 rc6_mode = intel_enable_rc6(dev_priv->dev);
3235 if (rc6_mode & INTEL_RC6_ENABLE)
3236 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3237
5a7dc92a
ED		 3238 /* We don't use those on Haswell */
3239 if (!IS_HASWELL(dev)) {
3240 if (rc6_mode & INTEL_RC6p_ENABLE)
3241 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3242
5a7dc92a
ED		 3243 if (rc6_mode & INTEL_RC6pp_ENABLE)
3244 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3245 }
2b4e57bd
ED		 3246
3247 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3248 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3249 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3250 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3251
3252 I915_WRITE(GEN6_RC_CONTROL,
3253 rc6_mask |
3254 GEN6_RC_CTL_EI_MODE(1) |
3255 GEN6_RC_CTL_HW_ENABLE);
3256
92bd1bf0
RV		 3257 if (IS_HASWELL(dev)) {
3258 I915_WRITE(GEN6_RPNSWREQ,
3259 HSW_FREQUENCY(10));
3260 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3261 HSW_FREQUENCY(12));
3262 } else {
3263 I915_WRITE(GEN6_RPNSWREQ,
3264 GEN6_FREQUENCY(10) |
3265 GEN6_OFFSET(0) |
3266 GEN6_AGGRESSIVE_TURBO);
3267 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3268 GEN6_FREQUENCY(12));
3269 }
2b4e57bd
ED		 3270
3271 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3272 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3273 dev_priv->rps.max_delay << 24 |
3274 dev_priv->rps.min_delay << 16);
5a7dc92a 3275
1ee9ae32
DV		 3276 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3277 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3278 I915_WRITE(GEN6_RP_UP_EI, 66000);
3279 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3280
2b4e57bd
ED		 3281 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3282 I915_WRITE(GEN6_RP_CONTROL,
3283 GEN6_RP_MEDIA_TURBO |
89ba829e 3284 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3285 GEN6_RP_MEDIA_IS_GFX |
3286 GEN6_RP_ENABLE |
3287 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3288 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3289
42c0526c 3290 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3291 if (!ret) {
42c0526c
BW		 3292 pcu_mbox = 0;
3293 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3294 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3295 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3296 (dev_priv->rps.max_delay & 0xff) * 50,
3297 (pcu_mbox & 0xff) * 50);
31c77388 3298 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3299 }
3300 } else {
3301 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3302 }
3303
7b9e0ae6 3304 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 3305
3306 /* requires MSI enabled */
4848405c 3307 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
c6a828d3 3308 spin_lock_irq(&dev_priv->rps.lock);
eda63ffb
BW		 3309 /* FIXME: Our interrupt enabling sequence is bonghits.
3310 * dev_priv->rps.pm_iir really should be 0 here. */
3311 dev_priv->rps.pm_iir = 0;
4848405c
BW		 3312 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3313 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
c6a828d3 3314 spin_unlock_irq(&dev_priv->rps.lock);
4848405c 3315 /* unmask all PM interrupts */
2b4e57bd
ED		 3316 I915_WRITE(GEN6_PMINTRMSK, 0);
3317
31643d54
BW		 3318 rc6vids = 0;
3319 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3320 if (IS_GEN6(dev) && ret) {
3321 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3322 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3323 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3324 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3325 rc6vids &= 0xffff00;
3326 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3327 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3328 if (ret)
3329 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3330 }
3331
2b4e57bd 3332 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3333}
3334
79f5b2c7 3335static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3336{
79f5b2c7 3337 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3338 int min_freq = 15;
3ebecd07
CW		 3339 unsigned int gpu_freq;
3340 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3341 int scaling_factor = 180;
3342
4fc688ce 3343 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3344
2b4e57bd
ED		 3345 max_ia_freq = cpufreq_quick_get_max(0);
3346 /*
3347 * Default to measured freq if none found, PCU will ensure we don't go
3348 * over
3349 */
3350 if (!max_ia_freq)
3351 max_ia_freq = tsc_khz;
3352
3353 /* Convert from kHz to MHz */
3354 max_ia_freq /= 1000;
3355
3ebecd07
CW		 3356 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3357 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3358 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3359
2b4e57bd
ED		 3360 /*
3361 * For each potential GPU frequency, load a ring frequency we'd like
3362 * to use for memory access. We do this by specifying the IA frequency
3363 * the PCU should use as a reference to determine the ring frequency.
3364 */
c6a828d3 3365 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3366 gpu_freq--) {
c6a828d3 3367 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3368 unsigned int ia_freq = 0, ring_freq = 0;
3369
3370 if (IS_HASWELL(dev)) {
3371 ring_freq = (gpu_freq * 5 + 3) / 4;
3372 ring_freq = max(min_ring_freq, ring_freq);
3373 /* leave ia_freq as the default, chosen by cpufreq */
3374 } else {
3375 /* On older processors, there is no separate ring
3376 * clock domain, so in order to boost the bandwidth
3377 * of the ring, we need to upclock the CPU (ia_freq).
3378 *
3379 * For GPU frequencies less than 750MHz,
3380 * just use the lowest ring freq.
3381 */
3382 if (gpu_freq < min_freq)
3383 ia_freq = 800;
3384 else
3385 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3386 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3387 }
2b4e57bd 3388
42c0526c
BW		 3389 sandybridge_pcode_write(dev_priv,
3390 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3391 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3392 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3393 gpu_freq);
2b4e57bd 3394 }
2b4e57bd
ED		 3395}
3396
0a073b84
JB		 3397int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3398{
3399 u32 val, rp0;
3400
64936258 3401 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3402
3403 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3404 /* Clamp to max */
3405 rp0 = min_t(u32, rp0, 0xea);
3406
3407 return rp0;
3408}
3409
3410static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3411{
3412 u32 val, rpe;
3413
64936258 3414 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3415 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3416 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3417 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3418
3419 return rpe;
3420}
3421
3422int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3423{
64936258 3424 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3425}
3426
52ceb908
JB		 3427static void vlv_rps_timer_work(struct work_struct *work)
3428{
3429 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3430 rps.vlv_work.work);
3431
3432 /*
3433 * Timer fired, we must be idle. Drop to min voltage state.
3434 * Note: we use RPe here since it should match the
3435 * Vmin we were shooting for. That should give us better
3436 * perf when we come back out of RC6 than if we used the
3437 * min freq available.
3438 */
3439 mutex_lock(&dev_priv->rps.hw_lock);
3440 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3441 mutex_unlock(&dev_priv->rps.hw_lock);
3442}
3443
c9cddffc
JB		 3444static void valleyview_setup_pctx(struct drm_device *dev)
3445{
3446 struct drm_i915_private *dev_priv = dev->dev_private;
3447 struct drm_i915_gem_object *pctx;
3448 unsigned long pctx_paddr;
3449 u32 pcbr;
3450 int pctx_size = 24*1024;
3451
3452 pcbr = I915_READ(VLV_PCBR);
3453 if (pcbr) {
3454 /* BIOS set it up already, grab the pre-alloc'd space */
3455 int pcbr_offset;
3456
3457 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3458 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3459 pcbr_offset,
3727d55e 3460 -1,
c9cddffc
JB		 3461 pctx_size);
3462 goto out;
3463 }
3464
3465 /*
3466 * From the Gunit register HAS:
3467 * The Gfx driver is expected to program this register and ensure
3468 * proper allocation within Gfx stolen memory. For example, this
3469 * register should be programmed such than the PCBR range does not
3470 * overlap with other ranges, such as the frame buffer, protected
3471 * memory, or any other relevant ranges.
3472 */
3473 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3474 if (!pctx) {
3475 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3476 return;
3477 }
3478
3479 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3480 I915_WRITE(VLV_PCBR, pctx_paddr);
3481
3482out:
3483 dev_priv->vlv_pctx = pctx;
3484}
3485
0a073b84
JB		 3486static void valleyview_enable_rps(struct drm_device *dev)
3487{
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_ring_buffer *ring;
3490 u32 gtfifodbg, val, rpe;
3491 int i;
3492
3493 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3494
3495 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3496 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3497 I915_WRITE(GTFIFODBG, gtfifodbg);
3498 }
3499
c9cddffc
JB		 3500 valleyview_setup_pctx(dev);
3501
0a073b84
JB		 3502 gen6_gt_force_wake_get(dev_priv);
3503
3504 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3505 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3506 I915_WRITE(GEN6_RP_UP_EI, 66000);
3507 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3508
3509 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3510
3511 I915_WRITE(GEN6_RP_CONTROL,
3512 GEN6_RP_MEDIA_TURBO |
3513 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3514 GEN6_RP_MEDIA_IS_GFX |
3515 GEN6_RP_ENABLE |
3516 GEN6_RP_UP_BUSY_AVG |
3517 GEN6_RP_DOWN_IDLE_CONT);
3518
3519 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3520 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3521 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3522
3523 for_each_ring(ring, dev_priv, i)
3524 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3525
3526 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3527
3528 /* allows RC6 residency counter to work */
3529 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3530 I915_WRITE(GEN6_RC_CONTROL,
3531 GEN7_RC_CTL_TO_MODE);
3532
64936258 3533 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3534 switch ((val >> 6) & 3) {
3535 case 0:
3536 case 1:
3537 dev_priv->mem_freq = 800;
3538 break;
3539 case 2:
3540 dev_priv->mem_freq = 1066;
3541 break;
3542 case 3:
3543 dev_priv->mem_freq = 1333;
3544 break;
3545 }
0a073b84
JB		 3546 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3547
3548 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3549 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3550
3551 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3552 vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3553 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3554
3555 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3556 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3557 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3558 dev_priv->rps.max_delay));
3559
3560 rpe = valleyview_rps_rpe_freq(dev_priv);
3561 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3562 vlv_gpu_freq(dev_priv->mem_freq, rpe));
52ceb908 3563 dev_priv->rps.rpe_delay = rpe;
0a073b84
JB		 3564
3565 val = valleyview_rps_min_freq(dev_priv);
3566 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3567 val));
3568 dev_priv->rps.min_delay = val;
3569
3570 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3571 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3572
52ceb908
JB		 3573 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3574
0a073b84
JB		 3575 valleyview_set_rps(dev_priv->dev, rpe);
3576
3577 /* requires MSI enabled */
4848405c 3578 I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
0a073b84
JB		 3579 spin_lock_irq(&dev_priv->rps.lock);
3580 WARN_ON(dev_priv->rps.pm_iir != 0);
3581 I915_WRITE(GEN6_PMIMR, 0);
3582 spin_unlock_irq(&dev_priv->rps.lock);
3583 /* enable all PM interrupts */
3584 I915_WRITE(GEN6_PMINTRMSK, 0);
3585
3586 gen6_gt_force_wake_put(dev_priv);
3587}
3588
930ebb46 3589void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3590{
3591 struct drm_i915_private *dev_priv = dev->dev_private;
3592
3e373948
DV		 3593 if (dev_priv->ips.renderctx) {
3594 i915_gem_object_unpin(dev_priv->ips.renderctx);
3595 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3596 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3597 }
3598
3e373948
DV		 3599 if (dev_priv->ips.pwrctx) {
3600 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3601 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3602 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3603 }
3604}
3605
930ebb46 3606static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3607{
3608 struct drm_i915_private *dev_priv = dev->dev_private;
3609
3610 if (I915_READ(PWRCTXA)) {
3611 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3612 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3613 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3614 50);
3615
3616 I915_WRITE(PWRCTXA, 0);
3617 POSTING_READ(PWRCTXA);
3618
3619 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3620 POSTING_READ(RSTDBYCTL);
3621 }
2b4e57bd
ED		 3622}
3623
3624static int ironlake_setup_rc6(struct drm_device *dev)
3625{
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627
3e373948
DV		 3628 if (dev_priv->ips.renderctx == NULL)
3629 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3630 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3631 return -ENOMEM;
3632
3e373948
DV		 3633 if (dev_priv->ips.pwrctx == NULL)
3634 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3635 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3636 ironlake_teardown_rc6(dev);
3637 return -ENOMEM;
3638 }
3639
3640 return 0;
3641}
3642
930ebb46 3643static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3644{
3645 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3646 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3647 bool was_interruptible;
2b4e57bd
ED		 3648 int ret;
3649
3650 /* rc6 disabled by default due to repeated reports of hanging during
3651 * boot and resume.
3652 */
3653 if (!intel_enable_rc6(dev))
3654 return;
3655
79f5b2c7
DV		 3656 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3657
2b4e57bd 3658 ret = ironlake_setup_rc6(dev);
79f5b2c7 3659 if (ret)
2b4e57bd 3660 return;
2b4e57bd 3661
3e960501
CW		 3662 was_interruptible = dev_priv->mm.interruptible;
3663 dev_priv->mm.interruptible = false;
3664
2b4e57bd
ED		 3665 /*
3666 * GPU can automatically power down the render unit if given a page
3667 * to save state.
3668 */
6d90c952 3669 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3670 if (ret) {
3671 ironlake_teardown_rc6(dev);
3e960501 3672 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3673 return;
3674 }
3675
6d90c952
DV		 3676 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3677 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 3678 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 3679 MI_MM_SPACE_GTT |
3680 MI_SAVE_EXT_STATE_EN |
3681 MI_RESTORE_EXT_STATE_EN |
3682 MI_RESTORE_INHIBIT);
3683 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3684 intel_ring_emit(ring, MI_NOOP);
3685 intel_ring_emit(ring, MI_FLUSH);
3686 intel_ring_advance(ring);
2b4e57bd
ED		 3687
3688 /*
3689 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3690 * does an implicit flush, combined with MI_FLUSH above, it should be
3691 * safe to assume that renderctx is valid
3692 */
3e960501
CW		 3693 ret = intel_ring_idle(ring);
3694 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3695 if (ret) {
def27a58 3696 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3697 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3698 return;
3699 }
3700
3e373948 3701 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 3702 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3703}
3704
dde18883
ED		 3705static unsigned long intel_pxfreq(u32 vidfreq)
3706{
3707 unsigned long freq;
3708 int div = (vidfreq & 0x3f0000) >> 16;
3709 int post = (vidfreq & 0x3000) >> 12;
3710 int pre = (vidfreq & 0x7);
3711
3712 if (!pre)
3713 return 0;
3714
3715 freq = ((div * 133333) / ((1<<post) * pre));
3716
3717 return freq;
3718}
3719
eb48eb00
DV		 3720static const struct cparams {
3721 u16 i;
3722 u16 t;
3723 u16 m;
3724 u16 c;
3725} cparams[] = {
3726 { 1, 1333, 301, 28664 },
3727 { 1, 1066, 294, 24460 },
3728 { 1, 800, 294, 25192 },
3729 { 0, 1333, 276, 27605 },
3730 { 0, 1066, 276, 27605 },
3731 { 0, 800, 231, 23784 },
3732};
3733
f531dcb2 3734static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3735{
3736 u64 total_count, diff, ret;
3737 u32 count1, count2, count3, m = 0, c = 0;
3738 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3739 int i;
3740
02d71956
DV		 3741 assert_spin_locked(&mchdev_lock);
3742
20e4d407 3743 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3744
3745 /* Prevent division-by-zero if we are asking too fast.
3746 * Also, we don't get interesting results if we are polling
3747 * faster than once in 10ms, so just return the saved value
3748 * in such cases.
3749 */
3750 if (diff1 <= 10)
20e4d407 3751 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3752
3753 count1 = I915_READ(DMIEC);
3754 count2 = I915_READ(DDREC);
3755 count3 = I915_READ(CSIEC);
3756
3757 total_count = count1 + count2 + count3;
3758
3759 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3760 if (total_count < dev_priv->ips.last_count1) {
3761 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3762 diff += total_count;
3763 } else {
20e4d407 3764 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3765 }
3766
3767 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3768 if (cparams[i].i == dev_priv->ips.c_m &&
3769 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3770 m = cparams[i].m;
3771 c = cparams[i].c;
3772 break;
3773 }
3774 }
3775
3776 diff = div_u64(diff, diff1);
3777 ret = ((m * diff) + c);
3778 ret = div_u64(ret, 10);
3779
20e4d407
DV		 3780 dev_priv->ips.last_count1 = total_count;
3781 dev_priv->ips.last_time1 = now;
eb48eb00 3782
20e4d407 3783 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3784
3785 return ret;
3786}
3787
f531dcb2
CW		 3788unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3789{
3790 unsigned long val;
3791
3792 if (dev_priv->info->gen != 5)
3793 return 0;
3794
3795 spin_lock_irq(&mchdev_lock);
3796
3797 val = __i915_chipset_val(dev_priv);
3798
3799 spin_unlock_irq(&mchdev_lock);
3800
3801 return val;
3802}
3803
eb48eb00
DV		 3804unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3805{
3806 unsigned long m, x, b;
3807 u32 tsfs;
3808
3809 tsfs = I915_READ(TSFS);
3810
3811 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3812 x = I915_READ8(TR1);
3813
3814 b = tsfs & TSFS_INTR_MASK;
3815
3816 return ((m * x) / 127) - b;
3817}
3818
3819static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3820{
3821 static const struct v_table {
3822 u16 vd; /* in .1 mil */
3823 u16 vm; /* in .1 mil */
3824 } v_table[] = {
3825 { 0, 0, },
3826 { 375, 0, },
3827 { 500, 0, },
3828 { 625, 0, },
3829 { 750, 0, },
3830 { 875, 0, },
3831 { 1000, 0, },
3832 { 1125, 0, },
3833 { 4125, 3000, },
3834 { 4125, 3000, },
3835 { 4125, 3000, },
3836 { 4125, 3000, },
3837 { 4125, 3000, },
3838 { 4125, 3000, },
3839 { 4125, 3000, },
3840 { 4125, 3000, },
3841 { 4125, 3000, },
3842 { 4125, 3000, },
3843 { 4125, 3000, },
3844 { 4125, 3000, },
3845 { 4125, 3000, },
3846 { 4125, 3000, },
3847 { 4125, 3000, },
3848 { 4125, 3000, },
3849 { 4125, 3000, },
3850 { 4125, 3000, },
3851 { 4125, 3000, },
3852 { 4125, 3000, },
3853 { 4125, 3000, },
3854 { 4125, 3000, },
3855 { 4125, 3000, },
3856 { 4125, 3000, },
3857 { 4250, 3125, },
3858 { 4375, 3250, },
3859 { 4500, 3375, },
3860 { 4625, 3500, },
3861 { 4750, 3625, },
3862 { 4875, 3750, },
3863 { 5000, 3875, },
3864 { 5125, 4000, },
3865 { 5250, 4125, },
3866 { 5375, 4250, },
3867 { 5500, 4375, },
3868 { 5625, 4500, },
3869 { 5750, 4625, },
3870 { 5875, 4750, },
3871 { 6000, 4875, },
3872 { 6125, 5000, },
3873 { 6250, 5125, },
3874 { 6375, 5250, },
3875 { 6500, 5375, },
3876 { 6625, 5500, },
3877 { 6750, 5625, },
3878 { 6875, 5750, },
3879 { 7000, 5875, },
3880 { 7125, 6000, },
3881 { 7250, 6125, },
3882 { 7375, 6250, },
3883 { 7500, 6375, },
3884 { 7625, 6500, },
3885 { 7750, 6625, },
3886 { 7875, 6750, },
3887 { 8000, 6875, },
3888 { 8125, 7000, },
3889 { 8250, 7125, },
3890 { 8375, 7250, },
3891 { 8500, 7375, },
3892 { 8625, 7500, },
3893 { 8750, 7625, },
3894 { 8875, 7750, },
3895 { 9000, 7875, },
3896 { 9125, 8000, },
3897 { 9250, 8125, },
3898 { 9375, 8250, },
3899 { 9500, 8375, },
3900 { 9625, 8500, },
3901 { 9750, 8625, },
3902 { 9875, 8750, },
3903 { 10000, 8875, },
3904 { 10125, 9000, },
3905 { 10250, 9125, },
3906 { 10375, 9250, },
3907 { 10500, 9375, },
3908 { 10625, 9500, },
3909 { 10750, 9625, },
3910 { 10875, 9750, },
3911 { 11000, 9875, },
3912 { 11125, 10000, },
3913 { 11250, 10125, },
3914 { 11375, 10250, },
3915 { 11500, 10375, },
3916 { 11625, 10500, },
3917 { 11750, 10625, },
3918 { 11875, 10750, },
3919 { 12000, 10875, },
3920 { 12125, 11000, },
3921 { 12250, 11125, },
3922 { 12375, 11250, },
3923 { 12500, 11375, },
3924 { 12625, 11500, },
3925 { 12750, 11625, },
3926 { 12875, 11750, },
3927 { 13000, 11875, },
3928 { 13125, 12000, },
3929 { 13250, 12125, },
3930 { 13375, 12250, },
3931 { 13500, 12375, },
3932 { 13625, 12500, },
3933 { 13750, 12625, },
3934 { 13875, 12750, },
3935 { 14000, 12875, },
3936 { 14125, 13000, },
3937 { 14250, 13125, },
3938 { 14375, 13250, },
3939 { 14500, 13375, },
3940 { 14625, 13500, },
3941 { 14750, 13625, },
3942 { 14875, 13750, },
3943 { 15000, 13875, },
3944 { 15125, 14000, },
3945 { 15250, 14125, },
3946 { 15375, 14250, },
3947 { 15500, 14375, },
3948 { 15625, 14500, },
3949 { 15750, 14625, },
3950 { 15875, 14750, },
3951 { 16000, 14875, },
3952 { 16125, 15000, },
3953 };
3954 if (dev_priv->info->is_mobile)
3955 return v_table[pxvid].vm;
3956 else
3957 return v_table[pxvid].vd;
3958}
3959
02d71956 3960static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3961{
3962 struct timespec now, diff1;
3963 u64 diff;
3964 unsigned long diffms;
3965 u32 count;
3966
02d71956 3967 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3968
3969 getrawmonotonic(&now);
20e4d407 3970 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3971
3972 /* Don't divide by 0 */
3973 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3974 if (!diffms)
3975 return;
3976
3977 count = I915_READ(GFXEC);
3978
20e4d407
DV		 3979 if (count < dev_priv->ips.last_count2) {
3980 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 3981 diff += count;
3982 } else {
20e4d407 3983 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 3984 }
3985
20e4d407
DV		 3986 dev_priv->ips.last_count2 = count;
3987 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 3988
3989 /* More magic constants... */
3990 diff = diff * 1181;
3991 diff = div_u64(diff, diffms * 10);
20e4d407 3992 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3993}
3994
02d71956
DV		 3995void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3996{
3997 if (dev_priv->info->gen != 5)
3998 return;
3999
9270388e 4000 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4001
4002 __i915_update_gfx_val(dev_priv);
4003
9270388e 4004 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4005}
4006
f531dcb2 4007static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4008{
4009 unsigned long t, corr, state1, corr2, state2;
4010 u32 pxvid, ext_v;
4011
02d71956
DV		 4012 assert_spin_locked(&mchdev_lock);
4013
c6a828d3 4014 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4015 pxvid = (pxvid >> 24) & 0x7f;
4016 ext_v = pvid_to_extvid(dev_priv, pxvid);
4017
4018 state1 = ext_v;
4019
4020 t = i915_mch_val(dev_priv);
4021
4022 /* Revel in the empirically derived constants */
4023
4024 /* Correction factor in 1/100000 units */
4025 if (t > 80)
4026 corr = ((t * 2349) + 135940);
4027 else if (t >= 50)
4028 corr = ((t * 964) + 29317);
4029 else /* < 50 */
4030 corr = ((t * 301) + 1004);
4031
4032 corr = corr * ((150142 * state1) / 10000 - 78642);
4033 corr /= 100000;
20e4d407 4034 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4035
4036 state2 = (corr2 * state1) / 10000;
4037 state2 /= 100; /* convert to mW */
4038
02d71956 4039 __i915_update_gfx_val(dev_priv);
eb48eb00 4040
20e4d407 4041 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4042}
4043
f531dcb2
CW		 4044unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4045{
4046 unsigned long val;
4047
4048 if (dev_priv->info->gen != 5)
4049 return 0;
4050
4051 spin_lock_irq(&mchdev_lock);
4052
4053 val = __i915_gfx_val(dev_priv);
4054
4055 spin_unlock_irq(&mchdev_lock);
4056
4057 return val;
4058}
4059
eb48eb00
DV		 4060/**
4061 * i915_read_mch_val - return value for IPS use
4062 *
4063 * Calculate and return a value for the IPS driver to use when deciding whether
4064 * we have thermal and power headroom to increase CPU or GPU power budget.
4065 */
4066unsigned long i915_read_mch_val(void)
4067{
4068 struct drm_i915_private *dev_priv;
4069 unsigned long chipset_val, graphics_val, ret = 0;
4070
9270388e 4071 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4072 if (!i915_mch_dev)
4073 goto out_unlock;
4074 dev_priv = i915_mch_dev;
4075
f531dcb2
CW		 4076 chipset_val = __i915_chipset_val(dev_priv);
4077 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4078
4079 ret = chipset_val + graphics_val;
4080
4081out_unlock:
9270388e 4082 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4083
4084 return ret;
4085}
4086EXPORT_SYMBOL_GPL(i915_read_mch_val);
4087
4088/**
4089 * i915_gpu_raise - raise GPU frequency limit
4090 *
4091 * Raise the limit; IPS indicates we have thermal headroom.
4092 */
4093bool i915_gpu_raise(void)
4094{
4095 struct drm_i915_private *dev_priv;
4096 bool ret = true;
4097
9270388e 4098 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4099 if (!i915_mch_dev) {
4100 ret = false;
4101 goto out_unlock;
4102 }
4103 dev_priv = i915_mch_dev;
4104
20e4d407
DV		 4105 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4106 dev_priv->ips.max_delay--;
eb48eb00
DV		 4107
4108out_unlock:
9270388e 4109 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4110
4111 return ret;
4112}
4113EXPORT_SYMBOL_GPL(i915_gpu_raise);
4114
4115/**
4116 * i915_gpu_lower - lower GPU frequency limit
4117 *
4118 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4119 * frequency maximum.
4120 */
4121bool i915_gpu_lower(void)
4122{
4123 struct drm_i915_private *dev_priv;
4124 bool ret = true;
4125
9270388e 4126 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4127 if (!i915_mch_dev) {
4128 ret = false;
4129 goto out_unlock;
4130 }
4131 dev_priv = i915_mch_dev;
4132
20e4d407
DV		 4133 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4134 dev_priv->ips.max_delay++;
eb48eb00
DV		 4135
4136out_unlock:
9270388e 4137 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4138
4139 return ret;
4140}
4141EXPORT_SYMBOL_GPL(i915_gpu_lower);
4142
4143/**
4144 * i915_gpu_busy - indicate GPU business to IPS
4145 *
4146 * Tell the IPS driver whether or not the GPU is busy.
4147 */
4148bool i915_gpu_busy(void)
4149{
4150 struct drm_i915_private *dev_priv;
f047e395 4151 struct intel_ring_buffer *ring;
eb48eb00 4152 bool ret = false;
f047e395 4153 int i;
eb48eb00 4154
9270388e 4155 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4156 if (!i915_mch_dev)
4157 goto out_unlock;
4158 dev_priv = i915_mch_dev;
4159
f047e395
CW		 4160 for_each_ring(ring, dev_priv, i)
4161 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4162
4163out_unlock:
9270388e 4164 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4165
4166 return ret;
4167}
4168EXPORT_SYMBOL_GPL(i915_gpu_busy);
4169
4170/**
4171 * i915_gpu_turbo_disable - disable graphics turbo
4172 *
4173 * Disable graphics turbo by resetting the max frequency and setting the
4174 * current frequency to the default.
4175 */
4176bool i915_gpu_turbo_disable(void)
4177{
4178 struct drm_i915_private *dev_priv;
4179 bool ret = true;
4180
9270388e 4181 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4182 if (!i915_mch_dev) {
4183 ret = false;
4184 goto out_unlock;
4185 }
4186 dev_priv = i915_mch_dev;
4187
20e4d407 4188 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4189
20e4d407 4190 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4191 ret = false;
4192
4193out_unlock:
9270388e 4194 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4195
4196 return ret;
4197}
4198EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4199
4200/**
4201 * Tells the intel_ips driver that the i915 driver is now loaded, if
4202 * IPS got loaded first.
4203 *
4204 * This awkward dance is so that neither module has to depend on the
4205 * other in order for IPS to do the appropriate communication of
4206 * GPU turbo limits to i915.
4207 */
4208static void
4209ips_ping_for_i915_load(void)
4210{
4211 void (*link)(void);
4212
4213 link = symbol_get(ips_link_to_i915_driver);
4214 if (link) {
4215 link();
4216 symbol_put(ips_link_to_i915_driver);
4217 }
4218}
4219
4220void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4221{
02d71956
DV		 4222 /* We only register the i915 ips part with intel-ips once everything is
4223 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4224 spin_lock_irq(&mchdev_lock);
eb48eb00 4225 i915_mch_dev = dev_priv;
9270388e 4226 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4227
4228 ips_ping_for_i915_load();
4229}
4230
4231void intel_gpu_ips_teardown(void)
4232{
9270388e 4233 spin_lock_irq(&mchdev_lock);
eb48eb00 4234 i915_mch_dev = NULL;
9270388e 4235 spin_unlock_irq(&mchdev_lock);
eb48eb00 4236}
8090c6b9 4237static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4238{
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 u32 lcfuse;
4241 u8 pxw[16];
4242 int i;
4243
4244 /* Disable to program */
4245 I915_WRITE(ECR, 0);
4246 POSTING_READ(ECR);
4247
4248 /* Program energy weights for various events */
4249 I915_WRITE(SDEW, 0x15040d00);
4250 I915_WRITE(CSIEW0, 0x007f0000);
4251 I915_WRITE(CSIEW1, 0x1e220004);
4252 I915_WRITE(CSIEW2, 0x04000004);
4253
4254 for (i = 0; i < 5; i++)
4255 I915_WRITE(PEW + (i * 4), 0);
4256 for (i = 0; i < 3; i++)
4257 I915_WRITE(DEW + (i * 4), 0);
4258
4259 /* Program P-state weights to account for frequency power adjustment */
4260 for (i = 0; i < 16; i++) {
4261 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4262 unsigned long freq = intel_pxfreq(pxvidfreq);
4263 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4264 PXVFREQ_PX_SHIFT;
4265 unsigned long val;
4266
4267 val = vid * vid;
4268 val *= (freq / 1000);
4269 val *= 255;
4270 val /= (127*127*900);
4271 if (val > 0xff)
4272 DRM_ERROR("bad pxval: %ld\n", val);
4273 pxw[i] = val;
4274 }
4275 /* Render standby states get 0 weight */
4276 pxw[14] = 0;
4277 pxw[15] = 0;
4278
4279 for (i = 0; i < 4; i++) {
4280 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4281 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4282 I915_WRITE(PXW + (i * 4), val);
4283 }
4284
4285 /* Adjust magic regs to magic values (more experimental results) */
4286 I915_WRITE(OGW0, 0);
4287 I915_WRITE(OGW1, 0);
4288 I915_WRITE(EG0, 0x00007f00);
4289 I915_WRITE(EG1, 0x0000000e);
4290 I915_WRITE(EG2, 0x000e0000);
4291 I915_WRITE(EG3, 0x68000300);
4292 I915_WRITE(EG4, 0x42000000);
4293 I915_WRITE(EG5, 0x00140031);
4294 I915_WRITE(EG6, 0);
4295 I915_WRITE(EG7, 0);
4296
4297 for (i = 0; i < 8; i++)
4298 I915_WRITE(PXWL + (i * 4), 0);
4299
4300 /* Enable PMON + select events */
4301 I915_WRITE(ECR, 0x80000019);
4302
4303 lcfuse = I915_READ(LCFUSE02);
4304
20e4d407 4305 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4306}
4307
8090c6b9
DV		 4308void intel_disable_gt_powersave(struct drm_device *dev)
4309{
1a01ab3b
JB		 4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311
fd0c0642
DV		 4312 /* Interrupts should be disabled already to avoid re-arming. */
4313 WARN_ON(dev->irq_enabled);
4314
930ebb46 4315 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4316 ironlake_disable_drps(dev);
930ebb46 4317 ironlake_disable_rc6(dev);
0a073b84 4318 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4319 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4320 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4321 if (IS_VALLEYVIEW(dev))
4322 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4323 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4324 if (IS_VALLEYVIEW(dev))
4325 valleyview_disable_rps(dev);
4326 else
4327 gen6_disable_rps(dev);
4fc688ce 4328 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4329 }
8090c6b9
DV		 4330}
4331
1a01ab3b
JB		 4332static void intel_gen6_powersave_work(struct work_struct *work)
4333{
4334 struct drm_i915_private *dev_priv =
4335 container_of(work, struct drm_i915_private,
4336 rps.delayed_resume_work.work);
4337 struct drm_device *dev = dev_priv->dev;
4338
4fc688ce 4339 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4340
4341 if (IS_VALLEYVIEW(dev)) {
4342 valleyview_enable_rps(dev);
4343 } else {
4344 gen6_enable_rps(dev);
4345 gen6_update_ring_freq(dev);
4346 }
4fc688ce 4347 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4348}
4349
8090c6b9
DV		 4350void intel_enable_gt_powersave(struct drm_device *dev)
4351{
1a01ab3b
JB		 4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353
8090c6b9
DV		 4354 if (IS_IRONLAKE_M(dev)) {
4355 ironlake_enable_drps(dev);
4356 ironlake_enable_rc6(dev);
4357 intel_init_emon(dev);
0a073b84 4358 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4359 /*
4360 * PCU communication is slow and this doesn't need to be
4361 * done at any specific time, so do this out of our fast path
4362 * to make resume and init faster.
4363 */
4364 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4365 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4366 }
4367}
4368
3107bd48
DV		 4369static void ibx_init_clock_gating(struct drm_device *dev)
4370{
4371 struct drm_i915_private *dev_priv = dev->dev_private;
4372
4373 /*
4374 * On Ibex Peak and Cougar Point, we need to disable clock
4375 * gating for the panel power sequencer or it will fail to
4376 * start up when no ports are active.
4377 */
4378 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4379}
4380
1fa61106 4381static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4382{
4383 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4384 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 4385
4386 /* Required for FBC */
4d47e4f5
DL		 4387 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4388 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4389 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4390
4391 I915_WRITE(PCH_3DCGDIS0,
4392 MARIUNIT_CLOCK_GATE_DISABLE |
4393 SVSMUNIT_CLOCK_GATE_DISABLE);
4394 I915_WRITE(PCH_3DCGDIS1,
4395 VFMUNIT_CLOCK_GATE_DISABLE);
4396
6f1d69b0
ED		 4397 /*
4398 * According to the spec the following bits should be set in
4399 * order to enable memory self-refresh
4400 * The bit 22/21 of 0x42004
4401 * The bit 5 of 0x42020
4402 * The bit 15 of 0x45000
4403 */
4404 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4405 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4406 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4407 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4408 I915_WRITE(DISP_ARB_CTL,
4409 (I915_READ(DISP_ARB_CTL) |
4410 DISP_FBC_WM_DIS));
4411 I915_WRITE(WM3_LP_ILK, 0);
4412 I915_WRITE(WM2_LP_ILK, 0);
4413 I915_WRITE(WM1_LP_ILK, 0);
4414
4415 /*
4416 * Based on the document from hardware guys the following bits
4417 * should be set unconditionally in order to enable FBC.
4418 * The bit 22 of 0x42000
4419 * The bit 22 of 0x42004
4420 * The bit 7,8,9 of 0x42020.
4421 */
4422 if (IS_IRONLAKE_M(dev)) {
4423 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4424 I915_READ(ILK_DISPLAY_CHICKEN1) |
4425 ILK_FBCQ_DIS);
4426 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4427 I915_READ(ILK_DISPLAY_CHICKEN2) |
4428 ILK_DPARB_GATE);
6f1d69b0
ED		 4429 }
4430
4d47e4f5
DL		 4431 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4432
6f1d69b0
ED		 4433 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4434 I915_READ(ILK_DISPLAY_CHICKEN2) |
4435 ILK_ELPIN_409_SELECT);
4436 I915_WRITE(_3D_CHICKEN2,
4437 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4438 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4439
ecdb4eb7 4440 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4441 I915_WRITE(CACHE_MODE_0,
4442 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 4443
4444 ibx_init_clock_gating(dev);
4445}
4446
4447static void cpt_init_clock_gating(struct drm_device *dev)
4448{
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450 int pipe;
3f704fa2 4451 uint32_t val;
3107bd48
DV		 4452
4453 /*
4454 * On Ibex Peak and Cougar Point, we need to disable clock
4455 * gating for the panel power sequencer or it will fail to
4456 * start up when no ports are active.
4457 */
4458 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4459 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4460 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4461 /* The below fixes the weird display corruption, a few pixels shifted
4462 * downward, on (only) LVDS of some HP laptops with IVY.
4463 */
3f704fa2 4464 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4465 val = I915_READ(TRANS_CHICKEN2(pipe));
4466 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4467 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4468 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4469 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4470 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4471 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4472 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4473 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4474 }
3107bd48
DV		 4475 /* WADP0ClockGatingDisable */
4476 for_each_pipe(pipe) {
4477 I915_WRITE(TRANS_CHICKEN1(pipe),
4478 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4479 }
6f1d69b0
ED		 4480}
4481
1d7aaa0c
DV		 4482static void gen6_check_mch_setup(struct drm_device *dev)
4483{
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485 uint32_t tmp;
4486
4487 tmp = I915_READ(MCH_SSKPD);
4488 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4489 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4490 DRM_INFO("This can cause pipe underruns and display issues.\n");
4491 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4492 }
4493}
4494
1fa61106 4495static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4496{
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 int pipe;
231e54f6 4499 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4500
231e54f6 4501 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4502
4503 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4504 I915_READ(ILK_DISPLAY_CHICKEN2) |
4505 ILK_ELPIN_409_SELECT);
4506
ecdb4eb7 4507 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4508 I915_WRITE(_3D_CHICKEN,
4509 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4510
ecdb4eb7 4511 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4512 if (IS_SNB_GT1(dev))
4513 I915_WRITE(GEN6_GT_MODE,
4514 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4515
6f1d69b0
ED		 4516 I915_WRITE(WM3_LP_ILK, 0);
4517 I915_WRITE(WM2_LP_ILK, 0);
4518 I915_WRITE(WM1_LP_ILK, 0);
4519
6f1d69b0 4520 I915_WRITE(CACHE_MODE_0,
50743298 4521 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4522
4523 I915_WRITE(GEN6_UCGCTL1,
4524 I915_READ(GEN6_UCGCTL1) |
4525 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4526 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4527
4528 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4529 * gating disable must be set. Failure to set it results in
4530 * flickering pixels due to Z write ordering failures after
4531 * some amount of runtime in the Mesa "fire" demo, and Unigine
4532 * Sanctuary and Tropics, and apparently anything else with
4533 * alpha test or pixel discard.
4534 *
4535 * According to the spec, bit 11 (RCCUNIT) must also be set,
4536 * but we didn't debug actual testcases to find it out.
0f846f81 4537 *
ecdb4eb7
DL		 4538 * Also apply WaDisableVDSUnitClockGating:snb and
4539 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4540 */
4541 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4542 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4543 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4544 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4545
4546 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4547 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4548 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4549
4550 /*
4551 * According to the spec the following bits should be
4552 * set in order to enable memory self-refresh and fbc:
4553 * The bit21 and bit22 of 0x42000
4554 * The bit21 and bit22 of 0x42004
4555 * The bit5 and bit7 of 0x42020
4556 * The bit14 of 0x70180
4557 * The bit14 of 0x71180
4558 */
4559 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4560 I915_READ(ILK_DISPLAY_CHICKEN1) |
4561 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4562 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4563 I915_READ(ILK_DISPLAY_CHICKEN2) |
4564 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4565 I915_WRITE(ILK_DSPCLK_GATE_D,
4566 I915_READ(ILK_DSPCLK_GATE_D) |
4567 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4568 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4569
ecdb4eb7 4570 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4571 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4572 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4573
6f1d69b0
ED		 4574 for_each_pipe(pipe) {
4575 I915_WRITE(DSPCNTR(pipe),
4576 I915_READ(DSPCNTR(pipe)) |
4577 DISPPLANE_TRICKLE_FEED_DISABLE);
4578 intel_flush_display_plane(dev_priv, pipe);
4579 }
f8f2ac9a
BW		 4580
4581 /* The default value should be 0x200 according to docs, but the two
4582 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4583 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4584 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4585
4586 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4587
4588 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4589}
4590
4591static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4592{
4593 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4594
4595 reg &= ~GEN7_FF_SCHED_MASK;
4596 reg |= GEN7_FF_TS_SCHED_HW;
4597 reg |= GEN7_FF_VS_SCHED_HW;
4598 reg |= GEN7_FF_DS_SCHED_HW;
4599
41c0b3a8
BW		 4600 if (IS_HASWELL(dev_priv->dev))
4601 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4602
6f1d69b0
ED		 4603 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4604}
4605
17a303ec
PZ		 4606static void lpt_init_clock_gating(struct drm_device *dev)
4607{
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609
4610 /*
4611 * TODO: this bit should only be enabled when really needed, then
4612 * disabled when not needed anymore in order to save power.
4613 */
4614 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4615 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4616 I915_READ(SOUTH_DSPCLK_GATE_D) |
4617 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4618
4619 /* WADPOClockGatingDisable:hsw */
4620 I915_WRITE(_TRANSA_CHICKEN1,
4621 I915_READ(_TRANSA_CHICKEN1) |
4622 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4623}
4624
7d708ee4
ID		 4625static void lpt_suspend_hw(struct drm_device *dev)
4626{
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628
4629 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4630 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4631
4632 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4633 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4634 }
4635}
4636
cad2a2d7
ED		 4637static void haswell_init_clock_gating(struct drm_device *dev)
4638{
4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640 int pipe;
cad2a2d7
ED		 4641
4642 I915_WRITE(WM3_LP_ILK, 0);
4643 I915_WRITE(WM2_LP_ILK, 0);
4644 I915_WRITE(WM1_LP_ILK, 0);
4645
4646 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4647 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4648 */
4649 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4650
ecdb4eb7 4651 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4652 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4653 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4654
ecdb4eb7 4655 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4656 I915_WRITE(GEN7_L3CNTLREG1,
4657 GEN7_WA_FOR_GEN7_L3_CONTROL);
4658 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4659 GEN7_WA_L3_CHICKEN_MODE);
4660
ecdb4eb7 4661 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4662 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4663 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4664 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4665
4666 for_each_pipe(pipe) {
4667 I915_WRITE(DSPCNTR(pipe),
4668 I915_READ(DSPCNTR(pipe)) |
4669 DISPPLANE_TRICKLE_FEED_DISABLE);
4670 intel_flush_display_plane(dev_priv, pipe);
4671 }
4672
ecdb4eb7 4673 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4674 gen7_setup_fixed_func_scheduler(dev_priv);
4675
ecdb4eb7 4676 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4677 I915_WRITE(CACHE_MODE_1,
4678 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4679
ecdb4eb7 4680 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4681 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4682 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4683
ecdb4eb7 4684 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4685 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4686
90a88643
PZ		 4687 /* WaRsPkgCStateDisplayPMReq:hsw */
4688 I915_WRITE(CHICKEN_PAR1_1,
4689 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4690
17a303ec 4691 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4692}
4693
1fa61106 4694static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4695{
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 int pipe;
20848223 4698 uint32_t snpcr;
6f1d69b0 4699
6f1d69b0
ED		 4700 I915_WRITE(WM3_LP_ILK, 0);
4701 I915_WRITE(WM2_LP_ILK, 0);
4702 I915_WRITE(WM1_LP_ILK, 0);
4703
231e54f6 4704 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4705
ecdb4eb7 4706 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4707 I915_WRITE(_3D_CHICKEN3,
4708 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4709
ecdb4eb7 4710 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4711 I915_WRITE(IVB_CHICKEN3,
4712 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4713 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4714
ecdb4eb7 4715 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4716 if (IS_IVB_GT1(dev))
4717 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4718 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4719 else
4720 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4721 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4722
ecdb4eb7 4723 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4724 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4725 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4726
ecdb4eb7 4727 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4728 I915_WRITE(GEN7_L3CNTLREG1,
4729 GEN7_WA_FOR_GEN7_L3_CONTROL);
4730 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4731 GEN7_WA_L3_CHICKEN_MODE);
4732 if (IS_IVB_GT1(dev))
4733 I915_WRITE(GEN7_ROW_CHICKEN2,
4734 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4735 else
4736 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4737 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4738
6f1d69b0 4739
ecdb4eb7 4740 /* WaForceL3Serialization:ivb */
61939d97
JB		 4741 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4742 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4743
0f846f81
JB		 4744 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4745 * gating disable must be set. Failure to set it results in
4746 * flickering pixels due to Z write ordering failures after
4747 * some amount of runtime in the Mesa "fire" demo, and Unigine
4748 * Sanctuary and Tropics, and apparently anything else with
4749 * alpha test or pixel discard.
4750 *
4751 * According to the spec, bit 11 (RCCUNIT) must also be set,
4752 * but we didn't debug actual testcases to find it out.
4753 *
4754 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4755 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4756 */
4757 I915_WRITE(GEN6_UCGCTL2,
4758 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4759 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4760
ecdb4eb7 4761 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4762 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4763 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4764 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4765
4766 for_each_pipe(pipe) {
4767 I915_WRITE(DSPCNTR(pipe),
4768 I915_READ(DSPCNTR(pipe)) |
4769 DISPPLANE_TRICKLE_FEED_DISABLE);
4770 intel_flush_display_plane(dev_priv, pipe);
4771 }
4772
ecdb4eb7 4773 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4774 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4775 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4776
ecdb4eb7 4777 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4778 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4779
ecdb4eb7 4780 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4781 I915_WRITE(CACHE_MODE_1,
4782 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4783
4784 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4785 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4786 snpcr |= GEN6_MBC_SNPCR_MED;
4787 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4788
ab5c608b
BW		 4789 if (!HAS_PCH_NOP(dev))
4790 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4791
4792 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4793}
4794
1fa61106 4795static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4796{
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 int pipe;
6f1d69b0 4799
d7fe0cc0 4800 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4801
ecdb4eb7 4802 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4803 I915_WRITE(_3D_CHICKEN3,
4804 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4805
ecdb4eb7 4806 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4807 I915_WRITE(IVB_CHICKEN3,
4808 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4809 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4810
ecdb4eb7 4811 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4812 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4813 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4814 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4815
ecdb4eb7 4816 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4817 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4818 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4819
ecdb4eb7 4820 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4821 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4822 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4823
ecdb4eb7 4824 /* WaForceL3Serialization:vlv */
61939d97
JB		 4825 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4826 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4827
ecdb4eb7 4828 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4829 I915_WRITE(GEN7_ROW_CHICKEN2,
4830 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4831
ecdb4eb7 4832 /* WaForceL3Serialization:vlv */
5c9664d7
JB		 4833 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4834 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4835
ecdb4eb7 4836 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4837 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4838 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4839 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4840
ecdb4eb7 4841 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4842 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4843 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4844
0f846f81
JB		 4845
4846 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4847 * gating disable must be set. Failure to set it results in
4848 * flickering pixels due to Z write ordering failures after
4849 * some amount of runtime in the Mesa "fire" demo, and Unigine
4850 * Sanctuary and Tropics, and apparently anything else with
4851 * alpha test or pixel discard.
4852 *
4853 * According to the spec, bit 11 (RCCUNIT) must also be set,
4854 * but we didn't debug actual testcases to find it out.
4855 *
4856 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4857 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4858 *
ecdb4eb7
DL		 4859 * Also apply WaDisableVDSUnitClockGating:vlv and
4860 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4861 */
4862 I915_WRITE(GEN6_UCGCTL2,
4863 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4864 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4865 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4866 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4867 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4868
e3f33d46
JB		 4869 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4870
6f1d69b0
ED		 4871 for_each_pipe(pipe) {
4872 I915_WRITE(DSPCNTR(pipe),
4873 I915_READ(DSPCNTR(pipe)) |
4874 DISPPLANE_TRICKLE_FEED_DISABLE);
4875 intel_flush_display_plane(dev_priv, pipe);
4876 }
4877
6b26c86d
DV		 4878 I915_WRITE(CACHE_MODE_1,
4879 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4880
2d809570 4881 /*
ecdb4eb7 4882 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4883 * Disable clock gating on th GCFG unit to prevent a delay
4884 * in the reporting of vblank events.
4885 */
4e8c84a5
JB		 4886 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4887
4888 /* Conservative clock gating settings for now */
4889 I915_WRITE(0x9400, 0xffffffff);
4890 I915_WRITE(0x9404, 0xffffffff);
4891 I915_WRITE(0x9408, 0xffffffff);
4892 I915_WRITE(0x940c, 0xffffffff);
4893 I915_WRITE(0x9410, 0xffffffff);
4894 I915_WRITE(0x9414, 0xffffffff);
4895 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4896}
4897
1fa61106 4898static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4899{
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901 uint32_t dspclk_gate;
4902
4903 I915_WRITE(RENCLK_GATE_D1, 0);
4904 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4905 GS_UNIT_CLOCK_GATE_DISABLE |
4906 CL_UNIT_CLOCK_GATE_DISABLE);
4907 I915_WRITE(RAMCLK_GATE_D, 0);
4908 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4909 OVRUNIT_CLOCK_GATE_DISABLE |
4910 OVCUNIT_CLOCK_GATE_DISABLE;
4911 if (IS_GM45(dev))
4912 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4913 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4914
4915 /* WaDisableRenderCachePipelinedFlush */
4916 I915_WRITE(CACHE_MODE_0,
4917 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 4918}
4919
1fa61106 4920static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4921{
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923
4924 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4925 I915_WRITE(RENCLK_GATE_D2, 0);
4926 I915_WRITE(DSPCLK_GATE_D, 0);
4927 I915_WRITE(RAMCLK_GATE_D, 0);
4928 I915_WRITE16(DEUC, 0);
4929}
4930
1fa61106 4931static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4932{
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934
4935 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4936 I965_RCC_CLOCK_GATE_DISABLE |
4937 I965_RCPB_CLOCK_GATE_DISABLE |
4938 I965_ISC_CLOCK_GATE_DISABLE |
4939 I965_FBC_CLOCK_GATE_DISABLE);
4940 I915_WRITE(RENCLK_GATE_D2, 0);
4941}
4942
1fa61106 4943static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4944{
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 u32 dstate = I915_READ(D_STATE);
4947
4948 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4949 DSTATE_DOT_CLOCK_GATING;
4950 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4951
4952 if (IS_PINEVIEW(dev))
4953 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4954
4955 /* IIR "flip pending" means done if this bit is set */
4956 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4957}
4958
1fa61106 4959static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4960{
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962
4963 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4964}
4965
1fa61106 4966static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4967{
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969
4970 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4971}
4972
6f1d69b0
ED		 4973void intel_init_clock_gating(struct drm_device *dev)
4974{
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976
4977 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4978}
4979
7d708ee4
ID		 4980void intel_suspend_hw(struct drm_device *dev)
4981{
4982 if (HAS_PCH_LPT(dev))
4983 lpt_suspend_hw(dev);
4984}
4985
15d199ea
PZ		 4986/**
4987 * We should only use the power well if we explicitly asked the hardware to
4988 * enable it, so check if it's enabled and also check if we've requested it to
4989 * be enabled.
4990 */
b97186f0
PZ		 4991bool intel_display_power_enabled(struct drm_device *dev,
4992 enum intel_display_power_domain domain)
15d199ea
PZ		 4993{
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4995
b97186f0
PZ		 4996 if (!HAS_POWER_WELL(dev))
4997 return true;
4998
4999 switch (domain) {
5000 case POWER_DOMAIN_PIPE_A:
5001 case POWER_DOMAIN_TRANSCODER_EDP:
5002 return true;
5003 case POWER_DOMAIN_PIPE_B:
5004 case POWER_DOMAIN_PIPE_C:
5005 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5006 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5007 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5008 case POWER_DOMAIN_TRANSCODER_A:
5009 case POWER_DOMAIN_TRANSCODER_B:
5010 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5011 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5012 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5013 default:
5014 BUG();
5015 }
15d199ea
PZ		 5016}
5017
cb10799c 5018void intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5019{
5020 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5021 bool is_enabled, enable_requested;
5022 uint32_t tmp;
d0d3e513 5023
86d52df6 5024 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5025 return;
5026
2124b72e
PZ		 5027 if (!i915_disable_power_well && !enable)
5028 return;
5029
fa42e23c
PZ		 5030 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5031 is_enabled = tmp & HSW_PWR_WELL_STATE;
5032 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5033
fa42e23c
PZ		 5034 if (enable) {
5035 if (!enable_requested)
5036 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5037
fa42e23c
PZ		 5038 if (!is_enabled) {
5039 DRM_DEBUG_KMS("Enabling power well\n");
5040 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5041 HSW_PWR_WELL_STATE), 20))
5042 DRM_ERROR("Timeout enabling power well\n");
5043 }
5044 } else {
5045 if (enable_requested) {
5046 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5047 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5048 }
5049 }
fa42e23c 5050}
d0d3e513 5051
fa42e23c
PZ		 5052/*
5053 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5054 * when not needed anymore. We have 4 registers that can request the power well
5055 * to be enabled, and it will only be disabled if none of the registers is
5056 * requesting it to be enabled.
d0d3e513 5057 */
fa42e23c 5058void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5059{
5060 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5061
86d52df6 5062 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5063 return;
5064
fa42e23c
PZ		 5065 /* For now, we need the power well to be always enabled. */
5066 intel_set_power_well(dev, true);
d0d3e513 5067
fa42e23c
PZ		 5068 /* We're taking over the BIOS, so clear any requests made by it since
5069 * the driver is in charge now. */
5070 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5071 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5072}
5073
1fa61106
ED		 5074/* Set up chip specific power management-related functions */
5075void intel_init_pm(struct drm_device *dev)
5076{
5077 struct drm_i915_private *dev_priv = dev->dev_private;
5078
5079 if (I915_HAS_FBC(dev)) {
5080 if (HAS_PCH_SPLIT(dev)) {
5081 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5082 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5083 dev_priv->display.enable_fbc =
5084 gen7_enable_fbc;
5085 else
5086 dev_priv->display.enable_fbc =
5087 ironlake_enable_fbc;
1fa61106
ED		 5088 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5089 } else if (IS_GM45(dev)) {
5090 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5091 dev_priv->display.enable_fbc = g4x_enable_fbc;
5092 dev_priv->display.disable_fbc = g4x_disable_fbc;
5093 } else if (IS_CRESTLINE(dev)) {
5094 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5095 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5096 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5097 }
5098 /* 855GM needs testing */
5099 }
5100
c921aba8
DV		 5101 /* For cxsr */
5102 if (IS_PINEVIEW(dev))
5103 i915_pineview_get_mem_freq(dev);
5104 else if (IS_GEN5(dev))
5105 i915_ironlake_get_mem_freq(dev);
5106
1fa61106
ED		 5107 /* For FIFO watermark updates */
5108 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 5109 if (IS_GEN5(dev)) {
5110 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5111 dev_priv->display.update_wm = ironlake_update_wm;
5112 else {
5113 DRM_DEBUG_KMS("Failed to get proper latency. "
5114 "Disable CxSR\n");
5115 dev_priv->display.update_wm = NULL;
5116 }
5117 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5118 } else if (IS_GEN6(dev)) {
5119 if (SNB_READ_WM0_LATENCY()) {
5120 dev_priv->display.update_wm = sandybridge_update_wm;
5121 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5122 } else {
5123 DRM_DEBUG_KMS("Failed to read display plane latency. "
5124 "Disable CxSR\n");
5125 dev_priv->display.update_wm = NULL;
5126 }
5127 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5128 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 5129 if (SNB_READ_WM0_LATENCY()) {
c43d0188 5130 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5131 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5132 } else {
5133 DRM_DEBUG_KMS("Failed to read display plane latency. "
5134 "Disable CxSR\n");
5135 dev_priv->display.update_wm = NULL;
5136 }
5137 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5138 } else if (IS_HASWELL(dev)) {
3e1f7266 5139 if (I915_READ64(MCH_SSKPD)) {
1011d8c4 5140 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5141 dev_priv->display.update_sprite_wm =
5142 haswell_update_sprite_wm;
6b8a5eeb
ED		 5143 } else {
5144 DRM_DEBUG_KMS("Failed to read display plane latency. "
5145 "Disable CxSR\n");
5146 dev_priv->display.update_wm = NULL;
5147 }
cad2a2d7 5148 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5149 } else
5150 dev_priv->display.update_wm = NULL;
5151 } else if (IS_VALLEYVIEW(dev)) {
5152 dev_priv->display.update_wm = valleyview_update_wm;
5153 dev_priv->display.init_clock_gating =
5154 valleyview_init_clock_gating;
1fa61106
ED		 5155 } else if (IS_PINEVIEW(dev)) {
5156 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5157 dev_priv->is_ddr3,
5158 dev_priv->fsb_freq,
5159 dev_priv->mem_freq)) {
5160 DRM_INFO("failed to find known CxSR latency "
5161 "(found ddr%s fsb freq %d, mem freq %d), "
5162 "disabling CxSR\n",
5163 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5164 dev_priv->fsb_freq, dev_priv->mem_freq);
5165 /* Disable CxSR and never update its watermark again */
5166 pineview_disable_cxsr(dev);
5167 dev_priv->display.update_wm = NULL;
5168 } else
5169 dev_priv->display.update_wm = pineview_update_wm;
5170 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5171 } else if (IS_G4X(dev)) {
5172 dev_priv->display.update_wm = g4x_update_wm;
5173 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5174 } else if (IS_GEN4(dev)) {
5175 dev_priv->display.update_wm = i965_update_wm;
5176 if (IS_CRESTLINE(dev))
5177 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5178 else if (IS_BROADWATER(dev))
5179 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5180 } else if (IS_GEN3(dev)) {
5181 dev_priv->display.update_wm = i9xx_update_wm;
5182 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5183 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5184 } else if (IS_I865G(dev)) {
5185 dev_priv->display.update_wm = i830_update_wm;
5186 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5187 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5188 } else if (IS_I85X(dev)) {
5189 dev_priv->display.update_wm = i9xx_update_wm;
5190 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5191 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5192 } else {
5193 dev_priv->display.update_wm = i830_update_wm;
5194 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5195 if (IS_845G(dev))
5196 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5197 else
5198 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5199 }
5200}
5201
6590190d
ED		 5202static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
5203{
5204 u32 gt_thread_status_mask;
5205
5206 if (IS_HASWELL(dev_priv->dev))
5207 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
5208 else
5209 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
5210
5211 /* w/a for a sporadic read returning 0 by waiting for the GT
5212 * thread to wake up.
5213 */
5214 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
5215 DRM_ERROR("GT thread status wait timed out\n");
5216}
5217
16995a9f
CW		 5218static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
5219{
5220 I915_WRITE_NOTRACE(FORCEWAKE, 0);
5221 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
5222}
5223
6590190d
ED		 5224static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5225{
ebd37ce1 5226 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
057d3860 5227 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5228 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5229
30771e16 5230 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 5231 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 5232
ebd37ce1 5233 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
057d3860 5234 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5235 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5236
8693a824 5237 /* WaRsForcewakeWaitTC0:snb */
6590190d
ED		 5238 __gen6_gt_wait_for_thread_c0(dev_priv);
5239}
5240
16995a9f
CW		 5241static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
5242{
5243 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5244 /* something from same cacheline, but !FORCEWAKE_MT */
5245 POSTING_READ(ECOBUS);
16995a9f
CW		 5246}
5247
6590190d
ED		 5248static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
5249{
5250 u32 forcewake_ack;
5251
5252 if (IS_HASWELL(dev_priv->dev))
5253 forcewake_ack = FORCEWAKE_ACK_HSW;
5254 else
5255 forcewake_ack = FORCEWAKE_MT_ACK;
5256
83983c8b 5257 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
057d3860 5258 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5259 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5260
c5836c27 5261 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5262 /* something from same cacheline, but !FORCEWAKE_MT */
5263 POSTING_READ(ECOBUS);
6590190d 5264
83983c8b 5265 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
057d3860 5266 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5267 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5268
8693a824 5269 /* WaRsForcewakeWaitTC0:ivb,hsw */
6590190d
ED		 5270 __gen6_gt_wait_for_thread_c0(dev_priv);
5271}
5272
5273/*
5274 * Generally this is called implicitly by the register read function. However,
5275 * if some sequence requires the GT to not power down then this function should
5276 * be called at the beginning of the sequence followed by a call to
5277 * gen6_gt_force_wake_put() at the end of the sequence.
5278 */
5279void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5280{
5281 unsigned long irqflags;
5282
5283 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5284 if (dev_priv->forcewake_count++ == 0)
5285 dev_priv->gt.force_wake_get(dev_priv);
5286 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5287}
5288
5289void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
5290{
5291 u32 gtfifodbg;
5292 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
5293 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
5294 "MMIO read or write has been dropped %x\n", gtfifodbg))
5295 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
5296}
5297
5298static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5299{
5300 I915_WRITE_NOTRACE(FORCEWAKE, 0);
b5144075
JN		 5301 /* something from same cacheline, but !FORCEWAKE */
5302 POSTING_READ(ECOBUS);
6590190d
ED		 5303 gen6_gt_check_fifodbg(dev_priv);
5304}
5305
5306static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
5307{
c5836c27 5308 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5309 /* something from same cacheline, but !FORCEWAKE_MT */
5310 POSTING_READ(ECOBUS);
6590190d
ED		 5311 gen6_gt_check_fifodbg(dev_priv);
5312}
5313
5314/*
5315 * see gen6_gt_force_wake_get()
5316 */
5317void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5318{
5319 unsigned long irqflags;
5320
5321 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5322 if (--dev_priv->forcewake_count == 0)
5323 dev_priv->gt.force_wake_put(dev_priv);
5324 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5325}
5326
5327int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
5328{
5329 int ret = 0;
5330
5331 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
5332 int loop = 500;
5333 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5334 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
5335 udelay(10);
5336 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5337 }
5338 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
5339 ++ret;
5340 dev_priv->gt_fifo_count = fifo;
5341 }
5342 dev_priv->gt_fifo_count--;
5343
5344 return ret;
5345}
5346
16995a9f
CW		 5347static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
5348{
5349 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5350 /* something from same cacheline, but !FORCEWAKE_VLV */
5351 POSTING_READ(FORCEWAKE_ACK_VLV);
16995a9f
CW		 5352}
5353
6590190d
ED		 5354static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
5355{
83983c8b 5356 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
057d3860 5357 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5358 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5359
c5836c27 5360 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5361 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5362 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 5363
83983c8b 5364 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
057d3860 5365 FORCEWAKE_ACK_TIMEOUT_MS))
ed5de399
JB		 5366 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5367
5368 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
5369 FORCEWAKE_KERNEL),
5370 FORCEWAKE_ACK_TIMEOUT_MS))
5371 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
6590190d 5372
8693a824 5373 /* WaRsForcewakeWaitTC0:vlv */
6590190d
ED		 5374 __gen6_gt_wait_for_thread_c0(dev_priv);
5375}
5376
5377static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
5378{
c5836c27 5379 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5380 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5381 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5382 /* The below doubles as a POSTING_READ */
5ab140a4 5383 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 5384}
5385
16995a9f
CW		 5386void intel_gt_reset(struct drm_device *dev)
5387{
5388 struct drm_i915_private *dev_priv = dev->dev_private;
5389
5390 if (IS_VALLEYVIEW(dev)) {
5391 vlv_force_wake_reset(dev_priv);
5392 } else if (INTEL_INFO(dev)->gen >= 6) {
5393 __gen6_gt_force_wake_reset(dev_priv);
5394 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5395 __gen6_gt_force_wake_mt_reset(dev_priv);
5396 }
5397}
5398
6590190d
ED		 5399void intel_gt_init(struct drm_device *dev)
5400{
5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402
5403 spin_lock_init(&dev_priv->gt_lock);
5404
16995a9f
CW		 5405 intel_gt_reset(dev);
5406
6590190d
ED		 5407 if (IS_VALLEYVIEW(dev)) {
5408 dev_priv->gt.force_wake_get = vlv_force_wake_get;
5409 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 5410 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5411 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
5412 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
5413 } else if (IS_GEN6(dev)) {
6590190d
ED		 5414 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
5415 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 5416 }
1a01ab3b
JB		 5417 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5418 intel_gen6_powersave_work);
6590190d
ED		 5419}
5420
42c0526c
BW		 5421int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5422{
4fc688ce 5423 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5424
5425 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5426 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5427 return -EAGAIN;
5428 }
5429
5430 I915_WRITE(GEN6_PCODE_DATA, *val);
5431 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5432
5433 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5434 500)) {
5435 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5436 return -ETIMEDOUT;
5437 }
5438
5439 *val = I915_READ(GEN6_PCODE_DATA);
5440 I915_WRITE(GEN6_PCODE_DATA, 0);
5441
5442 return 0;
5443}
5444
5445int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5446{
4fc688ce 5447 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5448
5449 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5450 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5451 return -EAGAIN;
5452 }
5453
5454 I915_WRITE(GEN6_PCODE_DATA, val);
5455 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5456
5457 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5458 500)) {
5459 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5460 return -ETIMEDOUT;
5461 }
5462
5463 I915_WRITE(GEN6_PCODE_DATA, 0);
5464
5465 return 0;
5466}
a0e4e199 5467
855ba3be
JB		 5468int vlv_gpu_freq(int ddr_freq, int val)
5469{
5470 int mult, base;
5471
5472 switch (ddr_freq) {
5473 case 800:
5474 mult = 20;
5475 base = 120;
5476 break;
5477 case 1066:
5478 mult = 22;
5479 base = 133;
5480 break;
5481 case 1333:
5482 mult = 21;
5483 base = 125;
5484 break;
5485 default:
5486 return -1;
5487 }
5488
5489 return ((val - 0xbd) * mult) + base;
5490}
5491
5492int vlv_freq_opcode(int ddr_freq, int val)
5493{
5494 int mult, base;
5495
5496 switch (ddr_freq) {
5497 case 800:
5498 mult = 20;
5499 base = 120;
5500 break;
5501 case 1066:
5502 mult = 22;
5503 base = 133;
5504 break;
5505 case 1333:
5506 mult = 21;
5507 base = 125;
5508 break;
5509 default:
5510 return -1;
5511 }
5512
5513 val /= mult;
5514 val -= base / mult;
5515 val += 0xbd;
5516
5517 if (val > 0xea)
5518 val = 0xea;
5519
5520 return val;
5521}
5522
Linux kernel - Deliverables
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