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Merge branch 'for_3.8-rc1' into v4l_for_linus
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
1fa61106 47static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 48{
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 u32 fbc_ctl;
51
52 /* Disable compression */
53 fbc_ctl = I915_READ(FBC_CONTROL);
54 if ((fbc_ctl & FBC_CTL_EN) == 0)
55 return;
56
57 fbc_ctl &= ~FBC_CTL_EN;
58 I915_WRITE(FBC_CONTROL, fbc_ctl);
59
60 /* Wait for compressing bit to clear */
61 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
62 DRM_DEBUG_KMS("FBC idle timed out\n");
63 return;
64 }
65
66 DRM_DEBUG_KMS("disabled FBC\n");
67}
68
1fa61106 69static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 70{
71 struct drm_device *dev = crtc->dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 struct drm_framebuffer *fb = crtc->fb;
74 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
75 struct drm_i915_gem_object *obj = intel_fb->obj;
76 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
77 int cfb_pitch;
78 int plane, i;
79 u32 fbc_ctl, fbc_ctl2;
80
81 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
82 if (fb->pitches[0] < cfb_pitch)
83 cfb_pitch = fb->pitches[0];
84
85 /* FBC_CTL wants 64B units */
86 cfb_pitch = (cfb_pitch / 64) - 1;
87 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
88
89 /* Clear old tags */
90 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
91 I915_WRITE(FBC_TAG + (i * 4), 0);
92
93 /* Set it up... */
94 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
95 fbc_ctl2 |= plane;
96 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
97 I915_WRITE(FBC_FENCE_OFF, crtc->y);
98
99 /* enable it... */
100 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
101 if (IS_I945GM(dev))
102 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
103 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
104 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
105 fbc_ctl |= obj->fence_reg;
106 I915_WRITE(FBC_CONTROL, fbc_ctl);
107
108 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
109 cfb_pitch, crtc->y, intel_crtc->plane);
110}
111
1fa61106 112static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 113{
114 struct drm_i915_private *dev_priv = dev->dev_private;
115
116 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
117}
118
1fa61106 119static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 120{
121 struct drm_device *dev = crtc->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct drm_framebuffer *fb = crtc->fb;
124 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
125 struct drm_i915_gem_object *obj = intel_fb->obj;
126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
127 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
128 unsigned long stall_watermark = 200;
129 u32 dpfc_ctl;
130
131 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
132 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
133 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
134
135 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
136 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
137 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
138 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
139
140 /* enable it... */
141 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
142
143 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
144}
145
1fa61106 146static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 147{
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 u32 dpfc_ctl;
150
151 /* Disable compression */
152 dpfc_ctl = I915_READ(DPFC_CONTROL);
153 if (dpfc_ctl & DPFC_CTL_EN) {
154 dpfc_ctl &= ~DPFC_CTL_EN;
155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
156
157 DRM_DEBUG_KMS("disabled FBC\n");
158 }
159}
160
1fa61106 161static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
166}
167
168static void sandybridge_blit_fbc_update(struct drm_device *dev)
169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 u32 blt_ecoskpd;
172
173 /* Make sure blitter notifies FBC of writes */
174 gen6_gt_force_wake_get(dev_priv);
175 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
176 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
177 GEN6_BLITTER_LOCK_SHIFT;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
179 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
180 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
181 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
182 GEN6_BLITTER_LOCK_SHIFT);
183 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
184 POSTING_READ(GEN6_BLITTER_ECOSKPD);
185 gen6_gt_force_wake_put(dev_priv);
186}
187
1fa61106 188static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 189{
190 struct drm_device *dev = crtc->dev;
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_framebuffer *fb = crtc->fb;
193 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
194 struct drm_i915_gem_object *obj = intel_fb->obj;
195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
196 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
197 unsigned long stall_watermark = 200;
198 u32 dpfc_ctl;
199
200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
201 dpfc_ctl &= DPFC_RESERVED;
202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
203 /* Set persistent mode for front-buffer rendering, ala X. */
204 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
205 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
206 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
207
208 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
209 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
210 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
211 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
212 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
213 /* enable it... */
214 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
215
216 if (IS_GEN6(dev)) {
217 I915_WRITE(SNB_DPFC_CTL_SA,
218 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
219 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
220 sandybridge_blit_fbc_update(dev);
221 }
222
223 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
224}
225
1fa61106 226static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 u32 dpfc_ctl;
230
231 /* Disable compression */
232 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
233 if (dpfc_ctl & DPFC_CTL_EN) {
234 dpfc_ctl &= ~DPFC_CTL_EN;
235 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
236
237 DRM_DEBUG_KMS("disabled FBC\n");
238 }
239}
240
1fa61106 241static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 242{
243 struct drm_i915_private *dev_priv = dev->dev_private;
244
245 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
246}
247
248bool intel_fbc_enabled(struct drm_device *dev)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251
252 if (!dev_priv->display.fbc_enabled)
253 return false;
254
255 return dev_priv->display.fbc_enabled(dev);
256}
257
258static void intel_fbc_work_fn(struct work_struct *__work)
259{
260 struct intel_fbc_work *work =
261 container_of(to_delayed_work(__work),
262 struct intel_fbc_work, work);
263 struct drm_device *dev = work->crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
265
266 mutex_lock(&dev->struct_mutex);
267 if (work == dev_priv->fbc_work) {
268 /* Double check that we haven't switched fb without cancelling
269 * the prior work.
270 */
271 if (work->crtc->fb == work->fb) {
272 dev_priv->display.enable_fbc(work->crtc,
273 work->interval);
274
275 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
276 dev_priv->cfb_fb = work->crtc->fb->base.id;
277 dev_priv->cfb_y = work->crtc->y;
278 }
279
280 dev_priv->fbc_work = NULL;
281 }
282 mutex_unlock(&dev->struct_mutex);
283
284 kfree(work);
285}
286
287static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
288{
289 if (dev_priv->fbc_work == NULL)
290 return;
291
292 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
293
294 /* Synchronisation is provided by struct_mutex and checking of
295 * dev_priv->fbc_work, so we can perform the cancellation
296 * entirely asynchronously.
297 */
298 if (cancel_delayed_work(&dev_priv->fbc_work->work))
299 /* tasklet was killed before being run, clean up */
300 kfree(dev_priv->fbc_work);
301
302 /* Mark the work as no longer wanted so that if it does
303 * wake-up (because the work was already running and waiting
304 * for our mutex), it will discover that is no longer
305 * necessary to run.
306 */
307 dev_priv->fbc_work = NULL;
308}
309
310void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
311{
312 struct intel_fbc_work *work;
313 struct drm_device *dev = crtc->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 if (!dev_priv->display.enable_fbc)
317 return;
318
319 intel_cancel_fbc_work(dev_priv);
320
321 work = kzalloc(sizeof *work, GFP_KERNEL);
322 if (work == NULL) {
323 dev_priv->display.enable_fbc(crtc, interval);
324 return;
325 }
326
327 work->crtc = crtc;
328 work->fb = crtc->fb;
329 work->interval = interval;
330 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
331
332 dev_priv->fbc_work = work;
333
334 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
335
336 /* Delay the actual enabling to let pageflipping cease and the
337 * display to settle before starting the compression. Note that
338 * this delay also serves a second purpose: it allows for a
339 * vblank to pass after disabling the FBC before we attempt
340 * to modify the control registers.
341 *
342 * A more complicated solution would involve tracking vblanks
343 * following the termination of the page-flipping sequence
344 * and indeed performing the enable as a co-routine and not
345 * waiting synchronously upon the vblank.
346 */
347 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
348}
349
350void intel_disable_fbc(struct drm_device *dev)
351{
352 struct drm_i915_private *dev_priv = dev->dev_private;
353
354 intel_cancel_fbc_work(dev_priv);
355
356 if (!dev_priv->display.disable_fbc)
357 return;
358
359 dev_priv->display.disable_fbc(dev);
360 dev_priv->cfb_plane = -1;
361}
362
363/**
364 * intel_update_fbc - enable/disable FBC as needed
365 * @dev: the drm_device
366 *
367 * Set up the framebuffer compression hardware at mode set time. We
368 * enable it if possible:
369 * - plane A only (on pre-965)
370 * - no pixel mulitply/line duplication
371 * - no alpha buffer discard
372 * - no dual wide
373 * - framebuffer <= 2048 in width, 1536 in height
374 *
375 * We can't assume that any compression will take place (worst case),
376 * so the compressed buffer has to be the same size as the uncompressed
377 * one. It also must reside (along with the line length buffer) in
378 * stolen memory.
379 *
380 * We need to enable/disable FBC on a global basis.
381 */
382void intel_update_fbc(struct drm_device *dev)
383{
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 struct drm_crtc *crtc = NULL, *tmp_crtc;
386 struct intel_crtc *intel_crtc;
387 struct drm_framebuffer *fb;
388 struct intel_framebuffer *intel_fb;
389 struct drm_i915_gem_object *obj;
390 int enable_fbc;
391
85208be0
ED		 392 if (!i915_powersave)
393 return;
394
395 if (!I915_HAS_FBC(dev))
396 return;
397
398 /*
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
406 */
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
93314b5b
CW		 408 if (tmp_crtc->enabled &&
409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
410 tmp_crtc->fb) {
85208be0
ED		 411 if (crtc) {
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
414 goto out_disable;
415 }
416 crtc = tmp_crtc;
417 }
418 }
419
420 if (!crtc || crtc->fb == NULL) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
423 goto out_disable;
424 }
425
426 intel_crtc = to_intel_crtc(crtc);
427 fb = crtc->fb;
428 intel_fb = to_intel_framebuffer(fb);
429 obj = intel_fb->obj;
430
431 enable_fbc = i915_enable_fbc;
432 if (enable_fbc < 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
434 enable_fbc = 1;
435 if (INTEL_INFO(dev)->gen <= 6)
436 enable_fbc = 0;
437 }
438 if (!enable_fbc) {
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
441 goto out_disable;
442 }
443 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
444 DRM_DEBUG_KMS("framebuffer too large, disabling "
445 "compression\n");
446 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
447 goto out_disable;
448 }
449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
451 DRM_DEBUG_KMS("mode incompatible with compression, "
452 "disabling\n");
453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
454 goto out_disable;
455 }
456 if ((crtc->mode.hdisplay > 2048) ||
457 (crtc->mode.vdisplay > 1536)) {
458 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
460 goto out_disable;
461 }
462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
463 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
464 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
465 goto out_disable;
466 }
467
468 /* The use of a CPU fence is mandatory in order to detect writes
469 * by the CPU to the scanout and trigger updates to the FBC.
470 */
471 if (obj->tiling_mode != I915_TILING_X ||
472 obj->fence_reg == I915_FENCE_REG_NONE) {
473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
474 dev_priv->no_fbc_reason = FBC_NOT_TILED;
475 goto out_disable;
476 }
477
478 /* If the kernel debugger is active, always disable compression */
479 if (in_dbg_master())
480 goto out_disable;
481
482 /* If the scanout has not changed, don't modify the FBC settings.
483 * Note that we make the fundamental assumption that the fb->obj
484 * cannot be unpinned (and have its GTT offset and fence revoked)
485 * without first being decoupled from the scanout and FBC disabled.
486 */
487 if (dev_priv->cfb_plane == intel_crtc->plane &&
488 dev_priv->cfb_fb == fb->base.id &&
489 dev_priv->cfb_y == crtc->y)
490 return;
491
492 if (intel_fbc_enabled(dev)) {
493 /* We update FBC along two paths, after changing fb/crtc
494 * configuration (modeswitching) and after page-flipping
495 * finishes. For the latter, we know that not only did
496 * we disable the FBC at the start of the page-flip
497 * sequence, but also more than one vblank has passed.
498 *
499 * For the former case of modeswitching, it is possible
500 * to switch between two FBC valid configurations
501 * instantaneously so we do need to disable the FBC
502 * before we can modify its control registers. We also
503 * have to wait for the next vblank for that to take
504 * effect. However, since we delay enabling FBC we can
505 * assume that a vblank has passed since disabling and
506 * that we can safely alter the registers in the deferred
507 * callback.
508 *
509 * In the scenario that we go from a valid to invalid
510 * and then back to valid FBC configuration we have
511 * no strict enforcement that a vblank occurred since
512 * disabling the FBC. However, along all current pipe
513 * disabling paths we do need to wait for a vblank at
514 * some point. And we wait before enabling FBC anyway.
515 */
516 DRM_DEBUG_KMS("disabling active FBC for update\n");
517 intel_disable_fbc(dev);
518 }
519
520 intel_enable_fbc(crtc, 500);
521 return;
522
523out_disable:
524 /* Multiple disables should be harmless */
525 if (intel_fbc_enabled(dev)) {
526 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
527 intel_disable_fbc(dev);
528 }
529}
530
c921aba8
DV		 531static void i915_pineview_get_mem_freq(struct drm_device *dev)
532{
533 drm_i915_private_t *dev_priv = dev->dev_private;
534 u32 tmp;
535
536 tmp = I915_READ(CLKCFG);
537
538 switch (tmp & CLKCFG_FSB_MASK) {
539 case CLKCFG_FSB_533:
540 dev_priv->fsb_freq = 533; /* 133*4 */
541 break;
542 case CLKCFG_FSB_800:
543 dev_priv->fsb_freq = 800; /* 200*4 */
544 break;
545 case CLKCFG_FSB_667:
546 dev_priv->fsb_freq = 667; /* 167*4 */
547 break;
548 case CLKCFG_FSB_400:
549 dev_priv->fsb_freq = 400; /* 100*4 */
550 break;
551 }
552
553 switch (tmp & CLKCFG_MEM_MASK) {
554 case CLKCFG_MEM_533:
555 dev_priv->mem_freq = 533;
556 break;
557 case CLKCFG_MEM_667:
558 dev_priv->mem_freq = 667;
559 break;
560 case CLKCFG_MEM_800:
561 dev_priv->mem_freq = 800;
562 break;
563 }
564
565 /* detect pineview DDR3 setting */
566 tmp = I915_READ(CSHRDDR3CTL);
567 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
568}
569
570static void i915_ironlake_get_mem_freq(struct drm_device *dev)
571{
572 drm_i915_private_t *dev_priv = dev->dev_private;
573 u16 ddrpll, csipll;
574
575 ddrpll = I915_READ16(DDRMPLL1);
576 csipll = I915_READ16(CSIPLL0);
577
578 switch (ddrpll & 0xff) {
579 case 0xc:
580 dev_priv->mem_freq = 800;
581 break;
582 case 0x10:
583 dev_priv->mem_freq = 1066;
584 break;
585 case 0x14:
586 dev_priv->mem_freq = 1333;
587 break;
588 case 0x18:
589 dev_priv->mem_freq = 1600;
590 break;
591 default:
592 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
593 ddrpll & 0xff);
594 dev_priv->mem_freq = 0;
595 break;
596 }
597
20e4d407 598 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 599
600 switch (csipll & 0x3ff) {
601 case 0x00c:
602 dev_priv->fsb_freq = 3200;
603 break;
604 case 0x00e:
605 dev_priv->fsb_freq = 3733;
606 break;
607 case 0x010:
608 dev_priv->fsb_freq = 4266;
609 break;
610 case 0x012:
611 dev_priv->fsb_freq = 4800;
612 break;
613 case 0x014:
614 dev_priv->fsb_freq = 5333;
615 break;
616 case 0x016:
617 dev_priv->fsb_freq = 5866;
618 break;
619 case 0x018:
620 dev_priv->fsb_freq = 6400;
621 break;
622 default:
623 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
624 csipll & 0x3ff);
625 dev_priv->fsb_freq = 0;
626 break;
627 }
628
629 if (dev_priv->fsb_freq == 3200) {
20e4d407 630 dev_priv->ips.c_m = 0;
c921aba8 631 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 632 dev_priv->ips.c_m = 1;
c921aba8 633 } else {
20e4d407 634 dev_priv->ips.c_m = 2;
c921aba8
DV		 635 }
636}
637
b445e3b0
ED		 638static const struct cxsr_latency cxsr_latency_table[] = {
639 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
640 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
641 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
642 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
643 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
644
645 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
646 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
647 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
648 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
649 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
650
651 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
652 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
653 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
654 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
655 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
656
657 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
658 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
659 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
660 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
661 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
662
663 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
664 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
665 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
666 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
667 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
668
669 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
670 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
671 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
672 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
673 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
674};
675
63c62275 676static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 677 int is_ddr3,
678 int fsb,
679 int mem)
680{
681 const struct cxsr_latency *latency;
682 int i;
683
684 if (fsb == 0 || mem == 0)
685 return NULL;
686
687 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
688 latency = &cxsr_latency_table[i];
689 if (is_desktop == latency->is_desktop &&
690 is_ddr3 == latency->is_ddr3 &&
691 fsb == latency->fsb_freq && mem == latency->mem_freq)
692 return latency;
693 }
694
695 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
696
697 return NULL;
698}
699
1fa61106 700static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 701{
702 struct drm_i915_private *dev_priv = dev->dev_private;
703
704 /* deactivate cxsr */
705 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
706}
707
708/*
709 * Latency for FIFO fetches is dependent on several factors:
710 * - memory configuration (speed, channels)
711 * - chipset
712 * - current MCH state
713 * It can be fairly high in some situations, so here we assume a fairly
714 * pessimal value. It's a tradeoff between extra memory fetches (if we
715 * set this value too high, the FIFO will fetch frequently to stay full)
716 * and power consumption (set it too low to save power and we might see
717 * FIFO underruns and display "flicker").
718 *
719 * A value of 5us seems to be a good balance; safe for very low end
720 * platforms but not overly aggressive on lower latency configs.
721 */
722static const int latency_ns = 5000;
723
1fa61106 724static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 725{
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t dsparb = I915_READ(DSPARB);
728 int size;
729
730 size = dsparb & 0x7f;
731 if (plane)
732 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
733
734 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
735 plane ? "B" : "A", size);
736
737 return size;
738}
739
1fa61106 740static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 741{
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 uint32_t dsparb = I915_READ(DSPARB);
744 int size;
745
746 size = dsparb & 0x1ff;
747 if (plane)
748 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
749 size >>= 1; /* Convert to cachelines */
750
751 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
752 plane ? "B" : "A", size);
753
754 return size;
755}
756
1fa61106 757static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 uint32_t dsparb = I915_READ(DSPARB);
761 int size;
762
763 size = dsparb & 0x7f;
764 size >>= 2; /* Convert to cachelines */
765
766 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
767 plane ? "B" : "A",
768 size);
769
770 return size;
771}
772
1fa61106 773static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 774{
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 uint32_t dsparb = I915_READ(DSPARB);
777 int size;
778
779 size = dsparb & 0x7f;
780 size >>= 1; /* Convert to cachelines */
781
782 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
783 plane ? "B" : "A", size);
784
785 return size;
786}
787
788/* Pineview has different values for various configs */
789static const struct intel_watermark_params pineview_display_wm = {
790 PINEVIEW_DISPLAY_FIFO,
791 PINEVIEW_MAX_WM,
792 PINEVIEW_DFT_WM,
793 PINEVIEW_GUARD_WM,
794 PINEVIEW_FIFO_LINE_SIZE
795};
796static const struct intel_watermark_params pineview_display_hplloff_wm = {
797 PINEVIEW_DISPLAY_FIFO,
798 PINEVIEW_MAX_WM,
799 PINEVIEW_DFT_HPLLOFF_WM,
800 PINEVIEW_GUARD_WM,
801 PINEVIEW_FIFO_LINE_SIZE
802};
803static const struct intel_watermark_params pineview_cursor_wm = {
804 PINEVIEW_CURSOR_FIFO,
805 PINEVIEW_CURSOR_MAX_WM,
806 PINEVIEW_CURSOR_DFT_WM,
807 PINEVIEW_CURSOR_GUARD_WM,
808 PINEVIEW_FIFO_LINE_SIZE,
809};
810static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
811 PINEVIEW_CURSOR_FIFO,
812 PINEVIEW_CURSOR_MAX_WM,
813 PINEVIEW_CURSOR_DFT_WM,
814 PINEVIEW_CURSOR_GUARD_WM,
815 PINEVIEW_FIFO_LINE_SIZE
816};
817static const struct intel_watermark_params g4x_wm_info = {
818 G4X_FIFO_SIZE,
819 G4X_MAX_WM,
820 G4X_MAX_WM,
821 2,
822 G4X_FIFO_LINE_SIZE,
823};
824static const struct intel_watermark_params g4x_cursor_wm_info = {
825 I965_CURSOR_FIFO,
826 I965_CURSOR_MAX_WM,
827 I965_CURSOR_DFT_WM,
828 2,
829 G4X_FIFO_LINE_SIZE,
830};
831static const struct intel_watermark_params valleyview_wm_info = {
832 VALLEYVIEW_FIFO_SIZE,
833 VALLEYVIEW_MAX_WM,
834 VALLEYVIEW_MAX_WM,
835 2,
836 G4X_FIFO_LINE_SIZE,
837};
838static const struct intel_watermark_params valleyview_cursor_wm_info = {
839 I965_CURSOR_FIFO,
840 VALLEYVIEW_CURSOR_MAX_WM,
841 I965_CURSOR_DFT_WM,
842 2,
843 G4X_FIFO_LINE_SIZE,
844};
845static const struct intel_watermark_params i965_cursor_wm_info = {
846 I965_CURSOR_FIFO,
847 I965_CURSOR_MAX_WM,
848 I965_CURSOR_DFT_WM,
849 2,
850 I915_FIFO_LINE_SIZE,
851};
852static const struct intel_watermark_params i945_wm_info = {
853 I945_FIFO_SIZE,
854 I915_MAX_WM,
855 1,
856 2,
857 I915_FIFO_LINE_SIZE
858};
859static const struct intel_watermark_params i915_wm_info = {
860 I915_FIFO_SIZE,
861 I915_MAX_WM,
862 1,
863 2,
864 I915_FIFO_LINE_SIZE
865};
866static const struct intel_watermark_params i855_wm_info = {
867 I855GM_FIFO_SIZE,
868 I915_MAX_WM,
869 1,
870 2,
871 I830_FIFO_LINE_SIZE
872};
873static const struct intel_watermark_params i830_wm_info = {
874 I830_FIFO_SIZE,
875 I915_MAX_WM,
876 1,
877 2,
878 I830_FIFO_LINE_SIZE
879};
880
881static const struct intel_watermark_params ironlake_display_wm_info = {
882 ILK_DISPLAY_FIFO,
883 ILK_DISPLAY_MAXWM,
884 ILK_DISPLAY_DFTWM,
885 2,
886 ILK_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params ironlake_cursor_wm_info = {
889 ILK_CURSOR_FIFO,
890 ILK_CURSOR_MAXWM,
891 ILK_CURSOR_DFTWM,
892 2,
893 ILK_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params ironlake_display_srwm_info = {
896 ILK_DISPLAY_SR_FIFO,
897 ILK_DISPLAY_MAX_SRWM,
898 ILK_DISPLAY_DFT_SRWM,
899 2,
900 ILK_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params ironlake_cursor_srwm_info = {
903 ILK_CURSOR_SR_FIFO,
904 ILK_CURSOR_MAX_SRWM,
905 ILK_CURSOR_DFT_SRWM,
906 2,
907 ILK_FIFO_LINE_SIZE
908};
909
910static const struct intel_watermark_params sandybridge_display_wm_info = {
911 SNB_DISPLAY_FIFO,
912 SNB_DISPLAY_MAXWM,
913 SNB_DISPLAY_DFTWM,
914 2,
915 SNB_FIFO_LINE_SIZE
916};
917static const struct intel_watermark_params sandybridge_cursor_wm_info = {
918 SNB_CURSOR_FIFO,
919 SNB_CURSOR_MAXWM,
920 SNB_CURSOR_DFTWM,
921 2,
922 SNB_FIFO_LINE_SIZE
923};
924static const struct intel_watermark_params sandybridge_display_srwm_info = {
925 SNB_DISPLAY_SR_FIFO,
926 SNB_DISPLAY_MAX_SRWM,
927 SNB_DISPLAY_DFT_SRWM,
928 2,
929 SNB_FIFO_LINE_SIZE
930};
931static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
932 SNB_CURSOR_SR_FIFO,
933 SNB_CURSOR_MAX_SRWM,
934 SNB_CURSOR_DFT_SRWM,
935 2,
936 SNB_FIFO_LINE_SIZE
937};
938
939
940/**
941 * intel_calculate_wm - calculate watermark level
942 * @clock_in_khz: pixel clock
943 * @wm: chip FIFO params
944 * @pixel_size: display pixel size
945 * @latency_ns: memory latency for the platform
946 *
947 * Calculate the watermark level (the level at which the display plane will
948 * start fetching from memory again). Each chip has a different display
949 * FIFO size and allocation, so the caller needs to figure that out and pass
950 * in the correct intel_watermark_params structure.
951 *
952 * As the pixel clock runs, the FIFO will be drained at a rate that depends
953 * on the pixel size. When it reaches the watermark level, it'll start
954 * fetching FIFO line sized based chunks from memory until the FIFO fills
955 * past the watermark point. If the FIFO drains completely, a FIFO underrun
956 * will occur, and a display engine hang could result.
957 */
958static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
959 const struct intel_watermark_params *wm,
960 int fifo_size,
961 int pixel_size,
962 unsigned long latency_ns)
963{
964 long entries_required, wm_size;
965
966 /*
967 * Note: we need to make sure we don't overflow for various clock &
968 * latency values.
969 * clocks go from a few thousand to several hundred thousand.
970 * latency is usually a few thousand
971 */
972 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
973 1000;
974 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
975
976 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
977
978 wm_size = fifo_size - (entries_required + wm->guard_size);
979
980 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
981
982 /* Don't promote wm_size to unsigned... */
983 if (wm_size > (long)wm->max_wm)
984 wm_size = wm->max_wm;
985 if (wm_size <= 0)
986 wm_size = wm->default_wm;
987 return wm_size;
988}
989
990static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
991{
992 struct drm_crtc *crtc, *enabled = NULL;
993
994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
995 if (crtc->enabled && crtc->fb) {
996 if (enabled)
997 return NULL;
998 enabled = crtc;
999 }
1000 }
1001
1002 return enabled;
1003}
1004
1fa61106 1005static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct drm_crtc *crtc;
1009 const struct cxsr_latency *latency;
1010 u32 reg;
1011 unsigned long wm;
1012
1013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014 dev_priv->fsb_freq, dev_priv->mem_freq);
1015 if (!latency) {
1016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017 pineview_disable_cxsr(dev);
1018 return;
1019 }
1020
1021 crtc = single_enabled_crtc(dev);
1022 if (crtc) {
1023 int clock = crtc->mode.clock;
1024 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026 /* Display SR */
1027 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028 pineview_display_wm.fifo_size,
1029 pixel_size, latency->display_sr);
1030 reg = I915_READ(DSPFW1);
1031 reg &= ~DSPFW_SR_MASK;
1032 reg |= wm << DSPFW_SR_SHIFT;
1033 I915_WRITE(DSPFW1, reg);
1034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036 /* cursor SR */
1037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038 pineview_display_wm.fifo_size,
1039 pixel_size, latency->cursor_sr);
1040 reg = I915_READ(DSPFW3);
1041 reg &= ~DSPFW_CURSOR_SR_MASK;
1042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043 I915_WRITE(DSPFW3, reg);
1044
1045 /* Display HPLL off SR */
1046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047 pineview_display_hplloff_wm.fifo_size,
1048 pixel_size, latency->display_hpll_disable);
1049 reg = I915_READ(DSPFW3);
1050 reg &= ~DSPFW_HPLL_SR_MASK;
1051 reg |= wm & DSPFW_HPLL_SR_MASK;
1052 I915_WRITE(DSPFW3, reg);
1053
1054 /* cursor HPLL off SR */
1055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056 pineview_display_hplloff_wm.fifo_size,
1057 pixel_size, latency->cursor_hpll_disable);
1058 reg = I915_READ(DSPFW3);
1059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061 I915_WRITE(DSPFW3, reg);
1062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064 /* activate cxsr */
1065 I915_WRITE(DSPFW3,
1066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068 } else {
1069 pineview_disable_cxsr(dev);
1070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071 }
1072}
1073
1074static bool g4x_compute_wm0(struct drm_device *dev,
1075 int plane,
1076 const struct intel_watermark_params *display,
1077 int display_latency_ns,
1078 const struct intel_watermark_params *cursor,
1079 int cursor_latency_ns,
1080 int *plane_wm,
1081 int *cursor_wm)
1082{
1083 struct drm_crtc *crtc;
1084 int htotal, hdisplay, clock, pixel_size;
1085 int line_time_us, line_count;
1086 int entries, tlb_miss;
1087
1088 crtc = intel_get_crtc_for_plane(dev, plane);
1089 if (crtc->fb == NULL || !crtc->enabled) {
1090 *cursor_wm = cursor->guard_size;
1091 *plane_wm = display->guard_size;
1092 return false;
1093 }
1094
1095 htotal = crtc->mode.htotal;
1096 hdisplay = crtc->mode.hdisplay;
1097 clock = crtc->mode.clock;
1098 pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100 /* Use the small buffer method to calculate plane watermark */
1101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103 if (tlb_miss > 0)
1104 entries += tlb_miss;
1105 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106 *plane_wm = entries + display->guard_size;
1107 if (*plane_wm > (int)display->max_wm)
1108 *plane_wm = display->max_wm;
1109
1110 /* Use the large buffer method to calculate cursor watermark */
1111 line_time_us = ((htotal * 1000) / clock);
1112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113 entries = line_count * 64 * pixel_size;
1114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115 if (tlb_miss > 0)
1116 entries += tlb_miss;
1117 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118 *cursor_wm = entries + cursor->guard_size;
1119 if (*cursor_wm > (int)cursor->max_wm)
1120 *cursor_wm = (int)cursor->max_wm;
1121
1122 return true;
1123}
1124
1125/*
1126 * Check the wm result.
1127 *
1128 * If any calculated watermark values is larger than the maximum value that
1129 * can be programmed into the associated watermark register, that watermark
1130 * must be disabled.
1131 */
1132static bool g4x_check_srwm(struct drm_device *dev,
1133 int display_wm, int cursor_wm,
1134 const struct intel_watermark_params *display,
1135 const struct intel_watermark_params *cursor)
1136{
1137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138 display_wm, cursor_wm);
1139
1140 if (display_wm > display->max_wm) {
1141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142 display_wm, display->max_wm);
1143 return false;
1144 }
1145
1146 if (cursor_wm > cursor->max_wm) {
1147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148 cursor_wm, cursor->max_wm);
1149 return false;
1150 }
1151
1152 if (!(display_wm || cursor_wm)) {
1153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154 return false;
1155 }
1156
1157 return true;
1158}
1159
1160static bool g4x_compute_srwm(struct drm_device *dev,
1161 int plane,
1162 int latency_ns,
1163 const struct intel_watermark_params *display,
1164 const struct intel_watermark_params *cursor,
1165 int *display_wm, int *cursor_wm)
1166{
1167 struct drm_crtc *crtc;
1168 int hdisplay, htotal, pixel_size, clock;
1169 unsigned long line_time_us;
1170 int line_count, line_size;
1171 int small, large;
1172 int entries;
1173
1174 if (!latency_ns) {
1175 *display_wm = *cursor_wm = 0;
1176 return false;
1177 }
1178
1179 crtc = intel_get_crtc_for_plane(dev, plane);
1180 hdisplay = crtc->mode.hdisplay;
1181 htotal = crtc->mode.htotal;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 line_time_us = (htotal * 1000) / clock;
1186 line_count = (latency_ns / line_time_us + 1000) / 1000;
1187 line_size = hdisplay * pixel_size;
1188
1189 /* Use the minimum of the small and large buffer method for primary */
1190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191 large = line_count * line_size;
1192
1193 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194 *display_wm = entries + display->guard_size;
1195
1196 /* calculate the self-refresh watermark for display cursor */
1197 entries = line_count * pixel_size * 64;
1198 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199 *cursor_wm = entries + cursor->guard_size;
1200
1201 return g4x_check_srwm(dev,
1202 *display_wm, *cursor_wm,
1203 display, cursor);
1204}
1205
1206static bool vlv_compute_drain_latency(struct drm_device *dev,
1207 int plane,
1208 int *plane_prec_mult,
1209 int *plane_dl,
1210 int *cursor_prec_mult,
1211 int *cursor_dl)
1212{
1213 struct drm_crtc *crtc;
1214 int clock, pixel_size;
1215 int entries;
1216
1217 crtc = intel_get_crtc_for_plane(dev, plane);
1218 if (crtc->fb == NULL || !crtc->enabled)
1219 return false;
1220
1221 clock = crtc->mode.clock; /* VESA DOT Clock */
1222 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1223
1224 entries = (clock / 1000) * pixel_size;
1225 *plane_prec_mult = (entries > 256) ?
1226 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228 pixel_size);
1229
1230 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1231 *cursor_prec_mult = (entries > 256) ?
1232 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235 return true;
1236}
1237
1238/*
1239 * Update drain latency registers of memory arbiter
1240 *
1241 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242 * to be programmed. Each plane has a drain latency multiplier and a drain
1243 * latency value.
1244 */
1245
1246static void vlv_update_drain_latency(struct drm_device *dev)
1247{
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252 either 16 or 32 */
1253
1254 /* For plane A, Cursor A */
1255 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256 &cursor_prec_mult, &cursora_dl)) {
1257 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262 I915_WRITE(VLV_DDL1, cursora_prec |
1263 (cursora_dl << DDL_CURSORA_SHIFT) |
1264 planea_prec | planea_dl);
1265 }
1266
1267 /* For plane B, Cursor B */
1268 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269 &cursor_prec_mult, &cursorb_dl)) {
1270 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275 I915_WRITE(VLV_DDL2, cursorb_prec |
1276 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277 planeb_prec | planeb_dl);
1278 }
1279}
1280
1281#define single_plane_enabled(mask) is_power_of_2(mask)
1282
1fa61106 1283static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1284{
1285 static const int sr_latency_ns = 12000;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288 int plane_sr, cursor_sr;
1289 unsigned int enabled = 0;
1290
1291 vlv_update_drain_latency(dev);
1292
1293 if (g4x_compute_wm0(dev, 0,
1294 &valleyview_wm_info, latency_ns,
1295 &valleyview_cursor_wm_info, latency_ns,
1296 &planea_wm, &cursora_wm))
1297 enabled |= 1;
1298
1299 if (g4x_compute_wm0(dev, 1,
1300 &valleyview_wm_info, latency_ns,
1301 &valleyview_cursor_wm_info, latency_ns,
1302 &planeb_wm, &cursorb_wm))
1303 enabled |= 2;
1304
1305 plane_sr = cursor_sr = 0;
1306 if (single_plane_enabled(enabled) &&
1307 g4x_compute_srwm(dev, ffs(enabled) - 1,
1308 sr_latency_ns,
1309 &valleyview_wm_info,
1310 &valleyview_cursor_wm_info,
1311 &plane_sr, &cursor_sr))
1312 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1313 else
1314 I915_WRITE(FW_BLC_SELF_VLV,
1315 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1316
1317 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1318 planea_wm, cursora_wm,
1319 planeb_wm, cursorb_wm,
1320 plane_sr, cursor_sr);
1321
1322 I915_WRITE(DSPFW1,
1323 (plane_sr << DSPFW_SR_SHIFT) |
1324 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1325 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1326 planea_wm);
1327 I915_WRITE(DSPFW2,
1328 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1329 (cursora_wm << DSPFW_CURSORA_SHIFT));
1330 I915_WRITE(DSPFW3,
1331 (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
1332}
1333
1fa61106 1334static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1335{
1336 static const int sr_latency_ns = 12000;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1339 int plane_sr, cursor_sr;
1340 unsigned int enabled = 0;
1341
1342 if (g4x_compute_wm0(dev, 0,
1343 &g4x_wm_info, latency_ns,
1344 &g4x_cursor_wm_info, latency_ns,
1345 &planea_wm, &cursora_wm))
1346 enabled |= 1;
1347
1348 if (g4x_compute_wm0(dev, 1,
1349 &g4x_wm_info, latency_ns,
1350 &g4x_cursor_wm_info, latency_ns,
1351 &planeb_wm, &cursorb_wm))
1352 enabled |= 2;
1353
1354 plane_sr = cursor_sr = 0;
1355 if (single_plane_enabled(enabled) &&
1356 g4x_compute_srwm(dev, ffs(enabled) - 1,
1357 sr_latency_ns,
1358 &g4x_wm_info,
1359 &g4x_cursor_wm_info,
1360 &plane_sr, &cursor_sr))
1361 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1362 else
1363 I915_WRITE(FW_BLC_SELF,
1364 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1365
1366 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1367 planea_wm, cursora_wm,
1368 planeb_wm, cursorb_wm,
1369 plane_sr, cursor_sr);
1370
1371 I915_WRITE(DSPFW1,
1372 (plane_sr << DSPFW_SR_SHIFT) |
1373 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1374 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1375 planea_wm);
1376 I915_WRITE(DSPFW2,
1377 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1378 (cursora_wm << DSPFW_CURSORA_SHIFT));
1379 /* HPLL off in SR has some issues on G4x... disable it */
1380 I915_WRITE(DSPFW3,
1381 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
1382 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1383}
1384
1fa61106 1385static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1386{
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 struct drm_crtc *crtc;
1389 int srwm = 1;
1390 int cursor_sr = 16;
1391
1392 /* Calc sr entries for one plane configs */
1393 crtc = single_enabled_crtc(dev);
1394 if (crtc) {
1395 /* self-refresh has much higher latency */
1396 static const int sr_latency_ns = 12000;
1397 int clock = crtc->mode.clock;
1398 int htotal = crtc->mode.htotal;
1399 int hdisplay = crtc->mode.hdisplay;
1400 int pixel_size = crtc->fb->bits_per_pixel / 8;
1401 unsigned long line_time_us;
1402 int entries;
1403
1404 line_time_us = ((htotal * 1000) / clock);
1405
1406 /* Use ns/us then divide to preserve precision */
1407 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1408 pixel_size * hdisplay;
1409 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1410 srwm = I965_FIFO_SIZE - entries;
1411 if (srwm < 0)
1412 srwm = 1;
1413 srwm &= 0x1ff;
1414 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1415 entries, srwm);
1416
1417 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1418 pixel_size * 64;
1419 entries = DIV_ROUND_UP(entries,
1420 i965_cursor_wm_info.cacheline_size);
1421 cursor_sr = i965_cursor_wm_info.fifo_size -
1422 (entries + i965_cursor_wm_info.guard_size);
1423
1424 if (cursor_sr > i965_cursor_wm_info.max_wm)
1425 cursor_sr = i965_cursor_wm_info.max_wm;
1426
1427 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1428 "cursor %d\n", srwm, cursor_sr);
1429
1430 if (IS_CRESTLINE(dev))
1431 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1432 } else {
1433 /* Turn off self refresh if both pipes are enabled */
1434 if (IS_CRESTLINE(dev))
1435 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1436 & ~FW_BLC_SELF_EN);
1437 }
1438
1439 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1440 srwm);
1441
1442 /* 965 has limitations... */
1443 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1444 (8 << 16) | (8 << 8) | (8 << 0));
1445 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1446 /* update cursor SR watermark */
1447 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1448}
1449
1fa61106 1450static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1451{
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 const struct intel_watermark_params *wm_info;
1454 uint32_t fwater_lo;
1455 uint32_t fwater_hi;
1456 int cwm, srwm = 1;
1457 int fifo_size;
1458 int planea_wm, planeb_wm;
1459 struct drm_crtc *crtc, *enabled = NULL;
1460
1461 if (IS_I945GM(dev))
1462 wm_info = &i945_wm_info;
1463 else if (!IS_GEN2(dev))
1464 wm_info = &i915_wm_info;
1465 else
1466 wm_info = &i855_wm_info;
1467
1468 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1469 crtc = intel_get_crtc_for_plane(dev, 0);
1470 if (crtc->enabled && crtc->fb) {
1471 planea_wm = intel_calculate_wm(crtc->mode.clock,
1472 wm_info, fifo_size,
1473 crtc->fb->bits_per_pixel / 8,
1474 latency_ns);
1475 enabled = crtc;
1476 } else
1477 planea_wm = fifo_size - wm_info->guard_size;
1478
1479 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1480 crtc = intel_get_crtc_for_plane(dev, 1);
1481 if (crtc->enabled && crtc->fb) {
1482 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1483 wm_info, fifo_size,
1484 crtc->fb->bits_per_pixel / 8,
1485 latency_ns);
1486 if (enabled == NULL)
1487 enabled = crtc;
1488 else
1489 enabled = NULL;
1490 } else
1491 planeb_wm = fifo_size - wm_info->guard_size;
1492
1493 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1494
1495 /*
1496 * Overlay gets an aggressive default since video jitter is bad.
1497 */
1498 cwm = 2;
1499
1500 /* Play safe and disable self-refresh before adjusting watermarks. */
1501 if (IS_I945G(dev) || IS_I945GM(dev))
1502 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1503 else if (IS_I915GM(dev))
1504 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1505
1506 /* Calc sr entries for one plane configs */
1507 if (HAS_FW_BLC(dev) && enabled) {
1508 /* self-refresh has much higher latency */
1509 static const int sr_latency_ns = 6000;
1510 int clock = enabled->mode.clock;
1511 int htotal = enabled->mode.htotal;
1512 int hdisplay = enabled->mode.hdisplay;
1513 int pixel_size = enabled->fb->bits_per_pixel / 8;
1514 unsigned long line_time_us;
1515 int entries;
1516
1517 line_time_us = (htotal * 1000) / clock;
1518
1519 /* Use ns/us then divide to preserve precision */
1520 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 pixel_size * hdisplay;
1522 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1523 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1524 srwm = wm_info->fifo_size - entries;
1525 if (srwm < 0)
1526 srwm = 1;
1527
1528 if (IS_I945G(dev) || IS_I945GM(dev))
1529 I915_WRITE(FW_BLC_SELF,
1530 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1531 else if (IS_I915GM(dev))
1532 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1533 }
1534
1535 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1536 planea_wm, planeb_wm, cwm, srwm);
1537
1538 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1539 fwater_hi = (cwm & 0x1f);
1540
1541 /* Set request length to 8 cachelines per fetch */
1542 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1543 fwater_hi = fwater_hi | (1 << 8);
1544
1545 I915_WRITE(FW_BLC, fwater_lo);
1546 I915_WRITE(FW_BLC2, fwater_hi);
1547
1548 if (HAS_FW_BLC(dev)) {
1549 if (enabled) {
1550 if (IS_I945G(dev) || IS_I945GM(dev))
1551 I915_WRITE(FW_BLC_SELF,
1552 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1553 else if (IS_I915GM(dev))
1554 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1555 DRM_DEBUG_KMS("memory self refresh enabled\n");
1556 } else
1557 DRM_DEBUG_KMS("memory self refresh disabled\n");
1558 }
1559}
1560
1fa61106 1561static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1562{
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct drm_crtc *crtc;
1565 uint32_t fwater_lo;
1566 int planea_wm;
1567
1568 crtc = single_enabled_crtc(dev);
1569 if (crtc == NULL)
1570 return;
1571
1572 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1573 dev_priv->display.get_fifo_size(dev, 0),
1574 crtc->fb->bits_per_pixel / 8,
1575 latency_ns);
1576 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1577 fwater_lo |= (3<<8) | planea_wm;
1578
1579 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1580
1581 I915_WRITE(FW_BLC, fwater_lo);
1582}
1583
1584#define ILK_LP0_PLANE_LATENCY 700
1585#define ILK_LP0_CURSOR_LATENCY 1300
1586
1587/*
1588 * Check the wm result.
1589 *
1590 * If any calculated watermark values is larger than the maximum value that
1591 * can be programmed into the associated watermark register, that watermark
1592 * must be disabled.
1593 */
1594static bool ironlake_check_srwm(struct drm_device *dev, int level,
1595 int fbc_wm, int display_wm, int cursor_wm,
1596 const struct intel_watermark_params *display,
1597 const struct intel_watermark_params *cursor)
1598{
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1602 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1603
1604 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1605 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1606 fbc_wm, SNB_FBC_MAX_SRWM, level);
1607
1608 /* fbc has it's own way to disable FBC WM */
1609 I915_WRITE(DISP_ARB_CTL,
1610 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1611 return false;
1612 }
1613
1614 if (display_wm > display->max_wm) {
1615 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1616 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1617 return false;
1618 }
1619
1620 if (cursor_wm > cursor->max_wm) {
1621 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1622 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1623 return false;
1624 }
1625
1626 if (!(fbc_wm || display_wm || cursor_wm)) {
1627 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1628 return false;
1629 }
1630
1631 return true;
1632}
1633
1634/*
1635 * Compute watermark values of WM[1-3],
1636 */
1637static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1638 int latency_ns,
1639 const struct intel_watermark_params *display,
1640 const struct intel_watermark_params *cursor,
1641 int *fbc_wm, int *display_wm, int *cursor_wm)
1642{
1643 struct drm_crtc *crtc;
1644 unsigned long line_time_us;
1645 int hdisplay, htotal, pixel_size, clock;
1646 int line_count, line_size;
1647 int small, large;
1648 int entries;
1649
1650 if (!latency_ns) {
1651 *fbc_wm = *display_wm = *cursor_wm = 0;
1652 return false;
1653 }
1654
1655 crtc = intel_get_crtc_for_plane(dev, plane);
1656 hdisplay = crtc->mode.hdisplay;
1657 htotal = crtc->mode.htotal;
1658 clock = crtc->mode.clock;
1659 pixel_size = crtc->fb->bits_per_pixel / 8;
1660
1661 line_time_us = (htotal * 1000) / clock;
1662 line_count = (latency_ns / line_time_us + 1000) / 1000;
1663 line_size = hdisplay * pixel_size;
1664
1665 /* Use the minimum of the small and large buffer method for primary */
1666 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1667 large = line_count * line_size;
1668
1669 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1670 *display_wm = entries + display->guard_size;
1671
1672 /*
1673 * Spec says:
1674 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1675 */
1676 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1677
1678 /* calculate the self-refresh watermark for display cursor */
1679 entries = line_count * pixel_size * 64;
1680 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1681 *cursor_wm = entries + cursor->guard_size;
1682
1683 return ironlake_check_srwm(dev, level,
1684 *fbc_wm, *display_wm, *cursor_wm,
1685 display, cursor);
1686}
1687
1fa61106 1688static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1689{
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int fbc_wm, plane_wm, cursor_wm;
1692 unsigned int enabled;
1693
1694 enabled = 0;
1695 if (g4x_compute_wm0(dev, 0,
1696 &ironlake_display_wm_info,
1697 ILK_LP0_PLANE_LATENCY,
1698 &ironlake_cursor_wm_info,
1699 ILK_LP0_CURSOR_LATENCY,
1700 &plane_wm, &cursor_wm)) {
1701 I915_WRITE(WM0_PIPEA_ILK,
1702 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1703 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1704 " plane %d, " "cursor: %d\n",
1705 plane_wm, cursor_wm);
1706 enabled |= 1;
1707 }
1708
1709 if (g4x_compute_wm0(dev, 1,
1710 &ironlake_display_wm_info,
1711 ILK_LP0_PLANE_LATENCY,
1712 &ironlake_cursor_wm_info,
1713 ILK_LP0_CURSOR_LATENCY,
1714 &plane_wm, &cursor_wm)) {
1715 I915_WRITE(WM0_PIPEB_ILK,
1716 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1717 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1718 " plane %d, cursor: %d\n",
1719 plane_wm, cursor_wm);
1720 enabled |= 2;
1721 }
1722
1723 /*
1724 * Calculate and update the self-refresh watermark only when one
1725 * display plane is used.
1726 */
1727 I915_WRITE(WM3_LP_ILK, 0);
1728 I915_WRITE(WM2_LP_ILK, 0);
1729 I915_WRITE(WM1_LP_ILK, 0);
1730
1731 if (!single_plane_enabled(enabled))
1732 return;
1733 enabled = ffs(enabled) - 1;
1734
1735 /* WM1 */
1736 if (!ironlake_compute_srwm(dev, 1, enabled,
1737 ILK_READ_WM1_LATENCY() * 500,
1738 &ironlake_display_srwm_info,
1739 &ironlake_cursor_srwm_info,
1740 &fbc_wm, &plane_wm, &cursor_wm))
1741 return;
1742
1743 I915_WRITE(WM1_LP_ILK,
1744 WM1_LP_SR_EN |
1745 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1746 (fbc_wm << WM1_LP_FBC_SHIFT) |
1747 (plane_wm << WM1_LP_SR_SHIFT) |
1748 cursor_wm);
1749
1750 /* WM2 */
1751 if (!ironlake_compute_srwm(dev, 2, enabled,
1752 ILK_READ_WM2_LATENCY() * 500,
1753 &ironlake_display_srwm_info,
1754 &ironlake_cursor_srwm_info,
1755 &fbc_wm, &plane_wm, &cursor_wm))
1756 return;
1757
1758 I915_WRITE(WM2_LP_ILK,
1759 WM2_LP_EN |
1760 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1761 (fbc_wm << WM1_LP_FBC_SHIFT) |
1762 (plane_wm << WM1_LP_SR_SHIFT) |
1763 cursor_wm);
1764
1765 /*
1766 * WM3 is unsupported on ILK, probably because we don't have latency
1767 * data for that power state
1768 */
1769}
1770
1fa61106 1771static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1772{
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1775 u32 val;
1776 int fbc_wm, plane_wm, cursor_wm;
1777 unsigned int enabled;
1778
1779 enabled = 0;
1780 if (g4x_compute_wm0(dev, 0,
1781 &sandybridge_display_wm_info, latency,
1782 &sandybridge_cursor_wm_info, latency,
1783 &plane_wm, &cursor_wm)) {
1784 val = I915_READ(WM0_PIPEA_ILK);
1785 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1786 I915_WRITE(WM0_PIPEA_ILK, val |
1787 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1788 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1789 " plane %d, " "cursor: %d\n",
1790 plane_wm, cursor_wm);
1791 enabled |= 1;
1792 }
1793
1794 if (g4x_compute_wm0(dev, 1,
1795 &sandybridge_display_wm_info, latency,
1796 &sandybridge_cursor_wm_info, latency,
1797 &plane_wm, &cursor_wm)) {
1798 val = I915_READ(WM0_PIPEB_ILK);
1799 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1800 I915_WRITE(WM0_PIPEB_ILK, val |
1801 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1802 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1803 " plane %d, cursor: %d\n",
1804 plane_wm, cursor_wm);
1805 enabled |= 2;
1806 }
1807
461bc9b5 1808 if ((dev_priv->num_pipe == 3) &&
b445e3b0
ED		 1809 g4x_compute_wm0(dev, 2,
1810 &sandybridge_display_wm_info, latency,
1811 &sandybridge_cursor_wm_info, latency,
1812 &plane_wm, &cursor_wm)) {
1813 val = I915_READ(WM0_PIPEC_IVB);
1814 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1815 I915_WRITE(WM0_PIPEC_IVB, val |
1816 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1817 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1818 " plane %d, cursor: %d\n",
1819 plane_wm, cursor_wm);
1820 enabled |= 3;
1821 }
1822
1823 /*
1824 * Calculate and update the self-refresh watermark only when one
1825 * display plane is used.
1826 *
1827 * SNB support 3 levels of watermark.
1828 *
1829 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1830 * and disabled in the descending order
1831 *
1832 */
1833 I915_WRITE(WM3_LP_ILK, 0);
1834 I915_WRITE(WM2_LP_ILK, 0);
1835 I915_WRITE(WM1_LP_ILK, 0);
1836
1837 if (!single_plane_enabled(enabled) ||
1838 dev_priv->sprite_scaling_enabled)
1839 return;
1840 enabled = ffs(enabled) - 1;
1841
1842 /* WM1 */
1843 if (!ironlake_compute_srwm(dev, 1, enabled,
1844 SNB_READ_WM1_LATENCY() * 500,
1845 &sandybridge_display_srwm_info,
1846 &sandybridge_cursor_srwm_info,
1847 &fbc_wm, &plane_wm, &cursor_wm))
1848 return;
1849
1850 I915_WRITE(WM1_LP_ILK,
1851 WM1_LP_SR_EN |
1852 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1853 (fbc_wm << WM1_LP_FBC_SHIFT) |
1854 (plane_wm << WM1_LP_SR_SHIFT) |
1855 cursor_wm);
1856
1857 /* WM2 */
1858 if (!ironlake_compute_srwm(dev, 2, enabled,
1859 SNB_READ_WM2_LATENCY() * 500,
1860 &sandybridge_display_srwm_info,
1861 &sandybridge_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1863 return;
1864
1865 I915_WRITE(WM2_LP_ILK,
1866 WM2_LP_EN |
1867 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1870 cursor_wm);
1871
1872 /* WM3 */
1873 if (!ironlake_compute_srwm(dev, 3, enabled,
1874 SNB_READ_WM3_LATENCY() * 500,
1875 &sandybridge_display_srwm_info,
1876 &sandybridge_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1878 return;
1879
1880 I915_WRITE(WM3_LP_ILK,
1881 WM3_LP_EN |
1882 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1885 cursor_wm);
1886}
1887
1f8eeabf
ED		 1888static void
1889haswell_update_linetime_wm(struct drm_device *dev, int pipe,
1890 struct drm_display_mode *mode)
1891{
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 u32 temp;
1894
1895 temp = I915_READ(PIPE_WM_LINETIME(pipe));
1896 temp &= ~PIPE_WM_LINETIME_MASK;
1897
1898 /* The WM are computed with base on how long it takes to fill a single
1899 * row at the given clock rate, multiplied by 8.
1900 * */
1901 temp |= PIPE_WM_LINETIME_TIME(
1902 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
1903
1904 /* IPS watermarks are only used by pipe A, and are ignored by
1905 * pipes B and C. They are calculated similarly to the common
1906 * linetime values, except that we are using CD clock frequency
1907 * in MHz instead of pixel rate for the division.
1908 *
1909 * This is a placeholder for the IPS watermark calculation code.
1910 */
1911
1912 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
1913}
1914
b445e3b0
ED		 1915static bool
1916sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1917 uint32_t sprite_width, int pixel_size,
1918 const struct intel_watermark_params *display,
1919 int display_latency_ns, int *sprite_wm)
1920{
1921 struct drm_crtc *crtc;
1922 int clock;
1923 int entries, tlb_miss;
1924
1925 crtc = intel_get_crtc_for_plane(dev, plane);
1926 if (crtc->fb == NULL || !crtc->enabled) {
1927 *sprite_wm = display->guard_size;
1928 return false;
1929 }
1930
1931 clock = crtc->mode.clock;
1932
1933 /* Use the small buffer method to calculate the sprite watermark */
1934 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1935 tlb_miss = display->fifo_size*display->cacheline_size -
1936 sprite_width * 8;
1937 if (tlb_miss > 0)
1938 entries += tlb_miss;
1939 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1940 *sprite_wm = entries + display->guard_size;
1941 if (*sprite_wm > (int)display->max_wm)
1942 *sprite_wm = display->max_wm;
1943
1944 return true;
1945}
1946
1947static bool
1948sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1949 uint32_t sprite_width, int pixel_size,
1950 const struct intel_watermark_params *display,
1951 int latency_ns, int *sprite_wm)
1952{
1953 struct drm_crtc *crtc;
1954 unsigned long line_time_us;
1955 int clock;
1956 int line_count, line_size;
1957 int small, large;
1958 int entries;
1959
1960 if (!latency_ns) {
1961 *sprite_wm = 0;
1962 return false;
1963 }
1964
1965 crtc = intel_get_crtc_for_plane(dev, plane);
1966 clock = crtc->mode.clock;
1967 if (!clock) {
1968 *sprite_wm = 0;
1969 return false;
1970 }
1971
1972 line_time_us = (sprite_width * 1000) / clock;
1973 if (!line_time_us) {
1974 *sprite_wm = 0;
1975 return false;
1976 }
1977
1978 line_count = (latency_ns / line_time_us + 1000) / 1000;
1979 line_size = sprite_width * pixel_size;
1980
1981 /* Use the minimum of the small and large buffer method for primary */
1982 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1983 large = line_count * line_size;
1984
1985 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1986 *sprite_wm = entries + display->guard_size;
1987
1988 return *sprite_wm > 0x3ff ? false : true;
1989}
1990
1fa61106 1991static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 1992 uint32_t sprite_width, int pixel_size)
1993{
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1996 u32 val;
1997 int sprite_wm, reg;
1998 int ret;
1999
2000 switch (pipe) {
2001 case 0:
2002 reg = WM0_PIPEA_ILK;
2003 break;
2004 case 1:
2005 reg = WM0_PIPEB_ILK;
2006 break;
2007 case 2:
2008 reg = WM0_PIPEC_IVB;
2009 break;
2010 default:
2011 return; /* bad pipe */
2012 }
2013
2014 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2015 &sandybridge_display_wm_info,
2016 latency, &sprite_wm);
2017 if (!ret) {
2018 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2019 pipe);
2020 return;
2021 }
2022
2023 val = I915_READ(reg);
2024 val &= ~WM0_PIPE_SPRITE_MASK;
2025 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2026 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2027
2028
2029 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2030 pixel_size,
2031 &sandybridge_display_srwm_info,
2032 SNB_READ_WM1_LATENCY() * 500,
2033 &sprite_wm);
2034 if (!ret) {
2035 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2036 pipe);
2037 return;
2038 }
2039 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2040
2041 /* Only IVB has two more LP watermarks for sprite */
2042 if (!IS_IVYBRIDGE(dev))
2043 return;
2044
2045 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2046 pixel_size,
2047 &sandybridge_display_srwm_info,
2048 SNB_READ_WM2_LATENCY() * 500,
2049 &sprite_wm);
2050 if (!ret) {
2051 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2052 pipe);
2053 return;
2054 }
2055 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2056
2057 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2058 pixel_size,
2059 &sandybridge_display_srwm_info,
2060 SNB_READ_WM3_LATENCY() * 500,
2061 &sprite_wm);
2062 if (!ret) {
2063 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2064 pipe);
2065 return;
2066 }
2067 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2068}
2069
2070/**
2071 * intel_update_watermarks - update FIFO watermark values based on current modes
2072 *
2073 * Calculate watermark values for the various WM regs based on current mode
2074 * and plane configuration.
2075 *
2076 * There are several cases to deal with here:
2077 * - normal (i.e. non-self-refresh)
2078 * - self-refresh (SR) mode
2079 * - lines are large relative to FIFO size (buffer can hold up to 2)
2080 * - lines are small relative to FIFO size (buffer can hold more than 2
2081 * lines), so need to account for TLB latency
2082 *
2083 * The normal calculation is:
2084 * watermark = dotclock * bytes per pixel * latency
2085 * where latency is platform & configuration dependent (we assume pessimal
2086 * values here).
2087 *
2088 * The SR calculation is:
2089 * watermark = (trunc(latency/line time)+1) * surface width *
2090 * bytes per pixel
2091 * where
2092 * line time = htotal / dotclock
2093 * surface width = hdisplay for normal plane and 64 for cursor
2094 * and latency is assumed to be high, as above.
2095 *
2096 * The final value programmed to the register should always be rounded up,
2097 * and include an extra 2 entries to account for clock crossings.
2098 *
2099 * We don't use the sprite, so we can ignore that. And on Crestline we have
2100 * to set the non-SR watermarks to 8.
2101 */
2102void intel_update_watermarks(struct drm_device *dev)
2103{
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105
2106 if (dev_priv->display.update_wm)
2107 dev_priv->display.update_wm(dev);
2108}
2109
1f8eeabf
ED		 2110void intel_update_linetime_watermarks(struct drm_device *dev,
2111 int pipe, struct drm_display_mode *mode)
2112{
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114
2115 if (dev_priv->display.update_linetime_wm)
2116 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2117}
2118
b445e3b0
ED		 2119void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2120 uint32_t sprite_width, int pixel_size)
2121{
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123
2124 if (dev_priv->display.update_sprite_wm)
2125 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2126 pixel_size);
2127}
2128
2b4e57bd
ED		 2129static struct drm_i915_gem_object *
2130intel_alloc_context_page(struct drm_device *dev)
2131{
2132 struct drm_i915_gem_object *ctx;
2133 int ret;
2134
2135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137 ctx = i915_gem_alloc_object(dev, 4096);
2138 if (!ctx) {
2139 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2140 return NULL;
2141 }
2142
86a1ee26 2143 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2144 if (ret) {
2145 DRM_ERROR("failed to pin power context: %d\n", ret);
2146 goto err_unref;
2147 }
2148
2149 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2150 if (ret) {
2151 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2152 goto err_unpin;
2153 }
2154
2155 return ctx;
2156
2157err_unpin:
2158 i915_gem_object_unpin(ctx);
2159err_unref:
2160 drm_gem_object_unreference(&ctx->base);
2161 mutex_unlock(&dev->struct_mutex);
2162 return NULL;
2163}
2164
9270388e
DV		 2165/**
2166 * Lock protecting IPS related data structures
9270388e
DV		 2167 */
2168DEFINE_SPINLOCK(mchdev_lock);
2169
2170/* Global for IPS driver to get at the current i915 device. Protected by
2171 * mchdev_lock. */
2172static struct drm_i915_private *i915_mch_dev;
2173
2b4e57bd
ED		 2174bool ironlake_set_drps(struct drm_device *dev, u8 val)
2175{
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 u16 rgvswctl;
2178
9270388e
DV		 2179 assert_spin_locked(&mchdev_lock);
2180
2b4e57bd
ED		 2181 rgvswctl = I915_READ16(MEMSWCTL);
2182 if (rgvswctl & MEMCTL_CMD_STS) {
2183 DRM_DEBUG("gpu busy, RCS change rejected\n");
2184 return false; /* still busy with another command */
2185 }
2186
2187 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2188 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2189 I915_WRITE16(MEMSWCTL, rgvswctl);
2190 POSTING_READ16(MEMSWCTL);
2191
2192 rgvswctl |= MEMCTL_CMD_STS;
2193 I915_WRITE16(MEMSWCTL, rgvswctl);
2194
2195 return true;
2196}
2197
8090c6b9 2198static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2199{
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 u32 rgvmodectl = I915_READ(MEMMODECTL);
2202 u8 fmax, fmin, fstart, vstart;
2203
9270388e
DV		 2204 spin_lock_irq(&mchdev_lock);
2205
2b4e57bd
ED		 2206 /* Enable temp reporting */
2207 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2208 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2209
2210 /* 100ms RC evaluation intervals */
2211 I915_WRITE(RCUPEI, 100000);
2212 I915_WRITE(RCDNEI, 100000);
2213
2214 /* Set max/min thresholds to 90ms and 80ms respectively */
2215 I915_WRITE(RCBMAXAVG, 90000);
2216 I915_WRITE(RCBMINAVG, 80000);
2217
2218 I915_WRITE(MEMIHYST, 1);
2219
2220 /* Set up min, max, and cur for interrupt handling */
2221 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2222 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2223 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2224 MEMMODE_FSTART_SHIFT;
2225
2226 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2227 PXVFREQ_PX_SHIFT;
2228
20e4d407
DV		 2229 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2230 dev_priv->ips.fstart = fstart;
2b4e57bd 2231
20e4d407
DV		 2232 dev_priv->ips.max_delay = fstart;
2233 dev_priv->ips.min_delay = fmin;
2234 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2235
2236 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2237 fmax, fmin, fstart);
2238
2239 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2240
2241 /*
2242 * Interrupts will be enabled in ironlake_irq_postinstall
2243 */
2244
2245 I915_WRITE(VIDSTART, vstart);
2246 POSTING_READ(VIDSTART);
2247
2248 rgvmodectl |= MEMMODE_SWMODE_EN;
2249 I915_WRITE(MEMMODECTL, rgvmodectl);
2250
9270388e 2251 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2252 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2253 mdelay(1);
2b4e57bd
ED		 2254
2255 ironlake_set_drps(dev, fstart);
2256
20e4d407 2257 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2258 I915_READ(0x112e0);
20e4d407
DV		 2259 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2260 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2261 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2262
2263 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2264}
2265
8090c6b9 2266static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2267{
2268 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2269 u16 rgvswctl;
2270
2271 spin_lock_irq(&mchdev_lock);
2272
2273 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2274
2275 /* Ack interrupts, disable EFC interrupt */
2276 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2277 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2278 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2279 I915_WRITE(DEIIR, DE_PCU_EVENT);
2280 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2281
2282 /* Go back to the starting frequency */
20e4d407 2283 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2284 mdelay(1);
2b4e57bd
ED		 2285 rgvswctl |= MEMCTL_CMD_STS;
2286 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2287 mdelay(1);
2b4e57bd 2288
9270388e 2289 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2290}
2291
acbe9475
DV		 2292/* There's a funny hw issue where the hw returns all 0 when reading from
2293 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2294 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2295 * all limits and the gpu stuck at whatever frequency it is at atm).
2296 */
65bccb5c 2297static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2298{
7b9e0ae6 2299 u32 limits;
2b4e57bd 2300
7b9e0ae6 2301 limits = 0;
c6a828d3
DV		 2302
2303 if (*val >= dev_priv->rps.max_delay)
2304 *val = dev_priv->rps.max_delay;
2305 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2306
2307 /* Only set the down limit when we've reached the lowest level to avoid
2308 * getting more interrupts, otherwise leave this clear. This prevents a
2309 * race in the hw when coming out of rc6: There's a tiny window where
2310 * the hw runs at the minimal clock before selecting the desired
2311 * frequency, if the down threshold expires in that window we will not
2312 * receive a down interrupt. */
c6a828d3
DV		 2313 if (*val <= dev_priv->rps.min_delay) {
2314 *val = dev_priv->rps.min_delay;
2315 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2316 }
2317
2318 return limits;
2319}
2320
2321void gen6_set_rps(struct drm_device *dev, u8 val)
2322{
2323 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2324 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2325
004777cb 2326 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
79249636
BW		 2327 WARN_ON(val > dev_priv->rps.max_delay);
2328 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2329
c6a828d3 2330 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2331 return;
2332
2333 I915_WRITE(GEN6_RPNSWREQ,
2334 GEN6_FREQUENCY(val) |
2335 GEN6_OFFSET(0) |
2336 GEN6_AGGRESSIVE_TURBO);
2337
2338 /* Make sure we continue to get interrupts
2339 * until we hit the minimum or maximum frequencies.
2340 */
2341 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2342
d5570a72
BW		 2343 POSTING_READ(GEN6_RPNSWREQ);
2344
c6a828d3 2345 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2346
2347 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2348}
2349
8090c6b9 2350static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353
88509484 2354 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2355 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2356 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2357 I915_WRITE(GEN6_PMIER, 0);
2358 /* Complete PM interrupt masking here doesn't race with the rps work
2359 * item again unmasking PM interrupts because that is using a different
2360 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2361 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2362
c6a828d3
DV		 2363 spin_lock_irq(&dev_priv->rps.lock);
2364 dev_priv->rps.pm_iir = 0;
2365 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2366
2367 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2368}
2369
2370int intel_enable_rc6(const struct drm_device *dev)
2371{
456470eb 2372 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2373 if (i915_enable_rc6 >= 0)
2374 return i915_enable_rc6;
2375
6567d748
CW		 2376 /* Disable RC6 on Ironlake */
2377 if (INTEL_INFO(dev)->gen == 5)
2378 return 0;
2b4e57bd 2379
456470eb
DV		 2380 if (IS_HASWELL(dev)) {
2381 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2382 return INTEL_RC6_ENABLE;
456470eb 2383 }
2b4e57bd 2384
456470eb 2385 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2386 if (INTEL_INFO(dev)->gen == 6) {
2387 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2388 return INTEL_RC6_ENABLE;
2389 }
456470eb 2390
2b4e57bd
ED		 2391 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2392 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2393}
2394
79f5b2c7 2395static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2396{
79f5b2c7 2397 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2398 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2399 u32 rp_state_cap;
2400 u32 gt_perf_status;
2b4e57bd
ED		 2401 u32 pcu_mbox, rc6_mask = 0;
2402 u32 gtfifodbg;
2b4e57bd
ED		 2403 int rc6_mode;
2404 int i;
2405
79f5b2c7
DV		 2406 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2407
2b4e57bd
ED		 2408 /* Here begins a magic sequence of register writes to enable
2409 * auto-downclocking.
2410 *
2411 * Perhaps there might be some value in exposing these to
2412 * userspace...
2413 */
2414 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2415
2416 /* Clear the DBG now so we don't confuse earlier errors */
2417 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2418 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2419 I915_WRITE(GTFIFODBG, gtfifodbg);
2420 }
2421
2422 gen6_gt_force_wake_get(dev_priv);
2423
7b9e0ae6
CW		 2424 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2425 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2426
2427 /* In units of 100MHz */
c6a828d3
DV		 2428 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2429 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2430 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2431
2b4e57bd
ED		 2432 /* disable the counters and set deterministic thresholds */
2433 I915_WRITE(GEN6_RC_CONTROL, 0);
2434
2435 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2436 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2437 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2438 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2439 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2440
b4519513
CW		 2441 for_each_ring(ring, dev_priv, i)
2442 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2443
2444 I915_WRITE(GEN6_RC_SLEEP, 0);
2445 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2446 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2447 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2448 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2449
5a7dc92a 2450 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2451 rc6_mode = intel_enable_rc6(dev_priv->dev);
2452 if (rc6_mode & INTEL_RC6_ENABLE)
2453 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2454
5a7dc92a
ED		 2455 /* We don't use those on Haswell */
2456 if (!IS_HASWELL(dev)) {
2457 if (rc6_mode & INTEL_RC6p_ENABLE)
2458 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2459
5a7dc92a
ED		 2460 if (rc6_mode & INTEL_RC6pp_ENABLE)
2461 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2462 }
2b4e57bd
ED		 2463
2464 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2465 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2466 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2467 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2468
2469 I915_WRITE(GEN6_RC_CONTROL,
2470 rc6_mask |
2471 GEN6_RC_CTL_EI_MODE(1) |
2472 GEN6_RC_CTL_HW_ENABLE);
2473
2474 I915_WRITE(GEN6_RPNSWREQ,
2475 GEN6_FREQUENCY(10) |
2476 GEN6_OFFSET(0) |
2477 GEN6_AGGRESSIVE_TURBO);
2478 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2479 GEN6_FREQUENCY(12));
2480
2481 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2482 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2483 dev_priv->rps.max_delay << 24 |
2484 dev_priv->rps.min_delay << 16);
5a7dc92a 2485
1ee9ae32
DV		 2486 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2487 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2488 I915_WRITE(GEN6_RP_UP_EI, 66000);
2489 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2490
2b4e57bd
ED		 2491 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2492 I915_WRITE(GEN6_RP_CONTROL,
2493 GEN6_RP_MEDIA_TURBO |
89ba829e 2494 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2495 GEN6_RP_MEDIA_IS_GFX |
2496 GEN6_RP_ENABLE |
2497 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2498 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd
ED		 2499
2500 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2501 500))
2502 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2503
2504 I915_WRITE(GEN6_PCODE_DATA, 0);
2505 I915_WRITE(GEN6_PCODE_MAILBOX,
2506 GEN6_PCODE_READY |
2507 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
2508 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2509 500))
2510 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2511
2b4e57bd
ED		 2512 /* Check for overclock support */
2513 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2514 500))
2515 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2516 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
2517 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
2518 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2519 500))
2520 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2521 if (pcu_mbox & (1<<31)) { /* OC supported */
c6a828d3 2522 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2b4e57bd
ED		 2523 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2524 }
2525
7b9e0ae6 2526 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2527
2528 /* requires MSI enabled */
ff928261 2529 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2530 spin_lock_irq(&dev_priv->rps.lock);
2531 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2532 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2533 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2534 /* enable all PM interrupts */
2535 I915_WRITE(GEN6_PMINTRMSK, 0);
2536
2537 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2538}
2539
79f5b2c7 2540static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2541{
79f5b2c7 2542 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd
ED		 2543 int min_freq = 15;
2544 int gpu_freq, ia_freq, max_ia_freq;
2545 int scaling_factor = 180;
2546
79f5b2c7
DV		 2547 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2548
2b4e57bd
ED		 2549 max_ia_freq = cpufreq_quick_get_max(0);
2550 /*
2551 * Default to measured freq if none found, PCU will ensure we don't go
2552 * over
2553 */
2554 if (!max_ia_freq)
2555 max_ia_freq = tsc_khz;
2556
2557 /* Convert from kHz to MHz */
2558 max_ia_freq /= 1000;
2559
2b4e57bd
ED		 2560 /*
2561 * For each potential GPU frequency, load a ring frequency we'd like
2562 * to use for memory access. We do this by specifying the IA frequency
2563 * the PCU should use as a reference to determine the ring frequency.
2564 */
c6a828d3 2565 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2566 gpu_freq--) {
c6a828d3 2567 int diff = dev_priv->rps.max_delay - gpu_freq;
2b4e57bd
ED		 2568
2569 /*
2570 * For GPU frequencies less than 750MHz, just use the lowest
2571 * ring freq.
2572 */
2573 if (gpu_freq < min_freq)
2574 ia_freq = 800;
2575 else
2576 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2577 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2578
2579 I915_WRITE(GEN6_PCODE_DATA,
2580 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
2581 gpu_freq);
2582 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
2583 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
2584 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
2585 GEN6_PCODE_READY) == 0, 10)) {
2586 DRM_ERROR("pcode write of freq table timed out\n");
2587 continue;
2588 }
2589 }
2b4e57bd
ED		 2590}
2591
930ebb46 2592void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 2593{
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595
2596 if (dev_priv->renderctx) {
2597 i915_gem_object_unpin(dev_priv->renderctx);
2598 drm_gem_object_unreference(&dev_priv->renderctx->base);
2599 dev_priv->renderctx = NULL;
2600 }
2601
2602 if (dev_priv->pwrctx) {
2603 i915_gem_object_unpin(dev_priv->pwrctx);
2604 drm_gem_object_unreference(&dev_priv->pwrctx->base);
2605 dev_priv->pwrctx = NULL;
2606 }
2607}
2608
930ebb46 2609static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2610{
2611 struct drm_i915_private *dev_priv = dev->dev_private;
2612
2613 if (I915_READ(PWRCTXA)) {
2614 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2615 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2616 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2617 50);
2618
2619 I915_WRITE(PWRCTXA, 0);
2620 POSTING_READ(PWRCTXA);
2621
2622 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2623 POSTING_READ(RSTDBYCTL);
2624 }
2b4e57bd
ED		 2625}
2626
2627static int ironlake_setup_rc6(struct drm_device *dev)
2628{
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630
2631 if (dev_priv->renderctx == NULL)
2632 dev_priv->renderctx = intel_alloc_context_page(dev);
2633 if (!dev_priv->renderctx)
2634 return -ENOMEM;
2635
2636 if (dev_priv->pwrctx == NULL)
2637 dev_priv->pwrctx = intel_alloc_context_page(dev);
2638 if (!dev_priv->pwrctx) {
2639 ironlake_teardown_rc6(dev);
2640 return -ENOMEM;
2641 }
2642
2643 return 0;
2644}
2645
930ebb46 2646static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2647{
2648 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2649 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2b4e57bd
ED		 2650 int ret;
2651
2652 /* rc6 disabled by default due to repeated reports of hanging during
2653 * boot and resume.
2654 */
2655 if (!intel_enable_rc6(dev))
2656 return;
2657
79f5b2c7
DV		 2658 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2659
2b4e57bd 2660 ret = ironlake_setup_rc6(dev);
79f5b2c7 2661 if (ret)
2b4e57bd 2662 return;
2b4e57bd
ED		 2663
2664 /*
2665 * GPU can automatically power down the render unit if given a page
2666 * to save state.
2667 */
6d90c952 2668 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2669 if (ret) {
2670 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2671 return;
2672 }
2673
6d90c952
DV		 2674 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2675 intel_ring_emit(ring, MI_SET_CONTEXT);
2676 intel_ring_emit(ring, dev_priv->renderctx->gtt_offset |
2677 MI_MM_SPACE_GTT |
2678 MI_SAVE_EXT_STATE_EN |
2679 MI_RESTORE_EXT_STATE_EN |
2680 MI_RESTORE_INHIBIT);
2681 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2682 intel_ring_emit(ring, MI_NOOP);
2683 intel_ring_emit(ring, MI_FLUSH);
2684 intel_ring_advance(ring);
2b4e57bd
ED		 2685
2686 /*
2687 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2688 * does an implicit flush, combined with MI_FLUSH above, it should be
2689 * safe to assume that renderctx is valid
2690 */
6d90c952 2691 ret = intel_wait_ring_idle(ring);
2b4e57bd
ED		 2692 if (ret) {
2693 DRM_ERROR("failed to enable ironlake power power savings\n");
2694 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2695 return;
2696 }
2697
2698 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
2699 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2700}
2701
dde18883
ED		 2702static unsigned long intel_pxfreq(u32 vidfreq)
2703{
2704 unsigned long freq;
2705 int div = (vidfreq & 0x3f0000) >> 16;
2706 int post = (vidfreq & 0x3000) >> 12;
2707 int pre = (vidfreq & 0x7);
2708
2709 if (!pre)
2710 return 0;
2711
2712 freq = ((div * 133333) / ((1<<post) * pre));
2713
2714 return freq;
2715}
2716
eb48eb00
DV		 2717static const struct cparams {
2718 u16 i;
2719 u16 t;
2720 u16 m;
2721 u16 c;
2722} cparams[] = {
2723 { 1, 1333, 301, 28664 },
2724 { 1, 1066, 294, 24460 },
2725 { 1, 800, 294, 25192 },
2726 { 0, 1333, 276, 27605 },
2727 { 0, 1066, 276, 27605 },
2728 { 0, 800, 231, 23784 },
2729};
2730
f531dcb2 2731static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2732{
2733 u64 total_count, diff, ret;
2734 u32 count1, count2, count3, m = 0, c = 0;
2735 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2736 int i;
2737
02d71956
DV		 2738 assert_spin_locked(&mchdev_lock);
2739
20e4d407 2740 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 2741
2742 /* Prevent division-by-zero if we are asking too fast.
2743 * Also, we don't get interesting results if we are polling
2744 * faster than once in 10ms, so just return the saved value
2745 * in such cases.
2746 */
2747 if (diff1 <= 10)
20e4d407 2748 return dev_priv->ips.chipset_power;
eb48eb00
DV		 2749
2750 count1 = I915_READ(DMIEC);
2751 count2 = I915_READ(DDREC);
2752 count3 = I915_READ(CSIEC);
2753
2754 total_count = count1 + count2 + count3;
2755
2756 /* FIXME: handle per-counter overflow */
20e4d407
DV		 2757 if (total_count < dev_priv->ips.last_count1) {
2758 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 2759 diff += total_count;
2760 } else {
20e4d407 2761 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 2762 }
2763
2764 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 2765 if (cparams[i].i == dev_priv->ips.c_m &&
2766 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 2767 m = cparams[i].m;
2768 c = cparams[i].c;
2769 break;
2770 }
2771 }
2772
2773 diff = div_u64(diff, diff1);
2774 ret = ((m * diff) + c);
2775 ret = div_u64(ret, 10);
2776
20e4d407
DV		 2777 dev_priv->ips.last_count1 = total_count;
2778 dev_priv->ips.last_time1 = now;
eb48eb00 2779
20e4d407 2780 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 2781
2782 return ret;
2783}
2784
f531dcb2
CW		 2785unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2786{
2787 unsigned long val;
2788
2789 if (dev_priv->info->gen != 5)
2790 return 0;
2791
2792 spin_lock_irq(&mchdev_lock);
2793
2794 val = __i915_chipset_val(dev_priv);
2795
2796 spin_unlock_irq(&mchdev_lock);
2797
2798 return val;
2799}
2800
eb48eb00
DV		 2801unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2802{
2803 unsigned long m, x, b;
2804 u32 tsfs;
2805
2806 tsfs = I915_READ(TSFS);
2807
2808 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2809 x = I915_READ8(TR1);
2810
2811 b = tsfs & TSFS_INTR_MASK;
2812
2813 return ((m * x) / 127) - b;
2814}
2815
2816static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2817{
2818 static const struct v_table {
2819 u16 vd; /* in .1 mil */
2820 u16 vm; /* in .1 mil */
2821 } v_table[] = {
2822 { 0, 0, },
2823 { 375, 0, },
2824 { 500, 0, },
2825 { 625, 0, },
2826 { 750, 0, },
2827 { 875, 0, },
2828 { 1000, 0, },
2829 { 1125, 0, },
2830 { 4125, 3000, },
2831 { 4125, 3000, },
2832 { 4125, 3000, },
2833 { 4125, 3000, },
2834 { 4125, 3000, },
2835 { 4125, 3000, },
2836 { 4125, 3000, },
2837 { 4125, 3000, },
2838 { 4125, 3000, },
2839 { 4125, 3000, },
2840 { 4125, 3000, },
2841 { 4125, 3000, },
2842 { 4125, 3000, },
2843 { 4125, 3000, },
2844 { 4125, 3000, },
2845 { 4125, 3000, },
2846 { 4125, 3000, },
2847 { 4125, 3000, },
2848 { 4125, 3000, },
2849 { 4125, 3000, },
2850 { 4125, 3000, },
2851 { 4125, 3000, },
2852 { 4125, 3000, },
2853 { 4125, 3000, },
2854 { 4250, 3125, },
2855 { 4375, 3250, },
2856 { 4500, 3375, },
2857 { 4625, 3500, },
2858 { 4750, 3625, },
2859 { 4875, 3750, },
2860 { 5000, 3875, },
2861 { 5125, 4000, },
2862 { 5250, 4125, },
2863 { 5375, 4250, },
2864 { 5500, 4375, },
2865 { 5625, 4500, },
2866 { 5750, 4625, },
2867 { 5875, 4750, },
2868 { 6000, 4875, },
2869 { 6125, 5000, },
2870 { 6250, 5125, },
2871 { 6375, 5250, },
2872 { 6500, 5375, },
2873 { 6625, 5500, },
2874 { 6750, 5625, },
2875 { 6875, 5750, },
2876 { 7000, 5875, },
2877 { 7125, 6000, },
2878 { 7250, 6125, },
2879 { 7375, 6250, },
2880 { 7500, 6375, },
2881 { 7625, 6500, },
2882 { 7750, 6625, },
2883 { 7875, 6750, },
2884 { 8000, 6875, },
2885 { 8125, 7000, },
2886 { 8250, 7125, },
2887 { 8375, 7250, },
2888 { 8500, 7375, },
2889 { 8625, 7500, },
2890 { 8750, 7625, },
2891 { 8875, 7750, },
2892 { 9000, 7875, },
2893 { 9125, 8000, },
2894 { 9250, 8125, },
2895 { 9375, 8250, },
2896 { 9500, 8375, },
2897 { 9625, 8500, },
2898 { 9750, 8625, },
2899 { 9875, 8750, },
2900 { 10000, 8875, },
2901 { 10125, 9000, },
2902 { 10250, 9125, },
2903 { 10375, 9250, },
2904 { 10500, 9375, },
2905 { 10625, 9500, },
2906 { 10750, 9625, },
2907 { 10875, 9750, },
2908 { 11000, 9875, },
2909 { 11125, 10000, },
2910 { 11250, 10125, },
2911 { 11375, 10250, },
2912 { 11500, 10375, },
2913 { 11625, 10500, },
2914 { 11750, 10625, },
2915 { 11875, 10750, },
2916 { 12000, 10875, },
2917 { 12125, 11000, },
2918 { 12250, 11125, },
2919 { 12375, 11250, },
2920 { 12500, 11375, },
2921 { 12625, 11500, },
2922 { 12750, 11625, },
2923 { 12875, 11750, },
2924 { 13000, 11875, },
2925 { 13125, 12000, },
2926 { 13250, 12125, },
2927 { 13375, 12250, },
2928 { 13500, 12375, },
2929 { 13625, 12500, },
2930 { 13750, 12625, },
2931 { 13875, 12750, },
2932 { 14000, 12875, },
2933 { 14125, 13000, },
2934 { 14250, 13125, },
2935 { 14375, 13250, },
2936 { 14500, 13375, },
2937 { 14625, 13500, },
2938 { 14750, 13625, },
2939 { 14875, 13750, },
2940 { 15000, 13875, },
2941 { 15125, 14000, },
2942 { 15250, 14125, },
2943 { 15375, 14250, },
2944 { 15500, 14375, },
2945 { 15625, 14500, },
2946 { 15750, 14625, },
2947 { 15875, 14750, },
2948 { 16000, 14875, },
2949 { 16125, 15000, },
2950 };
2951 if (dev_priv->info->is_mobile)
2952 return v_table[pxvid].vm;
2953 else
2954 return v_table[pxvid].vd;
2955}
2956
02d71956 2957static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2958{
2959 struct timespec now, diff1;
2960 u64 diff;
2961 unsigned long diffms;
2962 u32 count;
2963
02d71956 2964 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 2965
2966 getrawmonotonic(&now);
20e4d407 2967 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 2968
2969 /* Don't divide by 0 */
2970 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2971 if (!diffms)
2972 return;
2973
2974 count = I915_READ(GFXEC);
2975
20e4d407
DV		 2976 if (count < dev_priv->ips.last_count2) {
2977 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 2978 diff += count;
2979 } else {
20e4d407 2980 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 2981 }
2982
20e4d407
DV		 2983 dev_priv->ips.last_count2 = count;
2984 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 2985
2986 /* More magic constants... */
2987 diff = diff * 1181;
2988 diff = div_u64(diff, diffms * 10);
20e4d407 2989 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 2990}
2991
02d71956
DV		 2992void i915_update_gfx_val(struct drm_i915_private *dev_priv)
2993{
2994 if (dev_priv->info->gen != 5)
2995 return;
2996
9270388e 2997 spin_lock_irq(&mchdev_lock);
02d71956
DV		 2998
2999 __i915_update_gfx_val(dev_priv);
3000
9270388e 3001 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3002}
3003
f531dcb2 3004static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3005{
3006 unsigned long t, corr, state1, corr2, state2;
3007 u32 pxvid, ext_v;
3008
02d71956
DV		 3009 assert_spin_locked(&mchdev_lock);
3010
c6a828d3 3011 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3012 pxvid = (pxvid >> 24) & 0x7f;
3013 ext_v = pvid_to_extvid(dev_priv, pxvid);
3014
3015 state1 = ext_v;
3016
3017 t = i915_mch_val(dev_priv);
3018
3019 /* Revel in the empirically derived constants */
3020
3021 /* Correction factor in 1/100000 units */
3022 if (t > 80)
3023 corr = ((t * 2349) + 135940);
3024 else if (t >= 50)
3025 corr = ((t * 964) + 29317);
3026 else /* < 50 */
3027 corr = ((t * 301) + 1004);
3028
3029 corr = corr * ((150142 * state1) / 10000 - 78642);
3030 corr /= 100000;
20e4d407 3031 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3032
3033 state2 = (corr2 * state1) / 10000;
3034 state2 /= 100; /* convert to mW */
3035
02d71956 3036 __i915_update_gfx_val(dev_priv);
eb48eb00 3037
20e4d407 3038 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3039}
3040
f531dcb2
CW		 3041unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3042{
3043 unsigned long val;
3044
3045 if (dev_priv->info->gen != 5)
3046 return 0;
3047
3048 spin_lock_irq(&mchdev_lock);
3049
3050 val = __i915_gfx_val(dev_priv);
3051
3052 spin_unlock_irq(&mchdev_lock);
3053
3054 return val;
3055}
3056
eb48eb00
DV		 3057/**
3058 * i915_read_mch_val - return value for IPS use
3059 *
3060 * Calculate and return a value for the IPS driver to use when deciding whether
3061 * we have thermal and power headroom to increase CPU or GPU power budget.
3062 */
3063unsigned long i915_read_mch_val(void)
3064{
3065 struct drm_i915_private *dev_priv;
3066 unsigned long chipset_val, graphics_val, ret = 0;
3067
9270388e 3068 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3069 if (!i915_mch_dev)
3070 goto out_unlock;
3071 dev_priv = i915_mch_dev;
3072
f531dcb2
CW		 3073 chipset_val = __i915_chipset_val(dev_priv);
3074 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3075
3076 ret = chipset_val + graphics_val;
3077
3078out_unlock:
9270388e 3079 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3080
3081 return ret;
3082}
3083EXPORT_SYMBOL_GPL(i915_read_mch_val);
3084
3085/**
3086 * i915_gpu_raise - raise GPU frequency limit
3087 *
3088 * Raise the limit; IPS indicates we have thermal headroom.
3089 */
3090bool i915_gpu_raise(void)
3091{
3092 struct drm_i915_private *dev_priv;
3093 bool ret = true;
3094
9270388e 3095 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3096 if (!i915_mch_dev) {
3097 ret = false;
3098 goto out_unlock;
3099 }
3100 dev_priv = i915_mch_dev;
3101
20e4d407
DV		 3102 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3103 dev_priv->ips.max_delay--;
eb48eb00
DV		 3104
3105out_unlock:
9270388e 3106 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3107
3108 return ret;
3109}
3110EXPORT_SYMBOL_GPL(i915_gpu_raise);
3111
3112/**
3113 * i915_gpu_lower - lower GPU frequency limit
3114 *
3115 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3116 * frequency maximum.
3117 */
3118bool i915_gpu_lower(void)
3119{
3120 struct drm_i915_private *dev_priv;
3121 bool ret = true;
3122
9270388e 3123 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3124 if (!i915_mch_dev) {
3125 ret = false;
3126 goto out_unlock;
3127 }
3128 dev_priv = i915_mch_dev;
3129
20e4d407
DV		 3130 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3131 dev_priv->ips.max_delay++;
eb48eb00
DV		 3132
3133out_unlock:
9270388e 3134 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3135
3136 return ret;
3137}
3138EXPORT_SYMBOL_GPL(i915_gpu_lower);
3139
3140/**
3141 * i915_gpu_busy - indicate GPU business to IPS
3142 *
3143 * Tell the IPS driver whether or not the GPU is busy.
3144 */
3145bool i915_gpu_busy(void)
3146{
3147 struct drm_i915_private *dev_priv;
f047e395 3148 struct intel_ring_buffer *ring;
eb48eb00 3149 bool ret = false;
f047e395 3150 int i;
eb48eb00 3151
9270388e 3152 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3153 if (!i915_mch_dev)
3154 goto out_unlock;
3155 dev_priv = i915_mch_dev;
3156
f047e395
CW		 3157 for_each_ring(ring, dev_priv, i)
3158 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3159
3160out_unlock:
9270388e 3161 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3162
3163 return ret;
3164}
3165EXPORT_SYMBOL_GPL(i915_gpu_busy);
3166
3167/**
3168 * i915_gpu_turbo_disable - disable graphics turbo
3169 *
3170 * Disable graphics turbo by resetting the max frequency and setting the
3171 * current frequency to the default.
3172 */
3173bool i915_gpu_turbo_disable(void)
3174{
3175 struct drm_i915_private *dev_priv;
3176 bool ret = true;
3177
9270388e 3178 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3179 if (!i915_mch_dev) {
3180 ret = false;
3181 goto out_unlock;
3182 }
3183 dev_priv = i915_mch_dev;
3184
20e4d407 3185 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3186
20e4d407 3187 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3188 ret = false;
3189
3190out_unlock:
9270388e 3191 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3192
3193 return ret;
3194}
3195EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3196
3197/**
3198 * Tells the intel_ips driver that the i915 driver is now loaded, if
3199 * IPS got loaded first.
3200 *
3201 * This awkward dance is so that neither module has to depend on the
3202 * other in order for IPS to do the appropriate communication of
3203 * GPU turbo limits to i915.
3204 */
3205static void
3206ips_ping_for_i915_load(void)
3207{
3208 void (*link)(void);
3209
3210 link = symbol_get(ips_link_to_i915_driver);
3211 if (link) {
3212 link();
3213 symbol_put(ips_link_to_i915_driver);
3214 }
3215}
3216
3217void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3218{
02d71956
DV		 3219 /* We only register the i915 ips part with intel-ips once everything is
3220 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3221 spin_lock_irq(&mchdev_lock);
eb48eb00 3222 i915_mch_dev = dev_priv;
9270388e 3223 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3224
3225 ips_ping_for_i915_load();
3226}
3227
3228void intel_gpu_ips_teardown(void)
3229{
9270388e 3230 spin_lock_irq(&mchdev_lock);
eb48eb00 3231 i915_mch_dev = NULL;
9270388e 3232 spin_unlock_irq(&mchdev_lock);
eb48eb00 3233}
8090c6b9 3234static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3235{
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 u32 lcfuse;
3238 u8 pxw[16];
3239 int i;
3240
3241 /* Disable to program */
3242 I915_WRITE(ECR, 0);
3243 POSTING_READ(ECR);
3244
3245 /* Program energy weights for various events */
3246 I915_WRITE(SDEW, 0x15040d00);
3247 I915_WRITE(CSIEW0, 0x007f0000);
3248 I915_WRITE(CSIEW1, 0x1e220004);
3249 I915_WRITE(CSIEW2, 0x04000004);
3250
3251 for (i = 0; i < 5; i++)
3252 I915_WRITE(PEW + (i * 4), 0);
3253 for (i = 0; i < 3; i++)
3254 I915_WRITE(DEW + (i * 4), 0);
3255
3256 /* Program P-state weights to account for frequency power adjustment */
3257 for (i = 0; i < 16; i++) {
3258 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3259 unsigned long freq = intel_pxfreq(pxvidfreq);
3260 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3261 PXVFREQ_PX_SHIFT;
3262 unsigned long val;
3263
3264 val = vid * vid;
3265 val *= (freq / 1000);
3266 val *= 255;
3267 val /= (127*127*900);
3268 if (val > 0xff)
3269 DRM_ERROR("bad pxval: %ld\n", val);
3270 pxw[i] = val;
3271 }
3272 /* Render standby states get 0 weight */
3273 pxw[14] = 0;
3274 pxw[15] = 0;
3275
3276 for (i = 0; i < 4; i++) {
3277 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3278 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3279 I915_WRITE(PXW + (i * 4), val);
3280 }
3281
3282 /* Adjust magic regs to magic values (more experimental results) */
3283 I915_WRITE(OGW0, 0);
3284 I915_WRITE(OGW1, 0);
3285 I915_WRITE(EG0, 0x00007f00);
3286 I915_WRITE(EG1, 0x0000000e);
3287 I915_WRITE(EG2, 0x000e0000);
3288 I915_WRITE(EG3, 0x68000300);
3289 I915_WRITE(EG4, 0x42000000);
3290 I915_WRITE(EG5, 0x00140031);
3291 I915_WRITE(EG6, 0);
3292 I915_WRITE(EG7, 0);
3293
3294 for (i = 0; i < 8; i++)
3295 I915_WRITE(PXWL + (i * 4), 0);
3296
3297 /* Enable PMON + select events */
3298 I915_WRITE(ECR, 0x80000019);
3299
3300 lcfuse = I915_READ(LCFUSE02);
3301
20e4d407 3302 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3303}
3304
8090c6b9
DV		 3305void intel_disable_gt_powersave(struct drm_device *dev)
3306{
930ebb46 3307 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3308 ironlake_disable_drps(dev);
930ebb46
DV		 3309 ironlake_disable_rc6(dev);
3310 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
8090c6b9 3311 gen6_disable_rps(dev);
930ebb46 3312 }
8090c6b9
DV		 3313}
3314
3315void intel_enable_gt_powersave(struct drm_device *dev)
3316{
8090c6b9
DV		 3317 if (IS_IRONLAKE_M(dev)) {
3318 ironlake_enable_drps(dev);
3319 ironlake_enable_rc6(dev);
3320 intel_init_emon(dev);
7cf50fc8 3321 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
79f5b2c7
DV		 3322 gen6_enable_rps(dev);
3323 gen6_update_ring_freq(dev);
8090c6b9
DV		 3324 }
3325}
3326
1fa61106 3327static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3331
3332 /* Required for FBC */
3333 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
3334 DPFCRUNIT_CLOCK_GATE_DISABLE |
3335 DPFDUNIT_CLOCK_GATE_DISABLE;
3336 /* Required for CxSR */
3337 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
3338
3339 I915_WRITE(PCH_3DCGDIS0,
3340 MARIUNIT_CLOCK_GATE_DISABLE |
3341 SVSMUNIT_CLOCK_GATE_DISABLE);
3342 I915_WRITE(PCH_3DCGDIS1,
3343 VFMUNIT_CLOCK_GATE_DISABLE);
3344
3345 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3346
3347 /*
3348 * According to the spec the following bits should be set in
3349 * order to enable memory self-refresh
3350 * The bit 22/21 of 0x42004
3351 * The bit 5 of 0x42020
3352 * The bit 15 of 0x45000
3353 */
3354 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3355 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3356 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3357 I915_WRITE(ILK_DSPCLK_GATE,
3358 (I915_READ(ILK_DSPCLK_GATE) |
3359 ILK_DPARB_CLK_GATE));
3360 I915_WRITE(DISP_ARB_CTL,
3361 (I915_READ(DISP_ARB_CTL) |
3362 DISP_FBC_WM_DIS));
3363 I915_WRITE(WM3_LP_ILK, 0);
3364 I915_WRITE(WM2_LP_ILK, 0);
3365 I915_WRITE(WM1_LP_ILK, 0);
3366
3367 /*
3368 * Based on the document from hardware guys the following bits
3369 * should be set unconditionally in order to enable FBC.
3370 * The bit 22 of 0x42000
3371 * The bit 22 of 0x42004
3372 * The bit 7,8,9 of 0x42020.
3373 */
3374 if (IS_IRONLAKE_M(dev)) {
3375 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3376 I915_READ(ILK_DISPLAY_CHICKEN1) |
3377 ILK_FBCQ_DIS);
3378 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3379 I915_READ(ILK_DISPLAY_CHICKEN2) |
3380 ILK_DPARB_GATE);
3381 I915_WRITE(ILK_DSPCLK_GATE,
3382 I915_READ(ILK_DSPCLK_GATE) |
3383 ILK_DPFC_DIS1 |
3384 ILK_DPFC_DIS2 |
3385 ILK_CLK_FBC);
3386 }
3387
3388 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3389 I915_READ(ILK_DISPLAY_CHICKEN2) |
3390 ILK_ELPIN_409_SELECT);
3391 I915_WRITE(_3D_CHICKEN2,
3392 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3393 _3D_CHICKEN2_WM_READ_PIPELINED);
3394}
3395
1fa61106 3396static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3397{
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 int pipe;
3400 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3401
3402 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3403
3404 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3405 I915_READ(ILK_DISPLAY_CHICKEN2) |
3406 ILK_ELPIN_409_SELECT);
3407
3408 I915_WRITE(WM3_LP_ILK, 0);
3409 I915_WRITE(WM2_LP_ILK, 0);
3410 I915_WRITE(WM1_LP_ILK, 0);
3411
6f1d69b0 3412 I915_WRITE(CACHE_MODE_0,
50743298 3413 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3414
3415 I915_WRITE(GEN6_UCGCTL1,
3416 I915_READ(GEN6_UCGCTL1) |
3417 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3418 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3419
3420 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3421 * gating disable must be set. Failure to set it results in
3422 * flickering pixels due to Z write ordering failures after
3423 * some amount of runtime in the Mesa "fire" demo, and Unigine
3424 * Sanctuary and Tropics, and apparently anything else with
3425 * alpha test or pixel discard.
3426 *
3427 * According to the spec, bit 11 (RCCUNIT) must also be set,
3428 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3429 *
3430 * Also apply WaDisableVDSUnitClockGating and
3431 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3432 */
3433 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3434 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3435 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3436 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3437
3438 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 3439 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3440 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 3441
3442 /*
3443 * According to the spec the following bits should be
3444 * set in order to enable memory self-refresh and fbc:
3445 * The bit21 and bit22 of 0x42000
3446 * The bit21 and bit22 of 0x42004
3447 * The bit5 and bit7 of 0x42020
3448 * The bit14 of 0x70180
3449 * The bit14 of 0x71180
3450 */
3451 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3452 I915_READ(ILK_DISPLAY_CHICKEN1) |
3453 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3454 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3455 I915_READ(ILK_DISPLAY_CHICKEN2) |
3456 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3457 I915_WRITE(ILK_DSPCLK_GATE,
3458 I915_READ(ILK_DSPCLK_GATE) |
3459 ILK_DPARB_CLK_GATE |
3460 ILK_DPFD_CLK_GATE);
3461
b4ae3f22
JB		 3462 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3463 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3464
6f1d69b0
ED		 3465 for_each_pipe(pipe) {
3466 I915_WRITE(DSPCNTR(pipe),
3467 I915_READ(DSPCNTR(pipe)) |
3468 DISPPLANE_TRICKLE_FEED_DISABLE);
3469 intel_flush_display_plane(dev_priv, pipe);
3470 }
f8f2ac9a
BW		 3471
3472 /* The default value should be 0x200 according to docs, but the two
3473 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3474 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3475 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
6f1d69b0
ED		 3476}
3477
3478static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3479{
3480 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3481
3482 reg &= ~GEN7_FF_SCHED_MASK;
3483 reg |= GEN7_FF_TS_SCHED_HW;
3484 reg |= GEN7_FF_VS_SCHED_HW;
3485 reg |= GEN7_FF_DS_SCHED_HW;
3486
3487 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3488}
3489
cad2a2d7
ED		 3490static void haswell_init_clock_gating(struct drm_device *dev)
3491{
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 int pipe;
3494 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3495
3496 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3497
3498 I915_WRITE(WM3_LP_ILK, 0);
3499 I915_WRITE(WM2_LP_ILK, 0);
3500 I915_WRITE(WM1_LP_ILK, 0);
3501
3502 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3503 * This implements the WaDisableRCZUnitClockGating workaround.
3504 */
3505 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3506
3507 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3508
3509 I915_WRITE(IVB_CHICKEN3,
3510 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3511 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3512
3513 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3514 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3515 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3516
3517 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3518 I915_WRITE(GEN7_L3CNTLREG1,
3519 GEN7_WA_FOR_GEN7_L3_CONTROL);
3520 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3521 GEN7_WA_L3_CHICKEN_MODE);
3522
3523 /* This is required by WaCatErrorRejectionIssue */
3524 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3525 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3526 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3527
3528 for_each_pipe(pipe) {
3529 I915_WRITE(DSPCNTR(pipe),
3530 I915_READ(DSPCNTR(pipe)) |
3531 DISPPLANE_TRICKLE_FEED_DISABLE);
3532 intel_flush_display_plane(dev_priv, pipe);
3533 }
3534
3535 gen7_setup_fixed_func_scheduler(dev_priv);
3536
3537 /* WaDisable4x2SubspanOptimization */
3538 I915_WRITE(CACHE_MODE_1,
3539 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5
ED		 3540
3541 /* XXX: This is a workaround for early silicon revisions and should be
3542 * removed later.
3543 */
3544 I915_WRITE(WM_DBG,
3545 I915_READ(WM_DBG) |
3546 WM_DBG_DISALLOW_MULTIPLE_LP |
3547 WM_DBG_DISALLOW_SPRITE |
3548 WM_DBG_DISALLOW_MAXFIFO);
3549
cad2a2d7
ED		 3550}
3551
1fa61106 3552static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3553{
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 int pipe;
3556 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
20848223 3557 uint32_t snpcr;
6f1d69b0
ED		 3558
3559 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3560
3561 I915_WRITE(WM3_LP_ILK, 0);
3562 I915_WRITE(WM2_LP_ILK, 0);
3563 I915_WRITE(WM1_LP_ILK, 0);
3564
6f1d69b0
ED		 3565 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3566
3567 I915_WRITE(IVB_CHICKEN3,
3568 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3569 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3570
3571 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3572 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3573 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3574
3575 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3576 I915_WRITE(GEN7_L3CNTLREG1,
3577 GEN7_WA_FOR_GEN7_L3_CONTROL);
3578 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3579 GEN7_WA_L3_CHICKEN_MODE);
3580
0f846f81
JB		 3581 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3582 * gating disable must be set. Failure to set it results in
3583 * flickering pixels due to Z write ordering failures after
3584 * some amount of runtime in the Mesa "fire" demo, and Unigine
3585 * Sanctuary and Tropics, and apparently anything else with
3586 * alpha test or pixel discard.
3587 *
3588 * According to the spec, bit 11 (RCCUNIT) must also be set,
3589 * but we didn't debug actual testcases to find it out.
3590 *
3591 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3592 * This implements the WaDisableRCZUnitClockGating workaround.
3593 */
3594 I915_WRITE(GEN6_UCGCTL2,
3595 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3596 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3597
6f1d69b0
ED		 3598 /* This is required by WaCatErrorRejectionIssue */
3599 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3600 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3601 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3602
3603 for_each_pipe(pipe) {
3604 I915_WRITE(DSPCNTR(pipe),
3605 I915_READ(DSPCNTR(pipe)) |
3606 DISPPLANE_TRICKLE_FEED_DISABLE);
3607 intel_flush_display_plane(dev_priv, pipe);
3608 }
3609
b4ae3f22
JB		 3610 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3611 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3612
6f1d69b0 3613 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3614
3615 /* WaDisable4x2SubspanOptimization */
3616 I915_WRITE(CACHE_MODE_1,
3617 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3618
3619 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3620 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3621 snpcr |= GEN6_MBC_SNPCR_MED;
3622 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6f1d69b0
ED		 3623}
3624
1fa61106 3625static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3626{
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 int pipe;
3629 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3630
3631 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3632
3633 I915_WRITE(WM3_LP_ILK, 0);
3634 I915_WRITE(WM2_LP_ILK, 0);
3635 I915_WRITE(WM1_LP_ILK, 0);
3636
6f1d69b0
ED		 3637 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3638
3639 I915_WRITE(IVB_CHICKEN3,
3640 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3641 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3642
3643 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3644 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3645 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3646
3647 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3648 I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
3649 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3650
3651 /* This is required by WaCatErrorRejectionIssue */
3652 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3653 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3654 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3655
b4ae3f22
JB		 3656 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3657 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3658
0f846f81
JB		 3659
3660 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3661 * gating disable must be set. Failure to set it results in
3662 * flickering pixels due to Z write ordering failures after
3663 * some amount of runtime in the Mesa "fire" demo, and Unigine
3664 * Sanctuary and Tropics, and apparently anything else with
3665 * alpha test or pixel discard.
3666 *
3667 * According to the spec, bit 11 (RCCUNIT) must also be set,
3668 * but we didn't debug actual testcases to find it out.
3669 *
3670 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3671 * This implements the WaDisableRCZUnitClockGating workaround.
3672 *
3673 * Also apply WaDisableVDSUnitClockGating and
3674 * WaDisableRCPBUnitClockGating.
3675 */
3676 I915_WRITE(GEN6_UCGCTL2,
3677 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3678 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3679 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3680 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3681 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3682
e3f33d46
JB		 3683 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3684
6f1d69b0
ED		 3685 for_each_pipe(pipe) {
3686 I915_WRITE(DSPCNTR(pipe),
3687 I915_READ(DSPCNTR(pipe)) |
3688 DISPPLANE_TRICKLE_FEED_DISABLE);
3689 intel_flush_display_plane(dev_priv, pipe);
3690 }
3691
6b26c86d
DV		 3692 I915_WRITE(CACHE_MODE_1,
3693 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f
JB		 3694
3695 /*
3696 * On ValleyView, the GUnit needs to signal the GT
3697 * when flip and other events complete. So enable
3698 * all the GUnit->GT interrupts here
3699 */
3700 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3701 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3702 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3703 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3704 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3705 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3706 PLANEA_FLIPDONE_INT_EN);
6f1d69b0
ED		 3707}
3708
1fa61106 3709static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3710{
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3712 uint32_t dspclk_gate;
3713
3714 I915_WRITE(RENCLK_GATE_D1, 0);
3715 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3716 GS_UNIT_CLOCK_GATE_DISABLE |
3717 CL_UNIT_CLOCK_GATE_DISABLE);
3718 I915_WRITE(RAMCLK_GATE_D, 0);
3719 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3720 OVRUNIT_CLOCK_GATE_DISABLE |
3721 OVCUNIT_CLOCK_GATE_DISABLE;
3722 if (IS_GM45(dev))
3723 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3724 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3725}
3726
1fa61106 3727static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3728{
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730
3731 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3732 I915_WRITE(RENCLK_GATE_D2, 0);
3733 I915_WRITE(DSPCLK_GATE_D, 0);
3734 I915_WRITE(RAMCLK_GATE_D, 0);
3735 I915_WRITE16(DEUC, 0);
3736}
3737
1fa61106 3738static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3739{
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741
3742 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3743 I965_RCC_CLOCK_GATE_DISABLE |
3744 I965_RCPB_CLOCK_GATE_DISABLE |
3745 I965_ISC_CLOCK_GATE_DISABLE |
3746 I965_FBC_CLOCK_GATE_DISABLE);
3747 I915_WRITE(RENCLK_GATE_D2, 0);
3748}
3749
1fa61106 3750static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3751{
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 u32 dstate = I915_READ(D_STATE);
3754
3755 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3756 DSTATE_DOT_CLOCK_GATING;
3757 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 3758
3759 if (IS_PINEVIEW(dev))
3760 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 3761
3762 /* IIR "flip pending" means done if this bit is set */
3763 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 3764}
3765
1fa61106 3766static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3767{
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769
3770 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3771}
3772
1fa61106 3773static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3774{
3775 struct drm_i915_private *dev_priv = dev->dev_private;
3776
3777 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3778}
3779
1fa61106 3780static void ibx_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3781{
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783
3784 /*
3785 * On Ibex Peak and Cougar Point, we need to disable clock
3786 * gating for the panel power sequencer or it will fail to
3787 * start up when no ports are active.
3788 */
3789 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3790}
3791
1fa61106 3792static void cpt_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3793{
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 int pipe;
3796
3797 /*
3798 * On Ibex Peak and Cougar Point, we need to disable clock
3799 * gating for the panel power sequencer or it will fail to
3800 * start up when no ports are active.
3801 */
3802 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3803 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3804 DPLS_EDP_PPS_FIX_DIS);
3805 /* Without this, mode sets may fail silently on FDI */
3806 for_each_pipe(pipe)
3807 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
3808}
3809
3810void intel_init_clock_gating(struct drm_device *dev)
3811{
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813
3814 dev_priv->display.init_clock_gating(dev);
3815
3816 if (dev_priv->display.init_pch_clock_gating)
3817 dev_priv->display.init_pch_clock_gating(dev);
3818}
3819
d0d3e513
ED		 3820/* Starting with Haswell, we have different power wells for
3821 * different parts of the GPU. This attempts to enable them all.
3822 */
3823void intel_init_power_wells(struct drm_device *dev)
3824{
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 unsigned long power_wells[] = {
3827 HSW_PWR_WELL_CTL1,
3828 HSW_PWR_WELL_CTL2,
3829 HSW_PWR_WELL_CTL4
3830 };
3831 int i;
3832
3833 if (!IS_HASWELL(dev))
3834 return;
3835
3836 mutex_lock(&dev->struct_mutex);
3837
3838 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
3839 int well = I915_READ(power_wells[i]);
3840
3841 if ((well & HSW_PWR_WELL_STATE) == 0) {
3842 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
3843 if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
3844 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
3845 }
3846 }
3847
3848 mutex_unlock(&dev->struct_mutex);
3849}
3850
1fa61106
ED		 3851/* Set up chip specific power management-related functions */
3852void intel_init_pm(struct drm_device *dev)
3853{
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855
3856 if (I915_HAS_FBC(dev)) {
3857 if (HAS_PCH_SPLIT(dev)) {
3858 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3859 dev_priv->display.enable_fbc = ironlake_enable_fbc;
3860 dev_priv->display.disable_fbc = ironlake_disable_fbc;
3861 } else if (IS_GM45(dev)) {
3862 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3863 dev_priv->display.enable_fbc = g4x_enable_fbc;
3864 dev_priv->display.disable_fbc = g4x_disable_fbc;
3865 } else if (IS_CRESTLINE(dev)) {
3866 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3867 dev_priv->display.enable_fbc = i8xx_enable_fbc;
3868 dev_priv->display.disable_fbc = i8xx_disable_fbc;
3869 }
3870 /* 855GM needs testing */
3871 }
3872
c921aba8
DV		 3873 /* For cxsr */
3874 if (IS_PINEVIEW(dev))
3875 i915_pineview_get_mem_freq(dev);
3876 else if (IS_GEN5(dev))
3877 i915_ironlake_get_mem_freq(dev);
3878
1fa61106
ED		 3879 /* For FIFO watermark updates */
3880 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 3881 if (HAS_PCH_IBX(dev))
3882 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
3883 else if (HAS_PCH_CPT(dev))
3884 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
3885
3886 if (IS_GEN5(dev)) {
3887 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3888 dev_priv->display.update_wm = ironlake_update_wm;
3889 else {
3890 DRM_DEBUG_KMS("Failed to get proper latency. "
3891 "Disable CxSR\n");
3892 dev_priv->display.update_wm = NULL;
3893 }
3894 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3895 } else if (IS_GEN6(dev)) {
3896 if (SNB_READ_WM0_LATENCY()) {
3897 dev_priv->display.update_wm = sandybridge_update_wm;
3898 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3899 } else {
3900 DRM_DEBUG_KMS("Failed to read display plane latency. "
3901 "Disable CxSR\n");
3902 dev_priv->display.update_wm = NULL;
3903 }
3904 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
3905 } else if (IS_IVYBRIDGE(dev)) {
3906 /* FIXME: detect B0+ stepping and use auto training */
3907 if (SNB_READ_WM0_LATENCY()) {
3908 dev_priv->display.update_wm = sandybridge_update_wm;
3909 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3910 } else {
3911 DRM_DEBUG_KMS("Failed to read display plane latency. "
3912 "Disable CxSR\n");
3913 dev_priv->display.update_wm = NULL;
3914 }
3915 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 3916 } else if (IS_HASWELL(dev)) {
3917 if (SNB_READ_WM0_LATENCY()) {
3918 dev_priv->display.update_wm = sandybridge_update_wm;
3919 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 3920 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 3921 } else {
3922 DRM_DEBUG_KMS("Failed to read display plane latency. "
3923 "Disable CxSR\n");
3924 dev_priv->display.update_wm = NULL;
3925 }
cad2a2d7 3926 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 3927 } else
3928 dev_priv->display.update_wm = NULL;
3929 } else if (IS_VALLEYVIEW(dev)) {
3930 dev_priv->display.update_wm = valleyview_update_wm;
3931 dev_priv->display.init_clock_gating =
3932 valleyview_init_clock_gating;
1fa61106
ED		 3933 } else if (IS_PINEVIEW(dev)) {
3934 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
3935 dev_priv->is_ddr3,
3936 dev_priv->fsb_freq,
3937 dev_priv->mem_freq)) {
3938 DRM_INFO("failed to find known CxSR latency "
3939 "(found ddr%s fsb freq %d, mem freq %d), "
3940 "disabling CxSR\n",
3941 (dev_priv->is_ddr3 == 1) ? "3" : "2",
3942 dev_priv->fsb_freq, dev_priv->mem_freq);
3943 /* Disable CxSR and never update its watermark again */
3944 pineview_disable_cxsr(dev);
3945 dev_priv->display.update_wm = NULL;
3946 } else
3947 dev_priv->display.update_wm = pineview_update_wm;
3948 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
3949 } else if (IS_G4X(dev)) {
3950 dev_priv->display.update_wm = g4x_update_wm;
3951 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
3952 } else if (IS_GEN4(dev)) {
3953 dev_priv->display.update_wm = i965_update_wm;
3954 if (IS_CRESTLINE(dev))
3955 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
3956 else if (IS_BROADWATER(dev))
3957 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
3958 } else if (IS_GEN3(dev)) {
3959 dev_priv->display.update_wm = i9xx_update_wm;
3960 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
3961 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
3962 } else if (IS_I865G(dev)) {
3963 dev_priv->display.update_wm = i830_update_wm;
3964 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
3965 dev_priv->display.get_fifo_size = i830_get_fifo_size;
3966 } else if (IS_I85X(dev)) {
3967 dev_priv->display.update_wm = i9xx_update_wm;
3968 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
3969 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
3970 } else {
3971 dev_priv->display.update_wm = i830_update_wm;
3972 dev_priv->display.init_clock_gating = i830_init_clock_gating;
3973 if (IS_845G(dev))
3974 dev_priv->display.get_fifo_size = i845_get_fifo_size;
3975 else
3976 dev_priv->display.get_fifo_size = i830_get_fifo_size;
3977 }
3978}
3979
6590190d
ED		 3980static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
3981{
3982 u32 gt_thread_status_mask;
3983
3984 if (IS_HASWELL(dev_priv->dev))
3985 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
3986 else
3987 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
3988
3989 /* w/a for a sporadic read returning 0 by waiting for the GT
3990 * thread to wake up.
3991 */
3992 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
3993 DRM_ERROR("GT thread status wait timed out\n");
3994}
3995
3996static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
3997{
3998 u32 forcewake_ack;
3999
4000 if (IS_HASWELL(dev_priv->dev))
4001 forcewake_ack = FORCEWAKE_ACK_HSW;
4002 else
4003 forcewake_ack = FORCEWAKE_ACK;
4004
057d3860
BW		 4005 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4006 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4007 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d
ED		 4008
4009 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 4010 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4011
057d3860
BW		 4012 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4013 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4014 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4015
4016 __gen6_gt_wait_for_thread_c0(dev_priv);
4017}
4018
4019static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4020{
4021 u32 forcewake_ack;
4022
4023 if (IS_HASWELL(dev_priv->dev))
4024 forcewake_ack = FORCEWAKE_ACK_HSW;
4025 else
4026 forcewake_ack = FORCEWAKE_MT_ACK;
4027
057d3860
BW		 4028 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4029 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4030 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d
ED		 4031
4032 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
8dee3eea 4033 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4034
057d3860
BW		 4035 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4036 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4037 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4038
4039 __gen6_gt_wait_for_thread_c0(dev_priv);
4040}
4041
4042/*
4043 * Generally this is called implicitly by the register read function. However,
4044 * if some sequence requires the GT to not power down then this function should
4045 * be called at the beginning of the sequence followed by a call to
4046 * gen6_gt_force_wake_put() at the end of the sequence.
4047 */
4048void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4049{
4050 unsigned long irqflags;
4051
4052 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4053 if (dev_priv->forcewake_count++ == 0)
4054 dev_priv->gt.force_wake_get(dev_priv);
4055 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4056}
4057
4058void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4059{
4060 u32 gtfifodbg;
4061 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4062 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4063 "MMIO read or write has been dropped %x\n", gtfifodbg))
4064 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4065}
4066
4067static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4068{
4069 I915_WRITE_NOTRACE(FORCEWAKE, 0);
8dee3eea 4070 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4071 gen6_gt_check_fifodbg(dev_priv);
4072}
4073
4074static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4075{
4076 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
8dee3eea 4077 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4078 gen6_gt_check_fifodbg(dev_priv);
4079}
4080
4081/*
4082 * see gen6_gt_force_wake_get()
4083 */
4084void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4085{
4086 unsigned long irqflags;
4087
4088 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4089 if (--dev_priv->forcewake_count == 0)
4090 dev_priv->gt.force_wake_put(dev_priv);
4091 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4092}
4093
4094int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4095{
4096 int ret = 0;
4097
4098 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4099 int loop = 500;
4100 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4101 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4102 udelay(10);
4103 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4104 }
4105 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4106 ++ret;
4107 dev_priv->gt_fifo_count = fifo;
4108 }
4109 dev_priv->gt_fifo_count--;
4110
4111 return ret;
4112}
4113
4114static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4115{
057d3860
BW		 4116 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4117 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4118 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4119
5ab140a4 4120 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(1));
6590190d 4121
057d3860
BW		 4122 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4123 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4124 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4125
4126 __gen6_gt_wait_for_thread_c0(dev_priv);
4127}
4128
4129static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4130{
5ab140a4
DV		 4131 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(1));
4132 /* The below doubles as a POSTING_READ */
4133 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4134}
4135
4136void intel_gt_init(struct drm_device *dev)
4137{
4138 struct drm_i915_private *dev_priv = dev->dev_private;
4139
4140 spin_lock_init(&dev_priv->gt_lock);
4141
4142 if (IS_VALLEYVIEW(dev)) {
4143 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4144 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4145 } else if (INTEL_INFO(dev)->gen >= 6) {
4146 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4147 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4148
4149 /* IVB configs may use multi-threaded forcewake */
4150 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4151 u32 ecobus;
4152
4153 /* A small trick here - if the bios hasn't configured
4154 * MT forcewake, and if the device is in RC6, then
4155 * force_wake_mt_get will not wake the device and the
4156 * ECOBUS read will return zero. Which will be
4157 * (correctly) interpreted by the test below as MT
4158 * forcewake being disabled.
4159 */
4160 mutex_lock(&dev->struct_mutex);
4161 __gen6_gt_force_wake_mt_get(dev_priv);
4162 ecobus = I915_READ_NOTRACE(ECOBUS);
4163 __gen6_gt_force_wake_mt_put(dev_priv);
4164 mutex_unlock(&dev->struct_mutex);
4165
4166 if (ecobus & FORCEWAKE_MT_ENABLE) {
4167 DRM_DEBUG_KMS("Using MT version of forcewake\n");
4168 dev_priv->gt.force_wake_get =
4169 __gen6_gt_force_wake_mt_get;
4170 dev_priv->gt.force_wake_put =
4171 __gen6_gt_force_wake_mt_put;
4172 }
4173 }
4174 }
4175}
4176
Linux kernel - Deliverables
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