projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/gen9: h/w w/a: syncing dependencies between camera and graphics
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /*
60 * WaDisableSDEUnitClockGating:skl
61 * This seems to be a pre-production w/a.
62 */
63 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
64 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
91e41d16
DL		 65
66 /* Wa4x4STCOptimizationDisable:skl */
67 I915_WRITE(CACHE_MODE_1,
68 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
da2078cd
DL		 69}
70
c921aba8
DV		 71static void i915_pineview_get_mem_freq(struct drm_device *dev)
72{
50227e1c 73 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 74 u32 tmp;
75
76 tmp = I915_READ(CLKCFG);
77
78 switch (tmp & CLKCFG_FSB_MASK) {
79 case CLKCFG_FSB_533:
80 dev_priv->fsb_freq = 533; /* 133*4 */
81 break;
82 case CLKCFG_FSB_800:
83 dev_priv->fsb_freq = 800; /* 200*4 */
84 break;
85 case CLKCFG_FSB_667:
86 dev_priv->fsb_freq = 667; /* 167*4 */
87 break;
88 case CLKCFG_FSB_400:
89 dev_priv->fsb_freq = 400; /* 100*4 */
90 break;
91 }
92
93 switch (tmp & CLKCFG_MEM_MASK) {
94 case CLKCFG_MEM_533:
95 dev_priv->mem_freq = 533;
96 break;
97 case CLKCFG_MEM_667:
98 dev_priv->mem_freq = 667;
99 break;
100 case CLKCFG_MEM_800:
101 dev_priv->mem_freq = 800;
102 break;
103 }
104
105 /* detect pineview DDR3 setting */
106 tmp = I915_READ(CSHRDDR3CTL);
107 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
108}
109
110static void i915_ironlake_get_mem_freq(struct drm_device *dev)
111{
50227e1c 112 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 113 u16 ddrpll, csipll;
114
115 ddrpll = I915_READ16(DDRMPLL1);
116 csipll = I915_READ16(CSIPLL0);
117
118 switch (ddrpll & 0xff) {
119 case 0xc:
120 dev_priv->mem_freq = 800;
121 break;
122 case 0x10:
123 dev_priv->mem_freq = 1066;
124 break;
125 case 0x14:
126 dev_priv->mem_freq = 1333;
127 break;
128 case 0x18:
129 dev_priv->mem_freq = 1600;
130 break;
131 default:
132 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
133 ddrpll & 0xff);
134 dev_priv->mem_freq = 0;
135 break;
136 }
137
20e4d407 138 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 139
140 switch (csipll & 0x3ff) {
141 case 0x00c:
142 dev_priv->fsb_freq = 3200;
143 break;
144 case 0x00e:
145 dev_priv->fsb_freq = 3733;
146 break;
147 case 0x010:
148 dev_priv->fsb_freq = 4266;
149 break;
150 case 0x012:
151 dev_priv->fsb_freq = 4800;
152 break;
153 case 0x014:
154 dev_priv->fsb_freq = 5333;
155 break;
156 case 0x016:
157 dev_priv->fsb_freq = 5866;
158 break;
159 case 0x018:
160 dev_priv->fsb_freq = 6400;
161 break;
162 default:
163 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
164 csipll & 0x3ff);
165 dev_priv->fsb_freq = 0;
166 break;
167 }
168
169 if (dev_priv->fsb_freq == 3200) {
20e4d407 170 dev_priv->ips.c_m = 0;
c921aba8 171 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 172 dev_priv->ips.c_m = 1;
c921aba8 173 } else {
20e4d407 174 dev_priv->ips.c_m = 2;
c921aba8
DV		 175 }
176}
177
b445e3b0
ED		 178static const struct cxsr_latency cxsr_latency_table[] = {
179 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
180 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
181 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
182 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
183 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
184
185 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
186 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
187 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
188 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
189 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
190
191 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
192 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
193 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
194 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
195 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
196
197 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
198 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
199 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
200 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
201 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
202
203 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
204 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
205 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
206 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
207 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
208
209 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
210 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
211 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
212 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
213 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
214};
215
63c62275 216static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 217 int is_ddr3,
218 int fsb,
219 int mem)
220{
221 const struct cxsr_latency *latency;
222 int i;
223
224 if (fsb == 0 || mem == 0)
225 return NULL;
226
227 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
228 latency = &cxsr_latency_table[i];
229 if (is_desktop == latency->is_desktop &&
230 is_ddr3 == latency->is_ddr3 &&
231 fsb == latency->fsb_freq && mem == latency->mem_freq)
232 return latency;
233 }
234
235 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
236
237 return NULL;
238}
239
5209b1f4 240void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 241{
5209b1f4
ID		 242 struct drm_device *dev = dev_priv->dev;
243 u32 val;
b445e3b0 244
5209b1f4
ID		 245 if (IS_VALLEYVIEW(dev)) {
246 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
247 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
248 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
249 } else if (IS_PINEVIEW(dev)) {
250 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
251 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
252 I915_WRITE(DSPFW3, val);
253 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
254 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
255 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
256 I915_WRITE(FW_BLC_SELF, val);
257 } else if (IS_I915GM(dev)) {
258 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
259 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
260 I915_WRITE(INSTPM, val);
261 } else {
262 return;
263 }
b445e3b0 264
5209b1f4
ID		 265 DRM_DEBUG_KMS("memory self-refresh is %s\n",
266 enable ? "enabled" : "disabled");
b445e3b0
ED		 267}
268
269/*
270 * Latency for FIFO fetches is dependent on several factors:
271 * - memory configuration (speed, channels)
272 * - chipset
273 * - current MCH state
274 * It can be fairly high in some situations, so here we assume a fairly
275 * pessimal value. It's a tradeoff between extra memory fetches (if we
276 * set this value too high, the FIFO will fetch frequently to stay full)
277 * and power consumption (set it too low to save power and we might see
278 * FIFO underruns and display "flicker").
279 *
280 * A value of 5us seems to be a good balance; safe for very low end
281 * platforms but not overly aggressive on lower latency configs.
282 */
5aef6003 283static const int pessimal_latency_ns = 5000;
b445e3b0 284
1fa61106 285static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 286{
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 uint32_t dsparb = I915_READ(DSPARB);
289 int size;
290
291 size = dsparb & 0x7f;
292 if (plane)
293 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
294
295 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
296 plane ? "B" : "A", size);
297
298 return size;
299}
300
feb56b93 301static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 302{
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 uint32_t dsparb = I915_READ(DSPARB);
305 int size;
306
307 size = dsparb & 0x1ff;
308 if (plane)
309 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
310 size >>= 1; /* Convert to cachelines */
311
312 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
313 plane ? "B" : "A", size);
314
315 return size;
316}
317
1fa61106 318static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 319{
320 struct drm_i915_private *dev_priv = dev->dev_private;
321 uint32_t dsparb = I915_READ(DSPARB);
322 int size;
323
324 size = dsparb & 0x7f;
325 size >>= 2; /* Convert to cachelines */
326
327 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
328 plane ? "B" : "A",
329 size);
330
331 return size;
332}
333
b445e3b0
ED		 334/* Pineview has different values for various configs */
335static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 336 .fifo_size = PINEVIEW_DISPLAY_FIFO,
337 .max_wm = PINEVIEW_MAX_WM,
338 .default_wm = PINEVIEW_DFT_WM,
339 .guard_size = PINEVIEW_GUARD_WM,
340 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 341};
342static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 343 .fifo_size = PINEVIEW_DISPLAY_FIFO,
344 .max_wm = PINEVIEW_MAX_WM,
345 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
346 .guard_size = PINEVIEW_GUARD_WM,
347 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 348};
349static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 350 .fifo_size = PINEVIEW_CURSOR_FIFO,
351 .max_wm = PINEVIEW_CURSOR_MAX_WM,
352 .default_wm = PINEVIEW_CURSOR_DFT_WM,
353 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
354 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 355};
356static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 357 .fifo_size = PINEVIEW_CURSOR_FIFO,
358 .max_wm = PINEVIEW_CURSOR_MAX_WM,
359 .default_wm = PINEVIEW_CURSOR_DFT_WM,
360 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
361 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 362};
363static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 364 .fifo_size = G4X_FIFO_SIZE,
365 .max_wm = G4X_MAX_WM,
366 .default_wm = G4X_MAX_WM,
367 .guard_size = 2,
368 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 369};
370static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 371 .fifo_size = I965_CURSOR_FIFO,
372 .max_wm = I965_CURSOR_MAX_WM,
373 .default_wm = I965_CURSOR_DFT_WM,
374 .guard_size = 2,
375 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 376};
377static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 378 .fifo_size = VALLEYVIEW_FIFO_SIZE,
379 .max_wm = VALLEYVIEW_MAX_WM,
380 .default_wm = VALLEYVIEW_MAX_WM,
381 .guard_size = 2,
382 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 383};
384static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 385 .fifo_size = I965_CURSOR_FIFO,
386 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
387 .default_wm = I965_CURSOR_DFT_WM,
388 .guard_size = 2,
389 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 390};
391static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 392 .fifo_size = I965_CURSOR_FIFO,
393 .max_wm = I965_CURSOR_MAX_WM,
394 .default_wm = I965_CURSOR_DFT_WM,
395 .guard_size = 2,
396 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 397};
398static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 399 .fifo_size = I945_FIFO_SIZE,
400 .max_wm = I915_MAX_WM,
401 .default_wm = 1,
402 .guard_size = 2,
403 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 404};
405static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 406 .fifo_size = I915_FIFO_SIZE,
407 .max_wm = I915_MAX_WM,
408 .default_wm = 1,
409 .guard_size = 2,
410 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 411};
9d539105 412static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 413 .fifo_size = I855GM_FIFO_SIZE,
414 .max_wm = I915_MAX_WM,
415 .default_wm = 1,
416 .guard_size = 2,
417 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 418};
9d539105
VS		 419static const struct intel_watermark_params i830_bc_wm_info = {
420 .fifo_size = I855GM_FIFO_SIZE,
421 .max_wm = I915_MAX_WM/2,
422 .default_wm = 1,
423 .guard_size = 2,
424 .cacheline_size = I830_FIFO_LINE_SIZE,
425};
feb56b93 426static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 427 .fifo_size = I830_FIFO_SIZE,
428 .max_wm = I915_MAX_WM,
429 .default_wm = 1,
430 .guard_size = 2,
431 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 432};
433
b445e3b0
ED		 434/**
435 * intel_calculate_wm - calculate watermark level
436 * @clock_in_khz: pixel clock
437 * @wm: chip FIFO params
438 * @pixel_size: display pixel size
439 * @latency_ns: memory latency for the platform
440 *
441 * Calculate the watermark level (the level at which the display plane will
442 * start fetching from memory again). Each chip has a different display
443 * FIFO size and allocation, so the caller needs to figure that out and pass
444 * in the correct intel_watermark_params structure.
445 *
446 * As the pixel clock runs, the FIFO will be drained at a rate that depends
447 * on the pixel size. When it reaches the watermark level, it'll start
448 * fetching FIFO line sized based chunks from memory until the FIFO fills
449 * past the watermark point. If the FIFO drains completely, a FIFO underrun
450 * will occur, and a display engine hang could result.
451 */
452static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
453 const struct intel_watermark_params *wm,
454 int fifo_size,
455 int pixel_size,
456 unsigned long latency_ns)
457{
458 long entries_required, wm_size;
459
460 /*
461 * Note: we need to make sure we don't overflow for various clock &
462 * latency values.
463 * clocks go from a few thousand to several hundred thousand.
464 * latency is usually a few thousand
465 */
466 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
467 1000;
468 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
469
470 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
471
472 wm_size = fifo_size - (entries_required + wm->guard_size);
473
474 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
475
476 /* Don't promote wm_size to unsigned... */
477 if (wm_size > (long)wm->max_wm)
478 wm_size = wm->max_wm;
479 if (wm_size <= 0)
480 wm_size = wm->default_wm;
d6feb196
VS		 481
482 /*
483 * Bspec seems to indicate that the value shouldn't be lower than
484 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
485 * Lets go for 8 which is the burst size since certain platforms
486 * already use a hardcoded 8 (which is what the spec says should be
487 * done).
488 */
489 if (wm_size <= 8)
490 wm_size = 8;
491
b445e3b0
ED		 492 return wm_size;
493}
494
495static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
496{
497 struct drm_crtc *crtc, *enabled = NULL;
498
70e1e0ec 499 for_each_crtc(dev, crtc) {
3490ea5d 500 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 501 if (enabled)
502 return NULL;
503 enabled = crtc;
504 }
505 }
506
507 return enabled;
508}
509
46ba614c 510static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 511{
46ba614c 512 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 513 struct drm_i915_private *dev_priv = dev->dev_private;
514 struct drm_crtc *crtc;
515 const struct cxsr_latency *latency;
516 u32 reg;
517 unsigned long wm;
518
519 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
520 dev_priv->fsb_freq, dev_priv->mem_freq);
521 if (!latency) {
522 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 523 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 524 return;
525 }
526
527 crtc = single_enabled_crtc(dev);
528 if (crtc) {
241bfc38 529 const struct drm_display_mode *adjusted_mode;
f4510a27 530 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 531 int clock;
532
6e3c9717 533 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 534 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 535
536 /* Display SR */
537 wm = intel_calculate_wm(clock, &pineview_display_wm,
538 pineview_display_wm.fifo_size,
539 pixel_size, latency->display_sr);
540 reg = I915_READ(DSPFW1);
541 reg &= ~DSPFW_SR_MASK;
542 reg |= wm << DSPFW_SR_SHIFT;
543 I915_WRITE(DSPFW1, reg);
544 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
545
546 /* cursor SR */
547 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
548 pineview_display_wm.fifo_size,
549 pixel_size, latency->cursor_sr);
550 reg = I915_READ(DSPFW3);
551 reg &= ~DSPFW_CURSOR_SR_MASK;
552 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
553 I915_WRITE(DSPFW3, reg);
554
555 /* Display HPLL off SR */
556 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
557 pineview_display_hplloff_wm.fifo_size,
558 pixel_size, latency->display_hpll_disable);
559 reg = I915_READ(DSPFW3);
560 reg &= ~DSPFW_HPLL_SR_MASK;
561 reg |= wm & DSPFW_HPLL_SR_MASK;
562 I915_WRITE(DSPFW3, reg);
563
564 /* cursor HPLL off SR */
565 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
566 pineview_display_hplloff_wm.fifo_size,
567 pixel_size, latency->cursor_hpll_disable);
568 reg = I915_READ(DSPFW3);
569 reg &= ~DSPFW_HPLL_CURSOR_MASK;
570 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
571 I915_WRITE(DSPFW3, reg);
572 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
573
5209b1f4 574 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 575 } else {
5209b1f4 576 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 577 }
578}
579
580static bool g4x_compute_wm0(struct drm_device *dev,
581 int plane,
582 const struct intel_watermark_params *display,
583 int display_latency_ns,
584 const struct intel_watermark_params *cursor,
585 int cursor_latency_ns,
586 int *plane_wm,
587 int *cursor_wm)
588{
589 struct drm_crtc *crtc;
4fe8590a 590 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 591 int htotal, hdisplay, clock, pixel_size;
592 int line_time_us, line_count;
593 int entries, tlb_miss;
594
595 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 596 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 597 *cursor_wm = cursor->guard_size;
598 *plane_wm = display->guard_size;
599 return false;
600 }
601
6e3c9717 602 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 603 clock = adjusted_mode->crtc_clock;
fec8cba3 604 htotal = adjusted_mode->crtc_htotal;
6e3c9717 605 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
f4510a27 606 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 607
608 /* Use the small buffer method to calculate plane watermark */
609 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
610 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
611 if (tlb_miss > 0)
612 entries += tlb_miss;
613 entries = DIV_ROUND_UP(entries, display->cacheline_size);
614 *plane_wm = entries + display->guard_size;
615 if (*plane_wm > (int)display->max_wm)
616 *plane_wm = display->max_wm;
617
618 /* Use the large buffer method to calculate cursor watermark */
922044c9 619 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 620 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 621 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 622 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
623 if (tlb_miss > 0)
624 entries += tlb_miss;
625 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
626 *cursor_wm = entries + cursor->guard_size;
627 if (*cursor_wm > (int)cursor->max_wm)
628 *cursor_wm = (int)cursor->max_wm;
629
630 return true;
631}
632
633/*
634 * Check the wm result.
635 *
636 * If any calculated watermark values is larger than the maximum value that
637 * can be programmed into the associated watermark register, that watermark
638 * must be disabled.
639 */
640static bool g4x_check_srwm(struct drm_device *dev,
641 int display_wm, int cursor_wm,
642 const struct intel_watermark_params *display,
643 const struct intel_watermark_params *cursor)
644{
645 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
646 display_wm, cursor_wm);
647
648 if (display_wm > display->max_wm) {
649 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
650 display_wm, display->max_wm);
651 return false;
652 }
653
654 if (cursor_wm > cursor->max_wm) {
655 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
656 cursor_wm, cursor->max_wm);
657 return false;
658 }
659
660 if (!(display_wm || cursor_wm)) {
661 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
662 return false;
663 }
664
665 return true;
666}
667
668static bool g4x_compute_srwm(struct drm_device *dev,
669 int plane,
670 int latency_ns,
671 const struct intel_watermark_params *display,
672 const struct intel_watermark_params *cursor,
673 int *display_wm, int *cursor_wm)
674{
675 struct drm_crtc *crtc;
4fe8590a 676 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 677 int hdisplay, htotal, pixel_size, clock;
678 unsigned long line_time_us;
679 int line_count, line_size;
680 int small, large;
681 int entries;
682
683 if (!latency_ns) {
684 *display_wm = *cursor_wm = 0;
685 return false;
686 }
687
688 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 689 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 690 clock = adjusted_mode->crtc_clock;
fec8cba3 691 htotal = adjusted_mode->crtc_htotal;
6e3c9717 692 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
f4510a27 693 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 694
922044c9 695 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 696 line_count = (latency_ns / line_time_us + 1000) / 1000;
697 line_size = hdisplay * pixel_size;
698
699 /* Use the minimum of the small and large buffer method for primary */
700 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
701 large = line_count * line_size;
702
703 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
704 *display_wm = entries + display->guard_size;
705
706 /* calculate the self-refresh watermark for display cursor */
7bb836dd 707 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 708 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
709 *cursor_wm = entries + cursor->guard_size;
710
711 return g4x_check_srwm(dev,
712 *display_wm, *cursor_wm,
713 display, cursor);
714}
715
0948c265
GB		 716static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
717 int pixel_size,
718 int *prec_mult,
719 int *drain_latency)
b445e3b0 720{
5e56ba45 721 struct drm_device *dev = crtc->dev;
b445e3b0 722 int entries;
6e3c9717 723 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
b445e3b0 724
0948c265 725 if (WARN(clock == 0, "Pixel clock is zero!\n"))
b445e3b0
ED		 726 return false;
727
0948c265
GB		 728 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
729 return false;
b445e3b0 730
a398e9c7 731 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
5e56ba45
RV		 732 if (IS_CHERRYVIEW(dev))
733 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
734 DRAIN_LATENCY_PRECISION_16;
735 else
736 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
737 DRAIN_LATENCY_PRECISION_32;
0948c265 738 *drain_latency = (64 * (*prec_mult) * 4) / entries;
b445e3b0 739
a398e9c7
GB		 740 if (*drain_latency > DRAIN_LATENCY_MASK)
741 *drain_latency = DRAIN_LATENCY_MASK;
b445e3b0
ED		 742
743 return true;
744}
745
746/*
747 * Update drain latency registers of memory arbiter
748 *
749 * Valleyview SoC has a new memory arbiter and needs drain latency registers
750 * to be programmed. Each plane has a drain latency multiplier and a drain
751 * latency value.
752 */
753
41aad816 754static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 755{
5e56ba45
RV		 756 struct drm_device *dev = crtc->dev;
757 struct drm_i915_private *dev_priv = dev->dev_private;
0948c265
GB		 758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759 int pixel_size;
760 int drain_latency;
761 enum pipe pipe = intel_crtc->pipe;
762 int plane_prec, prec_mult, plane_dl;
5e56ba45
RV		 763 const int high_precision = IS_CHERRYVIEW(dev) ?
764 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
b445e3b0 765
5e56ba45
RV		 766 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
767 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
0948c265
GB		 768 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
769
770 if (!intel_crtc_active(crtc)) {
771 I915_WRITE(VLV_DDL(pipe), plane_dl);
772 return;
773 }
b445e3b0 774
0948c265
GB		 775 /* Primary plane Drain Latency */
776 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
777 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
5e56ba45
RV		 778 plane_prec = (prec_mult == high_precision) ?
779 DDL_PLANE_PRECISION_HIGH :
780 DDL_PLANE_PRECISION_LOW;
0948c265 781 plane_dl |= plane_prec | drain_latency;
b445e3b0
ED		 782 }
783
0948c265
GB		 784 /* Cursor Drain Latency
785 * BPP is always 4 for cursor
786 */
787 pixel_size = 4;
b445e3b0 788
0948c265
GB		 789 /* Program cursor DL only if it is enabled */
790 if (intel_crtc->cursor_base &&
791 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
5e56ba45
RV		 792 plane_prec = (prec_mult == high_precision) ?
793 DDL_CURSOR_PRECISION_HIGH :
794 DDL_CURSOR_PRECISION_LOW;
0948c265 795 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
b445e3b0 796 }
0948c265
GB		 797
798 I915_WRITE(VLV_DDL(pipe), plane_dl);
b445e3b0
ED		 799}
800
801#define single_plane_enabled(mask) is_power_of_2(mask)
802
46ba614c 803static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 804{
46ba614c 805 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 806 static const int sr_latency_ns = 12000;
807 struct drm_i915_private *dev_priv = dev->dev_private;
808 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
809 int plane_sr, cursor_sr;
af6c4575 810 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 811 unsigned int enabled = 0;
9858425c 812 bool cxsr_enabled;
b445e3b0 813
41aad816 814 vlv_update_drain_latency(crtc);
b445e3b0 815
51cea1f4 816 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 817 &valleyview_wm_info, pessimal_latency_ns,
818 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 819 &planea_wm, &cursora_wm))
51cea1f4 820 enabled |= 1 << PIPE_A;
b445e3b0 821
51cea1f4 822 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 823 &valleyview_wm_info, pessimal_latency_ns,
824 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 825 &planeb_wm, &cursorb_wm))
51cea1f4 826 enabled |= 1 << PIPE_B;
b445e3b0 827
b445e3b0
ED		 828 if (single_plane_enabled(enabled) &&
829 g4x_compute_srwm(dev, ffs(enabled) - 1,
830 sr_latency_ns,
831 &valleyview_wm_info,
832 &valleyview_cursor_wm_info,
af6c4575
CW		 833 &plane_sr, &ignore_cursor_sr) &&
834 g4x_compute_srwm(dev, ffs(enabled) - 1,
835 2*sr_latency_ns,
836 &valleyview_wm_info,
837 &valleyview_cursor_wm_info,
52bd02d8 838 &ignore_plane_sr, &cursor_sr)) {
9858425c 839 cxsr_enabled = true;
52bd02d8 840 } else {
9858425c 841 cxsr_enabled = false;
5209b1f4 842 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 843 plane_sr = cursor_sr = 0;
844 }
b445e3b0 845
a5043453
VS		 846 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
847 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 848 planea_wm, cursora_wm,
849 planeb_wm, cursorb_wm,
850 plane_sr, cursor_sr);
851
852 I915_WRITE(DSPFW1,
853 (plane_sr << DSPFW_SR_SHIFT) |
854 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
855 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 856 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 857 I915_WRITE(DSPFW2,
8c919b28 858 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 859 (cursora_wm << DSPFW_CURSORA_SHIFT));
860 I915_WRITE(DSPFW3,
8c919b28
CW		 861 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
862 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 863
864 if (cxsr_enabled)
865 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 866}
867
3c2777fd
VS		 868static void cherryview_update_wm(struct drm_crtc *crtc)
869{
870 struct drm_device *dev = crtc->dev;
871 static const int sr_latency_ns = 12000;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 int planea_wm, planeb_wm, planec_wm;
874 int cursora_wm, cursorb_wm, cursorc_wm;
875 int plane_sr, cursor_sr;
876 int ignore_plane_sr, ignore_cursor_sr;
877 unsigned int enabled = 0;
878 bool cxsr_enabled;
879
880 vlv_update_drain_latency(crtc);
881
882 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 883 &valleyview_wm_info, pessimal_latency_ns,
884 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 885 &planea_wm, &cursora_wm))
886 enabled |= 1 << PIPE_A;
887
888 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 889 &valleyview_wm_info, pessimal_latency_ns,
890 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 891 &planeb_wm, &cursorb_wm))
892 enabled |= 1 << PIPE_B;
893
894 if (g4x_compute_wm0(dev, PIPE_C,
5aef6003
CW		 895 &valleyview_wm_info, pessimal_latency_ns,
896 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 897 &planec_wm, &cursorc_wm))
898 enabled |= 1 << PIPE_C;
899
900 if (single_plane_enabled(enabled) &&
901 g4x_compute_srwm(dev, ffs(enabled) - 1,
902 sr_latency_ns,
903 &valleyview_wm_info,
904 &valleyview_cursor_wm_info,
905 &plane_sr, &ignore_cursor_sr) &&
906 g4x_compute_srwm(dev, ffs(enabled) - 1,
907 2*sr_latency_ns,
908 &valleyview_wm_info,
909 &valleyview_cursor_wm_info,
910 &ignore_plane_sr, &cursor_sr)) {
911 cxsr_enabled = true;
912 } else {
913 cxsr_enabled = false;
914 intel_set_memory_cxsr(dev_priv, false);
915 plane_sr = cursor_sr = 0;
916 }
917
918 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
919 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
920 "SR: plane=%d, cursor=%d\n",
921 planea_wm, cursora_wm,
922 planeb_wm, cursorb_wm,
923 planec_wm, cursorc_wm,
924 plane_sr, cursor_sr);
925
926 I915_WRITE(DSPFW1,
927 (plane_sr << DSPFW_SR_SHIFT) |
928 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
929 (planeb_wm << DSPFW_PLANEB_SHIFT) |
930 (planea_wm << DSPFW_PLANEA_SHIFT));
931 I915_WRITE(DSPFW2,
932 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
933 (cursora_wm << DSPFW_CURSORA_SHIFT));
934 I915_WRITE(DSPFW3,
935 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
936 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
937 I915_WRITE(DSPFW9_CHV,
938 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
939 DSPFW_CURSORC_MASK)) |
940 (planec_wm << DSPFW_PLANEC_SHIFT) |
941 (cursorc_wm << DSPFW_CURSORC_SHIFT));
942
943 if (cxsr_enabled)
944 intel_set_memory_cxsr(dev_priv, true);
945}
946
01e184cc
GB		 947static void valleyview_update_sprite_wm(struct drm_plane *plane,
948 struct drm_crtc *crtc,
949 uint32_t sprite_width,
950 uint32_t sprite_height,
951 int pixel_size,
952 bool enabled, bool scaled)
953{
954 struct drm_device *dev = crtc->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 int pipe = to_intel_plane(plane)->pipe;
957 int sprite = to_intel_plane(plane)->plane;
958 int drain_latency;
959 int plane_prec;
960 int sprite_dl;
961 int prec_mult;
5e56ba45
RV		 962 const int high_precision = IS_CHERRYVIEW(dev) ?
963 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
01e184cc 964
5e56ba45 965 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
01e184cc
GB		 966 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
967
968 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
969 &drain_latency)) {
5e56ba45
RV		 970 plane_prec = (prec_mult == high_precision) ?
971 DDL_SPRITE_PRECISION_HIGH(sprite) :
972 DDL_SPRITE_PRECISION_LOW(sprite);
01e184cc
GB		 973 sprite_dl |= plane_prec |
974 (drain_latency << DDL_SPRITE_SHIFT(sprite));
975 }
976
977 I915_WRITE(VLV_DDL(pipe), sprite_dl);
978}
979
46ba614c 980static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 981{
46ba614c 982 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 983 static const int sr_latency_ns = 12000;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
986 int plane_sr, cursor_sr;
987 unsigned int enabled = 0;
9858425c 988 bool cxsr_enabled;
b445e3b0 989
51cea1f4 990 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 991 &g4x_wm_info, pessimal_latency_ns,
992 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 993 &planea_wm, &cursora_wm))
51cea1f4 994 enabled |= 1 << PIPE_A;
b445e3b0 995
51cea1f4 996 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 997 &g4x_wm_info, pessimal_latency_ns,
998 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 999 &planeb_wm, &cursorb_wm))
51cea1f4 1000 enabled |= 1 << PIPE_B;
b445e3b0 1001
b445e3b0
ED		 1002 if (single_plane_enabled(enabled) &&
1003 g4x_compute_srwm(dev, ffs(enabled) - 1,
1004 sr_latency_ns,
1005 &g4x_wm_info,
1006 &g4x_cursor_wm_info,
52bd02d8 1007 &plane_sr, &cursor_sr)) {
9858425c 1008 cxsr_enabled = true;
52bd02d8 1009 } else {
9858425c 1010 cxsr_enabled = false;
5209b1f4 1011 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1012 plane_sr = cursor_sr = 0;
1013 }
b445e3b0 1014
a5043453
VS		 1015 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1016 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1017 planea_wm, cursora_wm,
1018 planeb_wm, cursorb_wm,
1019 plane_sr, cursor_sr);
1020
1021 I915_WRITE(DSPFW1,
1022 (plane_sr << DSPFW_SR_SHIFT) |
1023 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1024 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1025 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1026 I915_WRITE(DSPFW2,
8c919b28 1027 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1028 (cursora_wm << DSPFW_CURSORA_SHIFT));
1029 /* HPLL off in SR has some issues on G4x... disable it */
1030 I915_WRITE(DSPFW3,
8c919b28 1031 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1032 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1033
1034 if (cxsr_enabled)
1035 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1036}
1037
46ba614c 1038static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1039{
46ba614c 1040 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 struct drm_crtc *crtc;
1043 int srwm = 1;
1044 int cursor_sr = 16;
9858425c 1045 bool cxsr_enabled;
b445e3b0
ED		 1046
1047 /* Calc sr entries for one plane configs */
1048 crtc = single_enabled_crtc(dev);
1049 if (crtc) {
1050 /* self-refresh has much higher latency */
1051 static const int sr_latency_ns = 12000;
4fe8590a 1052 const struct drm_display_mode *adjusted_mode =
6e3c9717 1053 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1054 int clock = adjusted_mode->crtc_clock;
fec8cba3 1055 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1056 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
f4510a27 1057 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1058 unsigned long line_time_us;
1059 int entries;
1060
922044c9 1061 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1062
1063 /* Use ns/us then divide to preserve precision */
1064 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1065 pixel_size * hdisplay;
1066 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1067 srwm = I965_FIFO_SIZE - entries;
1068 if (srwm < 0)
1069 srwm = 1;
1070 srwm &= 0x1ff;
1071 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1072 entries, srwm);
1073
1074 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1075 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1076 entries = DIV_ROUND_UP(entries,
1077 i965_cursor_wm_info.cacheline_size);
1078 cursor_sr = i965_cursor_wm_info.fifo_size -
1079 (entries + i965_cursor_wm_info.guard_size);
1080
1081 if (cursor_sr > i965_cursor_wm_info.max_wm)
1082 cursor_sr = i965_cursor_wm_info.max_wm;
1083
1084 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1085 "cursor %d\n", srwm, cursor_sr);
1086
9858425c 1087 cxsr_enabled = true;
b445e3b0 1088 } else {
9858425c 1089 cxsr_enabled = false;
b445e3b0 1090 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1091 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1092 }
1093
1094 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1095 srwm);
1096
1097 /* 965 has limitations... */
1098 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1099 (8 << DSPFW_CURSORB_SHIFT) |
1100 (8 << DSPFW_PLANEB_SHIFT) |
1101 (8 << DSPFW_PLANEA_SHIFT));
1102 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1103 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1104 /* update cursor SR watermark */
1105 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1106
1107 if (cxsr_enabled)
1108 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1109}
1110
46ba614c 1111static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1112{
46ba614c 1113 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 const struct intel_watermark_params *wm_info;
1116 uint32_t fwater_lo;
1117 uint32_t fwater_hi;
1118 int cwm, srwm = 1;
1119 int fifo_size;
1120 int planea_wm, planeb_wm;
1121 struct drm_crtc *crtc, *enabled = NULL;
1122
1123 if (IS_I945GM(dev))
1124 wm_info = &i945_wm_info;
1125 else if (!IS_GEN2(dev))
1126 wm_info = &i915_wm_info;
1127 else
9d539105 1128 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1129
1130 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1131 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1132 if (intel_crtc_active(crtc)) {
241bfc38 1133 const struct drm_display_mode *adjusted_mode;
f4510a27 1134 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1135 if (IS_GEN2(dev))
1136 cpp = 4;
1137
6e3c9717 1138 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1139 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1140 wm_info, fifo_size, cpp,
5aef6003 1141 pessimal_latency_ns);
b445e3b0 1142 enabled = crtc;
9d539105 1143 } else {
b445e3b0 1144 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1145 if (planea_wm > (long)wm_info->max_wm)
1146 planea_wm = wm_info->max_wm;
1147 }
1148
1149 if (IS_GEN2(dev))
1150 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1151
1152 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1153 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1154 if (intel_crtc_active(crtc)) {
241bfc38 1155 const struct drm_display_mode *adjusted_mode;
f4510a27 1156 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1157 if (IS_GEN2(dev))
1158 cpp = 4;
1159
6e3c9717 1160 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1161 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1162 wm_info, fifo_size, cpp,
5aef6003 1163 pessimal_latency_ns);
b445e3b0
ED		 1164 if (enabled == NULL)
1165 enabled = crtc;
1166 else
1167 enabled = NULL;
9d539105 1168 } else {
b445e3b0 1169 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1170 if (planeb_wm > (long)wm_info->max_wm)
1171 planeb_wm = wm_info->max_wm;
1172 }
b445e3b0
ED		 1173
1174 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1175
2ab1bc9d 1176 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1177 struct drm_i915_gem_object *obj;
2ab1bc9d 1178
2ff8fde1 1179 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1180
1181 /* self-refresh seems busted with untiled */
2ff8fde1 1182 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1183 enabled = NULL;
1184 }
1185
b445e3b0
ED		 1186 /*
1187 * Overlay gets an aggressive default since video jitter is bad.
1188 */
1189 cwm = 2;
1190
1191 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1192 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1193
1194 /* Calc sr entries for one plane configs */
1195 if (HAS_FW_BLC(dev) && enabled) {
1196 /* self-refresh has much higher latency */
1197 static const int sr_latency_ns = 6000;
4fe8590a 1198 const struct drm_display_mode *adjusted_mode =
6e3c9717 1199 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1200 int clock = adjusted_mode->crtc_clock;
fec8cba3 1201 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1202 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
f4510a27 1203 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1204 unsigned long line_time_us;
1205 int entries;
1206
922044c9 1207 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1208
1209 /* Use ns/us then divide to preserve precision */
1210 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1211 pixel_size * hdisplay;
1212 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1213 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1214 srwm = wm_info->fifo_size - entries;
1215 if (srwm < 0)
1216 srwm = 1;
1217
1218 if (IS_I945G(dev) || IS_I945GM(dev))
1219 I915_WRITE(FW_BLC_SELF,
1220 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1221 else if (IS_I915GM(dev))
1222 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1223 }
1224
1225 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1226 planea_wm, planeb_wm, cwm, srwm);
1227
1228 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1229 fwater_hi = (cwm & 0x1f);
1230
1231 /* Set request length to 8 cachelines per fetch */
1232 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1233 fwater_hi = fwater_hi | (1 << 8);
1234
1235 I915_WRITE(FW_BLC, fwater_lo);
1236 I915_WRITE(FW_BLC2, fwater_hi);
1237
5209b1f4
ID		 1238 if (enabled)
1239 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1240}
1241
feb56b93 1242static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1243{
46ba614c 1244 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 struct drm_crtc *crtc;
241bfc38 1247 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1248 uint32_t fwater_lo;
1249 int planea_wm;
1250
1251 crtc = single_enabled_crtc(dev);
1252 if (crtc == NULL)
1253 return;
1254
6e3c9717 1255 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1256 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1257 &i845_wm_info,
b445e3b0 1258 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1259 4, pessimal_latency_ns);
b445e3b0
ED		 1260 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1261 fwater_lo |= (3<<8) | planea_wm;
1262
1263 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1264
1265 I915_WRITE(FW_BLC, fwater_lo);
1266}
1267
3658729a
VS		 1268static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1269 struct drm_crtc *crtc)
801bcfff
PZ		 1270{
1271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1272 uint32_t pixel_rate;
801bcfff 1273
6e3c9717 1274 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1275
1276 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1277 * adjust the pixel_rate here. */
1278
6e3c9717 1279 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1280 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1281 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1282
6e3c9717
ACO		 1283 pipe_w = intel_crtc->config->pipe_src_w;
1284 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1285 pfit_w = (pfit_size >> 16) & 0xFFFF;
1286 pfit_h = pfit_size & 0xFFFF;
1287 if (pipe_w < pfit_w)
1288 pipe_w = pfit_w;
1289 if (pipe_h < pfit_h)
1290 pipe_h = pfit_h;
1291
1292 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1293 pfit_w * pfit_h);
1294 }
1295
1296 return pixel_rate;
1297}
1298
37126462 1299/* latency must be in 0.1us units. */
23297044 1300static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1301 uint32_t latency)
1302{
1303 uint64_t ret;
1304
3312ba65
VS		 1305 if (WARN(latency == 0, "Latency value missing\n"))
1306 return UINT_MAX;
1307
801bcfff
PZ		 1308 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1309 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1310
1311 return ret;
1312}
1313
37126462 1314/* latency must be in 0.1us units. */
23297044 1315static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1316 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1317 uint32_t latency)
1318{
1319 uint32_t ret;
1320
3312ba65
VS		 1321 if (WARN(latency == 0, "Latency value missing\n"))
1322 return UINT_MAX;
1323
801bcfff
PZ		 1324 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1325 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1326 ret = DIV_ROUND_UP(ret, 64) + 2;
1327 return ret;
1328}
1329
23297044 1330static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1331 uint8_t bytes_per_pixel)
1332{
1333 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1334}
1335
2ac96d2a
PB		 1336struct skl_pipe_wm_parameters {
1337 bool active;
1338 uint32_t pipe_htotal;
1339 uint32_t pixel_rate; /* in KHz */
1340 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1341 struct intel_plane_wm_parameters cursor;
1342};
1343
820c1980 1344struct ilk_pipe_wm_parameters {
801bcfff 1345 bool active;
801bcfff
PZ		 1346 uint32_t pipe_htotal;
1347 uint32_t pixel_rate;
c35426d2
VS		 1348 struct intel_plane_wm_parameters pri;
1349 struct intel_plane_wm_parameters spr;
1350 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1351};
1352
820c1980 1353struct ilk_wm_maximums {
cca32e9a
PZ		 1354 uint16_t pri;
1355 uint16_t spr;
1356 uint16_t cur;
1357 uint16_t fbc;
1358};
1359
240264f4
VS		 1360/* used in computing the new watermarks state */
1361struct intel_wm_config {
1362 unsigned int num_pipes_active;
1363 bool sprites_enabled;
1364 bool sprites_scaled;
240264f4
VS		 1365};
1366
37126462
VS		 1367/*
1368 * For both WM_PIPE and WM_LP.
1369 * mem_value must be in 0.1us units.
1370 */
820c1980 1371static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1372 uint32_t mem_value,
1373 bool is_lp)
801bcfff 1374{
cca32e9a
PZ		 1375 uint32_t method1, method2;
1376
c35426d2 1377 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1378 return 0;
1379
23297044 1380 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1381 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1382 mem_value);
1383
1384 if (!is_lp)
1385 return method1;
1386
23297044 1387 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1388 params->pipe_htotal,
c35426d2
VS		 1389 params->pri.horiz_pixels,
1390 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1391 mem_value);
1392
1393 return min(method1, method2);
801bcfff
PZ		 1394}
1395
37126462
VS		 1396/*
1397 * For both WM_PIPE and WM_LP.
1398 * mem_value must be in 0.1us units.
1399 */
820c1980 1400static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1401 uint32_t mem_value)
1402{
1403 uint32_t method1, method2;
1404
c35426d2 1405 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1406 return 0;
1407
23297044 1408 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1409 params->spr.bytes_per_pixel,
801bcfff 1410 mem_value);
23297044 1411 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1412 params->pipe_htotal,
c35426d2
VS		 1413 params->spr.horiz_pixels,
1414 params->spr.bytes_per_pixel,
801bcfff
PZ		 1415 mem_value);
1416 return min(method1, method2);
1417}
1418
37126462
VS		 1419/*
1420 * For both WM_PIPE and WM_LP.
1421 * mem_value must be in 0.1us units.
1422 */
820c1980 1423static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1424 uint32_t mem_value)
1425{
c35426d2 1426 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1427 return 0;
1428
23297044 1429 return ilk_wm_method2(params->pixel_rate,
801bcfff 1430 params->pipe_htotal,
c35426d2
VS		 1431 params->cur.horiz_pixels,
1432 params->cur.bytes_per_pixel,
801bcfff
PZ		 1433 mem_value);
1434}
1435
cca32e9a 1436/* Only for WM_LP. */
820c1980 1437static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1438 uint32_t pri_val)
cca32e9a 1439{
c35426d2 1440 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1441 return 0;
1442
23297044 1443 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1444 params->pri.horiz_pixels,
1445 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1446}
1447
158ae64f
VS		 1448static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1449{
416f4727
VS		 1450 if (INTEL_INFO(dev)->gen >= 8)
1451 return 3072;
1452 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1453 return 768;
1454 else
1455 return 512;
1456}
1457
4e975081
VS		 1458static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1459 int level, bool is_sprite)
1460{
1461 if (INTEL_INFO(dev)->gen >= 8)
1462 /* BDW primary/sprite plane watermarks */
1463 return level == 0 ? 255 : 2047;
1464 else if (INTEL_INFO(dev)->gen >= 7)
1465 /* IVB/HSW primary/sprite plane watermarks */
1466 return level == 0 ? 127 : 1023;
1467 else if (!is_sprite)
1468 /* ILK/SNB primary plane watermarks */
1469 return level == 0 ? 127 : 511;
1470 else
1471 /* ILK/SNB sprite plane watermarks */
1472 return level == 0 ? 63 : 255;
1473}
1474
1475static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1476 int level)
1477{
1478 if (INTEL_INFO(dev)->gen >= 7)
1479 return level == 0 ? 63 : 255;
1480 else
1481 return level == 0 ? 31 : 63;
1482}
1483
1484static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1485{
1486 if (INTEL_INFO(dev)->gen >= 8)
1487 return 31;
1488 else
1489 return 15;
1490}
1491
158ae64f
VS		 1492/* Calculate the maximum primary/sprite plane watermark */
1493static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1494 int level,
240264f4 1495 const struct intel_wm_config *config,
158ae64f
VS		 1496 enum intel_ddb_partitioning ddb_partitioning,
1497 bool is_sprite)
1498{
1499 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1500
1501 /* if sprites aren't enabled, sprites get nothing */
240264f4 1502 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1503 return 0;
1504
1505 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1506 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1507 fifo_size /= INTEL_INFO(dev)->num_pipes;
1508
1509 /*
1510 * For some reason the non self refresh
1511 * FIFO size is only half of the self
1512 * refresh FIFO size on ILK/SNB.
1513 */
1514 if (INTEL_INFO(dev)->gen <= 6)
1515 fifo_size /= 2;
1516 }
1517
240264f4 1518 if (config->sprites_enabled) {
158ae64f
VS		 1519 /* level 0 is always calculated with 1:1 split */
1520 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1521 if (is_sprite)
1522 fifo_size *= 5;
1523 fifo_size /= 6;
1524 } else {
1525 fifo_size /= 2;
1526 }
1527 }
1528
1529 /* clamp to max that the registers can hold */
4e975081 1530 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1531}
1532
1533/* Calculate the maximum cursor plane watermark */
1534static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1535 int level,
1536 const struct intel_wm_config *config)
158ae64f
VS		 1537{
1538 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1539 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1540 return 64;
1541
1542 /* otherwise just report max that registers can hold */
4e975081 1543 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1544}
1545
d34ff9c6 1546static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1547 int level,
1548 const struct intel_wm_config *config,
1549 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1550 struct ilk_wm_maximums *max)
158ae64f 1551{
240264f4
VS		 1552 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1553 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1554 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1555 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1556}
1557
a3cb4048
VS		 1558static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1559 int level,
1560 struct ilk_wm_maximums *max)
1561{
1562 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1563 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1564 max->cur = ilk_cursor_wm_reg_max(dev, level);
1565 max->fbc = ilk_fbc_wm_reg_max(dev);
1566}
1567
d9395655 1568static bool ilk_validate_wm_level(int level,
820c1980 1569 const struct ilk_wm_maximums *max,
d9395655 1570 struct intel_wm_level *result)
a9786a11
VS		 1571{
1572 bool ret;
1573
1574 /* already determined to be invalid? */
1575 if (!result->enable)
1576 return false;
1577
1578 result->enable = result->pri_val <= max->pri &&
1579 result->spr_val <= max->spr &&
1580 result->cur_val <= max->cur;
1581
1582 ret = result->enable;
1583
1584 /*
1585 * HACK until we can pre-compute everything,
1586 * and thus fail gracefully if LP0 watermarks
1587 * are exceeded...
1588 */
1589 if (level == 0 && !result->enable) {
1590 if (result->pri_val > max->pri)
1591 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1592 level, result->pri_val, max->pri);
1593 if (result->spr_val > max->spr)
1594 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1595 level, result->spr_val, max->spr);
1596 if (result->cur_val > max->cur)
1597 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1598 level, result->cur_val, max->cur);
1599
1600 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1601 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1602 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1603 result->enable = true;
1604 }
1605
a9786a11
VS		 1606 return ret;
1607}
1608
d34ff9c6 1609static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1610 int level,
820c1980 1611 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1612 struct intel_wm_level *result)
6f5ddd17
VS		 1613{
1614 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1615 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1616 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1617
1618 /* WM1+ latency values stored in 0.5us units */
1619 if (level > 0) {
1620 pri_latency *= 5;
1621 spr_latency *= 5;
1622 cur_latency *= 5;
1623 }
1624
1625 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1626 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1627 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1628 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1629 result->enable = true;
1630}
1631
801bcfff
PZ		 1632static uint32_t
1633hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1634{
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1637 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1638 u32 linetime, ips_linetime;
1f8eeabf 1639
801bcfff
PZ		 1640 if (!intel_crtc_active(crtc))
1641 return 0;
1011d8c4 1642
1f8eeabf
ED		 1643 /* The WM are computed with base on how long it takes to fill a single
1644 * row at the given clock rate, multiplied by 8.
1645 * */
fec8cba3
JB		 1646 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1647 mode->crtc_clock);
1648 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1649 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1650
801bcfff
PZ		 1651 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1652 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1653}
1654
2af30a5c 1655static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1656{
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658
2af30a5c
PB		 1659 if (IS_GEN9(dev)) {
1660 uint32_t val;
4f947386 1661 int ret, i;
367294be 1662 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1663
1664 /* read the first set of memory latencies[0:3] */
1665 val = 0; /* data0 to be programmed to 0 for first set */
1666 mutex_lock(&dev_priv->rps.hw_lock);
1667 ret = sandybridge_pcode_read(dev_priv,
1668 GEN9_PCODE_READ_MEM_LATENCY,
1669 &val);
1670 mutex_unlock(&dev_priv->rps.hw_lock);
1671
1672 if (ret) {
1673 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1674 return;
1675 }
1676
1677 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1678 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1679 GEN9_MEM_LATENCY_LEVEL_MASK;
1680 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1681 GEN9_MEM_LATENCY_LEVEL_MASK;
1682 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1683 GEN9_MEM_LATENCY_LEVEL_MASK;
1684
1685 /* read the second set of memory latencies[4:7] */
1686 val = 1; /* data0 to be programmed to 1 for second set */
1687 mutex_lock(&dev_priv->rps.hw_lock);
1688 ret = sandybridge_pcode_read(dev_priv,
1689 GEN9_PCODE_READ_MEM_LATENCY,
1690 &val);
1691 mutex_unlock(&dev_priv->rps.hw_lock);
1692 if (ret) {
1693 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1694 return;
1695 }
1696
1697 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1698 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1699 GEN9_MEM_LATENCY_LEVEL_MASK;
1700 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1701 GEN9_MEM_LATENCY_LEVEL_MASK;
1702 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1703 GEN9_MEM_LATENCY_LEVEL_MASK;
1704
367294be
VK		 1705 /*
1706 * punit doesn't take into account the read latency so we need
1707 * to add 2us to the various latency levels we retrieve from
1708 * the punit.
1709 * - W0 is a bit special in that it's the only level that
1710 * can't be disabled if we want to have display working, so
1711 * we always add 2us there.
1712 * - For levels >=1, punit returns 0us latency when they are
1713 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1714 *
1715 * Additionally, if a level n (n > 1) has a 0us latency, all
1716 * levels m (m >= n) need to be disabled. We make sure to
1717 * sanitize the values out of the punit to satisfy this
1718 * requirement.
367294be
VK		 1719 */
1720 wm[0] += 2;
1721 for (level = 1; level <= max_level; level++)
1722 if (wm[level] != 0)
1723 wm[level] += 2;
4f947386
VK		 1724 else {
1725 for (i = level + 1; i <= max_level; i++)
1726 wm[i] = 0;
367294be 1727
4f947386
VK		 1728 break;
1729 }
2af30a5c 1730 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1731 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1732
1733 wm[0] = (sskpd >> 56) & 0xFF;
1734 if (wm[0] == 0)
1735 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1736 wm[1] = (sskpd >> 4) & 0xFF;
1737 wm[2] = (sskpd >> 12) & 0xFF;
1738 wm[3] = (sskpd >> 20) & 0x1FF;
1739 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1740 } else if (INTEL_INFO(dev)->gen >= 6) {
1741 uint32_t sskpd = I915_READ(MCH_SSKPD);
1742
1743 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1744 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1745 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1746 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1747 } else if (INTEL_INFO(dev)->gen >= 5) {
1748 uint32_t mltr = I915_READ(MLTR_ILK);
1749
1750 /* ILK primary LP0 latency is 700 ns */
1751 wm[0] = 7;
1752 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1753 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1754 }
1755}
1756
53615a5e
VS		 1757static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1758{
1759 /* ILK sprite LP0 latency is 1300 ns */
1760 if (INTEL_INFO(dev)->gen == 5)
1761 wm[0] = 13;
1762}
1763
1764static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1765{
1766 /* ILK cursor LP0 latency is 1300 ns */
1767 if (INTEL_INFO(dev)->gen == 5)
1768 wm[0] = 13;
1769
1770 /* WaDoubleCursorLP3Latency:ivb */
1771 if (IS_IVYBRIDGE(dev))
1772 wm[3] *= 2;
1773}
1774
546c81fd 1775int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1776{
26ec971e 1777 /* how many WM levels are we expecting */
2af30a5c
PB		 1778 if (IS_GEN9(dev))
1779 return 7;
1780 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1781 return 4;
26ec971e 1782 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1783 return 3;
26ec971e 1784 else
ad0d6dc4
VS		 1785 return 2;
1786}
7526ed79 1787
ad0d6dc4
VS		 1788static void intel_print_wm_latency(struct drm_device *dev,
1789 const char *name,
2af30a5c 1790 const uint16_t wm[8])
ad0d6dc4
VS		 1791{
1792 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1793
1794 for (level = 0; level <= max_level; level++) {
1795 unsigned int latency = wm[level];
1796
1797 if (latency == 0) {
1798 DRM_ERROR("%s WM%d latency not provided\n",
1799 name, level);
1800 continue;
1801 }
1802
2af30a5c
PB		 1803 /*
1804 * - latencies are in us on gen9.
1805 * - before then, WM1+ latency values are in 0.5us units
1806 */
1807 if (IS_GEN9(dev))
1808 latency *= 10;
1809 else if (level > 0)
26ec971e
VS		 1810 latency *= 5;
1811
1812 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1813 name, level, wm[level],
1814 latency / 10, latency % 10);
1815 }
1816}
1817
e95a2f75
VS		 1818static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1819 uint16_t wm[5], uint16_t min)
1820{
1821 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1822
1823 if (wm[0] >= min)
1824 return false;
1825
1826 wm[0] = max(wm[0], min);
1827 for (level = 1; level <= max_level; level++)
1828 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1829
1830 return true;
1831}
1832
1833static void snb_wm_latency_quirk(struct drm_device *dev)
1834{
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 bool changed;
1837
1838 /*
1839 * The BIOS provided WM memory latency values are often
1840 * inadequate for high resolution displays. Adjust them.
1841 */
1842 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1843 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1844 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1845
1846 if (!changed)
1847 return;
1848
1849 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1850 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1851 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1852 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
1853}
1854
fa50ad61 1855static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 1856{
1857 struct drm_i915_private *dev_priv = dev->dev_private;
1858
1859 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
1860
1861 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
1862 sizeof(dev_priv->wm.pri_latency));
1863 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
1864 sizeof(dev_priv->wm.pri_latency));
1865
1866 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
1867 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 1868
1869 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1870 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1871 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 1872
1873 if (IS_GEN6(dev))
1874 snb_wm_latency_quirk(dev);
53615a5e
VS		 1875}
1876
2af30a5c
PB		 1877static void skl_setup_wm_latency(struct drm_device *dev)
1878{
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880
1881 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
1882 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
1883}
1884
820c1980 1885static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 1886 struct ilk_pipe_wm_parameters *p)
1011d8c4 1887{
7c4a395f
VS		 1888 struct drm_device *dev = crtc->dev;
1889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1890 enum pipe pipe = intel_crtc->pipe;
7c4a395f 1891 struct drm_plane *plane;
1011d8c4 1892
2a44b76b
VS		 1893 if (!intel_crtc_active(crtc))
1894 return;
801bcfff 1895
2a44b76b 1896 p->active = true;
6e3c9717 1897 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b
VS		 1898 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
1899 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
1900 p->cur.bytes_per_pixel = 4;
6e3c9717 1901 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2a44b76b
VS		 1902 p->cur.horiz_pixels = intel_crtc->cursor_width;
1903 /* TODO: for now, assume primary and cursor planes are always enabled. */
1904 p->pri.enabled = true;
1905 p->cur.enabled = true;
7c4a395f 1906
af2b653b 1907 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 1908 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 1909
2a44b76b 1910 if (intel_plane->pipe == pipe) {
7c4a395f 1911 p->spr = intel_plane->wm;
2a44b76b
VS		 1912 break;
1913 }
1914 }
1915}
1916
1917static void ilk_compute_wm_config(struct drm_device *dev,
1918 struct intel_wm_config *config)
1919{
1920 struct intel_crtc *intel_crtc;
1921
1922 /* Compute the currently _active_ config */
d3fcc808 1923 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 1924 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 1925
2a44b76b
VS		 1926 if (!wm->pipe_enabled)
1927 continue;
cca32e9a 1928
2a44b76b
VS		 1929 config->sprites_enabled |= wm->sprites_enabled;
1930 config->sprites_scaled |= wm->sprites_scaled;
1931 config->num_pipes_active++;
cca32e9a 1932 }
801bcfff
PZ		 1933}
1934
0b2ae6d7
VS		 1935/* Compute new watermarks for the pipe */
1936static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 1937 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 1938 struct intel_pipe_wm *pipe_wm)
1939{
1940 struct drm_device *dev = crtc->dev;
d34ff9c6 1941 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 1942 int level, max_level = ilk_wm_max_level(dev);
1943 /* LP0 watermark maximums depend on this pipe alone */
1944 struct intel_wm_config config = {
1945 .num_pipes_active = 1,
1946 .sprites_enabled = params->spr.enabled,
1947 .sprites_scaled = params->spr.scaled,
1948 };
820c1980 1949 struct ilk_wm_maximums max;
0b2ae6d7 1950
2a44b76b
VS		 1951 pipe_wm->pipe_enabled = params->active;
1952 pipe_wm->sprites_enabled = params->spr.enabled;
1953 pipe_wm->sprites_scaled = params->spr.scaled;
1954
7b39a0b7
VS		 1955 /* ILK/SNB: LP2+ watermarks only w/o sprites */
1956 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
1957 max_level = 1;
1958
1959 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
1960 if (params->spr.scaled)
1961 max_level = 0;
1962
a3cb4048 1963 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 1964
a42a5719 1965 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 1966 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 1967
a3cb4048
VS		 1968 /* LP0 watermarks always use 1/2 DDB partitioning */
1969 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
1970
0b2ae6d7 1971 /* At least LP0 must be valid */
a3cb4048
VS		 1972 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
1973 return false;
1974
1975 ilk_compute_wm_reg_maximums(dev, 1, &max);
1976
1977 for (level = 1; level <= max_level; level++) {
1978 struct intel_wm_level wm = {};
1979
1980 ilk_compute_wm_level(dev_priv, level, params, &wm);
1981
1982 /*
1983 * Disable any watermark level that exceeds the
1984 * register maximums since such watermarks are
1985 * always invalid.
1986 */
1987 if (!ilk_validate_wm_level(level, &max, &wm))
1988 break;
1989
1990 pipe_wm->wm[level] = wm;
1991 }
1992
1993 return true;
0b2ae6d7
VS		 1994}
1995
1996/*
1997 * Merge the watermarks from all active pipes for a specific level.
1998 */
1999static void ilk_merge_wm_level(struct drm_device *dev,
2000 int level,
2001 struct intel_wm_level *ret_wm)
2002{
2003 const struct intel_crtc *intel_crtc;
2004
d52fea5b
VS		 2005 ret_wm->enable = true;
2006
d3fcc808 2007 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2008 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2009 const struct intel_wm_level *wm = &active->wm[level];
2010
2011 if (!active->pipe_enabled)
2012 continue;
0b2ae6d7 2013
d52fea5b
VS		 2014 /*
2015 * The watermark values may have been used in the past,
2016 * so we must maintain them in the registers for some
2017 * time even if the level is now disabled.
2018 */
0b2ae6d7 2019 if (!wm->enable)
d52fea5b 2020 ret_wm->enable = false;
0b2ae6d7
VS		 2021
2022 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2023 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2024 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2025 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2026 }
0b2ae6d7
VS		 2027}
2028
2029/*
2030 * Merge all low power watermarks for all active pipes.
2031 */
2032static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2033 const struct intel_wm_config *config,
820c1980 2034 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2035 struct intel_pipe_wm *merged)
2036{
2037 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2038 int last_enabled_level = max_level;
0b2ae6d7 2039
0ba22e26
VS		 2040 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2041 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2042 config->num_pipes_active > 1)
2043 return;
2044
6c8b6c28
VS		 2045 /* ILK: FBC WM must be disabled always */
2046 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2047
2048 /* merge each WM1+ level */
2049 for (level = 1; level <= max_level; level++) {
2050 struct intel_wm_level *wm = &merged->wm[level];
2051
2052 ilk_merge_wm_level(dev, level, wm);
2053
d52fea5b
VS		 2054 if (level > last_enabled_level)
2055 wm->enable = false;
2056 else if (!ilk_validate_wm_level(level, max, wm))
2057 /* make sure all following levels get disabled */
2058 last_enabled_level = level - 1;
0b2ae6d7
VS		 2059
2060 /*
2061 * The spec says it is preferred to disable
2062 * FBC WMs instead of disabling a WM level.
2063 */
2064 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2065 if (wm->enable)
2066 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2067 wm->fbc_val = 0;
2068 }
2069 }
6c8b6c28
VS		 2070
2071 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2072 /*
2073 * FIXME this is racy. FBC might get enabled later.
2074 * What we should check here is whether FBC can be
2075 * enabled sometime later.
2076 */
2077 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2078 for (level = 2; level <= max_level; level++) {
2079 struct intel_wm_level *wm = &merged->wm[level];
2080
2081 wm->enable = false;
2082 }
2083 }
0b2ae6d7
VS		 2084}
2085
b380ca3c
VS		 2086static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2087{
2088 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2089 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2090}
2091
a68d68ee
VS		 2092/* The value we need to program into the WM_LPx latency field */
2093static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2094{
2095 struct drm_i915_private *dev_priv = dev->dev_private;
2096
a42a5719 2097 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2098 return 2 * level;
2099 else
2100 return dev_priv->wm.pri_latency[level];
2101}
2102
820c1980 2103static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2104 const struct intel_pipe_wm *merged,
609cedef 2105 enum intel_ddb_partitioning partitioning,
820c1980 2106 struct ilk_wm_values *results)
801bcfff 2107{
0b2ae6d7
VS		 2108 struct intel_crtc *intel_crtc;
2109 int level, wm_lp;
cca32e9a 2110
0362c781 2111 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2112 results->partitioning = partitioning;
cca32e9a 2113
0b2ae6d7 2114 /* LP1+ register values */
cca32e9a 2115 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2116 const struct intel_wm_level *r;
801bcfff 2117
b380ca3c 2118 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2119
0362c781 2120 r = &merged->wm[level];
cca32e9a 2121
d52fea5b
VS		 2122 /*
2123 * Maintain the watermark values even if the level is
2124 * disabled. Doing otherwise could cause underruns.
2125 */
2126 results->wm_lp[wm_lp - 1] =
a68d68ee 2127 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2128 (r->pri_val << WM1_LP_SR_SHIFT) |
2129 r->cur_val;
2130
d52fea5b
VS		 2131 if (r->enable)
2132 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2133
416f4727
VS		 2134 if (INTEL_INFO(dev)->gen >= 8)
2135 results->wm_lp[wm_lp - 1] |=
2136 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2137 else
2138 results->wm_lp[wm_lp - 1] |=
2139 r->fbc_val << WM1_LP_FBC_SHIFT;
2140
d52fea5b
VS		 2141 /*
2142 * Always set WM1S_LP_EN when spr_val != 0, even if the
2143 * level is disabled. Doing otherwise could cause underruns.
2144 */
6cef2b8a
VS		 2145 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2146 WARN_ON(wm_lp != 1);
2147 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2148 } else
2149 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2150 }
801bcfff 2151
0b2ae6d7 2152 /* LP0 register values */
d3fcc808 2153 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2154 enum pipe pipe = intel_crtc->pipe;
2155 const struct intel_wm_level *r =
2156 &intel_crtc->wm.active.wm[0];
2157
2158 if (WARN_ON(!r->enable))
2159 continue;
2160
2161 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2162
0b2ae6d7
VS		 2163 results->wm_pipe[pipe] =
2164 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2165 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2166 r->cur_val;
801bcfff
PZ		 2167 }
2168}
2169
861f3389
PZ		 2170/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2171 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2172static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2173 struct intel_pipe_wm *r1,
2174 struct intel_pipe_wm *r2)
861f3389 2175{
198a1e9b
VS		 2176 int level, max_level = ilk_wm_max_level(dev);
2177 int level1 = 0, level2 = 0;
861f3389 2178
198a1e9b
VS		 2179 for (level = 1; level <= max_level; level++) {
2180 if (r1->wm[level].enable)
2181 level1 = level;
2182 if (r2->wm[level].enable)
2183 level2 = level;
861f3389
PZ		 2184 }
2185
198a1e9b
VS		 2186 if (level1 == level2) {
2187 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2188 return r2;
2189 else
2190 return r1;
198a1e9b 2191 } else if (level1 > level2) {
861f3389
PZ		 2192 return r1;
2193 } else {
2194 return r2;
2195 }
2196}
2197
49a687c4
VS		 2198/* dirty bits used to track which watermarks need changes */
2199#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2200#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2201#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2202#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2203#define WM_DIRTY_FBC (1 << 24)
2204#define WM_DIRTY_DDB (1 << 25)
2205
055e393f 2206static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2207 const struct ilk_wm_values *old,
2208 const struct ilk_wm_values *new)
49a687c4
VS		 2209{
2210 unsigned int dirty = 0;
2211 enum pipe pipe;
2212 int wm_lp;
2213
055e393f 2214 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2215 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2216 dirty |= WM_DIRTY_LINETIME(pipe);
2217 /* Must disable LP1+ watermarks too */
2218 dirty |= WM_DIRTY_LP_ALL;
2219 }
2220
2221 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2222 dirty |= WM_DIRTY_PIPE(pipe);
2223 /* Must disable LP1+ watermarks too */
2224 dirty |= WM_DIRTY_LP_ALL;
2225 }
2226 }
2227
2228 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2229 dirty |= WM_DIRTY_FBC;
2230 /* Must disable LP1+ watermarks too */
2231 dirty |= WM_DIRTY_LP_ALL;
2232 }
2233
2234 if (old->partitioning != new->partitioning) {
2235 dirty |= WM_DIRTY_DDB;
2236 /* Must disable LP1+ watermarks too */
2237 dirty |= WM_DIRTY_LP_ALL;
2238 }
2239
2240 /* LP1+ watermarks already deemed dirty, no need to continue */
2241 if (dirty & WM_DIRTY_LP_ALL)
2242 return dirty;
2243
2244 /* Find the lowest numbered LP1+ watermark in need of an update... */
2245 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2246 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2247 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2248 break;
2249 }
2250
2251 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2252 for (; wm_lp <= 3; wm_lp++)
2253 dirty |= WM_DIRTY_LP(wm_lp);
2254
2255 return dirty;
2256}
2257
8553c18e
VS		 2258static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2259 unsigned int dirty)
801bcfff 2260{
820c1980 2261 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2262 bool changed = false;
801bcfff 2263
facd619b
VS		 2264 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2265 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2266 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2267 changed = true;
facd619b
VS		 2268 }
2269 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2270 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2271 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2272 changed = true;
facd619b
VS		 2273 }
2274 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2275 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2276 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2277 changed = true;
facd619b 2278 }
801bcfff 2279
facd619b
VS		 2280 /*
2281 * Don't touch WM1S_LP_EN here.
2282 * Doing so could cause underruns.
2283 */
6cef2b8a 2284
8553c18e
VS		 2285 return changed;
2286}
2287
2288/*
2289 * The spec says we shouldn't write when we don't need, because every write
2290 * causes WMs to be re-evaluated, expending some power.
2291 */
820c1980
ID		 2292static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2293 struct ilk_wm_values *results)
8553c18e
VS		 2294{
2295 struct drm_device *dev = dev_priv->dev;
820c1980 2296 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2297 unsigned int dirty;
2298 uint32_t val;
2299
055e393f 2300 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2301 if (!dirty)
2302 return;
2303
2304 _ilk_disable_lp_wm(dev_priv, dirty);
2305
49a687c4 2306 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2307 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2308 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2309 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2310 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2311 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2312
49a687c4 2313 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2314 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2315 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2316 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2317 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2318 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2319
49a687c4 2320 if (dirty & WM_DIRTY_DDB) {
a42a5719 2321 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2322 val = I915_READ(WM_MISC);
2323 if (results->partitioning == INTEL_DDB_PART_1_2)
2324 val &= ~WM_MISC_DATA_PARTITION_5_6;
2325 else
2326 val |= WM_MISC_DATA_PARTITION_5_6;
2327 I915_WRITE(WM_MISC, val);
2328 } else {
2329 val = I915_READ(DISP_ARB_CTL2);
2330 if (results->partitioning == INTEL_DDB_PART_1_2)
2331 val &= ~DISP_DATA_PARTITION_5_6;
2332 else
2333 val |= DISP_DATA_PARTITION_5_6;
2334 I915_WRITE(DISP_ARB_CTL2, val);
2335 }
1011d8c4
PZ		 2336 }
2337
49a687c4 2338 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2339 val = I915_READ(DISP_ARB_CTL);
2340 if (results->enable_fbc_wm)
2341 val &= ~DISP_FBC_WM_DIS;
2342 else
2343 val |= DISP_FBC_WM_DIS;
2344 I915_WRITE(DISP_ARB_CTL, val);
2345 }
2346
954911eb
ID		 2347 if (dirty & WM_DIRTY_LP(1) &&
2348 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2349 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2350
2351 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2352 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2353 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2354 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2355 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2356 }
801bcfff 2357
facd619b 2358 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2359 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2360 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2361 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2362 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2363 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2364
2365 dev_priv->wm.hw = *results;
801bcfff
PZ		 2366}
2367
8553c18e
VS		 2368static bool ilk_disable_lp_wm(struct drm_device *dev)
2369{
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2371
2372 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2373}
2374
b9cec075
DL		 2375/*
2376 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2377 * different active planes.
2378 */
2379
2380#define SKL_DDB_SIZE 896 /* in blocks */
2381
2382static void
2383skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2384 struct drm_crtc *for_crtc,
2385 const struct intel_wm_config *config,
2386 const struct skl_pipe_wm_parameters *params,
2387 struct skl_ddb_entry *alloc /* out */)
2388{
2389 struct drm_crtc *crtc;
2390 unsigned int pipe_size, ddb_size;
2391 int nth_active_pipe;
2392
2393 if (!params->active) {
2394 alloc->start = 0;
2395 alloc->end = 0;
2396 return;
2397 }
2398
2399 ddb_size = SKL_DDB_SIZE;
2400
2401 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2402
2403 nth_active_pipe = 0;
2404 for_each_crtc(dev, crtc) {
2405 if (!intel_crtc_active(crtc))
2406 continue;
2407
2408 if (crtc == for_crtc)
2409 break;
2410
2411 nth_active_pipe++;
2412 }
2413
2414 pipe_size = ddb_size / config->num_pipes_active;
2415 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2416 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2417}
2418
2419static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2420{
2421 if (config->num_pipes_active == 1)
2422 return 32;
2423
2424 return 8;
2425}
2426
a269c583
DL		 2427static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2428{
2429 entry->start = reg & 0x3ff;
2430 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2431 if (entry->end)
2432 entry->end += 1;
a269c583
DL		 2433}
2434
08db6652
DL		 2435void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2436 struct skl_ddb_allocation *ddb /* out */)
a269c583
DL		 2437{
2438 struct drm_device *dev = dev_priv->dev;
2439 enum pipe pipe;
2440 int plane;
2441 u32 val;
2442
2443 for_each_pipe(dev_priv, pipe) {
2444 for_each_plane(pipe, plane) {
2445 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2446 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2447 val);
2448 }
2449
2450 val = I915_READ(CUR_BUF_CFG(pipe));
2451 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2452 }
2453}
2454
b9cec075
DL		 2455static unsigned int
2456skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2457{
2458 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2459}
2460
2461/*
2462 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2463 * a 8192x4096@32bpp framebuffer:
2464 * 3 * 4096 * 8192 * 4 < 2^32
2465 */
2466static unsigned int
2467skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2468 const struct skl_pipe_wm_parameters *params)
2469{
2470 unsigned int total_data_rate = 0;
2471 int plane;
2472
2473 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2474 const struct intel_plane_wm_parameters *p;
2475
2476 p = &params->plane[plane];
2477 if (!p->enabled)
2478 continue;
2479
2480 total_data_rate += skl_plane_relative_data_rate(p);
2481 }
2482
2483 return total_data_rate;
2484}
2485
2486static void
2487skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2488 const struct intel_wm_config *config,
2489 const struct skl_pipe_wm_parameters *params,
2490 struct skl_ddb_allocation *ddb /* out */)
2491{
2492 struct drm_device *dev = crtc->dev;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 enum pipe pipe = intel_crtc->pipe;
34bb56af 2495 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075
DL		 2496 uint16_t alloc_size, start, cursor_blocks;
2497 unsigned int total_data_rate;
2498 int plane;
2499
34bb56af
DL		 2500 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2501 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2502 if (alloc_size == 0) {
2503 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2504 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2505 return;
2506 }
2507
2508 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2509 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2510 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2511
2512 alloc_size -= cursor_blocks;
34bb56af 2513 alloc->end -= cursor_blocks;
b9cec075
DL		 2514
2515 /*
2516 * Each active plane get a portion of the remaining space, in
2517 * proportion to the amount of data they need to fetch from memory.
2518 *
2519 * FIXME: we may not allocate every single block here.
2520 */
2521 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2522
34bb56af 2523 start = alloc->start;
b9cec075
DL		 2524 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2525 const struct intel_plane_wm_parameters *p;
2526 unsigned int data_rate;
2527 uint16_t plane_blocks;
2528
2529 p = &params->plane[plane];
2530 if (!p->enabled)
2531 continue;
2532
2533 data_rate = skl_plane_relative_data_rate(p);
2534
2535 /*
2536 * promote the expression to 64 bits to avoid overflowing, the
2537 * result is < available as data_rate / total_data_rate < 1
2538 */
2539 plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
2540 total_data_rate);
2541
2542 ddb->plane[pipe][plane].start = start;
16160e3d 2543 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2544
2545 start += plane_blocks;
2546 }
2547
2548}
2549
5cec258b 2550static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2551{
2552 /* TODO: Take into account the scalers once we support them */
2d112de7 2553 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2554}
2555
2556/*
2557 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2558 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2559 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2560 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2561*/
2562static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2563 uint32_t latency)
2564{
2565 uint32_t wm_intermediate_val, ret;
2566
2567 if (latency == 0)
2568 return UINT_MAX;
2569
2570 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel;
2571 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2572
2573 return ret;
2574}
2575
2576static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2577 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2578 uint32_t latency)
2579{
2580 uint32_t ret, plane_bytes_per_line, wm_intermediate_val;
2581
2582 if (latency == 0)
2583 return UINT_MAX;
2584
2585 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
2586 wm_intermediate_val = latency * pixel_rate;
2587 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
2588 plane_bytes_per_line;
2589
2590 return ret;
2591}
2592
2d41c0b5
PB		 2593static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2594 const struct intel_crtc *intel_crtc)
2595{
2596 struct drm_device *dev = intel_crtc->base.dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2599 enum pipe pipe = intel_crtc->pipe;
2600
2601 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2602 sizeof(new_ddb->plane[pipe])))
2603 return true;
2604
2605 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2606 sizeof(new_ddb->cursor[pipe])))
2607 return true;
2608
2609 return false;
2610}
2611
2612static void skl_compute_wm_global_parameters(struct drm_device *dev,
2613 struct intel_wm_config *config)
2614{
2615 struct drm_crtc *crtc;
2616 struct drm_plane *plane;
2617
2618 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2619 config->num_pipes_active += intel_crtc_active(crtc);
2620
2621 /* FIXME: I don't think we need those two global parameters on SKL */
2622 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2623 struct intel_plane *intel_plane = to_intel_plane(plane);
2624
2625 config->sprites_enabled |= intel_plane->wm.enabled;
2626 config->sprites_scaled |= intel_plane->wm.scaled;
2627 }
2628}
2629
2630static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2631 struct skl_pipe_wm_parameters *p)
2632{
2633 struct drm_device *dev = crtc->dev;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 enum pipe pipe = intel_crtc->pipe;
2636 struct drm_plane *plane;
2637 int i = 1; /* Index for sprite planes start */
2638
2639 p->active = intel_crtc_active(crtc);
2640 if (p->active) {
6e3c9717
ACO		 2641 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2642 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5
PB		 2643
2644 /*
2645 * For now, assume primary and cursor planes are always enabled.
2646 */
2647 p->plane[0].enabled = true;
2648 p->plane[0].bytes_per_pixel =
2649 crtc->primary->fb->bits_per_pixel / 8;
6e3c9717
ACO		 2650 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2651 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
2d41c0b5
PB		 2652
2653 p->cursor.enabled = true;
2654 p->cursor.bytes_per_pixel = 4;
2655 p->cursor.horiz_pixels = intel_crtc->cursor_width ?
2656 intel_crtc->cursor_width : 64;
2657 }
2658
2659 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2660 struct intel_plane *intel_plane = to_intel_plane(plane);
2661
a712f8eb
SJ		 2662 if (intel_plane->pipe == pipe &&
2663 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2664 p->plane[i++] = intel_plane->wm;
2665 }
2666}
2667
2668static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2669 struct intel_plane_wm_parameters *p_params,
2670 uint16_t ddb_allocation,
2671 uint32_t mem_value,
2672 uint16_t *out_blocks, /* out */
2673 uint8_t *out_lines /* out */)
2d41c0b5 2674{
e6d66171 2675 uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines;
2d41c0b5
PB		 2676 uint32_t result_bytes;
2677
4f947386 2678 if (mem_value == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2679 return false;
2680
2681 method1 = skl_wm_method1(p->pixel_rate,
2682 p_params->bytes_per_pixel,
2683 mem_value);
2684 method2 = skl_wm_method2(p->pixel_rate,
2685 p->pipe_htotal,
2686 p_params->horiz_pixels,
2687 p_params->bytes_per_pixel,
2688 mem_value);
2689
2690 plane_bytes_per_line = p_params->horiz_pixels *
2691 p_params->bytes_per_pixel;
2692
2693 /* For now xtile and linear */
21fca258 2694 if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1)
2d41c0b5
PB		 2695 result_bytes = min(method1, method2);
2696 else
2697 result_bytes = method1;
2698
e6d66171
DL		 2699 res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1;
2700 res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line);
2701
2702 if (res_blocks > ddb_allocation || res_lines > 31)
2703 return false;
2704
2705 *out_blocks = res_blocks;
2706 *out_lines = res_lines;
2d41c0b5
PB		 2707
2708 return true;
2709}
2710
2711static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2712 struct skl_ddb_allocation *ddb,
2713 struct skl_pipe_wm_parameters *p,
2714 enum pipe pipe,
2715 int level,
2716 int num_planes,
2717 struct skl_wm_level *result)
2718{
2719 uint16_t latency = dev_priv->wm.skl_latency[level];
2720 uint16_t ddb_blocks;
2721 int i;
2722
2723 for (i = 0; i < num_planes; i++) {
2724 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2725
2726 result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i],
2727 ddb_blocks,
2728 latency,
2729 &result->plane_res_b[i],
2730 &result->plane_res_l[i]);
2731 }
2732
2733 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
2734 result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks,
2735 latency, &result->cursor_res_b,
2736 &result->cursor_res_l);
2737}
2738
407b50f3
DL		 2739static uint32_t
2740skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2741{
2742 if (!intel_crtc_active(crtc))
2743 return 0;
2744
2745 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2746
2747}
2748
2749static void skl_compute_transition_wm(struct drm_crtc *crtc,
2750 struct skl_pipe_wm_parameters *params,
9414f563 2751 struct skl_wm_level *trans_wm /* out */)
407b50f3 2752{
9414f563
DL		 2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int i;
2755
407b50f3
DL		 2756 if (!params->active)
2757 return;
9414f563
DL		 2758
2759 /* Until we know more, just disable transition WMs */
2760 for (i = 0; i < intel_num_planes(intel_crtc); i++)
2761 trans_wm->plane_en[i] = false;
2762 trans_wm->cursor_en = false;
407b50f3
DL		 2763}
2764
2d41c0b5
PB		 2765static void skl_compute_pipe_wm(struct drm_crtc *crtc,
2766 struct skl_ddb_allocation *ddb,
2767 struct skl_pipe_wm_parameters *params,
2768 struct skl_pipe_wm *pipe_wm)
2769{
2770 struct drm_device *dev = crtc->dev;
2771 const struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 int level, max_level = ilk_wm_max_level(dev);
2774
2775 for (level = 0; level <= max_level; level++) {
2776 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
2777 level, intel_num_planes(intel_crtc),
2778 &pipe_wm->wm[level]);
2779 }
2780 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
2781
9414f563 2782 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 2783}
2784
2785static void skl_compute_wm_results(struct drm_device *dev,
2786 struct skl_pipe_wm_parameters *p,
2787 struct skl_pipe_wm *p_wm,
2788 struct skl_wm_values *r,
2789 struct intel_crtc *intel_crtc)
2790{
2791 int level, max_level = ilk_wm_max_level(dev);
2792 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 2793 uint32_t temp;
2794 int i;
2d41c0b5
PB		 2795
2796 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 2797 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2798 temp = 0;
2d41c0b5
PB		 2799
2800 temp |= p_wm->wm[level].plane_res_l[i] <<
2801 PLANE_WM_LINES_SHIFT;
2802 temp |= p_wm->wm[level].plane_res_b[i];
2803 if (p_wm->wm[level].plane_en[i])
2804 temp |= PLANE_WM_EN;
2805
2806 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 2807 }
2808
2809 temp = 0;
2d41c0b5
PB		 2810
2811 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
2812 temp |= p_wm->wm[level].cursor_res_b;
2813
2814 if (p_wm->wm[level].cursor_en)
2815 temp |= PLANE_WM_EN;
2816
2817 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 2818
2819 }
2820
9414f563
DL		 2821 /* transition WMs */
2822 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2823 temp = 0;
2824 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
2825 temp |= p_wm->trans_wm.plane_res_b[i];
2826 if (p_wm->trans_wm.plane_en[i])
2827 temp |= PLANE_WM_EN;
2828
2829 r->plane_trans[pipe][i] = temp;
2830 }
2831
2832 temp = 0;
2833 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
2834 temp |= p_wm->trans_wm.cursor_res_b;
2835 if (p_wm->trans_wm.cursor_en)
2836 temp |= PLANE_WM_EN;
2837
2838 r->cursor_trans[pipe] = temp;
2839
2d41c0b5
PB		 2840 r->wm_linetime[pipe] = p_wm->linetime;
2841}
2842
16160e3d
DL		 2843static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
2844 const struct skl_ddb_entry *entry)
2845{
2846 if (entry->end)
2847 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
2848 else
2849 I915_WRITE(reg, 0);
2850}
2851
2d41c0b5
PB		 2852static void skl_write_wm_values(struct drm_i915_private *dev_priv,
2853 const struct skl_wm_values *new)
2854{
2855 struct drm_device *dev = dev_priv->dev;
2856 struct intel_crtc *crtc;
2857
2858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2859 int i, level, max_level = ilk_wm_max_level(dev);
2860 enum pipe pipe = crtc->pipe;
2861
5d374d96
DL		 2862 if (!new->dirty[pipe])
2863 continue;
8211bd5b 2864
5d374d96 2865 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 2866
5d374d96
DL		 2867 for (level = 0; level <= max_level; level++) {
2868 for (i = 0; i < intel_num_planes(crtc); i++)
2869 I915_WRITE(PLANE_WM(pipe, i, level),
2870 new->plane[pipe][i][level]);
2871 I915_WRITE(CUR_WM(pipe, level),
2872 new->cursor[pipe][level]);
2d41c0b5 2873 }
5d374d96
DL		 2874 for (i = 0; i < intel_num_planes(crtc); i++)
2875 I915_WRITE(PLANE_WM_TRANS(pipe, i),
2876 new->plane_trans[pipe][i]);
2877 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
2878
2879 for (i = 0; i < intel_num_planes(crtc); i++)
2880 skl_ddb_entry_write(dev_priv,
2881 PLANE_BUF_CFG(pipe, i),
2882 &new->ddb.plane[pipe][i]);
2883
2884 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
2885 &new->ddb.cursor[pipe]);
2d41c0b5 2886 }
2d41c0b5
PB		 2887}
2888
0e8fb7ba
DL		 2889/*
2890 * When setting up a new DDB allocation arrangement, we need to correctly
2891 * sequence the times at which the new allocations for the pipes are taken into
2892 * account or we'll have pipes fetching from space previously allocated to
2893 * another pipe.
2894 *
2895 * Roughly the sequence looks like:
2896 * 1. re-allocate the pipe(s) with the allocation being reduced and not
2897 * overlapping with a previous light-up pipe (another way to put it is:
2898 * pipes with their new allocation strickly included into their old ones).
2899 * 2. re-allocate the other pipes that get their allocation reduced
2900 * 3. allocate the pipes having their allocation increased
2901 *
2902 * Steps 1. and 2. are here to take care of the following case:
2903 * - Initially DDB looks like this:
2904 * | B | C |
2905 * - enable pipe A.
2906 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
2907 * allocation
2908 * | A | B | C |
2909 *
2910 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
2911 */
2912
d21b795c
DL		 2913static void
2914skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba
DL		 2915{
2916 struct drm_device *dev = dev_priv->dev;
2917 int plane;
2918
d21b795c
DL		 2919 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
2920
0e8fb7ba
DL		 2921 for_each_plane(pipe, plane) {
2922 I915_WRITE(PLANE_SURF(pipe, plane),
2923 I915_READ(PLANE_SURF(pipe, plane)));
2924 }
2925 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
2926}
2927
2928static bool
2929skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
2930 const struct skl_ddb_allocation *new,
2931 enum pipe pipe)
2932{
2933 uint16_t old_size, new_size;
2934
2935 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
2936 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
2937
2938 return old_size != new_size &&
2939 new->pipe[pipe].start >= old->pipe[pipe].start &&
2940 new->pipe[pipe].end <= old->pipe[pipe].end;
2941}
2942
2943static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
2944 struct skl_wm_values *new_values)
2945{
2946 struct drm_device *dev = dev_priv->dev;
2947 struct skl_ddb_allocation *cur_ddb, *new_ddb;
2948 bool reallocated[I915_MAX_PIPES] = {false, false, false};
2949 struct intel_crtc *crtc;
2950 enum pipe pipe;
2951
2952 new_ddb = &new_values->ddb;
2953 cur_ddb = &dev_priv->wm.skl_hw.ddb;
2954
2955 /*
2956 * First pass: flush the pipes with the new allocation contained into
2957 * the old space.
2958 *
2959 * We'll wait for the vblank on those pipes to ensure we can safely
2960 * re-allocate the freed space without this pipe fetching from it.
2961 */
2962 for_each_intel_crtc(dev, crtc) {
2963 if (!crtc->active)
2964 continue;
2965
2966 pipe = crtc->pipe;
2967
2968 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
2969 continue;
2970
d21b795c 2971 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 2972 intel_wait_for_vblank(dev, pipe);
2973
2974 reallocated[pipe] = true;
2975 }
2976
2977
2978 /*
2979 * Second pass: flush the pipes that are having their allocation
2980 * reduced, but overlapping with a previous allocation.
2981 *
2982 * Here as well we need to wait for the vblank to make sure the freed
2983 * space is not used anymore.
2984 */
2985 for_each_intel_crtc(dev, crtc) {
2986 if (!crtc->active)
2987 continue;
2988
2989 pipe = crtc->pipe;
2990
2991 if (reallocated[pipe])
2992 continue;
2993
2994 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
2995 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 2996 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 2997 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 2998 reallocated[pipe] = true;
0e8fb7ba 2999 }
0e8fb7ba
DL		 3000 }
3001
3002 /*
3003 * Third pass: flush the pipes that got more space allocated.
3004 *
3005 * We don't need to actively wait for the update here, next vblank
3006 * will just get more DDB space with the correct WM values.
3007 */
3008 for_each_intel_crtc(dev, crtc) {
3009 if (!crtc->active)
3010 continue;
3011
3012 pipe = crtc->pipe;
3013
3014 /*
3015 * At this point, only the pipes more space than before are
3016 * left to re-allocate.
3017 */
3018 if (reallocated[pipe])
3019 continue;
3020
d21b795c 3021 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3022 }
3023}
3024
2d41c0b5
PB		 3025static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3026 struct skl_pipe_wm_parameters *params,
3027 struct intel_wm_config *config,
3028 struct skl_ddb_allocation *ddb, /* out */
3029 struct skl_pipe_wm *pipe_wm /* out */)
3030{
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032
3033 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3034 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3035 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3036
3037 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3038 return false;
3039
3040 intel_crtc->wm.skl_active = *pipe_wm;
3041 return true;
3042}
3043
3044static void skl_update_other_pipe_wm(struct drm_device *dev,
3045 struct drm_crtc *crtc,
3046 struct intel_wm_config *config,
3047 struct skl_wm_values *r)
3048{
3049 struct intel_crtc *intel_crtc;
3050 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3051
3052 /*
3053 * If the WM update hasn't changed the allocation for this_crtc (the
3054 * crtc we are currently computing the new WM values for), other
3055 * enabled crtcs will keep the same allocation and we don't need to
3056 * recompute anything for them.
3057 */
3058 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3059 return;
3060
3061 /*
3062 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3063 * other active pipes need new DDB allocation and WM values.
3064 */
3065 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3066 base.head) {
3067 struct skl_pipe_wm_parameters params = {};
3068 struct skl_pipe_wm pipe_wm = {};
3069 bool wm_changed;
3070
3071 if (this_crtc->pipe == intel_crtc->pipe)
3072 continue;
3073
3074 if (!intel_crtc->active)
3075 continue;
3076
3077 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3078 &params, config,
3079 &r->ddb, &pipe_wm);
3080
3081 /*
3082 * If we end up re-computing the other pipe WM values, it's
3083 * because it was really needed, so we expect the WM values to
3084 * be different.
3085 */
3086 WARN_ON(!wm_changed);
3087
3088 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3089 r->dirty[intel_crtc->pipe] = true;
3090 }
3091}
3092
3093static void skl_update_wm(struct drm_crtc *crtc)
3094{
3095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3096 struct drm_device *dev = crtc->dev;
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 struct skl_pipe_wm_parameters params = {};
3099 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3100 struct skl_pipe_wm pipe_wm = {};
3101 struct intel_wm_config config = {};
3102
3103 memset(results, 0, sizeof(*results));
3104
3105 skl_compute_wm_global_parameters(dev, &config);
3106
3107 if (!skl_update_pipe_wm(crtc, &params, &config,
3108 &results->ddb, &pipe_wm))
3109 return;
3110
3111 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3112 results->dirty[intel_crtc->pipe] = true;
3113
3114 skl_update_other_pipe_wm(dev, crtc, &config, results);
3115 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3116 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3117
3118 /* store the new configuration */
3119 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3120}
3121
3122static void
3123skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3124 uint32_t sprite_width, uint32_t sprite_height,
3125 int pixel_size, bool enabled, bool scaled)
3126{
3127 struct intel_plane *intel_plane = to_intel_plane(plane);
3128
3129 intel_plane->wm.enabled = enabled;
3130 intel_plane->wm.scaled = scaled;
3131 intel_plane->wm.horiz_pixels = sprite_width;
3132 intel_plane->wm.vert_pixels = sprite_height;
3133 intel_plane->wm.bytes_per_pixel = pixel_size;
3134
3135 skl_update_wm(crtc);
3136}
3137
820c1980 3138static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3139{
7c4a395f 3140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3141 struct drm_device *dev = crtc->dev;
801bcfff 3142 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3143 struct ilk_wm_maximums max;
3144 struct ilk_pipe_wm_parameters params = {};
3145 struct ilk_wm_values results = {};
77c122bc 3146 enum intel_ddb_partitioning partitioning;
7c4a395f 3147 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3148 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3149 struct intel_wm_config config = {};
7c4a395f 3150
2a44b76b 3151 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3152
3153 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3154
3155 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3156 return;
861f3389 3157
7c4a395f 3158 intel_crtc->wm.active = pipe_wm;
861f3389 3159
2a44b76b
VS		 3160 ilk_compute_wm_config(dev, &config);
3161
34982fe1 3162 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3163 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3164
3165 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3166 if (INTEL_INFO(dev)->gen >= 7 &&
3167 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3168 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3169 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3170
820c1980 3171 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3172 } else {
198a1e9b 3173 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3174 }
3175
198a1e9b 3176 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3177 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3178
820c1980 3179 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3180
820c1980 3181 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3182}
3183
ed57cb8a
DL		 3184static void
3185ilk_update_sprite_wm(struct drm_plane *plane,
3186 struct drm_crtc *crtc,
3187 uint32_t sprite_width, uint32_t sprite_height,
3188 int pixel_size, bool enabled, bool scaled)
526682e9 3189{
8553c18e 3190 struct drm_device *dev = plane->dev;
adf3d35e 3191 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3192
adf3d35e
VS		 3193 intel_plane->wm.enabled = enabled;
3194 intel_plane->wm.scaled = scaled;
3195 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3196 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3197 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3198
8553c18e
VS		 3199 /*
3200 * IVB workaround: must disable low power watermarks for at least
3201 * one frame before enabling scaling. LP watermarks can be re-enabled
3202 * when scaling is disabled.
3203 *
3204 * WaCxSRDisabledForSpriteScaling:ivb
3205 */
3206 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3207 intel_wait_for_vblank(dev, intel_plane->pipe);
3208
820c1980 3209 ilk_update_wm(crtc);
526682e9
PZ		 3210}
3211
3078999f
PB		 3212static void skl_pipe_wm_active_state(uint32_t val,
3213 struct skl_pipe_wm *active,
3214 bool is_transwm,
3215 bool is_cursor,
3216 int i,
3217 int level)
3218{
3219 bool is_enabled = (val & PLANE_WM_EN) != 0;
3220
3221 if (!is_transwm) {
3222 if (!is_cursor) {
3223 active->wm[level].plane_en[i] = is_enabled;
3224 active->wm[level].plane_res_b[i] =
3225 val & PLANE_WM_BLOCKS_MASK;
3226 active->wm[level].plane_res_l[i] =
3227 (val >> PLANE_WM_LINES_SHIFT) &
3228 PLANE_WM_LINES_MASK;
3229 } else {
3230 active->wm[level].cursor_en = is_enabled;
3231 active->wm[level].cursor_res_b =
3232 val & PLANE_WM_BLOCKS_MASK;
3233 active->wm[level].cursor_res_l =
3234 (val >> PLANE_WM_LINES_SHIFT) &
3235 PLANE_WM_LINES_MASK;
3236 }
3237 } else {
3238 if (!is_cursor) {
3239 active->trans_wm.plane_en[i] = is_enabled;
3240 active->trans_wm.plane_res_b[i] =
3241 val & PLANE_WM_BLOCKS_MASK;
3242 active->trans_wm.plane_res_l[i] =
3243 (val >> PLANE_WM_LINES_SHIFT) &
3244 PLANE_WM_LINES_MASK;
3245 } else {
3246 active->trans_wm.cursor_en = is_enabled;
3247 active->trans_wm.cursor_res_b =
3248 val & PLANE_WM_BLOCKS_MASK;
3249 active->trans_wm.cursor_res_l =
3250 (val >> PLANE_WM_LINES_SHIFT) &
3251 PLANE_WM_LINES_MASK;
3252 }
3253 }
3254}
3255
3256static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3257{
3258 struct drm_device *dev = crtc->dev;
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3262 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3263 enum pipe pipe = intel_crtc->pipe;
3264 int level, i, max_level;
3265 uint32_t temp;
3266
3267 max_level = ilk_wm_max_level(dev);
3268
3269 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3270
3271 for (level = 0; level <= max_level; level++) {
3272 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3273 hw->plane[pipe][i][level] =
3274 I915_READ(PLANE_WM(pipe, i, level));
3275 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3276 }
3277
3278 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3279 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3280 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3281
3282 if (!intel_crtc_active(crtc))
3283 return;
3284
3285 hw->dirty[pipe] = true;
3286
3287 active->linetime = hw->wm_linetime[pipe];
3288
3289 for (level = 0; level <= max_level; level++) {
3290 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3291 temp = hw->plane[pipe][i][level];
3292 skl_pipe_wm_active_state(temp, active, false,
3293 false, i, level);
3294 }
3295 temp = hw->cursor[pipe][level];
3296 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3297 }
3298
3299 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3300 temp = hw->plane_trans[pipe][i];
3301 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3302 }
3303
3304 temp = hw->cursor_trans[pipe];
3305 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3306}
3307
3308void skl_wm_get_hw_state(struct drm_device *dev)
3309{
a269c583
DL		 3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3312 struct drm_crtc *crtc;
3313
a269c583 3314 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3315 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3316 skl_pipe_wm_get_hw_state(crtc);
3317}
3318
243e6a44
VS		 3319static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3320{
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3323 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3326 enum pipe pipe = intel_crtc->pipe;
3327 static const unsigned int wm0_pipe_reg[] = {
3328 [PIPE_A] = WM0_PIPEA_ILK,
3329 [PIPE_B] = WM0_PIPEB_ILK,
3330 [PIPE_C] = WM0_PIPEC_IVB,
3331 };
3332
3333 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3334 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3335 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3336
2a44b76b
VS		 3337 active->pipe_enabled = intel_crtc_active(crtc);
3338
3339 if (active->pipe_enabled) {
243e6a44
VS		 3340 u32 tmp = hw->wm_pipe[pipe];
3341
3342 /*
3343 * For active pipes LP0 watermark is marked as
3344 * enabled, and LP1+ watermaks as disabled since
3345 * we can't really reverse compute them in case
3346 * multiple pipes are active.
3347 */
3348 active->wm[0].enable = true;
3349 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3350 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3351 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3352 active->linetime = hw->wm_linetime[pipe];
3353 } else {
3354 int level, max_level = ilk_wm_max_level(dev);
3355
3356 /*
3357 * For inactive pipes, all watermark levels
3358 * should be marked as enabled but zeroed,
3359 * which is what we'd compute them to.
3360 */
3361 for (level = 0; level <= max_level; level++)
3362 active->wm[level].enable = true;
3363 }
3364}
3365
3366void ilk_wm_get_hw_state(struct drm_device *dev)
3367{
3368 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3369 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3370 struct drm_crtc *crtc;
3371
70e1e0ec 3372 for_each_crtc(dev, crtc)
243e6a44
VS		 3373 ilk_pipe_wm_get_hw_state(crtc);
3374
3375 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3376 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3377 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3378
3379 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3380 if (INTEL_INFO(dev)->gen >= 7) {
3381 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3382 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3383 }
243e6a44 3384
a42a5719 3385 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3386 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3387 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3388 else if (IS_IVYBRIDGE(dev))
3389 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3390 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3391
3392 hw->enable_fbc_wm =
3393 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3394}
3395
b445e3b0
ED		 3396/**
3397 * intel_update_watermarks - update FIFO watermark values based on current modes
3398 *
3399 * Calculate watermark values for the various WM regs based on current mode
3400 * and plane configuration.
3401 *
3402 * There are several cases to deal with here:
3403 * - normal (i.e. non-self-refresh)
3404 * - self-refresh (SR) mode
3405 * - lines are large relative to FIFO size (buffer can hold up to 2)
3406 * - lines are small relative to FIFO size (buffer can hold more than 2
3407 * lines), so need to account for TLB latency
3408 *
3409 * The normal calculation is:
3410 * watermark = dotclock * bytes per pixel * latency
3411 * where latency is platform & configuration dependent (we assume pessimal
3412 * values here).
3413 *
3414 * The SR calculation is:
3415 * watermark = (trunc(latency/line time)+1) * surface width *
3416 * bytes per pixel
3417 * where
3418 * line time = htotal / dotclock
3419 * surface width = hdisplay for normal plane and 64 for cursor
3420 * and latency is assumed to be high, as above.
3421 *
3422 * The final value programmed to the register should always be rounded up,
3423 * and include an extra 2 entries to account for clock crossings.
3424 *
3425 * We don't use the sprite, so we can ignore that. And on Crestline we have
3426 * to set the non-SR watermarks to 8.
3427 */
46ba614c 3428void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3429{
46ba614c 3430 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3431
3432 if (dev_priv->display.update_wm)
46ba614c 3433 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3434}
3435
adf3d35e
VS		 3436void intel_update_sprite_watermarks(struct drm_plane *plane,
3437 struct drm_crtc *crtc,
ed57cb8a
DL		 3438 uint32_t sprite_width,
3439 uint32_t sprite_height,
3440 int pixel_size,
39db4a4d 3441 bool enabled, bool scaled)
b445e3b0 3442{
adf3d35e 3443 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3444
3445 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3446 dev_priv->display.update_sprite_wm(plane, crtc,
3447 sprite_width, sprite_height,
39db4a4d 3448 pixel_size, enabled, scaled);
b445e3b0
ED		 3449}
3450
2b4e57bd
ED		 3451static struct drm_i915_gem_object *
3452intel_alloc_context_page(struct drm_device *dev)
3453{
3454 struct drm_i915_gem_object *ctx;
3455 int ret;
3456
3457 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3458
3459 ctx = i915_gem_alloc_object(dev, 4096);
3460 if (!ctx) {
3461 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3462 return NULL;
3463 }
3464
c69766f2 3465 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 3466 if (ret) {
3467 DRM_ERROR("failed to pin power context: %d\n", ret);
3468 goto err_unref;
3469 }
3470
3471 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3472 if (ret) {
3473 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3474 goto err_unpin;
3475 }
3476
3477 return ctx;
3478
3479err_unpin:
d7f46fc4 3480 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 3481err_unref:
3482 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3483 return NULL;
3484}
3485
9270388e
DV		 3486/**
3487 * Lock protecting IPS related data structures
9270388e
DV		 3488 */
3489DEFINE_SPINLOCK(mchdev_lock);
3490
3491/* Global for IPS driver to get at the current i915 device. Protected by
3492 * mchdev_lock. */
3493static struct drm_i915_private *i915_mch_dev;
3494
2b4e57bd
ED		 3495bool ironlake_set_drps(struct drm_device *dev, u8 val)
3496{
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 u16 rgvswctl;
3499
9270388e
DV		 3500 assert_spin_locked(&mchdev_lock);
3501
2b4e57bd
ED		 3502 rgvswctl = I915_READ16(MEMSWCTL);
3503 if (rgvswctl & MEMCTL_CMD_STS) {
3504 DRM_DEBUG("gpu busy, RCS change rejected\n");
3505 return false; /* still busy with another command */
3506 }
3507
3508 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3509 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3510 I915_WRITE16(MEMSWCTL, rgvswctl);
3511 POSTING_READ16(MEMSWCTL);
3512
3513 rgvswctl |= MEMCTL_CMD_STS;
3514 I915_WRITE16(MEMSWCTL, rgvswctl);
3515
3516 return true;
3517}
3518
8090c6b9 3519static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3520{
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 u32 rgvmodectl = I915_READ(MEMMODECTL);
3523 u8 fmax, fmin, fstart, vstart;
3524
9270388e
DV		 3525 spin_lock_irq(&mchdev_lock);
3526
2b4e57bd
ED		 3527 /* Enable temp reporting */
3528 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3529 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3530
3531 /* 100ms RC evaluation intervals */
3532 I915_WRITE(RCUPEI, 100000);
3533 I915_WRITE(RCDNEI, 100000);
3534
3535 /* Set max/min thresholds to 90ms and 80ms respectively */
3536 I915_WRITE(RCBMAXAVG, 90000);
3537 I915_WRITE(RCBMINAVG, 80000);
3538
3539 I915_WRITE(MEMIHYST, 1);
3540
3541 /* Set up min, max, and cur for interrupt handling */
3542 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3543 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3544 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3545 MEMMODE_FSTART_SHIFT;
3546
3547 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3548 PXVFREQ_PX_SHIFT;
3549
20e4d407
DV		 3550 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3551 dev_priv->ips.fstart = fstart;
2b4e57bd 3552
20e4d407
DV		 3553 dev_priv->ips.max_delay = fstart;
3554 dev_priv->ips.min_delay = fmin;
3555 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3556
3557 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3558 fmax, fmin, fstart);
3559
3560 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3561
3562 /*
3563 * Interrupts will be enabled in ironlake_irq_postinstall
3564 */
3565
3566 I915_WRITE(VIDSTART, vstart);
3567 POSTING_READ(VIDSTART);
3568
3569 rgvmodectl |= MEMMODE_SWMODE_EN;
3570 I915_WRITE(MEMMODECTL, rgvmodectl);
3571
9270388e 3572 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3573 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3574 mdelay(1);
2b4e57bd
ED		 3575
3576 ironlake_set_drps(dev, fstart);
3577
20e4d407 3578 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3579 I915_READ(0x112e0);
20e4d407
DV		 3580 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3581 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3582 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3583
3584 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3585}
3586
8090c6b9 3587static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3588{
3589 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3590 u16 rgvswctl;
3591
3592 spin_lock_irq(&mchdev_lock);
3593
3594 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3595
3596 /* Ack interrupts, disable EFC interrupt */
3597 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3598 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3599 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3600 I915_WRITE(DEIIR, DE_PCU_EVENT);
3601 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3602
3603 /* Go back to the starting frequency */
20e4d407 3604 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3605 mdelay(1);
2b4e57bd
ED		 3606 rgvswctl |= MEMCTL_CMD_STS;
3607 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3608 mdelay(1);
2b4e57bd 3609
9270388e 3610 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3611}
3612
acbe9475
DV		 3613/* There's a funny hw issue where the hw returns all 0 when reading from
3614 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3615 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3616 * all limits and the gpu stuck at whatever frequency it is at atm).
3617 */
6917c7b9 3618static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3619{
7b9e0ae6 3620 u32 limits;
2b4e57bd 3621
20b46e59
DV		 3622 /* Only set the down limit when we've reached the lowest level to avoid
3623 * getting more interrupts, otherwise leave this clear. This prevents a
3624 * race in the hw when coming out of rc6: There's a tiny window where
3625 * the hw runs at the minimal clock before selecting the desired
3626 * frequency, if the down threshold expires in that window we will not
3627 * receive a down interrupt. */
b39fb297
BW		 3628 limits = dev_priv->rps.max_freq_softlimit << 24;
3629 if (val <= dev_priv->rps.min_freq_softlimit)
3630 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3631
3632 return limits;
3633}
3634
dd75fdc8
CW		 3635static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3636{
3637 int new_power;
3638
3639 new_power = dev_priv->rps.power;
3640 switch (dev_priv->rps.power) {
3641 case LOW_POWER:
b39fb297 3642 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3643 new_power = BETWEEN;
3644 break;
3645
3646 case BETWEEN:
b39fb297 3647 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3648 new_power = LOW_POWER;
b39fb297 3649 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3650 new_power = HIGH_POWER;
3651 break;
3652
3653 case HIGH_POWER:
b39fb297 3654 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3655 new_power = BETWEEN;
3656 break;
3657 }
3658 /* Max/min bins are special */
b39fb297 3659 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3660 new_power = LOW_POWER;
b39fb297 3661 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3662 new_power = HIGH_POWER;
3663 if (new_power == dev_priv->rps.power)
3664 return;
3665
3666 /* Note the units here are not exactly 1us, but 1280ns. */
3667 switch (new_power) {
3668 case LOW_POWER:
3669 /* Upclock if more than 95% busy over 16ms */
3670 I915_WRITE(GEN6_RP_UP_EI, 12500);
3671 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3672
3673 /* Downclock if less than 85% busy over 32ms */
3674 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3675 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3676
3677 I915_WRITE(GEN6_RP_CONTROL,
3678 GEN6_RP_MEDIA_TURBO |
3679 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3680 GEN6_RP_MEDIA_IS_GFX |
3681 GEN6_RP_ENABLE |
3682 GEN6_RP_UP_BUSY_AVG |
3683 GEN6_RP_DOWN_IDLE_AVG);
3684 break;
3685
3686 case BETWEEN:
3687 /* Upclock if more than 90% busy over 13ms */
3688 I915_WRITE(GEN6_RP_UP_EI, 10250);
3689 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3690
3691 /* Downclock if less than 75% busy over 32ms */
3692 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3693 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3694
3695 I915_WRITE(GEN6_RP_CONTROL,
3696 GEN6_RP_MEDIA_TURBO |
3697 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3698 GEN6_RP_MEDIA_IS_GFX |
3699 GEN6_RP_ENABLE |
3700 GEN6_RP_UP_BUSY_AVG |
3701 GEN6_RP_DOWN_IDLE_AVG);
3702 break;
3703
3704 case HIGH_POWER:
3705 /* Upclock if more than 85% busy over 10ms */
3706 I915_WRITE(GEN6_RP_UP_EI, 8000);
3707 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3708
3709 /* Downclock if less than 60% busy over 32ms */
3710 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3711 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3712
3713 I915_WRITE(GEN6_RP_CONTROL,
3714 GEN6_RP_MEDIA_TURBO |
3715 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3716 GEN6_RP_MEDIA_IS_GFX |
3717 GEN6_RP_ENABLE |
3718 GEN6_RP_UP_BUSY_AVG |
3719 GEN6_RP_DOWN_IDLE_AVG);
3720 break;
3721 }
3722
3723 dev_priv->rps.power = new_power;
3724 dev_priv->rps.last_adj = 0;
3725}
3726
2876ce73
CW		 3727static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3728{
3729 u32 mask = 0;
3730
3731 if (val > dev_priv->rps.min_freq_softlimit)
3732 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3733 if (val < dev_priv->rps.max_freq_softlimit)
3734 mask |= GEN6_PM_RP_UP_THRESHOLD;
3735
7b3c29f6
CW		 3736 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3737 mask &= dev_priv->pm_rps_events;
3738
59d02a1f 3739 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 3740}
3741
b8a5ff8d
JM		 3742/* gen6_set_rps is called to update the frequency request, but should also be
3743 * called when the range (min_delay and max_delay) is modified so that we can
3744 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 3745static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 3746{
3747 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3748
4fc688ce 3749 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3750 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3751 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3752
eb64cad1
CW		 3753 /* min/max delay may still have been modified so be sure to
3754 * write the limits value.
3755 */
3756 if (val != dev_priv->rps.cur_freq) {
3757 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3758
50e6a2a7 3759 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3760 I915_WRITE(GEN6_RPNSWREQ,
3761 HSW_FREQUENCY(val));
3762 else
3763 I915_WRITE(GEN6_RPNSWREQ,
3764 GEN6_FREQUENCY(val) |
3765 GEN6_OFFSET(0) |
3766 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3767 }
7b9e0ae6 3768
7b9e0ae6
CW		 3769 /* Make sure we continue to get interrupts
3770 * until we hit the minimum or maximum frequencies.
3771 */
eb64cad1 3772 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3773 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3774
d5570a72
BW		 3775 POSTING_READ(GEN6_RPNSWREQ);
3776
b39fb297 3777 dev_priv->rps.cur_freq = val;
be2cde9a 3778 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3779}
3780
ffe02b40
VS		 3781static void valleyview_set_rps(struct drm_device *dev, u8 val)
3782{
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784
3785 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3786 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3787 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3788
3789 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3790 "Odd GPU freq value\n"))
3791 val &= ~1;
3792
3793 if (val != dev_priv->rps.cur_freq)
3794 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3795
3796 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3797
3798 dev_priv->rps.cur_freq = val;
3799 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
3800}
3801
76c3552f
D		 3802/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3803 *
3804 * * If Gfx is Idle, then
3805 * 1. Mask Turbo interrupts
3806 * 2. Bring up Gfx clock
3807 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3808 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3809 * 5. Unmask Turbo interrupts
3810*/
3811static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3812{
5549d25f
D		 3813 struct drm_device *dev = dev_priv->dev;
3814
21a11fff
VS		 3815 /* CHV and latest VLV don't need to force the gfx clock */
3816 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
5549d25f
D		 3817 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3818 return;
3819 }
3820
76c3552f
D		 3821 /*
3822 * When we are idle. Drop to min voltage state.
3823 */
3824
b39fb297 3825 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3826 return;
3827
3828 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 3829 I915_WRITE(GEN6_PMINTRMSK,
3830 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 3831
650ad970 3832 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3833
b39fb297 3834 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3835
3836 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3837 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3838
3839 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 3840 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 3841 DRM_ERROR("timed out waiting for Punit\n");
3842
650ad970 3843 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3844
2876ce73
CW		 3845 I915_WRITE(GEN6_PMINTRMSK,
3846 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3847}
3848
b29c19b6
CW		 3849void gen6_rps_idle(struct drm_i915_private *dev_priv)
3850{
691bb717
DL		 3851 struct drm_device *dev = dev_priv->dev;
3852
b29c19b6 3853 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3854 if (dev_priv->rps.enabled) {
21a11fff 3855 if (IS_VALLEYVIEW(dev))
76c3552f 3856 vlv_set_rps_idle(dev_priv);
7526ed79 3857 else
b39fb297 3858 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3859 dev_priv->rps.last_adj = 0;
3860 }
b29c19b6
CW		 3861 mutex_unlock(&dev_priv->rps.hw_lock);
3862}
3863
3864void gen6_rps_boost(struct drm_i915_private *dev_priv)
3865{
3866 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3867 if (dev_priv->rps.enabled) {
ffe02b40 3868 intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3869 dev_priv->rps.last_adj = 0;
3870 }
b29c19b6
CW		 3871 mutex_unlock(&dev_priv->rps.hw_lock);
3872}
3873
ffe02b40 3874void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 3875{
ffe02b40
VS		 3876 if (IS_VALLEYVIEW(dev))
3877 valleyview_set_rps(dev, val);
3878 else
3879 gen6_set_rps(dev, val);
0a073b84
JB		 3880}
3881
20e49366
ZW		 3882static void gen9_disable_rps(struct drm_device *dev)
3883{
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885
3886 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 3887 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 3888}
3889
44fc7d5c 3890static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3891{
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3895 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 3896}
3897
38807746
D		 3898static void cherryview_disable_rps(struct drm_device *dev)
3899{
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901
3902 I915_WRITE(GEN6_RC_CONTROL, 0);
3903}
3904
44fc7d5c
DV		 3905static void valleyview_disable_rps(struct drm_device *dev)
3906{
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908
98a2e5f9
D		 3909 /* we're doing forcewake before Disabling RC6,
3910 * This what the BIOS expects when going into suspend */
59bad947 3911 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 3912
44fc7d5c 3913 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3914
59bad947 3915 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 3916}
3917
dc39fff7
BW		 3918static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3919{
91ca689a
ID		 3920 if (IS_VALLEYVIEW(dev)) {
3921 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3922 mode = GEN6_RC_CTL_RC6_ENABLE;
3923 else
3924 mode = 0;
3925 }
58abf1da
RV		 3926 if (HAS_RC6p(dev))
3927 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
3928 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3929 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3930 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3931
3932 else
3933 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
3934 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 3935}
3936
e6069ca8 3937static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3938{
eb4926e4
DL		 3939 /* No RC6 before Ironlake */
3940 if (INTEL_INFO(dev)->gen < 5)
3941 return 0;
3942
e6069ca8
ID		 3943 /* RC6 is only on Ironlake mobile not on desktop */
3944 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3945 return 0;
3946
456470eb 3947 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3948 if (enable_rc6 >= 0) {
3949 int mask;
3950
58abf1da 3951 if (HAS_RC6p(dev))
e6069ca8
ID		 3952 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3953 INTEL_RC6pp_ENABLE;
3954 else
3955 mask = INTEL_RC6_ENABLE;
3956
3957 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 3958 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3959 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3960
3961 return enable_rc6 & mask;
3962 }
2b4e57bd 3963
6567d748
CW		 3964 /* Disable RC6 on Ironlake */
3965 if (INTEL_INFO(dev)->gen == 5)
3966 return 0;
2b4e57bd 3967
8bade1ad 3968 if (IS_IVYBRIDGE(dev))
cca84a1f 3969 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3970
3971 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3972}
3973
e6069ca8
ID		 3974int intel_enable_rc6(const struct drm_device *dev)
3975{
3976 return i915.enable_rc6;
3977}
3978
93ee2920 3979static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 3980{
93ee2920
TR		 3981 struct drm_i915_private *dev_priv = dev->dev_private;
3982 uint32_t rp_state_cap;
3983 u32 ddcc_status = 0;
3984 int ret;
3985
3986 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 3987 /* All of these values are in units of 50MHz */
3988 dev_priv->rps.cur_freq = 0;
93ee2920 3989 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 3990 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 3991 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 3992 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3280e8b0
BW		 3993 /* hw_max = RP0 until we check for overclocking */
3994 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3995
93ee2920
TR		 3996 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3997 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3998 ret = sandybridge_pcode_read(dev_priv,
3999 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4000 &ddcc_status);
4001 if (0 == ret)
4002 dev_priv->rps.efficient_freq =
4003 (ddcc_status >> 8) & 0xff;
4004 }
4005
3280e8b0
BW		 4006 /* Preserve min/max settings in case of re-init */
4007 if (dev_priv->rps.max_freq_softlimit == 0)
4008 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4009
93ee2920
TR		 4010 if (dev_priv->rps.min_freq_softlimit == 0) {
4011 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4012 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR		 4013 /* max(RPe, 450 MHz) */
4014 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR		 4015 else
4016 dev_priv->rps.min_freq_softlimit =
4017 dev_priv->rps.min_freq;
4018 }
3280e8b0
BW		 4019}
4020
b6fef0ef 4021/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4022static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4023{
4024 struct drm_i915_private *dev_priv = dev->dev_private;
4025
4026 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4027
ba1c554c
DL		 4028 gen6_init_rps_frequencies(dev);
4029
b6fef0ef
JB		 4030 I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
4031 I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
4032
4033 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4034 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
4035 I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
4036 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
4037 I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
4038 I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
4039 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4040 I915_WRITE(GEN6_PMINTRMSK, 0x6);
4041 I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
4042 GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
4043 GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
4044 GEN6_RP_DOWN_IDLE_AVG);
4045
4046 gen6_enable_rps_interrupts(dev);
4047
4048 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4049}
4050
4051static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4052{
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 struct intel_engine_cs *ring;
4055 uint32_t rc6_mask = 0;
4056 int unused;
4057
4058 /* 1a: Software RC state - RC0 */
4059 I915_WRITE(GEN6_RC_STATE, 0);
4060
4061 /* 1b: Get forcewake during program sequence. Although the driver
4062 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4063 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4064
4065 /* 2a: Disable RC states. */
4066 I915_WRITE(GEN6_RC_CONTROL, 0);
4067
4068 /* 2b: Program RC6 thresholds.*/
4069 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4070 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4071 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4072 for_each_ring(ring, dev_priv, unused)
4073 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4074 I915_WRITE(GEN6_RC_SLEEP, 0);
4075 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4076
38c23527
ZW		 4077 /* 2c: Program Coarse Power Gating Policies. */
4078 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4079 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4080
20e49366
ZW		 4081 /* 3a: Enable RC6 */
4082 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4083 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4084 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4085 "on" : "off");
4086 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4087 GEN6_RC_CTL_EI_MODE(1) |
4088 rc6_mask);
4089
38c23527
ZW		 4090 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4091 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4092
59bad947 4093 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4094
4095}
4096
6edee7f3
BW		 4097static void gen8_enable_rps(struct drm_device *dev)
4098{
4099 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4100 struct intel_engine_cs *ring;
93ee2920 4101 uint32_t rc6_mask = 0;
6edee7f3
BW		 4102 int unused;
4103
4104 /* 1a: Software RC state - RC0 */
4105 I915_WRITE(GEN6_RC_STATE, 0);
4106
4107 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4108 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4109 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4110
4111 /* 2a: Disable RC states. */
4112 I915_WRITE(GEN6_RC_CONTROL, 0);
4113
93ee2920
TR		 4114 /* Initialize rps frequencies */
4115 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4116
4117 /* 2b: Program RC6 thresholds.*/
4118 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4119 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4120 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4121 for_each_ring(ring, dev_priv, unused)
4122 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4123 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4124 if (IS_BROADWELL(dev))
4125 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4126 else
4127 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4128
4129 /* 3: Enable RC6 */
4130 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4131 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4132 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4133 if (IS_BROADWELL(dev))
4134 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4135 GEN7_RC_CTL_TO_MODE |
4136 rc6_mask);
4137 else
4138 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4139 GEN6_RC_CTL_EI_MODE(1) |
4140 rc6_mask);
6edee7f3
BW		 4141
4142 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4143 I915_WRITE(GEN6_RPNSWREQ,
4144 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4145 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4146 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4147 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4148 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4149
4150 /* Docs recommend 900MHz, and 300 MHz respectively */
4151 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4152 dev_priv->rps.max_freq_softlimit << 24 |
4153 dev_priv->rps.min_freq_softlimit << 16);
4154
4155 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4156 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4157 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4158 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4159
4160 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4161
4162 /* 5: Enable RPS */
7526ed79
DV		 4163 I915_WRITE(GEN6_RP_CONTROL,
4164 GEN6_RP_MEDIA_TURBO |
4165 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4166 GEN6_RP_MEDIA_IS_GFX |
4167 GEN6_RP_ENABLE |
4168 GEN6_RP_UP_BUSY_AVG |
4169 GEN6_RP_DOWN_IDLE_AVG);
4170
4171 /* 6: Ring frequency + overclocking (our driver does this later */
4172
c7f3153a
TR		 4173 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4174 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
7526ed79 4175
59bad947 4176 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4177}
4178
79f5b2c7 4179static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4180{
79f5b2c7 4181 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4182 struct intel_engine_cs *ring;
d060c169 4183 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4184 u32 gtfifodbg;
2b4e57bd 4185 int rc6_mode;
42c0526c 4186 int i, ret;
2b4e57bd 4187
4fc688ce 4188 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4189
2b4e57bd
ED		 4190 /* Here begins a magic sequence of register writes to enable
4191 * auto-downclocking.
4192 *
4193 * Perhaps there might be some value in exposing these to
4194 * userspace...
4195 */
4196 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4197
4198 /* Clear the DBG now so we don't confuse earlier errors */
4199 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4200 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4201 I915_WRITE(GTFIFODBG, gtfifodbg);
4202 }
4203
59bad947 4204 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4205
93ee2920
TR		 4206 /* Initialize rps frequencies */
4207 gen6_init_rps_frequencies(dev);
dd0a1aa1 4208
2b4e57bd
ED		 4209 /* disable the counters and set deterministic thresholds */
4210 I915_WRITE(GEN6_RC_CONTROL, 0);
4211
4212 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4213 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4214 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4215 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4216 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4217
b4519513
CW		 4218 for_each_ring(ring, dev_priv, i)
4219 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4220
4221 I915_WRITE(GEN6_RC_SLEEP, 0);
4222 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4223 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4224 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4225 else
4226 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4227 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4228 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4229
5a7dc92a 4230 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4231 rc6_mode = intel_enable_rc6(dev_priv->dev);
4232 if (rc6_mode & INTEL_RC6_ENABLE)
4233 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4234
5a7dc92a
ED		 4235 /* We don't use those on Haswell */
4236 if (!IS_HASWELL(dev)) {
4237 if (rc6_mode & INTEL_RC6p_ENABLE)
4238 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4239
5a7dc92a
ED		 4240 if (rc6_mode & INTEL_RC6pp_ENABLE)
4241 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4242 }
2b4e57bd 4243
dc39fff7 4244 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4245
4246 I915_WRITE(GEN6_RC_CONTROL,
4247 rc6_mask |
4248 GEN6_RC_CTL_EI_MODE(1) |
4249 GEN6_RC_CTL_HW_ENABLE);
4250
dd75fdc8
CW		 4251 /* Power down if completely idle for over 50ms */
4252 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4253 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4254
42c0526c 4255 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4256 if (ret)
42c0526c 4257 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4258
4259 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4260 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4261 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4262 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4263 (pcu_mbox & 0xff) * 50);
b39fb297 4264 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4265 }
4266
dd75fdc8 4267 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 4268 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 4269
31643d54
BW		 4270 rc6vids = 0;
4271 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4272 if (IS_GEN6(dev) && ret) {
4273 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4274 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4275 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4276 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4277 rc6vids &= 0xffff00;
4278 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4279 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4280 if (ret)
4281 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4282 }
4283
59bad947 4284 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4285}
4286
c2bc2fc5 4287static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4288{
79f5b2c7 4289 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4290 int min_freq = 15;
3ebecd07
CW		 4291 unsigned int gpu_freq;
4292 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4293 int scaling_factor = 180;
eda79642 4294 struct cpufreq_policy *policy;
2b4e57bd 4295
4fc688ce 4296 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4297
eda79642
BW		 4298 policy = cpufreq_cpu_get(0);
4299 if (policy) {
4300 max_ia_freq = policy->cpuinfo.max_freq;
4301 cpufreq_cpu_put(policy);
4302 } else {
4303 /*
4304 * Default to measured freq if none found, PCU will ensure we
4305 * don't go over
4306 */
2b4e57bd 4307 max_ia_freq = tsc_khz;
eda79642 4308 }
2b4e57bd
ED		 4309
4310 /* Convert from kHz to MHz */
4311 max_ia_freq /= 1000;
4312
153b4b95 4313 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4314 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4315 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4316
2b4e57bd
ED		 4317 /*
4318 * For each potential GPU frequency, load a ring frequency we'd like
4319 * to use for memory access. We do this by specifying the IA frequency
4320 * the PCU should use as a reference to determine the ring frequency.
4321 */
6985b352 4322 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4323 gpu_freq--) {
6985b352 4324 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4325 unsigned int ia_freq = 0, ring_freq = 0;
4326
46c764d4
BW		 4327 if (INTEL_INFO(dev)->gen >= 8) {
4328 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4329 ring_freq = max(min_ring_freq, gpu_freq);
4330 } else if (IS_HASWELL(dev)) {
f6aca45c 4331 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4332 ring_freq = max(min_ring_freq, ring_freq);
4333 /* leave ia_freq as the default, chosen by cpufreq */
4334 } else {
4335 /* On older processors, there is no separate ring
4336 * clock domain, so in order to boost the bandwidth
4337 * of the ring, we need to upclock the CPU (ia_freq).
4338 *
4339 * For GPU frequencies less than 750MHz,
4340 * just use the lowest ring freq.
4341 */
4342 if (gpu_freq < min_freq)
4343 ia_freq = 800;
4344 else
4345 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4346 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4347 }
2b4e57bd 4348
42c0526c
BW		 4349 sandybridge_pcode_write(dev_priv,
4350 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4351 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4352 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4353 gpu_freq);
2b4e57bd 4354 }
2b4e57bd
ED		 4355}
4356
c2bc2fc5
ID		 4357void gen6_update_ring_freq(struct drm_device *dev)
4358{
4359 struct drm_i915_private *dev_priv = dev->dev_private;
4360
4361 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4362 return;
4363
4364 mutex_lock(&dev_priv->rps.hw_lock);
4365 __gen6_update_ring_freq(dev);
4366 mutex_unlock(&dev_priv->rps.hw_lock);
4367}
4368
03af2045 4369static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4370{
095acd5f 4371 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4372 u32 val, rp0;
4373
095acd5f
D		 4374 if (dev->pdev->revision >= 0x20) {
4375 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4376
095acd5f
D		 4377 switch (INTEL_INFO(dev)->eu_total) {
4378 case 8:
4379 /* (2 * 4) config */
4380 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4381 break;
4382 case 12:
4383 /* (2 * 6) config */
4384 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4385 break;
4386 case 16:
4387 /* (2 * 8) config */
4388 default:
4389 /* Setting (2 * 8) Min RP0 for any other combination */
4390 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4391 break;
4392 }
4393 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4394 } else {
4395 /* For pre-production hardware */
4396 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4397 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4398 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4399 }
2b6b3a09
D		 4400 return rp0;
4401}
4402
4403static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4404{
4405 u32 val, rpe;
4406
4407 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4408 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4409
4410 return rpe;
4411}
4412
7707df4a
D		 4413static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4414{
095acd5f 4415 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4416 u32 val, rp1;
4417
095acd5f
D		 4418 if (dev->pdev->revision >= 0x20) {
4419 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4420 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4421 } else {
4422 /* For pre-production hardware */
4423 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4424 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4425 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4426 }
7707df4a
D		 4427 return rp1;
4428}
4429
03af2045 4430static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4431{
095acd5f 4432 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4433 u32 val, rpn;
4434
095acd5f
D		 4435 if (dev->pdev->revision >= 0x20) {
4436 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4437 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4438 FB_GFX_FREQ_FUSE_MASK);
4439 } else { /* For pre-production hardware */
4440 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4441 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4442 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4443 }
4444
2b6b3a09
D		 4445 return rpn;
4446}
4447
f8f2b001
D		 4448static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4449{
4450 u32 val, rp1;
4451
4452 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4453
4454 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4455
4456 return rp1;
4457}
4458
03af2045 4459static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4460{
4461 u32 val, rp0;
4462
64936258 4463 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4464
4465 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4466 /* Clamp to max */
4467 rp0 = min_t(u32, rp0, 0xea);
4468
4469 return rp0;
4470}
4471
4472static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4473{
4474 u32 val, rpe;
4475
64936258 4476 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4477 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4478 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4479 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4480
4481 return rpe;
4482}
4483
03af2045 4484static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4485{
64936258 4486 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4487}
4488
ae48434c
ID		 4489/* Check that the pctx buffer wasn't move under us. */
4490static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4491{
4492 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4493
4494 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4495 dev_priv->vlv_pctx->stolen->start);
4496}
4497
38807746
D		 4498
4499/* Check that the pcbr address is not empty. */
4500static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4501{
4502 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4503
4504 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4505}
4506
4507static void cherryview_setup_pctx(struct drm_device *dev)
4508{
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510 unsigned long pctx_paddr, paddr;
4511 struct i915_gtt *gtt = &dev_priv->gtt;
4512 u32 pcbr;
4513 int pctx_size = 32*1024;
4514
4515 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4516
4517 pcbr = I915_READ(VLV_PCBR);
4518 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4519 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4520 paddr = (dev_priv->mm.stolen_base +
4521 (gtt->stolen_size - pctx_size));
4522
4523 pctx_paddr = (paddr & (~4095));
4524 I915_WRITE(VLV_PCBR, pctx_paddr);
4525 }
ce611ef8
VS		 4526
4527 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4528}
4529
c9cddffc
JB		 4530static void valleyview_setup_pctx(struct drm_device *dev)
4531{
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 struct drm_i915_gem_object *pctx;
4534 unsigned long pctx_paddr;
4535 u32 pcbr;
4536 int pctx_size = 24*1024;
4537
17b0c1f7
ID		 4538 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4539
c9cddffc
JB		 4540 pcbr = I915_READ(VLV_PCBR);
4541 if (pcbr) {
4542 /* BIOS set it up already, grab the pre-alloc'd space */
4543 int pcbr_offset;
4544
4545 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4546 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4547 pcbr_offset,
190d6cd5 4548 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4549 pctx_size);
4550 goto out;
4551 }
4552
ce611ef8
VS		 4553 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4554
c9cddffc
JB		 4555 /*
4556 * From the Gunit register HAS:
4557 * The Gfx driver is expected to program this register and ensure
4558 * proper allocation within Gfx stolen memory. For example, this
4559 * register should be programmed such than the PCBR range does not
4560 * overlap with other ranges, such as the frame buffer, protected
4561 * memory, or any other relevant ranges.
4562 */
4563 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4564 if (!pctx) {
4565 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4566 return;
4567 }
4568
4569 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4570 I915_WRITE(VLV_PCBR, pctx_paddr);
4571
4572out:
ce611ef8 4573 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4574 dev_priv->vlv_pctx = pctx;
4575}
4576
ae48434c
ID		 4577static void valleyview_cleanup_pctx(struct drm_device *dev)
4578{
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580
4581 if (WARN_ON(!dev_priv->vlv_pctx))
4582 return;
4583
4584 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4585 dev_priv->vlv_pctx = NULL;
4586}
4587
4e80519e
ID		 4588static void valleyview_init_gt_powersave(struct drm_device *dev)
4589{
4590 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4591 u32 val;
4e80519e
ID		 4592
4593 valleyview_setup_pctx(dev);
4594
4595 mutex_lock(&dev_priv->rps.hw_lock);
4596
2bb25c17
VS		 4597 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4598 switch ((val >> 6) & 3) {
4599 case 0:
4600 case 1:
4601 dev_priv->mem_freq = 800;
4602 break;
4603 case 2:
4604 dev_priv->mem_freq = 1066;
4605 break;
4606 case 3:
4607 dev_priv->mem_freq = 1333;
4608 break;
4609 }
80b83b62 4610 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4611
4e80519e
ID		 4612 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4613 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4614 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4615 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4616 dev_priv->rps.max_freq);
4617
4618 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4619 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4620 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4621 dev_priv->rps.efficient_freq);
4622
f8f2b001
D		 4623 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4624 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4625 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4626 dev_priv->rps.rp1_freq);
4627
4e80519e
ID		 4628 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4629 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4630 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4631 dev_priv->rps.min_freq);
4632
4633 /* Preserve min/max settings in case of re-init */
4634 if (dev_priv->rps.max_freq_softlimit == 0)
4635 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4636
4637 if (dev_priv->rps.min_freq_softlimit == 0)
4638 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4639
4640 mutex_unlock(&dev_priv->rps.hw_lock);
4641}
4642
38807746
D		 4643static void cherryview_init_gt_powersave(struct drm_device *dev)
4644{
2b6b3a09 4645 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4646 u32 val;
2b6b3a09 4647
38807746 4648 cherryview_setup_pctx(dev);
2b6b3a09
D		 4649
4650 mutex_lock(&dev_priv->rps.hw_lock);
4651
c6e8f39d
VS		 4652 mutex_lock(&dev_priv->dpio_lock);
4653 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4654 mutex_unlock(&dev_priv->dpio_lock);
4655
2bb25c17
VS		 4656 switch ((val >> 2) & 0x7) {
4657 case 0:
4658 case 1:
4659 dev_priv->rps.cz_freq = 200;
4660 dev_priv->mem_freq = 1600;
4661 break;
4662 case 2:
4663 dev_priv->rps.cz_freq = 267;
4664 dev_priv->mem_freq = 1600;
4665 break;
4666 case 3:
4667 dev_priv->rps.cz_freq = 333;
4668 dev_priv->mem_freq = 2000;
4669 break;
4670 case 4:
4671 dev_priv->rps.cz_freq = 320;
4672 dev_priv->mem_freq = 1600;
4673 break;
4674 case 5:
4675 dev_priv->rps.cz_freq = 400;
4676 dev_priv->mem_freq = 1600;
4677 break;
4678 }
80b83b62 4679 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4680
2b6b3a09
D		 4681 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4682 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4683 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4684 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 4685 dev_priv->rps.max_freq);
4686
4687 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4688 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4689 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4690 dev_priv->rps.efficient_freq);
4691
7707df4a
D		 4692 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4693 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 4694 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 4695 dev_priv->rps.rp1_freq);
4696
2b6b3a09
D		 4697 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4698 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4699 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 4700 dev_priv->rps.min_freq);
4701
1c14762d
VS		 4702 WARN_ONCE((dev_priv->rps.max_freq |
4703 dev_priv->rps.efficient_freq |
4704 dev_priv->rps.rp1_freq |
4705 dev_priv->rps.min_freq) & 1,
4706 "Odd GPU freq values\n");
4707
2b6b3a09
D		 4708 /* Preserve min/max settings in case of re-init */
4709 if (dev_priv->rps.max_freq_softlimit == 0)
4710 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4711
4712 if (dev_priv->rps.min_freq_softlimit == 0)
4713 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4714
4715 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4716}
4717
4e80519e
ID		 4718static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4719{
4720 valleyview_cleanup_pctx(dev);
4721}
4722
38807746
D		 4723static void cherryview_enable_rps(struct drm_device *dev)
4724{
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726 struct intel_engine_cs *ring;
2b6b3a09 4727 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4728 int i;
4729
4730 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4731
4732 gtfifodbg = I915_READ(GTFIFODBG);
4733 if (gtfifodbg) {
4734 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4735 gtfifodbg);
4736 I915_WRITE(GTFIFODBG, gtfifodbg);
4737 }
4738
4739 cherryview_check_pctx(dev_priv);
4740
4741 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4742 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4743 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 4744
160614a2
VS		 4745 /* Disable RC states. */
4746 I915_WRITE(GEN6_RC_CONTROL, 0);
4747
38807746
D		 4748 /* 2a: Program RC6 thresholds.*/
4749 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4750 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4751 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4752
4753 for_each_ring(ring, dev_priv, i)
4754 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4755 I915_WRITE(GEN6_RC_SLEEP, 0);
4756
af5a75a3
VS		 4757 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4758 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D		 4759
4760 /* allows RC6 residency counter to work */
4761 I915_WRITE(VLV_COUNTER_CONTROL,
4762 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4763 VLV_MEDIA_RC6_COUNT_EN |
4764 VLV_RENDER_RC6_COUNT_EN));
4765
4766 /* For now we assume BIOS is allocating and populating the PCBR */
4767 pcbr = I915_READ(VLV_PCBR);
4768
38807746
D		 4769 /* 3: Enable RC6 */
4770 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4771 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 4772 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 4773
4774 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4775
2b6b3a09 4776 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 4777 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 4778 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4779 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4780 I915_WRITE(GEN6_RP_UP_EI, 66000);
4781 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4782
4783 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4784
4785 /* 5: Enable RPS */
4786 I915_WRITE(GEN6_RP_CONTROL,
4787 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 4788 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 4789 GEN6_RP_ENABLE |
4790 GEN6_RP_UP_BUSY_AVG |
4791 GEN6_RP_DOWN_IDLE_AVG);
4792
4793 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4794
8d40c3ae
VS		 4795 /* RPS code assumes GPLL is used */
4796 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4797
c8e9627d 4798 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 4799 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4800
4801 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4802 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 4803 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 4804 dev_priv->rps.cur_freq);
4805
4806 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 4807 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4808 dev_priv->rps.efficient_freq);
4809
4810 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4811
59bad947 4812 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 4813}
4814
0a073b84
JB		 4815static void valleyview_enable_rps(struct drm_device *dev)
4816{
4817 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4818 struct intel_engine_cs *ring;
2a5913a8 4819 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4820 int i;
4821
4822 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4823
ae48434c
ID		 4824 valleyview_check_pctx(dev_priv);
4825
0a073b84 4826 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4827 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4828 gtfifodbg);
0a073b84
JB		 4829 I915_WRITE(GTFIFODBG, gtfifodbg);
4830 }
4831
c8d9a590 4832 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 4833 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 4834
160614a2
VS		 4835 /* Disable RC states. */
4836 I915_WRITE(GEN6_RC_CONTROL, 0);
4837
cad725fe 4838 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 4839 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4840 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4841 I915_WRITE(GEN6_RP_UP_EI, 66000);
4842 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4843
4844 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4845
4846 I915_WRITE(GEN6_RP_CONTROL,
4847 GEN6_RP_MEDIA_TURBO |
4848 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4849 GEN6_RP_MEDIA_IS_GFX |
4850 GEN6_RP_ENABLE |
4851 GEN6_RP_UP_BUSY_AVG |
4852 GEN6_RP_DOWN_IDLE_CONT);
4853
4854 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4855 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4856 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4857
4858 for_each_ring(ring, dev_priv, i)
4859 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4860
2f0aa304 4861 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4862
4863 /* allows RC6 residency counter to work */
49798eb2 4864 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4865 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4866 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4867 VLV_MEDIA_RC6_COUNT_EN |
4868 VLV_RENDER_RC6_COUNT_EN));
31685c25 4869
a2b23fe0 4870 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4871 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4872
4873 intel_print_rc6_info(dev, rc6_mode);
4874
a2b23fe0 4875 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4876
64936258 4877 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 4878
8d40c3ae
VS		 4879 /* RPS code assumes GPLL is used */
4880 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4881
c8e9627d 4882 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 4883 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4884
b39fb297 4885 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4886 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 4887 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 4888 dev_priv->rps.cur_freq);
0a073b84 4889
73008b98 4890 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 4891 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 4892 dev_priv->rps.efficient_freq);
0a073b84 4893
b39fb297 4894 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4895
59bad947 4896 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4897}
4898
930ebb46 4899void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4900{
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902
3e373948 4903 if (dev_priv->ips.renderctx) {
d7f46fc4 4904 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4905 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4906 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4907 }
4908
3e373948 4909 if (dev_priv->ips.pwrctx) {
d7f46fc4 4910 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4911 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4912 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4913 }
4914}
4915
930ebb46 4916static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4917{
4918 struct drm_i915_private *dev_priv = dev->dev_private;
4919
4920 if (I915_READ(PWRCTXA)) {
4921 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4922 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4923 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4924 50);
4925
4926 I915_WRITE(PWRCTXA, 0);
4927 POSTING_READ(PWRCTXA);
4928
4929 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4930 POSTING_READ(RSTDBYCTL);
4931 }
2b4e57bd
ED		 4932}
4933
4934static int ironlake_setup_rc6(struct drm_device *dev)
4935{
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937
3e373948
DV		 4938 if (dev_priv->ips.renderctx == NULL)
4939 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4940 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4941 return -ENOMEM;
4942
3e373948
DV		 4943 if (dev_priv->ips.pwrctx == NULL)
4944 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4945 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4946 ironlake_teardown_rc6(dev);
4947 return -ENOMEM;
4948 }
4949
4950 return 0;
4951}
4952
930ebb46 4953static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4954{
4955 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4956 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4957 bool was_interruptible;
2b4e57bd
ED		 4958 int ret;
4959
4960 /* rc6 disabled by default due to repeated reports of hanging during
4961 * boot and resume.
4962 */
4963 if (!intel_enable_rc6(dev))
4964 return;
4965
79f5b2c7
DV		 4966 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4967
2b4e57bd 4968 ret = ironlake_setup_rc6(dev);
79f5b2c7 4969 if (ret)
2b4e57bd 4970 return;
2b4e57bd 4971
3e960501
CW		 4972 was_interruptible = dev_priv->mm.interruptible;
4973 dev_priv->mm.interruptible = false;
4974
2b4e57bd
ED		 4975 /*
4976 * GPU can automatically power down the render unit if given a page
4977 * to save state.
4978 */
6d90c952 4979 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4980 if (ret) {
4981 ironlake_teardown_rc6(dev);
3e960501 4982 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4983 return;
4984 }
4985
6d90c952
DV		 4986 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4987 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4988 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4989 MI_MM_SPACE_GTT |
4990 MI_SAVE_EXT_STATE_EN |
4991 MI_RESTORE_EXT_STATE_EN |
4992 MI_RESTORE_INHIBIT);
4993 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4994 intel_ring_emit(ring, MI_NOOP);
4995 intel_ring_emit(ring, MI_FLUSH);
4996 intel_ring_advance(ring);
2b4e57bd
ED		 4997
4998 /*
4999 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
5000 * does an implicit flush, combined with MI_FLUSH above, it should be
5001 * safe to assume that renderctx is valid
5002 */
3e960501
CW		 5003 ret = intel_ring_idle(ring);
5004 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 5005 if (ret) {
def27a58 5006 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 5007 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 5008 return;
5009 }
5010
f343c5f6 5011 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 5012 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 5013
91ca689a 5014 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 5015}
5016
dde18883
ED		 5017static unsigned long intel_pxfreq(u32 vidfreq)
5018{
5019 unsigned long freq;
5020 int div = (vidfreq & 0x3f0000) >> 16;
5021 int post = (vidfreq & 0x3000) >> 12;
5022 int pre = (vidfreq & 0x7);
5023
5024 if (!pre)
5025 return 0;
5026
5027 freq = ((div * 133333) / ((1<<post) * pre));
5028
5029 return freq;
5030}
5031
eb48eb00
DV		 5032static const struct cparams {
5033 u16 i;
5034 u16 t;
5035 u16 m;
5036 u16 c;
5037} cparams[] = {
5038 { 1, 1333, 301, 28664 },
5039 { 1, 1066, 294, 24460 },
5040 { 1, 800, 294, 25192 },
5041 { 0, 1333, 276, 27605 },
5042 { 0, 1066, 276, 27605 },
5043 { 0, 800, 231, 23784 },
5044};
5045
f531dcb2 5046static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5047{
5048 u64 total_count, diff, ret;
5049 u32 count1, count2, count3, m = 0, c = 0;
5050 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5051 int i;
5052
02d71956
DV		 5053 assert_spin_locked(&mchdev_lock);
5054
20e4d407 5055 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5056
5057 /* Prevent division-by-zero if we are asking too fast.
5058 * Also, we don't get interesting results if we are polling
5059 * faster than once in 10ms, so just return the saved value
5060 * in such cases.
5061 */
5062 if (diff1 <= 10)
20e4d407 5063 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5064
5065 count1 = I915_READ(DMIEC);
5066 count2 = I915_READ(DDREC);
5067 count3 = I915_READ(CSIEC);
5068
5069 total_count = count1 + count2 + count3;
5070
5071 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5072 if (total_count < dev_priv->ips.last_count1) {
5073 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5074 diff += total_count;
5075 } else {
20e4d407 5076 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5077 }
5078
5079 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5080 if (cparams[i].i == dev_priv->ips.c_m &&
5081 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5082 m = cparams[i].m;
5083 c = cparams[i].c;
5084 break;
5085 }
5086 }
5087
5088 diff = div_u64(diff, diff1);
5089 ret = ((m * diff) + c);
5090 ret = div_u64(ret, 10);
5091
20e4d407
DV		 5092 dev_priv->ips.last_count1 = total_count;
5093 dev_priv->ips.last_time1 = now;
eb48eb00 5094
20e4d407 5095 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5096
5097 return ret;
5098}
5099
f531dcb2
CW		 5100unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5101{
3d13ef2e 5102 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5103 unsigned long val;
5104
3d13ef2e 5105 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5106 return 0;
5107
5108 spin_lock_irq(&mchdev_lock);
5109
5110 val = __i915_chipset_val(dev_priv);
5111
5112 spin_unlock_irq(&mchdev_lock);
5113
5114 return val;
5115}
5116
eb48eb00
DV		 5117unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5118{
5119 unsigned long m, x, b;
5120 u32 tsfs;
5121
5122 tsfs = I915_READ(TSFS);
5123
5124 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5125 x = I915_READ8(TR1);
5126
5127 b = tsfs & TSFS_INTR_MASK;
5128
5129 return ((m * x) / 127) - b;
5130}
5131
d972d6ee
MK		 5132static int _pxvid_to_vd(u8 pxvid)
5133{
5134 if (pxvid == 0)
5135 return 0;
5136
5137 if (pxvid >= 8 && pxvid < 31)
5138 pxvid = 31;
5139
5140 return (pxvid + 2) * 125;
5141}
5142
5143static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5144{
3d13ef2e 5145 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5146 const int vd = _pxvid_to_vd(pxvid);
5147 const int vm = vd - 1125;
5148
3d13ef2e 5149 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5150 return vm > 0 ? vm : 0;
5151
5152 return vd;
eb48eb00
DV		 5153}
5154
02d71956 5155static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5156{
5ed0bdf2 5157 u64 now, diff, diffms;
eb48eb00
DV		 5158 u32 count;
5159
02d71956 5160 assert_spin_locked(&mchdev_lock);
eb48eb00 5161
5ed0bdf2
TG		 5162 now = ktime_get_raw_ns();
5163 diffms = now - dev_priv->ips.last_time2;
5164 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5165
5166 /* Don't divide by 0 */
eb48eb00
DV		 5167 if (!diffms)
5168 return;
5169
5170 count = I915_READ(GFXEC);
5171
20e4d407
DV		 5172 if (count < dev_priv->ips.last_count2) {
5173 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5174 diff += count;
5175 } else {
20e4d407 5176 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5177 }
5178
20e4d407
DV		 5179 dev_priv->ips.last_count2 = count;
5180 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5181
5182 /* More magic constants... */
5183 diff = diff * 1181;
5184 diff = div_u64(diff, diffms * 10);
20e4d407 5185 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5186}
5187
02d71956
DV		 5188void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5189{
3d13ef2e
DL		 5190 struct drm_device *dev = dev_priv->dev;
5191
5192 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5193 return;
5194
9270388e 5195 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5196
5197 __i915_update_gfx_val(dev_priv);
5198
9270388e 5199 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5200}
5201
f531dcb2 5202static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5203{
5204 unsigned long t, corr, state1, corr2, state2;
5205 u32 pxvid, ext_v;
5206
02d71956
DV		 5207 assert_spin_locked(&mchdev_lock);
5208
b39fb297 5209 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5210 pxvid = (pxvid >> 24) & 0x7f;
5211 ext_v = pvid_to_extvid(dev_priv, pxvid);
5212
5213 state1 = ext_v;
5214
5215 t = i915_mch_val(dev_priv);
5216
5217 /* Revel in the empirically derived constants */
5218
5219 /* Correction factor in 1/100000 units */
5220 if (t > 80)
5221 corr = ((t * 2349) + 135940);
5222 else if (t >= 50)
5223 corr = ((t * 964) + 29317);
5224 else /* < 50 */
5225 corr = ((t * 301) + 1004);
5226
5227 corr = corr * ((150142 * state1) / 10000 - 78642);
5228 corr /= 100000;
20e4d407 5229 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5230
5231 state2 = (corr2 * state1) / 10000;
5232 state2 /= 100; /* convert to mW */
5233
02d71956 5234 __i915_update_gfx_val(dev_priv);
eb48eb00 5235
20e4d407 5236 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5237}
5238
f531dcb2
CW		 5239unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5240{
3d13ef2e 5241 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5242 unsigned long val;
5243
3d13ef2e 5244 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5245 return 0;
5246
5247 spin_lock_irq(&mchdev_lock);
5248
5249 val = __i915_gfx_val(dev_priv);
5250
5251 spin_unlock_irq(&mchdev_lock);
5252
5253 return val;
5254}
5255
eb48eb00
DV		 5256/**
5257 * i915_read_mch_val - return value for IPS use
5258 *
5259 * Calculate and return a value for the IPS driver to use when deciding whether
5260 * we have thermal and power headroom to increase CPU or GPU power budget.
5261 */
5262unsigned long i915_read_mch_val(void)
5263{
5264 struct drm_i915_private *dev_priv;
5265 unsigned long chipset_val, graphics_val, ret = 0;
5266
9270388e 5267 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5268 if (!i915_mch_dev)
5269 goto out_unlock;
5270 dev_priv = i915_mch_dev;
5271
f531dcb2
CW		 5272 chipset_val = __i915_chipset_val(dev_priv);
5273 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5274
5275 ret = chipset_val + graphics_val;
5276
5277out_unlock:
9270388e 5278 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5279
5280 return ret;
5281}
5282EXPORT_SYMBOL_GPL(i915_read_mch_val);
5283
5284/**
5285 * i915_gpu_raise - raise GPU frequency limit
5286 *
5287 * Raise the limit; IPS indicates we have thermal headroom.
5288 */
5289bool i915_gpu_raise(void)
5290{
5291 struct drm_i915_private *dev_priv;
5292 bool ret = true;
5293
9270388e 5294 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5295 if (!i915_mch_dev) {
5296 ret = false;
5297 goto out_unlock;
5298 }
5299 dev_priv = i915_mch_dev;
5300
20e4d407
DV		 5301 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5302 dev_priv->ips.max_delay--;
eb48eb00
DV		 5303
5304out_unlock:
9270388e 5305 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5306
5307 return ret;
5308}
5309EXPORT_SYMBOL_GPL(i915_gpu_raise);
5310
5311/**
5312 * i915_gpu_lower - lower GPU frequency limit
5313 *
5314 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5315 * frequency maximum.
5316 */
5317bool i915_gpu_lower(void)
5318{
5319 struct drm_i915_private *dev_priv;
5320 bool ret = true;
5321
9270388e 5322 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5323 if (!i915_mch_dev) {
5324 ret = false;
5325 goto out_unlock;
5326 }
5327 dev_priv = i915_mch_dev;
5328
20e4d407
DV		 5329 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5330 dev_priv->ips.max_delay++;
eb48eb00
DV		 5331
5332out_unlock:
9270388e 5333 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5334
5335 return ret;
5336}
5337EXPORT_SYMBOL_GPL(i915_gpu_lower);
5338
5339/**
5340 * i915_gpu_busy - indicate GPU business to IPS
5341 *
5342 * Tell the IPS driver whether or not the GPU is busy.
5343 */
5344bool i915_gpu_busy(void)
5345{
5346 struct drm_i915_private *dev_priv;
a4872ba6 5347 struct intel_engine_cs *ring;
eb48eb00 5348 bool ret = false;
f047e395 5349 int i;
eb48eb00 5350
9270388e 5351 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5352 if (!i915_mch_dev)
5353 goto out_unlock;
5354 dev_priv = i915_mch_dev;
5355
f047e395
CW		 5356 for_each_ring(ring, dev_priv, i)
5357 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5358
5359out_unlock:
9270388e 5360 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5361
5362 return ret;
5363}
5364EXPORT_SYMBOL_GPL(i915_gpu_busy);
5365
5366/**
5367 * i915_gpu_turbo_disable - disable graphics turbo
5368 *
5369 * Disable graphics turbo by resetting the max frequency and setting the
5370 * current frequency to the default.
5371 */
5372bool i915_gpu_turbo_disable(void)
5373{
5374 struct drm_i915_private *dev_priv;
5375 bool ret = true;
5376
9270388e 5377 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5378 if (!i915_mch_dev) {
5379 ret = false;
5380 goto out_unlock;
5381 }
5382 dev_priv = i915_mch_dev;
5383
20e4d407 5384 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5385
20e4d407 5386 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5387 ret = false;
5388
5389out_unlock:
9270388e 5390 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5391
5392 return ret;
5393}
5394EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5395
5396/**
5397 * Tells the intel_ips driver that the i915 driver is now loaded, if
5398 * IPS got loaded first.
5399 *
5400 * This awkward dance is so that neither module has to depend on the
5401 * other in order for IPS to do the appropriate communication of
5402 * GPU turbo limits to i915.
5403 */
5404static void
5405ips_ping_for_i915_load(void)
5406{
5407 void (*link)(void);
5408
5409 link = symbol_get(ips_link_to_i915_driver);
5410 if (link) {
5411 link();
5412 symbol_put(ips_link_to_i915_driver);
5413 }
5414}
5415
5416void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5417{
02d71956
DV		 5418 /* We only register the i915 ips part with intel-ips once everything is
5419 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5420 spin_lock_irq(&mchdev_lock);
eb48eb00 5421 i915_mch_dev = dev_priv;
9270388e 5422 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5423
5424 ips_ping_for_i915_load();
5425}
5426
5427void intel_gpu_ips_teardown(void)
5428{
9270388e 5429 spin_lock_irq(&mchdev_lock);
eb48eb00 5430 i915_mch_dev = NULL;
9270388e 5431 spin_unlock_irq(&mchdev_lock);
eb48eb00 5432}
76c3552f 5433
8090c6b9 5434static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5435{
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 u32 lcfuse;
5438 u8 pxw[16];
5439 int i;
5440
5441 /* Disable to program */
5442 I915_WRITE(ECR, 0);
5443 POSTING_READ(ECR);
5444
5445 /* Program energy weights for various events */
5446 I915_WRITE(SDEW, 0x15040d00);
5447 I915_WRITE(CSIEW0, 0x007f0000);
5448 I915_WRITE(CSIEW1, 0x1e220004);
5449 I915_WRITE(CSIEW2, 0x04000004);
5450
5451 for (i = 0; i < 5; i++)
5452 I915_WRITE(PEW + (i * 4), 0);
5453 for (i = 0; i < 3; i++)
5454 I915_WRITE(DEW + (i * 4), 0);
5455
5456 /* Program P-state weights to account for frequency power adjustment */
5457 for (i = 0; i < 16; i++) {
5458 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5459 unsigned long freq = intel_pxfreq(pxvidfreq);
5460 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5461 PXVFREQ_PX_SHIFT;
5462 unsigned long val;
5463
5464 val = vid * vid;
5465 val *= (freq / 1000);
5466 val *= 255;
5467 val /= (127*127*900);
5468 if (val > 0xff)
5469 DRM_ERROR("bad pxval: %ld\n", val);
5470 pxw[i] = val;
5471 }
5472 /* Render standby states get 0 weight */
5473 pxw[14] = 0;
5474 pxw[15] = 0;
5475
5476 for (i = 0; i < 4; i++) {
5477 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5478 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5479 I915_WRITE(PXW + (i * 4), val);
5480 }
5481
5482 /* Adjust magic regs to magic values (more experimental results) */
5483 I915_WRITE(OGW0, 0);
5484 I915_WRITE(OGW1, 0);
5485 I915_WRITE(EG0, 0x00007f00);
5486 I915_WRITE(EG1, 0x0000000e);
5487 I915_WRITE(EG2, 0x000e0000);
5488 I915_WRITE(EG3, 0x68000300);
5489 I915_WRITE(EG4, 0x42000000);
5490 I915_WRITE(EG5, 0x00140031);
5491 I915_WRITE(EG6, 0);
5492 I915_WRITE(EG7, 0);
5493
5494 for (i = 0; i < 8; i++)
5495 I915_WRITE(PXWL + (i * 4), 0);
5496
5497 /* Enable PMON + select events */
5498 I915_WRITE(ECR, 0x80000019);
5499
5500 lcfuse = I915_READ(LCFUSE02);
5501
20e4d407 5502 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5503}
5504
ae48434c
ID		 5505void intel_init_gt_powersave(struct drm_device *dev)
5506{
e6069ca8
ID		 5507 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5508
38807746
D		 5509 if (IS_CHERRYVIEW(dev))
5510 cherryview_init_gt_powersave(dev);
5511 else if (IS_VALLEYVIEW(dev))
4e80519e 5512 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5513}
5514
5515void intel_cleanup_gt_powersave(struct drm_device *dev)
5516{
38807746
D		 5517 if (IS_CHERRYVIEW(dev))
5518 return;
5519 else if (IS_VALLEYVIEW(dev))
4e80519e 5520 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5521}
5522
dbea3cea
ID		 5523static void gen6_suspend_rps(struct drm_device *dev)
5524{
5525 struct drm_i915_private *dev_priv = dev->dev_private;
5526
5527 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5528
5529 /*
5530 * TODO: disable RPS interrupts on GEN9+ too once RPS support
5531 * is added for it.
5532 */
5533 if (INTEL_INFO(dev)->gen < 9)
5534 gen6_disable_rps_interrupts(dev);
5535}
5536
156c7ca0
JB		 5537/**
5538 * intel_suspend_gt_powersave - suspend PM work and helper threads
5539 * @dev: drm device
5540 *
5541 * We don't want to disable RC6 or other features here, we just want
5542 * to make sure any work we've queued has finished and won't bother
5543 * us while we're suspended.
5544 */
5545void intel_suspend_gt_powersave(struct drm_device *dev)
5546{
5547 struct drm_i915_private *dev_priv = dev->dev_private;
5548
d4d70aa5
ID		 5549 if (INTEL_INFO(dev)->gen < 6)
5550 return;
5551
dbea3cea 5552 gen6_suspend_rps(dev);
b47adc17
D		 5553
5554 /* Force GPU to min freq during suspend */
5555 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5556}
5557
8090c6b9
DV		 5558void intel_disable_gt_powersave(struct drm_device *dev)
5559{
1a01ab3b
JB		 5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561
930ebb46 5562 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5563 ironlake_disable_drps(dev);
930ebb46 5564 ironlake_disable_rc6(dev);
38807746 5565 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5566 intel_suspend_gt_powersave(dev);
e494837a 5567
4fc688ce 5568 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5569 if (INTEL_INFO(dev)->gen >= 9)
5570 gen9_disable_rps(dev);
5571 else if (IS_CHERRYVIEW(dev))
38807746
D		 5572 cherryview_disable_rps(dev);
5573 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5574 valleyview_disable_rps(dev);
5575 else
5576 gen6_disable_rps(dev);
e534770a 5577
c0951f0c 5578 dev_priv->rps.enabled = false;
4fc688ce 5579 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5580 }
8090c6b9
DV		 5581}
5582
1a01ab3b
JB		 5583static void intel_gen6_powersave_work(struct work_struct *work)
5584{
5585 struct drm_i915_private *dev_priv =
5586 container_of(work, struct drm_i915_private,
5587 rps.delayed_resume_work.work);
5588 struct drm_device *dev = dev_priv->dev;
5589
4fc688ce 5590 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5591
3cc134e3
ID		 5592 /*
5593 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
5594 * added for it.
5595 */
5596 if (INTEL_INFO(dev)->gen < 9)
5597 gen6_reset_rps_interrupts(dev);
5598
38807746
D		 5599 if (IS_CHERRYVIEW(dev)) {
5600 cherryview_enable_rps(dev);
5601 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5602 valleyview_enable_rps(dev);
20e49366 5603 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5604 gen9_enable_rc6(dev);
20e49366 5605 gen9_enable_rps(dev);
b6fef0ef 5606 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5607 } else if (IS_BROADWELL(dev)) {
5608 gen8_enable_rps(dev);
c2bc2fc5 5609 __gen6_update_ring_freq(dev);
0a073b84
JB		 5610 } else {
5611 gen6_enable_rps(dev);
c2bc2fc5 5612 __gen6_update_ring_freq(dev);
0a073b84 5613 }
c0951f0c 5614 dev_priv->rps.enabled = true;
3cc134e3
ID		 5615
5616 if (INTEL_INFO(dev)->gen < 9)
5617 gen6_enable_rps_interrupts(dev);
5618
4fc688ce 5619 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5620
5621 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5622}
5623
8090c6b9
DV		 5624void intel_enable_gt_powersave(struct drm_device *dev)
5625{
1a01ab3b
JB		 5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627
8090c6b9 5628 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5629 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5630 ironlake_enable_drps(dev);
5631 ironlake_enable_rc6(dev);
5632 intel_init_emon(dev);
dc1d0136 5633 mutex_unlock(&dev->struct_mutex);
38807746 5634 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5635 /*
5636 * PCU communication is slow and this doesn't need to be
5637 * done at any specific time, so do this out of our fast path
5638 * to make resume and init faster.
c6df39b5
ID		 5639 *
5640 * We depend on the HW RC6 power context save/restore
5641 * mechanism when entering D3 through runtime PM suspend. So
5642 * disable RPM until RPS/RC6 is properly setup. We can only
5643 * get here via the driver load/system resume/runtime resume
5644 * paths, so the _noresume version is enough (and in case of
5645 * runtime resume it's necessary).
1a01ab3b 5646 */
c6df39b5
ID		 5647 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5648 round_jiffies_up_relative(HZ)))
5649 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5650 }
5651}
5652
c6df39b5
ID		 5653void intel_reset_gt_powersave(struct drm_device *dev)
5654{
5655 struct drm_i915_private *dev_priv = dev->dev_private;
5656
dbea3cea
ID		 5657 if (INTEL_INFO(dev)->gen < 6)
5658 return;
5659
5660 gen6_suspend_rps(dev);
c6df39b5 5661 dev_priv->rps.enabled = false;
c6df39b5
ID		 5662}
5663
3107bd48
DV		 5664static void ibx_init_clock_gating(struct drm_device *dev)
5665{
5666 struct drm_i915_private *dev_priv = dev->dev_private;
5667
5668 /*
5669 * On Ibex Peak and Cougar Point, we need to disable clock
5670 * gating for the panel power sequencer or it will fail to
5671 * start up when no ports are active.
5672 */
5673 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5674}
5675
0e088b8f
VS		 5676static void g4x_disable_trickle_feed(struct drm_device *dev)
5677{
5678 struct drm_i915_private *dev_priv = dev->dev_private;
5679 int pipe;
5680
055e393f 5681 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5682 I915_WRITE(DSPCNTR(pipe),
5683 I915_READ(DSPCNTR(pipe)) |
5684 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5685 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5686 }
5687}
5688
017636cc
VS		 5689static void ilk_init_lp_watermarks(struct drm_device *dev)
5690{
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692
5693 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5694 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5695 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5696
5697 /*
5698 * Don't touch WM1S_LP_EN here.
5699 * Doing so could cause underruns.
5700 */
5701}
5702
1fa61106 5703static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5704{
5705 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5706 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5707
f1e8fa56
DL		 5708 /*
5709 * Required for FBC
5710 * WaFbcDisableDpfcClockGating:ilk
5711 */
4d47e4f5
DL		 5712 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5713 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5714 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5715
5716 I915_WRITE(PCH_3DCGDIS0,
5717 MARIUNIT_CLOCK_GATE_DISABLE |
5718 SVSMUNIT_CLOCK_GATE_DISABLE);
5719 I915_WRITE(PCH_3DCGDIS1,
5720 VFMUNIT_CLOCK_GATE_DISABLE);
5721
6f1d69b0
ED		 5722 /*
5723 * According to the spec the following bits should be set in
5724 * order to enable memory self-refresh
5725 * The bit 22/21 of 0x42004
5726 * The bit 5 of 0x42020
5727 * The bit 15 of 0x45000
5728 */
5729 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5730 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5731 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5732 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5733 I915_WRITE(DISP_ARB_CTL,
5734 (I915_READ(DISP_ARB_CTL) |
5735 DISP_FBC_WM_DIS));
017636cc
VS		 5736
5737 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5738
5739 /*
5740 * Based on the document from hardware guys the following bits
5741 * should be set unconditionally in order to enable FBC.
5742 * The bit 22 of 0x42000
5743 * The bit 22 of 0x42004
5744 * The bit 7,8,9 of 0x42020.
5745 */
5746 if (IS_IRONLAKE_M(dev)) {
4bb35334 5747 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5748 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5749 I915_READ(ILK_DISPLAY_CHICKEN1) |
5750 ILK_FBCQ_DIS);
5751 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5752 I915_READ(ILK_DISPLAY_CHICKEN2) |
5753 ILK_DPARB_GATE);
6f1d69b0
ED		 5754 }
5755
4d47e4f5
DL		 5756 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5757
6f1d69b0
ED		 5758 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5759 I915_READ(ILK_DISPLAY_CHICKEN2) |
5760 ILK_ELPIN_409_SELECT);
5761 I915_WRITE(_3D_CHICKEN2,
5762 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5763 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5764
ecdb4eb7 5765 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5766 I915_WRITE(CACHE_MODE_0,
5767 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5768
4e04632e
AG		 5769 /* WaDisable_RenderCache_OperationalFlush:ilk */
5770 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5771
0e088b8f 5772 g4x_disable_trickle_feed(dev);
bdad2b2f 5773
3107bd48
DV		 5774 ibx_init_clock_gating(dev);
5775}
5776
5777static void cpt_init_clock_gating(struct drm_device *dev)
5778{
5779 struct drm_i915_private *dev_priv = dev->dev_private;
5780 int pipe;
3f704fa2 5781 uint32_t val;
3107bd48
DV		 5782
5783 /*
5784 * On Ibex Peak and Cougar Point, we need to disable clock
5785 * gating for the panel power sequencer or it will fail to
5786 * start up when no ports are active.
5787 */
cd664078
JB		 5788 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5789 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5790 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5791 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5792 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5793 /* The below fixes the weird display corruption, a few pixels shifted
5794 * downward, on (only) LVDS of some HP laptops with IVY.
5795 */
055e393f 5796 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5797 val = I915_READ(TRANS_CHICKEN2(pipe));
5798 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5799 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5800 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5801 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5802 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5803 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5804 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5805 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5806 }
3107bd48 5807 /* WADP0ClockGatingDisable */
055e393f 5808 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5809 I915_WRITE(TRANS_CHICKEN1(pipe),
5810 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5811 }
6f1d69b0
ED		 5812}
5813
1d7aaa0c
DV		 5814static void gen6_check_mch_setup(struct drm_device *dev)
5815{
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 uint32_t tmp;
5818
5819 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5820 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5821 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5822 tmp);
1d7aaa0c
DV		 5823}
5824
1fa61106 5825static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5826{
5827 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5828 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5829
231e54f6 5830 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5831
5832 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5833 I915_READ(ILK_DISPLAY_CHICKEN2) |
5834 ILK_ELPIN_409_SELECT);
5835
ecdb4eb7 5836 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5837 I915_WRITE(_3D_CHICKEN,
5838 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5839
4e04632e
AG		 5840 /* WaDisable_RenderCache_OperationalFlush:snb */
5841 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5842
8d85d272
VS		 5843 /*
5844 * BSpec recoomends 8x4 when MSAA is used,
5845 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5846 *
5847 * Note that PS/WM thread counts depend on the WIZ hashing
5848 * disable bit, which we don't touch here, but it's good
5849 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5850 */
5851 I915_WRITE(GEN6_GT_MODE,
98533251 5852 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5853
017636cc 5854 ilk_init_lp_watermarks(dev);
6f1d69b0 5855
6f1d69b0 5856 I915_WRITE(CACHE_MODE_0,
50743298 5857 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5858
5859 I915_WRITE(GEN6_UCGCTL1,
5860 I915_READ(GEN6_UCGCTL1) |
5861 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5862 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5863
5864 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5865 * gating disable must be set. Failure to set it results in
5866 * flickering pixels due to Z write ordering failures after
5867 * some amount of runtime in the Mesa "fire" demo, and Unigine
5868 * Sanctuary and Tropics, and apparently anything else with
5869 * alpha test or pixel discard.
5870 *
5871 * According to the spec, bit 11 (RCCUNIT) must also be set,
5872 * but we didn't debug actual testcases to find it out.
0f846f81 5873 *
ef59318c
VS		 5874 * WaDisableRCCUnitClockGating:snb
5875 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5876 */
5877 I915_WRITE(GEN6_UCGCTL2,
5878 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5879 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5880
5eb146dd 5881 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5882 I915_WRITE(_3D_CHICKEN3,
5883 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5884
e927ecde
VS		 5885 /*
5886 * Bspec says:
5887 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5888 * 3DSTATE_SF number of SF output attributes is more than 16."
5889 */
5890 I915_WRITE(_3D_CHICKEN3,
5891 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5892
6f1d69b0
ED		 5893 /*
5894 * According to the spec the following bits should be
5895 * set in order to enable memory self-refresh and fbc:
5896 * The bit21 and bit22 of 0x42000
5897 * The bit21 and bit22 of 0x42004
5898 * The bit5 and bit7 of 0x42020
5899 * The bit14 of 0x70180
5900 * The bit14 of 0x71180
4bb35334
DL		 5901 *
5902 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5903 */
5904 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5905 I915_READ(ILK_DISPLAY_CHICKEN1) |
5906 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5907 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5908 I915_READ(ILK_DISPLAY_CHICKEN2) |
5909 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5910 I915_WRITE(ILK_DSPCLK_GATE_D,
5911 I915_READ(ILK_DSPCLK_GATE_D) |
5912 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5913 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5914
0e088b8f 5915 g4x_disable_trickle_feed(dev);
f8f2ac9a 5916
3107bd48 5917 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5918
5919 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5920}
5921
5922static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5923{
5924 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5925
3aad9059 5926 /*
46680e0a 5927 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5928 *
5929 * This actually overrides the dispatch
5930 * mode for all thread types.
5931 */
6f1d69b0
ED		 5932 reg &= ~GEN7_FF_SCHED_MASK;
5933 reg |= GEN7_FF_TS_SCHED_HW;
5934 reg |= GEN7_FF_VS_SCHED_HW;
5935 reg |= GEN7_FF_DS_SCHED_HW;
5936
5937 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5938}
5939
17a303ec
PZ		 5940static void lpt_init_clock_gating(struct drm_device *dev)
5941{
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943
5944 /*
5945 * TODO: this bit should only be enabled when really needed, then
5946 * disabled when not needed anymore in order to save power.
5947 */
5948 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5949 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5950 I915_READ(SOUTH_DSPCLK_GATE_D) |
5951 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5952
5953 /* WADPOClockGatingDisable:hsw */
5954 I915_WRITE(_TRANSA_CHICKEN1,
5955 I915_READ(_TRANSA_CHICKEN1) |
5956 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5957}
5958
7d708ee4
ID		 5959static void lpt_suspend_hw(struct drm_device *dev)
5960{
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962
5963 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5964 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5965
5966 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5967 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5968 }
5969}
5970
47c2bd97 5971static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 5972{
5973 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5974 enum pipe pipe;
1020a5c2
BW		 5975
5976 I915_WRITE(WM3_LP_ILK, 0);
5977 I915_WRITE(WM2_LP_ILK, 0);
5978 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 5979
ab57fff1 5980 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5981 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5982
ab57fff1 5983 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5984 I915_WRITE(CHICKEN_PAR1_1,
5985 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5986
ab57fff1 5987 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 5988 for_each_pipe(dev_priv, pipe) {
07d27e20 5989 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5990 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5991 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5992 }
63801f21 5993
ab57fff1
BW		 5994 /* WaVSRefCountFullforceMissDisable:bdw */
5995 /* WaDSRefCountFullforceMissDisable:bdw */
5996 I915_WRITE(GEN7_FF_THREAD_MODE,
5997 I915_READ(GEN7_FF_THREAD_MODE) &
5998 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 5999
295e8bb7
VS		 6000 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6001 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6002
6003 /* WaDisableSDEUnitClockGating:bdw */
6004 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6005 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6006
89d6b2b8 6007 lpt_init_clock_gating(dev);
1020a5c2
BW		 6008}
6009
cad2a2d7
ED		 6010static void haswell_init_clock_gating(struct drm_device *dev)
6011{
6012 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6013
017636cc 6014 ilk_init_lp_watermarks(dev);
cad2a2d7 6015
f3fc4884
FJ		 6016 /* L3 caching of data atomics doesn't work -- disable it. */
6017 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6018 I915_WRITE(HSW_ROW_CHICKEN3,
6019 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6020
ecdb4eb7 6021 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6022 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6023 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6024 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6025
e36ea7ff
VS		 6026 /* WaVSRefCountFullforceMissDisable:hsw */
6027 I915_WRITE(GEN7_FF_THREAD_MODE,
6028 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6029
4e04632e
AG		 6030 /* WaDisable_RenderCache_OperationalFlush:hsw */
6031 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6032
fe27c606
CW		 6033 /* enable HiZ Raw Stall Optimization */
6034 I915_WRITE(CACHE_MODE_0_GEN7,
6035 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6036
ecdb4eb7 6037 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6038 I915_WRITE(CACHE_MODE_1,
6039 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6040
a12c4967
VS		 6041 /*
6042 * BSpec recommends 8x4 when MSAA is used,
6043 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6044 *
6045 * Note that PS/WM thread counts depend on the WIZ hashing
6046 * disable bit, which we don't touch here, but it's good
6047 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6048 */
6049 I915_WRITE(GEN7_GT_MODE,
98533251 6050 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6051
94411593
KG		 6052 /* WaSampleCChickenBitEnable:hsw */
6053 I915_WRITE(HALF_SLICE_CHICKEN3,
6054 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6055
ecdb4eb7 6056 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6057 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6058
90a88643
PZ		 6059 /* WaRsPkgCStateDisplayPMReq:hsw */
6060 I915_WRITE(CHICKEN_PAR1_1,
6061 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6062
17a303ec 6063 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6064}
6065
1fa61106 6066static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6067{
6068 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6069 uint32_t snpcr;
6f1d69b0 6070
017636cc 6071 ilk_init_lp_watermarks(dev);
6f1d69b0 6072
231e54f6 6073 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6074
ecdb4eb7 6075 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6076 I915_WRITE(_3D_CHICKEN3,
6077 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6078
ecdb4eb7 6079 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6080 I915_WRITE(IVB_CHICKEN3,
6081 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6082 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6083
ecdb4eb7 6084 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6085 if (IS_IVB_GT1(dev))
6086 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6087 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6088
4e04632e
AG		 6089 /* WaDisable_RenderCache_OperationalFlush:ivb */
6090 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6091
ecdb4eb7 6092 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6093 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6094 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6095
ecdb4eb7 6096 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6097 I915_WRITE(GEN7_L3CNTLREG1,
6098 GEN7_WA_FOR_GEN7_L3_CONTROL);
6099 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6100 GEN7_WA_L3_CHICKEN_MODE);
6101 if (IS_IVB_GT1(dev))
6102 I915_WRITE(GEN7_ROW_CHICKEN2,
6103 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6104 else {
6105 /* must write both registers */
6106 I915_WRITE(GEN7_ROW_CHICKEN2,
6107 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6108 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6109 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6110 }
6f1d69b0 6111
ecdb4eb7 6112 /* WaForceL3Serialization:ivb */
61939d97
JB		 6113 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6114 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6115
1b80a19a 6116 /*
0f846f81 6117 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6118 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6119 */
6120 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6121 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6122
ecdb4eb7 6123 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6124 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6125 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6126 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6127
0e088b8f 6128 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6129
6130 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6131
22721343
CW		 6132 if (0) { /* causes HiZ corruption on ivb:gt1 */
6133 /* enable HiZ Raw Stall Optimization */
6134 I915_WRITE(CACHE_MODE_0_GEN7,
6135 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6136 }
116f2b6d 6137
ecdb4eb7 6138 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6139 I915_WRITE(CACHE_MODE_1,
6140 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6141
a607c1a4
VS		 6142 /*
6143 * BSpec recommends 8x4 when MSAA is used,
6144 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6145 *
6146 * Note that PS/WM thread counts depend on the WIZ hashing
6147 * disable bit, which we don't touch here, but it's good
6148 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6149 */
6150 I915_WRITE(GEN7_GT_MODE,
98533251 6151 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6152
20848223
BW		 6153 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6154 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6155 snpcr |= GEN6_MBC_SNPCR_MED;
6156 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6157
ab5c608b
BW		 6158 if (!HAS_PCH_NOP(dev))
6159 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6160
6161 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6162}
6163
1fa61106 6164static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6165{
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6167
d7fe0cc0 6168 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6169
ecdb4eb7 6170 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6171 I915_WRITE(_3D_CHICKEN3,
6172 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6173
ecdb4eb7 6174 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6175 I915_WRITE(IVB_CHICKEN3,
6176 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6177 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6178
fad7d36e 6179 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6180 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6181 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6182 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6183 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6184
4e04632e
AG		 6185 /* WaDisable_RenderCache_OperationalFlush:vlv */
6186 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6187
ecdb4eb7 6188 /* WaForceL3Serialization:vlv */
61939d97
JB		 6189 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6190 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6191
ecdb4eb7 6192 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6193 I915_WRITE(GEN7_ROW_CHICKEN2,
6194 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6195
ecdb4eb7 6196 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6197 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6198 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6199 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6200
46680e0a
VS		 6201 gen7_setup_fixed_func_scheduler(dev_priv);
6202
3c0edaeb 6203 /*
0f846f81 6204 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6205 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6206 */
6207 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6208 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6209
c98f5062
AG		 6210 /* WaDisableL3Bank2xClockGate:vlv
6211 * Disabling L3 clock gating- MMIO 940c[25] = 1
6212 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6213 I915_WRITE(GEN7_UCGCTL4,
6214 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6215
e0d8d59b 6216 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 6217
afd58e79
VS		 6218 /*
6219 * BSpec says this must be set, even though
6220 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6221 */
6b26c86d
DV		 6222 I915_WRITE(CACHE_MODE_1,
6223 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6224
da2518f9
VS		 6225 /*
6226 * BSpec recommends 8x4 when MSAA is used,
6227 * however in practice 16x4 seems fastest.
6228 *
6229 * Note that PS/WM thread counts depend on the WIZ hashing
6230 * disable bit, which we don't touch here, but it's good
6231 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6232 */
6233 I915_WRITE(GEN7_GT_MODE,
6234 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6235
031994ee
VS		 6236 /*
6237 * WaIncreaseL3CreditsForVLVB0:vlv
6238 * This is the hardware default actually.
6239 */
6240 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6241
2d809570 6242 /*
ecdb4eb7 6243 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6244 * Disable clock gating on th GCFG unit to prevent a delay
6245 * in the reporting of vblank events.
6246 */
7a0d1eed 6247 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6248}
6249
a4565da8
VS		 6250static void cherryview_init_clock_gating(struct drm_device *dev)
6251{
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253
6254 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6255
6256 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70 6257
232ce337
VS		 6258 /* WaVSRefCountFullforceMissDisable:chv */
6259 /* WaDSRefCountFullforceMissDisable:chv */
6260 I915_WRITE(GEN7_FF_THREAD_MODE,
6261 I915_READ(GEN7_FF_THREAD_MODE) &
6262 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6263
6264 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6265 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6266 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6267
6268 /* WaDisableCSUnitClockGating:chv */
6269 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6270 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6271
6272 /* WaDisableSDEUnitClockGating:chv */
6273 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6274 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6275}
6276
1fa61106 6277static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6278{
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 uint32_t dspclk_gate;
6281
6282 I915_WRITE(RENCLK_GATE_D1, 0);
6283 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6284 GS_UNIT_CLOCK_GATE_DISABLE |
6285 CL_UNIT_CLOCK_GATE_DISABLE);
6286 I915_WRITE(RAMCLK_GATE_D, 0);
6287 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6288 OVRUNIT_CLOCK_GATE_DISABLE |
6289 OVCUNIT_CLOCK_GATE_DISABLE;
6290 if (IS_GM45(dev))
6291 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6292 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6293
6294 /* WaDisableRenderCachePipelinedFlush */
6295 I915_WRITE(CACHE_MODE_0,
6296 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6297
4e04632e
AG		 6298 /* WaDisable_RenderCache_OperationalFlush:g4x */
6299 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6300
0e088b8f 6301 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6302}
6303
1fa61106 6304static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6305{
6306 struct drm_i915_private *dev_priv = dev->dev_private;
6307
6308 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6309 I915_WRITE(RENCLK_GATE_D2, 0);
6310 I915_WRITE(DSPCLK_GATE_D, 0);
6311 I915_WRITE(RAMCLK_GATE_D, 0);
6312 I915_WRITE16(DEUC, 0);
20f94967
VS		 6313 I915_WRITE(MI_ARB_STATE,
6314 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6315
6316 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6317 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6318}
6319
1fa61106 6320static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6321{
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323
6324 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6325 I965_RCC_CLOCK_GATE_DISABLE |
6326 I965_RCPB_CLOCK_GATE_DISABLE |
6327 I965_ISC_CLOCK_GATE_DISABLE |
6328 I965_FBC_CLOCK_GATE_DISABLE);
6329 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6330 I915_WRITE(MI_ARB_STATE,
6331 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6332
6333 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6334 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6335}
6336
1fa61106 6337static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6338{
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 u32 dstate = I915_READ(D_STATE);
6341
6342 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6343 DSTATE_DOT_CLOCK_GATING;
6344 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6345
6346 if (IS_PINEVIEW(dev))
6347 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6348
6349 /* IIR "flip pending" means done if this bit is set */
6350 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6351
6352 /* interrupts should cause a wake up from C3 */
3299254f 6353 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6354
6355 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6356 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6357
6358 I915_WRITE(MI_ARB_STATE,
6359 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6360}
6361
1fa61106 6362static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6363{
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365
6366 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6367
6368 /* interrupts should cause a wake up from C3 */
6369 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6370 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6371
6372 I915_WRITE(MEM_MODE,
6373 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6374}
6375
1fa61106 6376static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6377{
6378 struct drm_i915_private *dev_priv = dev->dev_private;
6379
6380 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6381
6382 I915_WRITE(MEM_MODE,
6383 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6384 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6385}
6386
6f1d69b0
ED		 6387void intel_init_clock_gating(struct drm_device *dev)
6388{
6389 struct drm_i915_private *dev_priv = dev->dev_private;
6390
6391 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6392}
6393
7d708ee4
ID		 6394void intel_suspend_hw(struct drm_device *dev)
6395{
6396 if (HAS_PCH_LPT(dev))
6397 lpt_suspend_hw(dev);
6398}
6399
1fa61106
ED		 6400/* Set up chip specific power management-related functions */
6401void intel_init_pm(struct drm_device *dev)
6402{
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404
7ff0ebcc 6405 intel_fbc_init(dev_priv);
1fa61106 6406
c921aba8
DV		 6407 /* For cxsr */
6408 if (IS_PINEVIEW(dev))
6409 i915_pineview_get_mem_freq(dev);
6410 else if (IS_GEN5(dev))
6411 i915_ironlake_get_mem_freq(dev);
6412
1fa61106 6413 /* For FIFO watermark updates */
f5ed50cb 6414 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6415 skl_setup_wm_latency(dev);
6416
c83155a6 6417 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
2d41c0b5
PB		 6418 dev_priv->display.update_wm = skl_update_wm;
6419 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6420 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6421 ilk_setup_wm_latency(dev);
53615a5e 6422
bd602544
VS		 6423 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6424 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6425 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6426 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6427 dev_priv->display.update_wm = ilk_update_wm;
6428 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6429 } else {
6430 DRM_DEBUG_KMS("Failed to read display plane latency. "
6431 "Disable CxSR\n");
6432 }
6433
6434 if (IS_GEN5(dev))
1fa61106 6435 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6436 else if (IS_GEN6(dev))
1fa61106 6437 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6438 else if (IS_IVYBRIDGE(dev))
1fa61106 6439 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6440 else if (IS_HASWELL(dev))
cad2a2d7 6441 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6442 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6443 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6444 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 6445 dev_priv->display.update_wm = cherryview_update_wm;
01e184cc 6446 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6447 dev_priv->display.init_clock_gating =
6448 cherryview_init_clock_gating;
1fa61106
ED		 6449 } else if (IS_VALLEYVIEW(dev)) {
6450 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6451 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6452 dev_priv->display.init_clock_gating =
6453 valleyview_init_clock_gating;
1fa61106
ED		 6454 } else if (IS_PINEVIEW(dev)) {
6455 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6456 dev_priv->is_ddr3,
6457 dev_priv->fsb_freq,
6458 dev_priv->mem_freq)) {
6459 DRM_INFO("failed to find known CxSR latency "
6460 "(found ddr%s fsb freq %d, mem freq %d), "
6461 "disabling CxSR\n",
6462 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6463 dev_priv->fsb_freq, dev_priv->mem_freq);
6464 /* Disable CxSR and never update its watermark again */
5209b1f4 6465 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6466 dev_priv->display.update_wm = NULL;
6467 } else
6468 dev_priv->display.update_wm = pineview_update_wm;
6469 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6470 } else if (IS_G4X(dev)) {
6471 dev_priv->display.update_wm = g4x_update_wm;
6472 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6473 } else if (IS_GEN4(dev)) {
6474 dev_priv->display.update_wm = i965_update_wm;
6475 if (IS_CRESTLINE(dev))
6476 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6477 else if (IS_BROADWATER(dev))
6478 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6479 } else if (IS_GEN3(dev)) {
6480 dev_priv->display.update_wm = i9xx_update_wm;
6481 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6482 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6483 } else if (IS_GEN2(dev)) {
6484 if (INTEL_INFO(dev)->num_pipes == 1) {
6485 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6486 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6487 } else {
6488 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6489 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6490 }
6491
6492 if (IS_I85X(dev) || IS_I865G(dev))
6493 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6494 else
6495 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6496 } else {
6497 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6498 }
6499}
6500
151a49d0 6501int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6502{
4fc688ce 6503 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6504
6505 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6506 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6507 return -EAGAIN;
6508 }
6509
6510 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6511 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6512 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6513
6514 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6515 500)) {
6516 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6517 return -ETIMEDOUT;
6518 }
6519
6520 *val = I915_READ(GEN6_PCODE_DATA);
6521 I915_WRITE(GEN6_PCODE_DATA, 0);
6522
6523 return 0;
6524}
6525
151a49d0 6526int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6527{
4fc688ce 6528 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6529
6530 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6531 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6532 return -EAGAIN;
6533 }
6534
6535 I915_WRITE(GEN6_PCODE_DATA, val);
6536 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6537
6538 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6539 500)) {
6540 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6541 return -ETIMEDOUT;
6542 }
6543
6544 I915_WRITE(GEN6_PCODE_DATA, 0);
6545
6546 return 0;
6547}
a0e4e199 6548
dd06f88c 6549static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6550{
dd06f88c
VS		 6551 switch (czclk_freq) {
6552 case 200:
6553 return 10;
6554 case 267:
6555 return 12;
6556 case 320:
6557 case 333:
dd06f88c 6558 return 16;
ab3fb157
VS		 6559 case 400:
6560 return 20;
855ba3be
JB		 6561 default:
6562 return -1;
6563 }
dd06f88c 6564}
855ba3be 6565
dd06f88c
VS		 6566static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6567{
6568 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6569
6570 div = vlv_gpu_freq_div(czclk_freq);
6571 if (div < 0)
6572 return div;
6573
6574 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6575}
6576
b55dd647 6577static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6578{
dd06f88c 6579 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6580
dd06f88c
VS		 6581 mul = vlv_gpu_freq_div(czclk_freq);
6582 if (mul < 0)
6583 return mul;
855ba3be 6584
dd06f88c 6585 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6586}
6587
b55dd647 6588static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6589{
dd06f88c 6590 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6591
dd06f88c
VS		 6592 div = vlv_gpu_freq_div(czclk_freq) / 2;
6593 if (div < 0)
6594 return div;
22b1b2f8 6595
dd06f88c 6596 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6597}
6598
b55dd647 6599static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6600{
dd06f88c 6601 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6602
dd06f88c
VS		 6603 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6604 if (mul < 0)
6605 return mul;
22b1b2f8 6606
1c14762d 6607 /* CHV needs even values */
dd06f88c 6608 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6609}
6610
616bc820 6611int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6612{
22b1b2f8 6613 if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6614 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6615 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6616 return byt_gpu_freq(dev_priv, val);
6617 else
6618 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6619}
6620
616bc820
VS		 6621int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6622{
22b1b2f8 6623 if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6624 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6625 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6626 return byt_freq_opcode(dev_priv, val);
6627 else
6628 return val / GT_FREQUENCY_MULTIPLIER;
6629}
22b1b2f8 6630
f742a552 6631void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6632{
6633 struct drm_i915_private *dev_priv = dev->dev_private;
6634
f742a552
DV		 6635 mutex_init(&dev_priv->rps.hw_lock);
6636
907b28c5
CW		 6637 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6638 intel_gen6_powersave_work);
5d584b2e 6639
33688d95 6640 dev_priv->pm.suspended = false;
907b28c5 6641}
Linux kernel - Deliverables
This page took 1.619607 seconds and 5 git commands to generate.