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drm/i915: Move drm_framebuffer_unreference out of struct_mutex for flips
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
3dcd020a
HN		 70 if (INTEL_REVID(dev) == SKL_REVID_A0) {
71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a
HN		 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78 }
8bc0ccf6 79
2caa3b26 80 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 81 /* WaDisableHDCInvalidation:skl */
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
83 BDW_DISABLE_HDC_INVALIDATION);
84
2caa3b26
DL		 85 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
86 I915_WRITE(FF_SLICE_CS_CHICKEN2,
87 I915_READ(FF_SLICE_CS_CHICKEN2) |
88 GEN9_TSG_BARRIER_ACK_DISABLE);
89 }
81e231af 90
8bc0ccf6
DL		 91 if (INTEL_REVID(dev) <= SKL_REVID_E0)
92 /* WaDisableLSQCROPERFforOCL:skl */
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
94 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 95}
96
c921aba8
DV		 97static void i915_pineview_get_mem_freq(struct drm_device *dev)
98{
50227e1c 99 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 100 u32 tmp;
101
102 tmp = I915_READ(CLKCFG);
103
104 switch (tmp & CLKCFG_FSB_MASK) {
105 case CLKCFG_FSB_533:
106 dev_priv->fsb_freq = 533; /* 133*4 */
107 break;
108 case CLKCFG_FSB_800:
109 dev_priv->fsb_freq = 800; /* 200*4 */
110 break;
111 case CLKCFG_FSB_667:
112 dev_priv->fsb_freq = 667; /* 167*4 */
113 break;
114 case CLKCFG_FSB_400:
115 dev_priv->fsb_freq = 400; /* 100*4 */
116 break;
117 }
118
119 switch (tmp & CLKCFG_MEM_MASK) {
120 case CLKCFG_MEM_533:
121 dev_priv->mem_freq = 533;
122 break;
123 case CLKCFG_MEM_667:
124 dev_priv->mem_freq = 667;
125 break;
126 case CLKCFG_MEM_800:
127 dev_priv->mem_freq = 800;
128 break;
129 }
130
131 /* detect pineview DDR3 setting */
132 tmp = I915_READ(CSHRDDR3CTL);
133 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
134}
135
136static void i915_ironlake_get_mem_freq(struct drm_device *dev)
137{
50227e1c 138 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 139 u16 ddrpll, csipll;
140
141 ddrpll = I915_READ16(DDRMPLL1);
142 csipll = I915_READ16(CSIPLL0);
143
144 switch (ddrpll & 0xff) {
145 case 0xc:
146 dev_priv->mem_freq = 800;
147 break;
148 case 0x10:
149 dev_priv->mem_freq = 1066;
150 break;
151 case 0x14:
152 dev_priv->mem_freq = 1333;
153 break;
154 case 0x18:
155 dev_priv->mem_freq = 1600;
156 break;
157 default:
158 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
159 ddrpll & 0xff);
160 dev_priv->mem_freq = 0;
161 break;
162 }
163
20e4d407 164 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 165
166 switch (csipll & 0x3ff) {
167 case 0x00c:
168 dev_priv->fsb_freq = 3200;
169 break;
170 case 0x00e:
171 dev_priv->fsb_freq = 3733;
172 break;
173 case 0x010:
174 dev_priv->fsb_freq = 4266;
175 break;
176 case 0x012:
177 dev_priv->fsb_freq = 4800;
178 break;
179 case 0x014:
180 dev_priv->fsb_freq = 5333;
181 break;
182 case 0x016:
183 dev_priv->fsb_freq = 5866;
184 break;
185 case 0x018:
186 dev_priv->fsb_freq = 6400;
187 break;
188 default:
189 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
190 csipll & 0x3ff);
191 dev_priv->fsb_freq = 0;
192 break;
193 }
194
195 if (dev_priv->fsb_freq == 3200) {
20e4d407 196 dev_priv->ips.c_m = 0;
c921aba8 197 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 198 dev_priv->ips.c_m = 1;
c921aba8 199 } else {
20e4d407 200 dev_priv->ips.c_m = 2;
c921aba8
DV		 201 }
202}
203
b445e3b0
ED		 204static const struct cxsr_latency cxsr_latency_table[] = {
205 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
206 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
207 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
208 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
209 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
210
211 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
212 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
213 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
214 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
215 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
216
217 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
218 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
219 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
220 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
221 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
222
223 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
224 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
225 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
226 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
227 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
228
229 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
230 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
231 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
232 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
233 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
234
235 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
236 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
237 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
238 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
239 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
240};
241
63c62275 242static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 243 int is_ddr3,
244 int fsb,
245 int mem)
246{
247 const struct cxsr_latency *latency;
248 int i;
249
250 if (fsb == 0 || mem == 0)
251 return NULL;
252
253 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
254 latency = &cxsr_latency_table[i];
255 if (is_desktop == latency->is_desktop &&
256 is_ddr3 == latency->is_ddr3 &&
257 fsb == latency->fsb_freq && mem == latency->mem_freq)
258 return latency;
259 }
260
261 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
262
263 return NULL;
264}
265
fc1ac8de
VS		 266static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
267{
268 u32 val;
269
270 mutex_lock(&dev_priv->rps.hw_lock);
271
272 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
273 if (enable)
274 val &= ~FORCE_DDR_HIGH_FREQ;
275 else
276 val |= FORCE_DDR_HIGH_FREQ;
277 val &= ~FORCE_DDR_LOW_FREQ;
278 val |= FORCE_DDR_FREQ_REQ_ACK;
279 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
280
281 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
282 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
283 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
cfb41411
VS		 288static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
289{
290 u32 val;
291
292 mutex_lock(&dev_priv->rps.hw_lock);
293
294 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
295 if (enable)
296 val |= DSP_MAXFIFO_PM5_ENABLE;
297 else
298 val &= ~DSP_MAXFIFO_PM5_ENABLE;
299 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
300
301 mutex_unlock(&dev_priv->rps.hw_lock);
302}
303
5209b1f4 304void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 305{
5209b1f4
ID		 306 struct drm_device *dev = dev_priv->dev;
307 u32 val;
b445e3b0 308
5209b1f4
ID		 309 if (IS_VALLEYVIEW(dev)) {
310 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS		 311 if (IS_CHERRYVIEW(dev))
312 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID		 313 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
314 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
315 } else if (IS_PINEVIEW(dev)) {
316 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
317 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
318 I915_WRITE(DSPFW3, val);
319 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
320 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
321 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
322 I915_WRITE(FW_BLC_SELF, val);
323 } else if (IS_I915GM(dev)) {
324 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
325 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
326 I915_WRITE(INSTPM, val);
327 } else {
328 return;
329 }
b445e3b0 330
5209b1f4
ID		 331 DRM_DEBUG_KMS("memory self-refresh is %s\n",
332 enable ? "enabled" : "disabled");
b445e3b0
ED		 333}
334
fc1ac8de 335
b445e3b0
ED		 336/*
337 * Latency for FIFO fetches is dependent on several factors:
338 * - memory configuration (speed, channels)
339 * - chipset
340 * - current MCH state
341 * It can be fairly high in some situations, so here we assume a fairly
342 * pessimal value. It's a tradeoff between extra memory fetches (if we
343 * set this value too high, the FIFO will fetch frequently to stay full)
344 * and power consumption (set it too low to save power and we might see
345 * FIFO underruns and display "flicker").
346 *
347 * A value of 5us seems to be a good balance; safe for very low end
348 * platforms but not overly aggressive on lower latency configs.
349 */
5aef6003 350static const int pessimal_latency_ns = 5000;
b445e3b0 351
b5004720
VS		 352#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
353 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
354
355static int vlv_get_fifo_size(struct drm_device *dev,
356 enum pipe pipe, int plane)
357{
358 struct drm_i915_private *dev_priv = dev->dev_private;
359 int sprite0_start, sprite1_start, size;
360
361 switch (pipe) {
362 uint32_t dsparb, dsparb2, dsparb3;
363 case PIPE_A:
364 dsparb = I915_READ(DSPARB);
365 dsparb2 = I915_READ(DSPARB2);
366 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
367 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
368 break;
369 case PIPE_B:
370 dsparb = I915_READ(DSPARB);
371 dsparb2 = I915_READ(DSPARB2);
372 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
373 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
374 break;
375 case PIPE_C:
376 dsparb2 = I915_READ(DSPARB2);
377 dsparb3 = I915_READ(DSPARB3);
378 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
379 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
380 break;
381 default:
382 return 0;
383 }
384
385 switch (plane) {
386 case 0:
387 size = sprite0_start;
388 break;
389 case 1:
390 size = sprite1_start - sprite0_start;
391 break;
392 case 2:
393 size = 512 - 1 - sprite1_start;
394 break;
395 default:
396 return 0;
397 }
398
399 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
400 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
401 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
402 size);
403
404 return size;
405}
406
1fa61106 407static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 408{
409 struct drm_i915_private *dev_priv = dev->dev_private;
410 uint32_t dsparb = I915_READ(DSPARB);
411 int size;
412
413 size = dsparb & 0x7f;
414 if (plane)
415 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
416
417 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
418 plane ? "B" : "A", size);
419
420 return size;
421}
422
feb56b93 423static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 424{
425 struct drm_i915_private *dev_priv = dev->dev_private;
426 uint32_t dsparb = I915_READ(DSPARB);
427 int size;
428
429 size = dsparb & 0x1ff;
430 if (plane)
431 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
432 size >>= 1; /* Convert to cachelines */
433
434 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
435 plane ? "B" : "A", size);
436
437 return size;
438}
439
1fa61106 440static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 441{
442 struct drm_i915_private *dev_priv = dev->dev_private;
443 uint32_t dsparb = I915_READ(DSPARB);
444 int size;
445
446 size = dsparb & 0x7f;
447 size >>= 2; /* Convert to cachelines */
448
449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
450 plane ? "B" : "A",
451 size);
452
453 return size;
454}
455
b445e3b0
ED		 456/* Pineview has different values for various configs */
457static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 458 .fifo_size = PINEVIEW_DISPLAY_FIFO,
459 .max_wm = PINEVIEW_MAX_WM,
460 .default_wm = PINEVIEW_DFT_WM,
461 .guard_size = PINEVIEW_GUARD_WM,
462 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 463};
464static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 465 .fifo_size = PINEVIEW_DISPLAY_FIFO,
466 .max_wm = PINEVIEW_MAX_WM,
467 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
468 .guard_size = PINEVIEW_GUARD_WM,
469 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 470};
471static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 472 .fifo_size = PINEVIEW_CURSOR_FIFO,
473 .max_wm = PINEVIEW_CURSOR_MAX_WM,
474 .default_wm = PINEVIEW_CURSOR_DFT_WM,
475 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 477};
478static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 479 .fifo_size = PINEVIEW_CURSOR_FIFO,
480 .max_wm = PINEVIEW_CURSOR_MAX_WM,
481 .default_wm = PINEVIEW_CURSOR_DFT_WM,
482 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 484};
485static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 486 .fifo_size = G4X_FIFO_SIZE,
487 .max_wm = G4X_MAX_WM,
488 .default_wm = G4X_MAX_WM,
489 .guard_size = 2,
490 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 491};
492static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 493 .fifo_size = I965_CURSOR_FIFO,
494 .max_wm = I965_CURSOR_MAX_WM,
495 .default_wm = I965_CURSOR_DFT_WM,
496 .guard_size = 2,
497 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 498};
499static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 500 .fifo_size = VALLEYVIEW_FIFO_SIZE,
501 .max_wm = VALLEYVIEW_MAX_WM,
502 .default_wm = VALLEYVIEW_MAX_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 505};
506static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 507 .fifo_size = I965_CURSOR_FIFO,
508 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
509 .default_wm = I965_CURSOR_DFT_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 512};
513static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = I965_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 519};
520static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 521 .fifo_size = I945_FIFO_SIZE,
522 .max_wm = I915_MAX_WM,
523 .default_wm = 1,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 526};
527static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 528 .fifo_size = I915_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 533};
9d539105 534static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 535 .fifo_size = I855GM_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 540};
9d539105
VS		 541static const struct intel_watermark_params i830_bc_wm_info = {
542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM/2,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
547};
feb56b93 548static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 549 .fifo_size = I830_FIFO_SIZE,
550 .max_wm = I915_MAX_WM,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 554};
555
b445e3b0
ED		 556/**
557 * intel_calculate_wm - calculate watermark level
558 * @clock_in_khz: pixel clock
559 * @wm: chip FIFO params
560 * @pixel_size: display pixel size
561 * @latency_ns: memory latency for the platform
562 *
563 * Calculate the watermark level (the level at which the display plane will
564 * start fetching from memory again). Each chip has a different display
565 * FIFO size and allocation, so the caller needs to figure that out and pass
566 * in the correct intel_watermark_params structure.
567 *
568 * As the pixel clock runs, the FIFO will be drained at a rate that depends
569 * on the pixel size. When it reaches the watermark level, it'll start
570 * fetching FIFO line sized based chunks from memory until the FIFO fills
571 * past the watermark point. If the FIFO drains completely, a FIFO underrun
572 * will occur, and a display engine hang could result.
573 */
574static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
575 const struct intel_watermark_params *wm,
576 int fifo_size,
577 int pixel_size,
578 unsigned long latency_ns)
579{
580 long entries_required, wm_size;
581
582 /*
583 * Note: we need to make sure we don't overflow for various clock &
584 * latency values.
585 * clocks go from a few thousand to several hundred thousand.
586 * latency is usually a few thousand
587 */
588 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
589 1000;
590 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
591
592 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
593
594 wm_size = fifo_size - (entries_required + wm->guard_size);
595
596 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
597
598 /* Don't promote wm_size to unsigned... */
599 if (wm_size > (long)wm->max_wm)
600 wm_size = wm->max_wm;
601 if (wm_size <= 0)
602 wm_size = wm->default_wm;
d6feb196
VS		 603
604 /*
605 * Bspec seems to indicate that the value shouldn't be lower than
606 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
607 * Lets go for 8 which is the burst size since certain platforms
608 * already use a hardcoded 8 (which is what the spec says should be
609 * done).
610 */
611 if (wm_size <= 8)
612 wm_size = 8;
613
b445e3b0
ED		 614 return wm_size;
615}
616
617static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
618{
619 struct drm_crtc *crtc, *enabled = NULL;
620
70e1e0ec 621 for_each_crtc(dev, crtc) {
3490ea5d 622 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 623 if (enabled)
624 return NULL;
625 enabled = crtc;
626 }
627 }
628
629 return enabled;
630}
631
46ba614c 632static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 633{
46ba614c 634 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 635 struct drm_i915_private *dev_priv = dev->dev_private;
636 struct drm_crtc *crtc;
637 const struct cxsr_latency *latency;
638 u32 reg;
639 unsigned long wm;
640
641 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
642 dev_priv->fsb_freq, dev_priv->mem_freq);
643 if (!latency) {
644 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 645 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 646 return;
647 }
648
649 crtc = single_enabled_crtc(dev);
650 if (crtc) {
241bfc38 651 const struct drm_display_mode *adjusted_mode;
59bea882 652 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 653 int clock;
654
6e3c9717 655 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 656 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 657
658 /* Display SR */
659 wm = intel_calculate_wm(clock, &pineview_display_wm,
660 pineview_display_wm.fifo_size,
661 pixel_size, latency->display_sr);
662 reg = I915_READ(DSPFW1);
663 reg &= ~DSPFW_SR_MASK;
664 reg |= wm << DSPFW_SR_SHIFT;
665 I915_WRITE(DSPFW1, reg);
666 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
667
668 /* cursor SR */
669 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
670 pineview_display_wm.fifo_size,
671 pixel_size, latency->cursor_sr);
672 reg = I915_READ(DSPFW3);
673 reg &= ~DSPFW_CURSOR_SR_MASK;
674 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
675 I915_WRITE(DSPFW3, reg);
676
677 /* Display HPLL off SR */
678 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
679 pineview_display_hplloff_wm.fifo_size,
680 pixel_size, latency->display_hpll_disable);
681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_HPLL_SR_MASK;
683 reg |= wm & DSPFW_HPLL_SR_MASK;
684 I915_WRITE(DSPFW3, reg);
685
686 /* cursor HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
689 pixel_size, latency->cursor_hpll_disable);
690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_CURSOR_MASK;
692 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
693 I915_WRITE(DSPFW3, reg);
694 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
695
5209b1f4 696 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 697 } else {
5209b1f4 698 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 699 }
700}
701
702static bool g4x_compute_wm0(struct drm_device *dev,
703 int plane,
704 const struct intel_watermark_params *display,
705 int display_latency_ns,
706 const struct intel_watermark_params *cursor,
707 int cursor_latency_ns,
708 int *plane_wm,
709 int *cursor_wm)
710{
711 struct drm_crtc *crtc;
4fe8590a 712 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 713 int htotal, hdisplay, clock, pixel_size;
714 int line_time_us, line_count;
715 int entries, tlb_miss;
716
717 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 718 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 719 *cursor_wm = cursor->guard_size;
720 *plane_wm = display->guard_size;
721 return false;
722 }
723
6e3c9717 724 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 725 clock = adjusted_mode->crtc_clock;
fec8cba3 726 htotal = adjusted_mode->crtc_htotal;
6e3c9717 727 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 728 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 729
730 /* Use the small buffer method to calculate plane watermark */
731 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
732 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
733 if (tlb_miss > 0)
734 entries += tlb_miss;
735 entries = DIV_ROUND_UP(entries, display->cacheline_size);
736 *plane_wm = entries + display->guard_size;
737 if (*plane_wm > (int)display->max_wm)
738 *plane_wm = display->max_wm;
739
740 /* Use the large buffer method to calculate cursor watermark */
922044c9 741 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 742 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 743 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 744 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
745 if (tlb_miss > 0)
746 entries += tlb_miss;
747 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
748 *cursor_wm = entries + cursor->guard_size;
749 if (*cursor_wm > (int)cursor->max_wm)
750 *cursor_wm = (int)cursor->max_wm;
751
752 return true;
753}
754
755/*
756 * Check the wm result.
757 *
758 * If any calculated watermark values is larger than the maximum value that
759 * can be programmed into the associated watermark register, that watermark
760 * must be disabled.
761 */
762static bool g4x_check_srwm(struct drm_device *dev,
763 int display_wm, int cursor_wm,
764 const struct intel_watermark_params *display,
765 const struct intel_watermark_params *cursor)
766{
767 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
768 display_wm, cursor_wm);
769
770 if (display_wm > display->max_wm) {
771 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
772 display_wm, display->max_wm);
773 return false;
774 }
775
776 if (cursor_wm > cursor->max_wm) {
777 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
778 cursor_wm, cursor->max_wm);
779 return false;
780 }
781
782 if (!(display_wm || cursor_wm)) {
783 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
784 return false;
785 }
786
787 return true;
788}
789
790static bool g4x_compute_srwm(struct drm_device *dev,
791 int plane,
792 int latency_ns,
793 const struct intel_watermark_params *display,
794 const struct intel_watermark_params *cursor,
795 int *display_wm, int *cursor_wm)
796{
797 struct drm_crtc *crtc;
4fe8590a 798 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 799 int hdisplay, htotal, pixel_size, clock;
800 unsigned long line_time_us;
801 int line_count, line_size;
802 int small, large;
803 int entries;
804
805 if (!latency_ns) {
806 *display_wm = *cursor_wm = 0;
807 return false;
808 }
809
810 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 811 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 812 clock = adjusted_mode->crtc_clock;
fec8cba3 813 htotal = adjusted_mode->crtc_htotal;
6e3c9717 814 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 815 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 816
922044c9 817 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 818 line_count = (latency_ns / line_time_us + 1000) / 1000;
819 line_size = hdisplay * pixel_size;
820
821 /* Use the minimum of the small and large buffer method for primary */
822 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
823 large = line_count * line_size;
824
825 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
826 *display_wm = entries + display->guard_size;
827
828 /* calculate the self-refresh watermark for display cursor */
3dd512fb 829 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 830 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
831 *cursor_wm = entries + cursor->guard_size;
832
833 return g4x_check_srwm(dev,
834 *display_wm, *cursor_wm,
835 display, cursor);
836}
837
0018fda1
VS		 838static void vlv_write_wm_values(struct intel_crtc *crtc,
839 const struct vlv_wm_values *wm)
840{
841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
842 enum pipe pipe = crtc->pipe;
843
844 I915_WRITE(VLV_DDL(pipe),
845 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
846 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
847 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
848 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
849
ae80152d
VS		 850 I915_WRITE(DSPFW1,
851 ((wm->sr.plane << DSPFW_SR_SHIFT) & DSPFW_SR_MASK) |
852 ((wm->pipe[PIPE_B].cursor << DSPFW_CURSORB_SHIFT) & DSPFW_CURSORB_MASK) |
853 ((wm->pipe[PIPE_B].primary << DSPFW_PLANEB_SHIFT) & DSPFW_PLANEB_MASK_VLV) |
854 ((wm->pipe[PIPE_A].primary << DSPFW_PLANEA_SHIFT) & DSPFW_PLANEA_MASK_VLV));
855 I915_WRITE(DSPFW2,
856 ((wm->pipe[PIPE_A].sprite[1] << DSPFW_SPRITEB_SHIFT) & DSPFW_SPRITEB_MASK_VLV) |
857 ((wm->pipe[PIPE_A].cursor << DSPFW_CURSORA_SHIFT) & DSPFW_CURSORA_MASK) |
858 ((wm->pipe[PIPE_A].sprite[0] << DSPFW_SPRITEA_SHIFT) & DSPFW_SPRITEA_MASK_VLV));
859 I915_WRITE(DSPFW3,
860 ((wm->sr.cursor << DSPFW_CURSOR_SR_SHIFT) & DSPFW_CURSOR_SR_MASK));
861
862 if (IS_CHERRYVIEW(dev_priv)) {
863 I915_WRITE(DSPFW7_CHV,
864 ((wm->pipe[PIPE_B].sprite[1] << DSPFW_SPRITED_SHIFT) & DSPFW_SPRITED_MASK) |
865 ((wm->pipe[PIPE_B].sprite[0] << DSPFW_SPRITEC_SHIFT) & DSPFW_SPRITEC_MASK));
866 I915_WRITE(DSPFW8_CHV,
867 ((wm->pipe[PIPE_C].sprite[1] << DSPFW_SPRITEF_SHIFT) & DSPFW_SPRITEF_MASK) |
868 ((wm->pipe[PIPE_C].sprite[0] << DSPFW_SPRITEE_SHIFT) & DSPFW_SPRITEE_MASK));
869 I915_WRITE(DSPFW9_CHV,
870 ((wm->pipe[PIPE_C].primary << DSPFW_PLANEC_SHIFT) & DSPFW_PLANEC_MASK) |
871 ((wm->pipe[PIPE_C].cursor << DSPFW_CURSORC_SHIFT) & DSPFW_CURSORC_MASK));
872 I915_WRITE(DSPHOWM,
873 (((wm->sr.plane >> 9) << DSPFW_SR_HI_SHIFT) & DSPFW_SR_HI_MASK) |
874 (((wm->pipe[PIPE_C].sprite[1] >> 8) << DSPFW_SPRITEF_HI_SHIFT) & DSPFW_SPRITEF_HI_MASK) |
875 (((wm->pipe[PIPE_C].sprite[0] >> 8) << DSPFW_SPRITEE_HI_SHIFT) & DSPFW_SPRITEE_HI_MASK) |
876 (((wm->pipe[PIPE_C].primary >> 8) << DSPFW_PLANEC_HI_SHIFT) & DSPFW_PLANEC_HI_MASK) |
877 (((wm->pipe[PIPE_B].sprite[1] >> 8) << DSPFW_SPRITED_HI_SHIFT) & DSPFW_SPRITED_HI_MASK) |
878 (((wm->pipe[PIPE_B].sprite[0] >> 8) << DSPFW_SPRITEC_HI_SHIFT) & DSPFW_SPRITEC_HI_MASK) |
879 (((wm->pipe[PIPE_B].primary >> 8) << DSPFW_PLANEB_HI_SHIFT) & DSPFW_PLANEB_HI_MASK) |
880 (((wm->pipe[PIPE_A].sprite[1] >> 8) << DSPFW_SPRITEB_HI_SHIFT) & DSPFW_SPRITEB_HI_MASK) |
881 (((wm->pipe[PIPE_A].sprite[0] >> 8) << DSPFW_SPRITEA_HI_SHIFT) & DSPFW_SPRITEA_HI_MASK) |
882 (((wm->pipe[PIPE_A].primary >> 8) << DSPFW_PLANEA_HI_SHIFT) & DSPFW_PLANEA_HI_MASK));
883 } else {
884 I915_WRITE(DSPFW7,
885 ((wm->pipe[PIPE_B].sprite[1] << DSPFW_SPRITED_SHIFT) & DSPFW_SPRITED_MASK) |
886 ((wm->pipe[PIPE_B].sprite[0] << DSPFW_SPRITEC_SHIFT) & DSPFW_SPRITEC_MASK));
887 I915_WRITE(DSPHOWM,
888 (((wm->sr.plane >> 9) << DSPFW_SR_HI_SHIFT) & DSPFW_SR_HI_MASK) |
889 (((wm->pipe[PIPE_B].sprite[1] >> 8) << DSPFW_SPRITED_HI_SHIFT) & DSPFW_SPRITED_HI_MASK) |
890 (((wm->pipe[PIPE_B].sprite[0] >> 8) << DSPFW_SPRITEC_HI_SHIFT) & DSPFW_SPRITEC_HI_MASK) |
891 (((wm->pipe[PIPE_B].primary >> 8) << DSPFW_PLANEB_HI_SHIFT) & DSPFW_PLANEB_HI_MASK) |
892 (((wm->pipe[PIPE_A].sprite[1] >> 8) << DSPFW_SPRITEB_HI_SHIFT) & DSPFW_SPRITEB_HI_MASK) |
893 (((wm->pipe[PIPE_A].sprite[0] >> 8) << DSPFW_SPRITEA_HI_SHIFT) & DSPFW_SPRITEA_HI_MASK) |
894 (((wm->pipe[PIPE_A].primary >> 8) << DSPFW_PLANEA_HI_SHIFT) & DSPFW_PLANEA_HI_MASK));
895 }
896
897 POSTING_READ(DSPFW1);
898
0018fda1
VS		 899 dev_priv->wm.vlv = *wm;
900}
901
341c526f 902static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 903 struct drm_plane *plane)
b445e3b0 904{
5e56ba45 905 struct drm_device *dev = crtc->dev;
883a3d2f
VS		 906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
907 int entries, prec_mult, drain_latency, pixel_size;
908 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 909 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 910
883a3d2f
VS		 911 /*
912 * FIXME the plane might have an fb
913 * but be invisible (eg. due to clipping)
914 */
915 if (!intel_crtc->active || !plane->state->fb)
916 return 0;
917
0948c265 918 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 919 return 0;
b445e3b0 920
883a3d2f
VS		 921 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
922
0948c265 923 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 924 return 0;
b445e3b0 925
a398e9c7 926 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 927
341c526f
VS		 928 prec_mult = high_precision;
929 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 930
341c526f
VS		 931 if (drain_latency > DRAIN_LATENCY_MASK) {
932 prec_mult /= 2;
933 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS		 934 }
935
341c526f
VS		 936 if (drain_latency > DRAIN_LATENCY_MASK)
937 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 938
341c526f
VS		 939 return drain_latency | (prec_mult == high_precision ?
940 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED		 941}
942
ae80152d
VS		 943static int vlv_compute_wm(struct intel_crtc *crtc,
944 struct intel_plane *plane,
945 int fifo_size)
b445e3b0 946{
ae80152d 947 int clock, entries, pixel_size;
b445e3b0 948
ae80152d
VS		 949 /*
950 * FIXME the plane might have an fb
951 * but be invisible (eg. due to clipping)
952 */
953 if (!crtc->active || !plane->base.state->fb)
954 return 0;
0948c265 955
ae80152d
VS		 956 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
957 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 958
ae80152d 959 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 960
ae80152d
VS		 961 /*
962 * Set up the watermark such that we don't start issuing memory
963 * requests until we are within PND's max deadline value (256us).
964 * Idea being to be idle as long as possible while still taking
965 * advatange of PND's deadline scheduling. The limit of 8
966 * cachelines (used when the FIFO will anyway drain in less time
967 * than 256us) should match what we would be done if trickle
968 * feed were enabled.
969 */
970 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
971}
972
973static bool vlv_compute_sr_wm(struct drm_device *dev,
974 struct vlv_wm_values *wm)
b445e3b0 975{
ae80152d
VS		 976 struct drm_i915_private *dev_priv = to_i915(dev);
977 struct drm_crtc *crtc;
978 enum pipe pipe = INVALID_PIPE;
979 int num_planes = 0;
980 int fifo_size = 0;
981 struct intel_plane *plane;
b445e3b0 982
ae80152d 983 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 984
ae80152d
VS		 985 crtc = single_enabled_crtc(dev);
986 /* maxfifo not supported on pipe C */
987 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
988 pipe = to_intel_crtc(crtc)->pipe;
989 num_planes = !!wm->pipe[pipe].primary +
990 !!wm->pipe[pipe].sprite[0] +
991 !!wm->pipe[pipe].sprite[1];
992 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
993 }
b445e3b0 994
ae80152d
VS		 995 if (fifo_size == 0 || num_planes > 1)
996 return false;
b445e3b0 997
ae80152d
VS		 998 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
999 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1000
ae80152d
VS		 1001 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1002 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003 continue;
b445e3b0 1004
ae80152d
VS		 1005 if (plane->pipe != pipe)
1006 continue;
9858425c 1007
ae80152d
VS		 1008 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1009 plane, fifo_size);
1010 if (wm->sr.plane != 0)
1011 break;
1012 }
1013
1014 return true;
b445e3b0
ED		 1015}
1016
ae80152d 1017static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS		 1018{
1019 struct drm_device *dev = crtc->dev;
3c2777fd 1020 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS		 1021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1022 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1023 bool cxsr_enabled;
ae80152d 1024 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1025
ae80152d
VS		 1026 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1027 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1028 to_intel_plane(crtc->primary),
1029 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1030
ae80152d
VS		 1031 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1032 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1033 to_intel_plane(crtc->cursor),
1034 0x3f);
3c2777fd 1035
ae80152d 1036 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1037
ae80152d
VS		 1038 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1039 return;
3c2777fd 1040
ae80152d
VS		 1041 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1042 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1043 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1044 wm.sr.plane, wm.sr.cursor);
3c2777fd 1045
fc1ac8de
VS		 1046 /*
1047 * FIXME DDR DVFS introduces massive memory latencies which
1048 * are not known to system agent so any deadline specified
1049 * by the display may not be respected. To support DDR DVFS
1050 * the watermark code needs to be rewritten to essentially
1051 * bypass deadline mechanism and rely solely on the
1052 * watermarks. For now disable DDR DVFS.
1053 */
1054 if (IS_CHERRYVIEW(dev_priv))
1055 chv_set_memory_dvfs(dev_priv, false);
1056
ae80152d
VS		 1057 if (!cxsr_enabled)
1058 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1059
ae80152d 1060 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS		 1061
1062 if (cxsr_enabled)
1063 intel_set_memory_cxsr(dev_priv, true);
1064}
1065
01e184cc
GB		 1066static void valleyview_update_sprite_wm(struct drm_plane *plane,
1067 struct drm_crtc *crtc,
1068 uint32_t sprite_width,
1069 uint32_t sprite_height,
1070 int pixel_size,
1071 bool enabled, bool scaled)
1072{
1073 struct drm_device *dev = crtc->dev;
1074 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS		 1075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1076 enum pipe pipe = intel_crtc->pipe;
01e184cc 1077 int sprite = to_intel_plane(plane)->plane;
ae80152d 1078 bool cxsr_enabled;
0018fda1 1079 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1080
ae80152d 1081 if (enabled) {
0018fda1 1082 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1083 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS		 1084
1085 wm.pipe[pipe].sprite[sprite] =
1086 vlv_compute_wm(intel_crtc,
1087 to_intel_plane(plane),
1088 vlv_get_fifo_size(dev, pipe, sprite+1));
1089 } else {
0018fda1 1090 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS		 1091 wm.pipe[pipe].sprite[sprite] = 0;
1092 }
1093
1094 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1095
1096 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1097 return;
1098
1099 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1100 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1101 sprite_name(pipe, sprite),
1102 wm.pipe[pipe].sprite[sprite],
1103 wm.sr.plane, wm.sr.cursor);
1104
1105 if (!cxsr_enabled)
1106 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1107
0018fda1 1108 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS		 1109
1110 if (cxsr_enabled)
1111 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB		 1112}
1113
ae80152d
VS		 1114#define single_plane_enabled(mask) is_power_of_2(mask)
1115
46ba614c 1116static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1117{
46ba614c 1118 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1119 static const int sr_latency_ns = 12000;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1122 int plane_sr, cursor_sr;
1123 unsigned int enabled = 0;
9858425c 1124 bool cxsr_enabled;
b445e3b0 1125
51cea1f4 1126 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1127 &g4x_wm_info, pessimal_latency_ns,
1128 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1129 &planea_wm, &cursora_wm))
51cea1f4 1130 enabled |= 1 << PIPE_A;
b445e3b0 1131
51cea1f4 1132 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1133 &g4x_wm_info, pessimal_latency_ns,
1134 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1135 &planeb_wm, &cursorb_wm))
51cea1f4 1136 enabled |= 1 << PIPE_B;
b445e3b0 1137
b445e3b0
ED		 1138 if (single_plane_enabled(enabled) &&
1139 g4x_compute_srwm(dev, ffs(enabled) - 1,
1140 sr_latency_ns,
1141 &g4x_wm_info,
1142 &g4x_cursor_wm_info,
52bd02d8 1143 &plane_sr, &cursor_sr)) {
9858425c 1144 cxsr_enabled = true;
52bd02d8 1145 } else {
9858425c 1146 cxsr_enabled = false;
5209b1f4 1147 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1148 plane_sr = cursor_sr = 0;
1149 }
b445e3b0 1150
a5043453
VS		 1151 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1152 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1153 planea_wm, cursora_wm,
1154 planeb_wm, cursorb_wm,
1155 plane_sr, cursor_sr);
1156
1157 I915_WRITE(DSPFW1,
1158 (plane_sr << DSPFW_SR_SHIFT) |
1159 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1160 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1161 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1162 I915_WRITE(DSPFW2,
8c919b28 1163 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1164 (cursora_wm << DSPFW_CURSORA_SHIFT));
1165 /* HPLL off in SR has some issues on G4x... disable it */
1166 I915_WRITE(DSPFW3,
8c919b28 1167 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1168 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1169
1170 if (cxsr_enabled)
1171 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1172}
1173
46ba614c 1174static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1175{
46ba614c 1176 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1177 struct drm_i915_private *dev_priv = dev->dev_private;
1178 struct drm_crtc *crtc;
1179 int srwm = 1;
1180 int cursor_sr = 16;
9858425c 1181 bool cxsr_enabled;
b445e3b0
ED		 1182
1183 /* Calc sr entries for one plane configs */
1184 crtc = single_enabled_crtc(dev);
1185 if (crtc) {
1186 /* self-refresh has much higher latency */
1187 static const int sr_latency_ns = 12000;
4fe8590a 1188 const struct drm_display_mode *adjusted_mode =
6e3c9717 1189 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1190 int clock = adjusted_mode->crtc_clock;
fec8cba3 1191 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1192 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1193 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1194 unsigned long line_time_us;
1195 int entries;
1196
922044c9 1197 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1198
1199 /* Use ns/us then divide to preserve precision */
1200 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1201 pixel_size * hdisplay;
1202 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1203 srwm = I965_FIFO_SIZE - entries;
1204 if (srwm < 0)
1205 srwm = 1;
1206 srwm &= 0x1ff;
1207 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1208 entries, srwm);
1209
1210 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1211 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1212 entries = DIV_ROUND_UP(entries,
1213 i965_cursor_wm_info.cacheline_size);
1214 cursor_sr = i965_cursor_wm_info.fifo_size -
1215 (entries + i965_cursor_wm_info.guard_size);
1216
1217 if (cursor_sr > i965_cursor_wm_info.max_wm)
1218 cursor_sr = i965_cursor_wm_info.max_wm;
1219
1220 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1221 "cursor %d\n", srwm, cursor_sr);
1222
9858425c 1223 cxsr_enabled = true;
b445e3b0 1224 } else {
9858425c 1225 cxsr_enabled = false;
b445e3b0 1226 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1227 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1228 }
1229
1230 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1231 srwm);
1232
1233 /* 965 has limitations... */
1234 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1235 (8 << DSPFW_CURSORB_SHIFT) |
1236 (8 << DSPFW_PLANEB_SHIFT) |
1237 (8 << DSPFW_PLANEA_SHIFT));
1238 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1239 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1240 /* update cursor SR watermark */
1241 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1242
1243 if (cxsr_enabled)
1244 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1245}
1246
46ba614c 1247static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1248{
46ba614c 1249 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 const struct intel_watermark_params *wm_info;
1252 uint32_t fwater_lo;
1253 uint32_t fwater_hi;
1254 int cwm, srwm = 1;
1255 int fifo_size;
1256 int planea_wm, planeb_wm;
1257 struct drm_crtc *crtc, *enabled = NULL;
1258
1259 if (IS_I945GM(dev))
1260 wm_info = &i945_wm_info;
1261 else if (!IS_GEN2(dev))
1262 wm_info = &i915_wm_info;
1263 else
9d539105 1264 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1265
1266 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1267 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1268 if (intel_crtc_active(crtc)) {
241bfc38 1269 const struct drm_display_mode *adjusted_mode;
59bea882 1270 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1271 if (IS_GEN2(dev))
1272 cpp = 4;
1273
6e3c9717 1274 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1275 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1276 wm_info, fifo_size, cpp,
5aef6003 1277 pessimal_latency_ns);
b445e3b0 1278 enabled = crtc;
9d539105 1279 } else {
b445e3b0 1280 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1281 if (planea_wm > (long)wm_info->max_wm)
1282 planea_wm = wm_info->max_wm;
1283 }
1284
1285 if (IS_GEN2(dev))
1286 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1287
1288 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1289 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1290 if (intel_crtc_active(crtc)) {
241bfc38 1291 const struct drm_display_mode *adjusted_mode;
59bea882 1292 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1293 if (IS_GEN2(dev))
1294 cpp = 4;
1295
6e3c9717 1296 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1297 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1298 wm_info, fifo_size, cpp,
5aef6003 1299 pessimal_latency_ns);
b445e3b0
ED		 1300 if (enabled == NULL)
1301 enabled = crtc;
1302 else
1303 enabled = NULL;
9d539105 1304 } else {
b445e3b0 1305 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1306 if (planeb_wm > (long)wm_info->max_wm)
1307 planeb_wm = wm_info->max_wm;
1308 }
b445e3b0
ED		 1309
1310 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1311
2ab1bc9d 1312 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1313 struct drm_i915_gem_object *obj;
2ab1bc9d 1314
59bea882 1315 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1316
1317 /* self-refresh seems busted with untiled */
2ff8fde1 1318 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1319 enabled = NULL;
1320 }
1321
b445e3b0
ED		 1322 /*
1323 * Overlay gets an aggressive default since video jitter is bad.
1324 */
1325 cwm = 2;
1326
1327 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1328 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1329
1330 /* Calc sr entries for one plane configs */
1331 if (HAS_FW_BLC(dev) && enabled) {
1332 /* self-refresh has much higher latency */
1333 static const int sr_latency_ns = 6000;
4fe8590a 1334 const struct drm_display_mode *adjusted_mode =
6e3c9717 1335 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1336 int clock = adjusted_mode->crtc_clock;
fec8cba3 1337 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1338 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1339 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1340 unsigned long line_time_us;
1341 int entries;
1342
922044c9 1343 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1344
1345 /* Use ns/us then divide to preserve precision */
1346 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1347 pixel_size * hdisplay;
1348 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1349 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1350 srwm = wm_info->fifo_size - entries;
1351 if (srwm < 0)
1352 srwm = 1;
1353
1354 if (IS_I945G(dev) || IS_I945GM(dev))
1355 I915_WRITE(FW_BLC_SELF,
1356 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1357 else if (IS_I915GM(dev))
1358 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1359 }
1360
1361 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1362 planea_wm, planeb_wm, cwm, srwm);
1363
1364 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1365 fwater_hi = (cwm & 0x1f);
1366
1367 /* Set request length to 8 cachelines per fetch */
1368 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1369 fwater_hi = fwater_hi | (1 << 8);
1370
1371 I915_WRITE(FW_BLC, fwater_lo);
1372 I915_WRITE(FW_BLC2, fwater_hi);
1373
5209b1f4
ID		 1374 if (enabled)
1375 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1376}
1377
feb56b93 1378static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1379{
46ba614c 1380 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1381 struct drm_i915_private *dev_priv = dev->dev_private;
1382 struct drm_crtc *crtc;
241bfc38 1383 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1384 uint32_t fwater_lo;
1385 int planea_wm;
1386
1387 crtc = single_enabled_crtc(dev);
1388 if (crtc == NULL)
1389 return;
1390
6e3c9717 1391 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1392 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1393 &i845_wm_info,
b445e3b0 1394 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1395 4, pessimal_latency_ns);
b445e3b0
ED		 1396 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1397 fwater_lo |= (3<<8) | planea_wm;
1398
1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1400
1401 I915_WRITE(FW_BLC, fwater_lo);
1402}
1403
3658729a
VS		 1404static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1405 struct drm_crtc *crtc)
801bcfff
PZ		 1406{
1407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1408 uint32_t pixel_rate;
801bcfff 1409
6e3c9717 1410 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1411
1412 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1413 * adjust the pixel_rate here. */
1414
6e3c9717 1415 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1416 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1417 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1418
6e3c9717
ACO		 1419 pipe_w = intel_crtc->config->pipe_src_w;
1420 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1421 pfit_w = (pfit_size >> 16) & 0xFFFF;
1422 pfit_h = pfit_size & 0xFFFF;
1423 if (pipe_w < pfit_w)
1424 pipe_w = pfit_w;
1425 if (pipe_h < pfit_h)
1426 pipe_h = pfit_h;
1427
1428 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1429 pfit_w * pfit_h);
1430 }
1431
1432 return pixel_rate;
1433}
1434
37126462 1435/* latency must be in 0.1us units. */
23297044 1436static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1437 uint32_t latency)
1438{
1439 uint64_t ret;
1440
3312ba65
VS		 1441 if (WARN(latency == 0, "Latency value missing\n"))
1442 return UINT_MAX;
1443
801bcfff
PZ		 1444 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1445 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1446
1447 return ret;
1448}
1449
37126462 1450/* latency must be in 0.1us units. */
23297044 1451static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1452 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1453 uint32_t latency)
1454{
1455 uint32_t ret;
1456
3312ba65
VS		 1457 if (WARN(latency == 0, "Latency value missing\n"))
1458 return UINT_MAX;
1459
801bcfff
PZ		 1460 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1461 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1462 ret = DIV_ROUND_UP(ret, 64) + 2;
1463 return ret;
1464}
1465
23297044 1466static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1467 uint8_t bytes_per_pixel)
1468{
1469 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1470}
1471
2ac96d2a
PB		 1472struct skl_pipe_wm_parameters {
1473 bool active;
1474 uint32_t pipe_htotal;
1475 uint32_t pixel_rate; /* in KHz */
1476 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1477 struct intel_plane_wm_parameters cursor;
1478};
1479
820c1980 1480struct ilk_pipe_wm_parameters {
801bcfff 1481 bool active;
801bcfff
PZ		 1482 uint32_t pipe_htotal;
1483 uint32_t pixel_rate;
c35426d2
VS		 1484 struct intel_plane_wm_parameters pri;
1485 struct intel_plane_wm_parameters spr;
1486 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1487};
1488
820c1980 1489struct ilk_wm_maximums {
cca32e9a
PZ		 1490 uint16_t pri;
1491 uint16_t spr;
1492 uint16_t cur;
1493 uint16_t fbc;
1494};
1495
240264f4
VS		 1496/* used in computing the new watermarks state */
1497struct intel_wm_config {
1498 unsigned int num_pipes_active;
1499 bool sprites_enabled;
1500 bool sprites_scaled;
240264f4
VS		 1501};
1502
37126462
VS		 1503/*
1504 * For both WM_PIPE and WM_LP.
1505 * mem_value must be in 0.1us units.
1506 */
820c1980 1507static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1508 uint32_t mem_value,
1509 bool is_lp)
801bcfff 1510{
cca32e9a
PZ		 1511 uint32_t method1, method2;
1512
c35426d2 1513 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1514 return 0;
1515
23297044 1516 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1517 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1518 mem_value);
1519
1520 if (!is_lp)
1521 return method1;
1522
23297044 1523 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1524 params->pipe_htotal,
c35426d2
VS		 1525 params->pri.horiz_pixels,
1526 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1527 mem_value);
1528
1529 return min(method1, method2);
801bcfff
PZ		 1530}
1531
37126462
VS		 1532/*
1533 * For both WM_PIPE and WM_LP.
1534 * mem_value must be in 0.1us units.
1535 */
820c1980 1536static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1537 uint32_t mem_value)
1538{
1539 uint32_t method1, method2;
1540
c35426d2 1541 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1542 return 0;
1543
23297044 1544 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1545 params->spr.bytes_per_pixel,
801bcfff 1546 mem_value);
23297044 1547 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1548 params->pipe_htotal,
c35426d2
VS		 1549 params->spr.horiz_pixels,
1550 params->spr.bytes_per_pixel,
801bcfff
PZ		 1551 mem_value);
1552 return min(method1, method2);
1553}
1554
37126462
VS		 1555/*
1556 * For both WM_PIPE and WM_LP.
1557 * mem_value must be in 0.1us units.
1558 */
820c1980 1559static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1560 uint32_t mem_value)
1561{
c35426d2 1562 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1563 return 0;
1564
23297044 1565 return ilk_wm_method2(params->pixel_rate,
801bcfff 1566 params->pipe_htotal,
c35426d2
VS		 1567 params->cur.horiz_pixels,
1568 params->cur.bytes_per_pixel,
801bcfff
PZ		 1569 mem_value);
1570}
1571
cca32e9a 1572/* Only for WM_LP. */
820c1980 1573static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1574 uint32_t pri_val)
cca32e9a 1575{
c35426d2 1576 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1577 return 0;
1578
23297044 1579 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1580 params->pri.horiz_pixels,
1581 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1582}
1583
158ae64f
VS		 1584static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1585{
416f4727
VS		 1586 if (INTEL_INFO(dev)->gen >= 8)
1587 return 3072;
1588 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1589 return 768;
1590 else
1591 return 512;
1592}
1593
4e975081
VS		 1594static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1595 int level, bool is_sprite)
1596{
1597 if (INTEL_INFO(dev)->gen >= 8)
1598 /* BDW primary/sprite plane watermarks */
1599 return level == 0 ? 255 : 2047;
1600 else if (INTEL_INFO(dev)->gen >= 7)
1601 /* IVB/HSW primary/sprite plane watermarks */
1602 return level == 0 ? 127 : 1023;
1603 else if (!is_sprite)
1604 /* ILK/SNB primary plane watermarks */
1605 return level == 0 ? 127 : 511;
1606 else
1607 /* ILK/SNB sprite plane watermarks */
1608 return level == 0 ? 63 : 255;
1609}
1610
1611static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1612 int level)
1613{
1614 if (INTEL_INFO(dev)->gen >= 7)
1615 return level == 0 ? 63 : 255;
1616 else
1617 return level == 0 ? 31 : 63;
1618}
1619
1620static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1621{
1622 if (INTEL_INFO(dev)->gen >= 8)
1623 return 31;
1624 else
1625 return 15;
1626}
1627
158ae64f
VS		 1628/* Calculate the maximum primary/sprite plane watermark */
1629static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1630 int level,
240264f4 1631 const struct intel_wm_config *config,
158ae64f
VS		 1632 enum intel_ddb_partitioning ddb_partitioning,
1633 bool is_sprite)
1634{
1635 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1636
1637 /* if sprites aren't enabled, sprites get nothing */
240264f4 1638 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1639 return 0;
1640
1641 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1642 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1643 fifo_size /= INTEL_INFO(dev)->num_pipes;
1644
1645 /*
1646 * For some reason the non self refresh
1647 * FIFO size is only half of the self
1648 * refresh FIFO size on ILK/SNB.
1649 */
1650 if (INTEL_INFO(dev)->gen <= 6)
1651 fifo_size /= 2;
1652 }
1653
240264f4 1654 if (config->sprites_enabled) {
158ae64f
VS		 1655 /* level 0 is always calculated with 1:1 split */
1656 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1657 if (is_sprite)
1658 fifo_size *= 5;
1659 fifo_size /= 6;
1660 } else {
1661 fifo_size /= 2;
1662 }
1663 }
1664
1665 /* clamp to max that the registers can hold */
4e975081 1666 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1667}
1668
1669/* Calculate the maximum cursor plane watermark */
1670static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1671 int level,
1672 const struct intel_wm_config *config)
158ae64f
VS		 1673{
1674 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1675 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1676 return 64;
1677
1678 /* otherwise just report max that registers can hold */
4e975081 1679 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1680}
1681
d34ff9c6 1682static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1683 int level,
1684 const struct intel_wm_config *config,
1685 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1686 struct ilk_wm_maximums *max)
158ae64f 1687{
240264f4
VS		 1688 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1689 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1690 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1691 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1692}
1693
a3cb4048
VS		 1694static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1695 int level,
1696 struct ilk_wm_maximums *max)
1697{
1698 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1699 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1700 max->cur = ilk_cursor_wm_reg_max(dev, level);
1701 max->fbc = ilk_fbc_wm_reg_max(dev);
1702}
1703
d9395655 1704static bool ilk_validate_wm_level(int level,
820c1980 1705 const struct ilk_wm_maximums *max,
d9395655 1706 struct intel_wm_level *result)
a9786a11
VS		 1707{
1708 bool ret;
1709
1710 /* already determined to be invalid? */
1711 if (!result->enable)
1712 return false;
1713
1714 result->enable = result->pri_val <= max->pri &&
1715 result->spr_val <= max->spr &&
1716 result->cur_val <= max->cur;
1717
1718 ret = result->enable;
1719
1720 /*
1721 * HACK until we can pre-compute everything,
1722 * and thus fail gracefully if LP0 watermarks
1723 * are exceeded...
1724 */
1725 if (level == 0 && !result->enable) {
1726 if (result->pri_val > max->pri)
1727 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1728 level, result->pri_val, max->pri);
1729 if (result->spr_val > max->spr)
1730 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1731 level, result->spr_val, max->spr);
1732 if (result->cur_val > max->cur)
1733 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1734 level, result->cur_val, max->cur);
1735
1736 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1737 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1738 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1739 result->enable = true;
1740 }
1741
a9786a11
VS		 1742 return ret;
1743}
1744
d34ff9c6 1745static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1746 int level,
820c1980 1747 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1748 struct intel_wm_level *result)
6f5ddd17
VS		 1749{
1750 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1751 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1752 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1753
1754 /* WM1+ latency values stored in 0.5us units */
1755 if (level > 0) {
1756 pri_latency *= 5;
1757 spr_latency *= 5;
1758 cur_latency *= 5;
1759 }
1760
1761 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1762 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1763 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1764 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1765 result->enable = true;
1766}
1767
801bcfff
PZ		 1768static uint32_t
1769hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1770{
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1773 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1774 u32 linetime, ips_linetime;
1f8eeabf 1775
3ef00284 1776 if (!intel_crtc->active)
801bcfff 1777 return 0;
1011d8c4 1778
1f8eeabf
ED		 1779 /* The WM are computed with base on how long it takes to fill a single
1780 * row at the given clock rate, multiplied by 8.
1781 * */
fec8cba3
JB		 1782 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1783 mode->crtc_clock);
1784 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1785 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1786
801bcfff
PZ		 1787 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1788 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1789}
1790
2af30a5c 1791static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1792{
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794
2af30a5c
PB		 1795 if (IS_GEN9(dev)) {
1796 uint32_t val;
4f947386 1797 int ret, i;
367294be 1798 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1799
1800 /* read the first set of memory latencies[0:3] */
1801 val = 0; /* data0 to be programmed to 0 for first set */
1802 mutex_lock(&dev_priv->rps.hw_lock);
1803 ret = sandybridge_pcode_read(dev_priv,
1804 GEN9_PCODE_READ_MEM_LATENCY,
1805 &val);
1806 mutex_unlock(&dev_priv->rps.hw_lock);
1807
1808 if (ret) {
1809 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1810 return;
1811 }
1812
1813 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1814 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1815 GEN9_MEM_LATENCY_LEVEL_MASK;
1816 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1817 GEN9_MEM_LATENCY_LEVEL_MASK;
1818 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1819 GEN9_MEM_LATENCY_LEVEL_MASK;
1820
1821 /* read the second set of memory latencies[4:7] */
1822 val = 1; /* data0 to be programmed to 1 for second set */
1823 mutex_lock(&dev_priv->rps.hw_lock);
1824 ret = sandybridge_pcode_read(dev_priv,
1825 GEN9_PCODE_READ_MEM_LATENCY,
1826 &val);
1827 mutex_unlock(&dev_priv->rps.hw_lock);
1828 if (ret) {
1829 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1830 return;
1831 }
1832
1833 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1834 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1835 GEN9_MEM_LATENCY_LEVEL_MASK;
1836 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1837 GEN9_MEM_LATENCY_LEVEL_MASK;
1838 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1839 GEN9_MEM_LATENCY_LEVEL_MASK;
1840
367294be 1841 /*
6f97235b
DL		 1842 * WaWmMemoryReadLatency:skl
1843 *
367294be
VK		 1844 * punit doesn't take into account the read latency so we need
1845 * to add 2us to the various latency levels we retrieve from
1846 * the punit.
1847 * - W0 is a bit special in that it's the only level that
1848 * can't be disabled if we want to have display working, so
1849 * we always add 2us there.
1850 * - For levels >=1, punit returns 0us latency when they are
1851 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1852 *
1853 * Additionally, if a level n (n > 1) has a 0us latency, all
1854 * levels m (m >= n) need to be disabled. We make sure to
1855 * sanitize the values out of the punit to satisfy this
1856 * requirement.
367294be
VK		 1857 */
1858 wm[0] += 2;
1859 for (level = 1; level <= max_level; level++)
1860 if (wm[level] != 0)
1861 wm[level] += 2;
4f947386
VK		 1862 else {
1863 for (i = level + 1; i <= max_level; i++)
1864 wm[i] = 0;
367294be 1865
4f947386
VK		 1866 break;
1867 }
2af30a5c 1868 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1869 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1870
1871 wm[0] = (sskpd >> 56) & 0xFF;
1872 if (wm[0] == 0)
1873 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1874 wm[1] = (sskpd >> 4) & 0xFF;
1875 wm[2] = (sskpd >> 12) & 0xFF;
1876 wm[3] = (sskpd >> 20) & 0x1FF;
1877 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1878 } else if (INTEL_INFO(dev)->gen >= 6) {
1879 uint32_t sskpd = I915_READ(MCH_SSKPD);
1880
1881 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1882 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1883 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1884 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1885 } else if (INTEL_INFO(dev)->gen >= 5) {
1886 uint32_t mltr = I915_READ(MLTR_ILK);
1887
1888 /* ILK primary LP0 latency is 700 ns */
1889 wm[0] = 7;
1890 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1891 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1892 }
1893}
1894
53615a5e
VS		 1895static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1896{
1897 /* ILK sprite LP0 latency is 1300 ns */
1898 if (INTEL_INFO(dev)->gen == 5)
1899 wm[0] = 13;
1900}
1901
1902static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1903{
1904 /* ILK cursor LP0 latency is 1300 ns */
1905 if (INTEL_INFO(dev)->gen == 5)
1906 wm[0] = 13;
1907
1908 /* WaDoubleCursorLP3Latency:ivb */
1909 if (IS_IVYBRIDGE(dev))
1910 wm[3] *= 2;
1911}
1912
546c81fd 1913int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1914{
26ec971e 1915 /* how many WM levels are we expecting */
2af30a5c
PB		 1916 if (IS_GEN9(dev))
1917 return 7;
1918 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1919 return 4;
26ec971e 1920 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1921 return 3;
26ec971e 1922 else
ad0d6dc4
VS		 1923 return 2;
1924}
7526ed79 1925
ad0d6dc4
VS		 1926static void intel_print_wm_latency(struct drm_device *dev,
1927 const char *name,
2af30a5c 1928 const uint16_t wm[8])
ad0d6dc4
VS		 1929{
1930 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1931
1932 for (level = 0; level <= max_level; level++) {
1933 unsigned int latency = wm[level];
1934
1935 if (latency == 0) {
1936 DRM_ERROR("%s WM%d latency not provided\n",
1937 name, level);
1938 continue;
1939 }
1940
2af30a5c
PB		 1941 /*
1942 * - latencies are in us on gen9.
1943 * - before then, WM1+ latency values are in 0.5us units
1944 */
1945 if (IS_GEN9(dev))
1946 latency *= 10;
1947 else if (level > 0)
26ec971e
VS		 1948 latency *= 5;
1949
1950 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1951 name, level, wm[level],
1952 latency / 10, latency % 10);
1953 }
1954}
1955
e95a2f75
VS		 1956static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1957 uint16_t wm[5], uint16_t min)
1958{
1959 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1960
1961 if (wm[0] >= min)
1962 return false;
1963
1964 wm[0] = max(wm[0], min);
1965 for (level = 1; level <= max_level; level++)
1966 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1967
1968 return true;
1969}
1970
1971static void snb_wm_latency_quirk(struct drm_device *dev)
1972{
1973 struct drm_i915_private *dev_priv = dev->dev_private;
1974 bool changed;
1975
1976 /*
1977 * The BIOS provided WM memory latency values are often
1978 * inadequate for high resolution displays. Adjust them.
1979 */
1980 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1981 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1982 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1983
1984 if (!changed)
1985 return;
1986
1987 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1988 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1989 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1990 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
1991}
1992
fa50ad61 1993static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 1994{
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996
1997 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
1998
1999 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2000 sizeof(dev_priv->wm.pri_latency));
2001 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2002 sizeof(dev_priv->wm.pri_latency));
2003
2004 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2005 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2006
2007 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2008 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2009 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2010
2011 if (IS_GEN6(dev))
2012 snb_wm_latency_quirk(dev);
53615a5e
VS		 2013}
2014
2af30a5c
PB		 2015static void skl_setup_wm_latency(struct drm_device *dev)
2016{
2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018
2019 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2020 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2021}
2022
820c1980 2023static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2024 struct ilk_pipe_wm_parameters *p)
1011d8c4 2025{
7c4a395f
VS		 2026 struct drm_device *dev = crtc->dev;
2027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2028 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2029 struct drm_plane *plane;
1011d8c4 2030
3ef00284 2031 if (!intel_crtc->active)
2a44b76b 2032 return;
801bcfff 2033
2a44b76b 2034 p->active = true;
6e3c9717 2035 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b 2036 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
59bea882 2037 p->pri.bytes_per_pixel = crtc->primary->state->fb->bits_per_pixel / 8;
2a44b76b 2038 p->cur.bytes_per_pixel = 4;
6e3c9717 2039 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2040 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2a44b76b
VS		 2041 /* TODO: for now, assume primary and cursor planes are always enabled. */
2042 p->pri.enabled = true;
2043 p->cur.enabled = true;
7c4a395f 2044
af2b653b 2045 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2046 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2047
2a44b76b 2048 if (intel_plane->pipe == pipe) {
7c4a395f 2049 p->spr = intel_plane->wm;
2a44b76b
VS		 2050 break;
2051 }
2052 }
2053}
2054
2055static void ilk_compute_wm_config(struct drm_device *dev,
2056 struct intel_wm_config *config)
2057{
2058 struct intel_crtc *intel_crtc;
2059
2060 /* Compute the currently _active_ config */
d3fcc808 2061 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2062 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2063
2a44b76b
VS		 2064 if (!wm->pipe_enabled)
2065 continue;
cca32e9a 2066
2a44b76b
VS		 2067 config->sprites_enabled |= wm->sprites_enabled;
2068 config->sprites_scaled |= wm->sprites_scaled;
2069 config->num_pipes_active++;
cca32e9a 2070 }
801bcfff
PZ		 2071}
2072
0b2ae6d7
VS		 2073/* Compute new watermarks for the pipe */
2074static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2075 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2076 struct intel_pipe_wm *pipe_wm)
2077{
2078 struct drm_device *dev = crtc->dev;
d34ff9c6 2079 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2080 int level, max_level = ilk_wm_max_level(dev);
2081 /* LP0 watermark maximums depend on this pipe alone */
2082 struct intel_wm_config config = {
2083 .num_pipes_active = 1,
2084 .sprites_enabled = params->spr.enabled,
2085 .sprites_scaled = params->spr.scaled,
2086 };
820c1980 2087 struct ilk_wm_maximums max;
0b2ae6d7 2088
2a44b76b
VS		 2089 pipe_wm->pipe_enabled = params->active;
2090 pipe_wm->sprites_enabled = params->spr.enabled;
2091 pipe_wm->sprites_scaled = params->spr.scaled;
2092
7b39a0b7
VS		 2093 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2094 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2095 max_level = 1;
2096
2097 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2098 if (params->spr.scaled)
2099 max_level = 0;
2100
a3cb4048 2101 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2102
a42a5719 2103 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2104 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2105
a3cb4048
VS		 2106 /* LP0 watermarks always use 1/2 DDB partitioning */
2107 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2108
0b2ae6d7 2109 /* At least LP0 must be valid */
a3cb4048
VS		 2110 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2111 return false;
2112
2113 ilk_compute_wm_reg_maximums(dev, 1, &max);
2114
2115 for (level = 1; level <= max_level; level++) {
2116 struct intel_wm_level wm = {};
2117
2118 ilk_compute_wm_level(dev_priv, level, params, &wm);
2119
2120 /*
2121 * Disable any watermark level that exceeds the
2122 * register maximums since such watermarks are
2123 * always invalid.
2124 */
2125 if (!ilk_validate_wm_level(level, &max, &wm))
2126 break;
2127
2128 pipe_wm->wm[level] = wm;
2129 }
2130
2131 return true;
0b2ae6d7
VS		 2132}
2133
2134/*
2135 * Merge the watermarks from all active pipes for a specific level.
2136 */
2137static void ilk_merge_wm_level(struct drm_device *dev,
2138 int level,
2139 struct intel_wm_level *ret_wm)
2140{
2141 const struct intel_crtc *intel_crtc;
2142
d52fea5b
VS		 2143 ret_wm->enable = true;
2144
d3fcc808 2145 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2146 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2147 const struct intel_wm_level *wm = &active->wm[level];
2148
2149 if (!active->pipe_enabled)
2150 continue;
0b2ae6d7 2151
d52fea5b
VS		 2152 /*
2153 * The watermark values may have been used in the past,
2154 * so we must maintain them in the registers for some
2155 * time even if the level is now disabled.
2156 */
0b2ae6d7 2157 if (!wm->enable)
d52fea5b 2158 ret_wm->enable = false;
0b2ae6d7
VS		 2159
2160 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2161 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2162 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2163 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2164 }
0b2ae6d7
VS		 2165}
2166
2167/*
2168 * Merge all low power watermarks for all active pipes.
2169 */
2170static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2171 const struct intel_wm_config *config,
820c1980 2172 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2173 struct intel_pipe_wm *merged)
2174{
2175 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2176 int last_enabled_level = max_level;
0b2ae6d7 2177
0ba22e26
VS		 2178 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2179 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2180 config->num_pipes_active > 1)
2181 return;
2182
6c8b6c28
VS		 2183 /* ILK: FBC WM must be disabled always */
2184 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2185
2186 /* merge each WM1+ level */
2187 for (level = 1; level <= max_level; level++) {
2188 struct intel_wm_level *wm = &merged->wm[level];
2189
2190 ilk_merge_wm_level(dev, level, wm);
2191
d52fea5b
VS		 2192 if (level > last_enabled_level)
2193 wm->enable = false;
2194 else if (!ilk_validate_wm_level(level, max, wm))
2195 /* make sure all following levels get disabled */
2196 last_enabled_level = level - 1;
0b2ae6d7
VS		 2197
2198 /*
2199 * The spec says it is preferred to disable
2200 * FBC WMs instead of disabling a WM level.
2201 */
2202 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2203 if (wm->enable)
2204 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2205 wm->fbc_val = 0;
2206 }
2207 }
6c8b6c28
VS		 2208
2209 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2210 /*
2211 * FIXME this is racy. FBC might get enabled later.
2212 * What we should check here is whether FBC can be
2213 * enabled sometime later.
2214 */
2215 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2216 for (level = 2; level <= max_level; level++) {
2217 struct intel_wm_level *wm = &merged->wm[level];
2218
2219 wm->enable = false;
2220 }
2221 }
0b2ae6d7
VS		 2222}
2223
b380ca3c
VS		 2224static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2225{
2226 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2227 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2228}
2229
a68d68ee
VS		 2230/* The value we need to program into the WM_LPx latency field */
2231static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2232{
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234
a42a5719 2235 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2236 return 2 * level;
2237 else
2238 return dev_priv->wm.pri_latency[level];
2239}
2240
820c1980 2241static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2242 const struct intel_pipe_wm *merged,
609cedef 2243 enum intel_ddb_partitioning partitioning,
820c1980 2244 struct ilk_wm_values *results)
801bcfff 2245{
0b2ae6d7
VS		 2246 struct intel_crtc *intel_crtc;
2247 int level, wm_lp;
cca32e9a 2248
0362c781 2249 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2250 results->partitioning = partitioning;
cca32e9a 2251
0b2ae6d7 2252 /* LP1+ register values */
cca32e9a 2253 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2254 const struct intel_wm_level *r;
801bcfff 2255
b380ca3c 2256 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2257
0362c781 2258 r = &merged->wm[level];
cca32e9a 2259
d52fea5b
VS		 2260 /*
2261 * Maintain the watermark values even if the level is
2262 * disabled. Doing otherwise could cause underruns.
2263 */
2264 results->wm_lp[wm_lp - 1] =
a68d68ee 2265 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2266 (r->pri_val << WM1_LP_SR_SHIFT) |
2267 r->cur_val;
2268
d52fea5b
VS		 2269 if (r->enable)
2270 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2271
416f4727
VS		 2272 if (INTEL_INFO(dev)->gen >= 8)
2273 results->wm_lp[wm_lp - 1] |=
2274 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2275 else
2276 results->wm_lp[wm_lp - 1] |=
2277 r->fbc_val << WM1_LP_FBC_SHIFT;
2278
d52fea5b
VS		 2279 /*
2280 * Always set WM1S_LP_EN when spr_val != 0, even if the
2281 * level is disabled. Doing otherwise could cause underruns.
2282 */
6cef2b8a
VS		 2283 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2284 WARN_ON(wm_lp != 1);
2285 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2286 } else
2287 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2288 }
801bcfff 2289
0b2ae6d7 2290 /* LP0 register values */
d3fcc808 2291 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2292 enum pipe pipe = intel_crtc->pipe;
2293 const struct intel_wm_level *r =
2294 &intel_crtc->wm.active.wm[0];
2295
2296 if (WARN_ON(!r->enable))
2297 continue;
2298
2299 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2300
0b2ae6d7
VS		 2301 results->wm_pipe[pipe] =
2302 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2303 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2304 r->cur_val;
801bcfff
PZ		 2305 }
2306}
2307
861f3389
PZ		 2308/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2309 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2310static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2311 struct intel_pipe_wm *r1,
2312 struct intel_pipe_wm *r2)
861f3389 2313{
198a1e9b
VS		 2314 int level, max_level = ilk_wm_max_level(dev);
2315 int level1 = 0, level2 = 0;
861f3389 2316
198a1e9b
VS		 2317 for (level = 1; level <= max_level; level++) {
2318 if (r1->wm[level].enable)
2319 level1 = level;
2320 if (r2->wm[level].enable)
2321 level2 = level;
861f3389
PZ		 2322 }
2323
198a1e9b
VS		 2324 if (level1 == level2) {
2325 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2326 return r2;
2327 else
2328 return r1;
198a1e9b 2329 } else if (level1 > level2) {
861f3389
PZ		 2330 return r1;
2331 } else {
2332 return r2;
2333 }
2334}
2335
49a687c4
VS		 2336/* dirty bits used to track which watermarks need changes */
2337#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2338#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2339#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2340#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2341#define WM_DIRTY_FBC (1 << 24)
2342#define WM_DIRTY_DDB (1 << 25)
2343
055e393f 2344static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2345 const struct ilk_wm_values *old,
2346 const struct ilk_wm_values *new)
49a687c4
VS		 2347{
2348 unsigned int dirty = 0;
2349 enum pipe pipe;
2350 int wm_lp;
2351
055e393f 2352 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2353 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2354 dirty |= WM_DIRTY_LINETIME(pipe);
2355 /* Must disable LP1+ watermarks too */
2356 dirty |= WM_DIRTY_LP_ALL;
2357 }
2358
2359 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2360 dirty |= WM_DIRTY_PIPE(pipe);
2361 /* Must disable LP1+ watermarks too */
2362 dirty |= WM_DIRTY_LP_ALL;
2363 }
2364 }
2365
2366 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2367 dirty |= WM_DIRTY_FBC;
2368 /* Must disable LP1+ watermarks too */
2369 dirty |= WM_DIRTY_LP_ALL;
2370 }
2371
2372 if (old->partitioning != new->partitioning) {
2373 dirty |= WM_DIRTY_DDB;
2374 /* Must disable LP1+ watermarks too */
2375 dirty |= WM_DIRTY_LP_ALL;
2376 }
2377
2378 /* LP1+ watermarks already deemed dirty, no need to continue */
2379 if (dirty & WM_DIRTY_LP_ALL)
2380 return dirty;
2381
2382 /* Find the lowest numbered LP1+ watermark in need of an update... */
2383 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2384 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2385 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2386 break;
2387 }
2388
2389 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2390 for (; wm_lp <= 3; wm_lp++)
2391 dirty |= WM_DIRTY_LP(wm_lp);
2392
2393 return dirty;
2394}
2395
8553c18e
VS		 2396static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2397 unsigned int dirty)
801bcfff 2398{
820c1980 2399 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2400 bool changed = false;
801bcfff 2401
facd619b
VS		 2402 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2403 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2404 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2405 changed = true;
facd619b
VS		 2406 }
2407 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2408 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2409 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2410 changed = true;
facd619b
VS		 2411 }
2412 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2413 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2414 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2415 changed = true;
facd619b 2416 }
801bcfff 2417
facd619b
VS		 2418 /*
2419 * Don't touch WM1S_LP_EN here.
2420 * Doing so could cause underruns.
2421 */
6cef2b8a 2422
8553c18e
VS		 2423 return changed;
2424}
2425
2426/*
2427 * The spec says we shouldn't write when we don't need, because every write
2428 * causes WMs to be re-evaluated, expending some power.
2429 */
820c1980
ID		 2430static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2431 struct ilk_wm_values *results)
8553c18e
VS		 2432{
2433 struct drm_device *dev = dev_priv->dev;
820c1980 2434 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2435 unsigned int dirty;
2436 uint32_t val;
2437
055e393f 2438 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2439 if (!dirty)
2440 return;
2441
2442 _ilk_disable_lp_wm(dev_priv, dirty);
2443
49a687c4 2444 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2445 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2446 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2447 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2448 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2449 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2450
49a687c4 2451 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2452 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2453 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2454 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2455 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2456 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2457
49a687c4 2458 if (dirty & WM_DIRTY_DDB) {
a42a5719 2459 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2460 val = I915_READ(WM_MISC);
2461 if (results->partitioning == INTEL_DDB_PART_1_2)
2462 val &= ~WM_MISC_DATA_PARTITION_5_6;
2463 else
2464 val |= WM_MISC_DATA_PARTITION_5_6;
2465 I915_WRITE(WM_MISC, val);
2466 } else {
2467 val = I915_READ(DISP_ARB_CTL2);
2468 if (results->partitioning == INTEL_DDB_PART_1_2)
2469 val &= ~DISP_DATA_PARTITION_5_6;
2470 else
2471 val |= DISP_DATA_PARTITION_5_6;
2472 I915_WRITE(DISP_ARB_CTL2, val);
2473 }
1011d8c4
PZ		 2474 }
2475
49a687c4 2476 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2477 val = I915_READ(DISP_ARB_CTL);
2478 if (results->enable_fbc_wm)
2479 val &= ~DISP_FBC_WM_DIS;
2480 else
2481 val |= DISP_FBC_WM_DIS;
2482 I915_WRITE(DISP_ARB_CTL, val);
2483 }
2484
954911eb
ID		 2485 if (dirty & WM_DIRTY_LP(1) &&
2486 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2487 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2488
2489 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2490 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2491 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2492 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2493 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2494 }
801bcfff 2495
facd619b 2496 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2497 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2498 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2499 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2500 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2501 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2502
2503 dev_priv->wm.hw = *results;
801bcfff
PZ		 2504}
2505
8553c18e
VS		 2506static bool ilk_disable_lp_wm(struct drm_device *dev)
2507{
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509
2510 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2511}
2512
b9cec075
DL		 2513/*
2514 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2515 * different active planes.
2516 */
2517
2518#define SKL_DDB_SIZE 896 /* in blocks */
2519
2520static void
2521skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2522 struct drm_crtc *for_crtc,
2523 const struct intel_wm_config *config,
2524 const struct skl_pipe_wm_parameters *params,
2525 struct skl_ddb_entry *alloc /* out */)
2526{
2527 struct drm_crtc *crtc;
2528 unsigned int pipe_size, ddb_size;
2529 int nth_active_pipe;
2530
2531 if (!params->active) {
2532 alloc->start = 0;
2533 alloc->end = 0;
2534 return;
2535 }
2536
2537 ddb_size = SKL_DDB_SIZE;
2538
2539 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2540
2541 nth_active_pipe = 0;
2542 for_each_crtc(dev, crtc) {
3ef00284 2543 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2544 continue;
2545
2546 if (crtc == for_crtc)
2547 break;
2548
2549 nth_active_pipe++;
2550 }
2551
2552 pipe_size = ddb_size / config->num_pipes_active;
2553 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2554 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2555}
2556
2557static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2558{
2559 if (config->num_pipes_active == 1)
2560 return 32;
2561
2562 return 8;
2563}
2564
a269c583
DL		 2565static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2566{
2567 entry->start = reg & 0x3ff;
2568 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2569 if (entry->end)
2570 entry->end += 1;
a269c583
DL		 2571}
2572
08db6652
DL		 2573void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2574 struct skl_ddb_allocation *ddb /* out */)
a269c583 2575{
a269c583
DL		 2576 enum pipe pipe;
2577 int plane;
2578 u32 val;
2579
2580 for_each_pipe(dev_priv, pipe) {
dd740780 2581 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2582 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2583 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2584 val);
2585 }
2586
2587 val = I915_READ(CUR_BUF_CFG(pipe));
2588 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2589 }
2590}
2591
b9cec075
DL		 2592static unsigned int
2593skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2594{
2595 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2596}
2597
2598/*
2599 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2600 * a 8192x4096@32bpp framebuffer:
2601 * 3 * 4096 * 8192 * 4 < 2^32
2602 */
2603static unsigned int
2604skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2605 const struct skl_pipe_wm_parameters *params)
2606{
2607 unsigned int total_data_rate = 0;
2608 int plane;
2609
2610 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2611 const struct intel_plane_wm_parameters *p;
2612
2613 p = &params->plane[plane];
2614 if (!p->enabled)
2615 continue;
2616
2617 total_data_rate += skl_plane_relative_data_rate(p);
2618 }
2619
2620 return total_data_rate;
2621}
2622
2623static void
2624skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2625 const struct intel_wm_config *config,
2626 const struct skl_pipe_wm_parameters *params,
2627 struct skl_ddb_allocation *ddb /* out */)
2628{
2629 struct drm_device *dev = crtc->dev;
dd740780 2630 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2632 enum pipe pipe = intel_crtc->pipe;
34bb56af 2633 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2634 uint16_t alloc_size, start, cursor_blocks;
80958155 2635 uint16_t minimum[I915_MAX_PLANES];
b9cec075
DL		 2636 unsigned int total_data_rate;
2637 int plane;
2638
34bb56af
DL		 2639 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2640 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2641 if (alloc_size == 0) {
2642 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2643 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2644 return;
2645 }
2646
2647 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2648 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2649 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2650
2651 alloc_size -= cursor_blocks;
34bb56af 2652 alloc->end -= cursor_blocks;
b9cec075 2653
80958155 2654 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2655 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2656 const struct intel_plane_wm_parameters *p;
2657
2658 p = &params->plane[plane];
2659 if (!p->enabled)
2660 continue;
2661
2662 minimum[plane] = 8;
2663 alloc_size -= minimum[plane];
2664 }
2665
b9cec075 2666 /*
80958155
DL		 2667 * 2. Distribute the remaining space in proportion to the amount of
2668 * data each plane needs to fetch from memory.
b9cec075
DL		 2669 *
2670 * FIXME: we may not allocate every single block here.
2671 */
2672 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2673
34bb56af 2674 start = alloc->start;
b9cec075
DL		 2675 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2676 const struct intel_plane_wm_parameters *p;
2677 unsigned int data_rate;
2678 uint16_t plane_blocks;
2679
2680 p = &params->plane[plane];
2681 if (!p->enabled)
2682 continue;
2683
2684 data_rate = skl_plane_relative_data_rate(p);
2685
2686 /*
2687 * promote the expression to 64 bits to avoid overflowing, the
2688 * result is < available as data_rate / total_data_rate < 1
2689 */
80958155
DL		 2690 plane_blocks = minimum[plane];
2691 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2692 total_data_rate);
b9cec075
DL		 2693
2694 ddb->plane[pipe][plane].start = start;
16160e3d 2695 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2696
2697 start += plane_blocks;
2698 }
2699
2700}
2701
5cec258b 2702static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2703{
2704 /* TODO: Take into account the scalers once we support them */
2d112de7 2705 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2706}
2707
2708/*
2709 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2710 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2711 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2712 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2713*/
2714static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2715 uint32_t latency)
2716{
2717 uint32_t wm_intermediate_val, ret;
2718
2719 if (latency == 0)
2720 return UINT_MAX;
2721
d4c2aa60 2722 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 2723 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2724
2725 return ret;
2726}
2727
2728static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2729 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2730 uint64_t tiling, uint32_t latency)
2d41c0b5 2731{
d4c2aa60
TU		 2732 uint32_t ret;
2733 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2734 uint32_t wm_intermediate_val;
2d41c0b5
PB		 2735
2736 if (latency == 0)
2737 return UINT_MAX;
2738
2739 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 2740
2741 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2742 tiling == I915_FORMAT_MOD_Yf_TILED) {
2743 plane_bytes_per_line *= 4;
2744 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2745 plane_blocks_per_line /= 4;
2746 } else {
2747 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2748 }
2749
2d41c0b5
PB		 2750 wm_intermediate_val = latency * pixel_rate;
2751 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2752 plane_blocks_per_line;
2d41c0b5
PB		 2753
2754 return ret;
2755}
2756
2d41c0b5
PB		 2757static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2758 const struct intel_crtc *intel_crtc)
2759{
2760 struct drm_device *dev = intel_crtc->base.dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2763 enum pipe pipe = intel_crtc->pipe;
2764
2765 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2766 sizeof(new_ddb->plane[pipe])))
2767 return true;
2768
2769 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2770 sizeof(new_ddb->cursor[pipe])))
2771 return true;
2772
2773 return false;
2774}
2775
2776static void skl_compute_wm_global_parameters(struct drm_device *dev,
2777 struct intel_wm_config *config)
2778{
2779 struct drm_crtc *crtc;
2780 struct drm_plane *plane;
2781
2782 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2783 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 2784
2785 /* FIXME: I don't think we need those two global parameters on SKL */
2786 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2787 struct intel_plane *intel_plane = to_intel_plane(plane);
2788
2789 config->sprites_enabled |= intel_plane->wm.enabled;
2790 config->sprites_scaled |= intel_plane->wm.scaled;
2791 }
2792}
2793
2794static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2795 struct skl_pipe_wm_parameters *p)
2796{
2797 struct drm_device *dev = crtc->dev;
2798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799 enum pipe pipe = intel_crtc->pipe;
2800 struct drm_plane *plane;
0fda6568 2801 struct drm_framebuffer *fb;
2d41c0b5
PB		 2802 int i = 1; /* Index for sprite planes start */
2803
3ef00284 2804 p->active = intel_crtc->active;
2d41c0b5 2805 if (p->active) {
6e3c9717
ACO		 2806 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2807 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5
PB		 2808
2809 /*
2810 * For now, assume primary and cursor planes are always enabled.
2811 */
2812 p->plane[0].enabled = true;
2813 p->plane[0].bytes_per_pixel =
59bea882 2814 crtc->primary->state->fb->bits_per_pixel / 8;
6e3c9717
ACO		 2815 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2816 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
0fda6568
TU		 2817 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2818 fb = crtc->primary->state->fb;
2819 /*
2820 * Framebuffer can be NULL on plane disable, but it does not
2821 * matter for watermarks if we assume no tiling in that case.
2822 */
2823 if (fb)
2824 p->plane[0].tiling = fb->modifier[0];
2d41c0b5
PB		 2825
2826 p->cursor.enabled = true;
2827 p->cursor.bytes_per_pixel = 4;
3dd512fb
MR		 2828 p->cursor.horiz_pixels = intel_crtc->base.cursor->state->crtc_w ?
2829 intel_crtc->base.cursor->state->crtc_w : 64;
2d41c0b5
PB		 2830 }
2831
2832 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2833 struct intel_plane *intel_plane = to_intel_plane(plane);
2834
a712f8eb
SJ		 2835 if (intel_plane->pipe == pipe &&
2836 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2837 p->plane[i++] = intel_plane->wm;
2838 }
2839}
2840
d4c2aa60
TU		 2841static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2842 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2843 struct intel_plane_wm_parameters *p_params,
2844 uint16_t ddb_allocation,
d4c2aa60 2845 int level,
afb024aa
DL		 2846 uint16_t *out_blocks, /* out */
2847 uint8_t *out_lines /* out */)
2d41c0b5 2848{
d4c2aa60
TU		 2849 uint32_t latency = dev_priv->wm.skl_latency[level];
2850 uint32_t method1, method2;
2851 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2852 uint32_t res_blocks, res_lines;
2853 uint32_t selected_result;
2d41c0b5 2854
d4c2aa60 2855 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2856 return false;
2857
2858 method1 = skl_wm_method1(p->pixel_rate,
2859 p_params->bytes_per_pixel,
d4c2aa60 2860 latency);
2d41c0b5
PB		 2861 method2 = skl_wm_method2(p->pixel_rate,
2862 p->pipe_htotal,
2863 p_params->horiz_pixels,
2864 p_params->bytes_per_pixel,
0fda6568 2865 p_params->tiling,
d4c2aa60 2866 latency);
2d41c0b5
PB		 2867
2868 plane_bytes_per_line = p_params->horiz_pixels *
2869 p_params->bytes_per_pixel;
d4c2aa60 2870 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2871
0fda6568
TU		 2872 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2873 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
2874 uint32_t y_tile_minimum = plane_blocks_per_line * 4;
2875 selected_result = max(method2, y_tile_minimum);
2876 } else {
2877 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2878 selected_result = min(method1, method2);
2879 else
2880 selected_result = method1;
2881 }
2d41c0b5 2882
d4c2aa60
TU		 2883 res_blocks = selected_result + 1;
2884 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2885
0fda6568
TU		 2886 if (level >= 1 && level <= 7) {
2887 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2888 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2889 res_lines += 4;
2890 else
2891 res_blocks++;
2892 }
e6d66171 2893
d4c2aa60 2894 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 2895 return false;
2896
2897 *out_blocks = res_blocks;
2898 *out_lines = res_lines;
2d41c0b5
PB		 2899
2900 return true;
2901}
2902
2903static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2904 struct skl_ddb_allocation *ddb,
2905 struct skl_pipe_wm_parameters *p,
2906 enum pipe pipe,
2907 int level,
2908 int num_planes,
2909 struct skl_wm_level *result)
2910{
2d41c0b5
PB		 2911 uint16_t ddb_blocks;
2912 int i;
2913
2914 for (i = 0; i < num_planes; i++) {
2915 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2916
d4c2aa60
TU		 2917 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2918 p, &p->plane[i],
2d41c0b5 2919 ddb_blocks,
d4c2aa60 2920 level,
2d41c0b5
PB		 2921 &result->plane_res_b[i],
2922 &result->plane_res_l[i]);
2923 }
2924
2925 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 2926 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2927 ddb_blocks, level,
2928 &result->cursor_res_b,
2d41c0b5
PB		 2929 &result->cursor_res_l);
2930}
2931
407b50f3
DL		 2932static uint32_t
2933skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2934{
3ef00284 2935 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 2936 return 0;
2937
2938 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2939
2940}
2941
2942static void skl_compute_transition_wm(struct drm_crtc *crtc,
2943 struct skl_pipe_wm_parameters *params,
9414f563 2944 struct skl_wm_level *trans_wm /* out */)
407b50f3 2945{
9414f563
DL		 2946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947 int i;
2948
407b50f3
DL		 2949 if (!params->active)
2950 return;
9414f563
DL		 2951
2952 /* Until we know more, just disable transition WMs */
2953 for (i = 0; i < intel_num_planes(intel_crtc); i++)
2954 trans_wm->plane_en[i] = false;
2955 trans_wm->cursor_en = false;
407b50f3
DL		 2956}
2957
2d41c0b5
PB		 2958static void skl_compute_pipe_wm(struct drm_crtc *crtc,
2959 struct skl_ddb_allocation *ddb,
2960 struct skl_pipe_wm_parameters *params,
2961 struct skl_pipe_wm *pipe_wm)
2962{
2963 struct drm_device *dev = crtc->dev;
2964 const struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2966 int level, max_level = ilk_wm_max_level(dev);
2967
2968 for (level = 0; level <= max_level; level++) {
2969 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
2970 level, intel_num_planes(intel_crtc),
2971 &pipe_wm->wm[level]);
2972 }
2973 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
2974
9414f563 2975 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 2976}
2977
2978static void skl_compute_wm_results(struct drm_device *dev,
2979 struct skl_pipe_wm_parameters *p,
2980 struct skl_pipe_wm *p_wm,
2981 struct skl_wm_values *r,
2982 struct intel_crtc *intel_crtc)
2983{
2984 int level, max_level = ilk_wm_max_level(dev);
2985 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 2986 uint32_t temp;
2987 int i;
2d41c0b5
PB		 2988
2989 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 2990 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2991 temp = 0;
2d41c0b5
PB		 2992
2993 temp |= p_wm->wm[level].plane_res_l[i] <<
2994 PLANE_WM_LINES_SHIFT;
2995 temp |= p_wm->wm[level].plane_res_b[i];
2996 if (p_wm->wm[level].plane_en[i])
2997 temp |= PLANE_WM_EN;
2998
2999 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3000 }
3001
3002 temp = 0;
2d41c0b5
PB		 3003
3004 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3005 temp |= p_wm->wm[level].cursor_res_b;
3006
3007 if (p_wm->wm[level].cursor_en)
3008 temp |= PLANE_WM_EN;
3009
3010 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3011
3012 }
3013
9414f563
DL		 3014 /* transition WMs */
3015 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3016 temp = 0;
3017 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3018 temp |= p_wm->trans_wm.plane_res_b[i];
3019 if (p_wm->trans_wm.plane_en[i])
3020 temp |= PLANE_WM_EN;
3021
3022 r->plane_trans[pipe][i] = temp;
3023 }
3024
3025 temp = 0;
3026 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3027 temp |= p_wm->trans_wm.cursor_res_b;
3028 if (p_wm->trans_wm.cursor_en)
3029 temp |= PLANE_WM_EN;
3030
3031 r->cursor_trans[pipe] = temp;
3032
2d41c0b5
PB		 3033 r->wm_linetime[pipe] = p_wm->linetime;
3034}
3035
16160e3d
DL		 3036static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3037 const struct skl_ddb_entry *entry)
3038{
3039 if (entry->end)
3040 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3041 else
3042 I915_WRITE(reg, 0);
3043}
3044
2d41c0b5
PB		 3045static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3046 const struct skl_wm_values *new)
3047{
3048 struct drm_device *dev = dev_priv->dev;
3049 struct intel_crtc *crtc;
3050
3051 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3052 int i, level, max_level = ilk_wm_max_level(dev);
3053 enum pipe pipe = crtc->pipe;
3054
5d374d96
DL		 3055 if (!new->dirty[pipe])
3056 continue;
8211bd5b 3057
5d374d96 3058 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3059
5d374d96
DL		 3060 for (level = 0; level <= max_level; level++) {
3061 for (i = 0; i < intel_num_planes(crtc); i++)
3062 I915_WRITE(PLANE_WM(pipe, i, level),
3063 new->plane[pipe][i][level]);
3064 I915_WRITE(CUR_WM(pipe, level),
3065 new->cursor[pipe][level]);
2d41c0b5 3066 }
5d374d96
DL		 3067 for (i = 0; i < intel_num_planes(crtc); i++)
3068 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3069 new->plane_trans[pipe][i]);
3070 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3071
3072 for (i = 0; i < intel_num_planes(crtc); i++)
3073 skl_ddb_entry_write(dev_priv,
3074 PLANE_BUF_CFG(pipe, i),
3075 &new->ddb.plane[pipe][i]);
3076
3077 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3078 &new->ddb.cursor[pipe]);
2d41c0b5 3079 }
2d41c0b5
PB		 3080}
3081
0e8fb7ba
DL		 3082/*
3083 * When setting up a new DDB allocation arrangement, we need to correctly
3084 * sequence the times at which the new allocations for the pipes are taken into
3085 * account or we'll have pipes fetching from space previously allocated to
3086 * another pipe.
3087 *
3088 * Roughly the sequence looks like:
3089 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3090 * overlapping with a previous light-up pipe (another way to put it is:
3091 * pipes with their new allocation strickly included into their old ones).
3092 * 2. re-allocate the other pipes that get their allocation reduced
3093 * 3. allocate the pipes having their allocation increased
3094 *
3095 * Steps 1. and 2. are here to take care of the following case:
3096 * - Initially DDB looks like this:
3097 * | B | C |
3098 * - enable pipe A.
3099 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3100 * allocation
3101 * | A | B | C |
3102 *
3103 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3104 */
3105
d21b795c
DL		 3106static void
3107skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3108{
0e8fb7ba
DL		 3109 int plane;
3110
d21b795c
DL		 3111 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3112
dd740780 3113 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3114 I915_WRITE(PLANE_SURF(pipe, plane),
3115 I915_READ(PLANE_SURF(pipe, plane)));
3116 }
3117 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3118}
3119
3120static bool
3121skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3122 const struct skl_ddb_allocation *new,
3123 enum pipe pipe)
3124{
3125 uint16_t old_size, new_size;
3126
3127 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3128 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3129
3130 return old_size != new_size &&
3131 new->pipe[pipe].start >= old->pipe[pipe].start &&
3132 new->pipe[pipe].end <= old->pipe[pipe].end;
3133}
3134
3135static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3136 struct skl_wm_values *new_values)
3137{
3138 struct drm_device *dev = dev_priv->dev;
3139 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3140 bool reallocated[I915_MAX_PIPES] = {false, false, false};
3141 struct intel_crtc *crtc;
3142 enum pipe pipe;
3143
3144 new_ddb = &new_values->ddb;
3145 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3146
3147 /*
3148 * First pass: flush the pipes with the new allocation contained into
3149 * the old space.
3150 *
3151 * We'll wait for the vblank on those pipes to ensure we can safely
3152 * re-allocate the freed space without this pipe fetching from it.
3153 */
3154 for_each_intel_crtc(dev, crtc) {
3155 if (!crtc->active)
3156 continue;
3157
3158 pipe = crtc->pipe;
3159
3160 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3161 continue;
3162
d21b795c 3163 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3164 intel_wait_for_vblank(dev, pipe);
3165
3166 reallocated[pipe] = true;
3167 }
3168
3169
3170 /*
3171 * Second pass: flush the pipes that are having their allocation
3172 * reduced, but overlapping with a previous allocation.
3173 *
3174 * Here as well we need to wait for the vblank to make sure the freed
3175 * space is not used anymore.
3176 */
3177 for_each_intel_crtc(dev, crtc) {
3178 if (!crtc->active)
3179 continue;
3180
3181 pipe = crtc->pipe;
3182
3183 if (reallocated[pipe])
3184 continue;
3185
3186 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3187 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3188 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3189 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3190 reallocated[pipe] = true;
0e8fb7ba 3191 }
0e8fb7ba
DL		 3192 }
3193
3194 /*
3195 * Third pass: flush the pipes that got more space allocated.
3196 *
3197 * We don't need to actively wait for the update here, next vblank
3198 * will just get more DDB space with the correct WM values.
3199 */
3200 for_each_intel_crtc(dev, crtc) {
3201 if (!crtc->active)
3202 continue;
3203
3204 pipe = crtc->pipe;
3205
3206 /*
3207 * At this point, only the pipes more space than before are
3208 * left to re-allocate.
3209 */
3210 if (reallocated[pipe])
3211 continue;
3212
d21b795c 3213 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3214 }
3215}
3216
2d41c0b5
PB		 3217static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3218 struct skl_pipe_wm_parameters *params,
3219 struct intel_wm_config *config,
3220 struct skl_ddb_allocation *ddb, /* out */
3221 struct skl_pipe_wm *pipe_wm /* out */)
3222{
3223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224
3225 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3226 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3227 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3228
3229 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3230 return false;
3231
3232 intel_crtc->wm.skl_active = *pipe_wm;
3233 return true;
3234}
3235
3236static void skl_update_other_pipe_wm(struct drm_device *dev,
3237 struct drm_crtc *crtc,
3238 struct intel_wm_config *config,
3239 struct skl_wm_values *r)
3240{
3241 struct intel_crtc *intel_crtc;
3242 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3243
3244 /*
3245 * If the WM update hasn't changed the allocation for this_crtc (the
3246 * crtc we are currently computing the new WM values for), other
3247 * enabled crtcs will keep the same allocation and we don't need to
3248 * recompute anything for them.
3249 */
3250 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3251 return;
3252
3253 /*
3254 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3255 * other active pipes need new DDB allocation and WM values.
3256 */
3257 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3258 base.head) {
3259 struct skl_pipe_wm_parameters params = {};
3260 struct skl_pipe_wm pipe_wm = {};
3261 bool wm_changed;
3262
3263 if (this_crtc->pipe == intel_crtc->pipe)
3264 continue;
3265
3266 if (!intel_crtc->active)
3267 continue;
3268
3269 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3270 &params, config,
3271 &r->ddb, &pipe_wm);
3272
3273 /*
3274 * If we end up re-computing the other pipe WM values, it's
3275 * because it was really needed, so we expect the WM values to
3276 * be different.
3277 */
3278 WARN_ON(!wm_changed);
3279
3280 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3281 r->dirty[intel_crtc->pipe] = true;
3282 }
3283}
3284
3285static void skl_update_wm(struct drm_crtc *crtc)
3286{
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct skl_pipe_wm_parameters params = {};
3291 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3292 struct skl_pipe_wm pipe_wm = {};
3293 struct intel_wm_config config = {};
3294
3295 memset(results, 0, sizeof(*results));
3296
3297 skl_compute_wm_global_parameters(dev, &config);
3298
3299 if (!skl_update_pipe_wm(crtc, &params, &config,
3300 &results->ddb, &pipe_wm))
3301 return;
3302
3303 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3304 results->dirty[intel_crtc->pipe] = true;
3305
3306 skl_update_other_pipe_wm(dev, crtc, &config, results);
3307 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3308 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3309
3310 /* store the new configuration */
3311 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3312}
3313
3314static void
3315skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3316 uint32_t sprite_width, uint32_t sprite_height,
3317 int pixel_size, bool enabled, bool scaled)
3318{
3319 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3320 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3321
3322 intel_plane->wm.enabled = enabled;
3323 intel_plane->wm.scaled = scaled;
3324 intel_plane->wm.horiz_pixels = sprite_width;
3325 intel_plane->wm.vert_pixels = sprite_height;
3326 intel_plane->wm.bytes_per_pixel = pixel_size;
0fda6568
TU		 3327 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3328 /*
3329 * Framebuffer can be NULL on plane disable, but it does not
3330 * matter for watermarks if we assume no tiling in that case.
3331 */
3332 if (fb)
3333 intel_plane->wm.tiling = fb->modifier[0];
2d41c0b5
PB		 3334
3335 skl_update_wm(crtc);
3336}
3337
820c1980 3338static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3339{
7c4a395f 3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3341 struct drm_device *dev = crtc->dev;
801bcfff 3342 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3343 struct ilk_wm_maximums max;
3344 struct ilk_pipe_wm_parameters params = {};
3345 struct ilk_wm_values results = {};
77c122bc 3346 enum intel_ddb_partitioning partitioning;
7c4a395f 3347 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3348 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3349 struct intel_wm_config config = {};
7c4a395f 3350
2a44b76b 3351 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3352
3353 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3354
3355 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3356 return;
861f3389 3357
7c4a395f 3358 intel_crtc->wm.active = pipe_wm;
861f3389 3359
2a44b76b
VS		 3360 ilk_compute_wm_config(dev, &config);
3361
34982fe1 3362 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3363 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3364
3365 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3366 if (INTEL_INFO(dev)->gen >= 7 &&
3367 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3368 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3369 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3370
820c1980 3371 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3372 } else {
198a1e9b 3373 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3374 }
3375
198a1e9b 3376 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3377 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3378
820c1980 3379 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3380
820c1980 3381 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3382}
3383
ed57cb8a
DL		 3384static void
3385ilk_update_sprite_wm(struct drm_plane *plane,
3386 struct drm_crtc *crtc,
3387 uint32_t sprite_width, uint32_t sprite_height,
3388 int pixel_size, bool enabled, bool scaled)
526682e9 3389{
8553c18e 3390 struct drm_device *dev = plane->dev;
adf3d35e 3391 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3392
adf3d35e
VS		 3393 intel_plane->wm.enabled = enabled;
3394 intel_plane->wm.scaled = scaled;
3395 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3396 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3397 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3398
8553c18e
VS		 3399 /*
3400 * IVB workaround: must disable low power watermarks for at least
3401 * one frame before enabling scaling. LP watermarks can be re-enabled
3402 * when scaling is disabled.
3403 *
3404 * WaCxSRDisabledForSpriteScaling:ivb
3405 */
3406 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3407 intel_wait_for_vblank(dev, intel_plane->pipe);
3408
820c1980 3409 ilk_update_wm(crtc);
526682e9
PZ		 3410}
3411
3078999f
PB		 3412static void skl_pipe_wm_active_state(uint32_t val,
3413 struct skl_pipe_wm *active,
3414 bool is_transwm,
3415 bool is_cursor,
3416 int i,
3417 int level)
3418{
3419 bool is_enabled = (val & PLANE_WM_EN) != 0;
3420
3421 if (!is_transwm) {
3422 if (!is_cursor) {
3423 active->wm[level].plane_en[i] = is_enabled;
3424 active->wm[level].plane_res_b[i] =
3425 val & PLANE_WM_BLOCKS_MASK;
3426 active->wm[level].plane_res_l[i] =
3427 (val >> PLANE_WM_LINES_SHIFT) &
3428 PLANE_WM_LINES_MASK;
3429 } else {
3430 active->wm[level].cursor_en = is_enabled;
3431 active->wm[level].cursor_res_b =
3432 val & PLANE_WM_BLOCKS_MASK;
3433 active->wm[level].cursor_res_l =
3434 (val >> PLANE_WM_LINES_SHIFT) &
3435 PLANE_WM_LINES_MASK;
3436 }
3437 } else {
3438 if (!is_cursor) {
3439 active->trans_wm.plane_en[i] = is_enabled;
3440 active->trans_wm.plane_res_b[i] =
3441 val & PLANE_WM_BLOCKS_MASK;
3442 active->trans_wm.plane_res_l[i] =
3443 (val >> PLANE_WM_LINES_SHIFT) &
3444 PLANE_WM_LINES_MASK;
3445 } else {
3446 active->trans_wm.cursor_en = is_enabled;
3447 active->trans_wm.cursor_res_b =
3448 val & PLANE_WM_BLOCKS_MASK;
3449 active->trans_wm.cursor_res_l =
3450 (val >> PLANE_WM_LINES_SHIFT) &
3451 PLANE_WM_LINES_MASK;
3452 }
3453 }
3454}
3455
3456static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3457{
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3462 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3463 enum pipe pipe = intel_crtc->pipe;
3464 int level, i, max_level;
3465 uint32_t temp;
3466
3467 max_level = ilk_wm_max_level(dev);
3468
3469 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3470
3471 for (level = 0; level <= max_level; level++) {
3472 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3473 hw->plane[pipe][i][level] =
3474 I915_READ(PLANE_WM(pipe, i, level));
3475 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3476 }
3477
3478 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3479 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3480 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3481
3ef00284 3482 if (!intel_crtc->active)
3078999f
PB		 3483 return;
3484
3485 hw->dirty[pipe] = true;
3486
3487 active->linetime = hw->wm_linetime[pipe];
3488
3489 for (level = 0; level <= max_level; level++) {
3490 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3491 temp = hw->plane[pipe][i][level];
3492 skl_pipe_wm_active_state(temp, active, false,
3493 false, i, level);
3494 }
3495 temp = hw->cursor[pipe][level];
3496 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3497 }
3498
3499 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3500 temp = hw->plane_trans[pipe][i];
3501 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3502 }
3503
3504 temp = hw->cursor_trans[pipe];
3505 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3506}
3507
3508void skl_wm_get_hw_state(struct drm_device *dev)
3509{
a269c583
DL		 3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3512 struct drm_crtc *crtc;
3513
a269c583 3514 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3515 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3516 skl_pipe_wm_get_hw_state(crtc);
3517}
3518
243e6a44
VS		 3519static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3520{
3521 struct drm_device *dev = crtc->dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3523 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3526 enum pipe pipe = intel_crtc->pipe;
3527 static const unsigned int wm0_pipe_reg[] = {
3528 [PIPE_A] = WM0_PIPEA_ILK,
3529 [PIPE_B] = WM0_PIPEB_ILK,
3530 [PIPE_C] = WM0_PIPEC_IVB,
3531 };
3532
3533 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3534 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3535 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3536
3ef00284 3537 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3538
3539 if (active->pipe_enabled) {
243e6a44
VS		 3540 u32 tmp = hw->wm_pipe[pipe];
3541
3542 /*
3543 * For active pipes LP0 watermark is marked as
3544 * enabled, and LP1+ watermaks as disabled since
3545 * we can't really reverse compute them in case
3546 * multiple pipes are active.
3547 */
3548 active->wm[0].enable = true;
3549 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3550 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3551 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3552 active->linetime = hw->wm_linetime[pipe];
3553 } else {
3554 int level, max_level = ilk_wm_max_level(dev);
3555
3556 /*
3557 * For inactive pipes, all watermark levels
3558 * should be marked as enabled but zeroed,
3559 * which is what we'd compute them to.
3560 */
3561 for (level = 0; level <= max_level; level++)
3562 active->wm[level].enable = true;
3563 }
3564}
3565
3566void ilk_wm_get_hw_state(struct drm_device *dev)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3569 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3570 struct drm_crtc *crtc;
3571
70e1e0ec 3572 for_each_crtc(dev, crtc)
243e6a44
VS		 3573 ilk_pipe_wm_get_hw_state(crtc);
3574
3575 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3576 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3577 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3578
3579 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3580 if (INTEL_INFO(dev)->gen >= 7) {
3581 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3582 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3583 }
243e6a44 3584
a42a5719 3585 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3586 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3587 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3588 else if (IS_IVYBRIDGE(dev))
3589 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3590 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3591
3592 hw->enable_fbc_wm =
3593 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3594}
3595
b445e3b0
ED		 3596/**
3597 * intel_update_watermarks - update FIFO watermark values based on current modes
3598 *
3599 * Calculate watermark values for the various WM regs based on current mode
3600 * and plane configuration.
3601 *
3602 * There are several cases to deal with here:
3603 * - normal (i.e. non-self-refresh)
3604 * - self-refresh (SR) mode
3605 * - lines are large relative to FIFO size (buffer can hold up to 2)
3606 * - lines are small relative to FIFO size (buffer can hold more than 2
3607 * lines), so need to account for TLB latency
3608 *
3609 * The normal calculation is:
3610 * watermark = dotclock * bytes per pixel * latency
3611 * where latency is platform & configuration dependent (we assume pessimal
3612 * values here).
3613 *
3614 * The SR calculation is:
3615 * watermark = (trunc(latency/line time)+1) * surface width *
3616 * bytes per pixel
3617 * where
3618 * line time = htotal / dotclock
3619 * surface width = hdisplay for normal plane and 64 for cursor
3620 * and latency is assumed to be high, as above.
3621 *
3622 * The final value programmed to the register should always be rounded up,
3623 * and include an extra 2 entries to account for clock crossings.
3624 *
3625 * We don't use the sprite, so we can ignore that. And on Crestline we have
3626 * to set the non-SR watermarks to 8.
3627 */
46ba614c 3628void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3629{
46ba614c 3630 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3631
3632 if (dev_priv->display.update_wm)
46ba614c 3633 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3634}
3635
adf3d35e
VS		 3636void intel_update_sprite_watermarks(struct drm_plane *plane,
3637 struct drm_crtc *crtc,
ed57cb8a
DL		 3638 uint32_t sprite_width,
3639 uint32_t sprite_height,
3640 int pixel_size,
39db4a4d 3641 bool enabled, bool scaled)
b445e3b0 3642{
adf3d35e 3643 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3644
3645 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3646 dev_priv->display.update_sprite_wm(plane, crtc,
3647 sprite_width, sprite_height,
39db4a4d 3648 pixel_size, enabled, scaled);
b445e3b0
ED		 3649}
3650
9270388e
DV		 3651/**
3652 * Lock protecting IPS related data structures
9270388e
DV		 3653 */
3654DEFINE_SPINLOCK(mchdev_lock);
3655
3656/* Global for IPS driver to get at the current i915 device. Protected by
3657 * mchdev_lock. */
3658static struct drm_i915_private *i915_mch_dev;
3659
2b4e57bd
ED		 3660bool ironlake_set_drps(struct drm_device *dev, u8 val)
3661{
3662 struct drm_i915_private *dev_priv = dev->dev_private;
3663 u16 rgvswctl;
3664
9270388e
DV		 3665 assert_spin_locked(&mchdev_lock);
3666
2b4e57bd
ED		 3667 rgvswctl = I915_READ16(MEMSWCTL);
3668 if (rgvswctl & MEMCTL_CMD_STS) {
3669 DRM_DEBUG("gpu busy, RCS change rejected\n");
3670 return false; /* still busy with another command */
3671 }
3672
3673 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3674 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3675 I915_WRITE16(MEMSWCTL, rgvswctl);
3676 POSTING_READ16(MEMSWCTL);
3677
3678 rgvswctl |= MEMCTL_CMD_STS;
3679 I915_WRITE16(MEMSWCTL, rgvswctl);
3680
3681 return true;
3682}
3683
8090c6b9 3684static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3685{
3686 struct drm_i915_private *dev_priv = dev->dev_private;
3687 u32 rgvmodectl = I915_READ(MEMMODECTL);
3688 u8 fmax, fmin, fstart, vstart;
3689
9270388e
DV		 3690 spin_lock_irq(&mchdev_lock);
3691
2b4e57bd
ED		 3692 /* Enable temp reporting */
3693 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3694 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3695
3696 /* 100ms RC evaluation intervals */
3697 I915_WRITE(RCUPEI, 100000);
3698 I915_WRITE(RCDNEI, 100000);
3699
3700 /* Set max/min thresholds to 90ms and 80ms respectively */
3701 I915_WRITE(RCBMAXAVG, 90000);
3702 I915_WRITE(RCBMINAVG, 80000);
3703
3704 I915_WRITE(MEMIHYST, 1);
3705
3706 /* Set up min, max, and cur for interrupt handling */
3707 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3708 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3709 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3710 MEMMODE_FSTART_SHIFT;
3711
3712 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3713 PXVFREQ_PX_SHIFT;
3714
20e4d407
DV		 3715 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3716 dev_priv->ips.fstart = fstart;
2b4e57bd 3717
20e4d407
DV		 3718 dev_priv->ips.max_delay = fstart;
3719 dev_priv->ips.min_delay = fmin;
3720 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3721
3722 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3723 fmax, fmin, fstart);
3724
3725 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3726
3727 /*
3728 * Interrupts will be enabled in ironlake_irq_postinstall
3729 */
3730
3731 I915_WRITE(VIDSTART, vstart);
3732 POSTING_READ(VIDSTART);
3733
3734 rgvmodectl |= MEMMODE_SWMODE_EN;
3735 I915_WRITE(MEMMODECTL, rgvmodectl);
3736
9270388e 3737 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3738 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3739 mdelay(1);
2b4e57bd
ED		 3740
3741 ironlake_set_drps(dev, fstart);
3742
20e4d407 3743 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3744 I915_READ(0x112e0);
20e4d407
DV		 3745 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3746 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3747 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3748
3749 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3750}
3751
8090c6b9 3752static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3753{
3754 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3755 u16 rgvswctl;
3756
3757 spin_lock_irq(&mchdev_lock);
3758
3759 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3760
3761 /* Ack interrupts, disable EFC interrupt */
3762 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3763 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3764 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3765 I915_WRITE(DEIIR, DE_PCU_EVENT);
3766 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3767
3768 /* Go back to the starting frequency */
20e4d407 3769 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3770 mdelay(1);
2b4e57bd
ED		 3771 rgvswctl |= MEMCTL_CMD_STS;
3772 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3773 mdelay(1);
2b4e57bd 3774
9270388e 3775 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3776}
3777
acbe9475
DV		 3778/* There's a funny hw issue where the hw returns all 0 when reading from
3779 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3780 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3781 * all limits and the gpu stuck at whatever frequency it is at atm).
3782 */
6917c7b9 3783static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3784{
7b9e0ae6 3785 u32 limits;
2b4e57bd 3786
20b46e59
DV		 3787 /* Only set the down limit when we've reached the lowest level to avoid
3788 * getting more interrupts, otherwise leave this clear. This prevents a
3789 * race in the hw when coming out of rc6: There's a tiny window where
3790 * the hw runs at the minimal clock before selecting the desired
3791 * frequency, if the down threshold expires in that window we will not
3792 * receive a down interrupt. */
b39fb297
BW		 3793 limits = dev_priv->rps.max_freq_softlimit << 24;
3794 if (val <= dev_priv->rps.min_freq_softlimit)
3795 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3796
3797 return limits;
3798}
3799
dd75fdc8
CW		 3800static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3801{
3802 int new_power;
3803
3804 new_power = dev_priv->rps.power;
3805 switch (dev_priv->rps.power) {
3806 case LOW_POWER:
b39fb297 3807 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3808 new_power = BETWEEN;
3809 break;
3810
3811 case BETWEEN:
b39fb297 3812 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3813 new_power = LOW_POWER;
b39fb297 3814 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3815 new_power = HIGH_POWER;
3816 break;
3817
3818 case HIGH_POWER:
b39fb297 3819 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3820 new_power = BETWEEN;
3821 break;
3822 }
3823 /* Max/min bins are special */
b39fb297 3824 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3825 new_power = LOW_POWER;
b39fb297 3826 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3827 new_power = HIGH_POWER;
3828 if (new_power == dev_priv->rps.power)
3829 return;
3830
3831 /* Note the units here are not exactly 1us, but 1280ns. */
3832 switch (new_power) {
3833 case LOW_POWER:
3834 /* Upclock if more than 95% busy over 16ms */
3835 I915_WRITE(GEN6_RP_UP_EI, 12500);
3836 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3837
3838 /* Downclock if less than 85% busy over 32ms */
3839 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3840 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3841
3842 I915_WRITE(GEN6_RP_CONTROL,
3843 GEN6_RP_MEDIA_TURBO |
3844 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3845 GEN6_RP_MEDIA_IS_GFX |
3846 GEN6_RP_ENABLE |
3847 GEN6_RP_UP_BUSY_AVG |
3848 GEN6_RP_DOWN_IDLE_AVG);
3849 break;
3850
3851 case BETWEEN:
3852 /* Upclock if more than 90% busy over 13ms */
3853 I915_WRITE(GEN6_RP_UP_EI, 10250);
3854 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3855
3856 /* Downclock if less than 75% busy over 32ms */
3857 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3858 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3859
3860 I915_WRITE(GEN6_RP_CONTROL,
3861 GEN6_RP_MEDIA_TURBO |
3862 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3863 GEN6_RP_MEDIA_IS_GFX |
3864 GEN6_RP_ENABLE |
3865 GEN6_RP_UP_BUSY_AVG |
3866 GEN6_RP_DOWN_IDLE_AVG);
3867 break;
3868
3869 case HIGH_POWER:
3870 /* Upclock if more than 85% busy over 10ms */
3871 I915_WRITE(GEN6_RP_UP_EI, 8000);
3872 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3873
3874 /* Downclock if less than 60% busy over 32ms */
3875 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3876 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3877
3878 I915_WRITE(GEN6_RP_CONTROL,
3879 GEN6_RP_MEDIA_TURBO |
3880 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3881 GEN6_RP_MEDIA_IS_GFX |
3882 GEN6_RP_ENABLE |
3883 GEN6_RP_UP_BUSY_AVG |
3884 GEN6_RP_DOWN_IDLE_AVG);
3885 break;
3886 }
3887
3888 dev_priv->rps.power = new_power;
3889 dev_priv->rps.last_adj = 0;
3890}
3891
2876ce73
CW		 3892static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3893{
3894 u32 mask = 0;
3895
3896 if (val > dev_priv->rps.min_freq_softlimit)
3897 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3898 if (val < dev_priv->rps.max_freq_softlimit)
3899 mask |= GEN6_PM_RP_UP_THRESHOLD;
3900
7b3c29f6
CW		 3901 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3902 mask &= dev_priv->pm_rps_events;
3903
59d02a1f 3904 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 3905}
3906
b8a5ff8d
JM		 3907/* gen6_set_rps is called to update the frequency request, but should also be
3908 * called when the range (min_delay and max_delay) is modified so that we can
3909 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 3910static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 3911{
3912 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3913
4fc688ce 3914 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3915 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3916 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3917
eb64cad1
CW		 3918 /* min/max delay may still have been modified so be sure to
3919 * write the limits value.
3920 */
3921 if (val != dev_priv->rps.cur_freq) {
3922 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3923
50e6a2a7 3924 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3925 I915_WRITE(GEN6_RPNSWREQ,
3926 HSW_FREQUENCY(val));
3927 else
3928 I915_WRITE(GEN6_RPNSWREQ,
3929 GEN6_FREQUENCY(val) |
3930 GEN6_OFFSET(0) |
3931 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3932 }
7b9e0ae6 3933
7b9e0ae6
CW		 3934 /* Make sure we continue to get interrupts
3935 * until we hit the minimum or maximum frequencies.
3936 */
eb64cad1 3937 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3938 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3939
d5570a72
BW		 3940 POSTING_READ(GEN6_RPNSWREQ);
3941
b39fb297 3942 dev_priv->rps.cur_freq = val;
be2cde9a 3943 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3944}
3945
ffe02b40
VS		 3946static void valleyview_set_rps(struct drm_device *dev, u8 val)
3947{
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949
3950 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3951 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3952 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3953
3954 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3955 "Odd GPU freq value\n"))
3956 val &= ~1;
3957
3958 if (val != dev_priv->rps.cur_freq)
3959 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3960
3961 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3962
3963 dev_priv->rps.cur_freq = val;
3964 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
3965}
3966
76c3552f
D		 3967/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3968 *
3969 * * If Gfx is Idle, then
3970 * 1. Mask Turbo interrupts
3971 * 2. Bring up Gfx clock
3972 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3973 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3974 * 5. Unmask Turbo interrupts
3975*/
3976static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3977{
5549d25f
D		 3978 struct drm_device *dev = dev_priv->dev;
3979
21a11fff
VS		 3980 /* CHV and latest VLV don't need to force the gfx clock */
3981 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
5549d25f
D		 3982 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3983 return;
3984 }
3985
76c3552f
D		 3986 /*
3987 * When we are idle. Drop to min voltage state.
3988 */
3989
b39fb297 3990 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3991 return;
3992
3993 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 3994 I915_WRITE(GEN6_PMINTRMSK,
3995 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 3996
650ad970 3997 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3998
b39fb297 3999 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 4000
4001 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 4002 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 4003
4004 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 4005 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 4006 DRM_ERROR("timed out waiting for Punit\n");
4007
650ad970 4008 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4009
2876ce73
CW		 4010 I915_WRITE(GEN6_PMINTRMSK,
4011 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 4012}
4013
b29c19b6
CW		 4014void gen6_rps_idle(struct drm_i915_private *dev_priv)
4015{
691bb717
DL		 4016 struct drm_device *dev = dev_priv->dev;
4017
b29c19b6 4018 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4019 if (dev_priv->rps.enabled) {
21a11fff 4020 if (IS_VALLEYVIEW(dev))
76c3552f 4021 vlv_set_rps_idle(dev_priv);
7526ed79 4022 else
b39fb297 4023 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 4024 dev_priv->rps.last_adj = 0;
4025 }
b29c19b6
CW		 4026 mutex_unlock(&dev_priv->rps.hw_lock);
4027}
4028
4029void gen6_rps_boost(struct drm_i915_private *dev_priv)
4030{
4031 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4032 if (dev_priv->rps.enabled) {
ffe02b40 4033 intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 4034 dev_priv->rps.last_adj = 0;
4035 }
b29c19b6
CW		 4036 mutex_unlock(&dev_priv->rps.hw_lock);
4037}
4038
ffe02b40 4039void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4040{
ffe02b40
VS		 4041 if (IS_VALLEYVIEW(dev))
4042 valleyview_set_rps(dev, val);
4043 else
4044 gen6_set_rps(dev, val);
0a073b84
JB		 4045}
4046
20e49366
ZW		 4047static void gen9_disable_rps(struct drm_device *dev)
4048{
4049 struct drm_i915_private *dev_priv = dev->dev_private;
4050
4051 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4052 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4053}
4054
44fc7d5c 4055static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4056{
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4058
4059 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4060 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4061}
4062
38807746
D		 4063static void cherryview_disable_rps(struct drm_device *dev)
4064{
4065 struct drm_i915_private *dev_priv = dev->dev_private;
4066
4067 I915_WRITE(GEN6_RC_CONTROL, 0);
4068}
4069
44fc7d5c
DV		 4070static void valleyview_disable_rps(struct drm_device *dev)
4071{
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073
98a2e5f9
D		 4074 /* we're doing forcewake before Disabling RC6,
4075 * This what the BIOS expects when going into suspend */
59bad947 4076 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4077
44fc7d5c 4078 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4079
59bad947 4080 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4081}
4082
dc39fff7
BW		 4083static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4084{
91ca689a
ID		 4085 if (IS_VALLEYVIEW(dev)) {
4086 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4087 mode = GEN6_RC_CTL_RC6_ENABLE;
4088 else
4089 mode = 0;
4090 }
58abf1da
RV		 4091 if (HAS_RC6p(dev))
4092 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4093 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4094 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4095 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4096
4097 else
4098 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4099 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4100}
4101
e6069ca8 4102static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4103{
eb4926e4
DL		 4104 /* No RC6 before Ironlake */
4105 if (INTEL_INFO(dev)->gen < 5)
4106 return 0;
4107
e6069ca8
ID		 4108 /* RC6 is only on Ironlake mobile not on desktop */
4109 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4110 return 0;
4111
456470eb 4112 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4113 if (enable_rc6 >= 0) {
4114 int mask;
4115
58abf1da 4116 if (HAS_RC6p(dev))
e6069ca8
ID		 4117 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4118 INTEL_RC6pp_ENABLE;
4119 else
4120 mask = INTEL_RC6_ENABLE;
4121
4122 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4123 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4124 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4125
4126 return enable_rc6 & mask;
4127 }
2b4e57bd 4128
6567d748
CW		 4129 /* Disable RC6 on Ironlake */
4130 if (INTEL_INFO(dev)->gen == 5)
4131 return 0;
2b4e57bd 4132
8bade1ad 4133 if (IS_IVYBRIDGE(dev))
cca84a1f 4134 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4135
4136 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4137}
4138
e6069ca8
ID		 4139int intel_enable_rc6(const struct drm_device *dev)
4140{
4141 return i915.enable_rc6;
4142}
4143
93ee2920 4144static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4145{
93ee2920
TR		 4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 uint32_t rp_state_cap;
4148 u32 ddcc_status = 0;
4149 int ret;
4150
4151 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 4152 /* All of these values are in units of 50MHz */
4153 dev_priv->rps.cur_freq = 0;
93ee2920 4154 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4155 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4156 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4157 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3280e8b0
BW		 4158 /* hw_max = RP0 until we check for overclocking */
4159 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4160
93ee2920
TR		 4161 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4162 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4163 ret = sandybridge_pcode_read(dev_priv,
4164 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4165 &ddcc_status);
4166 if (0 == ret)
4167 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4168 clamp_t(u8,
4169 ((ddcc_status >> 8) & 0xff),
4170 dev_priv->rps.min_freq,
4171 dev_priv->rps.max_freq);
93ee2920
TR		 4172 }
4173
3280e8b0
BW		 4174 /* Preserve min/max settings in case of re-init */
4175 if (dev_priv->rps.max_freq_softlimit == 0)
4176 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4177
93ee2920
TR		 4178 if (dev_priv->rps.min_freq_softlimit == 0) {
4179 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4180 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR		 4181 /* max(RPe, 450 MHz) */
4182 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR		 4183 else
4184 dev_priv->rps.min_freq_softlimit =
4185 dev_priv->rps.min_freq;
4186 }
3280e8b0
BW		 4187}
4188
b6fef0ef 4189/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4190static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4191{
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193
4194 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4195
ba1c554c
DL		 4196 gen6_init_rps_frequencies(dev);
4197
b6fef0ef
JB		 4198 I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
4199 I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
4200
4201 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4202 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
4203 I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
4204 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
4205 I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
4206 I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
4207 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4208 I915_WRITE(GEN6_PMINTRMSK, 0x6);
4209 I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
4210 GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
4211 GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
4212 GEN6_RP_DOWN_IDLE_AVG);
4213
4214 gen6_enable_rps_interrupts(dev);
4215
4216 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4217}
4218
4219static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4220{
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 struct intel_engine_cs *ring;
4223 uint32_t rc6_mask = 0;
4224 int unused;
4225
4226 /* 1a: Software RC state - RC0 */
4227 I915_WRITE(GEN6_RC_STATE, 0);
4228
4229 /* 1b: Get forcewake during program sequence. Although the driver
4230 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4231 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4232
4233 /* 2a: Disable RC states. */
4234 I915_WRITE(GEN6_RC_CONTROL, 0);
4235
4236 /* 2b: Program RC6 thresholds.*/
4237 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4238 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4239 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4240 for_each_ring(ring, dev_priv, unused)
4241 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4242 I915_WRITE(GEN6_RC_SLEEP, 0);
4243 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4244
38c23527
ZW		 4245 /* 2c: Program Coarse Power Gating Policies. */
4246 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4247 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4248
20e49366
ZW		 4249 /* 3a: Enable RC6 */
4250 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4251 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4252 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4253 "on" : "off");
4254 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4255 GEN6_RC_CTL_EI_MODE(1) |
4256 rc6_mask);
4257
38c23527
ZW		 4258 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4259 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4260
59bad947 4261 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4262
4263}
4264
6edee7f3
BW		 4265static void gen8_enable_rps(struct drm_device *dev)
4266{
4267 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4268 struct intel_engine_cs *ring;
93ee2920 4269 uint32_t rc6_mask = 0;
6edee7f3
BW		 4270 int unused;
4271
4272 /* 1a: Software RC state - RC0 */
4273 I915_WRITE(GEN6_RC_STATE, 0);
4274
4275 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4276 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4277 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4278
4279 /* 2a: Disable RC states. */
4280 I915_WRITE(GEN6_RC_CONTROL, 0);
4281
93ee2920
TR		 4282 /* Initialize rps frequencies */
4283 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4284
4285 /* 2b: Program RC6 thresholds.*/
4286 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4287 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4288 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4289 for_each_ring(ring, dev_priv, unused)
4290 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4291 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4292 if (IS_BROADWELL(dev))
4293 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4294 else
4295 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4296
4297 /* 3: Enable RC6 */
4298 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4299 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4300 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4301 if (IS_BROADWELL(dev))
4302 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4303 GEN7_RC_CTL_TO_MODE |
4304 rc6_mask);
4305 else
4306 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4307 GEN6_RC_CTL_EI_MODE(1) |
4308 rc6_mask);
6edee7f3
BW		 4309
4310 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4311 I915_WRITE(GEN6_RPNSWREQ,
4312 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4313 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4314 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4315 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4316 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4317
4318 /* Docs recommend 900MHz, and 300 MHz respectively */
4319 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4320 dev_priv->rps.max_freq_softlimit << 24 |
4321 dev_priv->rps.min_freq_softlimit << 16);
4322
4323 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4324 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4325 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4326 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4327
4328 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4329
4330 /* 5: Enable RPS */
7526ed79
DV		 4331 I915_WRITE(GEN6_RP_CONTROL,
4332 GEN6_RP_MEDIA_TURBO |
4333 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4334 GEN6_RP_MEDIA_IS_GFX |
4335 GEN6_RP_ENABLE |
4336 GEN6_RP_UP_BUSY_AVG |
4337 GEN6_RP_DOWN_IDLE_AVG);
4338
4339 /* 6: Ring frequency + overclocking (our driver does this later */
4340
c7f3153a
TR		 4341 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4342 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
7526ed79 4343
59bad947 4344 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4345}
4346
79f5b2c7 4347static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4348{
79f5b2c7 4349 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4350 struct intel_engine_cs *ring;
d060c169 4351 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4352 u32 gtfifodbg;
2b4e57bd 4353 int rc6_mode;
42c0526c 4354 int i, ret;
2b4e57bd 4355
4fc688ce 4356 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4357
2b4e57bd
ED		 4358 /* Here begins a magic sequence of register writes to enable
4359 * auto-downclocking.
4360 *
4361 * Perhaps there might be some value in exposing these to
4362 * userspace...
4363 */
4364 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4365
4366 /* Clear the DBG now so we don't confuse earlier errors */
4367 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4368 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4369 I915_WRITE(GTFIFODBG, gtfifodbg);
4370 }
4371
59bad947 4372 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4373
93ee2920
TR		 4374 /* Initialize rps frequencies */
4375 gen6_init_rps_frequencies(dev);
dd0a1aa1 4376
2b4e57bd
ED		 4377 /* disable the counters and set deterministic thresholds */
4378 I915_WRITE(GEN6_RC_CONTROL, 0);
4379
4380 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4381 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4382 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4383 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4384 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4385
b4519513
CW		 4386 for_each_ring(ring, dev_priv, i)
4387 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4388
4389 I915_WRITE(GEN6_RC_SLEEP, 0);
4390 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4391 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4392 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4393 else
4394 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4395 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4396 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4397
5a7dc92a 4398 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4399 rc6_mode = intel_enable_rc6(dev_priv->dev);
4400 if (rc6_mode & INTEL_RC6_ENABLE)
4401 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4402
5a7dc92a
ED		 4403 /* We don't use those on Haswell */
4404 if (!IS_HASWELL(dev)) {
4405 if (rc6_mode & INTEL_RC6p_ENABLE)
4406 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4407
5a7dc92a
ED		 4408 if (rc6_mode & INTEL_RC6pp_ENABLE)
4409 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4410 }
2b4e57bd 4411
dc39fff7 4412 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4413
4414 I915_WRITE(GEN6_RC_CONTROL,
4415 rc6_mask |
4416 GEN6_RC_CTL_EI_MODE(1) |
4417 GEN6_RC_CTL_HW_ENABLE);
4418
dd75fdc8
CW		 4419 /* Power down if completely idle for over 50ms */
4420 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4421 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4422
42c0526c 4423 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4424 if (ret)
42c0526c 4425 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4426
4427 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4428 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4429 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4430 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4431 (pcu_mbox & 0xff) * 50);
b39fb297 4432 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4433 }
4434
dd75fdc8 4435 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 4436 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 4437
31643d54
BW		 4438 rc6vids = 0;
4439 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4440 if (IS_GEN6(dev) && ret) {
4441 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4442 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4443 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4444 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4445 rc6vids &= 0xffff00;
4446 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4447 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4448 if (ret)
4449 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4450 }
4451
59bad947 4452 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4453}
4454
c2bc2fc5 4455static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4456{
79f5b2c7 4457 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4458 int min_freq = 15;
3ebecd07
CW		 4459 unsigned int gpu_freq;
4460 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4461 int scaling_factor = 180;
eda79642 4462 struct cpufreq_policy *policy;
2b4e57bd 4463
4fc688ce 4464 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4465
eda79642
BW		 4466 policy = cpufreq_cpu_get(0);
4467 if (policy) {
4468 max_ia_freq = policy->cpuinfo.max_freq;
4469 cpufreq_cpu_put(policy);
4470 } else {
4471 /*
4472 * Default to measured freq if none found, PCU will ensure we
4473 * don't go over
4474 */
2b4e57bd 4475 max_ia_freq = tsc_khz;
eda79642 4476 }
2b4e57bd
ED		 4477
4478 /* Convert from kHz to MHz */
4479 max_ia_freq /= 1000;
4480
153b4b95 4481 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4482 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4483 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4484
2b4e57bd
ED		 4485 /*
4486 * For each potential GPU frequency, load a ring frequency we'd like
4487 * to use for memory access. We do this by specifying the IA frequency
4488 * the PCU should use as a reference to determine the ring frequency.
4489 */
6985b352 4490 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4491 gpu_freq--) {
6985b352 4492 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4493 unsigned int ia_freq = 0, ring_freq = 0;
4494
46c764d4
BW		 4495 if (INTEL_INFO(dev)->gen >= 8) {
4496 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4497 ring_freq = max(min_ring_freq, gpu_freq);
4498 } else if (IS_HASWELL(dev)) {
f6aca45c 4499 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4500 ring_freq = max(min_ring_freq, ring_freq);
4501 /* leave ia_freq as the default, chosen by cpufreq */
4502 } else {
4503 /* On older processors, there is no separate ring
4504 * clock domain, so in order to boost the bandwidth
4505 * of the ring, we need to upclock the CPU (ia_freq).
4506 *
4507 * For GPU frequencies less than 750MHz,
4508 * just use the lowest ring freq.
4509 */
4510 if (gpu_freq < min_freq)
4511 ia_freq = 800;
4512 else
4513 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4514 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4515 }
2b4e57bd 4516
42c0526c
BW		 4517 sandybridge_pcode_write(dev_priv,
4518 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4519 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4520 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4521 gpu_freq);
2b4e57bd 4522 }
2b4e57bd
ED		 4523}
4524
c2bc2fc5
ID		 4525void gen6_update_ring_freq(struct drm_device *dev)
4526{
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528
4529 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4530 return;
4531
4532 mutex_lock(&dev_priv->rps.hw_lock);
4533 __gen6_update_ring_freq(dev);
4534 mutex_unlock(&dev_priv->rps.hw_lock);
4535}
4536
03af2045 4537static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4538{
095acd5f 4539 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4540 u32 val, rp0;
4541
095acd5f
D		 4542 if (dev->pdev->revision >= 0x20) {
4543 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4544
095acd5f
D		 4545 switch (INTEL_INFO(dev)->eu_total) {
4546 case 8:
4547 /* (2 * 4) config */
4548 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4549 break;
4550 case 12:
4551 /* (2 * 6) config */
4552 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4553 break;
4554 case 16:
4555 /* (2 * 8) config */
4556 default:
4557 /* Setting (2 * 8) Min RP0 for any other combination */
4558 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4559 break;
4560 }
4561 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4562 } else {
4563 /* For pre-production hardware */
4564 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4565 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4566 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4567 }
2b6b3a09
D		 4568 return rp0;
4569}
4570
4571static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4572{
4573 u32 val, rpe;
4574
4575 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4576 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4577
4578 return rpe;
4579}
4580
7707df4a
D		 4581static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4582{
095acd5f 4583 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4584 u32 val, rp1;
4585
095acd5f
D		 4586 if (dev->pdev->revision >= 0x20) {
4587 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4588 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4589 } else {
4590 /* For pre-production hardware */
4591 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4592 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4593 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4594 }
7707df4a
D		 4595 return rp1;
4596}
4597
03af2045 4598static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4599{
095acd5f 4600 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4601 u32 val, rpn;
4602
095acd5f
D		 4603 if (dev->pdev->revision >= 0x20) {
4604 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4605 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4606 FB_GFX_FREQ_FUSE_MASK);
4607 } else { /* For pre-production hardware */
4608 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4609 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4610 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4611 }
4612
2b6b3a09
D		 4613 return rpn;
4614}
4615
f8f2b001
D		 4616static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4617{
4618 u32 val, rp1;
4619
4620 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4621
4622 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4623
4624 return rp1;
4625}
4626
03af2045 4627static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4628{
4629 u32 val, rp0;
4630
64936258 4631 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4632
4633 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4634 /* Clamp to max */
4635 rp0 = min_t(u32, rp0, 0xea);
4636
4637 return rp0;
4638}
4639
4640static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4641{
4642 u32 val, rpe;
4643
64936258 4644 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4645 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4646 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4647 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4648
4649 return rpe;
4650}
4651
03af2045 4652static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4653{
64936258 4654 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4655}
4656
ae48434c
ID		 4657/* Check that the pctx buffer wasn't move under us. */
4658static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4659{
4660 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4661
4662 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4663 dev_priv->vlv_pctx->stolen->start);
4664}
4665
38807746
D		 4666
4667/* Check that the pcbr address is not empty. */
4668static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4669{
4670 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4671
4672 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4673}
4674
4675static void cherryview_setup_pctx(struct drm_device *dev)
4676{
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 unsigned long pctx_paddr, paddr;
4679 struct i915_gtt *gtt = &dev_priv->gtt;
4680 u32 pcbr;
4681 int pctx_size = 32*1024;
4682
4683 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4684
4685 pcbr = I915_READ(VLV_PCBR);
4686 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4687 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4688 paddr = (dev_priv->mm.stolen_base +
4689 (gtt->stolen_size - pctx_size));
4690
4691 pctx_paddr = (paddr & (~4095));
4692 I915_WRITE(VLV_PCBR, pctx_paddr);
4693 }
ce611ef8
VS		 4694
4695 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4696}
4697
c9cddffc
JB		 4698static void valleyview_setup_pctx(struct drm_device *dev)
4699{
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 struct drm_i915_gem_object *pctx;
4702 unsigned long pctx_paddr;
4703 u32 pcbr;
4704 int pctx_size = 24*1024;
4705
17b0c1f7
ID		 4706 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4707
c9cddffc
JB		 4708 pcbr = I915_READ(VLV_PCBR);
4709 if (pcbr) {
4710 /* BIOS set it up already, grab the pre-alloc'd space */
4711 int pcbr_offset;
4712
4713 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4714 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4715 pcbr_offset,
190d6cd5 4716 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4717 pctx_size);
4718 goto out;
4719 }
4720
ce611ef8
VS		 4721 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4722
c9cddffc
JB		 4723 /*
4724 * From the Gunit register HAS:
4725 * The Gfx driver is expected to program this register and ensure
4726 * proper allocation within Gfx stolen memory. For example, this
4727 * register should be programmed such than the PCBR range does not
4728 * overlap with other ranges, such as the frame buffer, protected
4729 * memory, or any other relevant ranges.
4730 */
4731 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4732 if (!pctx) {
4733 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4734 return;
4735 }
4736
4737 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4738 I915_WRITE(VLV_PCBR, pctx_paddr);
4739
4740out:
ce611ef8 4741 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4742 dev_priv->vlv_pctx = pctx;
4743}
4744
ae48434c
ID		 4745static void valleyview_cleanup_pctx(struct drm_device *dev)
4746{
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748
4749 if (WARN_ON(!dev_priv->vlv_pctx))
4750 return;
4751
4752 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4753 dev_priv->vlv_pctx = NULL;
4754}
4755
4e80519e
ID		 4756static void valleyview_init_gt_powersave(struct drm_device *dev)
4757{
4758 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4759 u32 val;
4e80519e
ID		 4760
4761 valleyview_setup_pctx(dev);
4762
4763 mutex_lock(&dev_priv->rps.hw_lock);
4764
2bb25c17
VS		 4765 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4766 switch ((val >> 6) & 3) {
4767 case 0:
4768 case 1:
4769 dev_priv->mem_freq = 800;
4770 break;
4771 case 2:
4772 dev_priv->mem_freq = 1066;
4773 break;
4774 case 3:
4775 dev_priv->mem_freq = 1333;
4776 break;
4777 }
80b83b62 4778 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4779
4e80519e
ID		 4780 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4781 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4782 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4783 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4784 dev_priv->rps.max_freq);
4785
4786 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4787 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4788 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4789 dev_priv->rps.efficient_freq);
4790
f8f2b001
D		 4791 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4792 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4793 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4794 dev_priv->rps.rp1_freq);
4795
4e80519e
ID		 4796 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4797 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4798 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4799 dev_priv->rps.min_freq);
4800
4801 /* Preserve min/max settings in case of re-init */
4802 if (dev_priv->rps.max_freq_softlimit == 0)
4803 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4804
4805 if (dev_priv->rps.min_freq_softlimit == 0)
4806 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4807
4808 mutex_unlock(&dev_priv->rps.hw_lock);
4809}
4810
38807746
D		 4811static void cherryview_init_gt_powersave(struct drm_device *dev)
4812{
2b6b3a09 4813 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4814 u32 val;
2b6b3a09 4815
38807746 4816 cherryview_setup_pctx(dev);
2b6b3a09
D		 4817
4818 mutex_lock(&dev_priv->rps.hw_lock);
4819
c6e8f39d
VS		 4820 mutex_lock(&dev_priv->dpio_lock);
4821 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4822 mutex_unlock(&dev_priv->dpio_lock);
4823
2bb25c17
VS		 4824 switch ((val >> 2) & 0x7) {
4825 case 0:
4826 case 1:
4827 dev_priv->rps.cz_freq = 200;
4828 dev_priv->mem_freq = 1600;
4829 break;
4830 case 2:
4831 dev_priv->rps.cz_freq = 267;
4832 dev_priv->mem_freq = 1600;
4833 break;
4834 case 3:
4835 dev_priv->rps.cz_freq = 333;
4836 dev_priv->mem_freq = 2000;
4837 break;
4838 case 4:
4839 dev_priv->rps.cz_freq = 320;
4840 dev_priv->mem_freq = 1600;
4841 break;
4842 case 5:
4843 dev_priv->rps.cz_freq = 400;
4844 dev_priv->mem_freq = 1600;
4845 break;
4846 }
80b83b62 4847 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4848
2b6b3a09
D		 4849 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4850 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4851 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4852 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 4853 dev_priv->rps.max_freq);
4854
4855 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4856 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4857 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4858 dev_priv->rps.efficient_freq);
4859
7707df4a
D		 4860 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4861 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 4862 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 4863 dev_priv->rps.rp1_freq);
4864
2b6b3a09
D		 4865 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4866 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4867 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 4868 dev_priv->rps.min_freq);
4869
1c14762d
VS		 4870 WARN_ONCE((dev_priv->rps.max_freq |
4871 dev_priv->rps.efficient_freq |
4872 dev_priv->rps.rp1_freq |
4873 dev_priv->rps.min_freq) & 1,
4874 "Odd GPU freq values\n");
4875
2b6b3a09
D		 4876 /* Preserve min/max settings in case of re-init */
4877 if (dev_priv->rps.max_freq_softlimit == 0)
4878 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4879
4880 if (dev_priv->rps.min_freq_softlimit == 0)
4881 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4882
4883 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4884}
4885
4e80519e
ID		 4886static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4887{
4888 valleyview_cleanup_pctx(dev);
4889}
4890
38807746
D		 4891static void cherryview_enable_rps(struct drm_device *dev)
4892{
4893 struct drm_i915_private *dev_priv = dev->dev_private;
4894 struct intel_engine_cs *ring;
2b6b3a09 4895 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4896 int i;
4897
4898 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4899
4900 gtfifodbg = I915_READ(GTFIFODBG);
4901 if (gtfifodbg) {
4902 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4903 gtfifodbg);
4904 I915_WRITE(GTFIFODBG, gtfifodbg);
4905 }
4906
4907 cherryview_check_pctx(dev_priv);
4908
4909 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4910 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4911 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 4912
160614a2
VS		 4913 /* Disable RC states. */
4914 I915_WRITE(GEN6_RC_CONTROL, 0);
4915
38807746
D		 4916 /* 2a: Program RC6 thresholds.*/
4917 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4918 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4919 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4920
4921 for_each_ring(ring, dev_priv, i)
4922 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4923 I915_WRITE(GEN6_RC_SLEEP, 0);
4924
af5a75a3
VS		 4925 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4926 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D		 4927
4928 /* allows RC6 residency counter to work */
4929 I915_WRITE(VLV_COUNTER_CONTROL,
4930 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4931 VLV_MEDIA_RC6_COUNT_EN |
4932 VLV_RENDER_RC6_COUNT_EN));
4933
4934 /* For now we assume BIOS is allocating and populating the PCBR */
4935 pcbr = I915_READ(VLV_PCBR);
4936
38807746
D		 4937 /* 3: Enable RC6 */
4938 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4939 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 4940 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 4941
4942 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4943
2b6b3a09 4944 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 4945 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 4946 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4947 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4948 I915_WRITE(GEN6_RP_UP_EI, 66000);
4949 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4950
4951 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4952
4953 /* 5: Enable RPS */
4954 I915_WRITE(GEN6_RP_CONTROL,
4955 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 4956 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 4957 GEN6_RP_ENABLE |
4958 GEN6_RP_UP_BUSY_AVG |
4959 GEN6_RP_DOWN_IDLE_AVG);
4960
4961 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4962
8d40c3ae
VS		 4963 /* RPS code assumes GPLL is used */
4964 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4965
c8e9627d 4966 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 4967 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4968
4969 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4970 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 4971 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 4972 dev_priv->rps.cur_freq);
4973
4974 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 4975 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4976 dev_priv->rps.efficient_freq);
4977
4978 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4979
59bad947 4980 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 4981}
4982
0a073b84
JB		 4983static void valleyview_enable_rps(struct drm_device *dev)
4984{
4985 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4986 struct intel_engine_cs *ring;
2a5913a8 4987 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4988 int i;
4989
4990 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4991
ae48434c
ID		 4992 valleyview_check_pctx(dev_priv);
4993
0a073b84 4994 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4995 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4996 gtfifodbg);
0a073b84
JB		 4997 I915_WRITE(GTFIFODBG, gtfifodbg);
4998 }
4999
c8d9a590 5000 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5001 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5002
160614a2
VS		 5003 /* Disable RC states. */
5004 I915_WRITE(GEN6_RC_CONTROL, 0);
5005
cad725fe 5006 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5007 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5008 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5009 I915_WRITE(GEN6_RP_UP_EI, 66000);
5010 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5011
5012 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5013
5014 I915_WRITE(GEN6_RP_CONTROL,
5015 GEN6_RP_MEDIA_TURBO |
5016 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5017 GEN6_RP_MEDIA_IS_GFX |
5018 GEN6_RP_ENABLE |
5019 GEN6_RP_UP_BUSY_AVG |
5020 GEN6_RP_DOWN_IDLE_CONT);
5021
5022 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5023 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5024 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5025
5026 for_each_ring(ring, dev_priv, i)
5027 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5028
2f0aa304 5029 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5030
5031 /* allows RC6 residency counter to work */
49798eb2 5032 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5033 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5034 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5035 VLV_MEDIA_RC6_COUNT_EN |
5036 VLV_RENDER_RC6_COUNT_EN));
31685c25 5037
a2b23fe0 5038 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5039 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5040
5041 intel_print_rc6_info(dev, rc6_mode);
5042
a2b23fe0 5043 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5044
64936258 5045 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5046
8d40c3ae
VS		 5047 /* RPS code assumes GPLL is used */
5048 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5049
c8e9627d 5050 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5051 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5052
b39fb297 5053 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5054 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5055 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5056 dev_priv->rps.cur_freq);
0a073b84 5057
73008b98 5058 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5059 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5060 dev_priv->rps.efficient_freq);
0a073b84 5061
b39fb297 5062 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5063
59bad947 5064 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5065}
5066
dde18883
ED		 5067static unsigned long intel_pxfreq(u32 vidfreq)
5068{
5069 unsigned long freq;
5070 int div = (vidfreq & 0x3f0000) >> 16;
5071 int post = (vidfreq & 0x3000) >> 12;
5072 int pre = (vidfreq & 0x7);
5073
5074 if (!pre)
5075 return 0;
5076
5077 freq = ((div * 133333) / ((1<<post) * pre));
5078
5079 return freq;
5080}
5081
eb48eb00
DV		 5082static const struct cparams {
5083 u16 i;
5084 u16 t;
5085 u16 m;
5086 u16 c;
5087} cparams[] = {
5088 { 1, 1333, 301, 28664 },
5089 { 1, 1066, 294, 24460 },
5090 { 1, 800, 294, 25192 },
5091 { 0, 1333, 276, 27605 },
5092 { 0, 1066, 276, 27605 },
5093 { 0, 800, 231, 23784 },
5094};
5095
f531dcb2 5096static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5097{
5098 u64 total_count, diff, ret;
5099 u32 count1, count2, count3, m = 0, c = 0;
5100 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5101 int i;
5102
02d71956
DV		 5103 assert_spin_locked(&mchdev_lock);
5104
20e4d407 5105 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5106
5107 /* Prevent division-by-zero if we are asking too fast.
5108 * Also, we don't get interesting results if we are polling
5109 * faster than once in 10ms, so just return the saved value
5110 * in such cases.
5111 */
5112 if (diff1 <= 10)
20e4d407 5113 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5114
5115 count1 = I915_READ(DMIEC);
5116 count2 = I915_READ(DDREC);
5117 count3 = I915_READ(CSIEC);
5118
5119 total_count = count1 + count2 + count3;
5120
5121 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5122 if (total_count < dev_priv->ips.last_count1) {
5123 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5124 diff += total_count;
5125 } else {
20e4d407 5126 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5127 }
5128
5129 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5130 if (cparams[i].i == dev_priv->ips.c_m &&
5131 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5132 m = cparams[i].m;
5133 c = cparams[i].c;
5134 break;
5135 }
5136 }
5137
5138 diff = div_u64(diff, diff1);
5139 ret = ((m * diff) + c);
5140 ret = div_u64(ret, 10);
5141
20e4d407
DV		 5142 dev_priv->ips.last_count1 = total_count;
5143 dev_priv->ips.last_time1 = now;
eb48eb00 5144
20e4d407 5145 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5146
5147 return ret;
5148}
5149
f531dcb2
CW		 5150unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5151{
3d13ef2e 5152 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5153 unsigned long val;
5154
3d13ef2e 5155 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5156 return 0;
5157
5158 spin_lock_irq(&mchdev_lock);
5159
5160 val = __i915_chipset_val(dev_priv);
5161
5162 spin_unlock_irq(&mchdev_lock);
5163
5164 return val;
5165}
5166
eb48eb00
DV		 5167unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5168{
5169 unsigned long m, x, b;
5170 u32 tsfs;
5171
5172 tsfs = I915_READ(TSFS);
5173
5174 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5175 x = I915_READ8(TR1);
5176
5177 b = tsfs & TSFS_INTR_MASK;
5178
5179 return ((m * x) / 127) - b;
5180}
5181
d972d6ee
MK		 5182static int _pxvid_to_vd(u8 pxvid)
5183{
5184 if (pxvid == 0)
5185 return 0;
5186
5187 if (pxvid >= 8 && pxvid < 31)
5188 pxvid = 31;
5189
5190 return (pxvid + 2) * 125;
5191}
5192
5193static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5194{
3d13ef2e 5195 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5196 const int vd = _pxvid_to_vd(pxvid);
5197 const int vm = vd - 1125;
5198
3d13ef2e 5199 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5200 return vm > 0 ? vm : 0;
5201
5202 return vd;
eb48eb00
DV		 5203}
5204
02d71956 5205static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5206{
5ed0bdf2 5207 u64 now, diff, diffms;
eb48eb00
DV		 5208 u32 count;
5209
02d71956 5210 assert_spin_locked(&mchdev_lock);
eb48eb00 5211
5ed0bdf2
TG		 5212 now = ktime_get_raw_ns();
5213 diffms = now - dev_priv->ips.last_time2;
5214 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5215
5216 /* Don't divide by 0 */
eb48eb00
DV		 5217 if (!diffms)
5218 return;
5219
5220 count = I915_READ(GFXEC);
5221
20e4d407
DV		 5222 if (count < dev_priv->ips.last_count2) {
5223 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5224 diff += count;
5225 } else {
20e4d407 5226 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5227 }
5228
20e4d407
DV		 5229 dev_priv->ips.last_count2 = count;
5230 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5231
5232 /* More magic constants... */
5233 diff = diff * 1181;
5234 diff = div_u64(diff, diffms * 10);
20e4d407 5235 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5236}
5237
02d71956
DV		 5238void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5239{
3d13ef2e
DL		 5240 struct drm_device *dev = dev_priv->dev;
5241
5242 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5243 return;
5244
9270388e 5245 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5246
5247 __i915_update_gfx_val(dev_priv);
5248
9270388e 5249 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5250}
5251
f531dcb2 5252static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5253{
5254 unsigned long t, corr, state1, corr2, state2;
5255 u32 pxvid, ext_v;
5256
02d71956
DV		 5257 assert_spin_locked(&mchdev_lock);
5258
b39fb297 5259 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5260 pxvid = (pxvid >> 24) & 0x7f;
5261 ext_v = pvid_to_extvid(dev_priv, pxvid);
5262
5263 state1 = ext_v;
5264
5265 t = i915_mch_val(dev_priv);
5266
5267 /* Revel in the empirically derived constants */
5268
5269 /* Correction factor in 1/100000 units */
5270 if (t > 80)
5271 corr = ((t * 2349) + 135940);
5272 else if (t >= 50)
5273 corr = ((t * 964) + 29317);
5274 else /* < 50 */
5275 corr = ((t * 301) + 1004);
5276
5277 corr = corr * ((150142 * state1) / 10000 - 78642);
5278 corr /= 100000;
20e4d407 5279 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5280
5281 state2 = (corr2 * state1) / 10000;
5282 state2 /= 100; /* convert to mW */
5283
02d71956 5284 __i915_update_gfx_val(dev_priv);
eb48eb00 5285
20e4d407 5286 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5287}
5288
f531dcb2
CW		 5289unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5290{
3d13ef2e 5291 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5292 unsigned long val;
5293
3d13ef2e 5294 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5295 return 0;
5296
5297 spin_lock_irq(&mchdev_lock);
5298
5299 val = __i915_gfx_val(dev_priv);
5300
5301 spin_unlock_irq(&mchdev_lock);
5302
5303 return val;
5304}
5305
eb48eb00
DV		 5306/**
5307 * i915_read_mch_val - return value for IPS use
5308 *
5309 * Calculate and return a value for the IPS driver to use when deciding whether
5310 * we have thermal and power headroom to increase CPU or GPU power budget.
5311 */
5312unsigned long i915_read_mch_val(void)
5313{
5314 struct drm_i915_private *dev_priv;
5315 unsigned long chipset_val, graphics_val, ret = 0;
5316
9270388e 5317 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5318 if (!i915_mch_dev)
5319 goto out_unlock;
5320 dev_priv = i915_mch_dev;
5321
f531dcb2
CW		 5322 chipset_val = __i915_chipset_val(dev_priv);
5323 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5324
5325 ret = chipset_val + graphics_val;
5326
5327out_unlock:
9270388e 5328 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5329
5330 return ret;
5331}
5332EXPORT_SYMBOL_GPL(i915_read_mch_val);
5333
5334/**
5335 * i915_gpu_raise - raise GPU frequency limit
5336 *
5337 * Raise the limit; IPS indicates we have thermal headroom.
5338 */
5339bool i915_gpu_raise(void)
5340{
5341 struct drm_i915_private *dev_priv;
5342 bool ret = true;
5343
9270388e 5344 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5345 if (!i915_mch_dev) {
5346 ret = false;
5347 goto out_unlock;
5348 }
5349 dev_priv = i915_mch_dev;
5350
20e4d407
DV		 5351 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5352 dev_priv->ips.max_delay--;
eb48eb00
DV		 5353
5354out_unlock:
9270388e 5355 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5356
5357 return ret;
5358}
5359EXPORT_SYMBOL_GPL(i915_gpu_raise);
5360
5361/**
5362 * i915_gpu_lower - lower GPU frequency limit
5363 *
5364 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5365 * frequency maximum.
5366 */
5367bool i915_gpu_lower(void)
5368{
5369 struct drm_i915_private *dev_priv;
5370 bool ret = true;
5371
9270388e 5372 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5373 if (!i915_mch_dev) {
5374 ret = false;
5375 goto out_unlock;
5376 }
5377 dev_priv = i915_mch_dev;
5378
20e4d407
DV		 5379 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5380 dev_priv->ips.max_delay++;
eb48eb00
DV		 5381
5382out_unlock:
9270388e 5383 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5384
5385 return ret;
5386}
5387EXPORT_SYMBOL_GPL(i915_gpu_lower);
5388
5389/**
5390 * i915_gpu_busy - indicate GPU business to IPS
5391 *
5392 * Tell the IPS driver whether or not the GPU is busy.
5393 */
5394bool i915_gpu_busy(void)
5395{
5396 struct drm_i915_private *dev_priv;
a4872ba6 5397 struct intel_engine_cs *ring;
eb48eb00 5398 bool ret = false;
f047e395 5399 int i;
eb48eb00 5400
9270388e 5401 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5402 if (!i915_mch_dev)
5403 goto out_unlock;
5404 dev_priv = i915_mch_dev;
5405
f047e395
CW		 5406 for_each_ring(ring, dev_priv, i)
5407 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5408
5409out_unlock:
9270388e 5410 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5411
5412 return ret;
5413}
5414EXPORT_SYMBOL_GPL(i915_gpu_busy);
5415
5416/**
5417 * i915_gpu_turbo_disable - disable graphics turbo
5418 *
5419 * Disable graphics turbo by resetting the max frequency and setting the
5420 * current frequency to the default.
5421 */
5422bool i915_gpu_turbo_disable(void)
5423{
5424 struct drm_i915_private *dev_priv;
5425 bool ret = true;
5426
9270388e 5427 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5428 if (!i915_mch_dev) {
5429 ret = false;
5430 goto out_unlock;
5431 }
5432 dev_priv = i915_mch_dev;
5433
20e4d407 5434 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5435
20e4d407 5436 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5437 ret = false;
5438
5439out_unlock:
9270388e 5440 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5441
5442 return ret;
5443}
5444EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5445
5446/**
5447 * Tells the intel_ips driver that the i915 driver is now loaded, if
5448 * IPS got loaded first.
5449 *
5450 * This awkward dance is so that neither module has to depend on the
5451 * other in order for IPS to do the appropriate communication of
5452 * GPU turbo limits to i915.
5453 */
5454static void
5455ips_ping_for_i915_load(void)
5456{
5457 void (*link)(void);
5458
5459 link = symbol_get(ips_link_to_i915_driver);
5460 if (link) {
5461 link();
5462 symbol_put(ips_link_to_i915_driver);
5463 }
5464}
5465
5466void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5467{
02d71956
DV		 5468 /* We only register the i915 ips part with intel-ips once everything is
5469 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5470 spin_lock_irq(&mchdev_lock);
eb48eb00 5471 i915_mch_dev = dev_priv;
9270388e 5472 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5473
5474 ips_ping_for_i915_load();
5475}
5476
5477void intel_gpu_ips_teardown(void)
5478{
9270388e 5479 spin_lock_irq(&mchdev_lock);
eb48eb00 5480 i915_mch_dev = NULL;
9270388e 5481 spin_unlock_irq(&mchdev_lock);
eb48eb00 5482}
76c3552f 5483
8090c6b9 5484static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5485{
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 u32 lcfuse;
5488 u8 pxw[16];
5489 int i;
5490
5491 /* Disable to program */
5492 I915_WRITE(ECR, 0);
5493 POSTING_READ(ECR);
5494
5495 /* Program energy weights for various events */
5496 I915_WRITE(SDEW, 0x15040d00);
5497 I915_WRITE(CSIEW0, 0x007f0000);
5498 I915_WRITE(CSIEW1, 0x1e220004);
5499 I915_WRITE(CSIEW2, 0x04000004);
5500
5501 for (i = 0; i < 5; i++)
5502 I915_WRITE(PEW + (i * 4), 0);
5503 for (i = 0; i < 3; i++)
5504 I915_WRITE(DEW + (i * 4), 0);
5505
5506 /* Program P-state weights to account for frequency power adjustment */
5507 for (i = 0; i < 16; i++) {
5508 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5509 unsigned long freq = intel_pxfreq(pxvidfreq);
5510 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5511 PXVFREQ_PX_SHIFT;
5512 unsigned long val;
5513
5514 val = vid * vid;
5515 val *= (freq / 1000);
5516 val *= 255;
5517 val /= (127*127*900);
5518 if (val > 0xff)
5519 DRM_ERROR("bad pxval: %ld\n", val);
5520 pxw[i] = val;
5521 }
5522 /* Render standby states get 0 weight */
5523 pxw[14] = 0;
5524 pxw[15] = 0;
5525
5526 for (i = 0; i < 4; i++) {
5527 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5528 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5529 I915_WRITE(PXW + (i * 4), val);
5530 }
5531
5532 /* Adjust magic regs to magic values (more experimental results) */
5533 I915_WRITE(OGW0, 0);
5534 I915_WRITE(OGW1, 0);
5535 I915_WRITE(EG0, 0x00007f00);
5536 I915_WRITE(EG1, 0x0000000e);
5537 I915_WRITE(EG2, 0x000e0000);
5538 I915_WRITE(EG3, 0x68000300);
5539 I915_WRITE(EG4, 0x42000000);
5540 I915_WRITE(EG5, 0x00140031);
5541 I915_WRITE(EG6, 0);
5542 I915_WRITE(EG7, 0);
5543
5544 for (i = 0; i < 8; i++)
5545 I915_WRITE(PXWL + (i * 4), 0);
5546
5547 /* Enable PMON + select events */
5548 I915_WRITE(ECR, 0x80000019);
5549
5550 lcfuse = I915_READ(LCFUSE02);
5551
20e4d407 5552 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5553}
5554
ae48434c
ID		 5555void intel_init_gt_powersave(struct drm_device *dev)
5556{
e6069ca8
ID		 5557 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5558
38807746
D		 5559 if (IS_CHERRYVIEW(dev))
5560 cherryview_init_gt_powersave(dev);
5561 else if (IS_VALLEYVIEW(dev))
4e80519e 5562 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5563}
5564
5565void intel_cleanup_gt_powersave(struct drm_device *dev)
5566{
38807746
D		 5567 if (IS_CHERRYVIEW(dev))
5568 return;
5569 else if (IS_VALLEYVIEW(dev))
4e80519e 5570 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5571}
5572
dbea3cea
ID		 5573static void gen6_suspend_rps(struct drm_device *dev)
5574{
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576
5577 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5578
5579 /*
5580 * TODO: disable RPS interrupts on GEN9+ too once RPS support
5581 * is added for it.
5582 */
5583 if (INTEL_INFO(dev)->gen < 9)
5584 gen6_disable_rps_interrupts(dev);
5585}
5586
156c7ca0
JB		 5587/**
5588 * intel_suspend_gt_powersave - suspend PM work and helper threads
5589 * @dev: drm device
5590 *
5591 * We don't want to disable RC6 or other features here, we just want
5592 * to make sure any work we've queued has finished and won't bother
5593 * us while we're suspended.
5594 */
5595void intel_suspend_gt_powersave(struct drm_device *dev)
5596{
5597 struct drm_i915_private *dev_priv = dev->dev_private;
5598
d4d70aa5
ID		 5599 if (INTEL_INFO(dev)->gen < 6)
5600 return;
5601
dbea3cea 5602 gen6_suspend_rps(dev);
b47adc17
D		 5603
5604 /* Force GPU to min freq during suspend */
5605 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5606}
5607
8090c6b9
DV		 5608void intel_disable_gt_powersave(struct drm_device *dev)
5609{
1a01ab3b
JB		 5610 struct drm_i915_private *dev_priv = dev->dev_private;
5611
930ebb46 5612 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5613 ironlake_disable_drps(dev);
38807746 5614 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5615 intel_suspend_gt_powersave(dev);
e494837a 5616
4fc688ce 5617 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5618 if (INTEL_INFO(dev)->gen >= 9)
5619 gen9_disable_rps(dev);
5620 else if (IS_CHERRYVIEW(dev))
38807746
D		 5621 cherryview_disable_rps(dev);
5622 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5623 valleyview_disable_rps(dev);
5624 else
5625 gen6_disable_rps(dev);
e534770a 5626
c0951f0c 5627 dev_priv->rps.enabled = false;
4fc688ce 5628 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5629 }
8090c6b9
DV		 5630}
5631
1a01ab3b
JB		 5632static void intel_gen6_powersave_work(struct work_struct *work)
5633{
5634 struct drm_i915_private *dev_priv =
5635 container_of(work, struct drm_i915_private,
5636 rps.delayed_resume_work.work);
5637 struct drm_device *dev = dev_priv->dev;
5638
4fc688ce 5639 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5640
3cc134e3
ID		 5641 /*
5642 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
5643 * added for it.
5644 */
5645 if (INTEL_INFO(dev)->gen < 9)
5646 gen6_reset_rps_interrupts(dev);
5647
38807746
D		 5648 if (IS_CHERRYVIEW(dev)) {
5649 cherryview_enable_rps(dev);
5650 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5651 valleyview_enable_rps(dev);
20e49366 5652 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5653 gen9_enable_rc6(dev);
20e49366 5654 gen9_enable_rps(dev);
b6fef0ef 5655 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5656 } else if (IS_BROADWELL(dev)) {
5657 gen8_enable_rps(dev);
c2bc2fc5 5658 __gen6_update_ring_freq(dev);
0a073b84
JB		 5659 } else {
5660 gen6_enable_rps(dev);
c2bc2fc5 5661 __gen6_update_ring_freq(dev);
0a073b84 5662 }
c0951f0c 5663 dev_priv->rps.enabled = true;
3cc134e3
ID		 5664
5665 if (INTEL_INFO(dev)->gen < 9)
5666 gen6_enable_rps_interrupts(dev);
5667
4fc688ce 5668 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5669
5670 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5671}
5672
8090c6b9
DV		 5673void intel_enable_gt_powersave(struct drm_device *dev)
5674{
1a01ab3b
JB		 5675 struct drm_i915_private *dev_priv = dev->dev_private;
5676
f61018b1
YZ		 5677 /* Powersaving is controlled by the host when inside a VM */
5678 if (intel_vgpu_active(dev))
5679 return;
5680
8090c6b9 5681 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5682 mutex_lock(&dev->struct_mutex);
8090c6b9 5683 ironlake_enable_drps(dev);
8090c6b9 5684 intel_init_emon(dev);
dc1d0136 5685 mutex_unlock(&dev->struct_mutex);
38807746 5686 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5687 /*
5688 * PCU communication is slow and this doesn't need to be
5689 * done at any specific time, so do this out of our fast path
5690 * to make resume and init faster.
c6df39b5
ID		 5691 *
5692 * We depend on the HW RC6 power context save/restore
5693 * mechanism when entering D3 through runtime PM suspend. So
5694 * disable RPM until RPS/RC6 is properly setup. We can only
5695 * get here via the driver load/system resume/runtime resume
5696 * paths, so the _noresume version is enough (and in case of
5697 * runtime resume it's necessary).
1a01ab3b 5698 */
c6df39b5
ID		 5699 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5700 round_jiffies_up_relative(HZ)))
5701 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5702 }
5703}
5704
c6df39b5
ID		 5705void intel_reset_gt_powersave(struct drm_device *dev)
5706{
5707 struct drm_i915_private *dev_priv = dev->dev_private;
5708
dbea3cea
ID		 5709 if (INTEL_INFO(dev)->gen < 6)
5710 return;
5711
5712 gen6_suspend_rps(dev);
c6df39b5 5713 dev_priv->rps.enabled = false;
c6df39b5
ID		 5714}
5715
3107bd48
DV		 5716static void ibx_init_clock_gating(struct drm_device *dev)
5717{
5718 struct drm_i915_private *dev_priv = dev->dev_private;
5719
5720 /*
5721 * On Ibex Peak and Cougar Point, we need to disable clock
5722 * gating for the panel power sequencer or it will fail to
5723 * start up when no ports are active.
5724 */
5725 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5726}
5727
0e088b8f
VS		 5728static void g4x_disable_trickle_feed(struct drm_device *dev)
5729{
5730 struct drm_i915_private *dev_priv = dev->dev_private;
5731 int pipe;
5732
055e393f 5733 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5734 I915_WRITE(DSPCNTR(pipe),
5735 I915_READ(DSPCNTR(pipe)) |
5736 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5737 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5738 }
5739}
5740
017636cc
VS		 5741static void ilk_init_lp_watermarks(struct drm_device *dev)
5742{
5743 struct drm_i915_private *dev_priv = dev->dev_private;
5744
5745 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5746 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5747 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5748
5749 /*
5750 * Don't touch WM1S_LP_EN here.
5751 * Doing so could cause underruns.
5752 */
5753}
5754
1fa61106 5755static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5756{
5757 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5758 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5759
f1e8fa56
DL		 5760 /*
5761 * Required for FBC
5762 * WaFbcDisableDpfcClockGating:ilk
5763 */
4d47e4f5
DL		 5764 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5765 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5766 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5767
5768 I915_WRITE(PCH_3DCGDIS0,
5769 MARIUNIT_CLOCK_GATE_DISABLE |
5770 SVSMUNIT_CLOCK_GATE_DISABLE);
5771 I915_WRITE(PCH_3DCGDIS1,
5772 VFMUNIT_CLOCK_GATE_DISABLE);
5773
6f1d69b0
ED		 5774 /*
5775 * According to the spec the following bits should be set in
5776 * order to enable memory self-refresh
5777 * The bit 22/21 of 0x42004
5778 * The bit 5 of 0x42020
5779 * The bit 15 of 0x45000
5780 */
5781 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5782 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5783 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5784 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5785 I915_WRITE(DISP_ARB_CTL,
5786 (I915_READ(DISP_ARB_CTL) |
5787 DISP_FBC_WM_DIS));
017636cc
VS		 5788
5789 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5790
5791 /*
5792 * Based on the document from hardware guys the following bits
5793 * should be set unconditionally in order to enable FBC.
5794 * The bit 22 of 0x42000
5795 * The bit 22 of 0x42004
5796 * The bit 7,8,9 of 0x42020.
5797 */
5798 if (IS_IRONLAKE_M(dev)) {
4bb35334 5799 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5800 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5801 I915_READ(ILK_DISPLAY_CHICKEN1) |
5802 ILK_FBCQ_DIS);
5803 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5804 I915_READ(ILK_DISPLAY_CHICKEN2) |
5805 ILK_DPARB_GATE);
6f1d69b0
ED		 5806 }
5807
4d47e4f5
DL		 5808 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5809
6f1d69b0
ED		 5810 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5811 I915_READ(ILK_DISPLAY_CHICKEN2) |
5812 ILK_ELPIN_409_SELECT);
5813 I915_WRITE(_3D_CHICKEN2,
5814 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5815 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5816
ecdb4eb7 5817 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5818 I915_WRITE(CACHE_MODE_0,
5819 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5820
4e04632e
AG		 5821 /* WaDisable_RenderCache_OperationalFlush:ilk */
5822 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5823
0e088b8f 5824 g4x_disable_trickle_feed(dev);
bdad2b2f 5825
3107bd48
DV		 5826 ibx_init_clock_gating(dev);
5827}
5828
5829static void cpt_init_clock_gating(struct drm_device *dev)
5830{
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 int pipe;
3f704fa2 5833 uint32_t val;
3107bd48
DV		 5834
5835 /*
5836 * On Ibex Peak and Cougar Point, we need to disable clock
5837 * gating for the panel power sequencer or it will fail to
5838 * start up when no ports are active.
5839 */
cd664078
JB		 5840 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5841 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5842 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5843 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5844 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5845 /* The below fixes the weird display corruption, a few pixels shifted
5846 * downward, on (only) LVDS of some HP laptops with IVY.
5847 */
055e393f 5848 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5849 val = I915_READ(TRANS_CHICKEN2(pipe));
5850 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5851 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5852 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5853 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5854 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5855 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5856 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5857 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5858 }
3107bd48 5859 /* WADP0ClockGatingDisable */
055e393f 5860 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5861 I915_WRITE(TRANS_CHICKEN1(pipe),
5862 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5863 }
6f1d69b0
ED		 5864}
5865
1d7aaa0c
DV		 5866static void gen6_check_mch_setup(struct drm_device *dev)
5867{
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 uint32_t tmp;
5870
5871 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5872 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5873 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5874 tmp);
1d7aaa0c
DV		 5875}
5876
1fa61106 5877static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5878{
5879 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5880 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5881
231e54f6 5882 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5883
5884 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5885 I915_READ(ILK_DISPLAY_CHICKEN2) |
5886 ILK_ELPIN_409_SELECT);
5887
ecdb4eb7 5888 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5889 I915_WRITE(_3D_CHICKEN,
5890 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5891
4e04632e
AG		 5892 /* WaDisable_RenderCache_OperationalFlush:snb */
5893 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5894
8d85d272
VS		 5895 /*
5896 * BSpec recoomends 8x4 when MSAA is used,
5897 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5898 *
5899 * Note that PS/WM thread counts depend on the WIZ hashing
5900 * disable bit, which we don't touch here, but it's good
5901 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5902 */
5903 I915_WRITE(GEN6_GT_MODE,
98533251 5904 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5905
017636cc 5906 ilk_init_lp_watermarks(dev);
6f1d69b0 5907
6f1d69b0 5908 I915_WRITE(CACHE_MODE_0,
50743298 5909 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5910
5911 I915_WRITE(GEN6_UCGCTL1,
5912 I915_READ(GEN6_UCGCTL1) |
5913 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5914 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5915
5916 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5917 * gating disable must be set. Failure to set it results in
5918 * flickering pixels due to Z write ordering failures after
5919 * some amount of runtime in the Mesa "fire" demo, and Unigine
5920 * Sanctuary and Tropics, and apparently anything else with
5921 * alpha test or pixel discard.
5922 *
5923 * According to the spec, bit 11 (RCCUNIT) must also be set,
5924 * but we didn't debug actual testcases to find it out.
0f846f81 5925 *
ef59318c
VS		 5926 * WaDisableRCCUnitClockGating:snb
5927 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5928 */
5929 I915_WRITE(GEN6_UCGCTL2,
5930 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5931 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5932
5eb146dd 5933 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5934 I915_WRITE(_3D_CHICKEN3,
5935 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5936
e927ecde
VS		 5937 /*
5938 * Bspec says:
5939 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5940 * 3DSTATE_SF number of SF output attributes is more than 16."
5941 */
5942 I915_WRITE(_3D_CHICKEN3,
5943 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5944
6f1d69b0
ED		 5945 /*
5946 * According to the spec the following bits should be
5947 * set in order to enable memory self-refresh and fbc:
5948 * The bit21 and bit22 of 0x42000
5949 * The bit21 and bit22 of 0x42004
5950 * The bit5 and bit7 of 0x42020
5951 * The bit14 of 0x70180
5952 * The bit14 of 0x71180
4bb35334
DL		 5953 *
5954 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5955 */
5956 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5957 I915_READ(ILK_DISPLAY_CHICKEN1) |
5958 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5959 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5960 I915_READ(ILK_DISPLAY_CHICKEN2) |
5961 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5962 I915_WRITE(ILK_DSPCLK_GATE_D,
5963 I915_READ(ILK_DSPCLK_GATE_D) |
5964 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5965 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5966
0e088b8f 5967 g4x_disable_trickle_feed(dev);
f8f2ac9a 5968
3107bd48 5969 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5970
5971 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5972}
5973
5974static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5975{
5976 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5977
3aad9059 5978 /*
46680e0a 5979 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5980 *
5981 * This actually overrides the dispatch
5982 * mode for all thread types.
5983 */
6f1d69b0
ED		 5984 reg &= ~GEN7_FF_SCHED_MASK;
5985 reg |= GEN7_FF_TS_SCHED_HW;
5986 reg |= GEN7_FF_VS_SCHED_HW;
5987 reg |= GEN7_FF_DS_SCHED_HW;
5988
5989 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5990}
5991
17a303ec
PZ		 5992static void lpt_init_clock_gating(struct drm_device *dev)
5993{
5994 struct drm_i915_private *dev_priv = dev->dev_private;
5995
5996 /*
5997 * TODO: this bit should only be enabled when really needed, then
5998 * disabled when not needed anymore in order to save power.
5999 */
6000 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6001 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6002 I915_READ(SOUTH_DSPCLK_GATE_D) |
6003 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6004
6005 /* WADPOClockGatingDisable:hsw */
6006 I915_WRITE(_TRANSA_CHICKEN1,
6007 I915_READ(_TRANSA_CHICKEN1) |
6008 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6009}
6010
7d708ee4
ID		 6011static void lpt_suspend_hw(struct drm_device *dev)
6012{
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014
6015 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6016 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6017
6018 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6019 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6020 }
6021}
6022
47c2bd97 6023static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6024{
6025 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6026 enum pipe pipe;
1020a5c2
BW		 6027
6028 I915_WRITE(WM3_LP_ILK, 0);
6029 I915_WRITE(WM2_LP_ILK, 0);
6030 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6031
ab57fff1 6032 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6033 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6034
ab57fff1 6035 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6036 I915_WRITE(CHICKEN_PAR1_1,
6037 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6038
ab57fff1 6039 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6040 for_each_pipe(dev_priv, pipe) {
07d27e20 6041 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6042 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6043 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6044 }
63801f21 6045
ab57fff1
BW		 6046 /* WaVSRefCountFullforceMissDisable:bdw */
6047 /* WaDSRefCountFullforceMissDisable:bdw */
6048 I915_WRITE(GEN7_FF_THREAD_MODE,
6049 I915_READ(GEN7_FF_THREAD_MODE) &
6050 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6051
295e8bb7
VS		 6052 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6053 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6054
6055 /* WaDisableSDEUnitClockGating:bdw */
6056 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6057 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6058
89d6b2b8 6059 lpt_init_clock_gating(dev);
1020a5c2
BW		 6060}
6061
cad2a2d7
ED		 6062static void haswell_init_clock_gating(struct drm_device *dev)
6063{
6064 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6065
017636cc 6066 ilk_init_lp_watermarks(dev);
cad2a2d7 6067
f3fc4884
FJ		 6068 /* L3 caching of data atomics doesn't work -- disable it. */
6069 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6070 I915_WRITE(HSW_ROW_CHICKEN3,
6071 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6072
ecdb4eb7 6073 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6074 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6075 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6076 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6077
e36ea7ff
VS		 6078 /* WaVSRefCountFullforceMissDisable:hsw */
6079 I915_WRITE(GEN7_FF_THREAD_MODE,
6080 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6081
4e04632e
AG		 6082 /* WaDisable_RenderCache_OperationalFlush:hsw */
6083 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6084
fe27c606
CW		 6085 /* enable HiZ Raw Stall Optimization */
6086 I915_WRITE(CACHE_MODE_0_GEN7,
6087 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6088
ecdb4eb7 6089 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6090 I915_WRITE(CACHE_MODE_1,
6091 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6092
a12c4967
VS		 6093 /*
6094 * BSpec recommends 8x4 when MSAA is used,
6095 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6096 *
6097 * Note that PS/WM thread counts depend on the WIZ hashing
6098 * disable bit, which we don't touch here, but it's good
6099 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6100 */
6101 I915_WRITE(GEN7_GT_MODE,
98533251 6102 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6103
94411593
KG		 6104 /* WaSampleCChickenBitEnable:hsw */
6105 I915_WRITE(HALF_SLICE_CHICKEN3,
6106 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6107
ecdb4eb7 6108 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6109 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6110
90a88643
PZ		 6111 /* WaRsPkgCStateDisplayPMReq:hsw */
6112 I915_WRITE(CHICKEN_PAR1_1,
6113 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6114
17a303ec 6115 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6116}
6117
1fa61106 6118static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6119{
6120 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6121 uint32_t snpcr;
6f1d69b0 6122
017636cc 6123 ilk_init_lp_watermarks(dev);
6f1d69b0 6124
231e54f6 6125 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6126
ecdb4eb7 6127 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6128 I915_WRITE(_3D_CHICKEN3,
6129 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6130
ecdb4eb7 6131 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6132 I915_WRITE(IVB_CHICKEN3,
6133 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6134 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6135
ecdb4eb7 6136 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6137 if (IS_IVB_GT1(dev))
6138 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6139 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6140
4e04632e
AG		 6141 /* WaDisable_RenderCache_OperationalFlush:ivb */
6142 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6143
ecdb4eb7 6144 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6145 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6146 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6147
ecdb4eb7 6148 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6149 I915_WRITE(GEN7_L3CNTLREG1,
6150 GEN7_WA_FOR_GEN7_L3_CONTROL);
6151 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6152 GEN7_WA_L3_CHICKEN_MODE);
6153 if (IS_IVB_GT1(dev))
6154 I915_WRITE(GEN7_ROW_CHICKEN2,
6155 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6156 else {
6157 /* must write both registers */
6158 I915_WRITE(GEN7_ROW_CHICKEN2,
6159 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6160 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6161 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6162 }
6f1d69b0 6163
ecdb4eb7 6164 /* WaForceL3Serialization:ivb */
61939d97
JB		 6165 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6166 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6167
1b80a19a 6168 /*
0f846f81 6169 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6170 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6171 */
6172 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6173 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6174
ecdb4eb7 6175 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6176 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6177 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6178 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6179
0e088b8f 6180 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6181
6182 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6183
22721343
CW		 6184 if (0) { /* causes HiZ corruption on ivb:gt1 */
6185 /* enable HiZ Raw Stall Optimization */
6186 I915_WRITE(CACHE_MODE_0_GEN7,
6187 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6188 }
116f2b6d 6189
ecdb4eb7 6190 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6191 I915_WRITE(CACHE_MODE_1,
6192 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6193
a607c1a4
VS		 6194 /*
6195 * BSpec recommends 8x4 when MSAA is used,
6196 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6197 *
6198 * Note that PS/WM thread counts depend on the WIZ hashing
6199 * disable bit, which we don't touch here, but it's good
6200 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6201 */
6202 I915_WRITE(GEN7_GT_MODE,
98533251 6203 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6204
20848223
BW		 6205 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6206 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6207 snpcr |= GEN6_MBC_SNPCR_MED;
6208 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6209
ab5c608b
BW		 6210 if (!HAS_PCH_NOP(dev))
6211 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6212
6213 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6214}
6215
c6beb13e
VS		 6216static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6217{
6218 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6219
6220 /*
6221 * Disable trickle feed and enable pnd deadline calculation
6222 */
6223 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6224 I915_WRITE(CBR1_VLV, 0);
6225}
6226
1fa61106 6227static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6228{
6229 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6230
c6beb13e 6231 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6232
ecdb4eb7 6233 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6234 I915_WRITE(_3D_CHICKEN3,
6235 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6236
ecdb4eb7 6237 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6238 I915_WRITE(IVB_CHICKEN3,
6239 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6240 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6241
fad7d36e 6242 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6243 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6244 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6245 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6246 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6247
4e04632e
AG		 6248 /* WaDisable_RenderCache_OperationalFlush:vlv */
6249 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6250
ecdb4eb7 6251 /* WaForceL3Serialization:vlv */
61939d97
JB		 6252 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6253 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6254
ecdb4eb7 6255 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6256 I915_WRITE(GEN7_ROW_CHICKEN2,
6257 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6258
ecdb4eb7 6259 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6260 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6261 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6262 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6263
46680e0a
VS		 6264 gen7_setup_fixed_func_scheduler(dev_priv);
6265
3c0edaeb 6266 /*
0f846f81 6267 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6268 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6269 */
6270 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6271 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6272
c98f5062
AG		 6273 /* WaDisableL3Bank2xClockGate:vlv
6274 * Disabling L3 clock gating- MMIO 940c[25] = 1
6275 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6276 I915_WRITE(GEN7_UCGCTL4,
6277 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6278
afd58e79
VS		 6279 /*
6280 * BSpec says this must be set, even though
6281 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6282 */
6b26c86d
DV		 6283 I915_WRITE(CACHE_MODE_1,
6284 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6285
da2518f9
VS		 6286 /*
6287 * BSpec recommends 8x4 when MSAA is used,
6288 * however in practice 16x4 seems fastest.
6289 *
6290 * Note that PS/WM thread counts depend on the WIZ hashing
6291 * disable bit, which we don't touch here, but it's good
6292 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6293 */
6294 I915_WRITE(GEN7_GT_MODE,
6295 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6296
031994ee
VS		 6297 /*
6298 * WaIncreaseL3CreditsForVLVB0:vlv
6299 * This is the hardware default actually.
6300 */
6301 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6302
2d809570 6303 /*
ecdb4eb7 6304 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6305 * Disable clock gating on th GCFG unit to prevent a delay
6306 * in the reporting of vblank events.
6307 */
7a0d1eed 6308 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6309}
6310
a4565da8
VS		 6311static void cherryview_init_clock_gating(struct drm_device *dev)
6312{
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6314
c6beb13e 6315 vlv_init_display_clock_gating(dev_priv);
dd811e70 6316
232ce337
VS		 6317 /* WaVSRefCountFullforceMissDisable:chv */
6318 /* WaDSRefCountFullforceMissDisable:chv */
6319 I915_WRITE(GEN7_FF_THREAD_MODE,
6320 I915_READ(GEN7_FF_THREAD_MODE) &
6321 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6322
6323 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6324 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6325 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6326
6327 /* WaDisableCSUnitClockGating:chv */
6328 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6329 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6330
6331 /* WaDisableSDEUnitClockGating:chv */
6332 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6333 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6334}
6335
1fa61106 6336static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6337{
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6339 uint32_t dspclk_gate;
6340
6341 I915_WRITE(RENCLK_GATE_D1, 0);
6342 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6343 GS_UNIT_CLOCK_GATE_DISABLE |
6344 CL_UNIT_CLOCK_GATE_DISABLE);
6345 I915_WRITE(RAMCLK_GATE_D, 0);
6346 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6347 OVRUNIT_CLOCK_GATE_DISABLE |
6348 OVCUNIT_CLOCK_GATE_DISABLE;
6349 if (IS_GM45(dev))
6350 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6351 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6352
6353 /* WaDisableRenderCachePipelinedFlush */
6354 I915_WRITE(CACHE_MODE_0,
6355 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6356
4e04632e
AG		 6357 /* WaDisable_RenderCache_OperationalFlush:g4x */
6358 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6359
0e088b8f 6360 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6361}
6362
1fa61106 6363static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6364{
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366
6367 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6368 I915_WRITE(RENCLK_GATE_D2, 0);
6369 I915_WRITE(DSPCLK_GATE_D, 0);
6370 I915_WRITE(RAMCLK_GATE_D, 0);
6371 I915_WRITE16(DEUC, 0);
20f94967
VS		 6372 I915_WRITE(MI_ARB_STATE,
6373 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6374
6375 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6376 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6377}
6378
1fa61106 6379static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6380{
6381 struct drm_i915_private *dev_priv = dev->dev_private;
6382
6383 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6384 I965_RCC_CLOCK_GATE_DISABLE |
6385 I965_RCPB_CLOCK_GATE_DISABLE |
6386 I965_ISC_CLOCK_GATE_DISABLE |
6387 I965_FBC_CLOCK_GATE_DISABLE);
6388 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6389 I915_WRITE(MI_ARB_STATE,
6390 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6391
6392 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6393 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6394}
6395
1fa61106 6396static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6397{
6398 struct drm_i915_private *dev_priv = dev->dev_private;
6399 u32 dstate = I915_READ(D_STATE);
6400
6401 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6402 DSTATE_DOT_CLOCK_GATING;
6403 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6404
6405 if (IS_PINEVIEW(dev))
6406 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6407
6408 /* IIR "flip pending" means done if this bit is set */
6409 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6410
6411 /* interrupts should cause a wake up from C3 */
3299254f 6412 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6413
6414 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6415 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6416
6417 I915_WRITE(MI_ARB_STATE,
6418 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6419}
6420
1fa61106 6421static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6422{
6423 struct drm_i915_private *dev_priv = dev->dev_private;
6424
6425 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6426
6427 /* interrupts should cause a wake up from C3 */
6428 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6429 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6430
6431 I915_WRITE(MEM_MODE,
6432 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6433}
6434
1fa61106 6435static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6436{
6437 struct drm_i915_private *dev_priv = dev->dev_private;
6438
6439 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6440
6441 I915_WRITE(MEM_MODE,
6442 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6443 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6444}
6445
6f1d69b0
ED		 6446void intel_init_clock_gating(struct drm_device *dev)
6447{
6448 struct drm_i915_private *dev_priv = dev->dev_private;
6449
c57e3551
DL		 6450 if (dev_priv->display.init_clock_gating)
6451 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6452}
6453
7d708ee4
ID		 6454void intel_suspend_hw(struct drm_device *dev)
6455{
6456 if (HAS_PCH_LPT(dev))
6457 lpt_suspend_hw(dev);
6458}
6459
1fa61106
ED		 6460/* Set up chip specific power management-related functions */
6461void intel_init_pm(struct drm_device *dev)
6462{
6463 struct drm_i915_private *dev_priv = dev->dev_private;
6464
7ff0ebcc 6465 intel_fbc_init(dev_priv);
1fa61106 6466
c921aba8
DV		 6467 /* For cxsr */
6468 if (IS_PINEVIEW(dev))
6469 i915_pineview_get_mem_freq(dev);
6470 else if (IS_GEN5(dev))
6471 i915_ironlake_get_mem_freq(dev);
6472
1fa61106 6473 /* For FIFO watermark updates */
f5ed50cb 6474 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6475 skl_setup_wm_latency(dev);
6476
45db2194 6477 dev_priv->display.init_clock_gating = skl_init_clock_gating;
2d41c0b5
PB		 6478 dev_priv->display.update_wm = skl_update_wm;
6479 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6480 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6481 ilk_setup_wm_latency(dev);
53615a5e 6482
bd602544
VS		 6483 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6484 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6485 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6486 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6487 dev_priv->display.update_wm = ilk_update_wm;
6488 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6489 } else {
6490 DRM_DEBUG_KMS("Failed to read display plane latency. "
6491 "Disable CxSR\n");
6492 }
6493
6494 if (IS_GEN5(dev))
1fa61106 6495 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6496 else if (IS_GEN6(dev))
1fa61106 6497 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6498 else if (IS_IVYBRIDGE(dev))
1fa61106 6499 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6500 else if (IS_HASWELL(dev))
cad2a2d7 6501 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6502 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6503 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6504 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6505 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6506 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6507 dev_priv->display.init_clock_gating =
6508 cherryview_init_clock_gating;
1fa61106
ED		 6509 } else if (IS_VALLEYVIEW(dev)) {
6510 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6511 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6512 dev_priv->display.init_clock_gating =
6513 valleyview_init_clock_gating;
1fa61106
ED		 6514 } else if (IS_PINEVIEW(dev)) {
6515 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6516 dev_priv->is_ddr3,
6517 dev_priv->fsb_freq,
6518 dev_priv->mem_freq)) {
6519 DRM_INFO("failed to find known CxSR latency "
6520 "(found ddr%s fsb freq %d, mem freq %d), "
6521 "disabling CxSR\n",
6522 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6523 dev_priv->fsb_freq, dev_priv->mem_freq);
6524 /* Disable CxSR and never update its watermark again */
5209b1f4 6525 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6526 dev_priv->display.update_wm = NULL;
6527 } else
6528 dev_priv->display.update_wm = pineview_update_wm;
6529 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6530 } else if (IS_G4X(dev)) {
6531 dev_priv->display.update_wm = g4x_update_wm;
6532 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6533 } else if (IS_GEN4(dev)) {
6534 dev_priv->display.update_wm = i965_update_wm;
6535 if (IS_CRESTLINE(dev))
6536 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6537 else if (IS_BROADWATER(dev))
6538 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6539 } else if (IS_GEN3(dev)) {
6540 dev_priv->display.update_wm = i9xx_update_wm;
6541 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6542 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6543 } else if (IS_GEN2(dev)) {
6544 if (INTEL_INFO(dev)->num_pipes == 1) {
6545 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6546 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6547 } else {
6548 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6549 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6550 }
6551
6552 if (IS_I85X(dev) || IS_I865G(dev))
6553 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6554 else
6555 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6556 } else {
6557 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6558 }
6559}
6560
151a49d0 6561int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6562{
4fc688ce 6563 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6564
6565 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6566 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6567 return -EAGAIN;
6568 }
6569
6570 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6571 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6572 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6573
6574 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6575 500)) {
6576 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6577 return -ETIMEDOUT;
6578 }
6579
6580 *val = I915_READ(GEN6_PCODE_DATA);
6581 I915_WRITE(GEN6_PCODE_DATA, 0);
6582
6583 return 0;
6584}
6585
151a49d0 6586int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6587{
4fc688ce 6588 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6589
6590 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6591 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6592 return -EAGAIN;
6593 }
6594
6595 I915_WRITE(GEN6_PCODE_DATA, val);
6596 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6597
6598 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6599 500)) {
6600 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6601 return -ETIMEDOUT;
6602 }
6603
6604 I915_WRITE(GEN6_PCODE_DATA, 0);
6605
6606 return 0;
6607}
a0e4e199 6608
dd06f88c 6609static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6610{
dd06f88c
VS		 6611 switch (czclk_freq) {
6612 case 200:
6613 return 10;
6614 case 267:
6615 return 12;
6616 case 320:
6617 case 333:
dd06f88c 6618 return 16;
ab3fb157
VS		 6619 case 400:
6620 return 20;
855ba3be
JB		 6621 default:
6622 return -1;
6623 }
dd06f88c 6624}
855ba3be 6625
dd06f88c
VS		 6626static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6627{
6628 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6629
6630 div = vlv_gpu_freq_div(czclk_freq);
6631 if (div < 0)
6632 return div;
6633
6634 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6635}
6636
b55dd647 6637static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6638{
dd06f88c 6639 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6640
dd06f88c
VS		 6641 mul = vlv_gpu_freq_div(czclk_freq);
6642 if (mul < 0)
6643 return mul;
855ba3be 6644
dd06f88c 6645 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6646}
6647
b55dd647 6648static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6649{
dd06f88c 6650 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6651
dd06f88c
VS		 6652 div = vlv_gpu_freq_div(czclk_freq) / 2;
6653 if (div < 0)
6654 return div;
22b1b2f8 6655
dd06f88c 6656 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6657}
6658
b55dd647 6659static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6660{
dd06f88c 6661 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6662
dd06f88c
VS		 6663 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6664 if (mul < 0)
6665 return mul;
22b1b2f8 6666
1c14762d 6667 /* CHV needs even values */
dd06f88c 6668 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6669}
6670
616bc820 6671int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6672{
22b1b2f8 6673 if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6674 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6675 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6676 return byt_gpu_freq(dev_priv, val);
6677 else
6678 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6679}
6680
616bc820
VS		 6681int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6682{
22b1b2f8 6683 if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6684 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6685 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6686 return byt_freq_opcode(dev_priv, val);
6687 else
6688 return val / GT_FREQUENCY_MULTIPLIER;
6689}
22b1b2f8 6690
f742a552 6691void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6692{
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6694
f742a552
DV		 6695 mutex_init(&dev_priv->rps.hw_lock);
6696
907b28c5
CW		 6697 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6698 intel_gen6_powersave_work);
5d584b2e 6699
33688d95 6700 dev_priv->pm.suspended = false;
907b28c5 6701}
Linux kernel - Deliverables
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