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drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
3dcd020a
HN		 70 if (INTEL_REVID(dev) == SKL_REVID_A0) {
71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a
HN		 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78 }
8bc0ccf6 79
2caa3b26 80 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 81 /* WaDisableHDCInvalidation:skl */
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
83 BDW_DISABLE_HDC_INVALIDATION);
84
2caa3b26
DL		 85 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
86 I915_WRITE(FF_SLICE_CS_CHICKEN2,
87 I915_READ(FF_SLICE_CS_CHICKEN2) |
88 GEN9_TSG_BARRIER_ACK_DISABLE);
89 }
81e231af 90
8bc0ccf6
DL		 91 if (INTEL_REVID(dev) <= SKL_REVID_E0)
92 /* WaDisableLSQCROPERFforOCL:skl */
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
94 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 95}
96
a82abe43
ID		 97static void bxt_init_clock_gating(struct drm_device *dev)
98{
32608ca2
ID		 99 struct drm_i915_private *dev_priv = dev->dev_private;
100
a82abe43 101 gen9_init_clock_gating(dev);
32608ca2
ID		 102
103 /*
104 * FIXME:
105 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 106 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 107 */
108 /* WaDisableSDEUnitClockGating:bxt */
109 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 110 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
111 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 112
a82abe43
ID		 113}
114
c921aba8
DV		 115static void i915_pineview_get_mem_freq(struct drm_device *dev)
116{
50227e1c 117 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 118 u32 tmp;
119
120 tmp = I915_READ(CLKCFG);
121
122 switch (tmp & CLKCFG_FSB_MASK) {
123 case CLKCFG_FSB_533:
124 dev_priv->fsb_freq = 533; /* 133*4 */
125 break;
126 case CLKCFG_FSB_800:
127 dev_priv->fsb_freq = 800; /* 200*4 */
128 break;
129 case CLKCFG_FSB_667:
130 dev_priv->fsb_freq = 667; /* 167*4 */
131 break;
132 case CLKCFG_FSB_400:
133 dev_priv->fsb_freq = 400; /* 100*4 */
134 break;
135 }
136
137 switch (tmp & CLKCFG_MEM_MASK) {
138 case CLKCFG_MEM_533:
139 dev_priv->mem_freq = 533;
140 break;
141 case CLKCFG_MEM_667:
142 dev_priv->mem_freq = 667;
143 break;
144 case CLKCFG_MEM_800:
145 dev_priv->mem_freq = 800;
146 break;
147 }
148
149 /* detect pineview DDR3 setting */
150 tmp = I915_READ(CSHRDDR3CTL);
151 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
152}
153
154static void i915_ironlake_get_mem_freq(struct drm_device *dev)
155{
50227e1c 156 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 157 u16 ddrpll, csipll;
158
159 ddrpll = I915_READ16(DDRMPLL1);
160 csipll = I915_READ16(CSIPLL0);
161
162 switch (ddrpll & 0xff) {
163 case 0xc:
164 dev_priv->mem_freq = 800;
165 break;
166 case 0x10:
167 dev_priv->mem_freq = 1066;
168 break;
169 case 0x14:
170 dev_priv->mem_freq = 1333;
171 break;
172 case 0x18:
173 dev_priv->mem_freq = 1600;
174 break;
175 default:
176 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
177 ddrpll & 0xff);
178 dev_priv->mem_freq = 0;
179 break;
180 }
181
20e4d407 182 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 183
184 switch (csipll & 0x3ff) {
185 case 0x00c:
186 dev_priv->fsb_freq = 3200;
187 break;
188 case 0x00e:
189 dev_priv->fsb_freq = 3733;
190 break;
191 case 0x010:
192 dev_priv->fsb_freq = 4266;
193 break;
194 case 0x012:
195 dev_priv->fsb_freq = 4800;
196 break;
197 case 0x014:
198 dev_priv->fsb_freq = 5333;
199 break;
200 case 0x016:
201 dev_priv->fsb_freq = 5866;
202 break;
203 case 0x018:
204 dev_priv->fsb_freq = 6400;
205 break;
206 default:
207 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
208 csipll & 0x3ff);
209 dev_priv->fsb_freq = 0;
210 break;
211 }
212
213 if (dev_priv->fsb_freq == 3200) {
20e4d407 214 dev_priv->ips.c_m = 0;
c921aba8 215 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 216 dev_priv->ips.c_m = 1;
c921aba8 217 } else {
20e4d407 218 dev_priv->ips.c_m = 2;
c921aba8
DV		 219 }
220}
221
b445e3b0
ED		 222static const struct cxsr_latency cxsr_latency_table[] = {
223 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
224 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
225 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
226 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
227 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
228
229 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
230 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
231 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
232 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
233 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
234
235 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
236 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
237 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
238 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
239 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
240
241 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
242 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
243 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
244 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
245 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
246
247 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
248 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
249 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
250 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
251 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
252
253 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
254 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
255 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
256 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
257 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
258};
259
63c62275 260static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 261 int is_ddr3,
262 int fsb,
263 int mem)
264{
265 const struct cxsr_latency *latency;
266 int i;
267
268 if (fsb == 0 || mem == 0)
269 return NULL;
270
271 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
272 latency = &cxsr_latency_table[i];
273 if (is_desktop == latency->is_desktop &&
274 is_ddr3 == latency->is_ddr3 &&
275 fsb == latency->fsb_freq && mem == latency->mem_freq)
276 return latency;
277 }
278
279 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
280
281 return NULL;
282}
283
fc1ac8de
VS		 284static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
285{
286 u32 val;
287
288 mutex_lock(&dev_priv->rps.hw_lock);
289
290 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
291 if (enable)
292 val &= ~FORCE_DDR_HIGH_FREQ;
293 else
294 val |= FORCE_DDR_HIGH_FREQ;
295 val &= ~FORCE_DDR_LOW_FREQ;
296 val |= FORCE_DDR_FREQ_REQ_ACK;
297 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
298
299 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
300 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
301 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
302
303 mutex_unlock(&dev_priv->rps.hw_lock);
304}
305
cfb41411
VS		 306static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
307{
308 u32 val;
309
310 mutex_lock(&dev_priv->rps.hw_lock);
311
312 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
313 if (enable)
314 val |= DSP_MAXFIFO_PM5_ENABLE;
315 else
316 val &= ~DSP_MAXFIFO_PM5_ENABLE;
317 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
318
319 mutex_unlock(&dev_priv->rps.hw_lock);
320}
321
f4998963
VS		 322#define FW_WM(value, plane) \
323 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
324
5209b1f4 325void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 326{
5209b1f4
ID		 327 struct drm_device *dev = dev_priv->dev;
328 u32 val;
b445e3b0 329
5209b1f4
ID		 330 if (IS_VALLEYVIEW(dev)) {
331 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS		 332 if (IS_CHERRYVIEW(dev))
333 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID		 334 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
335 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
336 } else if (IS_PINEVIEW(dev)) {
337 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
338 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
339 I915_WRITE(DSPFW3, val);
340 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
341 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
342 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
343 I915_WRITE(FW_BLC_SELF, val);
344 } else if (IS_I915GM(dev)) {
345 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
346 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
347 I915_WRITE(INSTPM, val);
348 } else {
349 return;
350 }
b445e3b0 351
5209b1f4
ID		 352 DRM_DEBUG_KMS("memory self-refresh is %s\n",
353 enable ? "enabled" : "disabled");
b445e3b0
ED		 354}
355
fc1ac8de 356
b445e3b0
ED		 357/*
358 * Latency for FIFO fetches is dependent on several factors:
359 * - memory configuration (speed, channels)
360 * - chipset
361 * - current MCH state
362 * It can be fairly high in some situations, so here we assume a fairly
363 * pessimal value. It's a tradeoff between extra memory fetches (if we
364 * set this value too high, the FIFO will fetch frequently to stay full)
365 * and power consumption (set it too low to save power and we might see
366 * FIFO underruns and display "flicker").
367 *
368 * A value of 5us seems to be a good balance; safe for very low end
369 * platforms but not overly aggressive on lower latency configs.
370 */
5aef6003 371static const int pessimal_latency_ns = 5000;
b445e3b0 372
b5004720
VS		 373#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
374 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
375
376static int vlv_get_fifo_size(struct drm_device *dev,
377 enum pipe pipe, int plane)
378{
379 struct drm_i915_private *dev_priv = dev->dev_private;
380 int sprite0_start, sprite1_start, size;
381
382 switch (pipe) {
383 uint32_t dsparb, dsparb2, dsparb3;
384 case PIPE_A:
385 dsparb = I915_READ(DSPARB);
386 dsparb2 = I915_READ(DSPARB2);
387 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
388 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
389 break;
390 case PIPE_B:
391 dsparb = I915_READ(DSPARB);
392 dsparb2 = I915_READ(DSPARB2);
393 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
394 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
395 break;
396 case PIPE_C:
397 dsparb2 = I915_READ(DSPARB2);
398 dsparb3 = I915_READ(DSPARB3);
399 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
400 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
401 break;
402 default:
403 return 0;
404 }
405
406 switch (plane) {
407 case 0:
408 size = sprite0_start;
409 break;
410 case 1:
411 size = sprite1_start - sprite0_start;
412 break;
413 case 2:
414 size = 512 - 1 - sprite1_start;
415 break;
416 default:
417 return 0;
418 }
419
420 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
421 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
422 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
423 size);
424
425 return size;
426}
427
1fa61106 428static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 429{
430 struct drm_i915_private *dev_priv = dev->dev_private;
431 uint32_t dsparb = I915_READ(DSPARB);
432 int size;
433
434 size = dsparb & 0x7f;
435 if (plane)
436 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
437
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
439 plane ? "B" : "A", size);
440
441 return size;
442}
443
feb56b93 444static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 445{
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 uint32_t dsparb = I915_READ(DSPARB);
448 int size;
449
450 size = dsparb & 0x1ff;
451 if (plane)
452 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
453 size >>= 1; /* Convert to cachelines */
454
455 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
456 plane ? "B" : "A", size);
457
458 return size;
459}
460
1fa61106 461static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 462{
463 struct drm_i915_private *dev_priv = dev->dev_private;
464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x7f;
468 size >>= 2; /* Convert to cachelines */
469
470 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
471 plane ? "B" : "A",
472 size);
473
474 return size;
475}
476
b445e3b0
ED		 477/* Pineview has different values for various configs */
478static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 479 .fifo_size = PINEVIEW_DISPLAY_FIFO,
480 .max_wm = PINEVIEW_MAX_WM,
481 .default_wm = PINEVIEW_DFT_WM,
482 .guard_size = PINEVIEW_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 484};
485static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 486 .fifo_size = PINEVIEW_DISPLAY_FIFO,
487 .max_wm = PINEVIEW_MAX_WM,
488 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
489 .guard_size = PINEVIEW_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 491};
492static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 493 .fifo_size = PINEVIEW_CURSOR_FIFO,
494 .max_wm = PINEVIEW_CURSOR_MAX_WM,
495 .default_wm = PINEVIEW_CURSOR_DFT_WM,
496 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
497 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 498};
499static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 500 .fifo_size = PINEVIEW_CURSOR_FIFO,
501 .max_wm = PINEVIEW_CURSOR_MAX_WM,
502 .default_wm = PINEVIEW_CURSOR_DFT_WM,
503 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
504 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 505};
506static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 507 .fifo_size = G4X_FIFO_SIZE,
508 .max_wm = G4X_MAX_WM,
509 .default_wm = G4X_MAX_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 512};
513static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = I965_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 519};
520static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 521 .fifo_size = VALLEYVIEW_FIFO_SIZE,
522 .max_wm = VALLEYVIEW_MAX_WM,
523 .default_wm = VALLEYVIEW_MAX_WM,
524 .guard_size = 2,
525 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 526};
527static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 528 .fifo_size = I965_CURSOR_FIFO,
529 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
530 .default_wm = I965_CURSOR_DFT_WM,
531 .guard_size = 2,
532 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 533};
534static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 535 .fifo_size = I965_CURSOR_FIFO,
536 .max_wm = I965_CURSOR_MAX_WM,
537 .default_wm = I965_CURSOR_DFT_WM,
538 .guard_size = 2,
539 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 540};
541static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 542 .fifo_size = I945_FIFO_SIZE,
543 .max_wm = I915_MAX_WM,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 547};
548static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 549 .fifo_size = I915_FIFO_SIZE,
550 .max_wm = I915_MAX_WM,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 554};
9d539105 555static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 556 .fifo_size = I855GM_FIFO_SIZE,
557 .max_wm = I915_MAX_WM,
558 .default_wm = 1,
559 .guard_size = 2,
560 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 561};
9d539105
VS		 562static const struct intel_watermark_params i830_bc_wm_info = {
563 .fifo_size = I855GM_FIFO_SIZE,
564 .max_wm = I915_MAX_WM/2,
565 .default_wm = 1,
566 .guard_size = 2,
567 .cacheline_size = I830_FIFO_LINE_SIZE,
568};
feb56b93 569static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 570 .fifo_size = I830_FIFO_SIZE,
571 .max_wm = I915_MAX_WM,
572 .default_wm = 1,
573 .guard_size = 2,
574 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 575};
576
b445e3b0
ED		 577/**
578 * intel_calculate_wm - calculate watermark level
579 * @clock_in_khz: pixel clock
580 * @wm: chip FIFO params
581 * @pixel_size: display pixel size
582 * @latency_ns: memory latency for the platform
583 *
584 * Calculate the watermark level (the level at which the display plane will
585 * start fetching from memory again). Each chip has a different display
586 * FIFO size and allocation, so the caller needs to figure that out and pass
587 * in the correct intel_watermark_params structure.
588 *
589 * As the pixel clock runs, the FIFO will be drained at a rate that depends
590 * on the pixel size. When it reaches the watermark level, it'll start
591 * fetching FIFO line sized based chunks from memory until the FIFO fills
592 * past the watermark point. If the FIFO drains completely, a FIFO underrun
593 * will occur, and a display engine hang could result.
594 */
595static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
596 const struct intel_watermark_params *wm,
597 int fifo_size,
598 int pixel_size,
599 unsigned long latency_ns)
600{
601 long entries_required, wm_size;
602
603 /*
604 * Note: we need to make sure we don't overflow for various clock &
605 * latency values.
606 * clocks go from a few thousand to several hundred thousand.
607 * latency is usually a few thousand
608 */
609 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
610 1000;
611 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
612
613 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
614
615 wm_size = fifo_size - (entries_required + wm->guard_size);
616
617 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
618
619 /* Don't promote wm_size to unsigned... */
620 if (wm_size > (long)wm->max_wm)
621 wm_size = wm->max_wm;
622 if (wm_size <= 0)
623 wm_size = wm->default_wm;
d6feb196
VS		 624
625 /*
626 * Bspec seems to indicate that the value shouldn't be lower than
627 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
628 * Lets go for 8 which is the burst size since certain platforms
629 * already use a hardcoded 8 (which is what the spec says should be
630 * done).
631 */
632 if (wm_size <= 8)
633 wm_size = 8;
634
b445e3b0
ED		 635 return wm_size;
636}
637
638static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
639{
640 struct drm_crtc *crtc, *enabled = NULL;
641
70e1e0ec 642 for_each_crtc(dev, crtc) {
3490ea5d 643 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 644 if (enabled)
645 return NULL;
646 enabled = crtc;
647 }
648 }
649
650 return enabled;
651}
652
46ba614c 653static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 654{
46ba614c 655 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 656 struct drm_i915_private *dev_priv = dev->dev_private;
657 struct drm_crtc *crtc;
658 const struct cxsr_latency *latency;
659 u32 reg;
660 unsigned long wm;
661
662 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
663 dev_priv->fsb_freq, dev_priv->mem_freq);
664 if (!latency) {
665 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 666 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 667 return;
668 }
669
670 crtc = single_enabled_crtc(dev);
671 if (crtc) {
241bfc38 672 const struct drm_display_mode *adjusted_mode;
59bea882 673 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 674 int clock;
675
6e3c9717 676 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 677 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 678
679 /* Display SR */
680 wm = intel_calculate_wm(clock, &pineview_display_wm,
681 pineview_display_wm.fifo_size,
682 pixel_size, latency->display_sr);
683 reg = I915_READ(DSPFW1);
684 reg &= ~DSPFW_SR_MASK;
f4998963 685 reg |= FW_WM(wm, SR);
b445e3b0
ED		 686 I915_WRITE(DSPFW1, reg);
687 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
688
689 /* cursor SR */
690 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
691 pineview_display_wm.fifo_size,
692 pixel_size, latency->cursor_sr);
693 reg = I915_READ(DSPFW3);
694 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 695 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 696 I915_WRITE(DSPFW3, reg);
697
698 /* Display HPLL off SR */
699 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
700 pineview_display_hplloff_wm.fifo_size,
701 pixel_size, latency->display_hpll_disable);
702 reg = I915_READ(DSPFW3);
703 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 704 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 705 I915_WRITE(DSPFW3, reg);
706
707 /* cursor HPLL off SR */
708 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
709 pineview_display_hplloff_wm.fifo_size,
710 pixel_size, latency->cursor_hpll_disable);
711 reg = I915_READ(DSPFW3);
712 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 713 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 714 I915_WRITE(DSPFW3, reg);
715 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
716
5209b1f4 717 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 718 } else {
5209b1f4 719 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 720 }
721}
722
723static bool g4x_compute_wm0(struct drm_device *dev,
724 int plane,
725 const struct intel_watermark_params *display,
726 int display_latency_ns,
727 const struct intel_watermark_params *cursor,
728 int cursor_latency_ns,
729 int *plane_wm,
730 int *cursor_wm)
731{
732 struct drm_crtc *crtc;
4fe8590a 733 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 734 int htotal, hdisplay, clock, pixel_size;
735 int line_time_us, line_count;
736 int entries, tlb_miss;
737
738 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 739 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 740 *cursor_wm = cursor->guard_size;
741 *plane_wm = display->guard_size;
742 return false;
743 }
744
6e3c9717 745 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 746 clock = adjusted_mode->crtc_clock;
fec8cba3 747 htotal = adjusted_mode->crtc_htotal;
6e3c9717 748 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 749 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 750
751 /* Use the small buffer method to calculate plane watermark */
752 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
753 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
754 if (tlb_miss > 0)
755 entries += tlb_miss;
756 entries = DIV_ROUND_UP(entries, display->cacheline_size);
757 *plane_wm = entries + display->guard_size;
758 if (*plane_wm > (int)display->max_wm)
759 *plane_wm = display->max_wm;
760
761 /* Use the large buffer method to calculate cursor watermark */
922044c9 762 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 763 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 764 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 765 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
766 if (tlb_miss > 0)
767 entries += tlb_miss;
768 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
769 *cursor_wm = entries + cursor->guard_size;
770 if (*cursor_wm > (int)cursor->max_wm)
771 *cursor_wm = (int)cursor->max_wm;
772
773 return true;
774}
775
776/*
777 * Check the wm result.
778 *
779 * If any calculated watermark values is larger than the maximum value that
780 * can be programmed into the associated watermark register, that watermark
781 * must be disabled.
782 */
783static bool g4x_check_srwm(struct drm_device *dev,
784 int display_wm, int cursor_wm,
785 const struct intel_watermark_params *display,
786 const struct intel_watermark_params *cursor)
787{
788 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
789 display_wm, cursor_wm);
790
791 if (display_wm > display->max_wm) {
792 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
793 display_wm, display->max_wm);
794 return false;
795 }
796
797 if (cursor_wm > cursor->max_wm) {
798 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
799 cursor_wm, cursor->max_wm);
800 return false;
801 }
802
803 if (!(display_wm || cursor_wm)) {
804 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
805 return false;
806 }
807
808 return true;
809}
810
811static bool g4x_compute_srwm(struct drm_device *dev,
812 int plane,
813 int latency_ns,
814 const struct intel_watermark_params *display,
815 const struct intel_watermark_params *cursor,
816 int *display_wm, int *cursor_wm)
817{
818 struct drm_crtc *crtc;
4fe8590a 819 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 820 int hdisplay, htotal, pixel_size, clock;
821 unsigned long line_time_us;
822 int line_count, line_size;
823 int small, large;
824 int entries;
825
826 if (!latency_ns) {
827 *display_wm = *cursor_wm = 0;
828 return false;
829 }
830
831 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 832 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 833 clock = adjusted_mode->crtc_clock;
fec8cba3 834 htotal = adjusted_mode->crtc_htotal;
6e3c9717 835 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 836 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 837
922044c9 838 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 839 line_count = (latency_ns / line_time_us + 1000) / 1000;
840 line_size = hdisplay * pixel_size;
841
842 /* Use the minimum of the small and large buffer method for primary */
843 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
844 large = line_count * line_size;
845
846 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
847 *display_wm = entries + display->guard_size;
848
849 /* calculate the self-refresh watermark for display cursor */
3dd512fb 850 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 851 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
852 *cursor_wm = entries + cursor->guard_size;
853
854 return g4x_check_srwm(dev,
855 *display_wm, *cursor_wm,
856 display, cursor);
857}
858
15665979
VS		 859#define FW_WM_VLV(value, plane) \
860 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
861
0018fda1
VS		 862static void vlv_write_wm_values(struct intel_crtc *crtc,
863 const struct vlv_wm_values *wm)
864{
865 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
866 enum pipe pipe = crtc->pipe;
867
868 I915_WRITE(VLV_DDL(pipe),
869 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
870 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
871 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
872 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
873
ae80152d 874 I915_WRITE(DSPFW1,
15665979
VS		 875 FW_WM(wm->sr.plane, SR) |
876 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
877 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
878 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 879 I915_WRITE(DSPFW2,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
881 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
882 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 883 I915_WRITE(DSPFW3,
15665979 884 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 885
886 if (IS_CHERRYVIEW(dev_priv)) {
887 I915_WRITE(DSPFW7_CHV,
15665979
VS		 888 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
889 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 890 I915_WRITE(DSPFW8_CHV,
15665979
VS		 891 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
892 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 893 I915_WRITE(DSPFW9_CHV,
15665979
VS		 894 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
895 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 896 I915_WRITE(DSPHOWM,
15665979
VS		 897 FW_WM(wm->sr.plane >> 9, SR_HI) |
898 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
899 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
900 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
902 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
903 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
904 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
905 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
906 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 907 } else {
908 I915_WRITE(DSPFW7,
15665979
VS		 909 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
910 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 911 I915_WRITE(DSPHOWM,
15665979
VS		 912 FW_WM(wm->sr.plane >> 9, SR_HI) |
913 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
914 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
915 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
916 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
917 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
918 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 919 }
920
921 POSTING_READ(DSPFW1);
922
0018fda1
VS		 923 dev_priv->wm.vlv = *wm;
924}
925
15665979
VS		 926#undef FW_WM_VLV
927
341c526f 928static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 929 struct drm_plane *plane)
b445e3b0 930{
5e56ba45 931 struct drm_device *dev = crtc->dev;
883a3d2f
VS		 932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
933 int entries, prec_mult, drain_latency, pixel_size;
934 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 935 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 936
883a3d2f
VS		 937 /*
938 * FIXME the plane might have an fb
939 * but be invisible (eg. due to clipping)
940 */
941 if (!intel_crtc->active || !plane->state->fb)
942 return 0;
943
0948c265 944 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 945 return 0;
b445e3b0 946
883a3d2f
VS		 947 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
948
0948c265 949 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 950 return 0;
b445e3b0 951
a398e9c7 952 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 953
341c526f
VS		 954 prec_mult = high_precision;
955 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 956
341c526f
VS		 957 if (drain_latency > DRAIN_LATENCY_MASK) {
958 prec_mult /= 2;
959 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS		 960 }
961
341c526f
VS		 962 if (drain_latency > DRAIN_LATENCY_MASK)
963 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 964
341c526f
VS		 965 return drain_latency | (prec_mult == high_precision ?
966 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED		 967}
968
ae80152d
VS		 969static int vlv_compute_wm(struct intel_crtc *crtc,
970 struct intel_plane *plane,
971 int fifo_size)
b445e3b0 972{
ae80152d 973 int clock, entries, pixel_size;
b445e3b0 974
ae80152d
VS		 975 /*
976 * FIXME the plane might have an fb
977 * but be invisible (eg. due to clipping)
978 */
979 if (!crtc->active || !plane->base.state->fb)
980 return 0;
0948c265 981
ae80152d
VS		 982 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
983 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 984
ae80152d 985 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 986
ae80152d
VS		 987 /*
988 * Set up the watermark such that we don't start issuing memory
989 * requests until we are within PND's max deadline value (256us).
990 * Idea being to be idle as long as possible while still taking
991 * advatange of PND's deadline scheduling. The limit of 8
992 * cachelines (used when the FIFO will anyway drain in less time
993 * than 256us) should match what we would be done if trickle
994 * feed were enabled.
995 */
996 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
997}
998
999static bool vlv_compute_sr_wm(struct drm_device *dev,
1000 struct vlv_wm_values *wm)
b445e3b0 1001{
ae80152d
VS		 1002 struct drm_i915_private *dev_priv = to_i915(dev);
1003 struct drm_crtc *crtc;
1004 enum pipe pipe = INVALID_PIPE;
1005 int num_planes = 0;
1006 int fifo_size = 0;
1007 struct intel_plane *plane;
b445e3b0 1008
ae80152d 1009 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 1010
ae80152d
VS		 1011 crtc = single_enabled_crtc(dev);
1012 /* maxfifo not supported on pipe C */
1013 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1014 pipe = to_intel_crtc(crtc)->pipe;
1015 num_planes = !!wm->pipe[pipe].primary +
1016 !!wm->pipe[pipe].sprite[0] +
1017 !!wm->pipe[pipe].sprite[1];
1018 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1019 }
b445e3b0 1020
ae80152d
VS		 1021 if (fifo_size == 0 || num_planes > 1)
1022 return false;
b445e3b0 1023
ae80152d
VS		 1024 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1025 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1026
ae80152d
VS		 1027 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1028 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1029 continue;
b445e3b0 1030
ae80152d
VS		 1031 if (plane->pipe != pipe)
1032 continue;
9858425c 1033
ae80152d
VS		 1034 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1035 plane, fifo_size);
1036 if (wm->sr.plane != 0)
1037 break;
1038 }
1039
1040 return true;
b445e3b0
ED		 1041}
1042
ae80152d 1043static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS		 1044{
1045 struct drm_device *dev = crtc->dev;
3c2777fd 1046 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS		 1047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1048 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1049 bool cxsr_enabled;
ae80152d 1050 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1051
ae80152d
VS		 1052 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1053 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1054 to_intel_plane(crtc->primary),
1055 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1056
ae80152d
VS		 1057 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1058 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1059 to_intel_plane(crtc->cursor),
1060 0x3f);
3c2777fd 1061
ae80152d 1062 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1063
ae80152d
VS		 1064 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1065 return;
3c2777fd 1066
ae80152d
VS		 1067 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1068 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1069 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1070 wm.sr.plane, wm.sr.cursor);
3c2777fd 1071
fc1ac8de
VS		 1072 /*
1073 * FIXME DDR DVFS introduces massive memory latencies which
1074 * are not known to system agent so any deadline specified
1075 * by the display may not be respected. To support DDR DVFS
1076 * the watermark code needs to be rewritten to essentially
1077 * bypass deadline mechanism and rely solely on the
1078 * watermarks. For now disable DDR DVFS.
1079 */
1080 if (IS_CHERRYVIEW(dev_priv))
1081 chv_set_memory_dvfs(dev_priv, false);
1082
ae80152d
VS		 1083 if (!cxsr_enabled)
1084 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1085
ae80152d 1086 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS		 1087
1088 if (cxsr_enabled)
1089 intel_set_memory_cxsr(dev_priv, true);
1090}
1091
01e184cc
GB		 1092static void valleyview_update_sprite_wm(struct drm_plane *plane,
1093 struct drm_crtc *crtc,
1094 uint32_t sprite_width,
1095 uint32_t sprite_height,
1096 int pixel_size,
1097 bool enabled, bool scaled)
1098{
1099 struct drm_device *dev = crtc->dev;
1100 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS		 1101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1102 enum pipe pipe = intel_crtc->pipe;
01e184cc 1103 int sprite = to_intel_plane(plane)->plane;
ae80152d 1104 bool cxsr_enabled;
0018fda1 1105 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1106
ae80152d 1107 if (enabled) {
0018fda1 1108 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1109 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS		 1110
1111 wm.pipe[pipe].sprite[sprite] =
1112 vlv_compute_wm(intel_crtc,
1113 to_intel_plane(plane),
1114 vlv_get_fifo_size(dev, pipe, sprite+1));
1115 } else {
0018fda1 1116 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS		 1117 wm.pipe[pipe].sprite[sprite] = 0;
1118 }
1119
1120 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1121
1122 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1123 return;
1124
1125 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1126 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1127 sprite_name(pipe, sprite),
1128 wm.pipe[pipe].sprite[sprite],
1129 wm.sr.plane, wm.sr.cursor);
1130
1131 if (!cxsr_enabled)
1132 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1133
0018fda1 1134 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS		 1135
1136 if (cxsr_enabled)
1137 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB		 1138}
1139
ae80152d
VS		 1140#define single_plane_enabled(mask) is_power_of_2(mask)
1141
46ba614c 1142static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1143{
46ba614c 1144 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1145 static const int sr_latency_ns = 12000;
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1148 int plane_sr, cursor_sr;
1149 unsigned int enabled = 0;
9858425c 1150 bool cxsr_enabled;
b445e3b0 1151
51cea1f4 1152 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1153 &g4x_wm_info, pessimal_latency_ns,
1154 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1155 &planea_wm, &cursora_wm))
51cea1f4 1156 enabled |= 1 << PIPE_A;
b445e3b0 1157
51cea1f4 1158 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1159 &g4x_wm_info, pessimal_latency_ns,
1160 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1161 &planeb_wm, &cursorb_wm))
51cea1f4 1162 enabled |= 1 << PIPE_B;
b445e3b0 1163
b445e3b0
ED		 1164 if (single_plane_enabled(enabled) &&
1165 g4x_compute_srwm(dev, ffs(enabled) - 1,
1166 sr_latency_ns,
1167 &g4x_wm_info,
1168 &g4x_cursor_wm_info,
52bd02d8 1169 &plane_sr, &cursor_sr)) {
9858425c 1170 cxsr_enabled = true;
52bd02d8 1171 } else {
9858425c 1172 cxsr_enabled = false;
5209b1f4 1173 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1174 plane_sr = cursor_sr = 0;
1175 }
b445e3b0 1176
a5043453
VS		 1177 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1178 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1179 planea_wm, cursora_wm,
1180 planeb_wm, cursorb_wm,
1181 plane_sr, cursor_sr);
1182
1183 I915_WRITE(DSPFW1,
f4998963
VS		 1184 FW_WM(plane_sr, SR) |
1185 FW_WM(cursorb_wm, CURSORB) |
1186 FW_WM(planeb_wm, PLANEB) |
1187 FW_WM(planea_wm, PLANEA));
b445e3b0 1188 I915_WRITE(DSPFW2,
8c919b28 1189 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1190 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1191 /* HPLL off in SR has some issues on G4x... disable it */
1192 I915_WRITE(DSPFW3,
8c919b28 1193 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1194 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1195
1196 if (cxsr_enabled)
1197 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1198}
1199
46ba614c 1200static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1201{
46ba614c 1202 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 struct drm_crtc *crtc;
1205 int srwm = 1;
1206 int cursor_sr = 16;
9858425c 1207 bool cxsr_enabled;
b445e3b0
ED		 1208
1209 /* Calc sr entries for one plane configs */
1210 crtc = single_enabled_crtc(dev);
1211 if (crtc) {
1212 /* self-refresh has much higher latency */
1213 static const int sr_latency_ns = 12000;
4fe8590a 1214 const struct drm_display_mode *adjusted_mode =
6e3c9717 1215 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1216 int clock = adjusted_mode->crtc_clock;
fec8cba3 1217 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1218 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1219 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1220 unsigned long line_time_us;
1221 int entries;
1222
922044c9 1223 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1224
1225 /* Use ns/us then divide to preserve precision */
1226 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1227 pixel_size * hdisplay;
1228 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1229 srwm = I965_FIFO_SIZE - entries;
1230 if (srwm < 0)
1231 srwm = 1;
1232 srwm &= 0x1ff;
1233 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1234 entries, srwm);
1235
1236 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1237 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1238 entries = DIV_ROUND_UP(entries,
1239 i965_cursor_wm_info.cacheline_size);
1240 cursor_sr = i965_cursor_wm_info.fifo_size -
1241 (entries + i965_cursor_wm_info.guard_size);
1242
1243 if (cursor_sr > i965_cursor_wm_info.max_wm)
1244 cursor_sr = i965_cursor_wm_info.max_wm;
1245
1246 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1247 "cursor %d\n", srwm, cursor_sr);
1248
9858425c 1249 cxsr_enabled = true;
b445e3b0 1250 } else {
9858425c 1251 cxsr_enabled = false;
b445e3b0 1252 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1253 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1254 }
1255
1256 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1257 srwm);
1258
1259 /* 965 has limitations... */
f4998963
VS		 1260 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1261 FW_WM(8, CURSORB) |
1262 FW_WM(8, PLANEB) |
1263 FW_WM(8, PLANEA));
1264 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1265 FW_WM(8, PLANEC_OLD));
b445e3b0 1266 /* update cursor SR watermark */
f4998963 1267 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1268
1269 if (cxsr_enabled)
1270 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1271}
1272
f4998963
VS		 1273#undef FW_WM
1274
46ba614c 1275static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1276{
46ba614c 1277 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279 const struct intel_watermark_params *wm_info;
1280 uint32_t fwater_lo;
1281 uint32_t fwater_hi;
1282 int cwm, srwm = 1;
1283 int fifo_size;
1284 int planea_wm, planeb_wm;
1285 struct drm_crtc *crtc, *enabled = NULL;
1286
1287 if (IS_I945GM(dev))
1288 wm_info = &i945_wm_info;
1289 else if (!IS_GEN2(dev))
1290 wm_info = &i915_wm_info;
1291 else
9d539105 1292 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1293
1294 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1295 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1296 if (intel_crtc_active(crtc)) {
241bfc38 1297 const struct drm_display_mode *adjusted_mode;
59bea882 1298 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1299 if (IS_GEN2(dev))
1300 cpp = 4;
1301
6e3c9717 1302 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1303 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1304 wm_info, fifo_size, cpp,
5aef6003 1305 pessimal_latency_ns);
b445e3b0 1306 enabled = crtc;
9d539105 1307 } else {
b445e3b0 1308 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1309 if (planea_wm > (long)wm_info->max_wm)
1310 planea_wm = wm_info->max_wm;
1311 }
1312
1313 if (IS_GEN2(dev))
1314 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1315
1316 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1317 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1318 if (intel_crtc_active(crtc)) {
241bfc38 1319 const struct drm_display_mode *adjusted_mode;
59bea882 1320 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1321 if (IS_GEN2(dev))
1322 cpp = 4;
1323
6e3c9717 1324 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1325 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1326 wm_info, fifo_size, cpp,
5aef6003 1327 pessimal_latency_ns);
b445e3b0
ED		 1328 if (enabled == NULL)
1329 enabled = crtc;
1330 else
1331 enabled = NULL;
9d539105 1332 } else {
b445e3b0 1333 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1334 if (planeb_wm > (long)wm_info->max_wm)
1335 planeb_wm = wm_info->max_wm;
1336 }
b445e3b0
ED		 1337
1338 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1339
2ab1bc9d 1340 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1341 struct drm_i915_gem_object *obj;
2ab1bc9d 1342
59bea882 1343 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1344
1345 /* self-refresh seems busted with untiled */
2ff8fde1 1346 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1347 enabled = NULL;
1348 }
1349
b445e3b0
ED		 1350 /*
1351 * Overlay gets an aggressive default since video jitter is bad.
1352 */
1353 cwm = 2;
1354
1355 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1356 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1357
1358 /* Calc sr entries for one plane configs */
1359 if (HAS_FW_BLC(dev) && enabled) {
1360 /* self-refresh has much higher latency */
1361 static const int sr_latency_ns = 6000;
4fe8590a 1362 const struct drm_display_mode *adjusted_mode =
6e3c9717 1363 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1364 int clock = adjusted_mode->crtc_clock;
fec8cba3 1365 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1366 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1367 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1368 unsigned long line_time_us;
1369 int entries;
1370
922044c9 1371 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1372
1373 /* Use ns/us then divide to preserve precision */
1374 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1375 pixel_size * hdisplay;
1376 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1377 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1378 srwm = wm_info->fifo_size - entries;
1379 if (srwm < 0)
1380 srwm = 1;
1381
1382 if (IS_I945G(dev) || IS_I945GM(dev))
1383 I915_WRITE(FW_BLC_SELF,
1384 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1385 else if (IS_I915GM(dev))
1386 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1387 }
1388
1389 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1390 planea_wm, planeb_wm, cwm, srwm);
1391
1392 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1393 fwater_hi = (cwm & 0x1f);
1394
1395 /* Set request length to 8 cachelines per fetch */
1396 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1397 fwater_hi = fwater_hi | (1 << 8);
1398
1399 I915_WRITE(FW_BLC, fwater_lo);
1400 I915_WRITE(FW_BLC2, fwater_hi);
1401
5209b1f4
ID		 1402 if (enabled)
1403 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1404}
1405
feb56b93 1406static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1407{
46ba614c 1408 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1409 struct drm_i915_private *dev_priv = dev->dev_private;
1410 struct drm_crtc *crtc;
241bfc38 1411 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1412 uint32_t fwater_lo;
1413 int planea_wm;
1414
1415 crtc = single_enabled_crtc(dev);
1416 if (crtc == NULL)
1417 return;
1418
6e3c9717 1419 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1420 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1421 &i845_wm_info,
b445e3b0 1422 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1423 4, pessimal_latency_ns);
b445e3b0
ED		 1424 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1425 fwater_lo |= (3<<8) | planea_wm;
1426
1427 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1428
1429 I915_WRITE(FW_BLC, fwater_lo);
1430}
1431
3658729a
VS		 1432static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1433 struct drm_crtc *crtc)
801bcfff
PZ		 1434{
1435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1436 uint32_t pixel_rate;
801bcfff 1437
6e3c9717 1438 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1439
1440 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1441 * adjust the pixel_rate here. */
1442
6e3c9717 1443 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1444 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1445 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1446
6e3c9717
ACO		 1447 pipe_w = intel_crtc->config->pipe_src_w;
1448 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1449 pfit_w = (pfit_size >> 16) & 0xFFFF;
1450 pfit_h = pfit_size & 0xFFFF;
1451 if (pipe_w < pfit_w)
1452 pipe_w = pfit_w;
1453 if (pipe_h < pfit_h)
1454 pipe_h = pfit_h;
1455
1456 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1457 pfit_w * pfit_h);
1458 }
1459
1460 return pixel_rate;
1461}
1462
37126462 1463/* latency must be in 0.1us units. */
23297044 1464static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1465 uint32_t latency)
1466{
1467 uint64_t ret;
1468
3312ba65
VS		 1469 if (WARN(latency == 0, "Latency value missing\n"))
1470 return UINT_MAX;
1471
801bcfff
PZ		 1472 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1473 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1474
1475 return ret;
1476}
1477
37126462 1478/* latency must be in 0.1us units. */
23297044 1479static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1480 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1481 uint32_t latency)
1482{
1483 uint32_t ret;
1484
3312ba65
VS		 1485 if (WARN(latency == 0, "Latency value missing\n"))
1486 return UINT_MAX;
1487
801bcfff
PZ		 1488 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1489 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1490 ret = DIV_ROUND_UP(ret, 64) + 2;
1491 return ret;
1492}
1493
23297044 1494static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1495 uint8_t bytes_per_pixel)
1496{
1497 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1498}
1499
2ac96d2a
PB		 1500struct skl_pipe_wm_parameters {
1501 bool active;
1502 uint32_t pipe_htotal;
1503 uint32_t pixel_rate; /* in KHz */
1504 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1505 struct intel_plane_wm_parameters cursor;
1506};
1507
820c1980 1508struct ilk_pipe_wm_parameters {
801bcfff 1509 bool active;
801bcfff
PZ		 1510 uint32_t pipe_htotal;
1511 uint32_t pixel_rate;
c35426d2
VS		 1512 struct intel_plane_wm_parameters pri;
1513 struct intel_plane_wm_parameters spr;
1514 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1515};
1516
820c1980 1517struct ilk_wm_maximums {
cca32e9a
PZ		 1518 uint16_t pri;
1519 uint16_t spr;
1520 uint16_t cur;
1521 uint16_t fbc;
1522};
1523
240264f4
VS		 1524/* used in computing the new watermarks state */
1525struct intel_wm_config {
1526 unsigned int num_pipes_active;
1527 bool sprites_enabled;
1528 bool sprites_scaled;
240264f4
VS		 1529};
1530
37126462
VS		 1531/*
1532 * For both WM_PIPE and WM_LP.
1533 * mem_value must be in 0.1us units.
1534 */
820c1980 1535static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1536 uint32_t mem_value,
1537 bool is_lp)
801bcfff 1538{
cca32e9a
PZ		 1539 uint32_t method1, method2;
1540
c35426d2 1541 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1542 return 0;
1543
23297044 1544 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1545 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1546 mem_value);
1547
1548 if (!is_lp)
1549 return method1;
1550
23297044 1551 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1552 params->pipe_htotal,
c35426d2
VS		 1553 params->pri.horiz_pixels,
1554 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1555 mem_value);
1556
1557 return min(method1, method2);
801bcfff
PZ		 1558}
1559
37126462
VS		 1560/*
1561 * For both WM_PIPE and WM_LP.
1562 * mem_value must be in 0.1us units.
1563 */
820c1980 1564static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1565 uint32_t mem_value)
1566{
1567 uint32_t method1, method2;
1568
c35426d2 1569 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1570 return 0;
1571
23297044 1572 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1573 params->spr.bytes_per_pixel,
801bcfff 1574 mem_value);
23297044 1575 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1576 params->pipe_htotal,
c35426d2
VS		 1577 params->spr.horiz_pixels,
1578 params->spr.bytes_per_pixel,
801bcfff
PZ		 1579 mem_value);
1580 return min(method1, method2);
1581}
1582
37126462
VS		 1583/*
1584 * For both WM_PIPE and WM_LP.
1585 * mem_value must be in 0.1us units.
1586 */
820c1980 1587static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1588 uint32_t mem_value)
1589{
c35426d2 1590 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1591 return 0;
1592
23297044 1593 return ilk_wm_method2(params->pixel_rate,
801bcfff 1594 params->pipe_htotal,
c35426d2
VS		 1595 params->cur.horiz_pixels,
1596 params->cur.bytes_per_pixel,
801bcfff
PZ		 1597 mem_value);
1598}
1599
cca32e9a 1600/* Only for WM_LP. */
820c1980 1601static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1602 uint32_t pri_val)
cca32e9a 1603{
c35426d2 1604 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1605 return 0;
1606
23297044 1607 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1608 params->pri.horiz_pixels,
1609 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1610}
1611
158ae64f
VS		 1612static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1613{
416f4727
VS		 1614 if (INTEL_INFO(dev)->gen >= 8)
1615 return 3072;
1616 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1617 return 768;
1618 else
1619 return 512;
1620}
1621
4e975081
VS		 1622static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1623 int level, bool is_sprite)
1624{
1625 if (INTEL_INFO(dev)->gen >= 8)
1626 /* BDW primary/sprite plane watermarks */
1627 return level == 0 ? 255 : 2047;
1628 else if (INTEL_INFO(dev)->gen >= 7)
1629 /* IVB/HSW primary/sprite plane watermarks */
1630 return level == 0 ? 127 : 1023;
1631 else if (!is_sprite)
1632 /* ILK/SNB primary plane watermarks */
1633 return level == 0 ? 127 : 511;
1634 else
1635 /* ILK/SNB sprite plane watermarks */
1636 return level == 0 ? 63 : 255;
1637}
1638
1639static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1640 int level)
1641{
1642 if (INTEL_INFO(dev)->gen >= 7)
1643 return level == 0 ? 63 : 255;
1644 else
1645 return level == 0 ? 31 : 63;
1646}
1647
1648static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1649{
1650 if (INTEL_INFO(dev)->gen >= 8)
1651 return 31;
1652 else
1653 return 15;
1654}
1655
158ae64f
VS		 1656/* Calculate the maximum primary/sprite plane watermark */
1657static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1658 int level,
240264f4 1659 const struct intel_wm_config *config,
158ae64f
VS		 1660 enum intel_ddb_partitioning ddb_partitioning,
1661 bool is_sprite)
1662{
1663 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1664
1665 /* if sprites aren't enabled, sprites get nothing */
240264f4 1666 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1667 return 0;
1668
1669 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1670 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1671 fifo_size /= INTEL_INFO(dev)->num_pipes;
1672
1673 /*
1674 * For some reason the non self refresh
1675 * FIFO size is only half of the self
1676 * refresh FIFO size on ILK/SNB.
1677 */
1678 if (INTEL_INFO(dev)->gen <= 6)
1679 fifo_size /= 2;
1680 }
1681
240264f4 1682 if (config->sprites_enabled) {
158ae64f
VS		 1683 /* level 0 is always calculated with 1:1 split */
1684 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1685 if (is_sprite)
1686 fifo_size *= 5;
1687 fifo_size /= 6;
1688 } else {
1689 fifo_size /= 2;
1690 }
1691 }
1692
1693 /* clamp to max that the registers can hold */
4e975081 1694 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1695}
1696
1697/* Calculate the maximum cursor plane watermark */
1698static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1699 int level,
1700 const struct intel_wm_config *config)
158ae64f
VS		 1701{
1702 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1703 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1704 return 64;
1705
1706 /* otherwise just report max that registers can hold */
4e975081 1707 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1708}
1709
d34ff9c6 1710static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1711 int level,
1712 const struct intel_wm_config *config,
1713 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1714 struct ilk_wm_maximums *max)
158ae64f 1715{
240264f4
VS		 1716 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1717 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1718 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1719 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1720}
1721
a3cb4048
VS		 1722static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1723 int level,
1724 struct ilk_wm_maximums *max)
1725{
1726 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1727 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1728 max->cur = ilk_cursor_wm_reg_max(dev, level);
1729 max->fbc = ilk_fbc_wm_reg_max(dev);
1730}
1731
d9395655 1732static bool ilk_validate_wm_level(int level,
820c1980 1733 const struct ilk_wm_maximums *max,
d9395655 1734 struct intel_wm_level *result)
a9786a11
VS		 1735{
1736 bool ret;
1737
1738 /* already determined to be invalid? */
1739 if (!result->enable)
1740 return false;
1741
1742 result->enable = result->pri_val <= max->pri &&
1743 result->spr_val <= max->spr &&
1744 result->cur_val <= max->cur;
1745
1746 ret = result->enable;
1747
1748 /*
1749 * HACK until we can pre-compute everything,
1750 * and thus fail gracefully if LP0 watermarks
1751 * are exceeded...
1752 */
1753 if (level == 0 && !result->enable) {
1754 if (result->pri_val > max->pri)
1755 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1756 level, result->pri_val, max->pri);
1757 if (result->spr_val > max->spr)
1758 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1759 level, result->spr_val, max->spr);
1760 if (result->cur_val > max->cur)
1761 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1762 level, result->cur_val, max->cur);
1763
1764 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1765 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1766 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1767 result->enable = true;
1768 }
1769
a9786a11
VS		 1770 return ret;
1771}
1772
d34ff9c6 1773static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1774 int level,
820c1980 1775 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1776 struct intel_wm_level *result)
6f5ddd17
VS		 1777{
1778 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1779 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1780 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1781
1782 /* WM1+ latency values stored in 0.5us units */
1783 if (level > 0) {
1784 pri_latency *= 5;
1785 spr_latency *= 5;
1786 cur_latency *= 5;
1787 }
1788
1789 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1790 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1791 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1792 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1793 result->enable = true;
1794}
1795
801bcfff
PZ		 1796static uint32_t
1797hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1798{
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1801 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1802 u32 linetime, ips_linetime;
1f8eeabf 1803
3ef00284 1804 if (!intel_crtc->active)
801bcfff 1805 return 0;
1011d8c4 1806
1f8eeabf
ED		 1807 /* The WM are computed with base on how long it takes to fill a single
1808 * row at the given clock rate, multiplied by 8.
1809 * */
fec8cba3
JB		 1810 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1811 mode->crtc_clock);
1812 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1813 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1814
801bcfff
PZ		 1815 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1816 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1817}
1818
2af30a5c 1819static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1820{
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822
2af30a5c
PB		 1823 if (IS_GEN9(dev)) {
1824 uint32_t val;
4f947386 1825 int ret, i;
367294be 1826 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1827
1828 /* read the first set of memory latencies[0:3] */
1829 val = 0; /* data0 to be programmed to 0 for first set */
1830 mutex_lock(&dev_priv->rps.hw_lock);
1831 ret = sandybridge_pcode_read(dev_priv,
1832 GEN9_PCODE_READ_MEM_LATENCY,
1833 &val);
1834 mutex_unlock(&dev_priv->rps.hw_lock);
1835
1836 if (ret) {
1837 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1838 return;
1839 }
1840
1841 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1842 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1843 GEN9_MEM_LATENCY_LEVEL_MASK;
1844 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1845 GEN9_MEM_LATENCY_LEVEL_MASK;
1846 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1847 GEN9_MEM_LATENCY_LEVEL_MASK;
1848
1849 /* read the second set of memory latencies[4:7] */
1850 val = 1; /* data0 to be programmed to 1 for second set */
1851 mutex_lock(&dev_priv->rps.hw_lock);
1852 ret = sandybridge_pcode_read(dev_priv,
1853 GEN9_PCODE_READ_MEM_LATENCY,
1854 &val);
1855 mutex_unlock(&dev_priv->rps.hw_lock);
1856 if (ret) {
1857 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1858 return;
1859 }
1860
1861 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1862 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1863 GEN9_MEM_LATENCY_LEVEL_MASK;
1864 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1865 GEN9_MEM_LATENCY_LEVEL_MASK;
1866 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1867 GEN9_MEM_LATENCY_LEVEL_MASK;
1868
367294be 1869 /*
6f97235b
DL		 1870 * WaWmMemoryReadLatency:skl
1871 *
367294be
VK		 1872 * punit doesn't take into account the read latency so we need
1873 * to add 2us to the various latency levels we retrieve from
1874 * the punit.
1875 * - W0 is a bit special in that it's the only level that
1876 * can't be disabled if we want to have display working, so
1877 * we always add 2us there.
1878 * - For levels >=1, punit returns 0us latency when they are
1879 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1880 *
1881 * Additionally, if a level n (n > 1) has a 0us latency, all
1882 * levels m (m >= n) need to be disabled. We make sure to
1883 * sanitize the values out of the punit to satisfy this
1884 * requirement.
367294be
VK		 1885 */
1886 wm[0] += 2;
1887 for (level = 1; level <= max_level; level++)
1888 if (wm[level] != 0)
1889 wm[level] += 2;
4f947386
VK		 1890 else {
1891 for (i = level + 1; i <= max_level; i++)
1892 wm[i] = 0;
367294be 1893
4f947386
VK		 1894 break;
1895 }
2af30a5c 1896 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1897 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1898
1899 wm[0] = (sskpd >> 56) & 0xFF;
1900 if (wm[0] == 0)
1901 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1902 wm[1] = (sskpd >> 4) & 0xFF;
1903 wm[2] = (sskpd >> 12) & 0xFF;
1904 wm[3] = (sskpd >> 20) & 0x1FF;
1905 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1906 } else if (INTEL_INFO(dev)->gen >= 6) {
1907 uint32_t sskpd = I915_READ(MCH_SSKPD);
1908
1909 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1910 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1911 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1912 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1913 } else if (INTEL_INFO(dev)->gen >= 5) {
1914 uint32_t mltr = I915_READ(MLTR_ILK);
1915
1916 /* ILK primary LP0 latency is 700 ns */
1917 wm[0] = 7;
1918 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1919 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1920 }
1921}
1922
53615a5e
VS		 1923static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1924{
1925 /* ILK sprite LP0 latency is 1300 ns */
1926 if (INTEL_INFO(dev)->gen == 5)
1927 wm[0] = 13;
1928}
1929
1930static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1931{
1932 /* ILK cursor LP0 latency is 1300 ns */
1933 if (INTEL_INFO(dev)->gen == 5)
1934 wm[0] = 13;
1935
1936 /* WaDoubleCursorLP3Latency:ivb */
1937 if (IS_IVYBRIDGE(dev))
1938 wm[3] *= 2;
1939}
1940
546c81fd 1941int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1942{
26ec971e 1943 /* how many WM levels are we expecting */
2af30a5c
PB		 1944 if (IS_GEN9(dev))
1945 return 7;
1946 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1947 return 4;
26ec971e 1948 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1949 return 3;
26ec971e 1950 else
ad0d6dc4
VS		 1951 return 2;
1952}
7526ed79 1953
ad0d6dc4
VS		 1954static void intel_print_wm_latency(struct drm_device *dev,
1955 const char *name,
2af30a5c 1956 const uint16_t wm[8])
ad0d6dc4
VS		 1957{
1958 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1959
1960 for (level = 0; level <= max_level; level++) {
1961 unsigned int latency = wm[level];
1962
1963 if (latency == 0) {
1964 DRM_ERROR("%s WM%d latency not provided\n",
1965 name, level);
1966 continue;
1967 }
1968
2af30a5c
PB		 1969 /*
1970 * - latencies are in us on gen9.
1971 * - before then, WM1+ latency values are in 0.5us units
1972 */
1973 if (IS_GEN9(dev))
1974 latency *= 10;
1975 else if (level > 0)
26ec971e
VS		 1976 latency *= 5;
1977
1978 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1979 name, level, wm[level],
1980 latency / 10, latency % 10);
1981 }
1982}
1983
e95a2f75
VS		 1984static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1985 uint16_t wm[5], uint16_t min)
1986{
1987 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1988
1989 if (wm[0] >= min)
1990 return false;
1991
1992 wm[0] = max(wm[0], min);
1993 for (level = 1; level <= max_level; level++)
1994 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1995
1996 return true;
1997}
1998
1999static void snb_wm_latency_quirk(struct drm_device *dev)
2000{
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 bool changed;
2003
2004 /*
2005 * The BIOS provided WM memory latency values are often
2006 * inadequate for high resolution displays. Adjust them.
2007 */
2008 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2009 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2010 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2011
2012 if (!changed)
2013 return;
2014
2015 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2016 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2017 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2018 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2019}
2020
fa50ad61 2021static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2022{
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024
2025 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2026
2027 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2028 sizeof(dev_priv->wm.pri_latency));
2029 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2030 sizeof(dev_priv->wm.pri_latency));
2031
2032 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2033 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2034
2035 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2036 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2037 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2038
2039 if (IS_GEN6(dev))
2040 snb_wm_latency_quirk(dev);
53615a5e
VS		 2041}
2042
2af30a5c
PB		 2043static void skl_setup_wm_latency(struct drm_device *dev)
2044{
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046
2047 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2048 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2049}
2050
820c1980 2051static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2052 struct ilk_pipe_wm_parameters *p)
1011d8c4 2053{
7c4a395f
VS		 2054 struct drm_device *dev = crtc->dev;
2055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2057 struct drm_plane *plane;
1011d8c4 2058
3ef00284 2059 if (!intel_crtc->active)
2a44b76b 2060 return;
801bcfff 2061
2a44b76b 2062 p->active = true;
6e3c9717 2063 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b 2064 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c9f038a1
MR		 2065
2066 if (crtc->primary->state->fb) {
2067 p->pri.enabled = true;
2068 p->pri.bytes_per_pixel =
2069 crtc->primary->state->fb->bits_per_pixel / 8;
2070 } else {
2071 p->pri.enabled = false;
2072 p->pri.bytes_per_pixel = 0;
2073 }
2074
2075 if (crtc->cursor->state->fb) {
2076 p->cur.enabled = true;
2077 p->cur.bytes_per_pixel = 4;
2078 } else {
2079 p->cur.enabled = false;
2080 p->cur.bytes_per_pixel = 0;
2081 }
6e3c9717 2082 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2083 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2084
af2b653b 2085 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2086 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2087
2a44b76b 2088 if (intel_plane->pipe == pipe) {
7c4a395f 2089 p->spr = intel_plane->wm;
2a44b76b
VS		 2090 break;
2091 }
2092 }
2093}
2094
2095static void ilk_compute_wm_config(struct drm_device *dev,
2096 struct intel_wm_config *config)
2097{
2098 struct intel_crtc *intel_crtc;
2099
2100 /* Compute the currently _active_ config */
d3fcc808 2101 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2102 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2103
2a44b76b
VS		 2104 if (!wm->pipe_enabled)
2105 continue;
cca32e9a 2106
2a44b76b
VS		 2107 config->sprites_enabled |= wm->sprites_enabled;
2108 config->sprites_scaled |= wm->sprites_scaled;
2109 config->num_pipes_active++;
cca32e9a 2110 }
801bcfff
PZ		 2111}
2112
0b2ae6d7
VS		 2113/* Compute new watermarks for the pipe */
2114static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2115 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2116 struct intel_pipe_wm *pipe_wm)
2117{
2118 struct drm_device *dev = crtc->dev;
d34ff9c6 2119 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2120 int level, max_level = ilk_wm_max_level(dev);
2121 /* LP0 watermark maximums depend on this pipe alone */
2122 struct intel_wm_config config = {
2123 .num_pipes_active = 1,
2124 .sprites_enabled = params->spr.enabled,
2125 .sprites_scaled = params->spr.scaled,
2126 };
820c1980 2127 struct ilk_wm_maximums max;
0b2ae6d7 2128
2a44b76b
VS		 2129 pipe_wm->pipe_enabled = params->active;
2130 pipe_wm->sprites_enabled = params->spr.enabled;
2131 pipe_wm->sprites_scaled = params->spr.scaled;
2132
7b39a0b7
VS		 2133 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2134 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2135 max_level = 1;
2136
2137 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2138 if (params->spr.scaled)
2139 max_level = 0;
2140
a3cb4048 2141 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2142
a42a5719 2143 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2144 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2145
a3cb4048
VS		 2146 /* LP0 watermarks always use 1/2 DDB partitioning */
2147 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2148
0b2ae6d7 2149 /* At least LP0 must be valid */
a3cb4048
VS		 2150 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2151 return false;
2152
2153 ilk_compute_wm_reg_maximums(dev, 1, &max);
2154
2155 for (level = 1; level <= max_level; level++) {
2156 struct intel_wm_level wm = {};
2157
2158 ilk_compute_wm_level(dev_priv, level, params, &wm);
2159
2160 /*
2161 * Disable any watermark level that exceeds the
2162 * register maximums since such watermarks are
2163 * always invalid.
2164 */
2165 if (!ilk_validate_wm_level(level, &max, &wm))
2166 break;
2167
2168 pipe_wm->wm[level] = wm;
2169 }
2170
2171 return true;
0b2ae6d7
VS		 2172}
2173
2174/*
2175 * Merge the watermarks from all active pipes for a specific level.
2176 */
2177static void ilk_merge_wm_level(struct drm_device *dev,
2178 int level,
2179 struct intel_wm_level *ret_wm)
2180{
2181 const struct intel_crtc *intel_crtc;
2182
d52fea5b
VS		 2183 ret_wm->enable = true;
2184
d3fcc808 2185 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2186 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2187 const struct intel_wm_level *wm = &active->wm[level];
2188
2189 if (!active->pipe_enabled)
2190 continue;
0b2ae6d7 2191
d52fea5b
VS		 2192 /*
2193 * The watermark values may have been used in the past,
2194 * so we must maintain them in the registers for some
2195 * time even if the level is now disabled.
2196 */
0b2ae6d7 2197 if (!wm->enable)
d52fea5b 2198 ret_wm->enable = false;
0b2ae6d7
VS		 2199
2200 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2201 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2202 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2203 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2204 }
0b2ae6d7
VS		 2205}
2206
2207/*
2208 * Merge all low power watermarks for all active pipes.
2209 */
2210static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2211 const struct intel_wm_config *config,
820c1980 2212 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2213 struct intel_pipe_wm *merged)
2214{
2215 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2216 int last_enabled_level = max_level;
0b2ae6d7 2217
0ba22e26
VS		 2218 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2219 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2220 config->num_pipes_active > 1)
2221 return;
2222
6c8b6c28
VS		 2223 /* ILK: FBC WM must be disabled always */
2224 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2225
2226 /* merge each WM1+ level */
2227 for (level = 1; level <= max_level; level++) {
2228 struct intel_wm_level *wm = &merged->wm[level];
2229
2230 ilk_merge_wm_level(dev, level, wm);
2231
d52fea5b
VS		 2232 if (level > last_enabled_level)
2233 wm->enable = false;
2234 else if (!ilk_validate_wm_level(level, max, wm))
2235 /* make sure all following levels get disabled */
2236 last_enabled_level = level - 1;
0b2ae6d7
VS		 2237
2238 /*
2239 * The spec says it is preferred to disable
2240 * FBC WMs instead of disabling a WM level.
2241 */
2242 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2243 if (wm->enable)
2244 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2245 wm->fbc_val = 0;
2246 }
2247 }
6c8b6c28
VS		 2248
2249 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2250 /*
2251 * FIXME this is racy. FBC might get enabled later.
2252 * What we should check here is whether FBC can be
2253 * enabled sometime later.
2254 */
2255 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2256 for (level = 2; level <= max_level; level++) {
2257 struct intel_wm_level *wm = &merged->wm[level];
2258
2259 wm->enable = false;
2260 }
2261 }
0b2ae6d7
VS		 2262}
2263
b380ca3c
VS		 2264static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2265{
2266 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2267 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2268}
2269
a68d68ee
VS		 2270/* The value we need to program into the WM_LPx latency field */
2271static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2272{
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274
a42a5719 2275 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2276 return 2 * level;
2277 else
2278 return dev_priv->wm.pri_latency[level];
2279}
2280
820c1980 2281static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2282 const struct intel_pipe_wm *merged,
609cedef 2283 enum intel_ddb_partitioning partitioning,
820c1980 2284 struct ilk_wm_values *results)
801bcfff 2285{
0b2ae6d7
VS		 2286 struct intel_crtc *intel_crtc;
2287 int level, wm_lp;
cca32e9a 2288
0362c781 2289 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2290 results->partitioning = partitioning;
cca32e9a 2291
0b2ae6d7 2292 /* LP1+ register values */
cca32e9a 2293 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2294 const struct intel_wm_level *r;
801bcfff 2295
b380ca3c 2296 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2297
0362c781 2298 r = &merged->wm[level];
cca32e9a 2299
d52fea5b
VS		 2300 /*
2301 * Maintain the watermark values even if the level is
2302 * disabled. Doing otherwise could cause underruns.
2303 */
2304 results->wm_lp[wm_lp - 1] =
a68d68ee 2305 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2306 (r->pri_val << WM1_LP_SR_SHIFT) |
2307 r->cur_val;
2308
d52fea5b
VS		 2309 if (r->enable)
2310 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2311
416f4727
VS		 2312 if (INTEL_INFO(dev)->gen >= 8)
2313 results->wm_lp[wm_lp - 1] |=
2314 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2315 else
2316 results->wm_lp[wm_lp - 1] |=
2317 r->fbc_val << WM1_LP_FBC_SHIFT;
2318
d52fea5b
VS		 2319 /*
2320 * Always set WM1S_LP_EN when spr_val != 0, even if the
2321 * level is disabled. Doing otherwise could cause underruns.
2322 */
6cef2b8a
VS		 2323 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2324 WARN_ON(wm_lp != 1);
2325 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2326 } else
2327 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2328 }
801bcfff 2329
0b2ae6d7 2330 /* LP0 register values */
d3fcc808 2331 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2332 enum pipe pipe = intel_crtc->pipe;
2333 const struct intel_wm_level *r =
2334 &intel_crtc->wm.active.wm[0];
2335
2336 if (WARN_ON(!r->enable))
2337 continue;
2338
2339 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2340
0b2ae6d7
VS		 2341 results->wm_pipe[pipe] =
2342 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2343 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2344 r->cur_val;
801bcfff
PZ		 2345 }
2346}
2347
861f3389
PZ		 2348/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2349 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2350static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2351 struct intel_pipe_wm *r1,
2352 struct intel_pipe_wm *r2)
861f3389 2353{
198a1e9b
VS		 2354 int level, max_level = ilk_wm_max_level(dev);
2355 int level1 = 0, level2 = 0;
861f3389 2356
198a1e9b
VS		 2357 for (level = 1; level <= max_level; level++) {
2358 if (r1->wm[level].enable)
2359 level1 = level;
2360 if (r2->wm[level].enable)
2361 level2 = level;
861f3389
PZ		 2362 }
2363
198a1e9b
VS		 2364 if (level1 == level2) {
2365 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2366 return r2;
2367 else
2368 return r1;
198a1e9b 2369 } else if (level1 > level2) {
861f3389
PZ		 2370 return r1;
2371 } else {
2372 return r2;
2373 }
2374}
2375
49a687c4
VS		 2376/* dirty bits used to track which watermarks need changes */
2377#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2378#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2379#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2380#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2381#define WM_DIRTY_FBC (1 << 24)
2382#define WM_DIRTY_DDB (1 << 25)
2383
055e393f 2384static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2385 const struct ilk_wm_values *old,
2386 const struct ilk_wm_values *new)
49a687c4
VS		 2387{
2388 unsigned int dirty = 0;
2389 enum pipe pipe;
2390 int wm_lp;
2391
055e393f 2392 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2393 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2394 dirty |= WM_DIRTY_LINETIME(pipe);
2395 /* Must disable LP1+ watermarks too */
2396 dirty |= WM_DIRTY_LP_ALL;
2397 }
2398
2399 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2400 dirty |= WM_DIRTY_PIPE(pipe);
2401 /* Must disable LP1+ watermarks too */
2402 dirty |= WM_DIRTY_LP_ALL;
2403 }
2404 }
2405
2406 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2407 dirty |= WM_DIRTY_FBC;
2408 /* Must disable LP1+ watermarks too */
2409 dirty |= WM_DIRTY_LP_ALL;
2410 }
2411
2412 if (old->partitioning != new->partitioning) {
2413 dirty |= WM_DIRTY_DDB;
2414 /* Must disable LP1+ watermarks too */
2415 dirty |= WM_DIRTY_LP_ALL;
2416 }
2417
2418 /* LP1+ watermarks already deemed dirty, no need to continue */
2419 if (dirty & WM_DIRTY_LP_ALL)
2420 return dirty;
2421
2422 /* Find the lowest numbered LP1+ watermark in need of an update... */
2423 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2424 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2425 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2426 break;
2427 }
2428
2429 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2430 for (; wm_lp <= 3; wm_lp++)
2431 dirty |= WM_DIRTY_LP(wm_lp);
2432
2433 return dirty;
2434}
2435
8553c18e
VS		 2436static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2437 unsigned int dirty)
801bcfff 2438{
820c1980 2439 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2440 bool changed = false;
801bcfff 2441
facd619b
VS		 2442 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2443 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2444 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2445 changed = true;
facd619b
VS		 2446 }
2447 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2448 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2449 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2450 changed = true;
facd619b
VS		 2451 }
2452 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2453 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2454 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2455 changed = true;
facd619b 2456 }
801bcfff 2457
facd619b
VS		 2458 /*
2459 * Don't touch WM1S_LP_EN here.
2460 * Doing so could cause underruns.
2461 */
6cef2b8a 2462
8553c18e
VS		 2463 return changed;
2464}
2465
2466/*
2467 * The spec says we shouldn't write when we don't need, because every write
2468 * causes WMs to be re-evaluated, expending some power.
2469 */
820c1980
ID		 2470static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2471 struct ilk_wm_values *results)
8553c18e
VS		 2472{
2473 struct drm_device *dev = dev_priv->dev;
820c1980 2474 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2475 unsigned int dirty;
2476 uint32_t val;
2477
055e393f 2478 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2479 if (!dirty)
2480 return;
2481
2482 _ilk_disable_lp_wm(dev_priv, dirty);
2483
49a687c4 2484 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2485 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2486 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2487 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2488 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2489 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2490
49a687c4 2491 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2492 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2493 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2494 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2495 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2496 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2497
49a687c4 2498 if (dirty & WM_DIRTY_DDB) {
a42a5719 2499 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2500 val = I915_READ(WM_MISC);
2501 if (results->partitioning == INTEL_DDB_PART_1_2)
2502 val &= ~WM_MISC_DATA_PARTITION_5_6;
2503 else
2504 val |= WM_MISC_DATA_PARTITION_5_6;
2505 I915_WRITE(WM_MISC, val);
2506 } else {
2507 val = I915_READ(DISP_ARB_CTL2);
2508 if (results->partitioning == INTEL_DDB_PART_1_2)
2509 val &= ~DISP_DATA_PARTITION_5_6;
2510 else
2511 val |= DISP_DATA_PARTITION_5_6;
2512 I915_WRITE(DISP_ARB_CTL2, val);
2513 }
1011d8c4
PZ		 2514 }
2515
49a687c4 2516 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2517 val = I915_READ(DISP_ARB_CTL);
2518 if (results->enable_fbc_wm)
2519 val &= ~DISP_FBC_WM_DIS;
2520 else
2521 val |= DISP_FBC_WM_DIS;
2522 I915_WRITE(DISP_ARB_CTL, val);
2523 }
2524
954911eb
ID		 2525 if (dirty & WM_DIRTY_LP(1) &&
2526 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2527 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2528
2529 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2530 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2531 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2532 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2533 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2534 }
801bcfff 2535
facd619b 2536 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2537 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2538 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2539 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2540 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2541 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2542
2543 dev_priv->wm.hw = *results;
801bcfff
PZ		 2544}
2545
8553c18e
VS		 2546static bool ilk_disable_lp_wm(struct drm_device *dev)
2547{
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549
2550 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2551}
2552
b9cec075
DL		 2553/*
2554 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2555 * different active planes.
2556 */
2557
2558#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2559#define BXT_DDB_SIZE 512
b9cec075
DL		 2560
2561static void
2562skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2563 struct drm_crtc *for_crtc,
2564 const struct intel_wm_config *config,
2565 const struct skl_pipe_wm_parameters *params,
2566 struct skl_ddb_entry *alloc /* out */)
2567{
2568 struct drm_crtc *crtc;
2569 unsigned int pipe_size, ddb_size;
2570 int nth_active_pipe;
2571
2572 if (!params->active) {
2573 alloc->start = 0;
2574 alloc->end = 0;
2575 return;
2576 }
2577
43d735a6
DL		 2578 if (IS_BROXTON(dev))
2579 ddb_size = BXT_DDB_SIZE;
2580 else
2581 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2582
2583 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2584
2585 nth_active_pipe = 0;
2586 for_each_crtc(dev, crtc) {
3ef00284 2587 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2588 continue;
2589
2590 if (crtc == for_crtc)
2591 break;
2592
2593 nth_active_pipe++;
2594 }
2595
2596 pipe_size = ddb_size / config->num_pipes_active;
2597 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2598 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2599}
2600
2601static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2602{
2603 if (config->num_pipes_active == 1)
2604 return 32;
2605
2606 return 8;
2607}
2608
a269c583
DL		 2609static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2610{
2611 entry->start = reg & 0x3ff;
2612 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2613 if (entry->end)
2614 entry->end += 1;
a269c583
DL		 2615}
2616
08db6652
DL		 2617void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2618 struct skl_ddb_allocation *ddb /* out */)
a269c583 2619{
a269c583
DL		 2620 enum pipe pipe;
2621 int plane;
2622 u32 val;
2623
2624 for_each_pipe(dev_priv, pipe) {
dd740780 2625 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2626 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2627 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2628 val);
2629 }
2630
2631 val = I915_READ(CUR_BUF_CFG(pipe));
2632 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2633 }
2634}
2635
b9cec075
DL		 2636static unsigned int
2637skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2638{
2639 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2640}
2641
2642/*
2643 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2644 * a 8192x4096@32bpp framebuffer:
2645 * 3 * 4096 * 8192 * 4 < 2^32
2646 */
2647static unsigned int
2648skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2649 const struct skl_pipe_wm_parameters *params)
2650{
2651 unsigned int total_data_rate = 0;
2652 int plane;
2653
2654 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2655 const struct intel_plane_wm_parameters *p;
2656
2657 p = &params->plane[plane];
2658 if (!p->enabled)
2659 continue;
2660
2661 total_data_rate += skl_plane_relative_data_rate(p);
2662 }
2663
2664 return total_data_rate;
2665}
2666
2667static void
2668skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2669 const struct intel_wm_config *config,
2670 const struct skl_pipe_wm_parameters *params,
2671 struct skl_ddb_allocation *ddb /* out */)
2672{
2673 struct drm_device *dev = crtc->dev;
dd740780 2674 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2676 enum pipe pipe = intel_crtc->pipe;
34bb56af 2677 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2678 uint16_t alloc_size, start, cursor_blocks;
80958155 2679 uint16_t minimum[I915_MAX_PLANES];
b9cec075
DL		 2680 unsigned int total_data_rate;
2681 int plane;
2682
34bb56af
DL		 2683 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2684 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2685 if (alloc_size == 0) {
2686 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2687 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2688 return;
2689 }
2690
2691 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2692 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2693 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2694
2695 alloc_size -= cursor_blocks;
34bb56af 2696 alloc->end -= cursor_blocks;
b9cec075 2697
80958155 2698 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2699 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2700 const struct intel_plane_wm_parameters *p;
2701
2702 p = &params->plane[plane];
2703 if (!p->enabled)
2704 continue;
2705
2706 minimum[plane] = 8;
2707 alloc_size -= minimum[plane];
2708 }
2709
b9cec075 2710 /*
80958155
DL		 2711 * 2. Distribute the remaining space in proportion to the amount of
2712 * data each plane needs to fetch from memory.
b9cec075
DL		 2713 *
2714 * FIXME: we may not allocate every single block here.
2715 */
2716 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2717
34bb56af 2718 start = alloc->start;
b9cec075
DL		 2719 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2720 const struct intel_plane_wm_parameters *p;
2721 unsigned int data_rate;
2722 uint16_t plane_blocks;
2723
2724 p = &params->plane[plane];
2725 if (!p->enabled)
2726 continue;
2727
2728 data_rate = skl_plane_relative_data_rate(p);
2729
2730 /*
2731 * promote the expression to 64 bits to avoid overflowing, the
2732 * result is < available as data_rate / total_data_rate < 1
2733 */
80958155
DL		 2734 plane_blocks = minimum[plane];
2735 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2736 total_data_rate);
b9cec075
DL		 2737
2738 ddb->plane[pipe][plane].start = start;
16160e3d 2739 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2740
2741 start += plane_blocks;
2742 }
2743
2744}
2745
5cec258b 2746static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2747{
2748 /* TODO: Take into account the scalers once we support them */
2d112de7 2749 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2750}
2751
2752/*
2753 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2754 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2755 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2756 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2757*/
2758static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2759 uint32_t latency)
2760{
2761 uint32_t wm_intermediate_val, ret;
2762
2763 if (latency == 0)
2764 return UINT_MAX;
2765
d4c2aa60 2766 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 2767 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2768
2769 return ret;
2770}
2771
2772static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2773 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2774 uint64_t tiling, uint32_t latency)
2d41c0b5 2775{
d4c2aa60
TU		 2776 uint32_t ret;
2777 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2778 uint32_t wm_intermediate_val;
2d41c0b5
PB		 2779
2780 if (latency == 0)
2781 return UINT_MAX;
2782
2783 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 2784
2785 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2786 tiling == I915_FORMAT_MOD_Yf_TILED) {
2787 plane_bytes_per_line *= 4;
2788 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2789 plane_blocks_per_line /= 4;
2790 } else {
2791 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2792 }
2793
2d41c0b5
PB		 2794 wm_intermediate_val = latency * pixel_rate;
2795 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2796 plane_blocks_per_line;
2d41c0b5
PB		 2797
2798 return ret;
2799}
2800
2d41c0b5
PB		 2801static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2802 const struct intel_crtc *intel_crtc)
2803{
2804 struct drm_device *dev = intel_crtc->base.dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2807 enum pipe pipe = intel_crtc->pipe;
2808
2809 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2810 sizeof(new_ddb->plane[pipe])))
2811 return true;
2812
2813 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2814 sizeof(new_ddb->cursor[pipe])))
2815 return true;
2816
2817 return false;
2818}
2819
2820static void skl_compute_wm_global_parameters(struct drm_device *dev,
2821 struct intel_wm_config *config)
2822{
2823 struct drm_crtc *crtc;
2824 struct drm_plane *plane;
2825
2826 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2827 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 2828
2829 /* FIXME: I don't think we need those two global parameters on SKL */
2830 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2831 struct intel_plane *intel_plane = to_intel_plane(plane);
2832
2833 config->sprites_enabled |= intel_plane->wm.enabled;
2834 config->sprites_scaled |= intel_plane->wm.scaled;
2835 }
2836}
2837
2838static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2839 struct skl_pipe_wm_parameters *p)
2840{
2841 struct drm_device *dev = crtc->dev;
2842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2843 enum pipe pipe = intel_crtc->pipe;
2844 struct drm_plane *plane;
0fda6568 2845 struct drm_framebuffer *fb;
2d41c0b5
PB		 2846 int i = 1; /* Index for sprite planes start */
2847
3ef00284 2848 p->active = intel_crtc->active;
2d41c0b5 2849 if (p->active) {
6e3c9717
ACO		 2850 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2851 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 2852
0fda6568 2853 fb = crtc->primary->state->fb;
c9f038a1
MR		 2854 if (fb) {
2855 p->plane[0].enabled = true;
2856 p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;
0fda6568 2857 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 2858 } else {
2859 p->plane[0].enabled = false;
2860 p->plane[0].bytes_per_pixel = 0;
2861 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2862 }
2863 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2864 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 2865 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 2866
c9f038a1
MR		 2867 fb = crtc->cursor->state->fb;
2868 if (fb) {
2869 p->cursor.enabled = true;
2870 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2871 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2872 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2873 } else {
2874 p->cursor.enabled = false;
2875 p->cursor.bytes_per_pixel = 0;
2876 p->cursor.horiz_pixels = 64;
2877 p->cursor.vert_pixels = 64;
2878 }
2d41c0b5
PB		 2879 }
2880
2881 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2882 struct intel_plane *intel_plane = to_intel_plane(plane);
2883
a712f8eb
SJ		 2884 if (intel_plane->pipe == pipe &&
2885 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2886 p->plane[i++] = intel_plane->wm;
2887 }
2888}
2889
d4c2aa60
TU		 2890static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2891 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2892 struct intel_plane_wm_parameters *p_params,
2893 uint16_t ddb_allocation,
d4c2aa60 2894 int level,
afb024aa
DL		 2895 uint16_t *out_blocks, /* out */
2896 uint8_t *out_lines /* out */)
2d41c0b5 2897{
d4c2aa60
TU		 2898 uint32_t latency = dev_priv->wm.skl_latency[level];
2899 uint32_t method1, method2;
2900 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2901 uint32_t res_blocks, res_lines;
2902 uint32_t selected_result;
2d41c0b5 2903
d4c2aa60 2904 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2905 return false;
2906
2907 method1 = skl_wm_method1(p->pixel_rate,
2908 p_params->bytes_per_pixel,
d4c2aa60 2909 latency);
2d41c0b5
PB		 2910 method2 = skl_wm_method2(p->pixel_rate,
2911 p->pipe_htotal,
2912 p_params->horiz_pixels,
2913 p_params->bytes_per_pixel,
0fda6568 2914 p_params->tiling,
d4c2aa60 2915 latency);
2d41c0b5
PB		 2916
2917 plane_bytes_per_line = p_params->horiz_pixels *
2918 p_params->bytes_per_pixel;
d4c2aa60 2919 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2920
0fda6568
TU		 2921 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2922 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 2923 uint32_t min_scanlines = 4;
2924 uint32_t y_tile_minimum;
2925 if (intel_rotation_90_or_270(p_params->rotation)) {
2926 switch (p_params->bytes_per_pixel) {
2927 case 1:
2928 min_scanlines = 16;
2929 break;
2930 case 2:
2931 min_scanlines = 8;
2932 break;
2933 case 8:
2934 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 2935 }
1fc0a8f7
TU		 2936 }
2937 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 2938 selected_result = max(method2, y_tile_minimum);
2939 } else {
2940 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2941 selected_result = min(method1, method2);
2942 else
2943 selected_result = method1;
2944 }
2d41c0b5 2945
d4c2aa60
TU		 2946 res_blocks = selected_result + 1;
2947 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2948
0fda6568
TU		 2949 if (level >= 1 && level <= 7) {
2950 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2951 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2952 res_lines += 4;
2953 else
2954 res_blocks++;
2955 }
e6d66171 2956
d4c2aa60 2957 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 2958 return false;
2959
2960 *out_blocks = res_blocks;
2961 *out_lines = res_lines;
2d41c0b5
PB		 2962
2963 return true;
2964}
2965
2966static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2967 struct skl_ddb_allocation *ddb,
2968 struct skl_pipe_wm_parameters *p,
2969 enum pipe pipe,
2970 int level,
2971 int num_planes,
2972 struct skl_wm_level *result)
2973{
2d41c0b5
PB		 2974 uint16_t ddb_blocks;
2975 int i;
2976
2977 for (i = 0; i < num_planes; i++) {
2978 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2979
d4c2aa60
TU		 2980 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2981 p, &p->plane[i],
2d41c0b5 2982 ddb_blocks,
d4c2aa60 2983 level,
2d41c0b5
PB		 2984 &result->plane_res_b[i],
2985 &result->plane_res_l[i]);
2986 }
2987
2988 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 2989 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2990 ddb_blocks, level,
2991 &result->cursor_res_b,
2d41c0b5
PB		 2992 &result->cursor_res_l);
2993}
2994
407b50f3
DL		 2995static uint32_t
2996skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2997{
3ef00284 2998 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 2999 return 0;
3000
3001 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3002
3003}
3004
3005static void skl_compute_transition_wm(struct drm_crtc *crtc,
3006 struct skl_pipe_wm_parameters *params,
9414f563 3007 struct skl_wm_level *trans_wm /* out */)
407b50f3 3008{
9414f563
DL		 3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010 int i;
3011
407b50f3
DL		 3012 if (!params->active)
3013 return;
9414f563
DL		 3014
3015 /* Until we know more, just disable transition WMs */
3016 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3017 trans_wm->plane_en[i] = false;
3018 trans_wm->cursor_en = false;
407b50f3
DL		 3019}
3020
2d41c0b5
PB		 3021static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3022 struct skl_ddb_allocation *ddb,
3023 struct skl_pipe_wm_parameters *params,
3024 struct skl_pipe_wm *pipe_wm)
3025{
3026 struct drm_device *dev = crtc->dev;
3027 const struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int level, max_level = ilk_wm_max_level(dev);
3030
3031 for (level = 0; level <= max_level; level++) {
3032 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3033 level, intel_num_planes(intel_crtc),
3034 &pipe_wm->wm[level]);
3035 }
3036 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3037
9414f563 3038 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3039}
3040
3041static void skl_compute_wm_results(struct drm_device *dev,
3042 struct skl_pipe_wm_parameters *p,
3043 struct skl_pipe_wm *p_wm,
3044 struct skl_wm_values *r,
3045 struct intel_crtc *intel_crtc)
3046{
3047 int level, max_level = ilk_wm_max_level(dev);
3048 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3049 uint32_t temp;
3050 int i;
2d41c0b5
PB		 3051
3052 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3053 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3054 temp = 0;
2d41c0b5
PB		 3055
3056 temp |= p_wm->wm[level].plane_res_l[i] <<
3057 PLANE_WM_LINES_SHIFT;
3058 temp |= p_wm->wm[level].plane_res_b[i];
3059 if (p_wm->wm[level].plane_en[i])
3060 temp |= PLANE_WM_EN;
3061
3062 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3063 }
3064
3065 temp = 0;
2d41c0b5
PB		 3066
3067 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3068 temp |= p_wm->wm[level].cursor_res_b;
3069
3070 if (p_wm->wm[level].cursor_en)
3071 temp |= PLANE_WM_EN;
3072
3073 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3074
3075 }
3076
9414f563
DL		 3077 /* transition WMs */
3078 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3079 temp = 0;
3080 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3081 temp |= p_wm->trans_wm.plane_res_b[i];
3082 if (p_wm->trans_wm.plane_en[i])
3083 temp |= PLANE_WM_EN;
3084
3085 r->plane_trans[pipe][i] = temp;
3086 }
3087
3088 temp = 0;
3089 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3090 temp |= p_wm->trans_wm.cursor_res_b;
3091 if (p_wm->trans_wm.cursor_en)
3092 temp |= PLANE_WM_EN;
3093
3094 r->cursor_trans[pipe] = temp;
3095
2d41c0b5
PB		 3096 r->wm_linetime[pipe] = p_wm->linetime;
3097}
3098
16160e3d
DL		 3099static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3100 const struct skl_ddb_entry *entry)
3101{
3102 if (entry->end)
3103 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3104 else
3105 I915_WRITE(reg, 0);
3106}
3107
2d41c0b5
PB		 3108static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3109 const struct skl_wm_values *new)
3110{
3111 struct drm_device *dev = dev_priv->dev;
3112 struct intel_crtc *crtc;
3113
3114 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3115 int i, level, max_level = ilk_wm_max_level(dev);
3116 enum pipe pipe = crtc->pipe;
3117
5d374d96
DL		 3118 if (!new->dirty[pipe])
3119 continue;
8211bd5b 3120
5d374d96 3121 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3122
5d374d96
DL		 3123 for (level = 0; level <= max_level; level++) {
3124 for (i = 0; i < intel_num_planes(crtc); i++)
3125 I915_WRITE(PLANE_WM(pipe, i, level),
3126 new->plane[pipe][i][level]);
3127 I915_WRITE(CUR_WM(pipe, level),
3128 new->cursor[pipe][level]);
2d41c0b5 3129 }
5d374d96
DL		 3130 for (i = 0; i < intel_num_planes(crtc); i++)
3131 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3132 new->plane_trans[pipe][i]);
3133 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3134
3135 for (i = 0; i < intel_num_planes(crtc); i++)
3136 skl_ddb_entry_write(dev_priv,
3137 PLANE_BUF_CFG(pipe, i),
3138 &new->ddb.plane[pipe][i]);
3139
3140 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3141 &new->ddb.cursor[pipe]);
2d41c0b5 3142 }
2d41c0b5
PB		 3143}
3144
0e8fb7ba
DL		 3145/*
3146 * When setting up a new DDB allocation arrangement, we need to correctly
3147 * sequence the times at which the new allocations for the pipes are taken into
3148 * account or we'll have pipes fetching from space previously allocated to
3149 * another pipe.
3150 *
3151 * Roughly the sequence looks like:
3152 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3153 * overlapping with a previous light-up pipe (another way to put it is:
3154 * pipes with their new allocation strickly included into their old ones).
3155 * 2. re-allocate the other pipes that get their allocation reduced
3156 * 3. allocate the pipes having their allocation increased
3157 *
3158 * Steps 1. and 2. are here to take care of the following case:
3159 * - Initially DDB looks like this:
3160 * | B | C |
3161 * - enable pipe A.
3162 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3163 * allocation
3164 * | A | B | C |
3165 *
3166 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3167 */
3168
d21b795c
DL		 3169static void
3170skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3171{
0e8fb7ba
DL		 3172 int plane;
3173
d21b795c
DL		 3174 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3175
dd740780 3176 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3177 I915_WRITE(PLANE_SURF(pipe, plane),
3178 I915_READ(PLANE_SURF(pipe, plane)));
3179 }
3180 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3181}
3182
3183static bool
3184skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3185 const struct skl_ddb_allocation *new,
3186 enum pipe pipe)
3187{
3188 uint16_t old_size, new_size;
3189
3190 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3191 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3192
3193 return old_size != new_size &&
3194 new->pipe[pipe].start >= old->pipe[pipe].start &&
3195 new->pipe[pipe].end <= old->pipe[pipe].end;
3196}
3197
3198static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3199 struct skl_wm_values *new_values)
3200{
3201 struct drm_device *dev = dev_priv->dev;
3202 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3203 bool reallocated[I915_MAX_PIPES] = {false, false, false};
3204 struct intel_crtc *crtc;
3205 enum pipe pipe;
3206
3207 new_ddb = &new_values->ddb;
3208 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3209
3210 /*
3211 * First pass: flush the pipes with the new allocation contained into
3212 * the old space.
3213 *
3214 * We'll wait for the vblank on those pipes to ensure we can safely
3215 * re-allocate the freed space without this pipe fetching from it.
3216 */
3217 for_each_intel_crtc(dev, crtc) {
3218 if (!crtc->active)
3219 continue;
3220
3221 pipe = crtc->pipe;
3222
3223 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3224 continue;
3225
d21b795c 3226 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3227 intel_wait_for_vblank(dev, pipe);
3228
3229 reallocated[pipe] = true;
3230 }
3231
3232
3233 /*
3234 * Second pass: flush the pipes that are having their allocation
3235 * reduced, but overlapping with a previous allocation.
3236 *
3237 * Here as well we need to wait for the vblank to make sure the freed
3238 * space is not used anymore.
3239 */
3240 for_each_intel_crtc(dev, crtc) {
3241 if (!crtc->active)
3242 continue;
3243
3244 pipe = crtc->pipe;
3245
3246 if (reallocated[pipe])
3247 continue;
3248
3249 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3250 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3251 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3252 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3253 reallocated[pipe] = true;
0e8fb7ba 3254 }
0e8fb7ba
DL		 3255 }
3256
3257 /*
3258 * Third pass: flush the pipes that got more space allocated.
3259 *
3260 * We don't need to actively wait for the update here, next vblank
3261 * will just get more DDB space with the correct WM values.
3262 */
3263 for_each_intel_crtc(dev, crtc) {
3264 if (!crtc->active)
3265 continue;
3266
3267 pipe = crtc->pipe;
3268
3269 /*
3270 * At this point, only the pipes more space than before are
3271 * left to re-allocate.
3272 */
3273 if (reallocated[pipe])
3274 continue;
3275
d21b795c 3276 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3277 }
3278}
3279
2d41c0b5
PB		 3280static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3281 struct skl_pipe_wm_parameters *params,
3282 struct intel_wm_config *config,
3283 struct skl_ddb_allocation *ddb, /* out */
3284 struct skl_pipe_wm *pipe_wm /* out */)
3285{
3286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287
3288 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3289 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3290 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3291
3292 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3293 return false;
3294
3295 intel_crtc->wm.skl_active = *pipe_wm;
3296 return true;
3297}
3298
3299static void skl_update_other_pipe_wm(struct drm_device *dev,
3300 struct drm_crtc *crtc,
3301 struct intel_wm_config *config,
3302 struct skl_wm_values *r)
3303{
3304 struct intel_crtc *intel_crtc;
3305 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3306
3307 /*
3308 * If the WM update hasn't changed the allocation for this_crtc (the
3309 * crtc we are currently computing the new WM values for), other
3310 * enabled crtcs will keep the same allocation and we don't need to
3311 * recompute anything for them.
3312 */
3313 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3314 return;
3315
3316 /*
3317 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3318 * other active pipes need new DDB allocation and WM values.
3319 */
3320 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3321 base.head) {
3322 struct skl_pipe_wm_parameters params = {};
3323 struct skl_pipe_wm pipe_wm = {};
3324 bool wm_changed;
3325
3326 if (this_crtc->pipe == intel_crtc->pipe)
3327 continue;
3328
3329 if (!intel_crtc->active)
3330 continue;
3331
3332 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3333 &params, config,
3334 &r->ddb, &pipe_wm);
3335
3336 /*
3337 * If we end up re-computing the other pipe WM values, it's
3338 * because it was really needed, so we expect the WM values to
3339 * be different.
3340 */
3341 WARN_ON(!wm_changed);
3342
3343 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3344 r->dirty[intel_crtc->pipe] = true;
3345 }
3346}
3347
3348static void skl_update_wm(struct drm_crtc *crtc)
3349{
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct skl_pipe_wm_parameters params = {};
3354 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3355 struct skl_pipe_wm pipe_wm = {};
3356 struct intel_wm_config config = {};
3357
3358 memset(results, 0, sizeof(*results));
3359
3360 skl_compute_wm_global_parameters(dev, &config);
3361
3362 if (!skl_update_pipe_wm(crtc, &params, &config,
3363 &results->ddb, &pipe_wm))
3364 return;
3365
3366 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3367 results->dirty[intel_crtc->pipe] = true;
3368
3369 skl_update_other_pipe_wm(dev, crtc, &config, results);
3370 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3371 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3372
3373 /* store the new configuration */
3374 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3375}
3376
3377static void
3378skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3379 uint32_t sprite_width, uint32_t sprite_height,
3380 int pixel_size, bool enabled, bool scaled)
3381{
3382 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3383 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3384
3385 intel_plane->wm.enabled = enabled;
3386 intel_plane->wm.scaled = scaled;
3387 intel_plane->wm.horiz_pixels = sprite_width;
3388 intel_plane->wm.vert_pixels = sprite_height;
3389 intel_plane->wm.bytes_per_pixel = pixel_size;
0fda6568
TU		 3390 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3391 /*
3392 * Framebuffer can be NULL on plane disable, but it does not
3393 * matter for watermarks if we assume no tiling in that case.
3394 */
3395 if (fb)
3396 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3397 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3398
3399 skl_update_wm(crtc);
3400}
3401
820c1980 3402static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3403{
7c4a395f 3404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3405 struct drm_device *dev = crtc->dev;
801bcfff 3406 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3407 struct ilk_wm_maximums max;
3408 struct ilk_pipe_wm_parameters params = {};
3409 struct ilk_wm_values results = {};
77c122bc 3410 enum intel_ddb_partitioning partitioning;
7c4a395f 3411 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3412 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3413 struct intel_wm_config config = {};
7c4a395f 3414
2a44b76b 3415 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3416
3417 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3418
3419 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3420 return;
861f3389 3421
7c4a395f 3422 intel_crtc->wm.active = pipe_wm;
861f3389 3423
2a44b76b
VS		 3424 ilk_compute_wm_config(dev, &config);
3425
34982fe1 3426 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3427 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3428
3429 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3430 if (INTEL_INFO(dev)->gen >= 7 &&
3431 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3432 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3433 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3434
820c1980 3435 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3436 } else {
198a1e9b 3437 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3438 }
3439
198a1e9b 3440 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3441 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3442
820c1980 3443 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3444
820c1980 3445 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3446}
3447
ed57cb8a
DL		 3448static void
3449ilk_update_sprite_wm(struct drm_plane *plane,
3450 struct drm_crtc *crtc,
3451 uint32_t sprite_width, uint32_t sprite_height,
3452 int pixel_size, bool enabled, bool scaled)
526682e9 3453{
8553c18e 3454 struct drm_device *dev = plane->dev;
adf3d35e 3455 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3456
adf3d35e
VS		 3457 intel_plane->wm.enabled = enabled;
3458 intel_plane->wm.scaled = scaled;
3459 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3460 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3461 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3462
8553c18e
VS		 3463 /*
3464 * IVB workaround: must disable low power watermarks for at least
3465 * one frame before enabling scaling. LP watermarks can be re-enabled
3466 * when scaling is disabled.
3467 *
3468 * WaCxSRDisabledForSpriteScaling:ivb
3469 */
3470 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3471 intel_wait_for_vblank(dev, intel_plane->pipe);
3472
820c1980 3473 ilk_update_wm(crtc);
526682e9
PZ		 3474}
3475
3078999f
PB		 3476static void skl_pipe_wm_active_state(uint32_t val,
3477 struct skl_pipe_wm *active,
3478 bool is_transwm,
3479 bool is_cursor,
3480 int i,
3481 int level)
3482{
3483 bool is_enabled = (val & PLANE_WM_EN) != 0;
3484
3485 if (!is_transwm) {
3486 if (!is_cursor) {
3487 active->wm[level].plane_en[i] = is_enabled;
3488 active->wm[level].plane_res_b[i] =
3489 val & PLANE_WM_BLOCKS_MASK;
3490 active->wm[level].plane_res_l[i] =
3491 (val >> PLANE_WM_LINES_SHIFT) &
3492 PLANE_WM_LINES_MASK;
3493 } else {
3494 active->wm[level].cursor_en = is_enabled;
3495 active->wm[level].cursor_res_b =
3496 val & PLANE_WM_BLOCKS_MASK;
3497 active->wm[level].cursor_res_l =
3498 (val >> PLANE_WM_LINES_SHIFT) &
3499 PLANE_WM_LINES_MASK;
3500 }
3501 } else {
3502 if (!is_cursor) {
3503 active->trans_wm.plane_en[i] = is_enabled;
3504 active->trans_wm.plane_res_b[i] =
3505 val & PLANE_WM_BLOCKS_MASK;
3506 active->trans_wm.plane_res_l[i] =
3507 (val >> PLANE_WM_LINES_SHIFT) &
3508 PLANE_WM_LINES_MASK;
3509 } else {
3510 active->trans_wm.cursor_en = is_enabled;
3511 active->trans_wm.cursor_res_b =
3512 val & PLANE_WM_BLOCKS_MASK;
3513 active->trans_wm.cursor_res_l =
3514 (val >> PLANE_WM_LINES_SHIFT) &
3515 PLANE_WM_LINES_MASK;
3516 }
3517 }
3518}
3519
3520static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3521{
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3527 enum pipe pipe = intel_crtc->pipe;
3528 int level, i, max_level;
3529 uint32_t temp;
3530
3531 max_level = ilk_wm_max_level(dev);
3532
3533 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3534
3535 for (level = 0; level <= max_level; level++) {
3536 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3537 hw->plane[pipe][i][level] =
3538 I915_READ(PLANE_WM(pipe, i, level));
3539 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3540 }
3541
3542 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3543 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3544 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3545
3ef00284 3546 if (!intel_crtc->active)
3078999f
PB		 3547 return;
3548
3549 hw->dirty[pipe] = true;
3550
3551 active->linetime = hw->wm_linetime[pipe];
3552
3553 for (level = 0; level <= max_level; level++) {
3554 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3555 temp = hw->plane[pipe][i][level];
3556 skl_pipe_wm_active_state(temp, active, false,
3557 false, i, level);
3558 }
3559 temp = hw->cursor[pipe][level];
3560 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3561 }
3562
3563 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3564 temp = hw->plane_trans[pipe][i];
3565 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3566 }
3567
3568 temp = hw->cursor_trans[pipe];
3569 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3570}
3571
3572void skl_wm_get_hw_state(struct drm_device *dev)
3573{
a269c583
DL		 3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3576 struct drm_crtc *crtc;
3577
a269c583 3578 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3579 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3580 skl_pipe_wm_get_hw_state(crtc);
3581}
3582
243e6a44
VS		 3583static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3584{
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3587 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3589 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3590 enum pipe pipe = intel_crtc->pipe;
3591 static const unsigned int wm0_pipe_reg[] = {
3592 [PIPE_A] = WM0_PIPEA_ILK,
3593 [PIPE_B] = WM0_PIPEB_ILK,
3594 [PIPE_C] = WM0_PIPEC_IVB,
3595 };
3596
3597 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3598 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3599 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3600
3ef00284 3601 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3602
3603 if (active->pipe_enabled) {
243e6a44
VS		 3604 u32 tmp = hw->wm_pipe[pipe];
3605
3606 /*
3607 * For active pipes LP0 watermark is marked as
3608 * enabled, and LP1+ watermaks as disabled since
3609 * we can't really reverse compute them in case
3610 * multiple pipes are active.
3611 */
3612 active->wm[0].enable = true;
3613 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3614 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3615 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3616 active->linetime = hw->wm_linetime[pipe];
3617 } else {
3618 int level, max_level = ilk_wm_max_level(dev);
3619
3620 /*
3621 * For inactive pipes, all watermark levels
3622 * should be marked as enabled but zeroed,
3623 * which is what we'd compute them to.
3624 */
3625 for (level = 0; level <= max_level; level++)
3626 active->wm[level].enable = true;
3627 }
3628}
3629
3630void ilk_wm_get_hw_state(struct drm_device *dev)
3631{
3632 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3633 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3634 struct drm_crtc *crtc;
3635
70e1e0ec 3636 for_each_crtc(dev, crtc)
243e6a44
VS		 3637 ilk_pipe_wm_get_hw_state(crtc);
3638
3639 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3640 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3641 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3642
3643 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3644 if (INTEL_INFO(dev)->gen >= 7) {
3645 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3646 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3647 }
243e6a44 3648
a42a5719 3649 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3650 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3651 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3652 else if (IS_IVYBRIDGE(dev))
3653 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3654 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3655
3656 hw->enable_fbc_wm =
3657 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3658}
3659
b445e3b0
ED		 3660/**
3661 * intel_update_watermarks - update FIFO watermark values based on current modes
3662 *
3663 * Calculate watermark values for the various WM regs based on current mode
3664 * and plane configuration.
3665 *
3666 * There are several cases to deal with here:
3667 * - normal (i.e. non-self-refresh)
3668 * - self-refresh (SR) mode
3669 * - lines are large relative to FIFO size (buffer can hold up to 2)
3670 * - lines are small relative to FIFO size (buffer can hold more than 2
3671 * lines), so need to account for TLB latency
3672 *
3673 * The normal calculation is:
3674 * watermark = dotclock * bytes per pixel * latency
3675 * where latency is platform & configuration dependent (we assume pessimal
3676 * values here).
3677 *
3678 * The SR calculation is:
3679 * watermark = (trunc(latency/line time)+1) * surface width *
3680 * bytes per pixel
3681 * where
3682 * line time = htotal / dotclock
3683 * surface width = hdisplay for normal plane and 64 for cursor
3684 * and latency is assumed to be high, as above.
3685 *
3686 * The final value programmed to the register should always be rounded up,
3687 * and include an extra 2 entries to account for clock crossings.
3688 *
3689 * We don't use the sprite, so we can ignore that. And on Crestline we have
3690 * to set the non-SR watermarks to 8.
3691 */
46ba614c 3692void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3693{
46ba614c 3694 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3695
3696 if (dev_priv->display.update_wm)
46ba614c 3697 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3698}
3699
adf3d35e
VS		 3700void intel_update_sprite_watermarks(struct drm_plane *plane,
3701 struct drm_crtc *crtc,
ed57cb8a
DL		 3702 uint32_t sprite_width,
3703 uint32_t sprite_height,
3704 int pixel_size,
39db4a4d 3705 bool enabled, bool scaled)
b445e3b0 3706{
adf3d35e 3707 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3708
3709 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3710 dev_priv->display.update_sprite_wm(plane, crtc,
3711 sprite_width, sprite_height,
39db4a4d 3712 pixel_size, enabled, scaled);
b445e3b0
ED		 3713}
3714
9270388e
DV		 3715/**
3716 * Lock protecting IPS related data structures
9270388e
DV		 3717 */
3718DEFINE_SPINLOCK(mchdev_lock);
3719
3720/* Global for IPS driver to get at the current i915 device. Protected by
3721 * mchdev_lock. */
3722static struct drm_i915_private *i915_mch_dev;
3723
2b4e57bd
ED		 3724bool ironlake_set_drps(struct drm_device *dev, u8 val)
3725{
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 u16 rgvswctl;
3728
9270388e
DV		 3729 assert_spin_locked(&mchdev_lock);
3730
2b4e57bd
ED		 3731 rgvswctl = I915_READ16(MEMSWCTL);
3732 if (rgvswctl & MEMCTL_CMD_STS) {
3733 DRM_DEBUG("gpu busy, RCS change rejected\n");
3734 return false; /* still busy with another command */
3735 }
3736
3737 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3738 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3739 I915_WRITE16(MEMSWCTL, rgvswctl);
3740 POSTING_READ16(MEMSWCTL);
3741
3742 rgvswctl |= MEMCTL_CMD_STS;
3743 I915_WRITE16(MEMSWCTL, rgvswctl);
3744
3745 return true;
3746}
3747
8090c6b9 3748static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3749{
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 u32 rgvmodectl = I915_READ(MEMMODECTL);
3752 u8 fmax, fmin, fstart, vstart;
3753
9270388e
DV		 3754 spin_lock_irq(&mchdev_lock);
3755
2b4e57bd
ED		 3756 /* Enable temp reporting */
3757 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3758 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3759
3760 /* 100ms RC evaluation intervals */
3761 I915_WRITE(RCUPEI, 100000);
3762 I915_WRITE(RCDNEI, 100000);
3763
3764 /* Set max/min thresholds to 90ms and 80ms respectively */
3765 I915_WRITE(RCBMAXAVG, 90000);
3766 I915_WRITE(RCBMINAVG, 80000);
3767
3768 I915_WRITE(MEMIHYST, 1);
3769
3770 /* Set up min, max, and cur for interrupt handling */
3771 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3772 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3773 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3774 MEMMODE_FSTART_SHIFT;
3775
3776 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3777 PXVFREQ_PX_SHIFT;
3778
20e4d407
DV		 3779 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3780 dev_priv->ips.fstart = fstart;
2b4e57bd 3781
20e4d407
DV		 3782 dev_priv->ips.max_delay = fstart;
3783 dev_priv->ips.min_delay = fmin;
3784 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3785
3786 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3787 fmax, fmin, fstart);
3788
3789 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3790
3791 /*
3792 * Interrupts will be enabled in ironlake_irq_postinstall
3793 */
3794
3795 I915_WRITE(VIDSTART, vstart);
3796 POSTING_READ(VIDSTART);
3797
3798 rgvmodectl |= MEMMODE_SWMODE_EN;
3799 I915_WRITE(MEMMODECTL, rgvmodectl);
3800
9270388e 3801 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3802 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3803 mdelay(1);
2b4e57bd
ED		 3804
3805 ironlake_set_drps(dev, fstart);
3806
20e4d407 3807 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3808 I915_READ(0x112e0);
20e4d407
DV		 3809 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3810 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3811 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3812
3813 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3814}
3815
8090c6b9 3816static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3817{
3818 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3819 u16 rgvswctl;
3820
3821 spin_lock_irq(&mchdev_lock);
3822
3823 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3824
3825 /* Ack interrupts, disable EFC interrupt */
3826 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3827 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3828 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3829 I915_WRITE(DEIIR, DE_PCU_EVENT);
3830 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3831
3832 /* Go back to the starting frequency */
20e4d407 3833 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3834 mdelay(1);
2b4e57bd
ED		 3835 rgvswctl |= MEMCTL_CMD_STS;
3836 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3837 mdelay(1);
2b4e57bd 3838
9270388e 3839 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3840}
3841
acbe9475
DV		 3842/* There's a funny hw issue where the hw returns all 0 when reading from
3843 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3844 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3845 * all limits and the gpu stuck at whatever frequency it is at atm).
3846 */
74ef1173 3847static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3848{
7b9e0ae6 3849 u32 limits;
2b4e57bd 3850
20b46e59
DV		 3851 /* Only set the down limit when we've reached the lowest level to avoid
3852 * getting more interrupts, otherwise leave this clear. This prevents a
3853 * race in the hw when coming out of rc6: There's a tiny window where
3854 * the hw runs at the minimal clock before selecting the desired
3855 * frequency, if the down threshold expires in that window we will not
3856 * receive a down interrupt. */
74ef1173
AG		 3857 if (IS_GEN9(dev_priv->dev)) {
3858 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3859 if (val <= dev_priv->rps.min_freq_softlimit)
3860 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3861 } else {
3862 limits = dev_priv->rps.max_freq_softlimit << 24;
3863 if (val <= dev_priv->rps.min_freq_softlimit)
3864 limits |= dev_priv->rps.min_freq_softlimit << 16;
3865 }
20b46e59
DV		 3866
3867 return limits;
3868}
3869
dd75fdc8
CW		 3870static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3871{
3872 int new_power;
8a586437
AG		 3873 u32 threshold_up = 0, threshold_down = 0; /* in % */
3874 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 3875
3876 new_power = dev_priv->rps.power;
3877 switch (dev_priv->rps.power) {
3878 case LOW_POWER:
b39fb297 3879 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3880 new_power = BETWEEN;
3881 break;
3882
3883 case BETWEEN:
b39fb297 3884 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3885 new_power = LOW_POWER;
b39fb297 3886 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3887 new_power = HIGH_POWER;
3888 break;
3889
3890 case HIGH_POWER:
b39fb297 3891 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3892 new_power = BETWEEN;
3893 break;
3894 }
3895 /* Max/min bins are special */
aed242ff 3896 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 3897 new_power = LOW_POWER;
aed242ff 3898 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3899 new_power = HIGH_POWER;
3900 if (new_power == dev_priv->rps.power)
3901 return;
3902
3903 /* Note the units here are not exactly 1us, but 1280ns. */
3904 switch (new_power) {
3905 case LOW_POWER:
3906 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 3907 ei_up = 16000;
3908 threshold_up = 95;
dd75fdc8
CW		 3909
3910 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 3911 ei_down = 32000;
3912 threshold_down = 85;
dd75fdc8
CW		 3913 break;
3914
3915 case BETWEEN:
3916 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 3917 ei_up = 13000;
3918 threshold_up = 90;
dd75fdc8
CW		 3919
3920 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 3921 ei_down = 32000;
3922 threshold_down = 75;
dd75fdc8
CW		 3923 break;
3924
3925 case HIGH_POWER:
3926 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 3927 ei_up = 10000;
3928 threshold_up = 85;
dd75fdc8
CW		 3929
3930 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 3931 ei_down = 32000;
3932 threshold_down = 60;
dd75fdc8
CW		 3933 break;
3934 }
3935
8a586437
AG		 3936 I915_WRITE(GEN6_RP_UP_EI,
3937 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3938 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3939 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3940
3941 I915_WRITE(GEN6_RP_DOWN_EI,
3942 GT_INTERVAL_FROM_US(dev_priv, ei_down));
3943 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3944 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
3945
3946 I915_WRITE(GEN6_RP_CONTROL,
3947 GEN6_RP_MEDIA_TURBO |
3948 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3949 GEN6_RP_MEDIA_IS_GFX |
3950 GEN6_RP_ENABLE |
3951 GEN6_RP_UP_BUSY_AVG |
3952 GEN6_RP_DOWN_IDLE_AVG);
3953
dd75fdc8
CW		 3954 dev_priv->rps.power = new_power;
3955 dev_priv->rps.last_adj = 0;
3956}
3957
2876ce73
CW		 3958static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3959{
3960 u32 mask = 0;
3961
3962 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 3963 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 3964 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 3965 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 3966
7b3c29f6
CW		 3967 mask &= dev_priv->pm_rps_events;
3968
59d02a1f 3969 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 3970}
3971
b8a5ff8d
JM		 3972/* gen6_set_rps is called to update the frequency request, but should also be
3973 * called when the range (min_delay and max_delay) is modified so that we can
3974 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 3975static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 3976{
3977 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3978
4fc688ce 3979 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 3980 WARN_ON(val > dev_priv->rps.max_freq);
3981 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 3982
eb64cad1
CW		 3983 /* min/max delay may still have been modified so be sure to
3984 * write the limits value.
3985 */
3986 if (val != dev_priv->rps.cur_freq) {
3987 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3988
5704195c
AG		 3989 if (IS_GEN9(dev))
3990 I915_WRITE(GEN6_RPNSWREQ,
3991 GEN9_FREQUENCY(val));
3992 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3993 I915_WRITE(GEN6_RPNSWREQ,
3994 HSW_FREQUENCY(val));
3995 else
3996 I915_WRITE(GEN6_RPNSWREQ,
3997 GEN6_FREQUENCY(val) |
3998 GEN6_OFFSET(0) |
3999 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4000 }
7b9e0ae6 4001
7b9e0ae6
CW		 4002 /* Make sure we continue to get interrupts
4003 * until we hit the minimum or maximum frequencies.
4004 */
74ef1173 4005 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4006 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4007
d5570a72
BW		 4008 POSTING_READ(GEN6_RPNSWREQ);
4009
b39fb297 4010 dev_priv->rps.cur_freq = val;
be2cde9a 4011 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4012}
4013
ffe02b40
VS		 4014static void valleyview_set_rps(struct drm_device *dev, u8 val)
4015{
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017
4018 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4019 WARN_ON(val > dev_priv->rps.max_freq);
4020 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4021
4022 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4023 "Odd GPU freq value\n"))
4024 val &= ~1;
4025
4026 if (val != dev_priv->rps.cur_freq)
4027 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4028
4029 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4030
4031 dev_priv->rps.cur_freq = val;
4032 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4033}
4034
76c3552f
D		 4035/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4036 *
4037 * * If Gfx is Idle, then
4038 * 1. Mask Turbo interrupts
4039 * 2. Bring up Gfx clock
4040 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4041 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4042 * 5. Unmask Turbo interrupts
4043*/
4044static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4045{
5549d25f 4046 struct drm_device *dev = dev_priv->dev;
aed242ff 4047 u32 val = dev_priv->rps.idle_freq;
5549d25f 4048
21a11fff
VS		 4049 /* CHV and latest VLV don't need to force the gfx clock */
4050 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
aed242ff 4051 valleyview_set_rps(dev_priv->dev, val);
5549d25f
D		 4052 return;
4053 }
4054
76c3552f
D		 4055 /*
4056 * When we are idle. Drop to min voltage state.
4057 */
4058
aed242ff 4059 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4060 return;
4061
4062 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 4063 I915_WRITE(GEN6_PMINTRMSK,
4064 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 4065
650ad970 4066 vlv_force_gfx_clock(dev_priv, true);
76c3552f 4067
aed242ff 4068 dev_priv->rps.cur_freq = val;
76c3552f 4069
aed242ff 4070 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
76c3552f
D		 4071
4072 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 4073 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 4074 DRM_ERROR("timed out waiting for Punit\n");
4075
650ad970 4076 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4077
aed242ff 4078 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
76c3552f
D		 4079}
4080
43cf3bf0
CW		 4081void gen6_rps_busy(struct drm_i915_private *dev_priv)
4082{
4083 mutex_lock(&dev_priv->rps.hw_lock);
4084 if (dev_priv->rps.enabled) {
4085 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4086 gen6_rps_reset_ei(dev_priv);
4087 I915_WRITE(GEN6_PMINTRMSK,
4088 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4089 }
4090 mutex_unlock(&dev_priv->rps.hw_lock);
4091}
4092
b29c19b6
CW		 4093void gen6_rps_idle(struct drm_i915_private *dev_priv)
4094{
691bb717
DL		 4095 struct drm_device *dev = dev_priv->dev;
4096
b29c19b6 4097 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4098 if (dev_priv->rps.enabled) {
21a11fff 4099 if (IS_VALLEYVIEW(dev))
76c3552f 4100 vlv_set_rps_idle(dev_priv);
7526ed79 4101 else
aed242ff 4102 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4103 dev_priv->rps.last_adj = 0;
43cf3bf0 4104 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4105 }
b29c19b6
CW		 4106 mutex_unlock(&dev_priv->rps.hw_lock);
4107}
4108
4109void gen6_rps_boost(struct drm_i915_private *dev_priv)
4110{
43cf3bf0
CW		 4111 u32 val;
4112
b29c19b6 4113 mutex_lock(&dev_priv->rps.hw_lock);
43cf3bf0
CW		 4114 val = dev_priv->rps.max_freq_softlimit;
4115 if (dev_priv->rps.enabled &&
4116 dev_priv->mm.busy &&
4117 dev_priv->rps.cur_freq < val) {
4118 intel_set_rps(dev_priv->dev, val);
c0951f0c
CW		 4119 dev_priv->rps.last_adj = 0;
4120 }
b29c19b6
CW		 4121 mutex_unlock(&dev_priv->rps.hw_lock);
4122}
4123
ffe02b40 4124void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4125{
ffe02b40
VS		 4126 if (IS_VALLEYVIEW(dev))
4127 valleyview_set_rps(dev, val);
4128 else
4129 gen6_set_rps(dev, val);
0a073b84
JB		 4130}
4131
20e49366
ZW		 4132static void gen9_disable_rps(struct drm_device *dev)
4133{
4134 struct drm_i915_private *dev_priv = dev->dev_private;
4135
4136 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4137 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4138}
4139
44fc7d5c 4140static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4141{
4142 struct drm_i915_private *dev_priv = dev->dev_private;
4143
4144 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4145 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4146}
4147
38807746
D		 4148static void cherryview_disable_rps(struct drm_device *dev)
4149{
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151
4152 I915_WRITE(GEN6_RC_CONTROL, 0);
4153}
4154
44fc7d5c
DV		 4155static void valleyview_disable_rps(struct drm_device *dev)
4156{
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158
98a2e5f9
D		 4159 /* we're doing forcewake before Disabling RC6,
4160 * This what the BIOS expects when going into suspend */
59bad947 4161 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4162
44fc7d5c 4163 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4164
59bad947 4165 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4166}
4167
dc39fff7
BW		 4168static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4169{
91ca689a
ID		 4170 if (IS_VALLEYVIEW(dev)) {
4171 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4172 mode = GEN6_RC_CTL_RC6_ENABLE;
4173 else
4174 mode = 0;
4175 }
58abf1da
RV		 4176 if (HAS_RC6p(dev))
4177 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4178 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4179 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4180 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4181
4182 else
4183 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4184 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4185}
4186
e6069ca8 4187static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4188{
eb4926e4
DL		 4189 /* No RC6 before Ironlake */
4190 if (INTEL_INFO(dev)->gen < 5)
4191 return 0;
4192
e6069ca8
ID		 4193 /* RC6 is only on Ironlake mobile not on desktop */
4194 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4195 return 0;
4196
456470eb 4197 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4198 if (enable_rc6 >= 0) {
4199 int mask;
4200
58abf1da 4201 if (HAS_RC6p(dev))
e6069ca8
ID		 4202 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4203 INTEL_RC6pp_ENABLE;
4204 else
4205 mask = INTEL_RC6_ENABLE;
4206
4207 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4208 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4209 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4210
4211 return enable_rc6 & mask;
4212 }
2b4e57bd 4213
6567d748
CW		 4214 /* Disable RC6 on Ironlake */
4215 if (INTEL_INFO(dev)->gen == 5)
4216 return 0;
2b4e57bd 4217
8bade1ad 4218 if (IS_IVYBRIDGE(dev))
cca84a1f 4219 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4220
4221 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4222}
4223
e6069ca8
ID		 4224int intel_enable_rc6(const struct drm_device *dev)
4225{
4226 return i915.enable_rc6;
4227}
4228
93ee2920 4229static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4230{
93ee2920
TR		 4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 uint32_t rp_state_cap;
4233 u32 ddcc_status = 0;
4234 int ret;
4235
4236 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 4237 /* All of these values are in units of 50MHz */
4238 dev_priv->rps.cur_freq = 0;
93ee2920 4239 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4240 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4241 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4242 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
cee991cb
AG		 4243 if (IS_SKYLAKE(dev)) {
4244 /* Store the frequency values in 16.66 MHZ units, which is
4245 the natural hardware unit for SKL */
4246 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4247 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4248 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4249 }
3280e8b0
BW		 4250 /* hw_max = RP0 until we check for overclocking */
4251 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4252
93ee2920
TR		 4253 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4254 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4255 ret = sandybridge_pcode_read(dev_priv,
4256 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4257 &ddcc_status);
4258 if (0 == ret)
4259 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4260 clamp_t(u8,
4261 ((ddcc_status >> 8) & 0xff),
4262 dev_priv->rps.min_freq,
4263 dev_priv->rps.max_freq);
93ee2920
TR		 4264 }
4265
aed242ff
CW		 4266 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4267
3280e8b0
BW		 4268 /* Preserve min/max settings in case of re-init */
4269 if (dev_priv->rps.max_freq_softlimit == 0)
4270 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4271
93ee2920
TR		 4272 if (dev_priv->rps.min_freq_softlimit == 0) {
4273 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4274 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR		 4275 /* max(RPe, 450 MHz) */
4276 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR		 4277 else
4278 dev_priv->rps.min_freq_softlimit =
4279 dev_priv->rps.min_freq;
4280 }
3280e8b0
BW		 4281}
4282
b6fef0ef 4283/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4284static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4285{
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287
4288 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4289
ba1c554c
DL		 4290 gen6_init_rps_frequencies(dev);
4291
0beb059a
AG		 4292 /* Program defaults and thresholds for RPS*/
4293 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4294 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4295
4296 /* 1 second timeout*/
4297 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4298 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4299
b6fef0ef 4300 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4301
0beb059a
AG		 4302 /* Leaning on the below call to gen6_set_rps to program/setup the
4303 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4304 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4305 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4306 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4307
4308 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4309}
4310
4311static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4312{
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4314 struct intel_engine_cs *ring;
4315 uint32_t rc6_mask = 0;
4316 int unused;
4317
4318 /* 1a: Software RC state - RC0 */
4319 I915_WRITE(GEN6_RC_STATE, 0);
4320
4321 /* 1b: Get forcewake during program sequence. Although the driver
4322 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4323 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4324
4325 /* 2a: Disable RC states. */
4326 I915_WRITE(GEN6_RC_CONTROL, 0);
4327
4328 /* 2b: Program RC6 thresholds.*/
4329 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4330 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4331 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4332 for_each_ring(ring, dev_priv, unused)
4333 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4334 I915_WRITE(GEN6_RC_SLEEP, 0);
4335 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4336
38c23527
ZW		 4337 /* 2c: Program Coarse Power Gating Policies. */
4338 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4339 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4340
20e49366
ZW		 4341 /* 3a: Enable RC6 */
4342 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4343 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4344 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4345 "on" : "off");
4346 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4347 GEN6_RC_CTL_EI_MODE(1) |
4348 rc6_mask);
4349
38c23527
ZW		 4350 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4351 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4352
59bad947 4353 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4354
4355}
4356
6edee7f3
BW		 4357static void gen8_enable_rps(struct drm_device *dev)
4358{
4359 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4360 struct intel_engine_cs *ring;
93ee2920 4361 uint32_t rc6_mask = 0;
6edee7f3
BW		 4362 int unused;
4363
4364 /* 1a: Software RC state - RC0 */
4365 I915_WRITE(GEN6_RC_STATE, 0);
4366
4367 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4368 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4369 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4370
4371 /* 2a: Disable RC states. */
4372 I915_WRITE(GEN6_RC_CONTROL, 0);
4373
93ee2920
TR		 4374 /* Initialize rps frequencies */
4375 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4376
4377 /* 2b: Program RC6 thresholds.*/
4378 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4379 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4380 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4381 for_each_ring(ring, dev_priv, unused)
4382 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4383 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4384 if (IS_BROADWELL(dev))
4385 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4386 else
4387 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4388
4389 /* 3: Enable RC6 */
4390 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4391 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4392 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4393 if (IS_BROADWELL(dev))
4394 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4395 GEN7_RC_CTL_TO_MODE |
4396 rc6_mask);
4397 else
4398 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4399 GEN6_RC_CTL_EI_MODE(1) |
4400 rc6_mask);
6edee7f3
BW		 4401
4402 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4403 I915_WRITE(GEN6_RPNSWREQ,
4404 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4405 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4406 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4407 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4408 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4409
4410 /* Docs recommend 900MHz, and 300 MHz respectively */
4411 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4412 dev_priv->rps.max_freq_softlimit << 24 |
4413 dev_priv->rps.min_freq_softlimit << 16);
4414
4415 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4416 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4417 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4418 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4419
4420 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4421
4422 /* 5: Enable RPS */
7526ed79
DV		 4423 I915_WRITE(GEN6_RP_CONTROL,
4424 GEN6_RP_MEDIA_TURBO |
4425 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4426 GEN6_RP_MEDIA_IS_GFX |
4427 GEN6_RP_ENABLE |
4428 GEN6_RP_UP_BUSY_AVG |
4429 GEN6_RP_DOWN_IDLE_AVG);
4430
4431 /* 6: Ring frequency + overclocking (our driver does this later */
4432
c7f3153a 4433 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4434 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4435
59bad947 4436 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4437}
4438
79f5b2c7 4439static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4440{
79f5b2c7 4441 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4442 struct intel_engine_cs *ring;
d060c169 4443 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4444 u32 gtfifodbg;
2b4e57bd 4445 int rc6_mode;
42c0526c 4446 int i, ret;
2b4e57bd 4447
4fc688ce 4448 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4449
2b4e57bd
ED		 4450 /* Here begins a magic sequence of register writes to enable
4451 * auto-downclocking.
4452 *
4453 * Perhaps there might be some value in exposing these to
4454 * userspace...
4455 */
4456 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4457
4458 /* Clear the DBG now so we don't confuse earlier errors */
4459 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4460 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4461 I915_WRITE(GTFIFODBG, gtfifodbg);
4462 }
4463
59bad947 4464 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4465
93ee2920
TR		 4466 /* Initialize rps frequencies */
4467 gen6_init_rps_frequencies(dev);
dd0a1aa1 4468
2b4e57bd
ED		 4469 /* disable the counters and set deterministic thresholds */
4470 I915_WRITE(GEN6_RC_CONTROL, 0);
4471
4472 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4473 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4474 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4475 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4476 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4477
b4519513
CW		 4478 for_each_ring(ring, dev_priv, i)
4479 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4480
4481 I915_WRITE(GEN6_RC_SLEEP, 0);
4482 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4483 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4484 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4485 else
4486 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4487 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4488 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4489
5a7dc92a 4490 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4491 rc6_mode = intel_enable_rc6(dev_priv->dev);
4492 if (rc6_mode & INTEL_RC6_ENABLE)
4493 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4494
5a7dc92a
ED		 4495 /* We don't use those on Haswell */
4496 if (!IS_HASWELL(dev)) {
4497 if (rc6_mode & INTEL_RC6p_ENABLE)
4498 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4499
5a7dc92a
ED		 4500 if (rc6_mode & INTEL_RC6pp_ENABLE)
4501 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4502 }
2b4e57bd 4503
dc39fff7 4504 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4505
4506 I915_WRITE(GEN6_RC_CONTROL,
4507 rc6_mask |
4508 GEN6_RC_CTL_EI_MODE(1) |
4509 GEN6_RC_CTL_HW_ENABLE);
4510
dd75fdc8
CW		 4511 /* Power down if completely idle for over 50ms */
4512 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4513 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4514
42c0526c 4515 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4516 if (ret)
42c0526c 4517 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4518
4519 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4520 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4521 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4522 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4523 (pcu_mbox & 0xff) * 50);
b39fb297 4524 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4525 }
4526
dd75fdc8 4527 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4528 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4529
31643d54
BW		 4530 rc6vids = 0;
4531 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4532 if (IS_GEN6(dev) && ret) {
4533 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4534 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4535 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4536 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4537 rc6vids &= 0xffff00;
4538 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4539 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4540 if (ret)
4541 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4542 }
4543
59bad947 4544 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4545}
4546
c2bc2fc5 4547static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4548{
79f5b2c7 4549 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4550 int min_freq = 15;
3ebecd07
CW		 4551 unsigned int gpu_freq;
4552 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4553 int scaling_factor = 180;
eda79642 4554 struct cpufreq_policy *policy;
2b4e57bd 4555
4fc688ce 4556 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4557
eda79642
BW		 4558 policy = cpufreq_cpu_get(0);
4559 if (policy) {
4560 max_ia_freq = policy->cpuinfo.max_freq;
4561 cpufreq_cpu_put(policy);
4562 } else {
4563 /*
4564 * Default to measured freq if none found, PCU will ensure we
4565 * don't go over
4566 */
2b4e57bd 4567 max_ia_freq = tsc_khz;
eda79642 4568 }
2b4e57bd
ED		 4569
4570 /* Convert from kHz to MHz */
4571 max_ia_freq /= 1000;
4572
153b4b95 4573 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4574 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4575 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4576
2b4e57bd
ED		 4577 /*
4578 * For each potential GPU frequency, load a ring frequency we'd like
4579 * to use for memory access. We do this by specifying the IA frequency
4580 * the PCU should use as a reference to determine the ring frequency.
4581 */
6985b352 4582 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4583 gpu_freq--) {
6985b352 4584 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4585 unsigned int ia_freq = 0, ring_freq = 0;
4586
46c764d4
BW		 4587 if (INTEL_INFO(dev)->gen >= 8) {
4588 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4589 ring_freq = max(min_ring_freq, gpu_freq);
4590 } else if (IS_HASWELL(dev)) {
f6aca45c 4591 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4592 ring_freq = max(min_ring_freq, ring_freq);
4593 /* leave ia_freq as the default, chosen by cpufreq */
4594 } else {
4595 /* On older processors, there is no separate ring
4596 * clock domain, so in order to boost the bandwidth
4597 * of the ring, we need to upclock the CPU (ia_freq).
4598 *
4599 * For GPU frequencies less than 750MHz,
4600 * just use the lowest ring freq.
4601 */
4602 if (gpu_freq < min_freq)
4603 ia_freq = 800;
4604 else
4605 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4606 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4607 }
2b4e57bd 4608
42c0526c
BW		 4609 sandybridge_pcode_write(dev_priv,
4610 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4611 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4612 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4613 gpu_freq);
2b4e57bd 4614 }
2b4e57bd
ED		 4615}
4616
c2bc2fc5
ID		 4617void gen6_update_ring_freq(struct drm_device *dev)
4618{
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4622 return;
4623
4624 mutex_lock(&dev_priv->rps.hw_lock);
4625 __gen6_update_ring_freq(dev);
4626 mutex_unlock(&dev_priv->rps.hw_lock);
4627}
4628
03af2045 4629static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4630{
095acd5f 4631 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4632 u32 val, rp0;
4633
095acd5f
D		 4634 if (dev->pdev->revision >= 0x20) {
4635 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4636
095acd5f
D		 4637 switch (INTEL_INFO(dev)->eu_total) {
4638 case 8:
4639 /* (2 * 4) config */
4640 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4641 break;
4642 case 12:
4643 /* (2 * 6) config */
4644 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4645 break;
4646 case 16:
4647 /* (2 * 8) config */
4648 default:
4649 /* Setting (2 * 8) Min RP0 for any other combination */
4650 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4651 break;
4652 }
4653 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4654 } else {
4655 /* For pre-production hardware */
4656 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4657 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4658 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4659 }
2b6b3a09
D		 4660 return rp0;
4661}
4662
4663static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4664{
4665 u32 val, rpe;
4666
4667 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4668 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4669
4670 return rpe;
4671}
4672
7707df4a
D		 4673static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4674{
095acd5f 4675 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4676 u32 val, rp1;
4677
095acd5f
D		 4678 if (dev->pdev->revision >= 0x20) {
4679 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4680 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4681 } else {
4682 /* For pre-production hardware */
4683 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4684 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4685 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4686 }
7707df4a
D		 4687 return rp1;
4688}
4689
03af2045 4690static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4691{
095acd5f 4692 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4693 u32 val, rpn;
4694
095acd5f
D		 4695 if (dev->pdev->revision >= 0x20) {
4696 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4697 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4698 FB_GFX_FREQ_FUSE_MASK);
4699 } else { /* For pre-production hardware */
4700 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4701 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4702 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4703 }
4704
2b6b3a09
D		 4705 return rpn;
4706}
4707
f8f2b001
D		 4708static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4709{
4710 u32 val, rp1;
4711
4712 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4713
4714 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4715
4716 return rp1;
4717}
4718
03af2045 4719static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4720{
4721 u32 val, rp0;
4722
64936258 4723 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4724
4725 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4726 /* Clamp to max */
4727 rp0 = min_t(u32, rp0, 0xea);
4728
4729 return rp0;
4730}
4731
4732static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4733{
4734 u32 val, rpe;
4735
64936258 4736 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4737 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4738 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4739 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4740
4741 return rpe;
4742}
4743
03af2045 4744static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4745{
64936258 4746 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4747}
4748
ae48434c
ID		 4749/* Check that the pctx buffer wasn't move under us. */
4750static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4751{
4752 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4753
4754 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4755 dev_priv->vlv_pctx->stolen->start);
4756}
4757
38807746
D		 4758
4759/* Check that the pcbr address is not empty. */
4760static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4761{
4762 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4763
4764 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4765}
4766
4767static void cherryview_setup_pctx(struct drm_device *dev)
4768{
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 unsigned long pctx_paddr, paddr;
4771 struct i915_gtt *gtt = &dev_priv->gtt;
4772 u32 pcbr;
4773 int pctx_size = 32*1024;
4774
4775 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4776
4777 pcbr = I915_READ(VLV_PCBR);
4778 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4779 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4780 paddr = (dev_priv->mm.stolen_base +
4781 (gtt->stolen_size - pctx_size));
4782
4783 pctx_paddr = (paddr & (~4095));
4784 I915_WRITE(VLV_PCBR, pctx_paddr);
4785 }
ce611ef8
VS		 4786
4787 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4788}
4789
c9cddffc
JB		 4790static void valleyview_setup_pctx(struct drm_device *dev)
4791{
4792 struct drm_i915_private *dev_priv = dev->dev_private;
4793 struct drm_i915_gem_object *pctx;
4794 unsigned long pctx_paddr;
4795 u32 pcbr;
4796 int pctx_size = 24*1024;
4797
17b0c1f7
ID		 4798 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4799
c9cddffc
JB		 4800 pcbr = I915_READ(VLV_PCBR);
4801 if (pcbr) {
4802 /* BIOS set it up already, grab the pre-alloc'd space */
4803 int pcbr_offset;
4804
4805 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4806 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4807 pcbr_offset,
190d6cd5 4808 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4809 pctx_size);
4810 goto out;
4811 }
4812
ce611ef8
VS		 4813 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4814
c9cddffc
JB		 4815 /*
4816 * From the Gunit register HAS:
4817 * The Gfx driver is expected to program this register and ensure
4818 * proper allocation within Gfx stolen memory. For example, this
4819 * register should be programmed such than the PCBR range does not
4820 * overlap with other ranges, such as the frame buffer, protected
4821 * memory, or any other relevant ranges.
4822 */
4823 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4824 if (!pctx) {
4825 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4826 return;
4827 }
4828
4829 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4830 I915_WRITE(VLV_PCBR, pctx_paddr);
4831
4832out:
ce611ef8 4833 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4834 dev_priv->vlv_pctx = pctx;
4835}
4836
ae48434c
ID		 4837static void valleyview_cleanup_pctx(struct drm_device *dev)
4838{
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4840
4841 if (WARN_ON(!dev_priv->vlv_pctx))
4842 return;
4843
4844 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4845 dev_priv->vlv_pctx = NULL;
4846}
4847
4e80519e
ID		 4848static void valleyview_init_gt_powersave(struct drm_device *dev)
4849{
4850 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4851 u32 val;
4e80519e
ID		 4852
4853 valleyview_setup_pctx(dev);
4854
4855 mutex_lock(&dev_priv->rps.hw_lock);
4856
2bb25c17
VS		 4857 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4858 switch ((val >> 6) & 3) {
4859 case 0:
4860 case 1:
4861 dev_priv->mem_freq = 800;
4862 break;
4863 case 2:
4864 dev_priv->mem_freq = 1066;
4865 break;
4866 case 3:
4867 dev_priv->mem_freq = 1333;
4868 break;
4869 }
80b83b62 4870 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4871
4e80519e
ID		 4872 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4873 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4874 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4875 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4876 dev_priv->rps.max_freq);
4877
4878 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4879 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4880 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4881 dev_priv->rps.efficient_freq);
4882
f8f2b001
D		 4883 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4884 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4885 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4886 dev_priv->rps.rp1_freq);
4887
4e80519e
ID		 4888 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4889 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4890 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4891 dev_priv->rps.min_freq);
4892
aed242ff
CW		 4893 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4894
4e80519e
ID		 4895 /* Preserve min/max settings in case of re-init */
4896 if (dev_priv->rps.max_freq_softlimit == 0)
4897 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4898
4899 if (dev_priv->rps.min_freq_softlimit == 0)
4900 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4901
4902 mutex_unlock(&dev_priv->rps.hw_lock);
4903}
4904
38807746
D		 4905static void cherryview_init_gt_powersave(struct drm_device *dev)
4906{
2b6b3a09 4907 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4908 u32 val;
2b6b3a09 4909
38807746 4910 cherryview_setup_pctx(dev);
2b6b3a09
D		 4911
4912 mutex_lock(&dev_priv->rps.hw_lock);
4913
c6e8f39d
VS		 4914 mutex_lock(&dev_priv->dpio_lock);
4915 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4916 mutex_unlock(&dev_priv->dpio_lock);
4917
2bb25c17
VS		 4918 switch ((val >> 2) & 0x7) {
4919 case 0:
4920 case 1:
4921 dev_priv->rps.cz_freq = 200;
4922 dev_priv->mem_freq = 1600;
4923 break;
4924 case 2:
4925 dev_priv->rps.cz_freq = 267;
4926 dev_priv->mem_freq = 1600;
4927 break;
4928 case 3:
4929 dev_priv->rps.cz_freq = 333;
4930 dev_priv->mem_freq = 2000;
4931 break;
4932 case 4:
4933 dev_priv->rps.cz_freq = 320;
4934 dev_priv->mem_freq = 1600;
4935 break;
4936 case 5:
4937 dev_priv->rps.cz_freq = 400;
4938 dev_priv->mem_freq = 1600;
4939 break;
4940 }
80b83b62 4941 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4942
2b6b3a09
D		 4943 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4944 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4945 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4946 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 4947 dev_priv->rps.max_freq);
4948
4949 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4950 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4951 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4952 dev_priv->rps.efficient_freq);
4953
7707df4a
D		 4954 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4955 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 4956 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 4957 dev_priv->rps.rp1_freq);
4958
2b6b3a09
D		 4959 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4960 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4961 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 4962 dev_priv->rps.min_freq);
4963
1c14762d
VS		 4964 WARN_ONCE((dev_priv->rps.max_freq |
4965 dev_priv->rps.efficient_freq |
4966 dev_priv->rps.rp1_freq |
4967 dev_priv->rps.min_freq) & 1,
4968 "Odd GPU freq values\n");
4969
aed242ff
CW		 4970 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4971
2b6b3a09
D		 4972 /* Preserve min/max settings in case of re-init */
4973 if (dev_priv->rps.max_freq_softlimit == 0)
4974 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4975
4976 if (dev_priv->rps.min_freq_softlimit == 0)
4977 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4978
4979 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4980}
4981
4e80519e
ID		 4982static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4983{
4984 valleyview_cleanup_pctx(dev);
4985}
4986
38807746
D		 4987static void cherryview_enable_rps(struct drm_device *dev)
4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 struct intel_engine_cs *ring;
2b6b3a09 4991 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4992 int i;
4993
4994 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4995
4996 gtfifodbg = I915_READ(GTFIFODBG);
4997 if (gtfifodbg) {
4998 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4999 gtfifodbg);
5000 I915_WRITE(GTFIFODBG, gtfifodbg);
5001 }
5002
5003 cherryview_check_pctx(dev_priv);
5004
5005 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5006 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5007 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5008
160614a2
VS		 5009 /* Disable RC states. */
5010 I915_WRITE(GEN6_RC_CONTROL, 0);
5011
38807746
D		 5012 /* 2a: Program RC6 thresholds.*/
5013 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5014 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5015 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5016
5017 for_each_ring(ring, dev_priv, i)
5018 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5019 I915_WRITE(GEN6_RC_SLEEP, 0);
5020
af5a75a3
VS		 5021 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
5022 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D		 5023
5024 /* allows RC6 residency counter to work */
5025 I915_WRITE(VLV_COUNTER_CONTROL,
5026 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5027 VLV_MEDIA_RC6_COUNT_EN |
5028 VLV_RENDER_RC6_COUNT_EN));
5029
5030 /* For now we assume BIOS is allocating and populating the PCBR */
5031 pcbr = I915_READ(VLV_PCBR);
5032
38807746
D		 5033 /* 3: Enable RC6 */
5034 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5035 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5036 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5037
5038 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5039
2b6b3a09 5040 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5041 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5042 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5043 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5044 I915_WRITE(GEN6_RP_UP_EI, 66000);
5045 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5046
5047 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5048
5049 /* 5: Enable RPS */
5050 I915_WRITE(GEN6_RP_CONTROL,
5051 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5052 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5053 GEN6_RP_ENABLE |
5054 GEN6_RP_UP_BUSY_AVG |
5055 GEN6_RP_DOWN_IDLE_AVG);
5056
5057 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5058
8d40c3ae
VS		 5059 /* RPS code assumes GPLL is used */
5060 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5061
c8e9627d 5062 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5063 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5064
5065 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5066 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5067 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5068 dev_priv->rps.cur_freq);
5069
5070 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5071 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5072 dev_priv->rps.efficient_freq);
5073
5074 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5075
59bad947 5076 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5077}
5078
0a073b84
JB		 5079static void valleyview_enable_rps(struct drm_device *dev)
5080{
5081 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5082 struct intel_engine_cs *ring;
2a5913a8 5083 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5084 int i;
5085
5086 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5087
ae48434c
ID		 5088 valleyview_check_pctx(dev_priv);
5089
0a073b84 5090 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5091 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5092 gtfifodbg);
0a073b84
JB		 5093 I915_WRITE(GTFIFODBG, gtfifodbg);
5094 }
5095
c8d9a590 5096 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5097 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5098
160614a2
VS		 5099 /* Disable RC states. */
5100 I915_WRITE(GEN6_RC_CONTROL, 0);
5101
cad725fe 5102 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5103 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5104 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5105 I915_WRITE(GEN6_RP_UP_EI, 66000);
5106 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5107
5108 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5109
5110 I915_WRITE(GEN6_RP_CONTROL,
5111 GEN6_RP_MEDIA_TURBO |
5112 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5113 GEN6_RP_MEDIA_IS_GFX |
5114 GEN6_RP_ENABLE |
5115 GEN6_RP_UP_BUSY_AVG |
5116 GEN6_RP_DOWN_IDLE_CONT);
5117
5118 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5119 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5120 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5121
5122 for_each_ring(ring, dev_priv, i)
5123 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5124
2f0aa304 5125 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5126
5127 /* allows RC6 residency counter to work */
49798eb2 5128 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5129 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5130 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5131 VLV_MEDIA_RC6_COUNT_EN |
5132 VLV_RENDER_RC6_COUNT_EN));
31685c25 5133
a2b23fe0 5134 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5135 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5136
5137 intel_print_rc6_info(dev, rc6_mode);
5138
a2b23fe0 5139 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5140
64936258 5141 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5142
8d40c3ae
VS		 5143 /* RPS code assumes GPLL is used */
5144 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5145
c8e9627d 5146 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5147 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5148
b39fb297 5149 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5150 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5151 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5152 dev_priv->rps.cur_freq);
0a073b84 5153
73008b98 5154 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5155 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5156 dev_priv->rps.efficient_freq);
0a073b84 5157
b39fb297 5158 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5159
59bad947 5160 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5161}
5162
dde18883
ED		 5163static unsigned long intel_pxfreq(u32 vidfreq)
5164{
5165 unsigned long freq;
5166 int div = (vidfreq & 0x3f0000) >> 16;
5167 int post = (vidfreq & 0x3000) >> 12;
5168 int pre = (vidfreq & 0x7);
5169
5170 if (!pre)
5171 return 0;
5172
5173 freq = ((div * 133333) / ((1<<post) * pre));
5174
5175 return freq;
5176}
5177
eb48eb00
DV		 5178static const struct cparams {
5179 u16 i;
5180 u16 t;
5181 u16 m;
5182 u16 c;
5183} cparams[] = {
5184 { 1, 1333, 301, 28664 },
5185 { 1, 1066, 294, 24460 },
5186 { 1, 800, 294, 25192 },
5187 { 0, 1333, 276, 27605 },
5188 { 0, 1066, 276, 27605 },
5189 { 0, 800, 231, 23784 },
5190};
5191
f531dcb2 5192static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5193{
5194 u64 total_count, diff, ret;
5195 u32 count1, count2, count3, m = 0, c = 0;
5196 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5197 int i;
5198
02d71956
DV		 5199 assert_spin_locked(&mchdev_lock);
5200
20e4d407 5201 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5202
5203 /* Prevent division-by-zero if we are asking too fast.
5204 * Also, we don't get interesting results if we are polling
5205 * faster than once in 10ms, so just return the saved value
5206 * in such cases.
5207 */
5208 if (diff1 <= 10)
20e4d407 5209 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5210
5211 count1 = I915_READ(DMIEC);
5212 count2 = I915_READ(DDREC);
5213 count3 = I915_READ(CSIEC);
5214
5215 total_count = count1 + count2 + count3;
5216
5217 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5218 if (total_count < dev_priv->ips.last_count1) {
5219 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5220 diff += total_count;
5221 } else {
20e4d407 5222 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5223 }
5224
5225 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5226 if (cparams[i].i == dev_priv->ips.c_m &&
5227 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5228 m = cparams[i].m;
5229 c = cparams[i].c;
5230 break;
5231 }
5232 }
5233
5234 diff = div_u64(diff, diff1);
5235 ret = ((m * diff) + c);
5236 ret = div_u64(ret, 10);
5237
20e4d407
DV		 5238 dev_priv->ips.last_count1 = total_count;
5239 dev_priv->ips.last_time1 = now;
eb48eb00 5240
20e4d407 5241 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5242
5243 return ret;
5244}
5245
f531dcb2
CW		 5246unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5247{
3d13ef2e 5248 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5249 unsigned long val;
5250
3d13ef2e 5251 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5252 return 0;
5253
5254 spin_lock_irq(&mchdev_lock);
5255
5256 val = __i915_chipset_val(dev_priv);
5257
5258 spin_unlock_irq(&mchdev_lock);
5259
5260 return val;
5261}
5262
eb48eb00
DV		 5263unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5264{
5265 unsigned long m, x, b;
5266 u32 tsfs;
5267
5268 tsfs = I915_READ(TSFS);
5269
5270 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5271 x = I915_READ8(TR1);
5272
5273 b = tsfs & TSFS_INTR_MASK;
5274
5275 return ((m * x) / 127) - b;
5276}
5277
d972d6ee
MK		 5278static int _pxvid_to_vd(u8 pxvid)
5279{
5280 if (pxvid == 0)
5281 return 0;
5282
5283 if (pxvid >= 8 && pxvid < 31)
5284 pxvid = 31;
5285
5286 return (pxvid + 2) * 125;
5287}
5288
5289static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5290{
3d13ef2e 5291 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5292 const int vd = _pxvid_to_vd(pxvid);
5293 const int vm = vd - 1125;
5294
3d13ef2e 5295 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5296 return vm > 0 ? vm : 0;
5297
5298 return vd;
eb48eb00
DV		 5299}
5300
02d71956 5301static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5302{
5ed0bdf2 5303 u64 now, diff, diffms;
eb48eb00
DV		 5304 u32 count;
5305
02d71956 5306 assert_spin_locked(&mchdev_lock);
eb48eb00 5307
5ed0bdf2
TG		 5308 now = ktime_get_raw_ns();
5309 diffms = now - dev_priv->ips.last_time2;
5310 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5311
5312 /* Don't divide by 0 */
eb48eb00
DV		 5313 if (!diffms)
5314 return;
5315
5316 count = I915_READ(GFXEC);
5317
20e4d407
DV		 5318 if (count < dev_priv->ips.last_count2) {
5319 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5320 diff += count;
5321 } else {
20e4d407 5322 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5323 }
5324
20e4d407
DV		 5325 dev_priv->ips.last_count2 = count;
5326 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5327
5328 /* More magic constants... */
5329 diff = diff * 1181;
5330 diff = div_u64(diff, diffms * 10);
20e4d407 5331 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5332}
5333
02d71956
DV		 5334void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5335{
3d13ef2e
DL		 5336 struct drm_device *dev = dev_priv->dev;
5337
5338 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5339 return;
5340
9270388e 5341 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5342
5343 __i915_update_gfx_val(dev_priv);
5344
9270388e 5345 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5346}
5347
f531dcb2 5348static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5349{
5350 unsigned long t, corr, state1, corr2, state2;
5351 u32 pxvid, ext_v;
5352
02d71956
DV		 5353 assert_spin_locked(&mchdev_lock);
5354
b39fb297 5355 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5356 pxvid = (pxvid >> 24) & 0x7f;
5357 ext_v = pvid_to_extvid(dev_priv, pxvid);
5358
5359 state1 = ext_v;
5360
5361 t = i915_mch_val(dev_priv);
5362
5363 /* Revel in the empirically derived constants */
5364
5365 /* Correction factor in 1/100000 units */
5366 if (t > 80)
5367 corr = ((t * 2349) + 135940);
5368 else if (t >= 50)
5369 corr = ((t * 964) + 29317);
5370 else /* < 50 */
5371 corr = ((t * 301) + 1004);
5372
5373 corr = corr * ((150142 * state1) / 10000 - 78642);
5374 corr /= 100000;
20e4d407 5375 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5376
5377 state2 = (corr2 * state1) / 10000;
5378 state2 /= 100; /* convert to mW */
5379
02d71956 5380 __i915_update_gfx_val(dev_priv);
eb48eb00 5381
20e4d407 5382 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5383}
5384
f531dcb2
CW		 5385unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5386{
3d13ef2e 5387 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5388 unsigned long val;
5389
3d13ef2e 5390 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5391 return 0;
5392
5393 spin_lock_irq(&mchdev_lock);
5394
5395 val = __i915_gfx_val(dev_priv);
5396
5397 spin_unlock_irq(&mchdev_lock);
5398
5399 return val;
5400}
5401
eb48eb00
DV		 5402/**
5403 * i915_read_mch_val - return value for IPS use
5404 *
5405 * Calculate and return a value for the IPS driver to use when deciding whether
5406 * we have thermal and power headroom to increase CPU or GPU power budget.
5407 */
5408unsigned long i915_read_mch_val(void)
5409{
5410 struct drm_i915_private *dev_priv;
5411 unsigned long chipset_val, graphics_val, ret = 0;
5412
9270388e 5413 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5414 if (!i915_mch_dev)
5415 goto out_unlock;
5416 dev_priv = i915_mch_dev;
5417
f531dcb2
CW		 5418 chipset_val = __i915_chipset_val(dev_priv);
5419 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5420
5421 ret = chipset_val + graphics_val;
5422
5423out_unlock:
9270388e 5424 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5425
5426 return ret;
5427}
5428EXPORT_SYMBOL_GPL(i915_read_mch_val);
5429
5430/**
5431 * i915_gpu_raise - raise GPU frequency limit
5432 *
5433 * Raise the limit; IPS indicates we have thermal headroom.
5434 */
5435bool i915_gpu_raise(void)
5436{
5437 struct drm_i915_private *dev_priv;
5438 bool ret = true;
5439
9270388e 5440 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5441 if (!i915_mch_dev) {
5442 ret = false;
5443 goto out_unlock;
5444 }
5445 dev_priv = i915_mch_dev;
5446
20e4d407
DV		 5447 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5448 dev_priv->ips.max_delay--;
eb48eb00
DV		 5449
5450out_unlock:
9270388e 5451 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5452
5453 return ret;
5454}
5455EXPORT_SYMBOL_GPL(i915_gpu_raise);
5456
5457/**
5458 * i915_gpu_lower - lower GPU frequency limit
5459 *
5460 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5461 * frequency maximum.
5462 */
5463bool i915_gpu_lower(void)
5464{
5465 struct drm_i915_private *dev_priv;
5466 bool ret = true;
5467
9270388e 5468 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5469 if (!i915_mch_dev) {
5470 ret = false;
5471 goto out_unlock;
5472 }
5473 dev_priv = i915_mch_dev;
5474
20e4d407
DV		 5475 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5476 dev_priv->ips.max_delay++;
eb48eb00
DV		 5477
5478out_unlock:
9270388e 5479 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5480
5481 return ret;
5482}
5483EXPORT_SYMBOL_GPL(i915_gpu_lower);
5484
5485/**
5486 * i915_gpu_busy - indicate GPU business to IPS
5487 *
5488 * Tell the IPS driver whether or not the GPU is busy.
5489 */
5490bool i915_gpu_busy(void)
5491{
5492 struct drm_i915_private *dev_priv;
a4872ba6 5493 struct intel_engine_cs *ring;
eb48eb00 5494 bool ret = false;
f047e395 5495 int i;
eb48eb00 5496
9270388e 5497 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5498 if (!i915_mch_dev)
5499 goto out_unlock;
5500 dev_priv = i915_mch_dev;
5501
f047e395
CW		 5502 for_each_ring(ring, dev_priv, i)
5503 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5504
5505out_unlock:
9270388e 5506 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5507
5508 return ret;
5509}
5510EXPORT_SYMBOL_GPL(i915_gpu_busy);
5511
5512/**
5513 * i915_gpu_turbo_disable - disable graphics turbo
5514 *
5515 * Disable graphics turbo by resetting the max frequency and setting the
5516 * current frequency to the default.
5517 */
5518bool i915_gpu_turbo_disable(void)
5519{
5520 struct drm_i915_private *dev_priv;
5521 bool ret = true;
5522
9270388e 5523 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5524 if (!i915_mch_dev) {
5525 ret = false;
5526 goto out_unlock;
5527 }
5528 dev_priv = i915_mch_dev;
5529
20e4d407 5530 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5531
20e4d407 5532 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5533 ret = false;
5534
5535out_unlock:
9270388e 5536 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5537
5538 return ret;
5539}
5540EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5541
5542/**
5543 * Tells the intel_ips driver that the i915 driver is now loaded, if
5544 * IPS got loaded first.
5545 *
5546 * This awkward dance is so that neither module has to depend on the
5547 * other in order for IPS to do the appropriate communication of
5548 * GPU turbo limits to i915.
5549 */
5550static void
5551ips_ping_for_i915_load(void)
5552{
5553 void (*link)(void);
5554
5555 link = symbol_get(ips_link_to_i915_driver);
5556 if (link) {
5557 link();
5558 symbol_put(ips_link_to_i915_driver);
5559 }
5560}
5561
5562void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5563{
02d71956
DV		 5564 /* We only register the i915 ips part with intel-ips once everything is
5565 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5566 spin_lock_irq(&mchdev_lock);
eb48eb00 5567 i915_mch_dev = dev_priv;
9270388e 5568 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5569
5570 ips_ping_for_i915_load();
5571}
5572
5573void intel_gpu_ips_teardown(void)
5574{
9270388e 5575 spin_lock_irq(&mchdev_lock);
eb48eb00 5576 i915_mch_dev = NULL;
9270388e 5577 spin_unlock_irq(&mchdev_lock);
eb48eb00 5578}
76c3552f 5579
8090c6b9 5580static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5581{
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5583 u32 lcfuse;
5584 u8 pxw[16];
5585 int i;
5586
5587 /* Disable to program */
5588 I915_WRITE(ECR, 0);
5589 POSTING_READ(ECR);
5590
5591 /* Program energy weights for various events */
5592 I915_WRITE(SDEW, 0x15040d00);
5593 I915_WRITE(CSIEW0, 0x007f0000);
5594 I915_WRITE(CSIEW1, 0x1e220004);
5595 I915_WRITE(CSIEW2, 0x04000004);
5596
5597 for (i = 0; i < 5; i++)
5598 I915_WRITE(PEW + (i * 4), 0);
5599 for (i = 0; i < 3; i++)
5600 I915_WRITE(DEW + (i * 4), 0);
5601
5602 /* Program P-state weights to account for frequency power adjustment */
5603 for (i = 0; i < 16; i++) {
5604 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5605 unsigned long freq = intel_pxfreq(pxvidfreq);
5606 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5607 PXVFREQ_PX_SHIFT;
5608 unsigned long val;
5609
5610 val = vid * vid;
5611 val *= (freq / 1000);
5612 val *= 255;
5613 val /= (127*127*900);
5614 if (val > 0xff)
5615 DRM_ERROR("bad pxval: %ld\n", val);
5616 pxw[i] = val;
5617 }
5618 /* Render standby states get 0 weight */
5619 pxw[14] = 0;
5620 pxw[15] = 0;
5621
5622 for (i = 0; i < 4; i++) {
5623 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5624 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5625 I915_WRITE(PXW + (i * 4), val);
5626 }
5627
5628 /* Adjust magic regs to magic values (more experimental results) */
5629 I915_WRITE(OGW0, 0);
5630 I915_WRITE(OGW1, 0);
5631 I915_WRITE(EG0, 0x00007f00);
5632 I915_WRITE(EG1, 0x0000000e);
5633 I915_WRITE(EG2, 0x000e0000);
5634 I915_WRITE(EG3, 0x68000300);
5635 I915_WRITE(EG4, 0x42000000);
5636 I915_WRITE(EG5, 0x00140031);
5637 I915_WRITE(EG6, 0);
5638 I915_WRITE(EG7, 0);
5639
5640 for (i = 0; i < 8; i++)
5641 I915_WRITE(PXWL + (i * 4), 0);
5642
5643 /* Enable PMON + select events */
5644 I915_WRITE(ECR, 0x80000019);
5645
5646 lcfuse = I915_READ(LCFUSE02);
5647
20e4d407 5648 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5649}
5650
ae48434c
ID		 5651void intel_init_gt_powersave(struct drm_device *dev)
5652{
e6069ca8
ID		 5653 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5654
38807746
D		 5655 if (IS_CHERRYVIEW(dev))
5656 cherryview_init_gt_powersave(dev);
5657 else if (IS_VALLEYVIEW(dev))
4e80519e 5658 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5659}
5660
5661void intel_cleanup_gt_powersave(struct drm_device *dev)
5662{
38807746
D		 5663 if (IS_CHERRYVIEW(dev))
5664 return;
5665 else if (IS_VALLEYVIEW(dev))
4e80519e 5666 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5667}
5668
dbea3cea
ID		 5669static void gen6_suspend_rps(struct drm_device *dev)
5670{
5671 struct drm_i915_private *dev_priv = dev->dev_private;
5672
5673 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5674
4c2a8897 5675 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 5676}
5677
156c7ca0
JB		 5678/**
5679 * intel_suspend_gt_powersave - suspend PM work and helper threads
5680 * @dev: drm device
5681 *
5682 * We don't want to disable RC6 or other features here, we just want
5683 * to make sure any work we've queued has finished and won't bother
5684 * us while we're suspended.
5685 */
5686void intel_suspend_gt_powersave(struct drm_device *dev)
5687{
5688 struct drm_i915_private *dev_priv = dev->dev_private;
5689
d4d70aa5
ID		 5690 if (INTEL_INFO(dev)->gen < 6)
5691 return;
5692
dbea3cea 5693 gen6_suspend_rps(dev);
b47adc17
D		 5694
5695 /* Force GPU to min freq during suspend */
5696 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5697}
5698
8090c6b9
DV		 5699void intel_disable_gt_powersave(struct drm_device *dev)
5700{
1a01ab3b
JB		 5701 struct drm_i915_private *dev_priv = dev->dev_private;
5702
930ebb46 5703 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5704 ironlake_disable_drps(dev);
38807746 5705 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5706 intel_suspend_gt_powersave(dev);
e494837a 5707
4fc688ce 5708 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5709 if (INTEL_INFO(dev)->gen >= 9)
5710 gen9_disable_rps(dev);
5711 else if (IS_CHERRYVIEW(dev))
38807746
D		 5712 cherryview_disable_rps(dev);
5713 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5714 valleyview_disable_rps(dev);
5715 else
5716 gen6_disable_rps(dev);
e534770a 5717
c0951f0c 5718 dev_priv->rps.enabled = false;
4fc688ce 5719 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5720 }
8090c6b9
DV		 5721}
5722
1a01ab3b
JB		 5723static void intel_gen6_powersave_work(struct work_struct *work)
5724{
5725 struct drm_i915_private *dev_priv =
5726 container_of(work, struct drm_i915_private,
5727 rps.delayed_resume_work.work);
5728 struct drm_device *dev = dev_priv->dev;
5729
4fc688ce 5730 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5731
4c2a8897 5732 gen6_reset_rps_interrupts(dev);
3cc134e3 5733
38807746
D		 5734 if (IS_CHERRYVIEW(dev)) {
5735 cherryview_enable_rps(dev);
5736 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5737 valleyview_enable_rps(dev);
20e49366 5738 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5739 gen9_enable_rc6(dev);
20e49366 5740 gen9_enable_rps(dev);
b6fef0ef 5741 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5742 } else if (IS_BROADWELL(dev)) {
5743 gen8_enable_rps(dev);
c2bc2fc5 5744 __gen6_update_ring_freq(dev);
0a073b84
JB		 5745 } else {
5746 gen6_enable_rps(dev);
c2bc2fc5 5747 __gen6_update_ring_freq(dev);
0a073b84 5748 }
aed242ff
CW		 5749
5750 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5751 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5752
5753 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5754 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5755
c0951f0c 5756 dev_priv->rps.enabled = true;
3cc134e3 5757
4c2a8897 5758 gen6_enable_rps_interrupts(dev);
3cc134e3 5759
4fc688ce 5760 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5761
5762 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5763}
5764
8090c6b9
DV		 5765void intel_enable_gt_powersave(struct drm_device *dev)
5766{
1a01ab3b
JB		 5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768
f61018b1
YZ		 5769 /* Powersaving is controlled by the host when inside a VM */
5770 if (intel_vgpu_active(dev))
5771 return;
5772
8090c6b9 5773 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5774 mutex_lock(&dev->struct_mutex);
8090c6b9 5775 ironlake_enable_drps(dev);
8090c6b9 5776 intel_init_emon(dev);
dc1d0136 5777 mutex_unlock(&dev->struct_mutex);
38807746 5778 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5779 /*
5780 * PCU communication is slow and this doesn't need to be
5781 * done at any specific time, so do this out of our fast path
5782 * to make resume and init faster.
c6df39b5
ID		 5783 *
5784 * We depend on the HW RC6 power context save/restore
5785 * mechanism when entering D3 through runtime PM suspend. So
5786 * disable RPM until RPS/RC6 is properly setup. We can only
5787 * get here via the driver load/system resume/runtime resume
5788 * paths, so the _noresume version is enough (and in case of
5789 * runtime resume it's necessary).
1a01ab3b 5790 */
c6df39b5
ID		 5791 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5792 round_jiffies_up_relative(HZ)))
5793 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5794 }
5795}
5796
c6df39b5
ID		 5797void intel_reset_gt_powersave(struct drm_device *dev)
5798{
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800
dbea3cea
ID		 5801 if (INTEL_INFO(dev)->gen < 6)
5802 return;
5803
5804 gen6_suspend_rps(dev);
c6df39b5 5805 dev_priv->rps.enabled = false;
c6df39b5
ID		 5806}
5807
3107bd48
DV		 5808static void ibx_init_clock_gating(struct drm_device *dev)
5809{
5810 struct drm_i915_private *dev_priv = dev->dev_private;
5811
5812 /*
5813 * On Ibex Peak and Cougar Point, we need to disable clock
5814 * gating for the panel power sequencer or it will fail to
5815 * start up when no ports are active.
5816 */
5817 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5818}
5819
0e088b8f
VS		 5820static void g4x_disable_trickle_feed(struct drm_device *dev)
5821{
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 int pipe;
5824
055e393f 5825 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5826 I915_WRITE(DSPCNTR(pipe),
5827 I915_READ(DSPCNTR(pipe)) |
5828 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5829 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5830 }
5831}
5832
017636cc
VS		 5833static void ilk_init_lp_watermarks(struct drm_device *dev)
5834{
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836
5837 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5838 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5839 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5840
5841 /*
5842 * Don't touch WM1S_LP_EN here.
5843 * Doing so could cause underruns.
5844 */
5845}
5846
1fa61106 5847static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5848{
5849 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5850 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5851
f1e8fa56
DL		 5852 /*
5853 * Required for FBC
5854 * WaFbcDisableDpfcClockGating:ilk
5855 */
4d47e4f5
DL		 5856 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5857 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5858 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5859
5860 I915_WRITE(PCH_3DCGDIS0,
5861 MARIUNIT_CLOCK_GATE_DISABLE |
5862 SVSMUNIT_CLOCK_GATE_DISABLE);
5863 I915_WRITE(PCH_3DCGDIS1,
5864 VFMUNIT_CLOCK_GATE_DISABLE);
5865
6f1d69b0
ED		 5866 /*
5867 * According to the spec the following bits should be set in
5868 * order to enable memory self-refresh
5869 * The bit 22/21 of 0x42004
5870 * The bit 5 of 0x42020
5871 * The bit 15 of 0x45000
5872 */
5873 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5874 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5875 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5876 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5877 I915_WRITE(DISP_ARB_CTL,
5878 (I915_READ(DISP_ARB_CTL) |
5879 DISP_FBC_WM_DIS));
017636cc
VS		 5880
5881 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5882
5883 /*
5884 * Based on the document from hardware guys the following bits
5885 * should be set unconditionally in order to enable FBC.
5886 * The bit 22 of 0x42000
5887 * The bit 22 of 0x42004
5888 * The bit 7,8,9 of 0x42020.
5889 */
5890 if (IS_IRONLAKE_M(dev)) {
4bb35334 5891 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5892 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5893 I915_READ(ILK_DISPLAY_CHICKEN1) |
5894 ILK_FBCQ_DIS);
5895 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5896 I915_READ(ILK_DISPLAY_CHICKEN2) |
5897 ILK_DPARB_GATE);
6f1d69b0
ED		 5898 }
5899
4d47e4f5
DL		 5900 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5901
6f1d69b0
ED		 5902 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5903 I915_READ(ILK_DISPLAY_CHICKEN2) |
5904 ILK_ELPIN_409_SELECT);
5905 I915_WRITE(_3D_CHICKEN2,
5906 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5907 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5908
ecdb4eb7 5909 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5910 I915_WRITE(CACHE_MODE_0,
5911 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5912
4e04632e
AG		 5913 /* WaDisable_RenderCache_OperationalFlush:ilk */
5914 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5915
0e088b8f 5916 g4x_disable_trickle_feed(dev);
bdad2b2f 5917
3107bd48
DV		 5918 ibx_init_clock_gating(dev);
5919}
5920
5921static void cpt_init_clock_gating(struct drm_device *dev)
5922{
5923 struct drm_i915_private *dev_priv = dev->dev_private;
5924 int pipe;
3f704fa2 5925 uint32_t val;
3107bd48
DV		 5926
5927 /*
5928 * On Ibex Peak and Cougar Point, we need to disable clock
5929 * gating for the panel power sequencer or it will fail to
5930 * start up when no ports are active.
5931 */
cd664078
JB		 5932 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5933 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5934 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5935 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5936 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5937 /* The below fixes the weird display corruption, a few pixels shifted
5938 * downward, on (only) LVDS of some HP laptops with IVY.
5939 */
055e393f 5940 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5941 val = I915_READ(TRANS_CHICKEN2(pipe));
5942 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5943 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5944 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5945 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5946 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5947 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5948 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5949 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5950 }
3107bd48 5951 /* WADP0ClockGatingDisable */
055e393f 5952 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5953 I915_WRITE(TRANS_CHICKEN1(pipe),
5954 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5955 }
6f1d69b0
ED		 5956}
5957
1d7aaa0c
DV		 5958static void gen6_check_mch_setup(struct drm_device *dev)
5959{
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961 uint32_t tmp;
5962
5963 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5964 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5965 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5966 tmp);
1d7aaa0c
DV		 5967}
5968
1fa61106 5969static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5970{
5971 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5972 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5973
231e54f6 5974 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5975
5976 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5977 I915_READ(ILK_DISPLAY_CHICKEN2) |
5978 ILK_ELPIN_409_SELECT);
5979
ecdb4eb7 5980 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5981 I915_WRITE(_3D_CHICKEN,
5982 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5983
4e04632e
AG		 5984 /* WaDisable_RenderCache_OperationalFlush:snb */
5985 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5986
8d85d272
VS		 5987 /*
5988 * BSpec recoomends 8x4 when MSAA is used,
5989 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5990 *
5991 * Note that PS/WM thread counts depend on the WIZ hashing
5992 * disable bit, which we don't touch here, but it's good
5993 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5994 */
5995 I915_WRITE(GEN6_GT_MODE,
98533251 5996 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5997
017636cc 5998 ilk_init_lp_watermarks(dev);
6f1d69b0 5999
6f1d69b0 6000 I915_WRITE(CACHE_MODE_0,
50743298 6001 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6002
6003 I915_WRITE(GEN6_UCGCTL1,
6004 I915_READ(GEN6_UCGCTL1) |
6005 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6006 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6007
6008 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6009 * gating disable must be set. Failure to set it results in
6010 * flickering pixels due to Z write ordering failures after
6011 * some amount of runtime in the Mesa "fire" demo, and Unigine
6012 * Sanctuary and Tropics, and apparently anything else with
6013 * alpha test or pixel discard.
6014 *
6015 * According to the spec, bit 11 (RCCUNIT) must also be set,
6016 * but we didn't debug actual testcases to find it out.
0f846f81 6017 *
ef59318c
VS		 6018 * WaDisableRCCUnitClockGating:snb
6019 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6020 */
6021 I915_WRITE(GEN6_UCGCTL2,
6022 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6023 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6024
5eb146dd 6025 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6026 I915_WRITE(_3D_CHICKEN3,
6027 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6028
e927ecde
VS		 6029 /*
6030 * Bspec says:
6031 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6032 * 3DSTATE_SF number of SF output attributes is more than 16."
6033 */
6034 I915_WRITE(_3D_CHICKEN3,
6035 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6036
6f1d69b0
ED		 6037 /*
6038 * According to the spec the following bits should be
6039 * set in order to enable memory self-refresh and fbc:
6040 * The bit21 and bit22 of 0x42000
6041 * The bit21 and bit22 of 0x42004
6042 * The bit5 and bit7 of 0x42020
6043 * The bit14 of 0x70180
6044 * The bit14 of 0x71180
4bb35334
DL		 6045 *
6046 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6047 */
6048 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6049 I915_READ(ILK_DISPLAY_CHICKEN1) |
6050 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6051 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6052 I915_READ(ILK_DISPLAY_CHICKEN2) |
6053 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6054 I915_WRITE(ILK_DSPCLK_GATE_D,
6055 I915_READ(ILK_DSPCLK_GATE_D) |
6056 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6057 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6058
0e088b8f 6059 g4x_disable_trickle_feed(dev);
f8f2ac9a 6060
3107bd48 6061 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6062
6063 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6064}
6065
6066static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6067{
6068 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6069
3aad9059 6070 /*
46680e0a 6071 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6072 *
6073 * This actually overrides the dispatch
6074 * mode for all thread types.
6075 */
6f1d69b0
ED		 6076 reg &= ~GEN7_FF_SCHED_MASK;
6077 reg |= GEN7_FF_TS_SCHED_HW;
6078 reg |= GEN7_FF_VS_SCHED_HW;
6079 reg |= GEN7_FF_DS_SCHED_HW;
6080
6081 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6082}
6083
17a303ec
PZ		 6084static void lpt_init_clock_gating(struct drm_device *dev)
6085{
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087
6088 /*
6089 * TODO: this bit should only be enabled when really needed, then
6090 * disabled when not needed anymore in order to save power.
6091 */
6092 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6093 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6094 I915_READ(SOUTH_DSPCLK_GATE_D) |
6095 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6096
6097 /* WADPOClockGatingDisable:hsw */
6098 I915_WRITE(_TRANSA_CHICKEN1,
6099 I915_READ(_TRANSA_CHICKEN1) |
6100 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6101}
6102
7d708ee4
ID		 6103static void lpt_suspend_hw(struct drm_device *dev)
6104{
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106
6107 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6108 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6109
6110 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6111 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6112 }
6113}
6114
47c2bd97 6115static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6116{
6117 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6118 enum pipe pipe;
1020a5c2
BW		 6119
6120 I915_WRITE(WM3_LP_ILK, 0);
6121 I915_WRITE(WM2_LP_ILK, 0);
6122 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6123
ab57fff1 6124 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6125 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6126
ab57fff1 6127 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6128 I915_WRITE(CHICKEN_PAR1_1,
6129 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6130
ab57fff1 6131 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6132 for_each_pipe(dev_priv, pipe) {
07d27e20 6133 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6134 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6135 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6136 }
63801f21 6137
ab57fff1
BW		 6138 /* WaVSRefCountFullforceMissDisable:bdw */
6139 /* WaDSRefCountFullforceMissDisable:bdw */
6140 I915_WRITE(GEN7_FF_THREAD_MODE,
6141 I915_READ(GEN7_FF_THREAD_MODE) &
6142 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6143
295e8bb7
VS		 6144 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6145 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6146
6147 /* WaDisableSDEUnitClockGating:bdw */
6148 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6149 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6150
89d6b2b8 6151 lpt_init_clock_gating(dev);
1020a5c2
BW		 6152}
6153
cad2a2d7
ED		 6154static void haswell_init_clock_gating(struct drm_device *dev)
6155{
6156 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6157
017636cc 6158 ilk_init_lp_watermarks(dev);
cad2a2d7 6159
f3fc4884
FJ		 6160 /* L3 caching of data atomics doesn't work -- disable it. */
6161 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6162 I915_WRITE(HSW_ROW_CHICKEN3,
6163 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6164
ecdb4eb7 6165 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6166 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6167 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6168 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6169
e36ea7ff
VS		 6170 /* WaVSRefCountFullforceMissDisable:hsw */
6171 I915_WRITE(GEN7_FF_THREAD_MODE,
6172 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6173
4e04632e
AG		 6174 /* WaDisable_RenderCache_OperationalFlush:hsw */
6175 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6176
fe27c606
CW		 6177 /* enable HiZ Raw Stall Optimization */
6178 I915_WRITE(CACHE_MODE_0_GEN7,
6179 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6180
ecdb4eb7 6181 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6182 I915_WRITE(CACHE_MODE_1,
6183 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6184
a12c4967
VS		 6185 /*
6186 * BSpec recommends 8x4 when MSAA is used,
6187 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6188 *
6189 * Note that PS/WM thread counts depend on the WIZ hashing
6190 * disable bit, which we don't touch here, but it's good
6191 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6192 */
6193 I915_WRITE(GEN7_GT_MODE,
98533251 6194 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6195
94411593
KG		 6196 /* WaSampleCChickenBitEnable:hsw */
6197 I915_WRITE(HALF_SLICE_CHICKEN3,
6198 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6199
ecdb4eb7 6200 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6201 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6202
90a88643
PZ		 6203 /* WaRsPkgCStateDisplayPMReq:hsw */
6204 I915_WRITE(CHICKEN_PAR1_1,
6205 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6206
17a303ec 6207 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6208}
6209
1fa61106 6210static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6211{
6212 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6213 uint32_t snpcr;
6f1d69b0 6214
017636cc 6215 ilk_init_lp_watermarks(dev);
6f1d69b0 6216
231e54f6 6217 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6218
ecdb4eb7 6219 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6220 I915_WRITE(_3D_CHICKEN3,
6221 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6222
ecdb4eb7 6223 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6224 I915_WRITE(IVB_CHICKEN3,
6225 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6226 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6227
ecdb4eb7 6228 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6229 if (IS_IVB_GT1(dev))
6230 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6231 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6232
4e04632e
AG		 6233 /* WaDisable_RenderCache_OperationalFlush:ivb */
6234 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6235
ecdb4eb7 6236 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6237 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6238 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6239
ecdb4eb7 6240 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6241 I915_WRITE(GEN7_L3CNTLREG1,
6242 GEN7_WA_FOR_GEN7_L3_CONTROL);
6243 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6244 GEN7_WA_L3_CHICKEN_MODE);
6245 if (IS_IVB_GT1(dev))
6246 I915_WRITE(GEN7_ROW_CHICKEN2,
6247 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6248 else {
6249 /* must write both registers */
6250 I915_WRITE(GEN7_ROW_CHICKEN2,
6251 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6252 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6253 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6254 }
6f1d69b0 6255
ecdb4eb7 6256 /* WaForceL3Serialization:ivb */
61939d97
JB		 6257 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6258 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6259
1b80a19a 6260 /*
0f846f81 6261 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6262 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6263 */
6264 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6265 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6266
ecdb4eb7 6267 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6268 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6269 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6270 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6271
0e088b8f 6272 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6273
6274 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6275
22721343
CW		 6276 if (0) { /* causes HiZ corruption on ivb:gt1 */
6277 /* enable HiZ Raw Stall Optimization */
6278 I915_WRITE(CACHE_MODE_0_GEN7,
6279 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6280 }
116f2b6d 6281
ecdb4eb7 6282 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6283 I915_WRITE(CACHE_MODE_1,
6284 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6285
a607c1a4
VS		 6286 /*
6287 * BSpec recommends 8x4 when MSAA is used,
6288 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6289 *
6290 * Note that PS/WM thread counts depend on the WIZ hashing
6291 * disable bit, which we don't touch here, but it's good
6292 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6293 */
6294 I915_WRITE(GEN7_GT_MODE,
98533251 6295 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6296
20848223
BW		 6297 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6298 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6299 snpcr |= GEN6_MBC_SNPCR_MED;
6300 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6301
ab5c608b
BW		 6302 if (!HAS_PCH_NOP(dev))
6303 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6304
6305 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6306}
6307
c6beb13e
VS		 6308static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6309{
6310 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6311
6312 /*
6313 * Disable trickle feed and enable pnd deadline calculation
6314 */
6315 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6316 I915_WRITE(CBR1_VLV, 0);
6317}
6318
1fa61106 6319static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6320{
6321 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6322
c6beb13e 6323 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6324
ecdb4eb7 6325 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6326 I915_WRITE(_3D_CHICKEN3,
6327 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6328
ecdb4eb7 6329 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6330 I915_WRITE(IVB_CHICKEN3,
6331 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6332 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6333
fad7d36e 6334 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6335 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6336 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6337 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6338 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6339
4e04632e
AG		 6340 /* WaDisable_RenderCache_OperationalFlush:vlv */
6341 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6342
ecdb4eb7 6343 /* WaForceL3Serialization:vlv */
61939d97
JB		 6344 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6345 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6346
ecdb4eb7 6347 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6348 I915_WRITE(GEN7_ROW_CHICKEN2,
6349 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6350
ecdb4eb7 6351 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6352 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6353 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6354 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6355
46680e0a
VS		 6356 gen7_setup_fixed_func_scheduler(dev_priv);
6357
3c0edaeb 6358 /*
0f846f81 6359 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6360 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6361 */
6362 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6363 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6364
c98f5062
AG		 6365 /* WaDisableL3Bank2xClockGate:vlv
6366 * Disabling L3 clock gating- MMIO 940c[25] = 1
6367 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6368 I915_WRITE(GEN7_UCGCTL4,
6369 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6370
afd58e79
VS		 6371 /*
6372 * BSpec says this must be set, even though
6373 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6374 */
6b26c86d
DV		 6375 I915_WRITE(CACHE_MODE_1,
6376 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6377
da2518f9
VS		 6378 /*
6379 * BSpec recommends 8x4 when MSAA is used,
6380 * however in practice 16x4 seems fastest.
6381 *
6382 * Note that PS/WM thread counts depend on the WIZ hashing
6383 * disable bit, which we don't touch here, but it's good
6384 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6385 */
6386 I915_WRITE(GEN7_GT_MODE,
6387 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6388
031994ee
VS		 6389 /*
6390 * WaIncreaseL3CreditsForVLVB0:vlv
6391 * This is the hardware default actually.
6392 */
6393 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6394
2d809570 6395 /*
ecdb4eb7 6396 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6397 * Disable clock gating on th GCFG unit to prevent a delay
6398 * in the reporting of vblank events.
6399 */
7a0d1eed 6400 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6401}
6402
a4565da8
VS		 6403static void cherryview_init_clock_gating(struct drm_device *dev)
6404{
6405 struct drm_i915_private *dev_priv = dev->dev_private;
6406
c6beb13e 6407 vlv_init_display_clock_gating(dev_priv);
dd811e70 6408
232ce337
VS		 6409 /* WaVSRefCountFullforceMissDisable:chv */
6410 /* WaDSRefCountFullforceMissDisable:chv */
6411 I915_WRITE(GEN7_FF_THREAD_MODE,
6412 I915_READ(GEN7_FF_THREAD_MODE) &
6413 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6414
6415 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6416 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6417 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6418
6419 /* WaDisableCSUnitClockGating:chv */
6420 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6421 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6422
6423 /* WaDisableSDEUnitClockGating:chv */
6424 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6425 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6426}
6427
1fa61106 6428static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6429{
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 uint32_t dspclk_gate;
6432
6433 I915_WRITE(RENCLK_GATE_D1, 0);
6434 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6435 GS_UNIT_CLOCK_GATE_DISABLE |
6436 CL_UNIT_CLOCK_GATE_DISABLE);
6437 I915_WRITE(RAMCLK_GATE_D, 0);
6438 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6439 OVRUNIT_CLOCK_GATE_DISABLE |
6440 OVCUNIT_CLOCK_GATE_DISABLE;
6441 if (IS_GM45(dev))
6442 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6443 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6444
6445 /* WaDisableRenderCachePipelinedFlush */
6446 I915_WRITE(CACHE_MODE_0,
6447 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6448
4e04632e
AG		 6449 /* WaDisable_RenderCache_OperationalFlush:g4x */
6450 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6451
0e088b8f 6452 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6453}
6454
1fa61106 6455static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6456{
6457 struct drm_i915_private *dev_priv = dev->dev_private;
6458
6459 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6460 I915_WRITE(RENCLK_GATE_D2, 0);
6461 I915_WRITE(DSPCLK_GATE_D, 0);
6462 I915_WRITE(RAMCLK_GATE_D, 0);
6463 I915_WRITE16(DEUC, 0);
20f94967
VS		 6464 I915_WRITE(MI_ARB_STATE,
6465 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6466
6467 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6468 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6469}
6470
1fa61106 6471static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6472{
6473 struct drm_i915_private *dev_priv = dev->dev_private;
6474
6475 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6476 I965_RCC_CLOCK_GATE_DISABLE |
6477 I965_RCPB_CLOCK_GATE_DISABLE |
6478 I965_ISC_CLOCK_GATE_DISABLE |
6479 I965_FBC_CLOCK_GATE_DISABLE);
6480 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6481 I915_WRITE(MI_ARB_STATE,
6482 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6483
6484 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6485 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6486}
6487
1fa61106 6488static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6489{
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 u32 dstate = I915_READ(D_STATE);
6492
6493 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6494 DSTATE_DOT_CLOCK_GATING;
6495 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6496
6497 if (IS_PINEVIEW(dev))
6498 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6499
6500 /* IIR "flip pending" means done if this bit is set */
6501 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6502
6503 /* interrupts should cause a wake up from C3 */
3299254f 6504 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6505
6506 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6507 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6508
6509 I915_WRITE(MI_ARB_STATE,
6510 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6511}
6512
1fa61106 6513static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6514{
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516
6517 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6518
6519 /* interrupts should cause a wake up from C3 */
6520 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6521 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6522
6523 I915_WRITE(MEM_MODE,
6524 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6525}
6526
1fa61106 6527static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6528{
6529 struct drm_i915_private *dev_priv = dev->dev_private;
6530
6531 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6532
6533 I915_WRITE(MEM_MODE,
6534 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6535 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6536}
6537
6f1d69b0
ED		 6538void intel_init_clock_gating(struct drm_device *dev)
6539{
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541
c57e3551
DL		 6542 if (dev_priv->display.init_clock_gating)
6543 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6544}
6545
7d708ee4
ID		 6546void intel_suspend_hw(struct drm_device *dev)
6547{
6548 if (HAS_PCH_LPT(dev))
6549 lpt_suspend_hw(dev);
6550}
6551
1fa61106
ED		 6552/* Set up chip specific power management-related functions */
6553void intel_init_pm(struct drm_device *dev)
6554{
6555 struct drm_i915_private *dev_priv = dev->dev_private;
6556
7ff0ebcc 6557 intel_fbc_init(dev_priv);
1fa61106 6558
c921aba8
DV		 6559 /* For cxsr */
6560 if (IS_PINEVIEW(dev))
6561 i915_pineview_get_mem_freq(dev);
6562 else if (IS_GEN5(dev))
6563 i915_ironlake_get_mem_freq(dev);
6564
1fa61106 6565 /* For FIFO watermark updates */
f5ed50cb 6566 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6567 skl_setup_wm_latency(dev);
6568
a82abe43
ID		 6569 if (IS_BROXTON(dev))
6570 dev_priv->display.init_clock_gating =
6571 bxt_init_clock_gating;
6572 else if (IS_SKYLAKE(dev))
6573 dev_priv->display.init_clock_gating =
6574 skl_init_clock_gating;
2d41c0b5
PB		 6575 dev_priv->display.update_wm = skl_update_wm;
6576 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6577 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6578 ilk_setup_wm_latency(dev);
53615a5e 6579
bd602544
VS		 6580 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6581 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6582 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6583 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6584 dev_priv->display.update_wm = ilk_update_wm;
6585 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6586 } else {
6587 DRM_DEBUG_KMS("Failed to read display plane latency. "
6588 "Disable CxSR\n");
6589 }
6590
6591 if (IS_GEN5(dev))
1fa61106 6592 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6593 else if (IS_GEN6(dev))
1fa61106 6594 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6595 else if (IS_IVYBRIDGE(dev))
1fa61106 6596 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6597 else if (IS_HASWELL(dev))
cad2a2d7 6598 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6599 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6600 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6601 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6602 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6603 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6604 dev_priv->display.init_clock_gating =
6605 cherryview_init_clock_gating;
1fa61106
ED		 6606 } else if (IS_VALLEYVIEW(dev)) {
6607 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6608 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6609 dev_priv->display.init_clock_gating =
6610 valleyview_init_clock_gating;
1fa61106
ED		 6611 } else if (IS_PINEVIEW(dev)) {
6612 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6613 dev_priv->is_ddr3,
6614 dev_priv->fsb_freq,
6615 dev_priv->mem_freq)) {
6616 DRM_INFO("failed to find known CxSR latency "
6617 "(found ddr%s fsb freq %d, mem freq %d), "
6618 "disabling CxSR\n",
6619 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6620 dev_priv->fsb_freq, dev_priv->mem_freq);
6621 /* Disable CxSR and never update its watermark again */
5209b1f4 6622 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6623 dev_priv->display.update_wm = NULL;
6624 } else
6625 dev_priv->display.update_wm = pineview_update_wm;
6626 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6627 } else if (IS_G4X(dev)) {
6628 dev_priv->display.update_wm = g4x_update_wm;
6629 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6630 } else if (IS_GEN4(dev)) {
6631 dev_priv->display.update_wm = i965_update_wm;
6632 if (IS_CRESTLINE(dev))
6633 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6634 else if (IS_BROADWATER(dev))
6635 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6636 } else if (IS_GEN3(dev)) {
6637 dev_priv->display.update_wm = i9xx_update_wm;
6638 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6639 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6640 } else if (IS_GEN2(dev)) {
6641 if (INTEL_INFO(dev)->num_pipes == 1) {
6642 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6643 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6644 } else {
6645 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6646 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6647 }
6648
6649 if (IS_I85X(dev) || IS_I865G(dev))
6650 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6651 else
6652 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6653 } else {
6654 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6655 }
6656}
6657
151a49d0 6658int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6659{
4fc688ce 6660 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6661
6662 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6663 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6664 return -EAGAIN;
6665 }
6666
6667 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6668 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6669 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6670
6671 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6672 500)) {
6673 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6674 return -ETIMEDOUT;
6675 }
6676
6677 *val = I915_READ(GEN6_PCODE_DATA);
6678 I915_WRITE(GEN6_PCODE_DATA, 0);
6679
6680 return 0;
6681}
6682
151a49d0 6683int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6684{
4fc688ce 6685 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6686
6687 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6688 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6689 return -EAGAIN;
6690 }
6691
6692 I915_WRITE(GEN6_PCODE_DATA, val);
6693 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6694
6695 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6696 500)) {
6697 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6698 return -ETIMEDOUT;
6699 }
6700
6701 I915_WRITE(GEN6_PCODE_DATA, 0);
6702
6703 return 0;
6704}
a0e4e199 6705
dd06f88c 6706static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6707{
dd06f88c
VS		 6708 switch (czclk_freq) {
6709 case 200:
6710 return 10;
6711 case 267:
6712 return 12;
6713 case 320:
6714 case 333:
dd06f88c 6715 return 16;
ab3fb157
VS		 6716 case 400:
6717 return 20;
855ba3be
JB		 6718 default:
6719 return -1;
6720 }
dd06f88c 6721}
855ba3be 6722
dd06f88c
VS		 6723static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6724{
6725 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6726
6727 div = vlv_gpu_freq_div(czclk_freq);
6728 if (div < 0)
6729 return div;
6730
6731 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6732}
6733
b55dd647 6734static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6735{
dd06f88c 6736 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6737
dd06f88c
VS		 6738 mul = vlv_gpu_freq_div(czclk_freq);
6739 if (mul < 0)
6740 return mul;
855ba3be 6741
dd06f88c 6742 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6743}
6744
b55dd647 6745static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6746{
dd06f88c 6747 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6748
dd06f88c
VS		 6749 div = vlv_gpu_freq_div(czclk_freq) / 2;
6750 if (div < 0)
6751 return div;
22b1b2f8 6752
dd06f88c 6753 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6754}
6755
b55dd647 6756static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6757{
dd06f88c 6758 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6759
dd06f88c
VS		 6760 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6761 if (mul < 0)
6762 return mul;
22b1b2f8 6763
1c14762d 6764 /* CHV needs even values */
dd06f88c 6765 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6766}
6767
616bc820 6768int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6769{
80b6dda4
AG		 6770 if (IS_GEN9(dev_priv->dev))
6771 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6772 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6773 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6774 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6775 return byt_gpu_freq(dev_priv, val);
6776 else
6777 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6778}
6779
616bc820
VS		 6780int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6781{
80b6dda4
AG		 6782 if (IS_GEN9(dev_priv->dev))
6783 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6784 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6785 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6786 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6787 return byt_freq_opcode(dev_priv, val);
6788 else
6789 return val / GT_FREQUENCY_MULTIPLIER;
6790}
22b1b2f8 6791
f742a552 6792void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6793{
6794 struct drm_i915_private *dev_priv = dev->dev_private;
6795
f742a552
DV		 6796 mutex_init(&dev_priv->rps.hw_lock);
6797
907b28c5
CW		 6798 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6799 intel_gen6_powersave_work);
5d584b2e 6800
33688d95 6801 dev_priv->pm.suspended = false;
907b28c5 6802}
Linux kernel - Deliverables
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