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drm/i915: Naming constants to be written to GEN9_PG_ENABLE
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
669506e7 70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 82 }
8bc0ccf6 83
2caa3b26 84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
2caa3b26
DL		 89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
91 I915_READ(FF_SLICE_CS_CHICKEN2) |
92 GEN9_TSG_BARRIER_ACK_DISABLE);
93 }
81e231af 94
8bc0ccf6
DL		 95 if (INTEL_REVID(dev) <= SKL_REVID_E0)
96 /* WaDisableLSQCROPERFforOCL:skl */
97 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
98 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 99}
100
c921aba8
DV		 101static void i915_pineview_get_mem_freq(struct drm_device *dev)
102{
50227e1c 103 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 104 u32 tmp;
105
106 tmp = I915_READ(CLKCFG);
107
108 switch (tmp & CLKCFG_FSB_MASK) {
109 case CLKCFG_FSB_533:
110 dev_priv->fsb_freq = 533; /* 133*4 */
111 break;
112 case CLKCFG_FSB_800:
113 dev_priv->fsb_freq = 800; /* 200*4 */
114 break;
115 case CLKCFG_FSB_667:
116 dev_priv->fsb_freq = 667; /* 167*4 */
117 break;
118 case CLKCFG_FSB_400:
119 dev_priv->fsb_freq = 400; /* 100*4 */
120 break;
121 }
122
123 switch (tmp & CLKCFG_MEM_MASK) {
124 case CLKCFG_MEM_533:
125 dev_priv->mem_freq = 533;
126 break;
127 case CLKCFG_MEM_667:
128 dev_priv->mem_freq = 667;
129 break;
130 case CLKCFG_MEM_800:
131 dev_priv->mem_freq = 800;
132 break;
133 }
134
135 /* detect pineview DDR3 setting */
136 tmp = I915_READ(CSHRDDR3CTL);
137 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
138}
139
140static void i915_ironlake_get_mem_freq(struct drm_device *dev)
141{
50227e1c 142 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 143 u16 ddrpll, csipll;
144
145 ddrpll = I915_READ16(DDRMPLL1);
146 csipll = I915_READ16(CSIPLL0);
147
148 switch (ddrpll & 0xff) {
149 case 0xc:
150 dev_priv->mem_freq = 800;
151 break;
152 case 0x10:
153 dev_priv->mem_freq = 1066;
154 break;
155 case 0x14:
156 dev_priv->mem_freq = 1333;
157 break;
158 case 0x18:
159 dev_priv->mem_freq = 1600;
160 break;
161 default:
162 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
163 ddrpll & 0xff);
164 dev_priv->mem_freq = 0;
165 break;
166 }
167
20e4d407 168 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 169
170 switch (csipll & 0x3ff) {
171 case 0x00c:
172 dev_priv->fsb_freq = 3200;
173 break;
174 case 0x00e:
175 dev_priv->fsb_freq = 3733;
176 break;
177 case 0x010:
178 dev_priv->fsb_freq = 4266;
179 break;
180 case 0x012:
181 dev_priv->fsb_freq = 4800;
182 break;
183 case 0x014:
184 dev_priv->fsb_freq = 5333;
185 break;
186 case 0x016:
187 dev_priv->fsb_freq = 5866;
188 break;
189 case 0x018:
190 dev_priv->fsb_freq = 6400;
191 break;
192 default:
193 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
194 csipll & 0x3ff);
195 dev_priv->fsb_freq = 0;
196 break;
197 }
198
199 if (dev_priv->fsb_freq == 3200) {
20e4d407 200 dev_priv->ips.c_m = 0;
c921aba8 201 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 202 dev_priv->ips.c_m = 1;
c921aba8 203 } else {
20e4d407 204 dev_priv->ips.c_m = 2;
c921aba8
DV		 205 }
206}
207
b445e3b0
ED		 208static const struct cxsr_latency cxsr_latency_table[] = {
209 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
210 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
211 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
212 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
213 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
214
215 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
216 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
217 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
218 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
219 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
220
221 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
222 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
223 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
224 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
225 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
226
227 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
228 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
229 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
230 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
231 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
232
233 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
234 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
235 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
236 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
237 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
238
239 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
240 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
241 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
242 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
243 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
244};
245
63c62275 246static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 247 int is_ddr3,
248 int fsb,
249 int mem)
250{
251 const struct cxsr_latency *latency;
252 int i;
253
254 if (fsb == 0 || mem == 0)
255 return NULL;
256
257 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
258 latency = &cxsr_latency_table[i];
259 if (is_desktop == latency->is_desktop &&
260 is_ddr3 == latency->is_ddr3 &&
261 fsb == latency->fsb_freq && mem == latency->mem_freq)
262 return latency;
263 }
264
265 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
266
267 return NULL;
268}
269
fc1ac8de
VS		 270static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
271{
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
277 if (enable)
278 val &= ~FORCE_DDR_HIGH_FREQ;
279 else
280 val |= FORCE_DDR_HIGH_FREQ;
281 val &= ~FORCE_DDR_LOW_FREQ;
282 val |= FORCE_DDR_FREQ_REQ_ACK;
283 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
284
285 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
286 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
287 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
288
289 mutex_unlock(&dev_priv->rps.hw_lock);
290}
291
cfb41411
VS		 292static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
293{
294 u32 val;
295
296 mutex_lock(&dev_priv->rps.hw_lock);
297
298 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
299 if (enable)
300 val |= DSP_MAXFIFO_PM5_ENABLE;
301 else
302 val &= ~DSP_MAXFIFO_PM5_ENABLE;
303 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
304
305 mutex_unlock(&dev_priv->rps.hw_lock);
306}
307
f4998963
VS		 308#define FW_WM(value, plane) \
309 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
310
5209b1f4 311void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 312{
5209b1f4
ID		 313 struct drm_device *dev = dev_priv->dev;
314 u32 val;
b445e3b0 315
5209b1f4
ID		 316 if (IS_VALLEYVIEW(dev)) {
317 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS		 318 if (IS_CHERRYVIEW(dev))
319 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID		 320 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
321 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
322 } else if (IS_PINEVIEW(dev)) {
323 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
324 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
325 I915_WRITE(DSPFW3, val);
326 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
327 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
328 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
329 I915_WRITE(FW_BLC_SELF, val);
330 } else if (IS_I915GM(dev)) {
331 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
332 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
333 I915_WRITE(INSTPM, val);
334 } else {
335 return;
336 }
b445e3b0 337
5209b1f4
ID		 338 DRM_DEBUG_KMS("memory self-refresh is %s\n",
339 enable ? "enabled" : "disabled");
b445e3b0
ED		 340}
341
fc1ac8de 342
b445e3b0
ED		 343/*
344 * Latency for FIFO fetches is dependent on several factors:
345 * - memory configuration (speed, channels)
346 * - chipset
347 * - current MCH state
348 * It can be fairly high in some situations, so here we assume a fairly
349 * pessimal value. It's a tradeoff between extra memory fetches (if we
350 * set this value too high, the FIFO will fetch frequently to stay full)
351 * and power consumption (set it too low to save power and we might see
352 * FIFO underruns and display "flicker").
353 *
354 * A value of 5us seems to be a good balance; safe for very low end
355 * platforms but not overly aggressive on lower latency configs.
356 */
5aef6003 357static const int pessimal_latency_ns = 5000;
b445e3b0 358
b5004720
VS		 359#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
360 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
361
362static int vlv_get_fifo_size(struct drm_device *dev,
363 enum pipe pipe, int plane)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 int sprite0_start, sprite1_start, size;
367
368 switch (pipe) {
369 uint32_t dsparb, dsparb2, dsparb3;
370 case PIPE_A:
371 dsparb = I915_READ(DSPARB);
372 dsparb2 = I915_READ(DSPARB2);
373 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
374 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
375 break;
376 case PIPE_B:
377 dsparb = I915_READ(DSPARB);
378 dsparb2 = I915_READ(DSPARB2);
379 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
380 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
381 break;
382 case PIPE_C:
383 dsparb2 = I915_READ(DSPARB2);
384 dsparb3 = I915_READ(DSPARB3);
385 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
386 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
387 break;
388 default:
389 return 0;
390 }
391
392 switch (plane) {
393 case 0:
394 size = sprite0_start;
395 break;
396 case 1:
397 size = sprite1_start - sprite0_start;
398 break;
399 case 2:
400 size = 512 - 1 - sprite1_start;
401 break;
402 default:
403 return 0;
404 }
405
406 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
407 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
408 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
409 size);
410
411 return size;
412}
413
1fa61106 414static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x7f;
421 if (plane)
422 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
423
424 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
425 plane ? "B" : "A", size);
426
427 return size;
428}
429
feb56b93 430static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 431{
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 uint32_t dsparb = I915_READ(DSPARB);
434 int size;
435
436 size = dsparb & 0x1ff;
437 if (plane)
438 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
439 size >>= 1; /* Convert to cachelines */
440
441 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
442 plane ? "B" : "A", size);
443
444 return size;
445}
446
1fa61106 447static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 448{
449 struct drm_i915_private *dev_priv = dev->dev_private;
450 uint32_t dsparb = I915_READ(DSPARB);
451 int size;
452
453 size = dsparb & 0x7f;
454 size >>= 2; /* Convert to cachelines */
455
456 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
457 plane ? "B" : "A",
458 size);
459
460 return size;
461}
462
b445e3b0
ED		 463/* Pineview has different values for various configs */
464static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 465 .fifo_size = PINEVIEW_DISPLAY_FIFO,
466 .max_wm = PINEVIEW_MAX_WM,
467 .default_wm = PINEVIEW_DFT_WM,
468 .guard_size = PINEVIEW_GUARD_WM,
469 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 470};
471static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 472 .fifo_size = PINEVIEW_DISPLAY_FIFO,
473 .max_wm = PINEVIEW_MAX_WM,
474 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
475 .guard_size = PINEVIEW_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 477};
478static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 479 .fifo_size = PINEVIEW_CURSOR_FIFO,
480 .max_wm = PINEVIEW_CURSOR_MAX_WM,
481 .default_wm = PINEVIEW_CURSOR_DFT_WM,
482 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 484};
485static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 486 .fifo_size = PINEVIEW_CURSOR_FIFO,
487 .max_wm = PINEVIEW_CURSOR_MAX_WM,
488 .default_wm = PINEVIEW_CURSOR_DFT_WM,
489 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 491};
492static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 493 .fifo_size = G4X_FIFO_SIZE,
494 .max_wm = G4X_MAX_WM,
495 .default_wm = G4X_MAX_WM,
496 .guard_size = 2,
497 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 498};
499static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 500 .fifo_size = I965_CURSOR_FIFO,
501 .max_wm = I965_CURSOR_MAX_WM,
502 .default_wm = I965_CURSOR_DFT_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 505};
506static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 507 .fifo_size = VALLEYVIEW_FIFO_SIZE,
508 .max_wm = VALLEYVIEW_MAX_WM,
509 .default_wm = VALLEYVIEW_MAX_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 512};
513static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 519};
520static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 521 .fifo_size = I965_CURSOR_FIFO,
522 .max_wm = I965_CURSOR_MAX_WM,
523 .default_wm = I965_CURSOR_DFT_WM,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 526};
527static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 528 .fifo_size = I945_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 533};
534static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 535 .fifo_size = I915_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 540};
9d539105 541static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 547};
9d539105
VS		 548static const struct intel_watermark_params i830_bc_wm_info = {
549 .fifo_size = I855GM_FIFO_SIZE,
550 .max_wm = I915_MAX_WM/2,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
554};
feb56b93 555static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 556 .fifo_size = I830_FIFO_SIZE,
557 .max_wm = I915_MAX_WM,
558 .default_wm = 1,
559 .guard_size = 2,
560 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 561};
562
b445e3b0
ED		 563/**
564 * intel_calculate_wm - calculate watermark level
565 * @clock_in_khz: pixel clock
566 * @wm: chip FIFO params
567 * @pixel_size: display pixel size
568 * @latency_ns: memory latency for the platform
569 *
570 * Calculate the watermark level (the level at which the display plane will
571 * start fetching from memory again). Each chip has a different display
572 * FIFO size and allocation, so the caller needs to figure that out and pass
573 * in the correct intel_watermark_params structure.
574 *
575 * As the pixel clock runs, the FIFO will be drained at a rate that depends
576 * on the pixel size. When it reaches the watermark level, it'll start
577 * fetching FIFO line sized based chunks from memory until the FIFO fills
578 * past the watermark point. If the FIFO drains completely, a FIFO underrun
579 * will occur, and a display engine hang could result.
580 */
581static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
582 const struct intel_watermark_params *wm,
583 int fifo_size,
584 int pixel_size,
585 unsigned long latency_ns)
586{
587 long entries_required, wm_size;
588
589 /*
590 * Note: we need to make sure we don't overflow for various clock &
591 * latency values.
592 * clocks go from a few thousand to several hundred thousand.
593 * latency is usually a few thousand
594 */
595 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
596 1000;
597 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
598
599 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
600
601 wm_size = fifo_size - (entries_required + wm->guard_size);
602
603 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
604
605 /* Don't promote wm_size to unsigned... */
606 if (wm_size > (long)wm->max_wm)
607 wm_size = wm->max_wm;
608 if (wm_size <= 0)
609 wm_size = wm->default_wm;
d6feb196
VS		 610
611 /*
612 * Bspec seems to indicate that the value shouldn't be lower than
613 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
614 * Lets go for 8 which is the burst size since certain platforms
615 * already use a hardcoded 8 (which is what the spec says should be
616 * done).
617 */
618 if (wm_size <= 8)
619 wm_size = 8;
620
b445e3b0
ED		 621 return wm_size;
622}
623
624static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
625{
626 struct drm_crtc *crtc, *enabled = NULL;
627
70e1e0ec 628 for_each_crtc(dev, crtc) {
3490ea5d 629 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 630 if (enabled)
631 return NULL;
632 enabled = crtc;
633 }
634 }
635
636 return enabled;
637}
638
46ba614c 639static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 640{
46ba614c 641 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 642 struct drm_i915_private *dev_priv = dev->dev_private;
643 struct drm_crtc *crtc;
644 const struct cxsr_latency *latency;
645 u32 reg;
646 unsigned long wm;
647
648 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
649 dev_priv->fsb_freq, dev_priv->mem_freq);
650 if (!latency) {
651 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 652 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 653 return;
654 }
655
656 crtc = single_enabled_crtc(dev);
657 if (crtc) {
241bfc38 658 const struct drm_display_mode *adjusted_mode;
59bea882 659 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 660 int clock;
661
6e3c9717 662 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 663 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
668 pixel_size, latency->display_sr);
669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
678 pixel_size, latency->cursor_sr);
679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
687 pixel_size, latency->display_hpll_disable);
688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
696 pixel_size, latency->cursor_hpll_disable);
697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 720 int htotal, hdisplay, clock, pixel_size;
721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 735 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
738 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 750 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 806 int hdisplay, htotal, pixel_size, clock;
807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 822 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
826 line_size = hdisplay * pixel_size;
827
828 /* Use the minimum of the small and large buffer method for primary */
829 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
3dd512fb 836 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
907 POSTING_READ(DSPFW1);
908
0018fda1
VS		 909 dev_priv->wm.vlv = *wm;
910}
911
15665979
VS		 912#undef FW_WM_VLV
913
341c526f 914static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 915 struct drm_plane *plane)
b445e3b0 916{
5e56ba45 917 struct drm_device *dev = crtc->dev;
883a3d2f
VS		 918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
919 int entries, prec_mult, drain_latency, pixel_size;
920 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 921 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 922
883a3d2f
VS		 923 /*
924 * FIXME the plane might have an fb
925 * but be invisible (eg. due to clipping)
926 */
927 if (!intel_crtc->active || !plane->state->fb)
928 return 0;
929
0948c265 930 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 931 return 0;
b445e3b0 932
883a3d2f
VS		 933 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
934
0948c265 935 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 936 return 0;
b445e3b0 937
a398e9c7 938 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 939
341c526f
VS		 940 prec_mult = high_precision;
941 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 942
341c526f
VS		 943 if (drain_latency > DRAIN_LATENCY_MASK) {
944 prec_mult /= 2;
945 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS		 946 }
947
341c526f
VS		 948 if (drain_latency > DRAIN_LATENCY_MASK)
949 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 950
341c526f
VS		 951 return drain_latency | (prec_mult == high_precision ?
952 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED		 953}
954
ae80152d
VS		 955static int vlv_compute_wm(struct intel_crtc *crtc,
956 struct intel_plane *plane,
957 int fifo_size)
b445e3b0 958{
ae80152d 959 int clock, entries, pixel_size;
b445e3b0 960
ae80152d
VS		 961 /*
962 * FIXME the plane might have an fb
963 * but be invisible (eg. due to clipping)
964 */
965 if (!crtc->active || !plane->base.state->fb)
966 return 0;
0948c265 967
ae80152d
VS		 968 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
969 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 970
ae80152d 971 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 972
ae80152d
VS		 973 /*
974 * Set up the watermark such that we don't start issuing memory
975 * requests until we are within PND's max deadline value (256us).
976 * Idea being to be idle as long as possible while still taking
977 * advatange of PND's deadline scheduling. The limit of 8
978 * cachelines (used when the FIFO will anyway drain in less time
979 * than 256us) should match what we would be done if trickle
980 * feed were enabled.
981 */
982 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
983}
984
985static bool vlv_compute_sr_wm(struct drm_device *dev,
986 struct vlv_wm_values *wm)
b445e3b0 987{
ae80152d
VS		 988 struct drm_i915_private *dev_priv = to_i915(dev);
989 struct drm_crtc *crtc;
990 enum pipe pipe = INVALID_PIPE;
991 int num_planes = 0;
992 int fifo_size = 0;
993 struct intel_plane *plane;
b445e3b0 994
ae80152d 995 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 996
ae80152d
VS		 997 crtc = single_enabled_crtc(dev);
998 /* maxfifo not supported on pipe C */
999 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1000 pipe = to_intel_crtc(crtc)->pipe;
1001 num_planes = !!wm->pipe[pipe].primary +
1002 !!wm->pipe[pipe].sprite[0] +
1003 !!wm->pipe[pipe].sprite[1];
1004 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1005 }
b445e3b0 1006
ae80152d
VS		 1007 if (fifo_size == 0 || num_planes > 1)
1008 return false;
b445e3b0 1009
ae80152d
VS		 1010 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1011 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1012
ae80152d
VS		 1013 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1014 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1015 continue;
b445e3b0 1016
ae80152d
VS		 1017 if (plane->pipe != pipe)
1018 continue;
9858425c 1019
ae80152d
VS		 1020 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1021 plane, fifo_size);
1022 if (wm->sr.plane != 0)
1023 break;
1024 }
1025
1026 return true;
b445e3b0
ED		 1027}
1028
ae80152d 1029static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS		 1030{
1031 struct drm_device *dev = crtc->dev;
3c2777fd 1032 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS		 1033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1034 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1035 bool cxsr_enabled;
ae80152d 1036 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1037
ae80152d
VS		 1038 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1039 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1040 to_intel_plane(crtc->primary),
1041 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1042
ae80152d
VS		 1043 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1044 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1045 to_intel_plane(crtc->cursor),
1046 0x3f);
3c2777fd 1047
ae80152d 1048 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1049
ae80152d
VS		 1050 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1051 return;
3c2777fd 1052
ae80152d
VS		 1053 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1054 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1055 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1056 wm.sr.plane, wm.sr.cursor);
3c2777fd 1057
fc1ac8de
VS		 1058 /*
1059 * FIXME DDR DVFS introduces massive memory latencies which
1060 * are not known to system agent so any deadline specified
1061 * by the display may not be respected. To support DDR DVFS
1062 * the watermark code needs to be rewritten to essentially
1063 * bypass deadline mechanism and rely solely on the
1064 * watermarks. For now disable DDR DVFS.
1065 */
1066 if (IS_CHERRYVIEW(dev_priv))
1067 chv_set_memory_dvfs(dev_priv, false);
1068
ae80152d
VS		 1069 if (!cxsr_enabled)
1070 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1071
ae80152d 1072 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS		 1073
1074 if (cxsr_enabled)
1075 intel_set_memory_cxsr(dev_priv, true);
1076}
1077
01e184cc
GB		 1078static void valleyview_update_sprite_wm(struct drm_plane *plane,
1079 struct drm_crtc *crtc,
1080 uint32_t sprite_width,
1081 uint32_t sprite_height,
1082 int pixel_size,
1083 bool enabled, bool scaled)
1084{
1085 struct drm_device *dev = crtc->dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS		 1087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1088 enum pipe pipe = intel_crtc->pipe;
01e184cc 1089 int sprite = to_intel_plane(plane)->plane;
ae80152d 1090 bool cxsr_enabled;
0018fda1 1091 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1092
ae80152d 1093 if (enabled) {
0018fda1 1094 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1095 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS		 1096
1097 wm.pipe[pipe].sprite[sprite] =
1098 vlv_compute_wm(intel_crtc,
1099 to_intel_plane(plane),
1100 vlv_get_fifo_size(dev, pipe, sprite+1));
1101 } else {
0018fda1 1102 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS		 1103 wm.pipe[pipe].sprite[sprite] = 0;
1104 }
1105
1106 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1107
1108 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1109 return;
1110
1111 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1112 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1113 sprite_name(pipe, sprite),
1114 wm.pipe[pipe].sprite[sprite],
1115 wm.sr.plane, wm.sr.cursor);
1116
1117 if (!cxsr_enabled)
1118 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1119
0018fda1 1120 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS		 1121
1122 if (cxsr_enabled)
1123 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB		 1124}
1125
ae80152d
VS		 1126#define single_plane_enabled(mask) is_power_of_2(mask)
1127
46ba614c 1128static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1129{
46ba614c 1130 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1131 static const int sr_latency_ns = 12000;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1134 int plane_sr, cursor_sr;
1135 unsigned int enabled = 0;
9858425c 1136 bool cxsr_enabled;
b445e3b0 1137
51cea1f4 1138 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1139 &g4x_wm_info, pessimal_latency_ns,
1140 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1141 &planea_wm, &cursora_wm))
51cea1f4 1142 enabled |= 1 << PIPE_A;
b445e3b0 1143
51cea1f4 1144 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1145 &g4x_wm_info, pessimal_latency_ns,
1146 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1147 &planeb_wm, &cursorb_wm))
51cea1f4 1148 enabled |= 1 << PIPE_B;
b445e3b0 1149
b445e3b0
ED		 1150 if (single_plane_enabled(enabled) &&
1151 g4x_compute_srwm(dev, ffs(enabled) - 1,
1152 sr_latency_ns,
1153 &g4x_wm_info,
1154 &g4x_cursor_wm_info,
52bd02d8 1155 &plane_sr, &cursor_sr)) {
9858425c 1156 cxsr_enabled = true;
52bd02d8 1157 } else {
9858425c 1158 cxsr_enabled = false;
5209b1f4 1159 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1160 plane_sr = cursor_sr = 0;
1161 }
b445e3b0 1162
a5043453
VS		 1163 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1164 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1165 planea_wm, cursora_wm,
1166 planeb_wm, cursorb_wm,
1167 plane_sr, cursor_sr);
1168
1169 I915_WRITE(DSPFW1,
f4998963
VS		 1170 FW_WM(plane_sr, SR) |
1171 FW_WM(cursorb_wm, CURSORB) |
1172 FW_WM(planeb_wm, PLANEB) |
1173 FW_WM(planea_wm, PLANEA));
b445e3b0 1174 I915_WRITE(DSPFW2,
8c919b28 1175 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1176 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1177 /* HPLL off in SR has some issues on G4x... disable it */
1178 I915_WRITE(DSPFW3,
8c919b28 1179 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1180 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1181
1182 if (cxsr_enabled)
1183 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1184}
1185
46ba614c 1186static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1187{
46ba614c 1188 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 struct drm_crtc *crtc;
1191 int srwm = 1;
1192 int cursor_sr = 16;
9858425c 1193 bool cxsr_enabled;
b445e3b0
ED		 1194
1195 /* Calc sr entries for one plane configs */
1196 crtc = single_enabled_crtc(dev);
1197 if (crtc) {
1198 /* self-refresh has much higher latency */
1199 static const int sr_latency_ns = 12000;
4fe8590a 1200 const struct drm_display_mode *adjusted_mode =
6e3c9717 1201 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1202 int clock = adjusted_mode->crtc_clock;
fec8cba3 1203 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1204 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1205 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1206 unsigned long line_time_us;
1207 int entries;
1208
922044c9 1209 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1210
1211 /* Use ns/us then divide to preserve precision */
1212 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1213 pixel_size * hdisplay;
1214 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1215 srwm = I965_FIFO_SIZE - entries;
1216 if (srwm < 0)
1217 srwm = 1;
1218 srwm &= 0x1ff;
1219 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1220 entries, srwm);
1221
1222 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1223 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1224 entries = DIV_ROUND_UP(entries,
1225 i965_cursor_wm_info.cacheline_size);
1226 cursor_sr = i965_cursor_wm_info.fifo_size -
1227 (entries + i965_cursor_wm_info.guard_size);
1228
1229 if (cursor_sr > i965_cursor_wm_info.max_wm)
1230 cursor_sr = i965_cursor_wm_info.max_wm;
1231
1232 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1233 "cursor %d\n", srwm, cursor_sr);
1234
9858425c 1235 cxsr_enabled = true;
b445e3b0 1236 } else {
9858425c 1237 cxsr_enabled = false;
b445e3b0 1238 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1239 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1240 }
1241
1242 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1243 srwm);
1244
1245 /* 965 has limitations... */
f4998963
VS		 1246 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1247 FW_WM(8, CURSORB) |
1248 FW_WM(8, PLANEB) |
1249 FW_WM(8, PLANEA));
1250 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1251 FW_WM(8, PLANEC_OLD));
b445e3b0 1252 /* update cursor SR watermark */
f4998963 1253 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1254
1255 if (cxsr_enabled)
1256 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1257}
1258
f4998963
VS		 1259#undef FW_WM
1260
46ba614c 1261static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1262{
46ba614c 1263 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1264 struct drm_i915_private *dev_priv = dev->dev_private;
1265 const struct intel_watermark_params *wm_info;
1266 uint32_t fwater_lo;
1267 uint32_t fwater_hi;
1268 int cwm, srwm = 1;
1269 int fifo_size;
1270 int planea_wm, planeb_wm;
1271 struct drm_crtc *crtc, *enabled = NULL;
1272
1273 if (IS_I945GM(dev))
1274 wm_info = &i945_wm_info;
1275 else if (!IS_GEN2(dev))
1276 wm_info = &i915_wm_info;
1277 else
9d539105 1278 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1279
1280 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1281 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1282 if (intel_crtc_active(crtc)) {
241bfc38 1283 const struct drm_display_mode *adjusted_mode;
59bea882 1284 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1285 if (IS_GEN2(dev))
1286 cpp = 4;
1287
6e3c9717 1288 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1289 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1290 wm_info, fifo_size, cpp,
5aef6003 1291 pessimal_latency_ns);
b445e3b0 1292 enabled = crtc;
9d539105 1293 } else {
b445e3b0 1294 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1295 if (planea_wm > (long)wm_info->max_wm)
1296 planea_wm = wm_info->max_wm;
1297 }
1298
1299 if (IS_GEN2(dev))
1300 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1301
1302 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1303 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1304 if (intel_crtc_active(crtc)) {
241bfc38 1305 const struct drm_display_mode *adjusted_mode;
59bea882 1306 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1307 if (IS_GEN2(dev))
1308 cpp = 4;
1309
6e3c9717 1310 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1311 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1312 wm_info, fifo_size, cpp,
5aef6003 1313 pessimal_latency_ns);
b445e3b0
ED		 1314 if (enabled == NULL)
1315 enabled = crtc;
1316 else
1317 enabled = NULL;
9d539105 1318 } else {
b445e3b0 1319 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1320 if (planeb_wm > (long)wm_info->max_wm)
1321 planeb_wm = wm_info->max_wm;
1322 }
b445e3b0
ED		 1323
1324 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1325
2ab1bc9d 1326 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1327 struct drm_i915_gem_object *obj;
2ab1bc9d 1328
59bea882 1329 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1330
1331 /* self-refresh seems busted with untiled */
2ff8fde1 1332 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1333 enabled = NULL;
1334 }
1335
b445e3b0
ED		 1336 /*
1337 * Overlay gets an aggressive default since video jitter is bad.
1338 */
1339 cwm = 2;
1340
1341 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1342 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1343
1344 /* Calc sr entries for one plane configs */
1345 if (HAS_FW_BLC(dev) && enabled) {
1346 /* self-refresh has much higher latency */
1347 static const int sr_latency_ns = 6000;
4fe8590a 1348 const struct drm_display_mode *adjusted_mode =
6e3c9717 1349 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1350 int clock = adjusted_mode->crtc_clock;
fec8cba3 1351 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1352 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1353 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1354 unsigned long line_time_us;
1355 int entries;
1356
922044c9 1357 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1358
1359 /* Use ns/us then divide to preserve precision */
1360 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1361 pixel_size * hdisplay;
1362 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1363 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1364 srwm = wm_info->fifo_size - entries;
1365 if (srwm < 0)
1366 srwm = 1;
1367
1368 if (IS_I945G(dev) || IS_I945GM(dev))
1369 I915_WRITE(FW_BLC_SELF,
1370 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1371 else if (IS_I915GM(dev))
1372 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1373 }
1374
1375 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1376 planea_wm, planeb_wm, cwm, srwm);
1377
1378 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1379 fwater_hi = (cwm & 0x1f);
1380
1381 /* Set request length to 8 cachelines per fetch */
1382 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1383 fwater_hi = fwater_hi | (1 << 8);
1384
1385 I915_WRITE(FW_BLC, fwater_lo);
1386 I915_WRITE(FW_BLC2, fwater_hi);
1387
5209b1f4
ID		 1388 if (enabled)
1389 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1390}
1391
feb56b93 1392static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1393{
46ba614c 1394 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_crtc *crtc;
241bfc38 1397 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1398 uint32_t fwater_lo;
1399 int planea_wm;
1400
1401 crtc = single_enabled_crtc(dev);
1402 if (crtc == NULL)
1403 return;
1404
6e3c9717 1405 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1406 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1407 &i845_wm_info,
b445e3b0 1408 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1409 4, pessimal_latency_ns);
b445e3b0
ED		 1410 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1411 fwater_lo |= (3<<8) | planea_wm;
1412
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1414
1415 I915_WRITE(FW_BLC, fwater_lo);
1416}
1417
3658729a
VS		 1418static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1419 struct drm_crtc *crtc)
801bcfff
PZ		 1420{
1421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1422 uint32_t pixel_rate;
801bcfff 1423
6e3c9717 1424 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1425
1426 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1427 * adjust the pixel_rate here. */
1428
6e3c9717 1429 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1430 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1431 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1432
6e3c9717
ACO		 1433 pipe_w = intel_crtc->config->pipe_src_w;
1434 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1435 pfit_w = (pfit_size >> 16) & 0xFFFF;
1436 pfit_h = pfit_size & 0xFFFF;
1437 if (pipe_w < pfit_w)
1438 pipe_w = pfit_w;
1439 if (pipe_h < pfit_h)
1440 pipe_h = pfit_h;
1441
1442 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1443 pfit_w * pfit_h);
1444 }
1445
1446 return pixel_rate;
1447}
1448
37126462 1449/* latency must be in 0.1us units. */
23297044 1450static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1451 uint32_t latency)
1452{
1453 uint64_t ret;
1454
3312ba65
VS		 1455 if (WARN(latency == 0, "Latency value missing\n"))
1456 return UINT_MAX;
1457
801bcfff
PZ		 1458 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1459 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1460
1461 return ret;
1462}
1463
37126462 1464/* latency must be in 0.1us units. */
23297044 1465static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1466 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1467 uint32_t latency)
1468{
1469 uint32_t ret;
1470
3312ba65
VS		 1471 if (WARN(latency == 0, "Latency value missing\n"))
1472 return UINT_MAX;
1473
801bcfff
PZ		 1474 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1475 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1476 ret = DIV_ROUND_UP(ret, 64) + 2;
1477 return ret;
1478}
1479
23297044 1480static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1481 uint8_t bytes_per_pixel)
1482{
1483 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1484}
1485
2ac96d2a
PB		 1486struct skl_pipe_wm_parameters {
1487 bool active;
1488 uint32_t pipe_htotal;
1489 uint32_t pixel_rate; /* in KHz */
1490 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1491 struct intel_plane_wm_parameters cursor;
1492};
1493
820c1980 1494struct ilk_pipe_wm_parameters {
801bcfff 1495 bool active;
801bcfff
PZ		 1496 uint32_t pipe_htotal;
1497 uint32_t pixel_rate;
c35426d2
VS		 1498 struct intel_plane_wm_parameters pri;
1499 struct intel_plane_wm_parameters spr;
1500 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1501};
1502
820c1980 1503struct ilk_wm_maximums {
cca32e9a
PZ		 1504 uint16_t pri;
1505 uint16_t spr;
1506 uint16_t cur;
1507 uint16_t fbc;
1508};
1509
240264f4
VS		 1510/* used in computing the new watermarks state */
1511struct intel_wm_config {
1512 unsigned int num_pipes_active;
1513 bool sprites_enabled;
1514 bool sprites_scaled;
240264f4
VS		 1515};
1516
37126462
VS		 1517/*
1518 * For both WM_PIPE and WM_LP.
1519 * mem_value must be in 0.1us units.
1520 */
820c1980 1521static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1522 uint32_t mem_value,
1523 bool is_lp)
801bcfff 1524{
cca32e9a
PZ		 1525 uint32_t method1, method2;
1526
c35426d2 1527 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1528 return 0;
1529
23297044 1530 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1531 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1532 mem_value);
1533
1534 if (!is_lp)
1535 return method1;
1536
23297044 1537 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1538 params->pipe_htotal,
c35426d2
VS		 1539 params->pri.horiz_pixels,
1540 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1541 mem_value);
1542
1543 return min(method1, method2);
801bcfff
PZ		 1544}
1545
37126462
VS		 1546/*
1547 * For both WM_PIPE and WM_LP.
1548 * mem_value must be in 0.1us units.
1549 */
820c1980 1550static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1551 uint32_t mem_value)
1552{
1553 uint32_t method1, method2;
1554
c35426d2 1555 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1556 return 0;
1557
23297044 1558 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1559 params->spr.bytes_per_pixel,
801bcfff 1560 mem_value);
23297044 1561 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1562 params->pipe_htotal,
c35426d2
VS		 1563 params->spr.horiz_pixels,
1564 params->spr.bytes_per_pixel,
801bcfff
PZ		 1565 mem_value);
1566 return min(method1, method2);
1567}
1568
37126462
VS		 1569/*
1570 * For both WM_PIPE and WM_LP.
1571 * mem_value must be in 0.1us units.
1572 */
820c1980 1573static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1574 uint32_t mem_value)
1575{
c35426d2 1576 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1577 return 0;
1578
23297044 1579 return ilk_wm_method2(params->pixel_rate,
801bcfff 1580 params->pipe_htotal,
c35426d2
VS		 1581 params->cur.horiz_pixels,
1582 params->cur.bytes_per_pixel,
801bcfff
PZ		 1583 mem_value);
1584}
1585
cca32e9a 1586/* Only for WM_LP. */
820c1980 1587static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1588 uint32_t pri_val)
cca32e9a 1589{
c35426d2 1590 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1591 return 0;
1592
23297044 1593 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1594 params->pri.horiz_pixels,
1595 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1596}
1597
158ae64f
VS		 1598static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1599{
416f4727
VS		 1600 if (INTEL_INFO(dev)->gen >= 8)
1601 return 3072;
1602 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1603 return 768;
1604 else
1605 return 512;
1606}
1607
4e975081
VS		 1608static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1609 int level, bool is_sprite)
1610{
1611 if (INTEL_INFO(dev)->gen >= 8)
1612 /* BDW primary/sprite plane watermarks */
1613 return level == 0 ? 255 : 2047;
1614 else if (INTEL_INFO(dev)->gen >= 7)
1615 /* IVB/HSW primary/sprite plane watermarks */
1616 return level == 0 ? 127 : 1023;
1617 else if (!is_sprite)
1618 /* ILK/SNB primary plane watermarks */
1619 return level == 0 ? 127 : 511;
1620 else
1621 /* ILK/SNB sprite plane watermarks */
1622 return level == 0 ? 63 : 255;
1623}
1624
1625static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1626 int level)
1627{
1628 if (INTEL_INFO(dev)->gen >= 7)
1629 return level == 0 ? 63 : 255;
1630 else
1631 return level == 0 ? 31 : 63;
1632}
1633
1634static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1635{
1636 if (INTEL_INFO(dev)->gen >= 8)
1637 return 31;
1638 else
1639 return 15;
1640}
1641
158ae64f
VS		 1642/* Calculate the maximum primary/sprite plane watermark */
1643static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1644 int level,
240264f4 1645 const struct intel_wm_config *config,
158ae64f
VS		 1646 enum intel_ddb_partitioning ddb_partitioning,
1647 bool is_sprite)
1648{
1649 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1650
1651 /* if sprites aren't enabled, sprites get nothing */
240264f4 1652 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1653 return 0;
1654
1655 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1656 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1657 fifo_size /= INTEL_INFO(dev)->num_pipes;
1658
1659 /*
1660 * For some reason the non self refresh
1661 * FIFO size is only half of the self
1662 * refresh FIFO size on ILK/SNB.
1663 */
1664 if (INTEL_INFO(dev)->gen <= 6)
1665 fifo_size /= 2;
1666 }
1667
240264f4 1668 if (config->sprites_enabled) {
158ae64f
VS		 1669 /* level 0 is always calculated with 1:1 split */
1670 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1671 if (is_sprite)
1672 fifo_size *= 5;
1673 fifo_size /= 6;
1674 } else {
1675 fifo_size /= 2;
1676 }
1677 }
1678
1679 /* clamp to max that the registers can hold */
4e975081 1680 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1681}
1682
1683/* Calculate the maximum cursor plane watermark */
1684static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1685 int level,
1686 const struct intel_wm_config *config)
158ae64f
VS		 1687{
1688 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1689 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1690 return 64;
1691
1692 /* otherwise just report max that registers can hold */
4e975081 1693 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1694}
1695
d34ff9c6 1696static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1697 int level,
1698 const struct intel_wm_config *config,
1699 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1700 struct ilk_wm_maximums *max)
158ae64f 1701{
240264f4
VS		 1702 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1703 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1704 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1705 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1706}
1707
a3cb4048
VS		 1708static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1709 int level,
1710 struct ilk_wm_maximums *max)
1711{
1712 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1713 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1714 max->cur = ilk_cursor_wm_reg_max(dev, level);
1715 max->fbc = ilk_fbc_wm_reg_max(dev);
1716}
1717
d9395655 1718static bool ilk_validate_wm_level(int level,
820c1980 1719 const struct ilk_wm_maximums *max,
d9395655 1720 struct intel_wm_level *result)
a9786a11
VS		 1721{
1722 bool ret;
1723
1724 /* already determined to be invalid? */
1725 if (!result->enable)
1726 return false;
1727
1728 result->enable = result->pri_val <= max->pri &&
1729 result->spr_val <= max->spr &&
1730 result->cur_val <= max->cur;
1731
1732 ret = result->enable;
1733
1734 /*
1735 * HACK until we can pre-compute everything,
1736 * and thus fail gracefully if LP0 watermarks
1737 * are exceeded...
1738 */
1739 if (level == 0 && !result->enable) {
1740 if (result->pri_val > max->pri)
1741 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1742 level, result->pri_val, max->pri);
1743 if (result->spr_val > max->spr)
1744 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1745 level, result->spr_val, max->spr);
1746 if (result->cur_val > max->cur)
1747 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1748 level, result->cur_val, max->cur);
1749
1750 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1751 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1752 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1753 result->enable = true;
1754 }
1755
a9786a11
VS		 1756 return ret;
1757}
1758
d34ff9c6 1759static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1760 int level,
820c1980 1761 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1762 struct intel_wm_level *result)
6f5ddd17
VS		 1763{
1764 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1765 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1766 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1767
1768 /* WM1+ latency values stored in 0.5us units */
1769 if (level > 0) {
1770 pri_latency *= 5;
1771 spr_latency *= 5;
1772 cur_latency *= 5;
1773 }
1774
1775 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1776 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1777 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1778 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1779 result->enable = true;
1780}
1781
801bcfff
PZ		 1782static uint32_t
1783hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1784{
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1787 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1788 u32 linetime, ips_linetime;
1f8eeabf 1789
3ef00284 1790 if (!intel_crtc->active)
801bcfff 1791 return 0;
1011d8c4 1792
1f8eeabf
ED		 1793 /* The WM are computed with base on how long it takes to fill a single
1794 * row at the given clock rate, multiplied by 8.
1795 * */
fec8cba3
JB		 1796 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1797 mode->crtc_clock);
1798 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1652d19e 1799 dev_priv->display.get_display_clock_speed(dev_priv->dev));
1f8eeabf 1800
801bcfff
PZ		 1801 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1802 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1803}
1804
2af30a5c 1805static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1806{
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1808
2af30a5c
PB		 1809 if (IS_GEN9(dev)) {
1810 uint32_t val;
4f947386 1811 int ret, i;
367294be 1812 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1813
1814 /* read the first set of memory latencies[0:3] */
1815 val = 0; /* data0 to be programmed to 0 for first set */
1816 mutex_lock(&dev_priv->rps.hw_lock);
1817 ret = sandybridge_pcode_read(dev_priv,
1818 GEN9_PCODE_READ_MEM_LATENCY,
1819 &val);
1820 mutex_unlock(&dev_priv->rps.hw_lock);
1821
1822 if (ret) {
1823 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1824 return;
1825 }
1826
1827 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1828 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1829 GEN9_MEM_LATENCY_LEVEL_MASK;
1830 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1831 GEN9_MEM_LATENCY_LEVEL_MASK;
1832 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1833 GEN9_MEM_LATENCY_LEVEL_MASK;
1834
1835 /* read the second set of memory latencies[4:7] */
1836 val = 1; /* data0 to be programmed to 1 for second set */
1837 mutex_lock(&dev_priv->rps.hw_lock);
1838 ret = sandybridge_pcode_read(dev_priv,
1839 GEN9_PCODE_READ_MEM_LATENCY,
1840 &val);
1841 mutex_unlock(&dev_priv->rps.hw_lock);
1842 if (ret) {
1843 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1844 return;
1845 }
1846
1847 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1851 GEN9_MEM_LATENCY_LEVEL_MASK;
1852 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1853 GEN9_MEM_LATENCY_LEVEL_MASK;
1854
367294be 1855 /*
6f97235b
DL		 1856 * WaWmMemoryReadLatency:skl
1857 *
367294be
VK		 1858 * punit doesn't take into account the read latency so we need
1859 * to add 2us to the various latency levels we retrieve from
1860 * the punit.
1861 * - W0 is a bit special in that it's the only level that
1862 * can't be disabled if we want to have display working, so
1863 * we always add 2us there.
1864 * - For levels >=1, punit returns 0us latency when they are
1865 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1866 *
1867 * Additionally, if a level n (n > 1) has a 0us latency, all
1868 * levels m (m >= n) need to be disabled. We make sure to
1869 * sanitize the values out of the punit to satisfy this
1870 * requirement.
367294be
VK		 1871 */
1872 wm[0] += 2;
1873 for (level = 1; level <= max_level; level++)
1874 if (wm[level] != 0)
1875 wm[level] += 2;
4f947386
VK		 1876 else {
1877 for (i = level + 1; i <= max_level; i++)
1878 wm[i] = 0;
367294be 1879
4f947386
VK		 1880 break;
1881 }
2af30a5c 1882 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1883 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1884
1885 wm[0] = (sskpd >> 56) & 0xFF;
1886 if (wm[0] == 0)
1887 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1888 wm[1] = (sskpd >> 4) & 0xFF;
1889 wm[2] = (sskpd >> 12) & 0xFF;
1890 wm[3] = (sskpd >> 20) & 0x1FF;
1891 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1892 } else if (INTEL_INFO(dev)->gen >= 6) {
1893 uint32_t sskpd = I915_READ(MCH_SSKPD);
1894
1895 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1896 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1897 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1898 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1899 } else if (INTEL_INFO(dev)->gen >= 5) {
1900 uint32_t mltr = I915_READ(MLTR_ILK);
1901
1902 /* ILK primary LP0 latency is 700 ns */
1903 wm[0] = 7;
1904 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1905 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1906 }
1907}
1908
53615a5e
VS		 1909static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1910{
1911 /* ILK sprite LP0 latency is 1300 ns */
1912 if (INTEL_INFO(dev)->gen == 5)
1913 wm[0] = 13;
1914}
1915
1916static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1917{
1918 /* ILK cursor LP0 latency is 1300 ns */
1919 if (INTEL_INFO(dev)->gen == 5)
1920 wm[0] = 13;
1921
1922 /* WaDoubleCursorLP3Latency:ivb */
1923 if (IS_IVYBRIDGE(dev))
1924 wm[3] *= 2;
1925}
1926
546c81fd 1927int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1928{
26ec971e 1929 /* how many WM levels are we expecting */
2af30a5c
PB		 1930 if (IS_GEN9(dev))
1931 return 7;
1932 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1933 return 4;
26ec971e 1934 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1935 return 3;
26ec971e 1936 else
ad0d6dc4
VS		 1937 return 2;
1938}
7526ed79 1939
ad0d6dc4
VS		 1940static void intel_print_wm_latency(struct drm_device *dev,
1941 const char *name,
2af30a5c 1942 const uint16_t wm[8])
ad0d6dc4
VS		 1943{
1944 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1945
1946 for (level = 0; level <= max_level; level++) {
1947 unsigned int latency = wm[level];
1948
1949 if (latency == 0) {
1950 DRM_ERROR("%s WM%d latency not provided\n",
1951 name, level);
1952 continue;
1953 }
1954
2af30a5c
PB		 1955 /*
1956 * - latencies are in us on gen9.
1957 * - before then, WM1+ latency values are in 0.5us units
1958 */
1959 if (IS_GEN9(dev))
1960 latency *= 10;
1961 else if (level > 0)
26ec971e
VS		 1962 latency *= 5;
1963
1964 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1965 name, level, wm[level],
1966 latency / 10, latency % 10);
1967 }
1968}
1969
e95a2f75
VS		 1970static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1971 uint16_t wm[5], uint16_t min)
1972{
1973 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1974
1975 if (wm[0] >= min)
1976 return false;
1977
1978 wm[0] = max(wm[0], min);
1979 for (level = 1; level <= max_level; level++)
1980 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1981
1982 return true;
1983}
1984
1985static void snb_wm_latency_quirk(struct drm_device *dev)
1986{
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 bool changed;
1989
1990 /*
1991 * The BIOS provided WM memory latency values are often
1992 * inadequate for high resolution displays. Adjust them.
1993 */
1994 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1995 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1996 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1997
1998 if (!changed)
1999 return;
2000
2001 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2002 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2003 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2004 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2005}
2006
fa50ad61 2007static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2008{
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010
2011 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2012
2013 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2014 sizeof(dev_priv->wm.pri_latency));
2015 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2016 sizeof(dev_priv->wm.pri_latency));
2017
2018 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2019 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2020
2021 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2022 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2023 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2024
2025 if (IS_GEN6(dev))
2026 snb_wm_latency_quirk(dev);
53615a5e
VS		 2027}
2028
2af30a5c
PB		 2029static void skl_setup_wm_latency(struct drm_device *dev)
2030{
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032
2033 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2034 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2035}
2036
820c1980 2037static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2038 struct ilk_pipe_wm_parameters *p)
1011d8c4 2039{
7c4a395f
VS		 2040 struct drm_device *dev = crtc->dev;
2041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2043 struct drm_plane *plane;
1011d8c4 2044
3ef00284 2045 if (!intel_crtc->active)
2a44b76b 2046 return;
801bcfff 2047
2a44b76b 2048 p->active = true;
6e3c9717 2049 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b 2050 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c9f038a1
MR		 2051
2052 if (crtc->primary->state->fb) {
2053 p->pri.enabled = true;
2054 p->pri.bytes_per_pixel =
2055 crtc->primary->state->fb->bits_per_pixel / 8;
2056 } else {
2057 p->pri.enabled = false;
2058 p->pri.bytes_per_pixel = 0;
2059 }
2060
2061 if (crtc->cursor->state->fb) {
2062 p->cur.enabled = true;
2063 p->cur.bytes_per_pixel = 4;
2064 } else {
2065 p->cur.enabled = false;
2066 p->cur.bytes_per_pixel = 0;
2067 }
6e3c9717 2068 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2069 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2070
af2b653b 2071 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2072 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2073
2a44b76b 2074 if (intel_plane->pipe == pipe) {
7c4a395f 2075 p->spr = intel_plane->wm;
2a44b76b
VS		 2076 break;
2077 }
2078 }
2079}
2080
2081static void ilk_compute_wm_config(struct drm_device *dev,
2082 struct intel_wm_config *config)
2083{
2084 struct intel_crtc *intel_crtc;
2085
2086 /* Compute the currently _active_ config */
d3fcc808 2087 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2088 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2089
2a44b76b
VS		 2090 if (!wm->pipe_enabled)
2091 continue;
cca32e9a 2092
2a44b76b
VS		 2093 config->sprites_enabled |= wm->sprites_enabled;
2094 config->sprites_scaled |= wm->sprites_scaled;
2095 config->num_pipes_active++;
cca32e9a 2096 }
801bcfff
PZ		 2097}
2098
0b2ae6d7
VS		 2099/* Compute new watermarks for the pipe */
2100static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2101 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2102 struct intel_pipe_wm *pipe_wm)
2103{
2104 struct drm_device *dev = crtc->dev;
d34ff9c6 2105 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2106 int level, max_level = ilk_wm_max_level(dev);
2107 /* LP0 watermark maximums depend on this pipe alone */
2108 struct intel_wm_config config = {
2109 .num_pipes_active = 1,
2110 .sprites_enabled = params->spr.enabled,
2111 .sprites_scaled = params->spr.scaled,
2112 };
820c1980 2113 struct ilk_wm_maximums max;
0b2ae6d7 2114
2a44b76b
VS		 2115 pipe_wm->pipe_enabled = params->active;
2116 pipe_wm->sprites_enabled = params->spr.enabled;
2117 pipe_wm->sprites_scaled = params->spr.scaled;
2118
7b39a0b7
VS		 2119 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2120 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2121 max_level = 1;
2122
2123 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2124 if (params->spr.scaled)
2125 max_level = 0;
2126
a3cb4048 2127 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2128
a42a5719 2129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2130 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2131
a3cb4048
VS		 2132 /* LP0 watermarks always use 1/2 DDB partitioning */
2133 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2134
0b2ae6d7 2135 /* At least LP0 must be valid */
a3cb4048
VS		 2136 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2137 return false;
2138
2139 ilk_compute_wm_reg_maximums(dev, 1, &max);
2140
2141 for (level = 1; level <= max_level; level++) {
2142 struct intel_wm_level wm = {};
2143
2144 ilk_compute_wm_level(dev_priv, level, params, &wm);
2145
2146 /*
2147 * Disable any watermark level that exceeds the
2148 * register maximums since such watermarks are
2149 * always invalid.
2150 */
2151 if (!ilk_validate_wm_level(level, &max, &wm))
2152 break;
2153
2154 pipe_wm->wm[level] = wm;
2155 }
2156
2157 return true;
0b2ae6d7
VS		 2158}
2159
2160/*
2161 * Merge the watermarks from all active pipes for a specific level.
2162 */
2163static void ilk_merge_wm_level(struct drm_device *dev,
2164 int level,
2165 struct intel_wm_level *ret_wm)
2166{
2167 const struct intel_crtc *intel_crtc;
2168
d52fea5b
VS		 2169 ret_wm->enable = true;
2170
d3fcc808 2171 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2172 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2173 const struct intel_wm_level *wm = &active->wm[level];
2174
2175 if (!active->pipe_enabled)
2176 continue;
0b2ae6d7 2177
d52fea5b
VS		 2178 /*
2179 * The watermark values may have been used in the past,
2180 * so we must maintain them in the registers for some
2181 * time even if the level is now disabled.
2182 */
0b2ae6d7 2183 if (!wm->enable)
d52fea5b 2184 ret_wm->enable = false;
0b2ae6d7
VS		 2185
2186 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2187 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2188 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2189 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2190 }
0b2ae6d7
VS		 2191}
2192
2193/*
2194 * Merge all low power watermarks for all active pipes.
2195 */
2196static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2197 const struct intel_wm_config *config,
820c1980 2198 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2199 struct intel_pipe_wm *merged)
2200{
2201 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2202 int last_enabled_level = max_level;
0b2ae6d7 2203
0ba22e26
VS		 2204 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2205 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2206 config->num_pipes_active > 1)
2207 return;
2208
6c8b6c28
VS		 2209 /* ILK: FBC WM must be disabled always */
2210 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2211
2212 /* merge each WM1+ level */
2213 for (level = 1; level <= max_level; level++) {
2214 struct intel_wm_level *wm = &merged->wm[level];
2215
2216 ilk_merge_wm_level(dev, level, wm);
2217
d52fea5b
VS		 2218 if (level > last_enabled_level)
2219 wm->enable = false;
2220 else if (!ilk_validate_wm_level(level, max, wm))
2221 /* make sure all following levels get disabled */
2222 last_enabled_level = level - 1;
0b2ae6d7
VS		 2223
2224 /*
2225 * The spec says it is preferred to disable
2226 * FBC WMs instead of disabling a WM level.
2227 */
2228 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2229 if (wm->enable)
2230 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2231 wm->fbc_val = 0;
2232 }
2233 }
6c8b6c28
VS		 2234
2235 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2236 /*
2237 * FIXME this is racy. FBC might get enabled later.
2238 * What we should check here is whether FBC can be
2239 * enabled sometime later.
2240 */
2241 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2242 for (level = 2; level <= max_level; level++) {
2243 struct intel_wm_level *wm = &merged->wm[level];
2244
2245 wm->enable = false;
2246 }
2247 }
0b2ae6d7
VS		 2248}
2249
b380ca3c
VS		 2250static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2251{
2252 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2253 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2254}
2255
a68d68ee
VS		 2256/* The value we need to program into the WM_LPx latency field */
2257static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2258{
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260
a42a5719 2261 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2262 return 2 * level;
2263 else
2264 return dev_priv->wm.pri_latency[level];
2265}
2266
820c1980 2267static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2268 const struct intel_pipe_wm *merged,
609cedef 2269 enum intel_ddb_partitioning partitioning,
820c1980 2270 struct ilk_wm_values *results)
801bcfff 2271{
0b2ae6d7
VS		 2272 struct intel_crtc *intel_crtc;
2273 int level, wm_lp;
cca32e9a 2274
0362c781 2275 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2276 results->partitioning = partitioning;
cca32e9a 2277
0b2ae6d7 2278 /* LP1+ register values */
cca32e9a 2279 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2280 const struct intel_wm_level *r;
801bcfff 2281
b380ca3c 2282 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2283
0362c781 2284 r = &merged->wm[level];
cca32e9a 2285
d52fea5b
VS		 2286 /*
2287 * Maintain the watermark values even if the level is
2288 * disabled. Doing otherwise could cause underruns.
2289 */
2290 results->wm_lp[wm_lp - 1] =
a68d68ee 2291 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2292 (r->pri_val << WM1_LP_SR_SHIFT) |
2293 r->cur_val;
2294
d52fea5b
VS		 2295 if (r->enable)
2296 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2297
416f4727
VS		 2298 if (INTEL_INFO(dev)->gen >= 8)
2299 results->wm_lp[wm_lp - 1] |=
2300 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2301 else
2302 results->wm_lp[wm_lp - 1] |=
2303 r->fbc_val << WM1_LP_FBC_SHIFT;
2304
d52fea5b
VS		 2305 /*
2306 * Always set WM1S_LP_EN when spr_val != 0, even if the
2307 * level is disabled. Doing otherwise could cause underruns.
2308 */
6cef2b8a
VS		 2309 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2310 WARN_ON(wm_lp != 1);
2311 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2312 } else
2313 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2314 }
801bcfff 2315
0b2ae6d7 2316 /* LP0 register values */
d3fcc808 2317 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2318 enum pipe pipe = intel_crtc->pipe;
2319 const struct intel_wm_level *r =
2320 &intel_crtc->wm.active.wm[0];
2321
2322 if (WARN_ON(!r->enable))
2323 continue;
2324
2325 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2326
0b2ae6d7
VS		 2327 results->wm_pipe[pipe] =
2328 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2329 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2330 r->cur_val;
801bcfff
PZ		 2331 }
2332}
2333
861f3389
PZ		 2334/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2335 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2336static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2337 struct intel_pipe_wm *r1,
2338 struct intel_pipe_wm *r2)
861f3389 2339{
198a1e9b
VS		 2340 int level, max_level = ilk_wm_max_level(dev);
2341 int level1 = 0, level2 = 0;
861f3389 2342
198a1e9b
VS		 2343 for (level = 1; level <= max_level; level++) {
2344 if (r1->wm[level].enable)
2345 level1 = level;
2346 if (r2->wm[level].enable)
2347 level2 = level;
861f3389
PZ		 2348 }
2349
198a1e9b
VS		 2350 if (level1 == level2) {
2351 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2352 return r2;
2353 else
2354 return r1;
198a1e9b 2355 } else if (level1 > level2) {
861f3389
PZ		 2356 return r1;
2357 } else {
2358 return r2;
2359 }
2360}
2361
49a687c4
VS		 2362/* dirty bits used to track which watermarks need changes */
2363#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2364#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2365#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2366#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2367#define WM_DIRTY_FBC (1 << 24)
2368#define WM_DIRTY_DDB (1 << 25)
2369
055e393f 2370static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2371 const struct ilk_wm_values *old,
2372 const struct ilk_wm_values *new)
49a687c4
VS		 2373{
2374 unsigned int dirty = 0;
2375 enum pipe pipe;
2376 int wm_lp;
2377
055e393f 2378 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2379 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2380 dirty |= WM_DIRTY_LINETIME(pipe);
2381 /* Must disable LP1+ watermarks too */
2382 dirty |= WM_DIRTY_LP_ALL;
2383 }
2384
2385 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2386 dirty |= WM_DIRTY_PIPE(pipe);
2387 /* Must disable LP1+ watermarks too */
2388 dirty |= WM_DIRTY_LP_ALL;
2389 }
2390 }
2391
2392 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2393 dirty |= WM_DIRTY_FBC;
2394 /* Must disable LP1+ watermarks too */
2395 dirty |= WM_DIRTY_LP_ALL;
2396 }
2397
2398 if (old->partitioning != new->partitioning) {
2399 dirty |= WM_DIRTY_DDB;
2400 /* Must disable LP1+ watermarks too */
2401 dirty |= WM_DIRTY_LP_ALL;
2402 }
2403
2404 /* LP1+ watermarks already deemed dirty, no need to continue */
2405 if (dirty & WM_DIRTY_LP_ALL)
2406 return dirty;
2407
2408 /* Find the lowest numbered LP1+ watermark in need of an update... */
2409 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2410 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2411 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2412 break;
2413 }
2414
2415 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2416 for (; wm_lp <= 3; wm_lp++)
2417 dirty |= WM_DIRTY_LP(wm_lp);
2418
2419 return dirty;
2420}
2421
8553c18e
VS		 2422static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2423 unsigned int dirty)
801bcfff 2424{
820c1980 2425 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2426 bool changed = false;
801bcfff 2427
facd619b
VS		 2428 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2429 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2430 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2431 changed = true;
facd619b
VS		 2432 }
2433 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2434 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2435 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2436 changed = true;
facd619b
VS		 2437 }
2438 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2439 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2440 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2441 changed = true;
facd619b 2442 }
801bcfff 2443
facd619b
VS		 2444 /*
2445 * Don't touch WM1S_LP_EN here.
2446 * Doing so could cause underruns.
2447 */
6cef2b8a 2448
8553c18e
VS		 2449 return changed;
2450}
2451
2452/*
2453 * The spec says we shouldn't write when we don't need, because every write
2454 * causes WMs to be re-evaluated, expending some power.
2455 */
820c1980
ID		 2456static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2457 struct ilk_wm_values *results)
8553c18e
VS		 2458{
2459 struct drm_device *dev = dev_priv->dev;
820c1980 2460 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2461 unsigned int dirty;
2462 uint32_t val;
2463
055e393f 2464 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2465 if (!dirty)
2466 return;
2467
2468 _ilk_disable_lp_wm(dev_priv, dirty);
2469
49a687c4 2470 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2471 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2472 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2473 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2474 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2475 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2476
49a687c4 2477 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2478 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2479 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2480 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2481 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2482 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2483
49a687c4 2484 if (dirty & WM_DIRTY_DDB) {
a42a5719 2485 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2486 val = I915_READ(WM_MISC);
2487 if (results->partitioning == INTEL_DDB_PART_1_2)
2488 val &= ~WM_MISC_DATA_PARTITION_5_6;
2489 else
2490 val |= WM_MISC_DATA_PARTITION_5_6;
2491 I915_WRITE(WM_MISC, val);
2492 } else {
2493 val = I915_READ(DISP_ARB_CTL2);
2494 if (results->partitioning == INTEL_DDB_PART_1_2)
2495 val &= ~DISP_DATA_PARTITION_5_6;
2496 else
2497 val |= DISP_DATA_PARTITION_5_6;
2498 I915_WRITE(DISP_ARB_CTL2, val);
2499 }
1011d8c4
PZ		 2500 }
2501
49a687c4 2502 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2503 val = I915_READ(DISP_ARB_CTL);
2504 if (results->enable_fbc_wm)
2505 val &= ~DISP_FBC_WM_DIS;
2506 else
2507 val |= DISP_FBC_WM_DIS;
2508 I915_WRITE(DISP_ARB_CTL, val);
2509 }
2510
954911eb
ID		 2511 if (dirty & WM_DIRTY_LP(1) &&
2512 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2513 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2514
2515 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2516 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2517 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2518 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2519 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2520 }
801bcfff 2521
facd619b 2522 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2523 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2524 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2525 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2526 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2527 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2528
2529 dev_priv->wm.hw = *results;
801bcfff
PZ		 2530}
2531
8553c18e
VS		 2532static bool ilk_disable_lp_wm(struct drm_device *dev)
2533{
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535
2536 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2537}
2538
b9cec075
DL		 2539/*
2540 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2541 * different active planes.
2542 */
2543
2544#define SKL_DDB_SIZE 896 /* in blocks */
2545
2546static void
2547skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2548 struct drm_crtc *for_crtc,
2549 const struct intel_wm_config *config,
2550 const struct skl_pipe_wm_parameters *params,
2551 struct skl_ddb_entry *alloc /* out */)
2552{
2553 struct drm_crtc *crtc;
2554 unsigned int pipe_size, ddb_size;
2555 int nth_active_pipe;
2556
2557 if (!params->active) {
2558 alloc->start = 0;
2559 alloc->end = 0;
2560 return;
2561 }
2562
2563 ddb_size = SKL_DDB_SIZE;
2564
2565 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2566
2567 nth_active_pipe = 0;
2568 for_each_crtc(dev, crtc) {
3ef00284 2569 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2570 continue;
2571
2572 if (crtc == for_crtc)
2573 break;
2574
2575 nth_active_pipe++;
2576 }
2577
2578 pipe_size = ddb_size / config->num_pipes_active;
2579 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2580 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2581}
2582
2583static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2584{
2585 if (config->num_pipes_active == 1)
2586 return 32;
2587
2588 return 8;
2589}
2590
a269c583
DL		 2591static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2592{
2593 entry->start = reg & 0x3ff;
2594 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2595 if (entry->end)
2596 entry->end += 1;
a269c583
DL		 2597}
2598
08db6652
DL		 2599void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2600 struct skl_ddb_allocation *ddb /* out */)
a269c583 2601{
a269c583
DL		 2602 enum pipe pipe;
2603 int plane;
2604 u32 val;
2605
2606 for_each_pipe(dev_priv, pipe) {
dd740780 2607 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2608 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2609 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2610 val);
2611 }
2612
2613 val = I915_READ(CUR_BUF_CFG(pipe));
2614 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2615 }
2616}
2617
b9cec075
DL		 2618static unsigned int
2619skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2620{
2621 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2622}
2623
2624/*
2625 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2626 * a 8192x4096@32bpp framebuffer:
2627 * 3 * 4096 * 8192 * 4 < 2^32
2628 */
2629static unsigned int
2630skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2631 const struct skl_pipe_wm_parameters *params)
2632{
2633 unsigned int total_data_rate = 0;
2634 int plane;
2635
2636 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2637 const struct intel_plane_wm_parameters *p;
2638
2639 p = &params->plane[plane];
2640 if (!p->enabled)
2641 continue;
2642
2643 total_data_rate += skl_plane_relative_data_rate(p);
2644 }
2645
2646 return total_data_rate;
2647}
2648
2649static void
2650skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2651 const struct intel_wm_config *config,
2652 const struct skl_pipe_wm_parameters *params,
2653 struct skl_ddb_allocation *ddb /* out */)
2654{
2655 struct drm_device *dev = crtc->dev;
dd740780 2656 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2658 enum pipe pipe = intel_crtc->pipe;
34bb56af 2659 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2660 uint16_t alloc_size, start, cursor_blocks;
80958155 2661 uint16_t minimum[I915_MAX_PLANES];
b9cec075
DL		 2662 unsigned int total_data_rate;
2663 int plane;
2664
34bb56af
DL		 2665 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2666 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2667 if (alloc_size == 0) {
2668 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2669 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2670 return;
2671 }
2672
2673 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2674 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2675 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2676
2677 alloc_size -= cursor_blocks;
34bb56af 2678 alloc->end -= cursor_blocks;
b9cec075 2679
80958155 2680 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2681 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2682 const struct intel_plane_wm_parameters *p;
2683
2684 p = &params->plane[plane];
2685 if (!p->enabled)
2686 continue;
2687
2688 minimum[plane] = 8;
2689 alloc_size -= minimum[plane];
2690 }
2691
b9cec075 2692 /*
80958155
DL		 2693 * 2. Distribute the remaining space in proportion to the amount of
2694 * data each plane needs to fetch from memory.
b9cec075
DL		 2695 *
2696 * FIXME: we may not allocate every single block here.
2697 */
2698 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2699
34bb56af 2700 start = alloc->start;
b9cec075
DL		 2701 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2702 const struct intel_plane_wm_parameters *p;
2703 unsigned int data_rate;
2704 uint16_t plane_blocks;
2705
2706 p = &params->plane[plane];
2707 if (!p->enabled)
2708 continue;
2709
2710 data_rate = skl_plane_relative_data_rate(p);
2711
2712 /*
2713 * promote the expression to 64 bits to avoid overflowing, the
2714 * result is < available as data_rate / total_data_rate < 1
2715 */
80958155
DL		 2716 plane_blocks = minimum[plane];
2717 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2718 total_data_rate);
b9cec075
DL		 2719
2720 ddb->plane[pipe][plane].start = start;
16160e3d 2721 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2722
2723 start += plane_blocks;
2724 }
2725
2726}
2727
5cec258b 2728static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2729{
2730 /* TODO: Take into account the scalers once we support them */
2d112de7 2731 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2732}
2733
2734/*
2735 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2736 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2737 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2738 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2739*/
2740static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2741 uint32_t latency)
2742{
2743 uint32_t wm_intermediate_val, ret;
2744
2745 if (latency == 0)
2746 return UINT_MAX;
2747
d4c2aa60 2748 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 2749 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2750
2751 return ret;
2752}
2753
2754static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2755 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2756 uint64_t tiling, uint32_t latency)
2d41c0b5 2757{
d4c2aa60
TU		 2758 uint32_t ret;
2759 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2760 uint32_t wm_intermediate_val;
2d41c0b5
PB		 2761
2762 if (latency == 0)
2763 return UINT_MAX;
2764
2765 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 2766
2767 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2768 tiling == I915_FORMAT_MOD_Yf_TILED) {
2769 plane_bytes_per_line *= 4;
2770 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2771 plane_blocks_per_line /= 4;
2772 } else {
2773 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2774 }
2775
2d41c0b5
PB		 2776 wm_intermediate_val = latency * pixel_rate;
2777 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2778 plane_blocks_per_line;
2d41c0b5
PB		 2779
2780 return ret;
2781}
2782
2d41c0b5
PB		 2783static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2784 const struct intel_crtc *intel_crtc)
2785{
2786 struct drm_device *dev = intel_crtc->base.dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2789 enum pipe pipe = intel_crtc->pipe;
2790
2791 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2792 sizeof(new_ddb->plane[pipe])))
2793 return true;
2794
2795 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2796 sizeof(new_ddb->cursor[pipe])))
2797 return true;
2798
2799 return false;
2800}
2801
2802static void skl_compute_wm_global_parameters(struct drm_device *dev,
2803 struct intel_wm_config *config)
2804{
2805 struct drm_crtc *crtc;
2806 struct drm_plane *plane;
2807
2808 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2809 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 2810
2811 /* FIXME: I don't think we need those two global parameters on SKL */
2812 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2813 struct intel_plane *intel_plane = to_intel_plane(plane);
2814
2815 config->sprites_enabled |= intel_plane->wm.enabled;
2816 config->sprites_scaled |= intel_plane->wm.scaled;
2817 }
2818}
2819
2820static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2821 struct skl_pipe_wm_parameters *p)
2822{
2823 struct drm_device *dev = crtc->dev;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 enum pipe pipe = intel_crtc->pipe;
2826 struct drm_plane *plane;
0fda6568 2827 struct drm_framebuffer *fb;
2d41c0b5
PB		 2828 int i = 1; /* Index for sprite planes start */
2829
3ef00284 2830 p->active = intel_crtc->active;
2d41c0b5 2831 if (p->active) {
6e3c9717
ACO		 2832 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2833 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 2834
0fda6568 2835 fb = crtc->primary->state->fb;
c9f038a1
MR		 2836 if (fb) {
2837 p->plane[0].enabled = true;
2838 p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;
0fda6568 2839 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 2840 } else {
2841 p->plane[0].enabled = false;
2842 p->plane[0].bytes_per_pixel = 0;
2843 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2844 }
2845 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2846 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 2847 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 2848
c9f038a1
MR		 2849 fb = crtc->cursor->state->fb;
2850 if (fb) {
2851 p->cursor.enabled = true;
2852 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2853 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2854 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2855 } else {
2856 p->cursor.enabled = false;
2857 p->cursor.bytes_per_pixel = 0;
2858 p->cursor.horiz_pixels = 64;
2859 p->cursor.vert_pixels = 64;
2860 }
2d41c0b5
PB		 2861 }
2862
2863 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2864 struct intel_plane *intel_plane = to_intel_plane(plane);
2865
a712f8eb
SJ		 2866 if (intel_plane->pipe == pipe &&
2867 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2868 p->plane[i++] = intel_plane->wm;
2869 }
2870}
2871
d4c2aa60
TU		 2872static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2873 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2874 struct intel_plane_wm_parameters *p_params,
2875 uint16_t ddb_allocation,
d4c2aa60 2876 int level,
afb024aa
DL		 2877 uint16_t *out_blocks, /* out */
2878 uint8_t *out_lines /* out */)
2d41c0b5 2879{
d4c2aa60
TU		 2880 uint32_t latency = dev_priv->wm.skl_latency[level];
2881 uint32_t method1, method2;
2882 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2883 uint32_t res_blocks, res_lines;
2884 uint32_t selected_result;
2d41c0b5 2885
d4c2aa60 2886 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2887 return false;
2888
2889 method1 = skl_wm_method1(p->pixel_rate,
2890 p_params->bytes_per_pixel,
d4c2aa60 2891 latency);
2d41c0b5
PB		 2892 method2 = skl_wm_method2(p->pixel_rate,
2893 p->pipe_htotal,
2894 p_params->horiz_pixels,
2895 p_params->bytes_per_pixel,
0fda6568 2896 p_params->tiling,
d4c2aa60 2897 latency);
2d41c0b5
PB		 2898
2899 plane_bytes_per_line = p_params->horiz_pixels *
2900 p_params->bytes_per_pixel;
d4c2aa60 2901 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2902
0fda6568
TU		 2903 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2904 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 2905 uint32_t min_scanlines = 4;
2906 uint32_t y_tile_minimum;
2907 if (intel_rotation_90_or_270(p_params->rotation)) {
2908 switch (p_params->bytes_per_pixel) {
2909 case 1:
2910 min_scanlines = 16;
2911 break;
2912 case 2:
2913 min_scanlines = 8;
2914 break;
2915 case 8:
2916 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 2917 }
1fc0a8f7
TU		 2918 }
2919 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 2920 selected_result = max(method2, y_tile_minimum);
2921 } else {
2922 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2923 selected_result = min(method1, method2);
2924 else
2925 selected_result = method1;
2926 }
2d41c0b5 2927
d4c2aa60
TU		 2928 res_blocks = selected_result + 1;
2929 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2930
0fda6568
TU		 2931 if (level >= 1 && level <= 7) {
2932 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2933 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2934 res_lines += 4;
2935 else
2936 res_blocks++;
2937 }
e6d66171 2938
d4c2aa60 2939 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 2940 return false;
2941
2942 *out_blocks = res_blocks;
2943 *out_lines = res_lines;
2d41c0b5
PB		 2944
2945 return true;
2946}
2947
2948static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2949 struct skl_ddb_allocation *ddb,
2950 struct skl_pipe_wm_parameters *p,
2951 enum pipe pipe,
2952 int level,
2953 int num_planes,
2954 struct skl_wm_level *result)
2955{
2d41c0b5
PB		 2956 uint16_t ddb_blocks;
2957 int i;
2958
2959 for (i = 0; i < num_planes; i++) {
2960 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2961
d4c2aa60
TU		 2962 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2963 p, &p->plane[i],
2d41c0b5 2964 ddb_blocks,
d4c2aa60 2965 level,
2d41c0b5
PB		 2966 &result->plane_res_b[i],
2967 &result->plane_res_l[i]);
2968 }
2969
2970 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 2971 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2972 ddb_blocks, level,
2973 &result->cursor_res_b,
2d41c0b5
PB		 2974 &result->cursor_res_l);
2975}
2976
407b50f3
DL		 2977static uint32_t
2978skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2979{
3ef00284 2980 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 2981 return 0;
2982
2983 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2984
2985}
2986
2987static void skl_compute_transition_wm(struct drm_crtc *crtc,
2988 struct skl_pipe_wm_parameters *params,
9414f563 2989 struct skl_wm_level *trans_wm /* out */)
407b50f3 2990{
9414f563
DL		 2991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2992 int i;
2993
407b50f3
DL		 2994 if (!params->active)
2995 return;
9414f563
DL		 2996
2997 /* Until we know more, just disable transition WMs */
2998 for (i = 0; i < intel_num_planes(intel_crtc); i++)
2999 trans_wm->plane_en[i] = false;
3000 trans_wm->cursor_en = false;
407b50f3
DL		 3001}
3002
2d41c0b5
PB		 3003static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3004 struct skl_ddb_allocation *ddb,
3005 struct skl_pipe_wm_parameters *params,
3006 struct skl_pipe_wm *pipe_wm)
3007{
3008 struct drm_device *dev = crtc->dev;
3009 const struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int level, max_level = ilk_wm_max_level(dev);
3012
3013 for (level = 0; level <= max_level; level++) {
3014 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3015 level, intel_num_planes(intel_crtc),
3016 &pipe_wm->wm[level]);
3017 }
3018 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3019
9414f563 3020 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3021}
3022
3023static void skl_compute_wm_results(struct drm_device *dev,
3024 struct skl_pipe_wm_parameters *p,
3025 struct skl_pipe_wm *p_wm,
3026 struct skl_wm_values *r,
3027 struct intel_crtc *intel_crtc)
3028{
3029 int level, max_level = ilk_wm_max_level(dev);
3030 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3031 uint32_t temp;
3032 int i;
2d41c0b5
PB		 3033
3034 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3035 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3036 temp = 0;
2d41c0b5
PB		 3037
3038 temp |= p_wm->wm[level].plane_res_l[i] <<
3039 PLANE_WM_LINES_SHIFT;
3040 temp |= p_wm->wm[level].plane_res_b[i];
3041 if (p_wm->wm[level].plane_en[i])
3042 temp |= PLANE_WM_EN;
3043
3044 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3045 }
3046
3047 temp = 0;
2d41c0b5
PB		 3048
3049 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3050 temp |= p_wm->wm[level].cursor_res_b;
3051
3052 if (p_wm->wm[level].cursor_en)
3053 temp |= PLANE_WM_EN;
3054
3055 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3056
3057 }
3058
9414f563
DL		 3059 /* transition WMs */
3060 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3061 temp = 0;
3062 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3063 temp |= p_wm->trans_wm.plane_res_b[i];
3064 if (p_wm->trans_wm.plane_en[i])
3065 temp |= PLANE_WM_EN;
3066
3067 r->plane_trans[pipe][i] = temp;
3068 }
3069
3070 temp = 0;
3071 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3072 temp |= p_wm->trans_wm.cursor_res_b;
3073 if (p_wm->trans_wm.cursor_en)
3074 temp |= PLANE_WM_EN;
3075
3076 r->cursor_trans[pipe] = temp;
3077
2d41c0b5
PB		 3078 r->wm_linetime[pipe] = p_wm->linetime;
3079}
3080
16160e3d
DL		 3081static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3082 const struct skl_ddb_entry *entry)
3083{
3084 if (entry->end)
3085 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3086 else
3087 I915_WRITE(reg, 0);
3088}
3089
2d41c0b5
PB		 3090static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3091 const struct skl_wm_values *new)
3092{
3093 struct drm_device *dev = dev_priv->dev;
3094 struct intel_crtc *crtc;
3095
3096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3097 int i, level, max_level = ilk_wm_max_level(dev);
3098 enum pipe pipe = crtc->pipe;
3099
5d374d96
DL		 3100 if (!new->dirty[pipe])
3101 continue;
8211bd5b 3102
5d374d96 3103 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3104
5d374d96
DL		 3105 for (level = 0; level <= max_level; level++) {
3106 for (i = 0; i < intel_num_planes(crtc); i++)
3107 I915_WRITE(PLANE_WM(pipe, i, level),
3108 new->plane[pipe][i][level]);
3109 I915_WRITE(CUR_WM(pipe, level),
3110 new->cursor[pipe][level]);
2d41c0b5 3111 }
5d374d96
DL		 3112 for (i = 0; i < intel_num_planes(crtc); i++)
3113 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3114 new->plane_trans[pipe][i]);
3115 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3116
3117 for (i = 0; i < intel_num_planes(crtc); i++)
3118 skl_ddb_entry_write(dev_priv,
3119 PLANE_BUF_CFG(pipe, i),
3120 &new->ddb.plane[pipe][i]);
3121
3122 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3123 &new->ddb.cursor[pipe]);
2d41c0b5 3124 }
2d41c0b5
PB		 3125}
3126
0e8fb7ba
DL		 3127/*
3128 * When setting up a new DDB allocation arrangement, we need to correctly
3129 * sequence the times at which the new allocations for the pipes are taken into
3130 * account or we'll have pipes fetching from space previously allocated to
3131 * another pipe.
3132 *
3133 * Roughly the sequence looks like:
3134 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3135 * overlapping with a previous light-up pipe (another way to put it is:
3136 * pipes with their new allocation strickly included into their old ones).
3137 * 2. re-allocate the other pipes that get their allocation reduced
3138 * 3. allocate the pipes having their allocation increased
3139 *
3140 * Steps 1. and 2. are here to take care of the following case:
3141 * - Initially DDB looks like this:
3142 * | B | C |
3143 * - enable pipe A.
3144 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3145 * allocation
3146 * | A | B | C |
3147 *
3148 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3149 */
3150
d21b795c
DL		 3151static void
3152skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3153{
0e8fb7ba
DL		 3154 int plane;
3155
d21b795c
DL		 3156 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3157
dd740780 3158 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3159 I915_WRITE(PLANE_SURF(pipe, plane),
3160 I915_READ(PLANE_SURF(pipe, plane)));
3161 }
3162 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3163}
3164
3165static bool
3166skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3167 const struct skl_ddb_allocation *new,
3168 enum pipe pipe)
3169{
3170 uint16_t old_size, new_size;
3171
3172 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3173 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3174
3175 return old_size != new_size &&
3176 new->pipe[pipe].start >= old->pipe[pipe].start &&
3177 new->pipe[pipe].end <= old->pipe[pipe].end;
3178}
3179
3180static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3181 struct skl_wm_values *new_values)
3182{
3183 struct drm_device *dev = dev_priv->dev;
3184 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3185 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3186 struct intel_crtc *crtc;
3187 enum pipe pipe;
3188
3189 new_ddb = &new_values->ddb;
3190 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3191
3192 /*
3193 * First pass: flush the pipes with the new allocation contained into
3194 * the old space.
3195 *
3196 * We'll wait for the vblank on those pipes to ensure we can safely
3197 * re-allocate the freed space without this pipe fetching from it.
3198 */
3199 for_each_intel_crtc(dev, crtc) {
3200 if (!crtc->active)
3201 continue;
3202
3203 pipe = crtc->pipe;
3204
3205 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3206 continue;
3207
d21b795c 3208 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3209 intel_wait_for_vblank(dev, pipe);
3210
3211 reallocated[pipe] = true;
3212 }
3213
3214
3215 /*
3216 * Second pass: flush the pipes that are having their allocation
3217 * reduced, but overlapping with a previous allocation.
3218 *
3219 * Here as well we need to wait for the vblank to make sure the freed
3220 * space is not used anymore.
3221 */
3222 for_each_intel_crtc(dev, crtc) {
3223 if (!crtc->active)
3224 continue;
3225
3226 pipe = crtc->pipe;
3227
3228 if (reallocated[pipe])
3229 continue;
3230
3231 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3232 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3233 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3234 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3235 reallocated[pipe] = true;
0e8fb7ba 3236 }
0e8fb7ba
DL		 3237 }
3238
3239 /*
3240 * Third pass: flush the pipes that got more space allocated.
3241 *
3242 * We don't need to actively wait for the update here, next vblank
3243 * will just get more DDB space with the correct WM values.
3244 */
3245 for_each_intel_crtc(dev, crtc) {
3246 if (!crtc->active)
3247 continue;
3248
3249 pipe = crtc->pipe;
3250
3251 /*
3252 * At this point, only the pipes more space than before are
3253 * left to re-allocate.
3254 */
3255 if (reallocated[pipe])
3256 continue;
3257
d21b795c 3258 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3259 }
3260}
3261
2d41c0b5
PB		 3262static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3263 struct skl_pipe_wm_parameters *params,
3264 struct intel_wm_config *config,
3265 struct skl_ddb_allocation *ddb, /* out */
3266 struct skl_pipe_wm *pipe_wm /* out */)
3267{
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269
3270 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3271 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3272 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3273
3274 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3275 return false;
3276
3277 intel_crtc->wm.skl_active = *pipe_wm;
3278 return true;
3279}
3280
3281static void skl_update_other_pipe_wm(struct drm_device *dev,
3282 struct drm_crtc *crtc,
3283 struct intel_wm_config *config,
3284 struct skl_wm_values *r)
3285{
3286 struct intel_crtc *intel_crtc;
3287 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3288
3289 /*
3290 * If the WM update hasn't changed the allocation for this_crtc (the
3291 * crtc we are currently computing the new WM values for), other
3292 * enabled crtcs will keep the same allocation and we don't need to
3293 * recompute anything for them.
3294 */
3295 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3296 return;
3297
3298 /*
3299 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3300 * other active pipes need new DDB allocation and WM values.
3301 */
3302 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3303 base.head) {
3304 struct skl_pipe_wm_parameters params = {};
3305 struct skl_pipe_wm pipe_wm = {};
3306 bool wm_changed;
3307
3308 if (this_crtc->pipe == intel_crtc->pipe)
3309 continue;
3310
3311 if (!intel_crtc->active)
3312 continue;
3313
3314 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3315 &params, config,
3316 &r->ddb, &pipe_wm);
3317
3318 /*
3319 * If we end up re-computing the other pipe WM values, it's
3320 * because it was really needed, so we expect the WM values to
3321 * be different.
3322 */
3323 WARN_ON(!wm_changed);
3324
3325 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3326 r->dirty[intel_crtc->pipe] = true;
3327 }
3328}
3329
3330static void skl_update_wm(struct drm_crtc *crtc)
3331{
3332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 struct skl_pipe_wm_parameters params = {};
3336 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3337 struct skl_pipe_wm pipe_wm = {};
3338 struct intel_wm_config config = {};
3339
3340 memset(results, 0, sizeof(*results));
3341
3342 skl_compute_wm_global_parameters(dev, &config);
3343
3344 if (!skl_update_pipe_wm(crtc, &params, &config,
3345 &results->ddb, &pipe_wm))
3346 return;
3347
3348 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3349 results->dirty[intel_crtc->pipe] = true;
3350
3351 skl_update_other_pipe_wm(dev, crtc, &config, results);
3352 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3353 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3354
3355 /* store the new configuration */
3356 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3357}
3358
3359static void
3360skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3361 uint32_t sprite_width, uint32_t sprite_height,
3362 int pixel_size, bool enabled, bool scaled)
3363{
3364 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3365 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3366
3367 intel_plane->wm.enabled = enabled;
3368 intel_plane->wm.scaled = scaled;
3369 intel_plane->wm.horiz_pixels = sprite_width;
3370 intel_plane->wm.vert_pixels = sprite_height;
3371 intel_plane->wm.bytes_per_pixel = pixel_size;
0fda6568
TU		 3372 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3373 /*
3374 * Framebuffer can be NULL on plane disable, but it does not
3375 * matter for watermarks if we assume no tiling in that case.
3376 */
3377 if (fb)
3378 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3379 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3380
3381 skl_update_wm(crtc);
3382}
3383
820c1980 3384static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3385{
7c4a395f 3386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3387 struct drm_device *dev = crtc->dev;
801bcfff 3388 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3389 struct ilk_wm_maximums max;
3390 struct ilk_pipe_wm_parameters params = {};
3391 struct ilk_wm_values results = {};
77c122bc 3392 enum intel_ddb_partitioning partitioning;
7c4a395f 3393 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3394 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3395 struct intel_wm_config config = {};
7c4a395f 3396
2a44b76b 3397 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3398
3399 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3400
3401 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3402 return;
861f3389 3403
7c4a395f 3404 intel_crtc->wm.active = pipe_wm;
861f3389 3405
2a44b76b
VS		 3406 ilk_compute_wm_config(dev, &config);
3407
34982fe1 3408 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3409 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3410
3411 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3412 if (INTEL_INFO(dev)->gen >= 7 &&
3413 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3414 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3415 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3416
820c1980 3417 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3418 } else {
198a1e9b 3419 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3420 }
3421
198a1e9b 3422 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3423 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3424
820c1980 3425 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3426
820c1980 3427 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3428}
3429
ed57cb8a
DL		 3430static void
3431ilk_update_sprite_wm(struct drm_plane *plane,
3432 struct drm_crtc *crtc,
3433 uint32_t sprite_width, uint32_t sprite_height,
3434 int pixel_size, bool enabled, bool scaled)
526682e9 3435{
8553c18e 3436 struct drm_device *dev = plane->dev;
adf3d35e 3437 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3438
adf3d35e
VS		 3439 intel_plane->wm.enabled = enabled;
3440 intel_plane->wm.scaled = scaled;
3441 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3442 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3443 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3444
8553c18e
VS		 3445 /*
3446 * IVB workaround: must disable low power watermarks for at least
3447 * one frame before enabling scaling. LP watermarks can be re-enabled
3448 * when scaling is disabled.
3449 *
3450 * WaCxSRDisabledForSpriteScaling:ivb
3451 */
3452 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3453 intel_wait_for_vblank(dev, intel_plane->pipe);
3454
820c1980 3455 ilk_update_wm(crtc);
526682e9
PZ		 3456}
3457
3078999f
PB		 3458static void skl_pipe_wm_active_state(uint32_t val,
3459 struct skl_pipe_wm *active,
3460 bool is_transwm,
3461 bool is_cursor,
3462 int i,
3463 int level)
3464{
3465 bool is_enabled = (val & PLANE_WM_EN) != 0;
3466
3467 if (!is_transwm) {
3468 if (!is_cursor) {
3469 active->wm[level].plane_en[i] = is_enabled;
3470 active->wm[level].plane_res_b[i] =
3471 val & PLANE_WM_BLOCKS_MASK;
3472 active->wm[level].plane_res_l[i] =
3473 (val >> PLANE_WM_LINES_SHIFT) &
3474 PLANE_WM_LINES_MASK;
3475 } else {
3476 active->wm[level].cursor_en = is_enabled;
3477 active->wm[level].cursor_res_b =
3478 val & PLANE_WM_BLOCKS_MASK;
3479 active->wm[level].cursor_res_l =
3480 (val >> PLANE_WM_LINES_SHIFT) &
3481 PLANE_WM_LINES_MASK;
3482 }
3483 } else {
3484 if (!is_cursor) {
3485 active->trans_wm.plane_en[i] = is_enabled;
3486 active->trans_wm.plane_res_b[i] =
3487 val & PLANE_WM_BLOCKS_MASK;
3488 active->trans_wm.plane_res_l[i] =
3489 (val >> PLANE_WM_LINES_SHIFT) &
3490 PLANE_WM_LINES_MASK;
3491 } else {
3492 active->trans_wm.cursor_en = is_enabled;
3493 active->trans_wm.cursor_res_b =
3494 val & PLANE_WM_BLOCKS_MASK;
3495 active->trans_wm.cursor_res_l =
3496 (val >> PLANE_WM_LINES_SHIFT) &
3497 PLANE_WM_LINES_MASK;
3498 }
3499 }
3500}
3501
3502static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3503{
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3508 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3509 enum pipe pipe = intel_crtc->pipe;
3510 int level, i, max_level;
3511 uint32_t temp;
3512
3513 max_level = ilk_wm_max_level(dev);
3514
3515 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3516
3517 for (level = 0; level <= max_level; level++) {
3518 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3519 hw->plane[pipe][i][level] =
3520 I915_READ(PLANE_WM(pipe, i, level));
3521 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3522 }
3523
3524 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3525 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3526 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3527
3ef00284 3528 if (!intel_crtc->active)
3078999f
PB		 3529 return;
3530
3531 hw->dirty[pipe] = true;
3532
3533 active->linetime = hw->wm_linetime[pipe];
3534
3535 for (level = 0; level <= max_level; level++) {
3536 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3537 temp = hw->plane[pipe][i][level];
3538 skl_pipe_wm_active_state(temp, active, false,
3539 false, i, level);
3540 }
3541 temp = hw->cursor[pipe][level];
3542 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3543 }
3544
3545 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3546 temp = hw->plane_trans[pipe][i];
3547 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3548 }
3549
3550 temp = hw->cursor_trans[pipe];
3551 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3552}
3553
3554void skl_wm_get_hw_state(struct drm_device *dev)
3555{
a269c583
DL		 3556 struct drm_i915_private *dev_priv = dev->dev_private;
3557 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3558 struct drm_crtc *crtc;
3559
a269c583 3560 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3561 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3562 skl_pipe_wm_get_hw_state(crtc);
3563}
3564
243e6a44
VS		 3565static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3566{
3567 struct drm_device *dev = crtc->dev;
3568 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3569 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3572 enum pipe pipe = intel_crtc->pipe;
3573 static const unsigned int wm0_pipe_reg[] = {
3574 [PIPE_A] = WM0_PIPEA_ILK,
3575 [PIPE_B] = WM0_PIPEB_ILK,
3576 [PIPE_C] = WM0_PIPEC_IVB,
3577 };
3578
3579 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3581 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3582
3ef00284 3583 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3584
3585 if (active->pipe_enabled) {
243e6a44
VS		 3586 u32 tmp = hw->wm_pipe[pipe];
3587
3588 /*
3589 * For active pipes LP0 watermark is marked as
3590 * enabled, and LP1+ watermaks as disabled since
3591 * we can't really reverse compute them in case
3592 * multiple pipes are active.
3593 */
3594 active->wm[0].enable = true;
3595 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3596 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3597 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3598 active->linetime = hw->wm_linetime[pipe];
3599 } else {
3600 int level, max_level = ilk_wm_max_level(dev);
3601
3602 /*
3603 * For inactive pipes, all watermark levels
3604 * should be marked as enabled but zeroed,
3605 * which is what we'd compute them to.
3606 */
3607 for (level = 0; level <= max_level; level++)
3608 active->wm[level].enable = true;
3609 }
3610}
3611
3612void ilk_wm_get_hw_state(struct drm_device *dev)
3613{
3614 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3615 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3616 struct drm_crtc *crtc;
3617
70e1e0ec 3618 for_each_crtc(dev, crtc)
243e6a44
VS		 3619 ilk_pipe_wm_get_hw_state(crtc);
3620
3621 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3622 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3623 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3624
3625 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3626 if (INTEL_INFO(dev)->gen >= 7) {
3627 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3628 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3629 }
243e6a44 3630
a42a5719 3631 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3632 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3633 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3634 else if (IS_IVYBRIDGE(dev))
3635 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3636 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3637
3638 hw->enable_fbc_wm =
3639 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3640}
3641
b445e3b0
ED		 3642/**
3643 * intel_update_watermarks - update FIFO watermark values based on current modes
3644 *
3645 * Calculate watermark values for the various WM regs based on current mode
3646 * and plane configuration.
3647 *
3648 * There are several cases to deal with here:
3649 * - normal (i.e. non-self-refresh)
3650 * - self-refresh (SR) mode
3651 * - lines are large relative to FIFO size (buffer can hold up to 2)
3652 * - lines are small relative to FIFO size (buffer can hold more than 2
3653 * lines), so need to account for TLB latency
3654 *
3655 * The normal calculation is:
3656 * watermark = dotclock * bytes per pixel * latency
3657 * where latency is platform & configuration dependent (we assume pessimal
3658 * values here).
3659 *
3660 * The SR calculation is:
3661 * watermark = (trunc(latency/line time)+1) * surface width *
3662 * bytes per pixel
3663 * where
3664 * line time = htotal / dotclock
3665 * surface width = hdisplay for normal plane and 64 for cursor
3666 * and latency is assumed to be high, as above.
3667 *
3668 * The final value programmed to the register should always be rounded up,
3669 * and include an extra 2 entries to account for clock crossings.
3670 *
3671 * We don't use the sprite, so we can ignore that. And on Crestline we have
3672 * to set the non-SR watermarks to 8.
3673 */
46ba614c 3674void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3675{
46ba614c 3676 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3677
3678 if (dev_priv->display.update_wm)
46ba614c 3679 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3680}
3681
adf3d35e
VS		 3682void intel_update_sprite_watermarks(struct drm_plane *plane,
3683 struct drm_crtc *crtc,
ed57cb8a
DL		 3684 uint32_t sprite_width,
3685 uint32_t sprite_height,
3686 int pixel_size,
39db4a4d 3687 bool enabled, bool scaled)
b445e3b0 3688{
adf3d35e 3689 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3690
3691 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3692 dev_priv->display.update_sprite_wm(plane, crtc,
3693 sprite_width, sprite_height,
39db4a4d 3694 pixel_size, enabled, scaled);
b445e3b0
ED		 3695}
3696
9270388e
DV		 3697/**
3698 * Lock protecting IPS related data structures
9270388e
DV		 3699 */
3700DEFINE_SPINLOCK(mchdev_lock);
3701
3702/* Global for IPS driver to get at the current i915 device. Protected by
3703 * mchdev_lock. */
3704static struct drm_i915_private *i915_mch_dev;
3705
2b4e57bd
ED		 3706bool ironlake_set_drps(struct drm_device *dev, u8 val)
3707{
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 u16 rgvswctl;
3710
9270388e
DV		 3711 assert_spin_locked(&mchdev_lock);
3712
2b4e57bd
ED		 3713 rgvswctl = I915_READ16(MEMSWCTL);
3714 if (rgvswctl & MEMCTL_CMD_STS) {
3715 DRM_DEBUG("gpu busy, RCS change rejected\n");
3716 return false; /* still busy with another command */
3717 }
3718
3719 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3720 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3721 I915_WRITE16(MEMSWCTL, rgvswctl);
3722 POSTING_READ16(MEMSWCTL);
3723
3724 rgvswctl |= MEMCTL_CMD_STS;
3725 I915_WRITE16(MEMSWCTL, rgvswctl);
3726
3727 return true;
3728}
3729
8090c6b9 3730static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3731{
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 u32 rgvmodectl = I915_READ(MEMMODECTL);
3734 u8 fmax, fmin, fstart, vstart;
3735
9270388e
DV		 3736 spin_lock_irq(&mchdev_lock);
3737
2b4e57bd
ED		 3738 /* Enable temp reporting */
3739 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3740 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3741
3742 /* 100ms RC evaluation intervals */
3743 I915_WRITE(RCUPEI, 100000);
3744 I915_WRITE(RCDNEI, 100000);
3745
3746 /* Set max/min thresholds to 90ms and 80ms respectively */
3747 I915_WRITE(RCBMAXAVG, 90000);
3748 I915_WRITE(RCBMINAVG, 80000);
3749
3750 I915_WRITE(MEMIHYST, 1);
3751
3752 /* Set up min, max, and cur for interrupt handling */
3753 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3754 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3755 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3756 MEMMODE_FSTART_SHIFT;
3757
3758 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3759 PXVFREQ_PX_SHIFT;
3760
20e4d407
DV		 3761 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3762 dev_priv->ips.fstart = fstart;
2b4e57bd 3763
20e4d407
DV		 3764 dev_priv->ips.max_delay = fstart;
3765 dev_priv->ips.min_delay = fmin;
3766 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3767
3768 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3769 fmax, fmin, fstart);
3770
3771 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3772
3773 /*
3774 * Interrupts will be enabled in ironlake_irq_postinstall
3775 */
3776
3777 I915_WRITE(VIDSTART, vstart);
3778 POSTING_READ(VIDSTART);
3779
3780 rgvmodectl |= MEMMODE_SWMODE_EN;
3781 I915_WRITE(MEMMODECTL, rgvmodectl);
3782
9270388e 3783 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3784 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3785 mdelay(1);
2b4e57bd
ED		 3786
3787 ironlake_set_drps(dev, fstart);
3788
20e4d407 3789 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3790 I915_READ(0x112e0);
20e4d407
DV		 3791 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3792 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3793 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3794
3795 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3796}
3797
8090c6b9 3798static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3799{
3800 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3801 u16 rgvswctl;
3802
3803 spin_lock_irq(&mchdev_lock);
3804
3805 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3806
3807 /* Ack interrupts, disable EFC interrupt */
3808 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3809 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3810 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3811 I915_WRITE(DEIIR, DE_PCU_EVENT);
3812 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3813
3814 /* Go back to the starting frequency */
20e4d407 3815 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3816 mdelay(1);
2b4e57bd
ED		 3817 rgvswctl |= MEMCTL_CMD_STS;
3818 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3819 mdelay(1);
2b4e57bd 3820
9270388e 3821 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3822}
3823
acbe9475
DV		 3824/* There's a funny hw issue where the hw returns all 0 when reading from
3825 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3826 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3827 * all limits and the gpu stuck at whatever frequency it is at atm).
3828 */
74ef1173 3829static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3830{
7b9e0ae6 3831 u32 limits;
2b4e57bd 3832
20b46e59
DV		 3833 /* Only set the down limit when we've reached the lowest level to avoid
3834 * getting more interrupts, otherwise leave this clear. This prevents a
3835 * race in the hw when coming out of rc6: There's a tiny window where
3836 * the hw runs at the minimal clock before selecting the desired
3837 * frequency, if the down threshold expires in that window we will not
3838 * receive a down interrupt. */
74ef1173
AG		 3839 if (IS_GEN9(dev_priv->dev)) {
3840 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3841 if (val <= dev_priv->rps.min_freq_softlimit)
3842 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3843 } else {
3844 limits = dev_priv->rps.max_freq_softlimit << 24;
3845 if (val <= dev_priv->rps.min_freq_softlimit)
3846 limits |= dev_priv->rps.min_freq_softlimit << 16;
3847 }
20b46e59
DV		 3848
3849 return limits;
3850}
3851
dd75fdc8
CW		 3852static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3853{
3854 int new_power;
8a586437
AG		 3855 u32 threshold_up = 0, threshold_down = 0; /* in % */
3856 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 3857
3858 new_power = dev_priv->rps.power;
3859 switch (dev_priv->rps.power) {
3860 case LOW_POWER:
b39fb297 3861 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3862 new_power = BETWEEN;
3863 break;
3864
3865 case BETWEEN:
b39fb297 3866 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3867 new_power = LOW_POWER;
b39fb297 3868 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3869 new_power = HIGH_POWER;
3870 break;
3871
3872 case HIGH_POWER:
b39fb297 3873 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3874 new_power = BETWEEN;
3875 break;
3876 }
3877 /* Max/min bins are special */
aed242ff 3878 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 3879 new_power = LOW_POWER;
aed242ff 3880 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3881 new_power = HIGH_POWER;
3882 if (new_power == dev_priv->rps.power)
3883 return;
3884
3885 /* Note the units here are not exactly 1us, but 1280ns. */
3886 switch (new_power) {
3887 case LOW_POWER:
3888 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 3889 ei_up = 16000;
3890 threshold_up = 95;
dd75fdc8
CW		 3891
3892 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 3893 ei_down = 32000;
3894 threshold_down = 85;
dd75fdc8
CW		 3895 break;
3896
3897 case BETWEEN:
3898 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 3899 ei_up = 13000;
3900 threshold_up = 90;
dd75fdc8
CW		 3901
3902 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 3903 ei_down = 32000;
3904 threshold_down = 75;
dd75fdc8
CW		 3905 break;
3906
3907 case HIGH_POWER:
3908 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 3909 ei_up = 10000;
3910 threshold_up = 85;
dd75fdc8
CW		 3911
3912 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 3913 ei_down = 32000;
3914 threshold_down = 60;
dd75fdc8
CW		 3915 break;
3916 }
3917
8a586437
AG		 3918 I915_WRITE(GEN6_RP_UP_EI,
3919 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3920 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3921 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3922
3923 I915_WRITE(GEN6_RP_DOWN_EI,
3924 GT_INTERVAL_FROM_US(dev_priv, ei_down));
3925 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3926 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
3927
3928 I915_WRITE(GEN6_RP_CONTROL,
3929 GEN6_RP_MEDIA_TURBO |
3930 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3931 GEN6_RP_MEDIA_IS_GFX |
3932 GEN6_RP_ENABLE |
3933 GEN6_RP_UP_BUSY_AVG |
3934 GEN6_RP_DOWN_IDLE_AVG);
3935
dd75fdc8 3936 dev_priv->rps.power = new_power;
8fb55197
CW		 3937 dev_priv->rps.up_threshold = threshold_up;
3938 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 3939 dev_priv->rps.last_adj = 0;
3940}
3941
2876ce73
CW		 3942static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3943{
3944 u32 mask = 0;
3945
3946 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 3947 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 3948 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 3949 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 3950
7b3c29f6
CW		 3951 mask &= dev_priv->pm_rps_events;
3952
59d02a1f 3953 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 3954}
3955
b8a5ff8d
JM		 3956/* gen6_set_rps is called to update the frequency request, but should also be
3957 * called when the range (min_delay and max_delay) is modified so that we can
3958 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 3959static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 3960{
3961 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3962
4fc688ce 3963 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 3964 WARN_ON(val > dev_priv->rps.max_freq);
3965 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 3966
eb64cad1
CW		 3967 /* min/max delay may still have been modified so be sure to
3968 * write the limits value.
3969 */
3970 if (val != dev_priv->rps.cur_freq) {
3971 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3972
5704195c
AG		 3973 if (IS_GEN9(dev))
3974 I915_WRITE(GEN6_RPNSWREQ,
3975 GEN9_FREQUENCY(val));
3976 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3977 I915_WRITE(GEN6_RPNSWREQ,
3978 HSW_FREQUENCY(val));
3979 else
3980 I915_WRITE(GEN6_RPNSWREQ,
3981 GEN6_FREQUENCY(val) |
3982 GEN6_OFFSET(0) |
3983 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3984 }
7b9e0ae6 3985
7b9e0ae6
CW		 3986 /* Make sure we continue to get interrupts
3987 * until we hit the minimum or maximum frequencies.
3988 */
74ef1173 3989 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 3990 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3991
d5570a72
BW		 3992 POSTING_READ(GEN6_RPNSWREQ);
3993
b39fb297 3994 dev_priv->rps.cur_freq = val;
be2cde9a 3995 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3996}
3997
ffe02b40
VS		 3998static void valleyview_set_rps(struct drm_device *dev, u8 val)
3999{
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001
4002 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4003 WARN_ON(val > dev_priv->rps.max_freq);
4004 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4005
4006 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4007 "Odd GPU freq value\n"))
4008 val &= ~1;
4009
8fb55197 4010 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4011 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4012 if (!IS_CHERRYVIEW(dev_priv))
4013 gen6_set_rps_thresholds(dev_priv, val);
4014 }
ffe02b40
VS		 4015
4016 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4017
4018 dev_priv->rps.cur_freq = val;
4019 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4020}
4021
76c3552f
D		 4022/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4023 *
4024 * * If Gfx is Idle, then
4025 * 1. Mask Turbo interrupts
4026 * 2. Bring up Gfx clock
4027 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4028 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4029 * 5. Unmask Turbo interrupts
4030*/
4031static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4032{
5549d25f 4033 struct drm_device *dev = dev_priv->dev;
aed242ff 4034 u32 val = dev_priv->rps.idle_freq;
5549d25f 4035
21a11fff
VS		 4036 /* CHV and latest VLV don't need to force the gfx clock */
4037 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
aed242ff 4038 valleyview_set_rps(dev_priv->dev, val);
5549d25f
D		 4039 return;
4040 }
4041
76c3552f
D		 4042 /*
4043 * When we are idle. Drop to min voltage state.
4044 */
4045
aed242ff 4046 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4047 return;
4048
4049 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 4050 I915_WRITE(GEN6_PMINTRMSK,
4051 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 4052
650ad970 4053 vlv_force_gfx_clock(dev_priv, true);
76c3552f 4054
aed242ff 4055 dev_priv->rps.cur_freq = val;
76c3552f 4056
aed242ff 4057 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
76c3552f
D		 4058
4059 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 4060 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 4061 DRM_ERROR("timed out waiting for Punit\n");
4062
8fb55197 4063 gen6_set_rps_thresholds(dev_priv, val);
650ad970 4064 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4065
aed242ff 4066 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
76c3552f
D		 4067}
4068
43cf3bf0
CW		 4069void gen6_rps_busy(struct drm_i915_private *dev_priv)
4070{
4071 mutex_lock(&dev_priv->rps.hw_lock);
4072 if (dev_priv->rps.enabled) {
4073 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4074 gen6_rps_reset_ei(dev_priv);
4075 I915_WRITE(GEN6_PMINTRMSK,
4076 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4077 }
4078 mutex_unlock(&dev_priv->rps.hw_lock);
4079}
4080
b29c19b6
CW		 4081void gen6_rps_idle(struct drm_i915_private *dev_priv)
4082{
691bb717
DL		 4083 struct drm_device *dev = dev_priv->dev;
4084
b29c19b6 4085 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4086 if (dev_priv->rps.enabled) {
21a11fff 4087 if (IS_VALLEYVIEW(dev))
76c3552f 4088 vlv_set_rps_idle(dev_priv);
7526ed79 4089 else
aed242ff 4090 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4091 dev_priv->rps.last_adj = 0;
43cf3bf0 4092 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4093 }
1854d5ca
CW		 4094
4095 while (!list_empty(&dev_priv->rps.clients))
4096 list_del_init(dev_priv->rps.clients.next);
b29c19b6
CW		 4097 mutex_unlock(&dev_priv->rps.hw_lock);
4098}
4099
1854d5ca
CW		 4100void gen6_rps_boost(struct drm_i915_private *dev_priv,
4101 struct drm_i915_file_private *file_priv)
b29c19b6 4102{
43cf3bf0
CW		 4103 u32 val;
4104
b29c19b6 4105 mutex_lock(&dev_priv->rps.hw_lock);
43cf3bf0
CW		 4106 val = dev_priv->rps.max_freq_softlimit;
4107 if (dev_priv->rps.enabled &&
4108 dev_priv->mm.busy &&
1854d5ca
CW		 4109 dev_priv->rps.cur_freq < val &&
4110 (file_priv == NULL || list_empty(&file_priv->rps_boost))) {
43cf3bf0 4111 intel_set_rps(dev_priv->dev, val);
c0951f0c 4112 dev_priv->rps.last_adj = 0;
1854d5ca
CW		 4113
4114 if (file_priv != NULL) {
4115 list_add(&file_priv->rps_boost, &dev_priv->rps.clients);
4116 file_priv->rps_boosts++;
4117 } else
4118 dev_priv->rps.boosts++;
c0951f0c 4119 }
b29c19b6
CW		 4120 mutex_unlock(&dev_priv->rps.hw_lock);
4121}
4122
ffe02b40 4123void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4124{
ffe02b40
VS		 4125 if (IS_VALLEYVIEW(dev))
4126 valleyview_set_rps(dev, val);
4127 else
4128 gen6_set_rps(dev, val);
0a073b84
JB		 4129}
4130
20e49366
ZW		 4131static void gen9_disable_rps(struct drm_device *dev)
4132{
4133 struct drm_i915_private *dev_priv = dev->dev_private;
4134
4135 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4136 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4137}
4138
44fc7d5c 4139static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4140{
4141 struct drm_i915_private *dev_priv = dev->dev_private;
4142
4143 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4144 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4145}
4146
38807746
D		 4147static void cherryview_disable_rps(struct drm_device *dev)
4148{
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4150
4151 I915_WRITE(GEN6_RC_CONTROL, 0);
4152}
4153
44fc7d5c
DV		 4154static void valleyview_disable_rps(struct drm_device *dev)
4155{
4156 struct drm_i915_private *dev_priv = dev->dev_private;
4157
98a2e5f9
D		 4158 /* we're doing forcewake before Disabling RC6,
4159 * This what the BIOS expects when going into suspend */
59bad947 4160 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4161
44fc7d5c 4162 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4163
59bad947 4164 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4165}
4166
dc39fff7
BW		 4167static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4168{
91ca689a
ID		 4169 if (IS_VALLEYVIEW(dev)) {
4170 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4171 mode = GEN6_RC_CTL_RC6_ENABLE;
4172 else
4173 mode = 0;
4174 }
58abf1da
RV		 4175 if (HAS_RC6p(dev))
4176 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4177 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4178 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4179 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4180
4181 else
4182 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4183 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4184}
4185
e6069ca8 4186static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4187{
eb4926e4
DL		 4188 /* No RC6 before Ironlake */
4189 if (INTEL_INFO(dev)->gen < 5)
4190 return 0;
4191
e6069ca8
ID		 4192 /* RC6 is only on Ironlake mobile not on desktop */
4193 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4194 return 0;
4195
456470eb 4196 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4197 if (enable_rc6 >= 0) {
4198 int mask;
4199
58abf1da 4200 if (HAS_RC6p(dev))
e6069ca8
ID		 4201 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4202 INTEL_RC6pp_ENABLE;
4203 else
4204 mask = INTEL_RC6_ENABLE;
4205
4206 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4207 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4208 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4209
4210 return enable_rc6 & mask;
4211 }
2b4e57bd 4212
6567d748
CW		 4213 /* Disable RC6 on Ironlake */
4214 if (INTEL_INFO(dev)->gen == 5)
4215 return 0;
2b4e57bd 4216
8bade1ad 4217 if (IS_IVYBRIDGE(dev))
cca84a1f 4218 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4219
4220 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4221}
4222
e6069ca8
ID		 4223int intel_enable_rc6(const struct drm_device *dev)
4224{
4225 return i915.enable_rc6;
4226}
4227
93ee2920 4228static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4229{
93ee2920
TR		 4230 struct drm_i915_private *dev_priv = dev->dev_private;
4231 uint32_t rp_state_cap;
4232 u32 ddcc_status = 0;
4233 int ret;
4234
4235 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 4236 /* All of these values are in units of 50MHz */
4237 dev_priv->rps.cur_freq = 0;
93ee2920 4238 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4239 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4240 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4241 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
cee991cb
AG		 4242 if (IS_SKYLAKE(dev)) {
4243 /* Store the frequency values in 16.66 MHZ units, which is
4244 the natural hardware unit for SKL */
4245 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4246 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4247 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4248 }
3280e8b0
BW		 4249 /* hw_max = RP0 until we check for overclocking */
4250 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4251
93ee2920
TR		 4252 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4253 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4254 ret = sandybridge_pcode_read(dev_priv,
4255 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4256 &ddcc_status);
4257 if (0 == ret)
4258 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4259 clamp_t(u8,
4260 ((ddcc_status >> 8) & 0xff),
4261 dev_priv->rps.min_freq,
4262 dev_priv->rps.max_freq);
93ee2920
TR		 4263 }
4264
aed242ff
CW		 4265 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4266
3280e8b0
BW		 4267 /* Preserve min/max settings in case of re-init */
4268 if (dev_priv->rps.max_freq_softlimit == 0)
4269 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4270
93ee2920
TR		 4271 if (dev_priv->rps.min_freq_softlimit == 0) {
4272 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4273 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR		 4274 /* max(RPe, 450 MHz) */
4275 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR		 4276 else
4277 dev_priv->rps.min_freq_softlimit =
4278 dev_priv->rps.min_freq;
4279 }
3280e8b0
BW		 4280}
4281
b6fef0ef 4282/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4283static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4284{
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4286
4287 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4288
ba1c554c
DL		 4289 gen6_init_rps_frequencies(dev);
4290
0beb059a
AG		 4291 /* Program defaults and thresholds for RPS*/
4292 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4293 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4294
4295 /* 1 second timeout*/
4296 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4297 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4298
b6fef0ef 4299 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4300
0beb059a
AG		 4301 /* Leaning on the below call to gen6_set_rps to program/setup the
4302 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4303 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4304 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4305 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4306
4307 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4308}
4309
4310static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4311{
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct intel_engine_cs *ring;
4314 uint32_t rc6_mask = 0;
4315 int unused;
4316
4317 /* 1a: Software RC state - RC0 */
4318 I915_WRITE(GEN6_RC_STATE, 0);
4319
4320 /* 1b: Get forcewake during program sequence. Although the driver
4321 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4322 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4323
4324 /* 2a: Disable RC states. */
4325 I915_WRITE(GEN6_RC_CONTROL, 0);
4326
4327 /* 2b: Program RC6 thresholds.*/
4328 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4329 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4330 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4331 for_each_ring(ring, dev_priv, unused)
4332 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4333 I915_WRITE(GEN6_RC_SLEEP, 0);
4334 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4335
38c23527
ZW		 4336 /* 2c: Program Coarse Power Gating Policies. */
4337 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4338 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4339
20e49366
ZW		 4340 /* 3a: Enable RC6 */
4341 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4342 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4343 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4344 "on" : "off");
4345 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4346 GEN6_RC_CTL_EI_MODE(1) |
4347 rc6_mask);
4348
38c23527 4349 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
a4104c55
SK		 4350 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4351 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4352
38c23527 4353
59bad947 4354 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4355
4356}
4357
6edee7f3
BW		 4358static void gen8_enable_rps(struct drm_device *dev)
4359{
4360 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4361 struct intel_engine_cs *ring;
93ee2920 4362 uint32_t rc6_mask = 0;
6edee7f3
BW		 4363 int unused;
4364
4365 /* 1a: Software RC state - RC0 */
4366 I915_WRITE(GEN6_RC_STATE, 0);
4367
4368 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4369 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4370 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4371
4372 /* 2a: Disable RC states. */
4373 I915_WRITE(GEN6_RC_CONTROL, 0);
4374
93ee2920
TR		 4375 /* Initialize rps frequencies */
4376 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4377
4378 /* 2b: Program RC6 thresholds.*/
4379 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4380 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4381 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4382 for_each_ring(ring, dev_priv, unused)
4383 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4384 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4385 if (IS_BROADWELL(dev))
4386 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4387 else
4388 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4389
4390 /* 3: Enable RC6 */
4391 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4392 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4393 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4394 if (IS_BROADWELL(dev))
4395 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4396 GEN7_RC_CTL_TO_MODE |
4397 rc6_mask);
4398 else
4399 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4400 GEN6_RC_CTL_EI_MODE(1) |
4401 rc6_mask);
6edee7f3
BW		 4402
4403 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4404 I915_WRITE(GEN6_RPNSWREQ,
4405 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4406 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4407 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4408 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4409 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4410
4411 /* Docs recommend 900MHz, and 300 MHz respectively */
4412 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4413 dev_priv->rps.max_freq_softlimit << 24 |
4414 dev_priv->rps.min_freq_softlimit << 16);
4415
4416 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4417 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4418 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4419 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4420
4421 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4422
4423 /* 5: Enable RPS */
7526ed79
DV		 4424 I915_WRITE(GEN6_RP_CONTROL,
4425 GEN6_RP_MEDIA_TURBO |
4426 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4427 GEN6_RP_MEDIA_IS_GFX |
4428 GEN6_RP_ENABLE |
4429 GEN6_RP_UP_BUSY_AVG |
4430 GEN6_RP_DOWN_IDLE_AVG);
4431
4432 /* 6: Ring frequency + overclocking (our driver does this later */
4433
c7f3153a 4434 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4435 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4436
59bad947 4437 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4438}
4439
79f5b2c7 4440static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4441{
79f5b2c7 4442 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4443 struct intel_engine_cs *ring;
d060c169 4444 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4445 u32 gtfifodbg;
2b4e57bd 4446 int rc6_mode;
42c0526c 4447 int i, ret;
2b4e57bd 4448
4fc688ce 4449 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4450
2b4e57bd
ED		 4451 /* Here begins a magic sequence of register writes to enable
4452 * auto-downclocking.
4453 *
4454 * Perhaps there might be some value in exposing these to
4455 * userspace...
4456 */
4457 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4458
4459 /* Clear the DBG now so we don't confuse earlier errors */
4460 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4461 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4462 I915_WRITE(GTFIFODBG, gtfifodbg);
4463 }
4464
59bad947 4465 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4466
93ee2920
TR		 4467 /* Initialize rps frequencies */
4468 gen6_init_rps_frequencies(dev);
dd0a1aa1 4469
2b4e57bd
ED		 4470 /* disable the counters and set deterministic thresholds */
4471 I915_WRITE(GEN6_RC_CONTROL, 0);
4472
4473 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4474 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4475 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4476 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4477 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4478
b4519513
CW		 4479 for_each_ring(ring, dev_priv, i)
4480 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4481
4482 I915_WRITE(GEN6_RC_SLEEP, 0);
4483 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4484 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4485 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4486 else
4487 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4488 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4489 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4490
5a7dc92a 4491 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4492 rc6_mode = intel_enable_rc6(dev_priv->dev);
4493 if (rc6_mode & INTEL_RC6_ENABLE)
4494 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4495
5a7dc92a
ED		 4496 /* We don't use those on Haswell */
4497 if (!IS_HASWELL(dev)) {
4498 if (rc6_mode & INTEL_RC6p_ENABLE)
4499 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4500
5a7dc92a
ED		 4501 if (rc6_mode & INTEL_RC6pp_ENABLE)
4502 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4503 }
2b4e57bd 4504
dc39fff7 4505 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4506
4507 I915_WRITE(GEN6_RC_CONTROL,
4508 rc6_mask |
4509 GEN6_RC_CTL_EI_MODE(1) |
4510 GEN6_RC_CTL_HW_ENABLE);
4511
dd75fdc8
CW		 4512 /* Power down if completely idle for over 50ms */
4513 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4514 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4515
42c0526c 4516 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4517 if (ret)
42c0526c 4518 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4519
4520 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4521 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4522 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4523 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4524 (pcu_mbox & 0xff) * 50);
b39fb297 4525 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4526 }
4527
dd75fdc8 4528 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4529 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4530
31643d54
BW		 4531 rc6vids = 0;
4532 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4533 if (IS_GEN6(dev) && ret) {
4534 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4535 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4536 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4537 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4538 rc6vids &= 0xffff00;
4539 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4540 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4541 if (ret)
4542 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4543 }
4544
59bad947 4545 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4546}
4547
c2bc2fc5 4548static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4549{
79f5b2c7 4550 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4551 int min_freq = 15;
3ebecd07
CW		 4552 unsigned int gpu_freq;
4553 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4554 int scaling_factor = 180;
eda79642 4555 struct cpufreq_policy *policy;
2b4e57bd 4556
4fc688ce 4557 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4558
eda79642
BW		 4559 policy = cpufreq_cpu_get(0);
4560 if (policy) {
4561 max_ia_freq = policy->cpuinfo.max_freq;
4562 cpufreq_cpu_put(policy);
4563 } else {
4564 /*
4565 * Default to measured freq if none found, PCU will ensure we
4566 * don't go over
4567 */
2b4e57bd 4568 max_ia_freq = tsc_khz;
eda79642 4569 }
2b4e57bd
ED		 4570
4571 /* Convert from kHz to MHz */
4572 max_ia_freq /= 1000;
4573
153b4b95 4574 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4575 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4576 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4577
2b4e57bd
ED		 4578 /*
4579 * For each potential GPU frequency, load a ring frequency we'd like
4580 * to use for memory access. We do this by specifying the IA frequency
4581 * the PCU should use as a reference to determine the ring frequency.
4582 */
6985b352 4583 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4584 gpu_freq--) {
6985b352 4585 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4586 unsigned int ia_freq = 0, ring_freq = 0;
4587
46c764d4
BW		 4588 if (INTEL_INFO(dev)->gen >= 8) {
4589 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4590 ring_freq = max(min_ring_freq, gpu_freq);
4591 } else if (IS_HASWELL(dev)) {
f6aca45c 4592 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4593 ring_freq = max(min_ring_freq, ring_freq);
4594 /* leave ia_freq as the default, chosen by cpufreq */
4595 } else {
4596 /* On older processors, there is no separate ring
4597 * clock domain, so in order to boost the bandwidth
4598 * of the ring, we need to upclock the CPU (ia_freq).
4599 *
4600 * For GPU frequencies less than 750MHz,
4601 * just use the lowest ring freq.
4602 */
4603 if (gpu_freq < min_freq)
4604 ia_freq = 800;
4605 else
4606 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4607 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4608 }
2b4e57bd 4609
42c0526c
BW		 4610 sandybridge_pcode_write(dev_priv,
4611 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4612 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4613 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4614 gpu_freq);
2b4e57bd 4615 }
2b4e57bd
ED		 4616}
4617
c2bc2fc5
ID		 4618void gen6_update_ring_freq(struct drm_device *dev)
4619{
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621
4622 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4623 return;
4624
4625 mutex_lock(&dev_priv->rps.hw_lock);
4626 __gen6_update_ring_freq(dev);
4627 mutex_unlock(&dev_priv->rps.hw_lock);
4628}
4629
03af2045 4630static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4631{
095acd5f 4632 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4633 u32 val, rp0;
4634
095acd5f
D		 4635 if (dev->pdev->revision >= 0x20) {
4636 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4637
095acd5f
D		 4638 switch (INTEL_INFO(dev)->eu_total) {
4639 case 8:
4640 /* (2 * 4) config */
4641 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4642 break;
4643 case 12:
4644 /* (2 * 6) config */
4645 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4646 break;
4647 case 16:
4648 /* (2 * 8) config */
4649 default:
4650 /* Setting (2 * 8) Min RP0 for any other combination */
4651 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4652 break;
4653 }
4654 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4655 } else {
4656 /* For pre-production hardware */
4657 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4658 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4659 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4660 }
2b6b3a09
D		 4661 return rp0;
4662}
4663
4664static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4665{
4666 u32 val, rpe;
4667
4668 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4669 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4670
4671 return rpe;
4672}
4673
7707df4a
D		 4674static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4675{
095acd5f 4676 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4677 u32 val, rp1;
4678
095acd5f
D		 4679 if (dev->pdev->revision >= 0x20) {
4680 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4681 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4682 } else {
4683 /* For pre-production hardware */
4684 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4685 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4686 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4687 }
7707df4a
D		 4688 return rp1;
4689}
4690
03af2045 4691static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4692{
095acd5f 4693 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4694 u32 val, rpn;
4695
095acd5f
D		 4696 if (dev->pdev->revision >= 0x20) {
4697 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4698 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4699 FB_GFX_FREQ_FUSE_MASK);
4700 } else { /* For pre-production hardware */
4701 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4702 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4703 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4704 }
4705
2b6b3a09
D		 4706 return rpn;
4707}
4708
f8f2b001
D		 4709static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4710{
4711 u32 val, rp1;
4712
4713 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4714
4715 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4716
4717 return rp1;
4718}
4719
03af2045 4720static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4721{
4722 u32 val, rp0;
4723
64936258 4724 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4725
4726 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4727 /* Clamp to max */
4728 rp0 = min_t(u32, rp0, 0xea);
4729
4730 return rp0;
4731}
4732
4733static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4734{
4735 u32 val, rpe;
4736
64936258 4737 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4738 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4739 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4740 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4741
4742 return rpe;
4743}
4744
03af2045 4745static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4746{
64936258 4747 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4748}
4749
ae48434c
ID		 4750/* Check that the pctx buffer wasn't move under us. */
4751static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4752{
4753 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4754
4755 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4756 dev_priv->vlv_pctx->stolen->start);
4757}
4758
38807746
D		 4759
4760/* Check that the pcbr address is not empty. */
4761static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4762{
4763 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4764
4765 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4766}
4767
4768static void cherryview_setup_pctx(struct drm_device *dev)
4769{
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4771 unsigned long pctx_paddr, paddr;
4772 struct i915_gtt *gtt = &dev_priv->gtt;
4773 u32 pcbr;
4774 int pctx_size = 32*1024;
4775
4776 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4777
4778 pcbr = I915_READ(VLV_PCBR);
4779 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4780 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4781 paddr = (dev_priv->mm.stolen_base +
4782 (gtt->stolen_size - pctx_size));
4783
4784 pctx_paddr = (paddr & (~4095));
4785 I915_WRITE(VLV_PCBR, pctx_paddr);
4786 }
ce611ef8
VS		 4787
4788 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4789}
4790
c9cddffc
JB		 4791static void valleyview_setup_pctx(struct drm_device *dev)
4792{
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794 struct drm_i915_gem_object *pctx;
4795 unsigned long pctx_paddr;
4796 u32 pcbr;
4797 int pctx_size = 24*1024;
4798
17b0c1f7
ID		 4799 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4800
c9cddffc
JB		 4801 pcbr = I915_READ(VLV_PCBR);
4802 if (pcbr) {
4803 /* BIOS set it up already, grab the pre-alloc'd space */
4804 int pcbr_offset;
4805
4806 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4807 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4808 pcbr_offset,
190d6cd5 4809 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4810 pctx_size);
4811 goto out;
4812 }
4813
ce611ef8
VS		 4814 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4815
c9cddffc
JB		 4816 /*
4817 * From the Gunit register HAS:
4818 * The Gfx driver is expected to program this register and ensure
4819 * proper allocation within Gfx stolen memory. For example, this
4820 * register should be programmed such than the PCBR range does not
4821 * overlap with other ranges, such as the frame buffer, protected
4822 * memory, or any other relevant ranges.
4823 */
4824 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4825 if (!pctx) {
4826 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4827 return;
4828 }
4829
4830 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4831 I915_WRITE(VLV_PCBR, pctx_paddr);
4832
4833out:
ce611ef8 4834 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4835 dev_priv->vlv_pctx = pctx;
4836}
4837
ae48434c
ID		 4838static void valleyview_cleanup_pctx(struct drm_device *dev)
4839{
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841
4842 if (WARN_ON(!dev_priv->vlv_pctx))
4843 return;
4844
4845 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4846 dev_priv->vlv_pctx = NULL;
4847}
4848
4e80519e
ID		 4849static void valleyview_init_gt_powersave(struct drm_device *dev)
4850{
4851 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4852 u32 val;
4e80519e
ID		 4853
4854 valleyview_setup_pctx(dev);
4855
4856 mutex_lock(&dev_priv->rps.hw_lock);
4857
2bb25c17
VS		 4858 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4859 switch ((val >> 6) & 3) {
4860 case 0:
4861 case 1:
4862 dev_priv->mem_freq = 800;
4863 break;
4864 case 2:
4865 dev_priv->mem_freq = 1066;
4866 break;
4867 case 3:
4868 dev_priv->mem_freq = 1333;
4869 break;
4870 }
80b83b62 4871 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4872
4e80519e
ID		 4873 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4874 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4875 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4876 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4877 dev_priv->rps.max_freq);
4878
4879 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4880 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4881 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4882 dev_priv->rps.efficient_freq);
4883
f8f2b001
D		 4884 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4885 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4886 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4887 dev_priv->rps.rp1_freq);
4888
4e80519e
ID		 4889 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4890 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4891 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4892 dev_priv->rps.min_freq);
4893
aed242ff
CW		 4894 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4895
4e80519e
ID		 4896 /* Preserve min/max settings in case of re-init */
4897 if (dev_priv->rps.max_freq_softlimit == 0)
4898 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4899
4900 if (dev_priv->rps.min_freq_softlimit == 0)
4901 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4902
4903 mutex_unlock(&dev_priv->rps.hw_lock);
4904}
4905
38807746
D		 4906static void cherryview_init_gt_powersave(struct drm_device *dev)
4907{
2b6b3a09 4908 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4909 u32 val;
2b6b3a09 4910
38807746 4911 cherryview_setup_pctx(dev);
2b6b3a09
D		 4912
4913 mutex_lock(&dev_priv->rps.hw_lock);
4914
c6e8f39d
VS		 4915 mutex_lock(&dev_priv->dpio_lock);
4916 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4917 mutex_unlock(&dev_priv->dpio_lock);
4918
2bb25c17
VS		 4919 switch ((val >> 2) & 0x7) {
4920 case 0:
4921 case 1:
4922 dev_priv->rps.cz_freq = 200;
4923 dev_priv->mem_freq = 1600;
4924 break;
4925 case 2:
4926 dev_priv->rps.cz_freq = 267;
4927 dev_priv->mem_freq = 1600;
4928 break;
4929 case 3:
4930 dev_priv->rps.cz_freq = 333;
4931 dev_priv->mem_freq = 2000;
4932 break;
4933 case 4:
4934 dev_priv->rps.cz_freq = 320;
4935 dev_priv->mem_freq = 1600;
4936 break;
4937 case 5:
4938 dev_priv->rps.cz_freq = 400;
4939 dev_priv->mem_freq = 1600;
4940 break;
4941 }
80b83b62 4942 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4943
2b6b3a09
D		 4944 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4945 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4946 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4947 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 4948 dev_priv->rps.max_freq);
4949
4950 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4951 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4952 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4953 dev_priv->rps.efficient_freq);
4954
7707df4a
D		 4955 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4956 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 4957 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 4958 dev_priv->rps.rp1_freq);
4959
2b6b3a09
D		 4960 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4961 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4962 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 4963 dev_priv->rps.min_freq);
4964
1c14762d
VS		 4965 WARN_ONCE((dev_priv->rps.max_freq |
4966 dev_priv->rps.efficient_freq |
4967 dev_priv->rps.rp1_freq |
4968 dev_priv->rps.min_freq) & 1,
4969 "Odd GPU freq values\n");
4970
aed242ff
CW		 4971 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4972
2b6b3a09
D		 4973 /* Preserve min/max settings in case of re-init */
4974 if (dev_priv->rps.max_freq_softlimit == 0)
4975 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4976
4977 if (dev_priv->rps.min_freq_softlimit == 0)
4978 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4979
4980 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4981}
4982
4e80519e
ID		 4983static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4984{
4985 valleyview_cleanup_pctx(dev);
4986}
4987
38807746
D		 4988static void cherryview_enable_rps(struct drm_device *dev)
4989{
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_engine_cs *ring;
2b6b3a09 4992 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4993 int i;
4994
4995 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4996
4997 gtfifodbg = I915_READ(GTFIFODBG);
4998 if (gtfifodbg) {
4999 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5000 gtfifodbg);
5001 I915_WRITE(GTFIFODBG, gtfifodbg);
5002 }
5003
5004 cherryview_check_pctx(dev_priv);
5005
5006 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5007 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5008 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5009
160614a2
VS		 5010 /* Disable RC states. */
5011 I915_WRITE(GEN6_RC_CONTROL, 0);
5012
38807746
D		 5013 /* 2a: Program RC6 thresholds.*/
5014 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5015 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5016 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5017
5018 for_each_ring(ring, dev_priv, i)
5019 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5020 I915_WRITE(GEN6_RC_SLEEP, 0);
5021
af5a75a3
VS		 5022 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
5023 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D		 5024
5025 /* allows RC6 residency counter to work */
5026 I915_WRITE(VLV_COUNTER_CONTROL,
5027 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5028 VLV_MEDIA_RC6_COUNT_EN |
5029 VLV_RENDER_RC6_COUNT_EN));
5030
5031 /* For now we assume BIOS is allocating and populating the PCBR */
5032 pcbr = I915_READ(VLV_PCBR);
5033
38807746
D		 5034 /* 3: Enable RC6 */
5035 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5036 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5037 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5038
5039 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5040
2b6b3a09 5041 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5042 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5043 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5044 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5045 I915_WRITE(GEN6_RP_UP_EI, 66000);
5046 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5047
5048 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5049
5050 /* 5: Enable RPS */
5051 I915_WRITE(GEN6_RP_CONTROL,
5052 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5053 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5054 GEN6_RP_ENABLE |
5055 GEN6_RP_UP_BUSY_AVG |
5056 GEN6_RP_DOWN_IDLE_AVG);
5057
5058 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5059
8d40c3ae
VS		 5060 /* RPS code assumes GPLL is used */
5061 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5062
c8e9627d 5063 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5064 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5065
5066 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5067 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5068 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5069 dev_priv->rps.cur_freq);
5070
5071 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5072 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5073 dev_priv->rps.efficient_freq);
5074
5075 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5076
59bad947 5077 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5078}
5079
0a073b84
JB		 5080static void valleyview_enable_rps(struct drm_device *dev)
5081{
5082 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5083 struct intel_engine_cs *ring;
2a5913a8 5084 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5085 int i;
5086
5087 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5088
ae48434c
ID		 5089 valleyview_check_pctx(dev_priv);
5090
0a073b84 5091 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5092 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5093 gtfifodbg);
0a073b84
JB		 5094 I915_WRITE(GTFIFODBG, gtfifodbg);
5095 }
5096
c8d9a590 5097 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5098 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5099
160614a2
VS		 5100 /* Disable RC states. */
5101 I915_WRITE(GEN6_RC_CONTROL, 0);
5102
cad725fe 5103 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5104 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5105 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5106 I915_WRITE(GEN6_RP_UP_EI, 66000);
5107 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5108
5109 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5110
5111 I915_WRITE(GEN6_RP_CONTROL,
5112 GEN6_RP_MEDIA_TURBO |
5113 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5114 GEN6_RP_MEDIA_IS_GFX |
5115 GEN6_RP_ENABLE |
5116 GEN6_RP_UP_BUSY_AVG |
5117 GEN6_RP_DOWN_IDLE_CONT);
5118
5119 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5120 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5121 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5122
5123 for_each_ring(ring, dev_priv, i)
5124 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5125
2f0aa304 5126 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5127
5128 /* allows RC6 residency counter to work */
49798eb2 5129 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5130 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5131 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5132 VLV_MEDIA_RC6_COUNT_EN |
5133 VLV_RENDER_RC6_COUNT_EN));
31685c25 5134
a2b23fe0 5135 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5136 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5137
5138 intel_print_rc6_info(dev, rc6_mode);
5139
a2b23fe0 5140 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5141
64936258 5142 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5143
8d40c3ae
VS		 5144 /* RPS code assumes GPLL is used */
5145 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5146
c8e9627d 5147 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5148 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5149
b39fb297 5150 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5151 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5152 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5153 dev_priv->rps.cur_freq);
0a073b84 5154
73008b98 5155 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5156 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5157 dev_priv->rps.efficient_freq);
0a073b84 5158
b39fb297 5159 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5160
59bad947 5161 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5162}
5163
dde18883
ED		 5164static unsigned long intel_pxfreq(u32 vidfreq)
5165{
5166 unsigned long freq;
5167 int div = (vidfreq & 0x3f0000) >> 16;
5168 int post = (vidfreq & 0x3000) >> 12;
5169 int pre = (vidfreq & 0x7);
5170
5171 if (!pre)
5172 return 0;
5173
5174 freq = ((div * 133333) / ((1<<post) * pre));
5175
5176 return freq;
5177}
5178
eb48eb00
DV		 5179static const struct cparams {
5180 u16 i;
5181 u16 t;
5182 u16 m;
5183 u16 c;
5184} cparams[] = {
5185 { 1, 1333, 301, 28664 },
5186 { 1, 1066, 294, 24460 },
5187 { 1, 800, 294, 25192 },
5188 { 0, 1333, 276, 27605 },
5189 { 0, 1066, 276, 27605 },
5190 { 0, 800, 231, 23784 },
5191};
5192
f531dcb2 5193static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5194{
5195 u64 total_count, diff, ret;
5196 u32 count1, count2, count3, m = 0, c = 0;
5197 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5198 int i;
5199
02d71956
DV		 5200 assert_spin_locked(&mchdev_lock);
5201
20e4d407 5202 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5203
5204 /* Prevent division-by-zero if we are asking too fast.
5205 * Also, we don't get interesting results if we are polling
5206 * faster than once in 10ms, so just return the saved value
5207 * in such cases.
5208 */
5209 if (diff1 <= 10)
20e4d407 5210 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5211
5212 count1 = I915_READ(DMIEC);
5213 count2 = I915_READ(DDREC);
5214 count3 = I915_READ(CSIEC);
5215
5216 total_count = count1 + count2 + count3;
5217
5218 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5219 if (total_count < dev_priv->ips.last_count1) {
5220 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5221 diff += total_count;
5222 } else {
20e4d407 5223 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5224 }
5225
5226 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5227 if (cparams[i].i == dev_priv->ips.c_m &&
5228 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5229 m = cparams[i].m;
5230 c = cparams[i].c;
5231 break;
5232 }
5233 }
5234
5235 diff = div_u64(diff, diff1);
5236 ret = ((m * diff) + c);
5237 ret = div_u64(ret, 10);
5238
20e4d407
DV		 5239 dev_priv->ips.last_count1 = total_count;
5240 dev_priv->ips.last_time1 = now;
eb48eb00 5241
20e4d407 5242 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5243
5244 return ret;
5245}
5246
f531dcb2
CW		 5247unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5248{
3d13ef2e 5249 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5250 unsigned long val;
5251
3d13ef2e 5252 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5253 return 0;
5254
5255 spin_lock_irq(&mchdev_lock);
5256
5257 val = __i915_chipset_val(dev_priv);
5258
5259 spin_unlock_irq(&mchdev_lock);
5260
5261 return val;
5262}
5263
eb48eb00
DV		 5264unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5265{
5266 unsigned long m, x, b;
5267 u32 tsfs;
5268
5269 tsfs = I915_READ(TSFS);
5270
5271 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5272 x = I915_READ8(TR1);
5273
5274 b = tsfs & TSFS_INTR_MASK;
5275
5276 return ((m * x) / 127) - b;
5277}
5278
d972d6ee
MK		 5279static int _pxvid_to_vd(u8 pxvid)
5280{
5281 if (pxvid == 0)
5282 return 0;
5283
5284 if (pxvid >= 8 && pxvid < 31)
5285 pxvid = 31;
5286
5287 return (pxvid + 2) * 125;
5288}
5289
5290static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5291{
3d13ef2e 5292 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5293 const int vd = _pxvid_to_vd(pxvid);
5294 const int vm = vd - 1125;
5295
3d13ef2e 5296 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5297 return vm > 0 ? vm : 0;
5298
5299 return vd;
eb48eb00
DV		 5300}
5301
02d71956 5302static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5303{
5ed0bdf2 5304 u64 now, diff, diffms;
eb48eb00
DV		 5305 u32 count;
5306
02d71956 5307 assert_spin_locked(&mchdev_lock);
eb48eb00 5308
5ed0bdf2
TG		 5309 now = ktime_get_raw_ns();
5310 diffms = now - dev_priv->ips.last_time2;
5311 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5312
5313 /* Don't divide by 0 */
eb48eb00
DV		 5314 if (!diffms)
5315 return;
5316
5317 count = I915_READ(GFXEC);
5318
20e4d407
DV		 5319 if (count < dev_priv->ips.last_count2) {
5320 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5321 diff += count;
5322 } else {
20e4d407 5323 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5324 }
5325
20e4d407
DV		 5326 dev_priv->ips.last_count2 = count;
5327 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5328
5329 /* More magic constants... */
5330 diff = diff * 1181;
5331 diff = div_u64(diff, diffms * 10);
20e4d407 5332 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5333}
5334
02d71956
DV		 5335void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5336{
3d13ef2e
DL		 5337 struct drm_device *dev = dev_priv->dev;
5338
5339 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5340 return;
5341
9270388e 5342 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5343
5344 __i915_update_gfx_val(dev_priv);
5345
9270388e 5346 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5347}
5348
f531dcb2 5349static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5350{
5351 unsigned long t, corr, state1, corr2, state2;
5352 u32 pxvid, ext_v;
5353
02d71956
DV		 5354 assert_spin_locked(&mchdev_lock);
5355
b39fb297 5356 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5357 pxvid = (pxvid >> 24) & 0x7f;
5358 ext_v = pvid_to_extvid(dev_priv, pxvid);
5359
5360 state1 = ext_v;
5361
5362 t = i915_mch_val(dev_priv);
5363
5364 /* Revel in the empirically derived constants */
5365
5366 /* Correction factor in 1/100000 units */
5367 if (t > 80)
5368 corr = ((t * 2349) + 135940);
5369 else if (t >= 50)
5370 corr = ((t * 964) + 29317);
5371 else /* < 50 */
5372 corr = ((t * 301) + 1004);
5373
5374 corr = corr * ((150142 * state1) / 10000 - 78642);
5375 corr /= 100000;
20e4d407 5376 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5377
5378 state2 = (corr2 * state1) / 10000;
5379 state2 /= 100; /* convert to mW */
5380
02d71956 5381 __i915_update_gfx_val(dev_priv);
eb48eb00 5382
20e4d407 5383 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5384}
5385
f531dcb2
CW		 5386unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5387{
3d13ef2e 5388 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5389 unsigned long val;
5390
3d13ef2e 5391 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5392 return 0;
5393
5394 spin_lock_irq(&mchdev_lock);
5395
5396 val = __i915_gfx_val(dev_priv);
5397
5398 spin_unlock_irq(&mchdev_lock);
5399
5400 return val;
5401}
5402
eb48eb00
DV		 5403/**
5404 * i915_read_mch_val - return value for IPS use
5405 *
5406 * Calculate and return a value for the IPS driver to use when deciding whether
5407 * we have thermal and power headroom to increase CPU or GPU power budget.
5408 */
5409unsigned long i915_read_mch_val(void)
5410{
5411 struct drm_i915_private *dev_priv;
5412 unsigned long chipset_val, graphics_val, ret = 0;
5413
9270388e 5414 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5415 if (!i915_mch_dev)
5416 goto out_unlock;
5417 dev_priv = i915_mch_dev;
5418
f531dcb2
CW		 5419 chipset_val = __i915_chipset_val(dev_priv);
5420 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5421
5422 ret = chipset_val + graphics_val;
5423
5424out_unlock:
9270388e 5425 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5426
5427 return ret;
5428}
5429EXPORT_SYMBOL_GPL(i915_read_mch_val);
5430
5431/**
5432 * i915_gpu_raise - raise GPU frequency limit
5433 *
5434 * Raise the limit; IPS indicates we have thermal headroom.
5435 */
5436bool i915_gpu_raise(void)
5437{
5438 struct drm_i915_private *dev_priv;
5439 bool ret = true;
5440
9270388e 5441 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5442 if (!i915_mch_dev) {
5443 ret = false;
5444 goto out_unlock;
5445 }
5446 dev_priv = i915_mch_dev;
5447
20e4d407
DV		 5448 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5449 dev_priv->ips.max_delay--;
eb48eb00
DV		 5450
5451out_unlock:
9270388e 5452 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5453
5454 return ret;
5455}
5456EXPORT_SYMBOL_GPL(i915_gpu_raise);
5457
5458/**
5459 * i915_gpu_lower - lower GPU frequency limit
5460 *
5461 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5462 * frequency maximum.
5463 */
5464bool i915_gpu_lower(void)
5465{
5466 struct drm_i915_private *dev_priv;
5467 bool ret = true;
5468
9270388e 5469 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5470 if (!i915_mch_dev) {
5471 ret = false;
5472 goto out_unlock;
5473 }
5474 dev_priv = i915_mch_dev;
5475
20e4d407
DV		 5476 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5477 dev_priv->ips.max_delay++;
eb48eb00
DV		 5478
5479out_unlock:
9270388e 5480 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5481
5482 return ret;
5483}
5484EXPORT_SYMBOL_GPL(i915_gpu_lower);
5485
5486/**
5487 * i915_gpu_busy - indicate GPU business to IPS
5488 *
5489 * Tell the IPS driver whether or not the GPU is busy.
5490 */
5491bool i915_gpu_busy(void)
5492{
5493 struct drm_i915_private *dev_priv;
a4872ba6 5494 struct intel_engine_cs *ring;
eb48eb00 5495 bool ret = false;
f047e395 5496 int i;
eb48eb00 5497
9270388e 5498 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5499 if (!i915_mch_dev)
5500 goto out_unlock;
5501 dev_priv = i915_mch_dev;
5502
f047e395
CW		 5503 for_each_ring(ring, dev_priv, i)
5504 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5505
5506out_unlock:
9270388e 5507 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5508
5509 return ret;
5510}
5511EXPORT_SYMBOL_GPL(i915_gpu_busy);
5512
5513/**
5514 * i915_gpu_turbo_disable - disable graphics turbo
5515 *
5516 * Disable graphics turbo by resetting the max frequency and setting the
5517 * current frequency to the default.
5518 */
5519bool i915_gpu_turbo_disable(void)
5520{
5521 struct drm_i915_private *dev_priv;
5522 bool ret = true;
5523
9270388e 5524 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5525 if (!i915_mch_dev) {
5526 ret = false;
5527 goto out_unlock;
5528 }
5529 dev_priv = i915_mch_dev;
5530
20e4d407 5531 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5532
20e4d407 5533 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5534 ret = false;
5535
5536out_unlock:
9270388e 5537 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5538
5539 return ret;
5540}
5541EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5542
5543/**
5544 * Tells the intel_ips driver that the i915 driver is now loaded, if
5545 * IPS got loaded first.
5546 *
5547 * This awkward dance is so that neither module has to depend on the
5548 * other in order for IPS to do the appropriate communication of
5549 * GPU turbo limits to i915.
5550 */
5551static void
5552ips_ping_for_i915_load(void)
5553{
5554 void (*link)(void);
5555
5556 link = symbol_get(ips_link_to_i915_driver);
5557 if (link) {
5558 link();
5559 symbol_put(ips_link_to_i915_driver);
5560 }
5561}
5562
5563void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5564{
02d71956
DV		 5565 /* We only register the i915 ips part with intel-ips once everything is
5566 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5567 spin_lock_irq(&mchdev_lock);
eb48eb00 5568 i915_mch_dev = dev_priv;
9270388e 5569 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5570
5571 ips_ping_for_i915_load();
5572}
5573
5574void intel_gpu_ips_teardown(void)
5575{
9270388e 5576 spin_lock_irq(&mchdev_lock);
eb48eb00 5577 i915_mch_dev = NULL;
9270388e 5578 spin_unlock_irq(&mchdev_lock);
eb48eb00 5579}
76c3552f 5580
8090c6b9 5581static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5582{
5583 struct drm_i915_private *dev_priv = dev->dev_private;
5584 u32 lcfuse;
5585 u8 pxw[16];
5586 int i;
5587
5588 /* Disable to program */
5589 I915_WRITE(ECR, 0);
5590 POSTING_READ(ECR);
5591
5592 /* Program energy weights for various events */
5593 I915_WRITE(SDEW, 0x15040d00);
5594 I915_WRITE(CSIEW0, 0x007f0000);
5595 I915_WRITE(CSIEW1, 0x1e220004);
5596 I915_WRITE(CSIEW2, 0x04000004);
5597
5598 for (i = 0; i < 5; i++)
5599 I915_WRITE(PEW + (i * 4), 0);
5600 for (i = 0; i < 3; i++)
5601 I915_WRITE(DEW + (i * 4), 0);
5602
5603 /* Program P-state weights to account for frequency power adjustment */
5604 for (i = 0; i < 16; i++) {
5605 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5606 unsigned long freq = intel_pxfreq(pxvidfreq);
5607 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5608 PXVFREQ_PX_SHIFT;
5609 unsigned long val;
5610
5611 val = vid * vid;
5612 val *= (freq / 1000);
5613 val *= 255;
5614 val /= (127*127*900);
5615 if (val > 0xff)
5616 DRM_ERROR("bad pxval: %ld\n", val);
5617 pxw[i] = val;
5618 }
5619 /* Render standby states get 0 weight */
5620 pxw[14] = 0;
5621 pxw[15] = 0;
5622
5623 for (i = 0; i < 4; i++) {
5624 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5625 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5626 I915_WRITE(PXW + (i * 4), val);
5627 }
5628
5629 /* Adjust magic regs to magic values (more experimental results) */
5630 I915_WRITE(OGW0, 0);
5631 I915_WRITE(OGW1, 0);
5632 I915_WRITE(EG0, 0x00007f00);
5633 I915_WRITE(EG1, 0x0000000e);
5634 I915_WRITE(EG2, 0x000e0000);
5635 I915_WRITE(EG3, 0x68000300);
5636 I915_WRITE(EG4, 0x42000000);
5637 I915_WRITE(EG5, 0x00140031);
5638 I915_WRITE(EG6, 0);
5639 I915_WRITE(EG7, 0);
5640
5641 for (i = 0; i < 8; i++)
5642 I915_WRITE(PXWL + (i * 4), 0);
5643
5644 /* Enable PMON + select events */
5645 I915_WRITE(ECR, 0x80000019);
5646
5647 lcfuse = I915_READ(LCFUSE02);
5648
20e4d407 5649 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5650}
5651
ae48434c
ID		 5652void intel_init_gt_powersave(struct drm_device *dev)
5653{
e6069ca8
ID		 5654 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5655
38807746
D		 5656 if (IS_CHERRYVIEW(dev))
5657 cherryview_init_gt_powersave(dev);
5658 else if (IS_VALLEYVIEW(dev))
4e80519e 5659 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5660}
5661
5662void intel_cleanup_gt_powersave(struct drm_device *dev)
5663{
38807746
D		 5664 if (IS_CHERRYVIEW(dev))
5665 return;
5666 else if (IS_VALLEYVIEW(dev))
4e80519e 5667 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5668}
5669
dbea3cea
ID		 5670static void gen6_suspend_rps(struct drm_device *dev)
5671{
5672 struct drm_i915_private *dev_priv = dev->dev_private;
5673
5674 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5675
4c2a8897 5676 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 5677}
5678
156c7ca0
JB		 5679/**
5680 * intel_suspend_gt_powersave - suspend PM work and helper threads
5681 * @dev: drm device
5682 *
5683 * We don't want to disable RC6 or other features here, we just want
5684 * to make sure any work we've queued has finished and won't bother
5685 * us while we're suspended.
5686 */
5687void intel_suspend_gt_powersave(struct drm_device *dev)
5688{
5689 struct drm_i915_private *dev_priv = dev->dev_private;
5690
d4d70aa5
ID		 5691 if (INTEL_INFO(dev)->gen < 6)
5692 return;
5693
dbea3cea 5694 gen6_suspend_rps(dev);
b47adc17
D		 5695
5696 /* Force GPU to min freq during suspend */
5697 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5698}
5699
8090c6b9
DV		 5700void intel_disable_gt_powersave(struct drm_device *dev)
5701{
1a01ab3b
JB		 5702 struct drm_i915_private *dev_priv = dev->dev_private;
5703
930ebb46 5704 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5705 ironlake_disable_drps(dev);
38807746 5706 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5707 intel_suspend_gt_powersave(dev);
e494837a 5708
4fc688ce 5709 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5710 if (INTEL_INFO(dev)->gen >= 9)
5711 gen9_disable_rps(dev);
5712 else if (IS_CHERRYVIEW(dev))
38807746
D		 5713 cherryview_disable_rps(dev);
5714 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5715 valleyview_disable_rps(dev);
5716 else
5717 gen6_disable_rps(dev);
e534770a 5718
c0951f0c 5719 dev_priv->rps.enabled = false;
4fc688ce 5720 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5721 }
8090c6b9
DV		 5722}
5723
1a01ab3b
JB		 5724static void intel_gen6_powersave_work(struct work_struct *work)
5725{
5726 struct drm_i915_private *dev_priv =
5727 container_of(work, struct drm_i915_private,
5728 rps.delayed_resume_work.work);
5729 struct drm_device *dev = dev_priv->dev;
5730
4fc688ce 5731 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5732
4c2a8897 5733 gen6_reset_rps_interrupts(dev);
3cc134e3 5734
38807746
D		 5735 if (IS_CHERRYVIEW(dev)) {
5736 cherryview_enable_rps(dev);
5737 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5738 valleyview_enable_rps(dev);
20e49366 5739 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5740 gen9_enable_rc6(dev);
20e49366 5741 gen9_enable_rps(dev);
b6fef0ef 5742 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5743 } else if (IS_BROADWELL(dev)) {
5744 gen8_enable_rps(dev);
c2bc2fc5 5745 __gen6_update_ring_freq(dev);
0a073b84
JB		 5746 } else {
5747 gen6_enable_rps(dev);
c2bc2fc5 5748 __gen6_update_ring_freq(dev);
0a073b84 5749 }
aed242ff
CW		 5750
5751 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5752 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5753
5754 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5755 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5756
c0951f0c 5757 dev_priv->rps.enabled = true;
3cc134e3 5758
4c2a8897 5759 gen6_enable_rps_interrupts(dev);
3cc134e3 5760
4fc688ce 5761 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5762
5763 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5764}
5765
8090c6b9
DV		 5766void intel_enable_gt_powersave(struct drm_device *dev)
5767{
1a01ab3b
JB		 5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769
f61018b1
YZ		 5770 /* Powersaving is controlled by the host when inside a VM */
5771 if (intel_vgpu_active(dev))
5772 return;
5773
8090c6b9 5774 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5775 mutex_lock(&dev->struct_mutex);
8090c6b9 5776 ironlake_enable_drps(dev);
8090c6b9 5777 intel_init_emon(dev);
dc1d0136 5778 mutex_unlock(&dev->struct_mutex);
38807746 5779 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5780 /*
5781 * PCU communication is slow and this doesn't need to be
5782 * done at any specific time, so do this out of our fast path
5783 * to make resume and init faster.
c6df39b5
ID		 5784 *
5785 * We depend on the HW RC6 power context save/restore
5786 * mechanism when entering D3 through runtime PM suspend. So
5787 * disable RPM until RPS/RC6 is properly setup. We can only
5788 * get here via the driver load/system resume/runtime resume
5789 * paths, so the _noresume version is enough (and in case of
5790 * runtime resume it's necessary).
1a01ab3b 5791 */
c6df39b5
ID		 5792 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5793 round_jiffies_up_relative(HZ)))
5794 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5795 }
5796}
5797
c6df39b5
ID		 5798void intel_reset_gt_powersave(struct drm_device *dev)
5799{
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801
dbea3cea
ID		 5802 if (INTEL_INFO(dev)->gen < 6)
5803 return;
5804
5805 gen6_suspend_rps(dev);
c6df39b5 5806 dev_priv->rps.enabled = false;
c6df39b5
ID		 5807}
5808
3107bd48
DV		 5809static void ibx_init_clock_gating(struct drm_device *dev)
5810{
5811 struct drm_i915_private *dev_priv = dev->dev_private;
5812
5813 /*
5814 * On Ibex Peak and Cougar Point, we need to disable clock
5815 * gating for the panel power sequencer or it will fail to
5816 * start up when no ports are active.
5817 */
5818 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5819}
5820
0e088b8f
VS		 5821static void g4x_disable_trickle_feed(struct drm_device *dev)
5822{
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 int pipe;
5825
055e393f 5826 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5827 I915_WRITE(DSPCNTR(pipe),
5828 I915_READ(DSPCNTR(pipe)) |
5829 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5830 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5831 }
5832}
5833
017636cc
VS		 5834static void ilk_init_lp_watermarks(struct drm_device *dev)
5835{
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837
5838 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5839 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5840 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5841
5842 /*
5843 * Don't touch WM1S_LP_EN here.
5844 * Doing so could cause underruns.
5845 */
5846}
5847
1fa61106 5848static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5849{
5850 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5851 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5852
f1e8fa56
DL		 5853 /*
5854 * Required for FBC
5855 * WaFbcDisableDpfcClockGating:ilk
5856 */
4d47e4f5
DL		 5857 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5858 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5859 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5860
5861 I915_WRITE(PCH_3DCGDIS0,
5862 MARIUNIT_CLOCK_GATE_DISABLE |
5863 SVSMUNIT_CLOCK_GATE_DISABLE);
5864 I915_WRITE(PCH_3DCGDIS1,
5865 VFMUNIT_CLOCK_GATE_DISABLE);
5866
6f1d69b0
ED		 5867 /*
5868 * According to the spec the following bits should be set in
5869 * order to enable memory self-refresh
5870 * The bit 22/21 of 0x42004
5871 * The bit 5 of 0x42020
5872 * The bit 15 of 0x45000
5873 */
5874 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5875 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5876 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5877 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5878 I915_WRITE(DISP_ARB_CTL,
5879 (I915_READ(DISP_ARB_CTL) |
5880 DISP_FBC_WM_DIS));
017636cc
VS		 5881
5882 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5883
5884 /*
5885 * Based on the document from hardware guys the following bits
5886 * should be set unconditionally in order to enable FBC.
5887 * The bit 22 of 0x42000
5888 * The bit 22 of 0x42004
5889 * The bit 7,8,9 of 0x42020.
5890 */
5891 if (IS_IRONLAKE_M(dev)) {
4bb35334 5892 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5893 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5894 I915_READ(ILK_DISPLAY_CHICKEN1) |
5895 ILK_FBCQ_DIS);
5896 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5897 I915_READ(ILK_DISPLAY_CHICKEN2) |
5898 ILK_DPARB_GATE);
6f1d69b0
ED		 5899 }
5900
4d47e4f5
DL		 5901 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5902
6f1d69b0
ED		 5903 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5904 I915_READ(ILK_DISPLAY_CHICKEN2) |
5905 ILK_ELPIN_409_SELECT);
5906 I915_WRITE(_3D_CHICKEN2,
5907 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5908 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5909
ecdb4eb7 5910 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5911 I915_WRITE(CACHE_MODE_0,
5912 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5913
4e04632e
AG		 5914 /* WaDisable_RenderCache_OperationalFlush:ilk */
5915 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5916
0e088b8f 5917 g4x_disable_trickle_feed(dev);
bdad2b2f 5918
3107bd48
DV		 5919 ibx_init_clock_gating(dev);
5920}
5921
5922static void cpt_init_clock_gating(struct drm_device *dev)
5923{
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 int pipe;
3f704fa2 5926 uint32_t val;
3107bd48
DV		 5927
5928 /*
5929 * On Ibex Peak and Cougar Point, we need to disable clock
5930 * gating for the panel power sequencer or it will fail to
5931 * start up when no ports are active.
5932 */
cd664078
JB		 5933 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5934 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5935 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5936 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5937 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5938 /* The below fixes the weird display corruption, a few pixels shifted
5939 * downward, on (only) LVDS of some HP laptops with IVY.
5940 */
055e393f 5941 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5942 val = I915_READ(TRANS_CHICKEN2(pipe));
5943 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5944 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5945 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5946 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5947 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5948 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5949 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5950 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5951 }
3107bd48 5952 /* WADP0ClockGatingDisable */
055e393f 5953 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5954 I915_WRITE(TRANS_CHICKEN1(pipe),
5955 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5956 }
6f1d69b0
ED		 5957}
5958
1d7aaa0c
DV		 5959static void gen6_check_mch_setup(struct drm_device *dev)
5960{
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962 uint32_t tmp;
5963
5964 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5965 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5966 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5967 tmp);
1d7aaa0c
DV		 5968}
5969
1fa61106 5970static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5971{
5972 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5973 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5974
231e54f6 5975 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5976
5977 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5978 I915_READ(ILK_DISPLAY_CHICKEN2) |
5979 ILK_ELPIN_409_SELECT);
5980
ecdb4eb7 5981 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5982 I915_WRITE(_3D_CHICKEN,
5983 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5984
4e04632e
AG		 5985 /* WaDisable_RenderCache_OperationalFlush:snb */
5986 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5987
8d85d272
VS		 5988 /*
5989 * BSpec recoomends 8x4 when MSAA is used,
5990 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5991 *
5992 * Note that PS/WM thread counts depend on the WIZ hashing
5993 * disable bit, which we don't touch here, but it's good
5994 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5995 */
5996 I915_WRITE(GEN6_GT_MODE,
98533251 5997 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5998
017636cc 5999 ilk_init_lp_watermarks(dev);
6f1d69b0 6000
6f1d69b0 6001 I915_WRITE(CACHE_MODE_0,
50743298 6002 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6003
6004 I915_WRITE(GEN6_UCGCTL1,
6005 I915_READ(GEN6_UCGCTL1) |
6006 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6007 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6008
6009 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6010 * gating disable must be set. Failure to set it results in
6011 * flickering pixels due to Z write ordering failures after
6012 * some amount of runtime in the Mesa "fire" demo, and Unigine
6013 * Sanctuary and Tropics, and apparently anything else with
6014 * alpha test or pixel discard.
6015 *
6016 * According to the spec, bit 11 (RCCUNIT) must also be set,
6017 * but we didn't debug actual testcases to find it out.
0f846f81 6018 *
ef59318c
VS		 6019 * WaDisableRCCUnitClockGating:snb
6020 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6021 */
6022 I915_WRITE(GEN6_UCGCTL2,
6023 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6024 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6025
5eb146dd 6026 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6027 I915_WRITE(_3D_CHICKEN3,
6028 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6029
e927ecde
VS		 6030 /*
6031 * Bspec says:
6032 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6033 * 3DSTATE_SF number of SF output attributes is more than 16."
6034 */
6035 I915_WRITE(_3D_CHICKEN3,
6036 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6037
6f1d69b0
ED		 6038 /*
6039 * According to the spec the following bits should be
6040 * set in order to enable memory self-refresh and fbc:
6041 * The bit21 and bit22 of 0x42000
6042 * The bit21 and bit22 of 0x42004
6043 * The bit5 and bit7 of 0x42020
6044 * The bit14 of 0x70180
6045 * The bit14 of 0x71180
4bb35334
DL		 6046 *
6047 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6048 */
6049 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6050 I915_READ(ILK_DISPLAY_CHICKEN1) |
6051 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6052 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6053 I915_READ(ILK_DISPLAY_CHICKEN2) |
6054 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6055 I915_WRITE(ILK_DSPCLK_GATE_D,
6056 I915_READ(ILK_DSPCLK_GATE_D) |
6057 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6058 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6059
0e088b8f 6060 g4x_disable_trickle_feed(dev);
f8f2ac9a 6061
3107bd48 6062 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6063
6064 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6065}
6066
6067static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6068{
6069 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6070
3aad9059 6071 /*
46680e0a 6072 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6073 *
6074 * This actually overrides the dispatch
6075 * mode for all thread types.
6076 */
6f1d69b0
ED		 6077 reg &= ~GEN7_FF_SCHED_MASK;
6078 reg |= GEN7_FF_TS_SCHED_HW;
6079 reg |= GEN7_FF_VS_SCHED_HW;
6080 reg |= GEN7_FF_DS_SCHED_HW;
6081
6082 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6083}
6084
17a303ec
PZ		 6085static void lpt_init_clock_gating(struct drm_device *dev)
6086{
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088
6089 /*
6090 * TODO: this bit should only be enabled when really needed, then
6091 * disabled when not needed anymore in order to save power.
6092 */
6093 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6094 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6095 I915_READ(SOUTH_DSPCLK_GATE_D) |
6096 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6097
6098 /* WADPOClockGatingDisable:hsw */
6099 I915_WRITE(_TRANSA_CHICKEN1,
6100 I915_READ(_TRANSA_CHICKEN1) |
6101 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6102}
6103
7d708ee4
ID		 6104static void lpt_suspend_hw(struct drm_device *dev)
6105{
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6109 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6110
6111 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6112 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6113 }
6114}
6115
47c2bd97 6116static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6117{
6118 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6119 enum pipe pipe;
1020a5c2
BW		 6120
6121 I915_WRITE(WM3_LP_ILK, 0);
6122 I915_WRITE(WM2_LP_ILK, 0);
6123 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6124
ab57fff1 6125 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6126 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6127
ab57fff1 6128 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6129 I915_WRITE(CHICKEN_PAR1_1,
6130 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6131
ab57fff1 6132 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6133 for_each_pipe(dev_priv, pipe) {
07d27e20 6134 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6135 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6136 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6137 }
63801f21 6138
ab57fff1
BW		 6139 /* WaVSRefCountFullforceMissDisable:bdw */
6140 /* WaDSRefCountFullforceMissDisable:bdw */
6141 I915_WRITE(GEN7_FF_THREAD_MODE,
6142 I915_READ(GEN7_FF_THREAD_MODE) &
6143 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6144
295e8bb7
VS		 6145 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6146 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6147
6148 /* WaDisableSDEUnitClockGating:bdw */
6149 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6150 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6151
89d6b2b8 6152 lpt_init_clock_gating(dev);
1020a5c2
BW		 6153}
6154
cad2a2d7
ED		 6155static void haswell_init_clock_gating(struct drm_device *dev)
6156{
6157 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6158
017636cc 6159 ilk_init_lp_watermarks(dev);
cad2a2d7 6160
f3fc4884
FJ		 6161 /* L3 caching of data atomics doesn't work -- disable it. */
6162 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6163 I915_WRITE(HSW_ROW_CHICKEN3,
6164 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6165
ecdb4eb7 6166 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6167 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6168 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6169 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6170
e36ea7ff
VS		 6171 /* WaVSRefCountFullforceMissDisable:hsw */
6172 I915_WRITE(GEN7_FF_THREAD_MODE,
6173 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6174
4e04632e
AG		 6175 /* WaDisable_RenderCache_OperationalFlush:hsw */
6176 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6177
fe27c606
CW		 6178 /* enable HiZ Raw Stall Optimization */
6179 I915_WRITE(CACHE_MODE_0_GEN7,
6180 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6181
ecdb4eb7 6182 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6183 I915_WRITE(CACHE_MODE_1,
6184 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6185
a12c4967
VS		 6186 /*
6187 * BSpec recommends 8x4 when MSAA is used,
6188 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6189 *
6190 * Note that PS/WM thread counts depend on the WIZ hashing
6191 * disable bit, which we don't touch here, but it's good
6192 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6193 */
6194 I915_WRITE(GEN7_GT_MODE,
98533251 6195 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6196
94411593
KG		 6197 /* WaSampleCChickenBitEnable:hsw */
6198 I915_WRITE(HALF_SLICE_CHICKEN3,
6199 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6200
ecdb4eb7 6201 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6202 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6203
90a88643
PZ		 6204 /* WaRsPkgCStateDisplayPMReq:hsw */
6205 I915_WRITE(CHICKEN_PAR1_1,
6206 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6207
17a303ec 6208 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6209}
6210
1fa61106 6211static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6212{
6213 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6214 uint32_t snpcr;
6f1d69b0 6215
017636cc 6216 ilk_init_lp_watermarks(dev);
6f1d69b0 6217
231e54f6 6218 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6219
ecdb4eb7 6220 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6221 I915_WRITE(_3D_CHICKEN3,
6222 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6223
ecdb4eb7 6224 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6225 I915_WRITE(IVB_CHICKEN3,
6226 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6227 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6228
ecdb4eb7 6229 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6230 if (IS_IVB_GT1(dev))
6231 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6232 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6233
4e04632e
AG		 6234 /* WaDisable_RenderCache_OperationalFlush:ivb */
6235 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6236
ecdb4eb7 6237 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6238 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6239 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6240
ecdb4eb7 6241 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6242 I915_WRITE(GEN7_L3CNTLREG1,
6243 GEN7_WA_FOR_GEN7_L3_CONTROL);
6244 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6245 GEN7_WA_L3_CHICKEN_MODE);
6246 if (IS_IVB_GT1(dev))
6247 I915_WRITE(GEN7_ROW_CHICKEN2,
6248 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6249 else {
6250 /* must write both registers */
6251 I915_WRITE(GEN7_ROW_CHICKEN2,
6252 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6253 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6254 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6255 }
6f1d69b0 6256
ecdb4eb7 6257 /* WaForceL3Serialization:ivb */
61939d97
JB		 6258 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6259 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6260
1b80a19a 6261 /*
0f846f81 6262 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6263 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6264 */
6265 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6266 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6267
ecdb4eb7 6268 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6269 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6270 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6271 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6272
0e088b8f 6273 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6274
6275 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6276
22721343
CW		 6277 if (0) { /* causes HiZ corruption on ivb:gt1 */
6278 /* enable HiZ Raw Stall Optimization */
6279 I915_WRITE(CACHE_MODE_0_GEN7,
6280 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6281 }
116f2b6d 6282
ecdb4eb7 6283 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6284 I915_WRITE(CACHE_MODE_1,
6285 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6286
a607c1a4
VS		 6287 /*
6288 * BSpec recommends 8x4 when MSAA is used,
6289 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6290 *
6291 * Note that PS/WM thread counts depend on the WIZ hashing
6292 * disable bit, which we don't touch here, but it's good
6293 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6294 */
6295 I915_WRITE(GEN7_GT_MODE,
98533251 6296 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6297
20848223
BW		 6298 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6299 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6300 snpcr |= GEN6_MBC_SNPCR_MED;
6301 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6302
ab5c608b
BW		 6303 if (!HAS_PCH_NOP(dev))
6304 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6305
6306 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6307}
6308
c6beb13e
VS		 6309static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6310{
6311 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6312
6313 /*
6314 * Disable trickle feed and enable pnd deadline calculation
6315 */
6316 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6317 I915_WRITE(CBR1_VLV, 0);
6318}
6319
1fa61106 6320static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6321{
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6323
c6beb13e 6324 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6325
ecdb4eb7 6326 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6327 I915_WRITE(_3D_CHICKEN3,
6328 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6329
ecdb4eb7 6330 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6331 I915_WRITE(IVB_CHICKEN3,
6332 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6333 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6334
fad7d36e 6335 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6336 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6337 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6338 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6339 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6340
4e04632e
AG		 6341 /* WaDisable_RenderCache_OperationalFlush:vlv */
6342 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6343
ecdb4eb7 6344 /* WaForceL3Serialization:vlv */
61939d97
JB		 6345 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6346 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6347
ecdb4eb7 6348 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6349 I915_WRITE(GEN7_ROW_CHICKEN2,
6350 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6351
ecdb4eb7 6352 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6353 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6354 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6355 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6356
46680e0a
VS		 6357 gen7_setup_fixed_func_scheduler(dev_priv);
6358
3c0edaeb 6359 /*
0f846f81 6360 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6361 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6362 */
6363 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6364 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6365
c98f5062
AG		 6366 /* WaDisableL3Bank2xClockGate:vlv
6367 * Disabling L3 clock gating- MMIO 940c[25] = 1
6368 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6369 I915_WRITE(GEN7_UCGCTL4,
6370 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6371
afd58e79
VS		 6372 /*
6373 * BSpec says this must be set, even though
6374 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6375 */
6b26c86d
DV		 6376 I915_WRITE(CACHE_MODE_1,
6377 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6378
da2518f9
VS		 6379 /*
6380 * BSpec recommends 8x4 when MSAA is used,
6381 * however in practice 16x4 seems fastest.
6382 *
6383 * Note that PS/WM thread counts depend on the WIZ hashing
6384 * disable bit, which we don't touch here, but it's good
6385 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6386 */
6387 I915_WRITE(GEN7_GT_MODE,
6388 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6389
031994ee
VS		 6390 /*
6391 * WaIncreaseL3CreditsForVLVB0:vlv
6392 * This is the hardware default actually.
6393 */
6394 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6395
2d809570 6396 /*
ecdb4eb7 6397 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6398 * Disable clock gating on th GCFG unit to prevent a delay
6399 * in the reporting of vblank events.
6400 */
7a0d1eed 6401 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6402}
6403
a4565da8
VS		 6404static void cherryview_init_clock_gating(struct drm_device *dev)
6405{
6406 struct drm_i915_private *dev_priv = dev->dev_private;
6407
c6beb13e 6408 vlv_init_display_clock_gating(dev_priv);
dd811e70 6409
232ce337
VS		 6410 /* WaVSRefCountFullforceMissDisable:chv */
6411 /* WaDSRefCountFullforceMissDisable:chv */
6412 I915_WRITE(GEN7_FF_THREAD_MODE,
6413 I915_READ(GEN7_FF_THREAD_MODE) &
6414 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6415
6416 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6417 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6418 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6419
6420 /* WaDisableCSUnitClockGating:chv */
6421 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6422 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6423
6424 /* WaDisableSDEUnitClockGating:chv */
6425 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6426 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6427}
6428
1fa61106 6429static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6430{
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 uint32_t dspclk_gate;
6433
6434 I915_WRITE(RENCLK_GATE_D1, 0);
6435 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6436 GS_UNIT_CLOCK_GATE_DISABLE |
6437 CL_UNIT_CLOCK_GATE_DISABLE);
6438 I915_WRITE(RAMCLK_GATE_D, 0);
6439 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6440 OVRUNIT_CLOCK_GATE_DISABLE |
6441 OVCUNIT_CLOCK_GATE_DISABLE;
6442 if (IS_GM45(dev))
6443 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6444 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6445
6446 /* WaDisableRenderCachePipelinedFlush */
6447 I915_WRITE(CACHE_MODE_0,
6448 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6449
4e04632e
AG		 6450 /* WaDisable_RenderCache_OperationalFlush:g4x */
6451 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6452
0e088b8f 6453 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6454}
6455
1fa61106 6456static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6457{
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459
6460 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6461 I915_WRITE(RENCLK_GATE_D2, 0);
6462 I915_WRITE(DSPCLK_GATE_D, 0);
6463 I915_WRITE(RAMCLK_GATE_D, 0);
6464 I915_WRITE16(DEUC, 0);
20f94967
VS		 6465 I915_WRITE(MI_ARB_STATE,
6466 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6467
6468 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6469 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6470}
6471
1fa61106 6472static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6473{
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475
6476 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6477 I965_RCC_CLOCK_GATE_DISABLE |
6478 I965_RCPB_CLOCK_GATE_DISABLE |
6479 I965_ISC_CLOCK_GATE_DISABLE |
6480 I965_FBC_CLOCK_GATE_DISABLE);
6481 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6482 I915_WRITE(MI_ARB_STATE,
6483 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6484
6485 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6486 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6487}
6488
1fa61106 6489static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6490{
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 u32 dstate = I915_READ(D_STATE);
6493
6494 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6495 DSTATE_DOT_CLOCK_GATING;
6496 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6497
6498 if (IS_PINEVIEW(dev))
6499 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6500
6501 /* IIR "flip pending" means done if this bit is set */
6502 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6503
6504 /* interrupts should cause a wake up from C3 */
3299254f 6505 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6506
6507 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6508 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6509
6510 I915_WRITE(MI_ARB_STATE,
6511 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6512}
6513
1fa61106 6514static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517
6518 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6519
6520 /* interrupts should cause a wake up from C3 */
6521 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6522 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6523
6524 I915_WRITE(MEM_MODE,
6525 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6526}
6527
1fa61106 6528static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6529{
6530 struct drm_i915_private *dev_priv = dev->dev_private;
6531
6532 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6533
6534 I915_WRITE(MEM_MODE,
6535 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6536 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6537}
6538
6f1d69b0
ED		 6539void intel_init_clock_gating(struct drm_device *dev)
6540{
6541 struct drm_i915_private *dev_priv = dev->dev_private;
6542
c57e3551
DL		 6543 if (dev_priv->display.init_clock_gating)
6544 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6545}
6546
7d708ee4
ID		 6547void intel_suspend_hw(struct drm_device *dev)
6548{
6549 if (HAS_PCH_LPT(dev))
6550 lpt_suspend_hw(dev);
6551}
6552
1fa61106
ED		 6553/* Set up chip specific power management-related functions */
6554void intel_init_pm(struct drm_device *dev)
6555{
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557
7ff0ebcc 6558 intel_fbc_init(dev_priv);
1fa61106 6559
c921aba8
DV		 6560 /* For cxsr */
6561 if (IS_PINEVIEW(dev))
6562 i915_pineview_get_mem_freq(dev);
6563 else if (IS_GEN5(dev))
6564 i915_ironlake_get_mem_freq(dev);
6565
1fa61106 6566 /* For FIFO watermark updates */
f5ed50cb 6567 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6568 skl_setup_wm_latency(dev);
6569
45db2194 6570 dev_priv->display.init_clock_gating = skl_init_clock_gating;
2d41c0b5
PB		 6571 dev_priv->display.update_wm = skl_update_wm;
6572 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6573 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6574 ilk_setup_wm_latency(dev);
53615a5e 6575
bd602544
VS		 6576 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6577 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6578 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6579 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6580 dev_priv->display.update_wm = ilk_update_wm;
6581 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6582 } else {
6583 DRM_DEBUG_KMS("Failed to read display plane latency. "
6584 "Disable CxSR\n");
6585 }
6586
6587 if (IS_GEN5(dev))
1fa61106 6588 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6589 else if (IS_GEN6(dev))
1fa61106 6590 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6591 else if (IS_IVYBRIDGE(dev))
1fa61106 6592 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6593 else if (IS_HASWELL(dev))
cad2a2d7 6594 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6595 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6596 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6597 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6598 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6599 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6600 dev_priv->display.init_clock_gating =
6601 cherryview_init_clock_gating;
1fa61106
ED		 6602 } else if (IS_VALLEYVIEW(dev)) {
6603 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6604 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6605 dev_priv->display.init_clock_gating =
6606 valleyview_init_clock_gating;
1fa61106
ED		 6607 } else if (IS_PINEVIEW(dev)) {
6608 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6609 dev_priv->is_ddr3,
6610 dev_priv->fsb_freq,
6611 dev_priv->mem_freq)) {
6612 DRM_INFO("failed to find known CxSR latency "
6613 "(found ddr%s fsb freq %d, mem freq %d), "
6614 "disabling CxSR\n",
6615 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6616 dev_priv->fsb_freq, dev_priv->mem_freq);
6617 /* Disable CxSR and never update its watermark again */
5209b1f4 6618 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6619 dev_priv->display.update_wm = NULL;
6620 } else
6621 dev_priv->display.update_wm = pineview_update_wm;
6622 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6623 } else if (IS_G4X(dev)) {
6624 dev_priv->display.update_wm = g4x_update_wm;
6625 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6626 } else if (IS_GEN4(dev)) {
6627 dev_priv->display.update_wm = i965_update_wm;
6628 if (IS_CRESTLINE(dev))
6629 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6630 else if (IS_BROADWATER(dev))
6631 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6632 } else if (IS_GEN3(dev)) {
6633 dev_priv->display.update_wm = i9xx_update_wm;
6634 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6635 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6636 } else if (IS_GEN2(dev)) {
6637 if (INTEL_INFO(dev)->num_pipes == 1) {
6638 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6639 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6640 } else {
6641 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6642 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6643 }
6644
6645 if (IS_I85X(dev) || IS_I865G(dev))
6646 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6647 else
6648 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6649 } else {
6650 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6651 }
6652}
6653
151a49d0 6654int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6655{
4fc688ce 6656 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6657
6658 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6659 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6660 return -EAGAIN;
6661 }
6662
6663 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6664 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6665 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6666
6667 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6668 500)) {
6669 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6670 return -ETIMEDOUT;
6671 }
6672
6673 *val = I915_READ(GEN6_PCODE_DATA);
6674 I915_WRITE(GEN6_PCODE_DATA, 0);
6675
6676 return 0;
6677}
6678
151a49d0 6679int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6680{
4fc688ce 6681 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6682
6683 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6684 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6685 return -EAGAIN;
6686 }
6687
6688 I915_WRITE(GEN6_PCODE_DATA, val);
6689 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6690
6691 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6692 500)) {
6693 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6694 return -ETIMEDOUT;
6695 }
6696
6697 I915_WRITE(GEN6_PCODE_DATA, 0);
6698
6699 return 0;
6700}
a0e4e199 6701
dd06f88c 6702static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6703{
dd06f88c
VS		 6704 switch (czclk_freq) {
6705 case 200:
6706 return 10;
6707 case 267:
6708 return 12;
6709 case 320:
6710 case 333:
dd06f88c 6711 return 16;
ab3fb157
VS		 6712 case 400:
6713 return 20;
855ba3be
JB		 6714 default:
6715 return -1;
6716 }
dd06f88c 6717}
855ba3be 6718
dd06f88c
VS		 6719static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6720{
6721 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6722
6723 div = vlv_gpu_freq_div(czclk_freq);
6724 if (div < 0)
6725 return div;
6726
6727 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6728}
6729
b55dd647 6730static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6731{
dd06f88c 6732 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6733
dd06f88c
VS		 6734 mul = vlv_gpu_freq_div(czclk_freq);
6735 if (mul < 0)
6736 return mul;
855ba3be 6737
dd06f88c 6738 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6739}
6740
b55dd647 6741static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6742{
dd06f88c 6743 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6744
dd06f88c
VS		 6745 div = vlv_gpu_freq_div(czclk_freq) / 2;
6746 if (div < 0)
6747 return div;
22b1b2f8 6748
dd06f88c 6749 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6750}
6751
b55dd647 6752static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6753{
dd06f88c 6754 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6755
dd06f88c
VS		 6756 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6757 if (mul < 0)
6758 return mul;
22b1b2f8 6759
1c14762d 6760 /* CHV needs even values */
dd06f88c 6761 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6762}
6763
616bc820 6764int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6765{
80b6dda4
AG		 6766 if (IS_GEN9(dev_priv->dev))
6767 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6768 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6769 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6770 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6771 return byt_gpu_freq(dev_priv, val);
6772 else
6773 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6774}
6775
616bc820
VS		 6776int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6777{
80b6dda4
AG		 6778 if (IS_GEN9(dev_priv->dev))
6779 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6780 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6781 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6782 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6783 return byt_freq_opcode(dev_priv, val);
6784 else
6785 return val / GT_FREQUENCY_MULTIPLIER;
6786}
22b1b2f8 6787
6ad790c0
CW		 6788struct request_boost {
6789 struct work_struct work;
6790 struct drm_i915_gem_request *rq;
6791};
6792
6793static void __intel_rps_boost_work(struct work_struct *work)
6794{
6795 struct request_boost *boost = container_of(work, struct request_boost, work);
6796
6797 if (!i915_gem_request_completed(boost->rq, true))
1854d5ca 6798 gen6_rps_boost(to_i915(boost->rq->ring->dev), NULL);
6ad790c0
CW		 6799
6800 i915_gem_request_unreference__unlocked(boost->rq);
6801 kfree(boost);
6802}
6803
6804void intel_queue_rps_boost_for_request(struct drm_device *dev,
6805 struct drm_i915_gem_request *rq)
6806{
6807 struct request_boost *boost;
6808
6809 if (rq == NULL || INTEL_INFO(dev)->gen < 6)
6810 return;
6811
6812 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6813 if (boost == NULL)
6814 return;
6815
6816 i915_gem_request_reference(rq);
6817 boost->rq = rq;
6818
6819 INIT_WORK(&boost->work, __intel_rps_boost_work);
6820 queue_work(to_i915(dev)->wq, &boost->work);
6821}
6822
f742a552 6823void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6824{
6825 struct drm_i915_private *dev_priv = dev->dev_private;
6826
f742a552
DV		 6827 mutex_init(&dev_priv->rps.hw_lock);
6828
907b28c5
CW		 6829 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6830 intel_gen6_powersave_work);
1854d5ca 6831 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 6832
33688d95 6833 dev_priv->pm.suspended = false;
907b28c5 6834}
Linux kernel - Deliverables
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