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drm/i915: IVB FBC WaFbcDisableDpfcClockGating
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
3490ea5d
CW		 47static bool intel_crtc_active(struct drm_crtc *crtc)
48{
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53}
54
1fa61106 55static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 56{
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75}
76
1fa61106 77static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 78{
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
84f44ce7
VS		 116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 118}
119
1fa61106 120static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125}
126
1fa61106 127static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 128{
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
84f44ce7 151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 152}
153
1fa61106 154static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 155{
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167}
168
1fa61106 169static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 170{
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174}
175
176static void sandybridge_blit_fbc_update(struct drm_device *dev)
177{
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194}
195
1fa61106 196static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 197{
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
84f44ce7 231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 232}
233
1fa61106 234static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
b74ea102
RV		 245 if (IS_IVYBRIDGE(dev))
246 /* WaFbcDisableDpfcClockGating */
247 I915_WRITE(ILK_DSPCLK_GATE_D,
248 I915_READ(ILK_DSPCLK_GATE_D) &
249 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
250
85208be0
ED		 251 DRM_DEBUG_KMS("disabled FBC\n");
252 }
253}
254
1fa61106 255static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258
259 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
260}
261
abe959c7
RV		 262static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
263{
264 struct drm_device *dev = crtc->dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_framebuffer *fb = crtc->fb;
267 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
268 struct drm_i915_gem_object *obj = intel_fb->obj;
269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
270
271 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
272
273 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
274 IVB_DPFC_CTL_FENCE_EN |
275 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
276
30ca7c6f
RV		 277 /* WaFbcAsynchFlipDisableFbcQueue */
278 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
b74ea102
RV		 279 /* WaFbcDisableDpfcClockGating */
280 I915_WRITE(ILK_DSPCLK_GATE_D,
281 I915_READ(ILK_DSPCLK_GATE_D) |
282 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
283
abe959c7
RV		 284 I915_WRITE(SNB_DPFC_CTL_SA,
285 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
286 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
287
288 sandybridge_blit_fbc_update(dev);
289
290 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
291}
292
85208be0
ED		 293bool intel_fbc_enabled(struct drm_device *dev)
294{
295 struct drm_i915_private *dev_priv = dev->dev_private;
296
297 if (!dev_priv->display.fbc_enabled)
298 return false;
299
300 return dev_priv->display.fbc_enabled(dev);
301}
302
303static void intel_fbc_work_fn(struct work_struct *__work)
304{
305 struct intel_fbc_work *work =
306 container_of(to_delayed_work(__work),
307 struct intel_fbc_work, work);
308 struct drm_device *dev = work->crtc->dev;
309 struct drm_i915_private *dev_priv = dev->dev_private;
310
311 mutex_lock(&dev->struct_mutex);
312 if (work == dev_priv->fbc_work) {
313 /* Double check that we haven't switched fb without cancelling
314 * the prior work.
315 */
316 if (work->crtc->fb == work->fb) {
317 dev_priv->display.enable_fbc(work->crtc,
318 work->interval);
319
320 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
321 dev_priv->cfb_fb = work->crtc->fb->base.id;
322 dev_priv->cfb_y = work->crtc->y;
323 }
324
325 dev_priv->fbc_work = NULL;
326 }
327 mutex_unlock(&dev->struct_mutex);
328
329 kfree(work);
330}
331
332static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
333{
334 if (dev_priv->fbc_work == NULL)
335 return;
336
337 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
338
339 /* Synchronisation is provided by struct_mutex and checking of
340 * dev_priv->fbc_work, so we can perform the cancellation
341 * entirely asynchronously.
342 */
343 if (cancel_delayed_work(&dev_priv->fbc_work->work))
344 /* tasklet was killed before being run, clean up */
345 kfree(dev_priv->fbc_work);
346
347 /* Mark the work as no longer wanted so that if it does
348 * wake-up (because the work was already running and waiting
349 * for our mutex), it will discover that is no longer
350 * necessary to run.
351 */
352 dev_priv->fbc_work = NULL;
353}
354
355void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
356{
357 struct intel_fbc_work *work;
358 struct drm_device *dev = crtc->dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
360
361 if (!dev_priv->display.enable_fbc)
362 return;
363
364 intel_cancel_fbc_work(dev_priv);
365
366 work = kzalloc(sizeof *work, GFP_KERNEL);
367 if (work == NULL) {
368 dev_priv->display.enable_fbc(crtc, interval);
369 return;
370 }
371
372 work->crtc = crtc;
373 work->fb = crtc->fb;
374 work->interval = interval;
375 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
376
377 dev_priv->fbc_work = work;
378
379 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
380
381 /* Delay the actual enabling to let pageflipping cease and the
382 * display to settle before starting the compression. Note that
383 * this delay also serves a second purpose: it allows for a
384 * vblank to pass after disabling the FBC before we attempt
385 * to modify the control registers.
386 *
387 * A more complicated solution would involve tracking vblanks
388 * following the termination of the page-flipping sequence
389 * and indeed performing the enable as a co-routine and not
390 * waiting synchronously upon the vblank.
391 */
392 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
393}
394
395void intel_disable_fbc(struct drm_device *dev)
396{
397 struct drm_i915_private *dev_priv = dev->dev_private;
398
399 intel_cancel_fbc_work(dev_priv);
400
401 if (!dev_priv->display.disable_fbc)
402 return;
403
404 dev_priv->display.disable_fbc(dev);
405 dev_priv->cfb_plane = -1;
406}
407
408/**
409 * intel_update_fbc - enable/disable FBC as needed
410 * @dev: the drm_device
411 *
412 * Set up the framebuffer compression hardware at mode set time. We
413 * enable it if possible:
414 * - plane A only (on pre-965)
415 * - no pixel mulitply/line duplication
416 * - no alpha buffer discard
417 * - no dual wide
418 * - framebuffer <= 2048 in width, 1536 in height
419 *
420 * We can't assume that any compression will take place (worst case),
421 * so the compressed buffer has to be the same size as the uncompressed
422 * one. It also must reside (along with the line length buffer) in
423 * stolen memory.
424 *
425 * We need to enable/disable FBC on a global basis.
426 */
427void intel_update_fbc(struct drm_device *dev)
428{
429 struct drm_i915_private *dev_priv = dev->dev_private;
430 struct drm_crtc *crtc = NULL, *tmp_crtc;
431 struct intel_crtc *intel_crtc;
432 struct drm_framebuffer *fb;
433 struct intel_framebuffer *intel_fb;
434 struct drm_i915_gem_object *obj;
435 int enable_fbc;
436
85208be0
ED		 437 if (!i915_powersave)
438 return;
439
440 if (!I915_HAS_FBC(dev))
441 return;
442
443 /*
444 * If FBC is already on, we just have to verify that we can
445 * keep it that way...
446 * Need to disable if:
447 * - more than one pipe is active
448 * - changing FBC params (stride, fence, mode)
449 * - new fb is too large to fit in compressed buffer
450 * - going to an unsupported config (interlace, pixel multiply, etc.)
451 */
452 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 453 if (intel_crtc_active(tmp_crtc) &&
454 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 455 if (crtc) {
456 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
457 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
458 goto out_disable;
459 }
460 crtc = tmp_crtc;
461 }
462 }
463
464 if (!crtc || crtc->fb == NULL) {
465 DRM_DEBUG_KMS("no output, disabling\n");
466 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
467 goto out_disable;
468 }
469
470 intel_crtc = to_intel_crtc(crtc);
471 fb = crtc->fb;
472 intel_fb = to_intel_framebuffer(fb);
473 obj = intel_fb->obj;
474
475 enable_fbc = i915_enable_fbc;
476 if (enable_fbc < 0) {
477 DRM_DEBUG_KMS("fbc set to per-chip default\n");
478 enable_fbc = 1;
abe959c7 479 if (INTEL_INFO(dev)->gen <= 7)
85208be0
ED		 480 enable_fbc = 0;
481 }
482 if (!enable_fbc) {
483 DRM_DEBUG_KMS("fbc disabled per module param\n");
484 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
485 goto out_disable;
486 }
85208be0
ED		 487 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
488 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
489 DRM_DEBUG_KMS("mode incompatible with compression, "
490 "disabling\n");
491 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
492 goto out_disable;
493 }
494 if ((crtc->mode.hdisplay > 2048) ||
495 (crtc->mode.vdisplay > 1536)) {
496 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
497 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
498 goto out_disable;
499 }
500 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
501 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
502 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
503 goto out_disable;
504 }
505
506 /* The use of a CPU fence is mandatory in order to detect writes
507 * by the CPU to the scanout and trigger updates to the FBC.
508 */
509 if (obj->tiling_mode != I915_TILING_X ||
510 obj->fence_reg == I915_FENCE_REG_NONE) {
511 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
512 dev_priv->no_fbc_reason = FBC_NOT_TILED;
513 goto out_disable;
514 }
515
516 /* If the kernel debugger is active, always disable compression */
517 if (in_dbg_master())
518 goto out_disable;
519
11be49eb 520 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
11be49eb
CW		 521 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
522 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
523 goto out_disable;
524 }
525
85208be0
ED		 526 /* If the scanout has not changed, don't modify the FBC settings.
527 * Note that we make the fundamental assumption that the fb->obj
528 * cannot be unpinned (and have its GTT offset and fence revoked)
529 * without first being decoupled from the scanout and FBC disabled.
530 */
531 if (dev_priv->cfb_plane == intel_crtc->plane &&
532 dev_priv->cfb_fb == fb->base.id &&
533 dev_priv->cfb_y == crtc->y)
534 return;
535
536 if (intel_fbc_enabled(dev)) {
537 /* We update FBC along two paths, after changing fb/crtc
538 * configuration (modeswitching) and after page-flipping
539 * finishes. For the latter, we know that not only did
540 * we disable the FBC at the start of the page-flip
541 * sequence, but also more than one vblank has passed.
542 *
543 * For the former case of modeswitching, it is possible
544 * to switch between two FBC valid configurations
545 * instantaneously so we do need to disable the FBC
546 * before we can modify its control registers. We also
547 * have to wait for the next vblank for that to take
548 * effect. However, since we delay enabling FBC we can
549 * assume that a vblank has passed since disabling and
550 * that we can safely alter the registers in the deferred
551 * callback.
552 *
553 * In the scenario that we go from a valid to invalid
554 * and then back to valid FBC configuration we have
555 * no strict enforcement that a vblank occurred since
556 * disabling the FBC. However, along all current pipe
557 * disabling paths we do need to wait for a vblank at
558 * some point. And we wait before enabling FBC anyway.
559 */
560 DRM_DEBUG_KMS("disabling active FBC for update\n");
561 intel_disable_fbc(dev);
562 }
563
564 intel_enable_fbc(crtc, 500);
565 return;
566
567out_disable:
568 /* Multiple disables should be harmless */
569 if (intel_fbc_enabled(dev)) {
570 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
571 intel_disable_fbc(dev);
572 }
11be49eb 573 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 574}
575
c921aba8
DV		 576static void i915_pineview_get_mem_freq(struct drm_device *dev)
577{
578 drm_i915_private_t *dev_priv = dev->dev_private;
579 u32 tmp;
580
581 tmp = I915_READ(CLKCFG);
582
583 switch (tmp & CLKCFG_FSB_MASK) {
584 case CLKCFG_FSB_533:
585 dev_priv->fsb_freq = 533; /* 133*4 */
586 break;
587 case CLKCFG_FSB_800:
588 dev_priv->fsb_freq = 800; /* 200*4 */
589 break;
590 case CLKCFG_FSB_667:
591 dev_priv->fsb_freq = 667; /* 167*4 */
592 break;
593 case CLKCFG_FSB_400:
594 dev_priv->fsb_freq = 400; /* 100*4 */
595 break;
596 }
597
598 switch (tmp & CLKCFG_MEM_MASK) {
599 case CLKCFG_MEM_533:
600 dev_priv->mem_freq = 533;
601 break;
602 case CLKCFG_MEM_667:
603 dev_priv->mem_freq = 667;
604 break;
605 case CLKCFG_MEM_800:
606 dev_priv->mem_freq = 800;
607 break;
608 }
609
610 /* detect pineview DDR3 setting */
611 tmp = I915_READ(CSHRDDR3CTL);
612 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
613}
614
615static void i915_ironlake_get_mem_freq(struct drm_device *dev)
616{
617 drm_i915_private_t *dev_priv = dev->dev_private;
618 u16 ddrpll, csipll;
619
620 ddrpll = I915_READ16(DDRMPLL1);
621 csipll = I915_READ16(CSIPLL0);
622
623 switch (ddrpll & 0xff) {
624 case 0xc:
625 dev_priv->mem_freq = 800;
626 break;
627 case 0x10:
628 dev_priv->mem_freq = 1066;
629 break;
630 case 0x14:
631 dev_priv->mem_freq = 1333;
632 break;
633 case 0x18:
634 dev_priv->mem_freq = 1600;
635 break;
636 default:
637 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
638 ddrpll & 0xff);
639 dev_priv->mem_freq = 0;
640 break;
641 }
642
20e4d407 643 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 644
645 switch (csipll & 0x3ff) {
646 case 0x00c:
647 dev_priv->fsb_freq = 3200;
648 break;
649 case 0x00e:
650 dev_priv->fsb_freq = 3733;
651 break;
652 case 0x010:
653 dev_priv->fsb_freq = 4266;
654 break;
655 case 0x012:
656 dev_priv->fsb_freq = 4800;
657 break;
658 case 0x014:
659 dev_priv->fsb_freq = 5333;
660 break;
661 case 0x016:
662 dev_priv->fsb_freq = 5866;
663 break;
664 case 0x018:
665 dev_priv->fsb_freq = 6400;
666 break;
667 default:
668 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
669 csipll & 0x3ff);
670 dev_priv->fsb_freq = 0;
671 break;
672 }
673
674 if (dev_priv->fsb_freq == 3200) {
20e4d407 675 dev_priv->ips.c_m = 0;
c921aba8 676 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 677 dev_priv->ips.c_m = 1;
c921aba8 678 } else {
20e4d407 679 dev_priv->ips.c_m = 2;
c921aba8
DV		 680 }
681}
682
b445e3b0
ED		 683static const struct cxsr_latency cxsr_latency_table[] = {
684 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
685 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
686 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
687 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
688 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
689
690 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
691 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
692 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
693 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
694 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
695
696 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
697 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
698 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
699 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
700 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
701
702 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
703 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
704 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
705 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
706 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
707
708 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
709 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
710 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
711 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
712 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
713
714 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
715 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
716 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
717 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
718 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
719};
720
63c62275 721static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 722 int is_ddr3,
723 int fsb,
724 int mem)
725{
726 const struct cxsr_latency *latency;
727 int i;
728
729 if (fsb == 0 || mem == 0)
730 return NULL;
731
732 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
733 latency = &cxsr_latency_table[i];
734 if (is_desktop == latency->is_desktop &&
735 is_ddr3 == latency->is_ddr3 &&
736 fsb == latency->fsb_freq && mem == latency->mem_freq)
737 return latency;
738 }
739
740 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
741
742 return NULL;
743}
744
1fa61106 745static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748
749 /* deactivate cxsr */
750 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
751}
752
753/*
754 * Latency for FIFO fetches is dependent on several factors:
755 * - memory configuration (speed, channels)
756 * - chipset
757 * - current MCH state
758 * It can be fairly high in some situations, so here we assume a fairly
759 * pessimal value. It's a tradeoff between extra memory fetches (if we
760 * set this value too high, the FIFO will fetch frequently to stay full)
761 * and power consumption (set it too low to save power and we might see
762 * FIFO underruns and display "flicker").
763 *
764 * A value of 5us seems to be a good balance; safe for very low end
765 * platforms but not overly aggressive on lower latency configs.
766 */
767static const int latency_ns = 5000;
768
1fa61106 769static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 770{
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 uint32_t dsparb = I915_READ(DSPARB);
773 int size;
774
775 size = dsparb & 0x7f;
776 if (plane)
777 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
778
779 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
780 plane ? "B" : "A", size);
781
782 return size;
783}
784
1fa61106 785static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 uint32_t dsparb = I915_READ(DSPARB);
789 int size;
790
791 size = dsparb & 0x1ff;
792 if (plane)
793 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
794 size >>= 1; /* Convert to cachelines */
795
796 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
797 plane ? "B" : "A", size);
798
799 return size;
800}
801
1fa61106 802static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 803{
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 uint32_t dsparb = I915_READ(DSPARB);
806 int size;
807
808 size = dsparb & 0x7f;
809 size >>= 2; /* Convert to cachelines */
810
811 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
812 plane ? "B" : "A",
813 size);
814
815 return size;
816}
817
1fa61106 818static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 819{
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 uint32_t dsparb = I915_READ(DSPARB);
822 int size;
823
824 size = dsparb & 0x7f;
825 size >>= 1; /* Convert to cachelines */
826
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
829
830 return size;
831}
832
833/* Pineview has different values for various configs */
834static const struct intel_watermark_params pineview_display_wm = {
835 PINEVIEW_DISPLAY_FIFO,
836 PINEVIEW_MAX_WM,
837 PINEVIEW_DFT_WM,
838 PINEVIEW_GUARD_WM,
839 PINEVIEW_FIFO_LINE_SIZE
840};
841static const struct intel_watermark_params pineview_display_hplloff_wm = {
842 PINEVIEW_DISPLAY_FIFO,
843 PINEVIEW_MAX_WM,
844 PINEVIEW_DFT_HPLLOFF_WM,
845 PINEVIEW_GUARD_WM,
846 PINEVIEW_FIFO_LINE_SIZE
847};
848static const struct intel_watermark_params pineview_cursor_wm = {
849 PINEVIEW_CURSOR_FIFO,
850 PINEVIEW_CURSOR_MAX_WM,
851 PINEVIEW_CURSOR_DFT_WM,
852 PINEVIEW_CURSOR_GUARD_WM,
853 PINEVIEW_FIFO_LINE_SIZE,
854};
855static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
856 PINEVIEW_CURSOR_FIFO,
857 PINEVIEW_CURSOR_MAX_WM,
858 PINEVIEW_CURSOR_DFT_WM,
859 PINEVIEW_CURSOR_GUARD_WM,
860 PINEVIEW_FIFO_LINE_SIZE
861};
862static const struct intel_watermark_params g4x_wm_info = {
863 G4X_FIFO_SIZE,
864 G4X_MAX_WM,
865 G4X_MAX_WM,
866 2,
867 G4X_FIFO_LINE_SIZE,
868};
869static const struct intel_watermark_params g4x_cursor_wm_info = {
870 I965_CURSOR_FIFO,
871 I965_CURSOR_MAX_WM,
872 I965_CURSOR_DFT_WM,
873 2,
874 G4X_FIFO_LINE_SIZE,
875};
876static const struct intel_watermark_params valleyview_wm_info = {
877 VALLEYVIEW_FIFO_SIZE,
878 VALLEYVIEW_MAX_WM,
879 VALLEYVIEW_MAX_WM,
880 2,
881 G4X_FIFO_LINE_SIZE,
882};
883static const struct intel_watermark_params valleyview_cursor_wm_info = {
884 I965_CURSOR_FIFO,
885 VALLEYVIEW_CURSOR_MAX_WM,
886 I965_CURSOR_DFT_WM,
887 2,
888 G4X_FIFO_LINE_SIZE,
889};
890static const struct intel_watermark_params i965_cursor_wm_info = {
891 I965_CURSOR_FIFO,
892 I965_CURSOR_MAX_WM,
893 I965_CURSOR_DFT_WM,
894 2,
895 I915_FIFO_LINE_SIZE,
896};
897static const struct intel_watermark_params i945_wm_info = {
898 I945_FIFO_SIZE,
899 I915_MAX_WM,
900 1,
901 2,
902 I915_FIFO_LINE_SIZE
903};
904static const struct intel_watermark_params i915_wm_info = {
905 I915_FIFO_SIZE,
906 I915_MAX_WM,
907 1,
908 2,
909 I915_FIFO_LINE_SIZE
910};
911static const struct intel_watermark_params i855_wm_info = {
912 I855GM_FIFO_SIZE,
913 I915_MAX_WM,
914 1,
915 2,
916 I830_FIFO_LINE_SIZE
917};
918static const struct intel_watermark_params i830_wm_info = {
919 I830_FIFO_SIZE,
920 I915_MAX_WM,
921 1,
922 2,
923 I830_FIFO_LINE_SIZE
924};
925
926static const struct intel_watermark_params ironlake_display_wm_info = {
927 ILK_DISPLAY_FIFO,
928 ILK_DISPLAY_MAXWM,
929 ILK_DISPLAY_DFTWM,
930 2,
931 ILK_FIFO_LINE_SIZE
932};
933static const struct intel_watermark_params ironlake_cursor_wm_info = {
934 ILK_CURSOR_FIFO,
935 ILK_CURSOR_MAXWM,
936 ILK_CURSOR_DFTWM,
937 2,
938 ILK_FIFO_LINE_SIZE
939};
940static const struct intel_watermark_params ironlake_display_srwm_info = {
941 ILK_DISPLAY_SR_FIFO,
942 ILK_DISPLAY_MAX_SRWM,
943 ILK_DISPLAY_DFT_SRWM,
944 2,
945 ILK_FIFO_LINE_SIZE
946};
947static const struct intel_watermark_params ironlake_cursor_srwm_info = {
948 ILK_CURSOR_SR_FIFO,
949 ILK_CURSOR_MAX_SRWM,
950 ILK_CURSOR_DFT_SRWM,
951 2,
952 ILK_FIFO_LINE_SIZE
953};
954
955static const struct intel_watermark_params sandybridge_display_wm_info = {
956 SNB_DISPLAY_FIFO,
957 SNB_DISPLAY_MAXWM,
958 SNB_DISPLAY_DFTWM,
959 2,
960 SNB_FIFO_LINE_SIZE
961};
962static const struct intel_watermark_params sandybridge_cursor_wm_info = {
963 SNB_CURSOR_FIFO,
964 SNB_CURSOR_MAXWM,
965 SNB_CURSOR_DFTWM,
966 2,
967 SNB_FIFO_LINE_SIZE
968};
969static const struct intel_watermark_params sandybridge_display_srwm_info = {
970 SNB_DISPLAY_SR_FIFO,
971 SNB_DISPLAY_MAX_SRWM,
972 SNB_DISPLAY_DFT_SRWM,
973 2,
974 SNB_FIFO_LINE_SIZE
975};
976static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
977 SNB_CURSOR_SR_FIFO,
978 SNB_CURSOR_MAX_SRWM,
979 SNB_CURSOR_DFT_SRWM,
980 2,
981 SNB_FIFO_LINE_SIZE
982};
983
984
985/**
986 * intel_calculate_wm - calculate watermark level
987 * @clock_in_khz: pixel clock
988 * @wm: chip FIFO params
989 * @pixel_size: display pixel size
990 * @latency_ns: memory latency for the platform
991 *
992 * Calculate the watermark level (the level at which the display plane will
993 * start fetching from memory again). Each chip has a different display
994 * FIFO size and allocation, so the caller needs to figure that out and pass
995 * in the correct intel_watermark_params structure.
996 *
997 * As the pixel clock runs, the FIFO will be drained at a rate that depends
998 * on the pixel size. When it reaches the watermark level, it'll start
999 * fetching FIFO line sized based chunks from memory until the FIFO fills
1000 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1001 * will occur, and a display engine hang could result.
1002 */
1003static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1004 const struct intel_watermark_params *wm,
1005 int fifo_size,
1006 int pixel_size,
1007 unsigned long latency_ns)
1008{
1009 long entries_required, wm_size;
1010
1011 /*
1012 * Note: we need to make sure we don't overflow for various clock &
1013 * latency values.
1014 * clocks go from a few thousand to several hundred thousand.
1015 * latency is usually a few thousand
1016 */
1017 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1018 1000;
1019 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1020
1021 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1022
1023 wm_size = fifo_size - (entries_required + wm->guard_size);
1024
1025 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1026
1027 /* Don't promote wm_size to unsigned... */
1028 if (wm_size > (long)wm->max_wm)
1029 wm_size = wm->max_wm;
1030 if (wm_size <= 0)
1031 wm_size = wm->default_wm;
1032 return wm_size;
1033}
1034
1035static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1036{
1037 struct drm_crtc *crtc, *enabled = NULL;
1038
1039 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1040 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1041 if (enabled)
1042 return NULL;
1043 enabled = crtc;
1044 }
1045 }
1046
1047 return enabled;
1048}
1049
1fa61106 1050static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1051{
1052 struct drm_i915_private *dev_priv = dev->dev_private;
1053 struct drm_crtc *crtc;
1054 const struct cxsr_latency *latency;
1055 u32 reg;
1056 unsigned long wm;
1057
1058 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1059 dev_priv->fsb_freq, dev_priv->mem_freq);
1060 if (!latency) {
1061 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1062 pineview_disable_cxsr(dev);
1063 return;
1064 }
1065
1066 crtc = single_enabled_crtc(dev);
1067 if (crtc) {
1068 int clock = crtc->mode.clock;
1069 int pixel_size = crtc->fb->bits_per_pixel / 8;
1070
1071 /* Display SR */
1072 wm = intel_calculate_wm(clock, &pineview_display_wm,
1073 pineview_display_wm.fifo_size,
1074 pixel_size, latency->display_sr);
1075 reg = I915_READ(DSPFW1);
1076 reg &= ~DSPFW_SR_MASK;
1077 reg |= wm << DSPFW_SR_SHIFT;
1078 I915_WRITE(DSPFW1, reg);
1079 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1080
1081 /* cursor SR */
1082 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1083 pineview_display_wm.fifo_size,
1084 pixel_size, latency->cursor_sr);
1085 reg = I915_READ(DSPFW3);
1086 reg &= ~DSPFW_CURSOR_SR_MASK;
1087 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1088 I915_WRITE(DSPFW3, reg);
1089
1090 /* Display HPLL off SR */
1091 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1092 pineview_display_hplloff_wm.fifo_size,
1093 pixel_size, latency->display_hpll_disable);
1094 reg = I915_READ(DSPFW3);
1095 reg &= ~DSPFW_HPLL_SR_MASK;
1096 reg |= wm & DSPFW_HPLL_SR_MASK;
1097 I915_WRITE(DSPFW3, reg);
1098
1099 /* cursor HPLL off SR */
1100 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1101 pineview_display_hplloff_wm.fifo_size,
1102 pixel_size, latency->cursor_hpll_disable);
1103 reg = I915_READ(DSPFW3);
1104 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1105 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1106 I915_WRITE(DSPFW3, reg);
1107 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1108
1109 /* activate cxsr */
1110 I915_WRITE(DSPFW3,
1111 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1112 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1113 } else {
1114 pineview_disable_cxsr(dev);
1115 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1116 }
1117}
1118
1119static bool g4x_compute_wm0(struct drm_device *dev,
1120 int plane,
1121 const struct intel_watermark_params *display,
1122 int display_latency_ns,
1123 const struct intel_watermark_params *cursor,
1124 int cursor_latency_ns,
1125 int *plane_wm,
1126 int *cursor_wm)
1127{
1128 struct drm_crtc *crtc;
1129 int htotal, hdisplay, clock, pixel_size;
1130 int line_time_us, line_count;
1131 int entries, tlb_miss;
1132
1133 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1134 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1135 *cursor_wm = cursor->guard_size;
1136 *plane_wm = display->guard_size;
1137 return false;
1138 }
1139
1140 htotal = crtc->mode.htotal;
1141 hdisplay = crtc->mode.hdisplay;
1142 clock = crtc->mode.clock;
1143 pixel_size = crtc->fb->bits_per_pixel / 8;
1144
1145 /* Use the small buffer method to calculate plane watermark */
1146 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1147 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1148 if (tlb_miss > 0)
1149 entries += tlb_miss;
1150 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1151 *plane_wm = entries + display->guard_size;
1152 if (*plane_wm > (int)display->max_wm)
1153 *plane_wm = display->max_wm;
1154
1155 /* Use the large buffer method to calculate cursor watermark */
1156 line_time_us = ((htotal * 1000) / clock);
1157 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1158 entries = line_count * 64 * pixel_size;
1159 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1160 if (tlb_miss > 0)
1161 entries += tlb_miss;
1162 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1163 *cursor_wm = entries + cursor->guard_size;
1164 if (*cursor_wm > (int)cursor->max_wm)
1165 *cursor_wm = (int)cursor->max_wm;
1166
1167 return true;
1168}
1169
1170/*
1171 * Check the wm result.
1172 *
1173 * If any calculated watermark values is larger than the maximum value that
1174 * can be programmed into the associated watermark register, that watermark
1175 * must be disabled.
1176 */
1177static bool g4x_check_srwm(struct drm_device *dev,
1178 int display_wm, int cursor_wm,
1179 const struct intel_watermark_params *display,
1180 const struct intel_watermark_params *cursor)
1181{
1182 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1183 display_wm, cursor_wm);
1184
1185 if (display_wm > display->max_wm) {
1186 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1187 display_wm, display->max_wm);
1188 return false;
1189 }
1190
1191 if (cursor_wm > cursor->max_wm) {
1192 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1193 cursor_wm, cursor->max_wm);
1194 return false;
1195 }
1196
1197 if (!(display_wm || cursor_wm)) {
1198 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1199 return false;
1200 }
1201
1202 return true;
1203}
1204
1205static bool g4x_compute_srwm(struct drm_device *dev,
1206 int plane,
1207 int latency_ns,
1208 const struct intel_watermark_params *display,
1209 const struct intel_watermark_params *cursor,
1210 int *display_wm, int *cursor_wm)
1211{
1212 struct drm_crtc *crtc;
1213 int hdisplay, htotal, pixel_size, clock;
1214 unsigned long line_time_us;
1215 int line_count, line_size;
1216 int small, large;
1217 int entries;
1218
1219 if (!latency_ns) {
1220 *display_wm = *cursor_wm = 0;
1221 return false;
1222 }
1223
1224 crtc = intel_get_crtc_for_plane(dev, plane);
1225 hdisplay = crtc->mode.hdisplay;
1226 htotal = crtc->mode.htotal;
1227 clock = crtc->mode.clock;
1228 pixel_size = crtc->fb->bits_per_pixel / 8;
1229
1230 line_time_us = (htotal * 1000) / clock;
1231 line_count = (latency_ns / line_time_us + 1000) / 1000;
1232 line_size = hdisplay * pixel_size;
1233
1234 /* Use the minimum of the small and large buffer method for primary */
1235 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1236 large = line_count * line_size;
1237
1238 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1239 *display_wm = entries + display->guard_size;
1240
1241 /* calculate the self-refresh watermark for display cursor */
1242 entries = line_count * pixel_size * 64;
1243 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1244 *cursor_wm = entries + cursor->guard_size;
1245
1246 return g4x_check_srwm(dev,
1247 *display_wm, *cursor_wm,
1248 display, cursor);
1249}
1250
1251static bool vlv_compute_drain_latency(struct drm_device *dev,
1252 int plane,
1253 int *plane_prec_mult,
1254 int *plane_dl,
1255 int *cursor_prec_mult,
1256 int *cursor_dl)
1257{
1258 struct drm_crtc *crtc;
1259 int clock, pixel_size;
1260 int entries;
1261
1262 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1263 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1264 return false;
1265
1266 clock = crtc->mode.clock; /* VESA DOT Clock */
1267 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1268
1269 entries = (clock / 1000) * pixel_size;
1270 *plane_prec_mult = (entries > 256) ?
1271 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1272 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1273 pixel_size);
1274
1275 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1276 *cursor_prec_mult = (entries > 256) ?
1277 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1278 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1279
1280 return true;
1281}
1282
1283/*
1284 * Update drain latency registers of memory arbiter
1285 *
1286 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1287 * to be programmed. Each plane has a drain latency multiplier and a drain
1288 * latency value.
1289 */
1290
1291static void vlv_update_drain_latency(struct drm_device *dev)
1292{
1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1295 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1296 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1297 either 16 or 32 */
1298
1299 /* For plane A, Cursor A */
1300 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1301 &cursor_prec_mult, &cursora_dl)) {
1302 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1303 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1304 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1305 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1306
1307 I915_WRITE(VLV_DDL1, cursora_prec |
1308 (cursora_dl << DDL_CURSORA_SHIFT) |
1309 planea_prec | planea_dl);
1310 }
1311
1312 /* For plane B, Cursor B */
1313 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1314 &cursor_prec_mult, &cursorb_dl)) {
1315 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1316 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1317 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1318 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1319
1320 I915_WRITE(VLV_DDL2, cursorb_prec |
1321 (cursorb_dl << DDL_CURSORB_SHIFT) |
1322 planeb_prec | planeb_dl);
1323 }
1324}
1325
1326#define single_plane_enabled(mask) is_power_of_2(mask)
1327
1fa61106 1328static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1329{
1330 static const int sr_latency_ns = 12000;
1331 struct drm_i915_private *dev_priv = dev->dev_private;
1332 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1333 int plane_sr, cursor_sr;
af6c4575 1334 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1335 unsigned int enabled = 0;
1336
1337 vlv_update_drain_latency(dev);
1338
1339 if (g4x_compute_wm0(dev, 0,
1340 &valleyview_wm_info, latency_ns,
1341 &valleyview_cursor_wm_info, latency_ns,
1342 &planea_wm, &cursora_wm))
1343 enabled |= 1;
1344
1345 if (g4x_compute_wm0(dev, 1,
1346 &valleyview_wm_info, latency_ns,
1347 &valleyview_cursor_wm_info, latency_ns,
1348 &planeb_wm, &cursorb_wm))
1349 enabled |= 2;
1350
b445e3b0
ED		 1351 if (single_plane_enabled(enabled) &&
1352 g4x_compute_srwm(dev, ffs(enabled) - 1,
1353 sr_latency_ns,
1354 &valleyview_wm_info,
1355 &valleyview_cursor_wm_info,
af6c4575
CW		 1356 &plane_sr, &ignore_cursor_sr) &&
1357 g4x_compute_srwm(dev, ffs(enabled) - 1,
1358 2*sr_latency_ns,
1359 &valleyview_wm_info,
1360 &valleyview_cursor_wm_info,
52bd02d8 1361 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1362 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1363 } else {
b445e3b0
ED		 1364 I915_WRITE(FW_BLC_SELF_VLV,
1365 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1366 plane_sr = cursor_sr = 0;
1367 }
b445e3b0
ED		 1368
1369 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1370 planea_wm, cursora_wm,
1371 planeb_wm, cursorb_wm,
1372 plane_sr, cursor_sr);
1373
1374 I915_WRITE(DSPFW1,
1375 (plane_sr << DSPFW_SR_SHIFT) |
1376 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1377 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1378 planea_wm);
1379 I915_WRITE(DSPFW2,
8c919b28 1380 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1381 (cursora_wm << DSPFW_CURSORA_SHIFT));
1382 I915_WRITE(DSPFW3,
8c919b28
CW		 1383 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1384 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1385}
1386
1fa61106 1387static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1388{
1389 static const int sr_latency_ns = 12000;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1392 int plane_sr, cursor_sr;
1393 unsigned int enabled = 0;
1394
1395 if (g4x_compute_wm0(dev, 0,
1396 &g4x_wm_info, latency_ns,
1397 &g4x_cursor_wm_info, latency_ns,
1398 &planea_wm, &cursora_wm))
1399 enabled |= 1;
1400
1401 if (g4x_compute_wm0(dev, 1,
1402 &g4x_wm_info, latency_ns,
1403 &g4x_cursor_wm_info, latency_ns,
1404 &planeb_wm, &cursorb_wm))
1405 enabled |= 2;
1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
b445e3b0 1413 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1414 } else {
b445e3b0
ED		 1415 I915_WRITE(FW_BLC_SELF,
1416 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0
ED		 1419
1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1421 planea_wm, cursora_wm,
1422 planeb_wm, cursorb_wm,
1423 plane_sr, cursor_sr);
1424
1425 I915_WRITE(DSPFW1,
1426 (plane_sr << DSPFW_SR_SHIFT) |
1427 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1428 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1429 planea_wm);
1430 I915_WRITE(DSPFW2,
8c919b28 1431 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1432 (cursora_wm << DSPFW_CURSORA_SHIFT));
1433 /* HPLL off in SR has some issues on G4x... disable it */
1434 I915_WRITE(DSPFW3,
8c919b28 1435 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1436 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1437}
1438
1fa61106 1439static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1440{
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 struct drm_crtc *crtc;
1443 int srwm = 1;
1444 int cursor_sr = 16;
1445
1446 /* Calc sr entries for one plane configs */
1447 crtc = single_enabled_crtc(dev);
1448 if (crtc) {
1449 /* self-refresh has much higher latency */
1450 static const int sr_latency_ns = 12000;
1451 int clock = crtc->mode.clock;
1452 int htotal = crtc->mode.htotal;
1453 int hdisplay = crtc->mode.hdisplay;
1454 int pixel_size = crtc->fb->bits_per_pixel / 8;
1455 unsigned long line_time_us;
1456 int entries;
1457
1458 line_time_us = ((htotal * 1000) / clock);
1459
1460 /* Use ns/us then divide to preserve precision */
1461 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1462 pixel_size * hdisplay;
1463 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1464 srwm = I965_FIFO_SIZE - entries;
1465 if (srwm < 0)
1466 srwm = 1;
1467 srwm &= 0x1ff;
1468 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1469 entries, srwm);
1470
1471 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1472 pixel_size * 64;
1473 entries = DIV_ROUND_UP(entries,
1474 i965_cursor_wm_info.cacheline_size);
1475 cursor_sr = i965_cursor_wm_info.fifo_size -
1476 (entries + i965_cursor_wm_info.guard_size);
1477
1478 if (cursor_sr > i965_cursor_wm_info.max_wm)
1479 cursor_sr = i965_cursor_wm_info.max_wm;
1480
1481 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1482 "cursor %d\n", srwm, cursor_sr);
1483
1484 if (IS_CRESTLINE(dev))
1485 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1486 } else {
1487 /* Turn off self refresh if both pipes are enabled */
1488 if (IS_CRESTLINE(dev))
1489 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1490 & ~FW_BLC_SELF_EN);
1491 }
1492
1493 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1494 srwm);
1495
1496 /* 965 has limitations... */
1497 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1498 (8 << 16) | (8 << 8) | (8 << 0));
1499 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1500 /* update cursor SR watermark */
1501 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1502}
1503
1fa61106 1504static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1505{
1506 struct drm_i915_private *dev_priv = dev->dev_private;
1507 const struct intel_watermark_params *wm_info;
1508 uint32_t fwater_lo;
1509 uint32_t fwater_hi;
1510 int cwm, srwm = 1;
1511 int fifo_size;
1512 int planea_wm, planeb_wm;
1513 struct drm_crtc *crtc, *enabled = NULL;
1514
1515 if (IS_I945GM(dev))
1516 wm_info = &i945_wm_info;
1517 else if (!IS_GEN2(dev))
1518 wm_info = &i915_wm_info;
1519 else
1520 wm_info = &i855_wm_info;
1521
1522 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1523 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1524 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1525 int cpp = crtc->fb->bits_per_pixel / 8;
1526 if (IS_GEN2(dev))
1527 cpp = 4;
1528
b445e3b0 1529 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1530 wm_info, fifo_size, cpp,
b445e3b0
ED		 1531 latency_ns);
1532 enabled = crtc;
1533 } else
1534 planea_wm = fifo_size - wm_info->guard_size;
1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1537 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1539 int cpp = crtc->fb->bits_per_pixel / 8;
1540 if (IS_GEN2(dev))
1541 cpp = 4;
1542
b445e3b0 1543 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1544 wm_info, fifo_size, cpp,
b445e3b0
ED		 1545 latency_ns);
1546 if (enabled == NULL)
1547 enabled = crtc;
1548 else
1549 enabled = NULL;
1550 } else
1551 planeb_wm = fifo_size - wm_info->guard_size;
1552
1553 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1554
1555 /*
1556 * Overlay gets an aggressive default since video jitter is bad.
1557 */
1558 cwm = 2;
1559
1560 /* Play safe and disable self-refresh before adjusting watermarks. */
1561 if (IS_I945G(dev) || IS_I945GM(dev))
1562 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1563 else if (IS_I915GM(dev))
1564 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
1570 int clock = enabled->mode.clock;
1571 int htotal = enabled->mode.htotal;
1572 int hdisplay = enabled->mode.hdisplay;
1573 int pixel_size = enabled->fb->bits_per_pixel / 8;
1574 unsigned long line_time_us;
1575 int entries;
1576
1577 line_time_us = (htotal * 1000) / clock;
1578
1579 /* Use ns/us then divide to preserve precision */
1580 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1581 pixel_size * hdisplay;
1582 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1583 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1584 srwm = wm_info->fifo_size - entries;
1585 if (srwm < 0)
1586 srwm = 1;
1587
1588 if (IS_I945G(dev) || IS_I945GM(dev))
1589 I915_WRITE(FW_BLC_SELF,
1590 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1591 else if (IS_I915GM(dev))
1592 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1593 }
1594
1595 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1596 planea_wm, planeb_wm, cwm, srwm);
1597
1598 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1599 fwater_hi = (cwm & 0x1f);
1600
1601 /* Set request length to 8 cachelines per fetch */
1602 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1603 fwater_hi = fwater_hi | (1 << 8);
1604
1605 I915_WRITE(FW_BLC, fwater_lo);
1606 I915_WRITE(FW_BLC2, fwater_hi);
1607
1608 if (HAS_FW_BLC(dev)) {
1609 if (enabled) {
1610 if (IS_I945G(dev) || IS_I945GM(dev))
1611 I915_WRITE(FW_BLC_SELF,
1612 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1613 else if (IS_I915GM(dev))
1614 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1615 DRM_DEBUG_KMS("memory self refresh enabled\n");
1616 } else
1617 DRM_DEBUG_KMS("memory self refresh disabled\n");
1618 }
1619}
1620
1fa61106 1621static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1622{
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_crtc *crtc;
1625 uint32_t fwater_lo;
1626 int planea_wm;
1627
1628 crtc = single_enabled_crtc(dev);
1629 if (crtc == NULL)
1630 return;
1631
1632 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1633 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1634 4, latency_ns);
b445e3b0
ED		 1635 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1636 fwater_lo |= (3<<8) | planea_wm;
1637
1638 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1639
1640 I915_WRITE(FW_BLC, fwater_lo);
1641}
1642
1643#define ILK_LP0_PLANE_LATENCY 700
1644#define ILK_LP0_CURSOR_LATENCY 1300
1645
1646/*
1647 * Check the wm result.
1648 *
1649 * If any calculated watermark values is larger than the maximum value that
1650 * can be programmed into the associated watermark register, that watermark
1651 * must be disabled.
1652 */
1653static bool ironlake_check_srwm(struct drm_device *dev, int level,
1654 int fbc_wm, int display_wm, int cursor_wm,
1655 const struct intel_watermark_params *display,
1656 const struct intel_watermark_params *cursor)
1657{
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1661 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1662
1663 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1664 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1665 fbc_wm, SNB_FBC_MAX_SRWM, level);
1666
1667 /* fbc has it's own way to disable FBC WM */
1668 I915_WRITE(DISP_ARB_CTL,
1669 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1670 return false;
615aaa5f
VS		 1671 } else if (INTEL_INFO(dev)->gen >= 6) {
1672 /* enable FBC WM (except on ILK, where it must remain off) */
1673 I915_WRITE(DISP_ARB_CTL,
1674 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1675 }
1676
1677 if (display_wm > display->max_wm) {
1678 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1679 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1680 return false;
1681 }
1682
1683 if (cursor_wm > cursor->max_wm) {
1684 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1685 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1686 return false;
1687 }
1688
1689 if (!(fbc_wm || display_wm || cursor_wm)) {
1690 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1691 return false;
1692 }
1693
1694 return true;
1695}
1696
1697/*
1698 * Compute watermark values of WM[1-3],
1699 */
1700static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1701 int latency_ns,
1702 const struct intel_watermark_params *display,
1703 const struct intel_watermark_params *cursor,
1704 int *fbc_wm, int *display_wm, int *cursor_wm)
1705{
1706 struct drm_crtc *crtc;
1707 unsigned long line_time_us;
1708 int hdisplay, htotal, pixel_size, clock;
1709 int line_count, line_size;
1710 int small, large;
1711 int entries;
1712
1713 if (!latency_ns) {
1714 *fbc_wm = *display_wm = *cursor_wm = 0;
1715 return false;
1716 }
1717
1718 crtc = intel_get_crtc_for_plane(dev, plane);
1719 hdisplay = crtc->mode.hdisplay;
1720 htotal = crtc->mode.htotal;
1721 clock = crtc->mode.clock;
1722 pixel_size = crtc->fb->bits_per_pixel / 8;
1723
1724 line_time_us = (htotal * 1000) / clock;
1725 line_count = (latency_ns / line_time_us + 1000) / 1000;
1726 line_size = hdisplay * pixel_size;
1727
1728 /* Use the minimum of the small and large buffer method for primary */
1729 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1730 large = line_count * line_size;
1731
1732 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1733 *display_wm = entries + display->guard_size;
1734
1735 /*
1736 * Spec says:
1737 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1738 */
1739 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1740
1741 /* calculate the self-refresh watermark for display cursor */
1742 entries = line_count * pixel_size * 64;
1743 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1744 *cursor_wm = entries + cursor->guard_size;
1745
1746 return ironlake_check_srwm(dev, level,
1747 *fbc_wm, *display_wm, *cursor_wm,
1748 display, cursor);
1749}
1750
1fa61106 1751static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1752{
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 int fbc_wm, plane_wm, cursor_wm;
1755 unsigned int enabled;
1756
1757 enabled = 0;
1758 if (g4x_compute_wm0(dev, 0,
1759 &ironlake_display_wm_info,
1760 ILK_LP0_PLANE_LATENCY,
1761 &ironlake_cursor_wm_info,
1762 ILK_LP0_CURSOR_LATENCY,
1763 &plane_wm, &cursor_wm)) {
1764 I915_WRITE(WM0_PIPEA_ILK,
1765 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1766 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1767 " plane %d, " "cursor: %d\n",
1768 plane_wm, cursor_wm);
1769 enabled |= 1;
1770 }
1771
1772 if (g4x_compute_wm0(dev, 1,
1773 &ironlake_display_wm_info,
1774 ILK_LP0_PLANE_LATENCY,
1775 &ironlake_cursor_wm_info,
1776 ILK_LP0_CURSOR_LATENCY,
1777 &plane_wm, &cursor_wm)) {
1778 I915_WRITE(WM0_PIPEB_ILK,
1779 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1780 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1781 " plane %d, cursor: %d\n",
1782 plane_wm, cursor_wm);
1783 enabled |= 2;
1784 }
1785
1786 /*
1787 * Calculate and update the self-refresh watermark only when one
1788 * display plane is used.
1789 */
1790 I915_WRITE(WM3_LP_ILK, 0);
1791 I915_WRITE(WM2_LP_ILK, 0);
1792 I915_WRITE(WM1_LP_ILK, 0);
1793
1794 if (!single_plane_enabled(enabled))
1795 return;
1796 enabled = ffs(enabled) - 1;
1797
1798 /* WM1 */
1799 if (!ironlake_compute_srwm(dev, 1, enabled,
1800 ILK_READ_WM1_LATENCY() * 500,
1801 &ironlake_display_srwm_info,
1802 &ironlake_cursor_srwm_info,
1803 &fbc_wm, &plane_wm, &cursor_wm))
1804 return;
1805
1806 I915_WRITE(WM1_LP_ILK,
1807 WM1_LP_SR_EN |
1808 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1809 (fbc_wm << WM1_LP_FBC_SHIFT) |
1810 (plane_wm << WM1_LP_SR_SHIFT) |
1811 cursor_wm);
1812
1813 /* WM2 */
1814 if (!ironlake_compute_srwm(dev, 2, enabled,
1815 ILK_READ_WM2_LATENCY() * 500,
1816 &ironlake_display_srwm_info,
1817 &ironlake_cursor_srwm_info,
1818 &fbc_wm, &plane_wm, &cursor_wm))
1819 return;
1820
1821 I915_WRITE(WM2_LP_ILK,
1822 WM2_LP_EN |
1823 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1824 (fbc_wm << WM1_LP_FBC_SHIFT) |
1825 (plane_wm << WM1_LP_SR_SHIFT) |
1826 cursor_wm);
1827
1828 /*
1829 * WM3 is unsupported on ILK, probably because we don't have latency
1830 * data for that power state
1831 */
1832}
1833
1fa61106 1834static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1835{
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1838 u32 val;
1839 int fbc_wm, plane_wm, cursor_wm;
1840 unsigned int enabled;
1841
1842 enabled = 0;
1843 if (g4x_compute_wm0(dev, 0,
1844 &sandybridge_display_wm_info, latency,
1845 &sandybridge_cursor_wm_info, latency,
1846 &plane_wm, &cursor_wm)) {
1847 val = I915_READ(WM0_PIPEA_ILK);
1848 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1849 I915_WRITE(WM0_PIPEA_ILK, val |
1850 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1851 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1852 " plane %d, " "cursor: %d\n",
1853 plane_wm, cursor_wm);
1854 enabled |= 1;
1855 }
1856
1857 if (g4x_compute_wm0(dev, 1,
1858 &sandybridge_display_wm_info, latency,
1859 &sandybridge_cursor_wm_info, latency,
1860 &plane_wm, &cursor_wm)) {
1861 val = I915_READ(WM0_PIPEB_ILK);
1862 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1863 I915_WRITE(WM0_PIPEB_ILK, val |
1864 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1865 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1866 " plane %d, cursor: %d\n",
1867 plane_wm, cursor_wm);
1868 enabled |= 2;
1869 }
1870
c43d0188
CW		 1871 /*
1872 * Calculate and update the self-refresh watermark only when one
1873 * display plane is used.
1874 *
1875 * SNB support 3 levels of watermark.
1876 *
1877 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1878 * and disabled in the descending order
1879 *
1880 */
1881 I915_WRITE(WM3_LP_ILK, 0);
1882 I915_WRITE(WM2_LP_ILK, 0);
1883 I915_WRITE(WM1_LP_ILK, 0);
1884
1885 if (!single_plane_enabled(enabled) ||
1886 dev_priv->sprite_scaling_enabled)
1887 return;
1888 enabled = ffs(enabled) - 1;
1889
1890 /* WM1 */
1891 if (!ironlake_compute_srwm(dev, 1, enabled,
1892 SNB_READ_WM1_LATENCY() * 500,
1893 &sandybridge_display_srwm_info,
1894 &sandybridge_cursor_srwm_info,
1895 &fbc_wm, &plane_wm, &cursor_wm))
1896 return;
1897
1898 I915_WRITE(WM1_LP_ILK,
1899 WM1_LP_SR_EN |
1900 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1901 (fbc_wm << WM1_LP_FBC_SHIFT) |
1902 (plane_wm << WM1_LP_SR_SHIFT) |
1903 cursor_wm);
1904
1905 /* WM2 */
1906 if (!ironlake_compute_srwm(dev, 2, enabled,
1907 SNB_READ_WM2_LATENCY() * 500,
1908 &sandybridge_display_srwm_info,
1909 &sandybridge_cursor_srwm_info,
1910 &fbc_wm, &plane_wm, &cursor_wm))
1911 return;
1912
1913 I915_WRITE(WM2_LP_ILK,
1914 WM2_LP_EN |
1915 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1916 (fbc_wm << WM1_LP_FBC_SHIFT) |
1917 (plane_wm << WM1_LP_SR_SHIFT) |
1918 cursor_wm);
1919
1920 /* WM3 */
1921 if (!ironlake_compute_srwm(dev, 3, enabled,
1922 SNB_READ_WM3_LATENCY() * 500,
1923 &sandybridge_display_srwm_info,
1924 &sandybridge_cursor_srwm_info,
1925 &fbc_wm, &plane_wm, &cursor_wm))
1926 return;
1927
1928 I915_WRITE(WM3_LP_ILK,
1929 WM3_LP_EN |
1930 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1931 (fbc_wm << WM1_LP_FBC_SHIFT) |
1932 (plane_wm << WM1_LP_SR_SHIFT) |
1933 cursor_wm);
1934}
1935
1936static void ivybridge_update_wm(struct drm_device *dev)
1937{
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1940 u32 val;
1941 int fbc_wm, plane_wm, cursor_wm;
1942 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1943 unsigned int enabled;
1944
1945 enabled = 0;
1946 if (g4x_compute_wm0(dev, 0,
1947 &sandybridge_display_wm_info, latency,
1948 &sandybridge_cursor_wm_info, latency,
1949 &plane_wm, &cursor_wm)) {
1950 val = I915_READ(WM0_PIPEA_ILK);
1951 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1952 I915_WRITE(WM0_PIPEA_ILK, val |
1953 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1954 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1955 " plane %d, " "cursor: %d\n",
1956 plane_wm, cursor_wm);
1957 enabled |= 1;
1958 }
1959
1960 if (g4x_compute_wm0(dev, 1,
1961 &sandybridge_display_wm_info, latency,
1962 &sandybridge_cursor_wm_info, latency,
1963 &plane_wm, &cursor_wm)) {
1964 val = I915_READ(WM0_PIPEB_ILK);
1965 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1966 I915_WRITE(WM0_PIPEB_ILK, val |
1967 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1968 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1969 " plane %d, cursor: %d\n",
1970 plane_wm, cursor_wm);
1971 enabled |= 2;
1972 }
1973
1974 if (g4x_compute_wm0(dev, 2,
b445e3b0
ED		 1975 &sandybridge_display_wm_info, latency,
1976 &sandybridge_cursor_wm_info, latency,
1977 &plane_wm, &cursor_wm)) {
1978 val = I915_READ(WM0_PIPEC_IVB);
1979 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1980 I915_WRITE(WM0_PIPEC_IVB, val |
1981 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1982 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1983 " plane %d, cursor: %d\n",
1984 plane_wm, cursor_wm);
1985 enabled |= 3;
1986 }
1987
1988 /*
1989 * Calculate and update the self-refresh watermark only when one
1990 * display plane is used.
1991 *
1992 * SNB support 3 levels of watermark.
1993 *
1994 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1995 * and disabled in the descending order
1996 *
1997 */
1998 I915_WRITE(WM3_LP_ILK, 0);
1999 I915_WRITE(WM2_LP_ILK, 0);
2000 I915_WRITE(WM1_LP_ILK, 0);
2001
2002 if (!single_plane_enabled(enabled) ||
2003 dev_priv->sprite_scaling_enabled)
2004 return;
2005 enabled = ffs(enabled) - 1;
2006
2007 /* WM1 */
2008 if (!ironlake_compute_srwm(dev, 1, enabled,
2009 SNB_READ_WM1_LATENCY() * 500,
2010 &sandybridge_display_srwm_info,
2011 &sandybridge_cursor_srwm_info,
2012 &fbc_wm, &plane_wm, &cursor_wm))
2013 return;
2014
2015 I915_WRITE(WM1_LP_ILK,
2016 WM1_LP_SR_EN |
2017 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2018 (fbc_wm << WM1_LP_FBC_SHIFT) |
2019 (plane_wm << WM1_LP_SR_SHIFT) |
2020 cursor_wm);
2021
2022 /* WM2 */
2023 if (!ironlake_compute_srwm(dev, 2, enabled,
2024 SNB_READ_WM2_LATENCY() * 500,
2025 &sandybridge_display_srwm_info,
2026 &sandybridge_cursor_srwm_info,
2027 &fbc_wm, &plane_wm, &cursor_wm))
2028 return;
2029
2030 I915_WRITE(WM2_LP_ILK,
2031 WM2_LP_EN |
2032 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2033 (fbc_wm << WM1_LP_FBC_SHIFT) |
2034 (plane_wm << WM1_LP_SR_SHIFT) |
2035 cursor_wm);
2036
c43d0188 2037 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2038 if (!ironlake_compute_srwm(dev, 3, enabled,
2039 SNB_READ_WM3_LATENCY() * 500,
2040 &sandybridge_display_srwm_info,
2041 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2042 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2043 !ironlake_compute_srwm(dev, 3, enabled,
2044 2 * SNB_READ_WM3_LATENCY() * 500,
2045 &sandybridge_display_srwm_info,
2046 &sandybridge_cursor_srwm_info,
2047 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2048 return;
2049
2050 I915_WRITE(WM3_LP_ILK,
2051 WM3_LP_EN |
2052 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2053 (fbc_wm << WM1_LP_FBC_SHIFT) |
2054 (plane_wm << WM1_LP_SR_SHIFT) |
2055 cursor_wm);
2056}
2057
1f8eeabf
ED		 2058static void
2059haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2060 struct drm_display_mode *mode)
2061{
2062 struct drm_i915_private *dev_priv = dev->dev_private;
2063 u32 temp;
2064
2065 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2066 temp &= ~PIPE_WM_LINETIME_MASK;
2067
2068 /* The WM are computed with base on how long it takes to fill a single
2069 * row at the given clock rate, multiplied by 8.
2070 * */
2071 temp |= PIPE_WM_LINETIME_TIME(
2072 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2073
2074 /* IPS watermarks are only used by pipe A, and are ignored by
2075 * pipes B and C. They are calculated similarly to the common
2076 * linetime values, except that we are using CD clock frequency
2077 * in MHz instead of pixel rate for the division.
2078 *
2079 * This is a placeholder for the IPS watermark calculation code.
2080 */
2081
2082 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2083}
2084
b445e3b0
ED		 2085static bool
2086sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2087 uint32_t sprite_width, int pixel_size,
2088 const struct intel_watermark_params *display,
2089 int display_latency_ns, int *sprite_wm)
2090{
2091 struct drm_crtc *crtc;
2092 int clock;
2093 int entries, tlb_miss;
2094
2095 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2096 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2097 *sprite_wm = display->guard_size;
2098 return false;
2099 }
2100
2101 clock = crtc->mode.clock;
2102
2103 /* Use the small buffer method to calculate the sprite watermark */
2104 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2105 tlb_miss = display->fifo_size*display->cacheline_size -
2106 sprite_width * 8;
2107 if (tlb_miss > 0)
2108 entries += tlb_miss;
2109 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2110 *sprite_wm = entries + display->guard_size;
2111 if (*sprite_wm > (int)display->max_wm)
2112 *sprite_wm = display->max_wm;
2113
2114 return true;
2115}
2116
2117static bool
2118sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2119 uint32_t sprite_width, int pixel_size,
2120 const struct intel_watermark_params *display,
2121 int latency_ns, int *sprite_wm)
2122{
2123 struct drm_crtc *crtc;
2124 unsigned long line_time_us;
2125 int clock;
2126 int line_count, line_size;
2127 int small, large;
2128 int entries;
2129
2130 if (!latency_ns) {
2131 *sprite_wm = 0;
2132 return false;
2133 }
2134
2135 crtc = intel_get_crtc_for_plane(dev, plane);
2136 clock = crtc->mode.clock;
2137 if (!clock) {
2138 *sprite_wm = 0;
2139 return false;
2140 }
2141
2142 line_time_us = (sprite_width * 1000) / clock;
2143 if (!line_time_us) {
2144 *sprite_wm = 0;
2145 return false;
2146 }
2147
2148 line_count = (latency_ns / line_time_us + 1000) / 1000;
2149 line_size = sprite_width * pixel_size;
2150
2151 /* Use the minimum of the small and large buffer method for primary */
2152 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2153 large = line_count * line_size;
2154
2155 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2156 *sprite_wm = entries + display->guard_size;
2157
2158 return *sprite_wm > 0x3ff ? false : true;
2159}
2160
1fa61106 2161static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 2162 uint32_t sprite_width, int pixel_size)
2163{
2164 struct drm_i915_private *dev_priv = dev->dev_private;
2165 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2166 u32 val;
2167 int sprite_wm, reg;
2168 int ret;
2169
2170 switch (pipe) {
2171 case 0:
2172 reg = WM0_PIPEA_ILK;
2173 break;
2174 case 1:
2175 reg = WM0_PIPEB_ILK;
2176 break;
2177 case 2:
2178 reg = WM0_PIPEC_IVB;
2179 break;
2180 default:
2181 return; /* bad pipe */
2182 }
2183
2184 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2185 &sandybridge_display_wm_info,
2186 latency, &sprite_wm);
2187 if (!ret) {
84f44ce7
VS		 2188 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2189 pipe_name(pipe));
b445e3b0
ED		 2190 return;
2191 }
2192
2193 val = I915_READ(reg);
2194 val &= ~WM0_PIPE_SPRITE_MASK;
2195 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2196 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2197
2198
2199 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2200 pixel_size,
2201 &sandybridge_display_srwm_info,
2202 SNB_READ_WM1_LATENCY() * 500,
2203 &sprite_wm);
2204 if (!ret) {
84f44ce7
VS		 2205 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2206 pipe_name(pipe));
b445e3b0
ED		 2207 return;
2208 }
2209 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2210
2211 /* Only IVB has two more LP watermarks for sprite */
2212 if (!IS_IVYBRIDGE(dev))
2213 return;
2214
2215 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2216 pixel_size,
2217 &sandybridge_display_srwm_info,
2218 SNB_READ_WM2_LATENCY() * 500,
2219 &sprite_wm);
2220 if (!ret) {
84f44ce7
VS		 2221 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2222 pipe_name(pipe));
b445e3b0
ED		 2223 return;
2224 }
2225 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2226
2227 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2228 pixel_size,
2229 &sandybridge_display_srwm_info,
2230 SNB_READ_WM3_LATENCY() * 500,
2231 &sprite_wm);
2232 if (!ret) {
84f44ce7
VS		 2233 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2234 pipe_name(pipe));
b445e3b0
ED		 2235 return;
2236 }
2237 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2238}
2239
2240/**
2241 * intel_update_watermarks - update FIFO watermark values based on current modes
2242 *
2243 * Calculate watermark values for the various WM regs based on current mode
2244 * and plane configuration.
2245 *
2246 * There are several cases to deal with here:
2247 * - normal (i.e. non-self-refresh)
2248 * - self-refresh (SR) mode
2249 * - lines are large relative to FIFO size (buffer can hold up to 2)
2250 * - lines are small relative to FIFO size (buffer can hold more than 2
2251 * lines), so need to account for TLB latency
2252 *
2253 * The normal calculation is:
2254 * watermark = dotclock * bytes per pixel * latency
2255 * where latency is platform & configuration dependent (we assume pessimal
2256 * values here).
2257 *
2258 * The SR calculation is:
2259 * watermark = (trunc(latency/line time)+1) * surface width *
2260 * bytes per pixel
2261 * where
2262 * line time = htotal / dotclock
2263 * surface width = hdisplay for normal plane and 64 for cursor
2264 * and latency is assumed to be high, as above.
2265 *
2266 * The final value programmed to the register should always be rounded up,
2267 * and include an extra 2 entries to account for clock crossings.
2268 *
2269 * We don't use the sprite, so we can ignore that. And on Crestline we have
2270 * to set the non-SR watermarks to 8.
2271 */
2272void intel_update_watermarks(struct drm_device *dev)
2273{
2274 struct drm_i915_private *dev_priv = dev->dev_private;
2275
2276 if (dev_priv->display.update_wm)
2277 dev_priv->display.update_wm(dev);
2278}
2279
1f8eeabf
ED		 2280void intel_update_linetime_watermarks(struct drm_device *dev,
2281 int pipe, struct drm_display_mode *mode)
2282{
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284
2285 if (dev_priv->display.update_linetime_wm)
2286 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2287}
2288
b445e3b0
ED		 2289void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2290 uint32_t sprite_width, int pixel_size)
2291{
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293
2294 if (dev_priv->display.update_sprite_wm)
2295 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2296 pixel_size);
2297}
2298
2b4e57bd
ED		 2299static struct drm_i915_gem_object *
2300intel_alloc_context_page(struct drm_device *dev)
2301{
2302 struct drm_i915_gem_object *ctx;
2303 int ret;
2304
2305 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2306
2307 ctx = i915_gem_alloc_object(dev, 4096);
2308 if (!ctx) {
2309 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2310 return NULL;
2311 }
2312
86a1ee26 2313 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2314 if (ret) {
2315 DRM_ERROR("failed to pin power context: %d\n", ret);
2316 goto err_unref;
2317 }
2318
2319 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2320 if (ret) {
2321 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2322 goto err_unpin;
2323 }
2324
2325 return ctx;
2326
2327err_unpin:
2328 i915_gem_object_unpin(ctx);
2329err_unref:
2330 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2331 return NULL;
2332}
2333
9270388e
DV		 2334/**
2335 * Lock protecting IPS related data structures
9270388e
DV		 2336 */
2337DEFINE_SPINLOCK(mchdev_lock);
2338
2339/* Global for IPS driver to get at the current i915 device. Protected by
2340 * mchdev_lock. */
2341static struct drm_i915_private *i915_mch_dev;
2342
2b4e57bd
ED		 2343bool ironlake_set_drps(struct drm_device *dev, u8 val)
2344{
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346 u16 rgvswctl;
2347
9270388e
DV		 2348 assert_spin_locked(&mchdev_lock);
2349
2b4e57bd
ED		 2350 rgvswctl = I915_READ16(MEMSWCTL);
2351 if (rgvswctl & MEMCTL_CMD_STS) {
2352 DRM_DEBUG("gpu busy, RCS change rejected\n");
2353 return false; /* still busy with another command */
2354 }
2355
2356 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2357 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2358 I915_WRITE16(MEMSWCTL, rgvswctl);
2359 POSTING_READ16(MEMSWCTL);
2360
2361 rgvswctl |= MEMCTL_CMD_STS;
2362 I915_WRITE16(MEMSWCTL, rgvswctl);
2363
2364 return true;
2365}
2366
8090c6b9 2367static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2368{
2369 struct drm_i915_private *dev_priv = dev->dev_private;
2370 u32 rgvmodectl = I915_READ(MEMMODECTL);
2371 u8 fmax, fmin, fstart, vstart;
2372
9270388e
DV		 2373 spin_lock_irq(&mchdev_lock);
2374
2b4e57bd
ED		 2375 /* Enable temp reporting */
2376 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2377 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2378
2379 /* 100ms RC evaluation intervals */
2380 I915_WRITE(RCUPEI, 100000);
2381 I915_WRITE(RCDNEI, 100000);
2382
2383 /* Set max/min thresholds to 90ms and 80ms respectively */
2384 I915_WRITE(RCBMAXAVG, 90000);
2385 I915_WRITE(RCBMINAVG, 80000);
2386
2387 I915_WRITE(MEMIHYST, 1);
2388
2389 /* Set up min, max, and cur for interrupt handling */
2390 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2391 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2392 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2393 MEMMODE_FSTART_SHIFT;
2394
2395 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2396 PXVFREQ_PX_SHIFT;
2397
20e4d407
DV		 2398 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2399 dev_priv->ips.fstart = fstart;
2b4e57bd 2400
20e4d407
DV		 2401 dev_priv->ips.max_delay = fstart;
2402 dev_priv->ips.min_delay = fmin;
2403 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2404
2405 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2406 fmax, fmin, fstart);
2407
2408 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2409
2410 /*
2411 * Interrupts will be enabled in ironlake_irq_postinstall
2412 */
2413
2414 I915_WRITE(VIDSTART, vstart);
2415 POSTING_READ(VIDSTART);
2416
2417 rgvmodectl |= MEMMODE_SWMODE_EN;
2418 I915_WRITE(MEMMODECTL, rgvmodectl);
2419
9270388e 2420 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2421 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2422 mdelay(1);
2b4e57bd
ED		 2423
2424 ironlake_set_drps(dev, fstart);
2425
20e4d407 2426 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2427 I915_READ(0x112e0);
20e4d407
DV		 2428 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2429 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2430 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2431
2432 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2433}
2434
8090c6b9 2435static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2436{
2437 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2438 u16 rgvswctl;
2439
2440 spin_lock_irq(&mchdev_lock);
2441
2442 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2443
2444 /* Ack interrupts, disable EFC interrupt */
2445 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2446 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2447 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2448 I915_WRITE(DEIIR, DE_PCU_EVENT);
2449 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2450
2451 /* Go back to the starting frequency */
20e4d407 2452 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2453 mdelay(1);
2b4e57bd
ED		 2454 rgvswctl |= MEMCTL_CMD_STS;
2455 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2456 mdelay(1);
2b4e57bd 2457
9270388e 2458 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2459}
2460
acbe9475
DV		 2461/* There's a funny hw issue where the hw returns all 0 when reading from
2462 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2463 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2464 * all limits and the gpu stuck at whatever frequency it is at atm).
2465 */
65bccb5c 2466static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2467{
7b9e0ae6 2468 u32 limits;
2b4e57bd 2469
7b9e0ae6 2470 limits = 0;
c6a828d3
DV		 2471
2472 if (*val >= dev_priv->rps.max_delay)
2473 *val = dev_priv->rps.max_delay;
2474 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2475
2476 /* Only set the down limit when we've reached the lowest level to avoid
2477 * getting more interrupts, otherwise leave this clear. This prevents a
2478 * race in the hw when coming out of rc6: There's a tiny window where
2479 * the hw runs at the minimal clock before selecting the desired
2480 * frequency, if the down threshold expires in that window we will not
2481 * receive a down interrupt. */
c6a828d3
DV		 2482 if (*val <= dev_priv->rps.min_delay) {
2483 *val = dev_priv->rps.min_delay;
2484 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2485 }
2486
2487 return limits;
2488}
2489
2490void gen6_set_rps(struct drm_device *dev, u8 val)
2491{
2492 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2493 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2494
4fc688ce 2495 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2496 WARN_ON(val > dev_priv->rps.max_delay);
2497 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2498
c6a828d3 2499 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2500 return;
2501
92bd1bf0
RV		 2502 if (IS_HASWELL(dev))
2503 I915_WRITE(GEN6_RPNSWREQ,
2504 HSW_FREQUENCY(val));
2505 else
2506 I915_WRITE(GEN6_RPNSWREQ,
2507 GEN6_FREQUENCY(val) |
2508 GEN6_OFFSET(0) |
2509 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 2510
2511 /* Make sure we continue to get interrupts
2512 * until we hit the minimum or maximum frequencies.
2513 */
2514 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2515
d5570a72
BW		 2516 POSTING_READ(GEN6_RPNSWREQ);
2517
c6a828d3 2518 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2519
2520 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2521}
2522
0a073b84
JB		 2523void valleyview_set_rps(struct drm_device *dev, u8 val)
2524{
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 unsigned long timeout = jiffies + msecs_to_jiffies(10);
2527 u32 limits = gen6_rps_limits(dev_priv, &val);
2528 u32 pval;
2529
2530 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2531 WARN_ON(val > dev_priv->rps.max_delay);
2532 WARN_ON(val < dev_priv->rps.min_delay);
2533
2534 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2535 vlv_gpu_freq(dev_priv->mem_freq,
2536 dev_priv->rps.cur_delay),
2537 vlv_gpu_freq(dev_priv->mem_freq, val));
2538
2539 if (val == dev_priv->rps.cur_delay)
2540 return;
2541
2542 valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2543
2544 do {
2545 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2546 if (time_after(jiffies, timeout)) {
2547 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2548 break;
2549 }
2550 udelay(10);
2551 } while (pval & 1);
2552
2553 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2554 if ((pval >> 8) != val)
2555 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2556 val, pval >> 8);
2557
2558 /* Make sure we continue to get interrupts
2559 * until we hit the minimum or maximum frequencies.
2560 */
2561 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2562
2563 dev_priv->rps.cur_delay = pval >> 8;
2564
2565 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2566}
2567
2568
8090c6b9 2569static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2570{
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572
88509484 2573 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2574 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2575 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2576 I915_WRITE(GEN6_PMIER, 0);
2577 /* Complete PM interrupt masking here doesn't race with the rps work
2578 * item again unmasking PM interrupts because that is using a different
2579 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2580 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2581
c6a828d3
DV		 2582 spin_lock_irq(&dev_priv->rps.lock);
2583 dev_priv->rps.pm_iir = 0;
2584 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2585
2586 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2587}
2588
d20d4f0c
JB		 2589static void valleyview_disable_rps(struct drm_device *dev)
2590{
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592
2593 I915_WRITE(GEN6_RC_CONTROL, 0);
2594 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2595 I915_WRITE(GEN6_PMIER, 0);
2596 /* Complete PM interrupt masking here doesn't race with the rps work
2597 * item again unmasking PM interrupts because that is using a different
2598 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2599 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2600
2601 spin_lock_irq(&dev_priv->rps.lock);
2602 dev_priv->rps.pm_iir = 0;
2603 spin_unlock_irq(&dev_priv->rps.lock);
2604
2605 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
c9cddffc
JB		 2606
2607 if (dev_priv->vlv_pctx) {
2608 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2609 dev_priv->vlv_pctx = NULL;
2610 }
d20d4f0c
JB		 2611}
2612
2b4e57bd
ED		 2613int intel_enable_rc6(const struct drm_device *dev)
2614{
456470eb 2615 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2616 if (i915_enable_rc6 >= 0)
2617 return i915_enable_rc6;
2618
6567d748
CW		 2619 /* Disable RC6 on Ironlake */
2620 if (INTEL_INFO(dev)->gen == 5)
2621 return 0;
2b4e57bd 2622
456470eb
DV		 2623 if (IS_HASWELL(dev)) {
2624 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2625 return INTEL_RC6_ENABLE;
456470eb 2626 }
2b4e57bd 2627
456470eb 2628 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2629 if (INTEL_INFO(dev)->gen == 6) {
2630 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2631 return INTEL_RC6_ENABLE;
2632 }
456470eb 2633
2b4e57bd
ED		 2634 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2635 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2636}
2637
79f5b2c7 2638static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2639{
79f5b2c7 2640 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2641 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2642 u32 rp_state_cap;
2643 u32 gt_perf_status;
31643d54 2644 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 2645 u32 gtfifodbg;
2b4e57bd 2646 int rc6_mode;
42c0526c 2647 int i, ret;
2b4e57bd 2648
4fc688ce 2649 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2650
2b4e57bd
ED		 2651 /* Here begins a magic sequence of register writes to enable
2652 * auto-downclocking.
2653 *
2654 * Perhaps there might be some value in exposing these to
2655 * userspace...
2656 */
2657 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2658
2659 /* Clear the DBG now so we don't confuse earlier errors */
2660 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2661 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2662 I915_WRITE(GTFIFODBG, gtfifodbg);
2663 }
2664
2665 gen6_gt_force_wake_get(dev_priv);
2666
7b9e0ae6
CW		 2667 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2668 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2669
31c77388
BW		 2670 /* In units of 50MHz */
2671 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 2672 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2673 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2674
2b4e57bd
ED		 2675 /* disable the counters and set deterministic thresholds */
2676 I915_WRITE(GEN6_RC_CONTROL, 0);
2677
2678 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2679 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2680 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2681 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2682 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2683
b4519513
CW		 2684 for_each_ring(ring, dev_priv, i)
2685 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2686
2687 I915_WRITE(GEN6_RC_SLEEP, 0);
2688 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2689 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 2690 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 2691 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2692
5a7dc92a 2693 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2694 rc6_mode = intel_enable_rc6(dev_priv->dev);
2695 if (rc6_mode & INTEL_RC6_ENABLE)
2696 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2697
5a7dc92a
ED		 2698 /* We don't use those on Haswell */
2699 if (!IS_HASWELL(dev)) {
2700 if (rc6_mode & INTEL_RC6p_ENABLE)
2701 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2702
5a7dc92a
ED		 2703 if (rc6_mode & INTEL_RC6pp_ENABLE)
2704 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2705 }
2b4e57bd
ED		 2706
2707 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2708 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2709 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2710 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2711
2712 I915_WRITE(GEN6_RC_CONTROL,
2713 rc6_mask |
2714 GEN6_RC_CTL_EI_MODE(1) |
2715 GEN6_RC_CTL_HW_ENABLE);
2716
92bd1bf0
RV		 2717 if (IS_HASWELL(dev)) {
2718 I915_WRITE(GEN6_RPNSWREQ,
2719 HSW_FREQUENCY(10));
2720 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2721 HSW_FREQUENCY(12));
2722 } else {
2723 I915_WRITE(GEN6_RPNSWREQ,
2724 GEN6_FREQUENCY(10) |
2725 GEN6_OFFSET(0) |
2726 GEN6_AGGRESSIVE_TURBO);
2727 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2728 GEN6_FREQUENCY(12));
2729 }
2b4e57bd
ED		 2730
2731 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2732 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2733 dev_priv->rps.max_delay << 24 |
2734 dev_priv->rps.min_delay << 16);
5a7dc92a 2735
1ee9ae32
DV		 2736 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2737 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2738 I915_WRITE(GEN6_RP_UP_EI, 66000);
2739 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2740
2b4e57bd
ED		 2741 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2742 I915_WRITE(GEN6_RP_CONTROL,
2743 GEN6_RP_MEDIA_TURBO |
89ba829e 2744 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2745 GEN6_RP_MEDIA_IS_GFX |
2746 GEN6_RP_ENABLE |
2747 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2748 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 2749
42c0526c 2750 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
fec46b5e 2751 if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
42c0526c
BW		 2752 pcu_mbox = 0;
2753 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 2754 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 2755 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 2756 (dev_priv->rps.max_delay & 0xff) * 50,
2757 (pcu_mbox & 0xff) * 50);
31c77388 2758 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 2759 }
2760 } else {
2761 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 2762 }
2763
7b9e0ae6 2764 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2765
2766 /* requires MSI enabled */
ff928261 2767 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2768 spin_lock_irq(&dev_priv->rps.lock);
2769 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2770 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2771 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2772 /* enable all PM interrupts */
2773 I915_WRITE(GEN6_PMINTRMSK, 0);
2774
31643d54
BW		 2775 rc6vids = 0;
2776 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2777 if (IS_GEN6(dev) && ret) {
2778 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2779 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2780 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2781 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2782 rc6vids &= 0xffff00;
2783 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2784 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2785 if (ret)
2786 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2787 }
2788
2b4e57bd 2789 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2790}
2791
79f5b2c7 2792static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2793{
79f5b2c7 2794 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 2795 int min_freq = 15;
3ebecd07
CW		 2796 unsigned int gpu_freq;
2797 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 2798 int scaling_factor = 180;
2799
4fc688ce 2800 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2801
2b4e57bd
ED		 2802 max_ia_freq = cpufreq_quick_get_max(0);
2803 /*
2804 * Default to measured freq if none found, PCU will ensure we don't go
2805 * over
2806 */
2807 if (!max_ia_freq)
2808 max_ia_freq = tsc_khz;
2809
2810 /* Convert from kHz to MHz */
2811 max_ia_freq /= 1000;
2812
3ebecd07
CW		 2813 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2814 /* convert DDR frequency from units of 133.3MHz to bandwidth */
2815 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2816
2b4e57bd
ED		 2817 /*
2818 * For each potential GPU frequency, load a ring frequency we'd like
2819 * to use for memory access. We do this by specifying the IA frequency
2820 * the PCU should use as a reference to determine the ring frequency.
2821 */
c6a828d3 2822 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2823 gpu_freq--) {
c6a828d3 2824 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 2825 unsigned int ia_freq = 0, ring_freq = 0;
2826
2827 if (IS_HASWELL(dev)) {
2828 ring_freq = (gpu_freq * 5 + 3) / 4;
2829 ring_freq = max(min_ring_freq, ring_freq);
2830 /* leave ia_freq as the default, chosen by cpufreq */
2831 } else {
2832 /* On older processors, there is no separate ring
2833 * clock domain, so in order to boost the bandwidth
2834 * of the ring, we need to upclock the CPU (ia_freq).
2835 *
2836 * For GPU frequencies less than 750MHz,
2837 * just use the lowest ring freq.
2838 */
2839 if (gpu_freq < min_freq)
2840 ia_freq = 800;
2841 else
2842 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2843 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2844 }
2b4e57bd 2845
42c0526c
BW		 2846 sandybridge_pcode_write(dev_priv,
2847 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 2848 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2849 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2850 gpu_freq);
2b4e57bd 2851 }
2b4e57bd
ED		 2852}
2853
0a073b84
JB		 2854int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2855{
2856 u32 val, rp0;
2857
2858 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2859
2860 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2861 /* Clamp to max */
2862 rp0 = min_t(u32, rp0, 0xea);
2863
2864 return rp0;
2865}
2866
2867static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2868{
2869 u32 val, rpe;
2870
2871 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2872 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2873 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2874 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2875
2876 return rpe;
2877}
2878
2879int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2880{
2881 u32 val;
2882
2883 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2884
2885 return val & 0xff;
2886}
2887
52ceb908
JB		 2888static void vlv_rps_timer_work(struct work_struct *work)
2889{
2890 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2891 rps.vlv_work.work);
2892
2893 /*
2894 * Timer fired, we must be idle. Drop to min voltage state.
2895 * Note: we use RPe here since it should match the
2896 * Vmin we were shooting for. That should give us better
2897 * perf when we come back out of RC6 than if we used the
2898 * min freq available.
2899 */
2900 mutex_lock(&dev_priv->rps.hw_lock);
2901 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2902 mutex_unlock(&dev_priv->rps.hw_lock);
2903}
2904
c9cddffc
JB		 2905static void valleyview_setup_pctx(struct drm_device *dev)
2906{
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 struct drm_i915_gem_object *pctx;
2909 unsigned long pctx_paddr;
2910 u32 pcbr;
2911 int pctx_size = 24*1024;
2912
2913 pcbr = I915_READ(VLV_PCBR);
2914 if (pcbr) {
2915 /* BIOS set it up already, grab the pre-alloc'd space */
2916 int pcbr_offset;
2917
2918 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2919 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2920 pcbr_offset,
3727d55e 2921 -1,
c9cddffc
JB		 2922 pctx_size);
2923 goto out;
2924 }
2925
2926 /*
2927 * From the Gunit register HAS:
2928 * The Gfx driver is expected to program this register and ensure
2929 * proper allocation within Gfx stolen memory. For example, this
2930 * register should be programmed such than the PCBR range does not
2931 * overlap with other ranges, such as the frame buffer, protected
2932 * memory, or any other relevant ranges.
2933 */
2934 pctx = i915_gem_object_create_stolen(dev, pctx_size);
2935 if (!pctx) {
2936 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2937 return;
2938 }
2939
2940 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2941 I915_WRITE(VLV_PCBR, pctx_paddr);
2942
2943out:
2944 dev_priv->vlv_pctx = pctx;
2945}
2946
0a073b84
JB		 2947static void valleyview_enable_rps(struct drm_device *dev)
2948{
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_ring_buffer *ring;
2951 u32 gtfifodbg, val, rpe;
2952 int i;
2953
2954 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2955
2956 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2957 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2958 I915_WRITE(GTFIFODBG, gtfifodbg);
2959 }
2960
c9cddffc
JB		 2961 valleyview_setup_pctx(dev);
2962
0a073b84
JB		 2963 gen6_gt_force_wake_get(dev_priv);
2964
2965 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2966 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2967 I915_WRITE(GEN6_RP_UP_EI, 66000);
2968 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2969
2970 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2971
2972 I915_WRITE(GEN6_RP_CONTROL,
2973 GEN6_RP_MEDIA_TURBO |
2974 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2975 GEN6_RP_MEDIA_IS_GFX |
2976 GEN6_RP_ENABLE |
2977 GEN6_RP_UP_BUSY_AVG |
2978 GEN6_RP_DOWN_IDLE_CONT);
2979
2980 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
2981 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2982 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2983
2984 for_each_ring(ring, dev_priv, i)
2985 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2986
2987 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
2988
2989 /* allows RC6 residency counter to work */
2990 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
2991 I915_WRITE(GEN6_RC_CONTROL,
2992 GEN7_RC_CTL_TO_MODE);
2993
2994 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
2445966e
JB		 2995 switch ((val >> 6) & 3) {
2996 case 0:
2997 case 1:
2998 dev_priv->mem_freq = 800;
2999 break;
3000 case 2:
3001 dev_priv->mem_freq = 1066;
3002 break;
3003 case 3:
3004 dev_priv->mem_freq = 1333;
3005 break;
3006 }
0a073b84
JB		 3007 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3008
3009 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3010 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3011
3012 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3013 vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3014 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3015
3016 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3017 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3018 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3019 dev_priv->rps.max_delay));
3020
3021 rpe = valleyview_rps_rpe_freq(dev_priv);
3022 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3023 vlv_gpu_freq(dev_priv->mem_freq, rpe));
52ceb908 3024 dev_priv->rps.rpe_delay = rpe;
0a073b84
JB		 3025
3026 val = valleyview_rps_min_freq(dev_priv);
3027 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3028 val));
3029 dev_priv->rps.min_delay = val;
3030
3031 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3032 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3033
52ceb908
JB		 3034 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3035
0a073b84
JB		 3036 valleyview_set_rps(dev_priv->dev, rpe);
3037
3038 /* requires MSI enabled */
3039 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3040 spin_lock_irq(&dev_priv->rps.lock);
3041 WARN_ON(dev_priv->rps.pm_iir != 0);
3042 I915_WRITE(GEN6_PMIMR, 0);
3043 spin_unlock_irq(&dev_priv->rps.lock);
3044 /* enable all PM interrupts */
3045 I915_WRITE(GEN6_PMINTRMSK, 0);
3046
3047 gen6_gt_force_wake_put(dev_priv);
3048}
3049
930ebb46 3050void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3051{
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053
3e373948
DV		 3054 if (dev_priv->ips.renderctx) {
3055 i915_gem_object_unpin(dev_priv->ips.renderctx);
3056 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3057 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3058 }
3059
3e373948
DV		 3060 if (dev_priv->ips.pwrctx) {
3061 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3062 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3063 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3064 }
3065}
3066
930ebb46 3067static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3068{
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070
3071 if (I915_READ(PWRCTXA)) {
3072 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3073 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3074 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3075 50);
3076
3077 I915_WRITE(PWRCTXA, 0);
3078 POSTING_READ(PWRCTXA);
3079
3080 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3081 POSTING_READ(RSTDBYCTL);
3082 }
2b4e57bd
ED		 3083}
3084
3085static int ironlake_setup_rc6(struct drm_device *dev)
3086{
3087 struct drm_i915_private *dev_priv = dev->dev_private;
3088
3e373948
DV		 3089 if (dev_priv->ips.renderctx == NULL)
3090 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3091 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3092 return -ENOMEM;
3093
3e373948
DV		 3094 if (dev_priv->ips.pwrctx == NULL)
3095 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3096 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3097 ironlake_teardown_rc6(dev);
3098 return -ENOMEM;
3099 }
3100
3101 return 0;
3102}
3103
930ebb46 3104static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3105{
3106 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3107 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3108 bool was_interruptible;
2b4e57bd
ED		 3109 int ret;
3110
3111 /* rc6 disabled by default due to repeated reports of hanging during
3112 * boot and resume.
3113 */
3114 if (!intel_enable_rc6(dev))
3115 return;
3116
79f5b2c7
DV		 3117 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3118
2b4e57bd 3119 ret = ironlake_setup_rc6(dev);
79f5b2c7 3120 if (ret)
2b4e57bd 3121 return;
2b4e57bd 3122
3e960501
CW		 3123 was_interruptible = dev_priv->mm.interruptible;
3124 dev_priv->mm.interruptible = false;
3125
2b4e57bd
ED		 3126 /*
3127 * GPU can automatically power down the render unit if given a page
3128 * to save state.
3129 */
6d90c952 3130 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3131 if (ret) {
3132 ironlake_teardown_rc6(dev);
3e960501 3133 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3134 return;
3135 }
3136
6d90c952
DV		 3137 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3138 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 3139 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 3140 MI_MM_SPACE_GTT |
3141 MI_SAVE_EXT_STATE_EN |
3142 MI_RESTORE_EXT_STATE_EN |
3143 MI_RESTORE_INHIBIT);
3144 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3145 intel_ring_emit(ring, MI_NOOP);
3146 intel_ring_emit(ring, MI_FLUSH);
3147 intel_ring_advance(ring);
2b4e57bd
ED		 3148
3149 /*
3150 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3151 * does an implicit flush, combined with MI_FLUSH above, it should be
3152 * safe to assume that renderctx is valid
3153 */
3e960501
CW		 3154 ret = intel_ring_idle(ring);
3155 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3156 if (ret) {
def27a58 3157 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3158 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3159 return;
3160 }
3161
3e373948 3162 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 3163 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3164}
3165
dde18883
ED		 3166static unsigned long intel_pxfreq(u32 vidfreq)
3167{
3168 unsigned long freq;
3169 int div = (vidfreq & 0x3f0000) >> 16;
3170 int post = (vidfreq & 0x3000) >> 12;
3171 int pre = (vidfreq & 0x7);
3172
3173 if (!pre)
3174 return 0;
3175
3176 freq = ((div * 133333) / ((1<<post) * pre));
3177
3178 return freq;
3179}
3180
eb48eb00
DV		 3181static const struct cparams {
3182 u16 i;
3183 u16 t;
3184 u16 m;
3185 u16 c;
3186} cparams[] = {
3187 { 1, 1333, 301, 28664 },
3188 { 1, 1066, 294, 24460 },
3189 { 1, 800, 294, 25192 },
3190 { 0, 1333, 276, 27605 },
3191 { 0, 1066, 276, 27605 },
3192 { 0, 800, 231, 23784 },
3193};
3194
f531dcb2 3195static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3196{
3197 u64 total_count, diff, ret;
3198 u32 count1, count2, count3, m = 0, c = 0;
3199 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3200 int i;
3201
02d71956
DV		 3202 assert_spin_locked(&mchdev_lock);
3203
20e4d407 3204 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3205
3206 /* Prevent division-by-zero if we are asking too fast.
3207 * Also, we don't get interesting results if we are polling
3208 * faster than once in 10ms, so just return the saved value
3209 * in such cases.
3210 */
3211 if (diff1 <= 10)
20e4d407 3212 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3213
3214 count1 = I915_READ(DMIEC);
3215 count2 = I915_READ(DDREC);
3216 count3 = I915_READ(CSIEC);
3217
3218 total_count = count1 + count2 + count3;
3219
3220 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3221 if (total_count < dev_priv->ips.last_count1) {
3222 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3223 diff += total_count;
3224 } else {
20e4d407 3225 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3226 }
3227
3228 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3229 if (cparams[i].i == dev_priv->ips.c_m &&
3230 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3231 m = cparams[i].m;
3232 c = cparams[i].c;
3233 break;
3234 }
3235 }
3236
3237 diff = div_u64(diff, diff1);
3238 ret = ((m * diff) + c);
3239 ret = div_u64(ret, 10);
3240
20e4d407
DV		 3241 dev_priv->ips.last_count1 = total_count;
3242 dev_priv->ips.last_time1 = now;
eb48eb00 3243
20e4d407 3244 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3245
3246 return ret;
3247}
3248
f531dcb2
CW		 3249unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3250{
3251 unsigned long val;
3252
3253 if (dev_priv->info->gen != 5)
3254 return 0;
3255
3256 spin_lock_irq(&mchdev_lock);
3257
3258 val = __i915_chipset_val(dev_priv);
3259
3260 spin_unlock_irq(&mchdev_lock);
3261
3262 return val;
3263}
3264
eb48eb00
DV		 3265unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3266{
3267 unsigned long m, x, b;
3268 u32 tsfs;
3269
3270 tsfs = I915_READ(TSFS);
3271
3272 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3273 x = I915_READ8(TR1);
3274
3275 b = tsfs & TSFS_INTR_MASK;
3276
3277 return ((m * x) / 127) - b;
3278}
3279
3280static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3281{
3282 static const struct v_table {
3283 u16 vd; /* in .1 mil */
3284 u16 vm; /* in .1 mil */
3285 } v_table[] = {
3286 { 0, 0, },
3287 { 375, 0, },
3288 { 500, 0, },
3289 { 625, 0, },
3290 { 750, 0, },
3291 { 875, 0, },
3292 { 1000, 0, },
3293 { 1125, 0, },
3294 { 4125, 3000, },
3295 { 4125, 3000, },
3296 { 4125, 3000, },
3297 { 4125, 3000, },
3298 { 4125, 3000, },
3299 { 4125, 3000, },
3300 { 4125, 3000, },
3301 { 4125, 3000, },
3302 { 4125, 3000, },
3303 { 4125, 3000, },
3304 { 4125, 3000, },
3305 { 4125, 3000, },
3306 { 4125, 3000, },
3307 { 4125, 3000, },
3308 { 4125, 3000, },
3309 { 4125, 3000, },
3310 { 4125, 3000, },
3311 { 4125, 3000, },
3312 { 4125, 3000, },
3313 { 4125, 3000, },
3314 { 4125, 3000, },
3315 { 4125, 3000, },
3316 { 4125, 3000, },
3317 { 4125, 3000, },
3318 { 4250, 3125, },
3319 { 4375, 3250, },
3320 { 4500, 3375, },
3321 { 4625, 3500, },
3322 { 4750, 3625, },
3323 { 4875, 3750, },
3324 { 5000, 3875, },
3325 { 5125, 4000, },
3326 { 5250, 4125, },
3327 { 5375, 4250, },
3328 { 5500, 4375, },
3329 { 5625, 4500, },
3330 { 5750, 4625, },
3331 { 5875, 4750, },
3332 { 6000, 4875, },
3333 { 6125, 5000, },
3334 { 6250, 5125, },
3335 { 6375, 5250, },
3336 { 6500, 5375, },
3337 { 6625, 5500, },
3338 { 6750, 5625, },
3339 { 6875, 5750, },
3340 { 7000, 5875, },
3341 { 7125, 6000, },
3342 { 7250, 6125, },
3343 { 7375, 6250, },
3344 { 7500, 6375, },
3345 { 7625, 6500, },
3346 { 7750, 6625, },
3347 { 7875, 6750, },
3348 { 8000, 6875, },
3349 { 8125, 7000, },
3350 { 8250, 7125, },
3351 { 8375, 7250, },
3352 { 8500, 7375, },
3353 { 8625, 7500, },
3354 { 8750, 7625, },
3355 { 8875, 7750, },
3356 { 9000, 7875, },
3357 { 9125, 8000, },
3358 { 9250, 8125, },
3359 { 9375, 8250, },
3360 { 9500, 8375, },
3361 { 9625, 8500, },
3362 { 9750, 8625, },
3363 { 9875, 8750, },
3364 { 10000, 8875, },
3365 { 10125, 9000, },
3366 { 10250, 9125, },
3367 { 10375, 9250, },
3368 { 10500, 9375, },
3369 { 10625, 9500, },
3370 { 10750, 9625, },
3371 { 10875, 9750, },
3372 { 11000, 9875, },
3373 { 11125, 10000, },
3374 { 11250, 10125, },
3375 { 11375, 10250, },
3376 { 11500, 10375, },
3377 { 11625, 10500, },
3378 { 11750, 10625, },
3379 { 11875, 10750, },
3380 { 12000, 10875, },
3381 { 12125, 11000, },
3382 { 12250, 11125, },
3383 { 12375, 11250, },
3384 { 12500, 11375, },
3385 { 12625, 11500, },
3386 { 12750, 11625, },
3387 { 12875, 11750, },
3388 { 13000, 11875, },
3389 { 13125, 12000, },
3390 { 13250, 12125, },
3391 { 13375, 12250, },
3392 { 13500, 12375, },
3393 { 13625, 12500, },
3394 { 13750, 12625, },
3395 { 13875, 12750, },
3396 { 14000, 12875, },
3397 { 14125, 13000, },
3398 { 14250, 13125, },
3399 { 14375, 13250, },
3400 { 14500, 13375, },
3401 { 14625, 13500, },
3402 { 14750, 13625, },
3403 { 14875, 13750, },
3404 { 15000, 13875, },
3405 { 15125, 14000, },
3406 { 15250, 14125, },
3407 { 15375, 14250, },
3408 { 15500, 14375, },
3409 { 15625, 14500, },
3410 { 15750, 14625, },
3411 { 15875, 14750, },
3412 { 16000, 14875, },
3413 { 16125, 15000, },
3414 };
3415 if (dev_priv->info->is_mobile)
3416 return v_table[pxvid].vm;
3417 else
3418 return v_table[pxvid].vd;
3419}
3420
02d71956 3421static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3422{
3423 struct timespec now, diff1;
3424 u64 diff;
3425 unsigned long diffms;
3426 u32 count;
3427
02d71956 3428 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3429
3430 getrawmonotonic(&now);
20e4d407 3431 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3432
3433 /* Don't divide by 0 */
3434 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3435 if (!diffms)
3436 return;
3437
3438 count = I915_READ(GFXEC);
3439
20e4d407
DV		 3440 if (count < dev_priv->ips.last_count2) {
3441 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 3442 diff += count;
3443 } else {
20e4d407 3444 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 3445 }
3446
20e4d407
DV		 3447 dev_priv->ips.last_count2 = count;
3448 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 3449
3450 /* More magic constants... */
3451 diff = diff * 1181;
3452 diff = div_u64(diff, diffms * 10);
20e4d407 3453 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3454}
3455
02d71956
DV		 3456void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3457{
3458 if (dev_priv->info->gen != 5)
3459 return;
3460
9270388e 3461 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3462
3463 __i915_update_gfx_val(dev_priv);
3464
9270388e 3465 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3466}
3467
f531dcb2 3468static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3469{
3470 unsigned long t, corr, state1, corr2, state2;
3471 u32 pxvid, ext_v;
3472
02d71956
DV		 3473 assert_spin_locked(&mchdev_lock);
3474
c6a828d3 3475 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3476 pxvid = (pxvid >> 24) & 0x7f;
3477 ext_v = pvid_to_extvid(dev_priv, pxvid);
3478
3479 state1 = ext_v;
3480
3481 t = i915_mch_val(dev_priv);
3482
3483 /* Revel in the empirically derived constants */
3484
3485 /* Correction factor in 1/100000 units */
3486 if (t > 80)
3487 corr = ((t * 2349) + 135940);
3488 else if (t >= 50)
3489 corr = ((t * 964) + 29317);
3490 else /* < 50 */
3491 corr = ((t * 301) + 1004);
3492
3493 corr = corr * ((150142 * state1) / 10000 - 78642);
3494 corr /= 100000;
20e4d407 3495 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3496
3497 state2 = (corr2 * state1) / 10000;
3498 state2 /= 100; /* convert to mW */
3499
02d71956 3500 __i915_update_gfx_val(dev_priv);
eb48eb00 3501
20e4d407 3502 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3503}
3504
f531dcb2
CW		 3505unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3506{
3507 unsigned long val;
3508
3509 if (dev_priv->info->gen != 5)
3510 return 0;
3511
3512 spin_lock_irq(&mchdev_lock);
3513
3514 val = __i915_gfx_val(dev_priv);
3515
3516 spin_unlock_irq(&mchdev_lock);
3517
3518 return val;
3519}
3520
eb48eb00
DV		 3521/**
3522 * i915_read_mch_val - return value for IPS use
3523 *
3524 * Calculate and return a value for the IPS driver to use when deciding whether
3525 * we have thermal and power headroom to increase CPU or GPU power budget.
3526 */
3527unsigned long i915_read_mch_val(void)
3528{
3529 struct drm_i915_private *dev_priv;
3530 unsigned long chipset_val, graphics_val, ret = 0;
3531
9270388e 3532 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3533 if (!i915_mch_dev)
3534 goto out_unlock;
3535 dev_priv = i915_mch_dev;
3536
f531dcb2
CW		 3537 chipset_val = __i915_chipset_val(dev_priv);
3538 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3539
3540 ret = chipset_val + graphics_val;
3541
3542out_unlock:
9270388e 3543 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3544
3545 return ret;
3546}
3547EXPORT_SYMBOL_GPL(i915_read_mch_val);
3548
3549/**
3550 * i915_gpu_raise - raise GPU frequency limit
3551 *
3552 * Raise the limit; IPS indicates we have thermal headroom.
3553 */
3554bool i915_gpu_raise(void)
3555{
3556 struct drm_i915_private *dev_priv;
3557 bool ret = true;
3558
9270388e 3559 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3560 if (!i915_mch_dev) {
3561 ret = false;
3562 goto out_unlock;
3563 }
3564 dev_priv = i915_mch_dev;
3565
20e4d407
DV		 3566 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3567 dev_priv->ips.max_delay--;
eb48eb00
DV		 3568
3569out_unlock:
9270388e 3570 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3571
3572 return ret;
3573}
3574EXPORT_SYMBOL_GPL(i915_gpu_raise);
3575
3576/**
3577 * i915_gpu_lower - lower GPU frequency limit
3578 *
3579 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3580 * frequency maximum.
3581 */
3582bool i915_gpu_lower(void)
3583{
3584 struct drm_i915_private *dev_priv;
3585 bool ret = true;
3586
9270388e 3587 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3588 if (!i915_mch_dev) {
3589 ret = false;
3590 goto out_unlock;
3591 }
3592 dev_priv = i915_mch_dev;
3593
20e4d407
DV		 3594 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3595 dev_priv->ips.max_delay++;
eb48eb00
DV		 3596
3597out_unlock:
9270388e 3598 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3599
3600 return ret;
3601}
3602EXPORT_SYMBOL_GPL(i915_gpu_lower);
3603
3604/**
3605 * i915_gpu_busy - indicate GPU business to IPS
3606 *
3607 * Tell the IPS driver whether or not the GPU is busy.
3608 */
3609bool i915_gpu_busy(void)
3610{
3611 struct drm_i915_private *dev_priv;
f047e395 3612 struct intel_ring_buffer *ring;
eb48eb00 3613 bool ret = false;
f047e395 3614 int i;
eb48eb00 3615
9270388e 3616 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3617 if (!i915_mch_dev)
3618 goto out_unlock;
3619 dev_priv = i915_mch_dev;
3620
f047e395
CW		 3621 for_each_ring(ring, dev_priv, i)
3622 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3623
3624out_unlock:
9270388e 3625 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3626
3627 return ret;
3628}
3629EXPORT_SYMBOL_GPL(i915_gpu_busy);
3630
3631/**
3632 * i915_gpu_turbo_disable - disable graphics turbo
3633 *
3634 * Disable graphics turbo by resetting the max frequency and setting the
3635 * current frequency to the default.
3636 */
3637bool i915_gpu_turbo_disable(void)
3638{
3639 struct drm_i915_private *dev_priv;
3640 bool ret = true;
3641
9270388e 3642 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3643 if (!i915_mch_dev) {
3644 ret = false;
3645 goto out_unlock;
3646 }
3647 dev_priv = i915_mch_dev;
3648
20e4d407 3649 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3650
20e4d407 3651 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3652 ret = false;
3653
3654out_unlock:
9270388e 3655 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3656
3657 return ret;
3658}
3659EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3660
3661/**
3662 * Tells the intel_ips driver that the i915 driver is now loaded, if
3663 * IPS got loaded first.
3664 *
3665 * This awkward dance is so that neither module has to depend on the
3666 * other in order for IPS to do the appropriate communication of
3667 * GPU turbo limits to i915.
3668 */
3669static void
3670ips_ping_for_i915_load(void)
3671{
3672 void (*link)(void);
3673
3674 link = symbol_get(ips_link_to_i915_driver);
3675 if (link) {
3676 link();
3677 symbol_put(ips_link_to_i915_driver);
3678 }
3679}
3680
3681void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3682{
02d71956
DV		 3683 /* We only register the i915 ips part with intel-ips once everything is
3684 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3685 spin_lock_irq(&mchdev_lock);
eb48eb00 3686 i915_mch_dev = dev_priv;
9270388e 3687 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3688
3689 ips_ping_for_i915_load();
3690}
3691
3692void intel_gpu_ips_teardown(void)
3693{
9270388e 3694 spin_lock_irq(&mchdev_lock);
eb48eb00 3695 i915_mch_dev = NULL;
9270388e 3696 spin_unlock_irq(&mchdev_lock);
eb48eb00 3697}
8090c6b9 3698static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3699{
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3701 u32 lcfuse;
3702 u8 pxw[16];
3703 int i;
3704
3705 /* Disable to program */
3706 I915_WRITE(ECR, 0);
3707 POSTING_READ(ECR);
3708
3709 /* Program energy weights for various events */
3710 I915_WRITE(SDEW, 0x15040d00);
3711 I915_WRITE(CSIEW0, 0x007f0000);
3712 I915_WRITE(CSIEW1, 0x1e220004);
3713 I915_WRITE(CSIEW2, 0x04000004);
3714
3715 for (i = 0; i < 5; i++)
3716 I915_WRITE(PEW + (i * 4), 0);
3717 for (i = 0; i < 3; i++)
3718 I915_WRITE(DEW + (i * 4), 0);
3719
3720 /* Program P-state weights to account for frequency power adjustment */
3721 for (i = 0; i < 16; i++) {
3722 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3723 unsigned long freq = intel_pxfreq(pxvidfreq);
3724 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3725 PXVFREQ_PX_SHIFT;
3726 unsigned long val;
3727
3728 val = vid * vid;
3729 val *= (freq / 1000);
3730 val *= 255;
3731 val /= (127*127*900);
3732 if (val > 0xff)
3733 DRM_ERROR("bad pxval: %ld\n", val);
3734 pxw[i] = val;
3735 }
3736 /* Render standby states get 0 weight */
3737 pxw[14] = 0;
3738 pxw[15] = 0;
3739
3740 for (i = 0; i < 4; i++) {
3741 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3742 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3743 I915_WRITE(PXW + (i * 4), val);
3744 }
3745
3746 /* Adjust magic regs to magic values (more experimental results) */
3747 I915_WRITE(OGW0, 0);
3748 I915_WRITE(OGW1, 0);
3749 I915_WRITE(EG0, 0x00007f00);
3750 I915_WRITE(EG1, 0x0000000e);
3751 I915_WRITE(EG2, 0x000e0000);
3752 I915_WRITE(EG3, 0x68000300);
3753 I915_WRITE(EG4, 0x42000000);
3754 I915_WRITE(EG5, 0x00140031);
3755 I915_WRITE(EG6, 0);
3756 I915_WRITE(EG7, 0);
3757
3758 for (i = 0; i < 8; i++)
3759 I915_WRITE(PXWL + (i * 4), 0);
3760
3761 /* Enable PMON + select events */
3762 I915_WRITE(ECR, 0x80000019);
3763
3764 lcfuse = I915_READ(LCFUSE02);
3765
20e4d407 3766 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3767}
3768
8090c6b9
DV		 3769void intel_disable_gt_powersave(struct drm_device *dev)
3770{
1a01ab3b
JB		 3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772
fd0c0642
DV		 3773 /* Interrupts should be disabled already to avoid re-arming. */
3774 WARN_ON(dev->irq_enabled);
3775
930ebb46 3776 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3777 ironlake_disable_drps(dev);
930ebb46 3778 ironlake_disable_rc6(dev);
0a073b84 3779 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 3780 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 3781 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 3782 if (IS_VALLEYVIEW(dev))
3783 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 3784 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 3785 if (IS_VALLEYVIEW(dev))
3786 valleyview_disable_rps(dev);
3787 else
3788 gen6_disable_rps(dev);
4fc688ce 3789 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 3790 }
8090c6b9
DV		 3791}
3792
1a01ab3b
JB		 3793static void intel_gen6_powersave_work(struct work_struct *work)
3794{
3795 struct drm_i915_private *dev_priv =
3796 container_of(work, struct drm_i915_private,
3797 rps.delayed_resume_work.work);
3798 struct drm_device *dev = dev_priv->dev;
3799
4fc688ce 3800 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 3801
3802 if (IS_VALLEYVIEW(dev)) {
3803 valleyview_enable_rps(dev);
3804 } else {
3805 gen6_enable_rps(dev);
3806 gen6_update_ring_freq(dev);
3807 }
4fc688ce 3808 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3809}
3810
8090c6b9
DV		 3811void intel_enable_gt_powersave(struct drm_device *dev)
3812{
1a01ab3b
JB		 3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814
8090c6b9
DV		 3815 if (IS_IRONLAKE_M(dev)) {
3816 ironlake_enable_drps(dev);
3817 ironlake_enable_rc6(dev);
3818 intel_init_emon(dev);
0a073b84 3819 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 3820 /*
3821 * PCU communication is slow and this doesn't need to be
3822 * done at any specific time, so do this out of our fast path
3823 * to make resume and init faster.
3824 */
3825 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3826 round_jiffies_up_relative(HZ));
8090c6b9
DV		 3827 }
3828}
3829
3107bd48
DV		 3830static void ibx_init_clock_gating(struct drm_device *dev)
3831{
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833
3834 /*
3835 * On Ibex Peak and Cougar Point, we need to disable clock
3836 * gating for the panel power sequencer or it will fail to
3837 * start up when no ports are active.
3838 */
3839 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3840}
3841
1fa61106 3842static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3843{
3844 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 3845 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 3846
3847 /* Required for FBC */
4d47e4f5
DL		 3848 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3849 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3850 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3851
3852 I915_WRITE(PCH_3DCGDIS0,
3853 MARIUNIT_CLOCK_GATE_DISABLE |
3854 SVSMUNIT_CLOCK_GATE_DISABLE);
3855 I915_WRITE(PCH_3DCGDIS1,
3856 VFMUNIT_CLOCK_GATE_DISABLE);
3857
6f1d69b0
ED		 3858 /*
3859 * According to the spec the following bits should be set in
3860 * order to enable memory self-refresh
3861 * The bit 22/21 of 0x42004
3862 * The bit 5 of 0x42020
3863 * The bit 15 of 0x45000
3864 */
3865 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3866 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3867 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 3868 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3869 I915_WRITE(DISP_ARB_CTL,
3870 (I915_READ(DISP_ARB_CTL) |
3871 DISP_FBC_WM_DIS));
3872 I915_WRITE(WM3_LP_ILK, 0);
3873 I915_WRITE(WM2_LP_ILK, 0);
3874 I915_WRITE(WM1_LP_ILK, 0);
3875
3876 /*
3877 * Based on the document from hardware guys the following bits
3878 * should be set unconditionally in order to enable FBC.
3879 * The bit 22 of 0x42000
3880 * The bit 22 of 0x42004
3881 * The bit 7,8,9 of 0x42020.
3882 */
3883 if (IS_IRONLAKE_M(dev)) {
3884 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3885 I915_READ(ILK_DISPLAY_CHICKEN1) |
3886 ILK_FBCQ_DIS);
3887 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3888 I915_READ(ILK_DISPLAY_CHICKEN2) |
3889 ILK_DPARB_GATE);
6f1d69b0
ED		 3890 }
3891
4d47e4f5
DL		 3892 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3893
6f1d69b0
ED		 3894 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3895 I915_READ(ILK_DISPLAY_CHICKEN2) |
3896 ILK_ELPIN_409_SELECT);
3897 I915_WRITE(_3D_CHICKEN2,
3898 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3899 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 3900
ecdb4eb7 3901 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 3902 I915_WRITE(CACHE_MODE_0,
3903 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 3904
3905 ibx_init_clock_gating(dev);
3906}
3907
3908static void cpt_init_clock_gating(struct drm_device *dev)
3909{
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911 int pipe;
3f704fa2 3912 uint32_t val;
3107bd48
DV		 3913
3914 /*
3915 * On Ibex Peak and Cougar Point, we need to disable clock
3916 * gating for the panel power sequencer or it will fail to
3917 * start up when no ports are active.
3918 */
3919 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3920 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3921 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 3922 /* The below fixes the weird display corruption, a few pixels shifted
3923 * downward, on (only) LVDS of some HP laptops with IVY.
3924 */
3f704fa2 3925 for_each_pipe(pipe) {
dc4bd2d1
PZ		 3926 val = I915_READ(TRANS_CHICKEN2(pipe));
3927 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3928 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 3929 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 3930 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 3931 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3932 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3933 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 3934 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3935 }
3107bd48
DV		 3936 /* WADP0ClockGatingDisable */
3937 for_each_pipe(pipe) {
3938 I915_WRITE(TRANS_CHICKEN1(pipe),
3939 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3940 }
6f1d69b0
ED		 3941}
3942
1d7aaa0c
DV		 3943static void gen6_check_mch_setup(struct drm_device *dev)
3944{
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 uint32_t tmp;
3947
3948 tmp = I915_READ(MCH_SSKPD);
3949 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3950 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3951 DRM_INFO("This can cause pipe underruns and display issues.\n");
3952 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3953 }
3954}
3955
1fa61106 3956static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3957{
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 int pipe;
231e54f6 3960 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 3961
231e54f6 3962 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 3963
3964 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3965 I915_READ(ILK_DISPLAY_CHICKEN2) |
3966 ILK_ELPIN_409_SELECT);
3967
ecdb4eb7 3968 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 3969 I915_WRITE(_3D_CHICKEN,
3970 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3971
ecdb4eb7 3972 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 3973 if (IS_SNB_GT1(dev))
3974 I915_WRITE(GEN6_GT_MODE,
3975 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3976
6f1d69b0
ED		 3977 I915_WRITE(WM3_LP_ILK, 0);
3978 I915_WRITE(WM2_LP_ILK, 0);
3979 I915_WRITE(WM1_LP_ILK, 0);
3980
6f1d69b0 3981 I915_WRITE(CACHE_MODE_0,
50743298 3982 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3983
3984 I915_WRITE(GEN6_UCGCTL1,
3985 I915_READ(GEN6_UCGCTL1) |
3986 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3987 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3988
3989 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3990 * gating disable must be set. Failure to set it results in
3991 * flickering pixels due to Z write ordering failures after
3992 * some amount of runtime in the Mesa "fire" demo, and Unigine
3993 * Sanctuary and Tropics, and apparently anything else with
3994 * alpha test or pixel discard.
3995 *
3996 * According to the spec, bit 11 (RCCUNIT) must also be set,
3997 * but we didn't debug actual testcases to find it out.
0f846f81 3998 *
ecdb4eb7
DL		 3999 * Also apply WaDisableVDSUnitClockGating:snb and
4000 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4001 */
4002 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4003 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4004 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4005 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4006
4007 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4008 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4009 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4010
4011 /*
4012 * According to the spec the following bits should be
4013 * set in order to enable memory self-refresh and fbc:
4014 * The bit21 and bit22 of 0x42000
4015 * The bit21 and bit22 of 0x42004
4016 * The bit5 and bit7 of 0x42020
4017 * The bit14 of 0x70180
4018 * The bit14 of 0x71180
4019 */
4020 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4021 I915_READ(ILK_DISPLAY_CHICKEN1) |
4022 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4023 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4024 I915_READ(ILK_DISPLAY_CHICKEN2) |
4025 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4026 I915_WRITE(ILK_DSPCLK_GATE_D,
4027 I915_READ(ILK_DSPCLK_GATE_D) |
4028 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4029 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4030
ecdb4eb7 4031 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4032 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4033 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4034
6f1d69b0
ED		 4035 for_each_pipe(pipe) {
4036 I915_WRITE(DSPCNTR(pipe),
4037 I915_READ(DSPCNTR(pipe)) |
4038 DISPPLANE_TRICKLE_FEED_DISABLE);
4039 intel_flush_display_plane(dev_priv, pipe);
4040 }
f8f2ac9a
BW		 4041
4042 /* The default value should be 0x200 according to docs, but the two
4043 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4044 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4045 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4046
4047 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4048
4049 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4050}
4051
4052static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4053{
4054 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4055
4056 reg &= ~GEN7_FF_SCHED_MASK;
4057 reg |= GEN7_FF_TS_SCHED_HW;
4058 reg |= GEN7_FF_VS_SCHED_HW;
4059 reg |= GEN7_FF_DS_SCHED_HW;
4060
41c0b3a8
BW		 4061 if (IS_HASWELL(dev_priv->dev))
4062 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4063
6f1d69b0
ED		 4064 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4065}
4066
17a303ec
PZ		 4067static void lpt_init_clock_gating(struct drm_device *dev)
4068{
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070
4071 /*
4072 * TODO: this bit should only be enabled when really needed, then
4073 * disabled when not needed anymore in order to save power.
4074 */
4075 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4076 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4077 I915_READ(SOUTH_DSPCLK_GATE_D) |
4078 PCH_LP_PARTITION_LEVEL_DISABLE);
4079}
4080
7d708ee4
ID		 4081static void lpt_suspend_hw(struct drm_device *dev)
4082{
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084
4085 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4086 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4087
4088 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4089 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4090 }
4091}
4092
cad2a2d7
ED		 4093static void haswell_init_clock_gating(struct drm_device *dev)
4094{
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 int pipe;
cad2a2d7
ED		 4097
4098 I915_WRITE(WM3_LP_ILK, 0);
4099 I915_WRITE(WM2_LP_ILK, 0);
4100 I915_WRITE(WM1_LP_ILK, 0);
4101
4102 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4103 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4104 */
4105 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4106
ecdb4eb7 4107 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4108 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4109 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4110
ecdb4eb7 4111 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4112 I915_WRITE(GEN7_L3CNTLREG1,
4113 GEN7_WA_FOR_GEN7_L3_CONTROL);
4114 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4115 GEN7_WA_L3_CHICKEN_MODE);
4116
ecdb4eb7 4117 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4118 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4119 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4120 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4121
4122 for_each_pipe(pipe) {
4123 I915_WRITE(DSPCNTR(pipe),
4124 I915_READ(DSPCNTR(pipe)) |
4125 DISPPLANE_TRICKLE_FEED_DISABLE);
4126 intel_flush_display_plane(dev_priv, pipe);
4127 }
4128
ecdb4eb7 4129 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4130 gen7_setup_fixed_func_scheduler(dev_priv);
4131
ecdb4eb7 4132 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4133 I915_WRITE(CACHE_MODE_1,
4134 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4135
ecdb4eb7 4136 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4137 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4138 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4139
ecdb4eb7 4140 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4141 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4142
1544d9d5
ED		 4143 /* XXX: This is a workaround for early silicon revisions and should be
4144 * removed later.
4145 */
4146 I915_WRITE(WM_DBG,
4147 I915_READ(WM_DBG) |
4148 WM_DBG_DISALLOW_MULTIPLE_LP |
4149 WM_DBG_DISALLOW_SPRITE |
4150 WM_DBG_DISALLOW_MAXFIFO);
4151
17a303ec 4152 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4153}
4154
1fa61106 4155static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4156{
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 int pipe;
20848223 4159 uint32_t snpcr;
6f1d69b0 4160
6f1d69b0
ED		 4161 I915_WRITE(WM3_LP_ILK, 0);
4162 I915_WRITE(WM2_LP_ILK, 0);
4163 I915_WRITE(WM1_LP_ILK, 0);
4164
231e54f6 4165 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4166
ecdb4eb7 4167 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4168 I915_WRITE(_3D_CHICKEN3,
4169 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4170
ecdb4eb7 4171 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4172 I915_WRITE(IVB_CHICKEN3,
4173 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4174 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4175
ecdb4eb7 4176 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4177 if (IS_IVB_GT1(dev))
4178 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4179 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4180 else
4181 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4182 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4183
ecdb4eb7 4184 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4185 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4186 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4187
ecdb4eb7 4188 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4189 I915_WRITE(GEN7_L3CNTLREG1,
4190 GEN7_WA_FOR_GEN7_L3_CONTROL);
4191 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4192 GEN7_WA_L3_CHICKEN_MODE);
4193 if (IS_IVB_GT1(dev))
4194 I915_WRITE(GEN7_ROW_CHICKEN2,
4195 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4196 else
4197 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4198 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4199
6f1d69b0 4200
ecdb4eb7 4201 /* WaForceL3Serialization:ivb */
61939d97
JB		 4202 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4203 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4204
0f846f81
JB		 4205 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4206 * gating disable must be set. Failure to set it results in
4207 * flickering pixels due to Z write ordering failures after
4208 * some amount of runtime in the Mesa "fire" demo, and Unigine
4209 * Sanctuary and Tropics, and apparently anything else with
4210 * alpha test or pixel discard.
4211 *
4212 * According to the spec, bit 11 (RCCUNIT) must also be set,
4213 * but we didn't debug actual testcases to find it out.
4214 *
4215 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4216 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4217 */
4218 I915_WRITE(GEN6_UCGCTL2,
4219 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4220 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4221
ecdb4eb7 4222 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4223 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4224 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4225 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4226
4227 for_each_pipe(pipe) {
4228 I915_WRITE(DSPCNTR(pipe),
4229 I915_READ(DSPCNTR(pipe)) |
4230 DISPPLANE_TRICKLE_FEED_DISABLE);
4231 intel_flush_display_plane(dev_priv, pipe);
4232 }
4233
ecdb4eb7 4234 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4235 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4236 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4237
ecdb4eb7 4238 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4239 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4240
ecdb4eb7 4241 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4242 I915_WRITE(CACHE_MODE_1,
4243 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4244
4245 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4246 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4247 snpcr |= GEN6_MBC_SNPCR_MED;
4248 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4249
ab5c608b
BW		 4250 if (!HAS_PCH_NOP(dev))
4251 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4252
4253 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4254}
4255
1fa61106 4256static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4257{
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 int pipe;
6f1d69b0
ED		 4260
4261 I915_WRITE(WM3_LP_ILK, 0);
4262 I915_WRITE(WM2_LP_ILK, 0);
4263 I915_WRITE(WM1_LP_ILK, 0);
4264
231e54f6 4265 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4266
ecdb4eb7 4267 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4268 I915_WRITE(_3D_CHICKEN3,
4269 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4270
ecdb4eb7 4271 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4272 I915_WRITE(IVB_CHICKEN3,
4273 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4274 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4275
ecdb4eb7 4276 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4277 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4278 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4279 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4280
ecdb4eb7 4281 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4282 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4283 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4284
ecdb4eb7 4285 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4286 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4287 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4288
ecdb4eb7 4289 /* WaForceL3Serialization:vlv */
61939d97
JB		 4290 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4291 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4292
ecdb4eb7 4293 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4294 I915_WRITE(GEN7_ROW_CHICKEN2,
4295 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4296
ecdb4eb7 4297 /* WaForceL3Serialization:vlv */
5c9664d7
JB		 4298 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4299 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4300
ecdb4eb7 4301 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4302 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4303 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4304 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4305
ecdb4eb7 4306 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4307 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4308 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4309
0f846f81
JB		 4310
4311 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4312 * gating disable must be set. Failure to set it results in
4313 * flickering pixels due to Z write ordering failures after
4314 * some amount of runtime in the Mesa "fire" demo, and Unigine
4315 * Sanctuary and Tropics, and apparently anything else with
4316 * alpha test or pixel discard.
4317 *
4318 * According to the spec, bit 11 (RCCUNIT) must also be set,
4319 * but we didn't debug actual testcases to find it out.
4320 *
4321 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4322 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4323 *
ecdb4eb7
DL		 4324 * Also apply WaDisableVDSUnitClockGating:vlv and
4325 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4326 */
4327 I915_WRITE(GEN6_UCGCTL2,
4328 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4329 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4330 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4331 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4332 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4333
e3f33d46
JB		 4334 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4335
6f1d69b0
ED		 4336 for_each_pipe(pipe) {
4337 I915_WRITE(DSPCNTR(pipe),
4338 I915_READ(DSPCNTR(pipe)) |
4339 DISPPLANE_TRICKLE_FEED_DISABLE);
4340 intel_flush_display_plane(dev_priv, pipe);
4341 }
4342
6b26c86d
DV		 4343 I915_WRITE(CACHE_MODE_1,
4344 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4345
2d809570 4346 /*
ecdb4eb7 4347 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4348 * Disable clock gating on th GCFG unit to prevent a delay
4349 * in the reporting of vblank events.
4350 */
4e8c84a5
JB		 4351 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4352
4353 /* Conservative clock gating settings for now */
4354 I915_WRITE(0x9400, 0xffffffff);
4355 I915_WRITE(0x9404, 0xffffffff);
4356 I915_WRITE(0x9408, 0xffffffff);
4357 I915_WRITE(0x940c, 0xffffffff);
4358 I915_WRITE(0x9410, 0xffffffff);
4359 I915_WRITE(0x9414, 0xffffffff);
4360 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4361}
4362
1fa61106 4363static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4364{
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 uint32_t dspclk_gate;
4367
4368 I915_WRITE(RENCLK_GATE_D1, 0);
4369 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4370 GS_UNIT_CLOCK_GATE_DISABLE |
4371 CL_UNIT_CLOCK_GATE_DISABLE);
4372 I915_WRITE(RAMCLK_GATE_D, 0);
4373 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4374 OVRUNIT_CLOCK_GATE_DISABLE |
4375 OVCUNIT_CLOCK_GATE_DISABLE;
4376 if (IS_GM45(dev))
4377 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4378 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4379
4380 /* WaDisableRenderCachePipelinedFlush */
4381 I915_WRITE(CACHE_MODE_0,
4382 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 4383}
4384
1fa61106 4385static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4386{
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388
4389 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4390 I915_WRITE(RENCLK_GATE_D2, 0);
4391 I915_WRITE(DSPCLK_GATE_D, 0);
4392 I915_WRITE(RAMCLK_GATE_D, 0);
4393 I915_WRITE16(DEUC, 0);
4394}
4395
1fa61106 4396static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4397{
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399
4400 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4401 I965_RCC_CLOCK_GATE_DISABLE |
4402 I965_RCPB_CLOCK_GATE_DISABLE |
4403 I965_ISC_CLOCK_GATE_DISABLE |
4404 I965_FBC_CLOCK_GATE_DISABLE);
4405 I915_WRITE(RENCLK_GATE_D2, 0);
4406}
4407
1fa61106 4408static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4409{
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 u32 dstate = I915_READ(D_STATE);
4412
4413 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4414 DSTATE_DOT_CLOCK_GATING;
4415 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4416
4417 if (IS_PINEVIEW(dev))
4418 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4419
4420 /* IIR "flip pending" means done if this bit is set */
4421 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4422}
4423
1fa61106 4424static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4425{
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427
4428 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4429}
4430
1fa61106 4431static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4432{
4433 struct drm_i915_private *dev_priv = dev->dev_private;
4434
4435 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4436}
4437
6f1d69b0
ED		 4438void intel_init_clock_gating(struct drm_device *dev)
4439{
4440 struct drm_i915_private *dev_priv = dev->dev_private;
4441
4442 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4443}
4444
7d708ee4
ID		 4445void intel_suspend_hw(struct drm_device *dev)
4446{
4447 if (HAS_PCH_LPT(dev))
4448 lpt_suspend_hw(dev);
4449}
4450
15d199ea
PZ		 4451/**
4452 * We should only use the power well if we explicitly asked the hardware to
4453 * enable it, so check if it's enabled and also check if we've requested it to
4454 * be enabled.
4455 */
b97186f0
PZ		 4456bool intel_display_power_enabled(struct drm_device *dev,
4457 enum intel_display_power_domain domain)
15d199ea
PZ		 4458{
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460
b97186f0
PZ		 4461 if (!HAS_POWER_WELL(dev))
4462 return true;
4463
4464 switch (domain) {
4465 case POWER_DOMAIN_PIPE_A:
4466 case POWER_DOMAIN_TRANSCODER_EDP:
4467 return true;
4468 case POWER_DOMAIN_PIPE_B:
4469 case POWER_DOMAIN_PIPE_C:
4470 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4471 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4472 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4473 case POWER_DOMAIN_TRANSCODER_A:
4474 case POWER_DOMAIN_TRANSCODER_B:
4475 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 4476 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4477 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 4478 default:
4479 BUG();
4480 }
15d199ea
PZ		 4481}
4482
cb10799c 4483void intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 4484{
4485 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 4486 bool is_enabled, enable_requested;
4487 uint32_t tmp;
d0d3e513 4488
86d52df6 4489 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 4490 return;
4491
2124b72e
PZ		 4492 if (!i915_disable_power_well && !enable)
4493 return;
4494
fa42e23c
PZ		 4495 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4496 is_enabled = tmp & HSW_PWR_WELL_STATE;
4497 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 4498
fa42e23c
PZ		 4499 if (enable) {
4500 if (!enable_requested)
4501 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 4502
fa42e23c
PZ		 4503 if (!is_enabled) {
4504 DRM_DEBUG_KMS("Enabling power well\n");
4505 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4506 HSW_PWR_WELL_STATE), 20))
4507 DRM_ERROR("Timeout enabling power well\n");
4508 }
4509 } else {
4510 if (enable_requested) {
4511 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4512 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 4513 }
4514 }
fa42e23c 4515}
d0d3e513 4516
fa42e23c
PZ		 4517/*
4518 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4519 * when not needed anymore. We have 4 registers that can request the power well
4520 * to be enabled, and it will only be disabled if none of the registers is
4521 * requesting it to be enabled.
d0d3e513 4522 */
fa42e23c 4523void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 4524{
4525 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 4526
86d52df6 4527 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 4528 return;
4529
fa42e23c
PZ		 4530 /* For now, we need the power well to be always enabled. */
4531 intel_set_power_well(dev, true);
d0d3e513 4532
fa42e23c
PZ		 4533 /* We're taking over the BIOS, so clear any requests made by it since
4534 * the driver is in charge now. */
4535 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4536 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 4537}
4538
1fa61106
ED		 4539/* Set up chip specific power management-related functions */
4540void intel_init_pm(struct drm_device *dev)
4541{
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543
4544 if (I915_HAS_FBC(dev)) {
4545 if (HAS_PCH_SPLIT(dev)) {
4546 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
abe959c7
RV		 4547 if (IS_IVYBRIDGE(dev))
4548 dev_priv->display.enable_fbc =
4549 gen7_enable_fbc;
4550 else
4551 dev_priv->display.enable_fbc =
4552 ironlake_enable_fbc;
1fa61106
ED		 4553 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4554 } else if (IS_GM45(dev)) {
4555 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4556 dev_priv->display.enable_fbc = g4x_enable_fbc;
4557 dev_priv->display.disable_fbc = g4x_disable_fbc;
4558 } else if (IS_CRESTLINE(dev)) {
4559 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4560 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4561 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4562 }
4563 /* 855GM needs testing */
4564 }
4565
c921aba8
DV		 4566 /* For cxsr */
4567 if (IS_PINEVIEW(dev))
4568 i915_pineview_get_mem_freq(dev);
4569 else if (IS_GEN5(dev))
4570 i915_ironlake_get_mem_freq(dev);
4571
1fa61106
ED		 4572 /* For FIFO watermark updates */
4573 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 4574 if (IS_GEN5(dev)) {
4575 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4576 dev_priv->display.update_wm = ironlake_update_wm;
4577 else {
4578 DRM_DEBUG_KMS("Failed to get proper latency. "
4579 "Disable CxSR\n");
4580 dev_priv->display.update_wm = NULL;
4581 }
4582 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4583 } else if (IS_GEN6(dev)) {
4584 if (SNB_READ_WM0_LATENCY()) {
4585 dev_priv->display.update_wm = sandybridge_update_wm;
4586 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4587 } else {
4588 DRM_DEBUG_KMS("Failed to read display plane latency. "
4589 "Disable CxSR\n");
4590 dev_priv->display.update_wm = NULL;
4591 }
4592 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4593 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 4594 if (SNB_READ_WM0_LATENCY()) {
c43d0188 4595 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 4596 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4597 } else {
4598 DRM_DEBUG_KMS("Failed to read display plane latency. "
4599 "Disable CxSR\n");
4600 dev_priv->display.update_wm = NULL;
4601 }
4602 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 4603 } else if (IS_HASWELL(dev)) {
4604 if (SNB_READ_WM0_LATENCY()) {
4605 dev_priv->display.update_wm = sandybridge_update_wm;
4606 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 4607 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 4608 } else {
4609 DRM_DEBUG_KMS("Failed to read display plane latency. "
4610 "Disable CxSR\n");
4611 dev_priv->display.update_wm = NULL;
4612 }
cad2a2d7 4613 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4614 } else
4615 dev_priv->display.update_wm = NULL;
4616 } else if (IS_VALLEYVIEW(dev)) {
4617 dev_priv->display.update_wm = valleyview_update_wm;
4618 dev_priv->display.init_clock_gating =
4619 valleyview_init_clock_gating;
1fa61106
ED		 4620 } else if (IS_PINEVIEW(dev)) {
4621 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4622 dev_priv->is_ddr3,
4623 dev_priv->fsb_freq,
4624 dev_priv->mem_freq)) {
4625 DRM_INFO("failed to find known CxSR latency "
4626 "(found ddr%s fsb freq %d, mem freq %d), "
4627 "disabling CxSR\n",
4628 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4629 dev_priv->fsb_freq, dev_priv->mem_freq);
4630 /* Disable CxSR and never update its watermark again */
4631 pineview_disable_cxsr(dev);
4632 dev_priv->display.update_wm = NULL;
4633 } else
4634 dev_priv->display.update_wm = pineview_update_wm;
4635 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4636 } else if (IS_G4X(dev)) {
4637 dev_priv->display.update_wm = g4x_update_wm;
4638 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4639 } else if (IS_GEN4(dev)) {
4640 dev_priv->display.update_wm = i965_update_wm;
4641 if (IS_CRESTLINE(dev))
4642 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4643 else if (IS_BROADWATER(dev))
4644 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4645 } else if (IS_GEN3(dev)) {
4646 dev_priv->display.update_wm = i9xx_update_wm;
4647 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4648 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4649 } else if (IS_I865G(dev)) {
4650 dev_priv->display.update_wm = i830_update_wm;
4651 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4652 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4653 } else if (IS_I85X(dev)) {
4654 dev_priv->display.update_wm = i9xx_update_wm;
4655 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4656 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4657 } else {
4658 dev_priv->display.update_wm = i830_update_wm;
4659 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4660 if (IS_845G(dev))
4661 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4662 else
4663 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4664 }
4665}
4666
6590190d
ED		 4667static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4668{
4669 u32 gt_thread_status_mask;
4670
4671 if (IS_HASWELL(dev_priv->dev))
4672 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4673 else
4674 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4675
4676 /* w/a for a sporadic read returning 0 by waiting for the GT
4677 * thread to wake up.
4678 */
4679 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4680 DRM_ERROR("GT thread status wait timed out\n");
4681}
4682
16995a9f
CW		 4683static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4684{
4685 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4686 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4687}
4688
6590190d
ED		 4689static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4690{
ebd37ce1 4691 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
057d3860 4692 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4693 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4694
30771e16 4695 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 4696 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4697
ebd37ce1 4698 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
057d3860 4699 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4700 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 4701
8693a824 4702 /* WaRsForcewakeWaitTC0:snb */
6590190d
ED		 4703 __gen6_gt_wait_for_thread_c0(dev_priv);
4704}
4705
16995a9f
CW		 4706static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4707{
4708 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 4709 /* something from same cacheline, but !FORCEWAKE_MT */
4710 POSTING_READ(ECOBUS);
16995a9f
CW		 4711}
4712
6590190d
ED		 4713static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4714{
4715 u32 forcewake_ack;
4716
4717 if (IS_HASWELL(dev_priv->dev))
4718 forcewake_ack = FORCEWAKE_ACK_HSW;
4719 else
4720 forcewake_ack = FORCEWAKE_MT_ACK;
4721
83983c8b 4722 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
057d3860 4723 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4724 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4725
c5836c27 4726 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
b5144075
JN		 4727 /* something from same cacheline, but !FORCEWAKE_MT */
4728 POSTING_READ(ECOBUS);
6590190d 4729
83983c8b 4730 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
057d3860 4731 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4732 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 4733
8693a824 4734 /* WaRsForcewakeWaitTC0:ivb,hsw */
6590190d
ED		 4735 __gen6_gt_wait_for_thread_c0(dev_priv);
4736}
4737
4738/*
4739 * Generally this is called implicitly by the register read function. However,
4740 * if some sequence requires the GT to not power down then this function should
4741 * be called at the beginning of the sequence followed by a call to
4742 * gen6_gt_force_wake_put() at the end of the sequence.
4743 */
4744void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4745{
4746 unsigned long irqflags;
4747
4748 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4749 if (dev_priv->forcewake_count++ == 0)
4750 dev_priv->gt.force_wake_get(dev_priv);
4751 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4752}
4753
4754void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4755{
4756 u32 gtfifodbg;
4757 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4758 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4759 "MMIO read or write has been dropped %x\n", gtfifodbg))
4760 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4761}
4762
4763static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4764{
4765 I915_WRITE_NOTRACE(FORCEWAKE, 0);
b5144075
JN		 4766 /* something from same cacheline, but !FORCEWAKE */
4767 POSTING_READ(ECOBUS);
6590190d
ED		 4768 gen6_gt_check_fifodbg(dev_priv);
4769}
4770
4771static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4772{
c5836c27 4773 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
b5144075
JN		 4774 /* something from same cacheline, but !FORCEWAKE_MT */
4775 POSTING_READ(ECOBUS);
6590190d
ED		 4776 gen6_gt_check_fifodbg(dev_priv);
4777}
4778
4779/*
4780 * see gen6_gt_force_wake_get()
4781 */
4782void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4783{
4784 unsigned long irqflags;
4785
4786 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4787 if (--dev_priv->forcewake_count == 0)
4788 dev_priv->gt.force_wake_put(dev_priv);
4789 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4790}
4791
4792int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4793{
4794 int ret = 0;
4795
4796 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4797 int loop = 500;
4798 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4799 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4800 udelay(10);
4801 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4802 }
4803 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4804 ++ret;
4805 dev_priv->gt_fifo_count = fifo;
4806 }
4807 dev_priv->gt_fifo_count--;
4808
4809 return ret;
4810}
4811
16995a9f
CW		 4812static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4813{
4814 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 4815 /* something from same cacheline, but !FORCEWAKE_VLV */
4816 POSTING_READ(FORCEWAKE_ACK_VLV);
16995a9f
CW		 4817}
4818
6590190d
ED		 4819static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4820{
83983c8b 4821 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
057d3860 4822 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4823 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4824
c5836c27 4825 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 4826 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4827 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 4828
83983c8b 4829 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
057d3860 4830 FORCEWAKE_ACK_TIMEOUT_MS))
ed5de399
JB		 4831 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4832
4833 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4834 FORCEWAKE_KERNEL),
4835 FORCEWAKE_ACK_TIMEOUT_MS))
4836 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
6590190d 4837
8693a824 4838 /* WaRsForcewakeWaitTC0:vlv */
6590190d
ED		 4839 __gen6_gt_wait_for_thread_c0(dev_priv);
4840}
4841
4842static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4843{
c5836c27 4844 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 4845 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4846 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4847 /* The below doubles as a POSTING_READ */
5ab140a4 4848 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4849}
4850
16995a9f
CW		 4851void intel_gt_reset(struct drm_device *dev)
4852{
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854
4855 if (IS_VALLEYVIEW(dev)) {
4856 vlv_force_wake_reset(dev_priv);
4857 } else if (INTEL_INFO(dev)->gen >= 6) {
4858 __gen6_gt_force_wake_reset(dev_priv);
4859 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4860 __gen6_gt_force_wake_mt_reset(dev_priv);
4861 }
4862}
4863
6590190d
ED		 4864void intel_gt_init(struct drm_device *dev)
4865{
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867
4868 spin_lock_init(&dev_priv->gt_lock);
4869
16995a9f
CW		 4870 intel_gt_reset(dev);
4871
6590190d
ED		 4872 if (IS_VALLEYVIEW(dev)) {
4873 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4874 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 4875 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4876 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4877 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4878 } else if (IS_GEN6(dev)) {
6590190d
ED		 4879 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4880 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 4881 }
1a01ab3b
JB		 4882 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4883 intel_gen6_powersave_work);
6590190d
ED		 4884}
4885
42c0526c
BW		 4886int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4887{
4fc688ce 4888 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4889
4890 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4891 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4892 return -EAGAIN;
4893 }
4894
4895 I915_WRITE(GEN6_PCODE_DATA, *val);
4896 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4897
4898 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4899 500)) {
4900 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4901 return -ETIMEDOUT;
4902 }
4903
4904 *val = I915_READ(GEN6_PCODE_DATA);
4905 I915_WRITE(GEN6_PCODE_DATA, 0);
4906
4907 return 0;
4908}
4909
4910int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4911{
4fc688ce 4912 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4913
4914 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4915 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4916 return -EAGAIN;
4917 }
4918
4919 I915_WRITE(GEN6_PCODE_DATA, val);
4920 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4921
4922 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4923 500)) {
4924 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4925 return -ETIMEDOUT;
4926 }
4927
4928 I915_WRITE(GEN6_PCODE_DATA, 0);
4929
4930 return 0;
4931}
a0e4e199 4932
0a073b84 4933static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
a0e4e199
JB		 4934 u8 addr, u32 *val)
4935{
0a073b84 4936 u32 cmd, devfn, be, bar;
a0e4e199
JB		 4937
4938 bar = 0;
4939 be = 0xf;
a0e4e199
JB		 4940 devfn = PCI_DEVFN(2, 0);
4941
4942 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4943 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4944 (bar << IOSF_BAR_SHIFT);
4945
4946 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4947
4948 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4949 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4950 opcode == PUNIT_OPCODE_REG_READ ?
4951 "read" : "write");
4952 return -EAGAIN;
4953 }
4954
4955 I915_WRITE(VLV_IOSF_ADDR, addr);
4956 if (opcode == PUNIT_OPCODE_REG_WRITE)
4957 I915_WRITE(VLV_IOSF_DATA, *val);
4958 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4959
4960 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
0a073b84 4961 5)) {
a0e4e199
JB		 4962 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4963 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4964 addr);
4965 return -ETIMEDOUT;
4966 }
4967
4968 if (opcode == PUNIT_OPCODE_REG_READ)
4969 *val = I915_READ(VLV_IOSF_DATA);
4970 I915_WRITE(VLV_IOSF_DATA, 0);
4971
4972 return 0;
4973}
4974
4975int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4976{
0a073b84
JB		 4977 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
4978 addr, val);
a0e4e199
JB		 4979}
4980
4981int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4982{
0a073b84
JB		 4983 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
4984 addr, &val);
4985}
4986
4987int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4988{
4989 return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
4990 addr, val);
a0e4e199 4991}
855ba3be
JB		 4992
4993int vlv_gpu_freq(int ddr_freq, int val)
4994{
4995 int mult, base;
4996
4997 switch (ddr_freq) {
4998 case 800:
4999 mult = 20;
5000 base = 120;
5001 break;
5002 case 1066:
5003 mult = 22;
5004 base = 133;
5005 break;
5006 case 1333:
5007 mult = 21;
5008 base = 125;
5009 break;
5010 default:
5011 return -1;
5012 }
5013
5014 return ((val - 0xbd) * mult) + base;
5015}
5016
5017int vlv_freq_opcode(int ddr_freq, int val)
5018{
5019 int mult, base;
5020
5021 switch (ddr_freq) {
5022 case 800:
5023 mult = 20;
5024 base = 120;
5025 break;
5026 case 1066:
5027 mult = 22;
5028 base = 133;
5029 break;
5030 case 1333:
5031 mult = 21;
5032 base = 125;
5033 break;
5034 default:
5035 return -1;
5036 }
5037
5038 val /= mult;
5039 val -= base / mult;
5040 val += 0xbd;
5041
5042 if (val > 0xea)
5043 val = 0xea;
5044
5045 return val;
5046}
5047
Linux kernel - Deliverables
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