projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Set has_fbc=true for all SNB+, except VLV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
dc39fff7
BW		 35/**
36 * RC6 is a special power stage which allows the GPU to enter an very
37 * low-voltage mode when idle, using down to 0V while at this stage. This
38 * stage is entered automatically when the GPU is idle when RC6 support is
39 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 *
41 * There are different RC6 modes available in Intel GPU, which differentiate
42 * among each other with the latency required to enter and leave RC6 and
43 * voltage consumed by the GPU in different states.
44 *
45 * The combination of the following flags define which states GPU is allowed
46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
47 * RC6pp is deepest RC6. Their support by hardware varies according to the
48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
49 * which brings the most power savings; deeper states save more power, but
50 * require higher latency to switch to and wake up.
51 */
52#define INTEL_RC6_ENABLE (1<<0)
53#define INTEL_RC6p_ENABLE (1<<1)
54#define INTEL_RC6pp_ENABLE (1<<2)
55
f6750b3c
ED		 56/* FBC, or Frame Buffer Compression, is a technique employed to compress the
57 * framebuffer contents in-memory, aiming at reducing the required bandwidth
58 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 59 *
f6750b3c
ED		 60 * The benefits of FBC are mostly visible with solid backgrounds and
61 * variation-less patterns.
85208be0 62 *
f6750b3c
ED		 63 * FBC-related functionality can be enabled by the means of the
64 * i915.i915_enable_fbc parameter
85208be0
ED		 65 */
66
1fa61106 67static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 68{
69 struct drm_i915_private *dev_priv = dev->dev_private;
70 u32 fbc_ctl;
71
72 /* Disable compression */
73 fbc_ctl = I915_READ(FBC_CONTROL);
74 if ((fbc_ctl & FBC_CTL_EN) == 0)
75 return;
76
77 fbc_ctl &= ~FBC_CTL_EN;
78 I915_WRITE(FBC_CONTROL, fbc_ctl);
79
80 /* Wait for compressing bit to clear */
81 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
82 DRM_DEBUG_KMS("FBC idle timed out\n");
83 return;
84 }
85
86 DRM_DEBUG_KMS("disabled FBC\n");
87}
88
1fa61106 89static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 90{
91 struct drm_device *dev = crtc->dev;
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct drm_framebuffer *fb = crtc->fb;
94 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
95 struct drm_i915_gem_object *obj = intel_fb->obj;
96 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
97 int cfb_pitch;
98 int plane, i;
99 u32 fbc_ctl, fbc_ctl2;
100
5c3fe8b0 101 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 102 if (fb->pitches[0] < cfb_pitch)
103 cfb_pitch = fb->pitches[0];
104
105 /* FBC_CTL wants 64B units */
106 cfb_pitch = (cfb_pitch / 64) - 1;
107 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
108
109 /* Clear old tags */
110 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
111 I915_WRITE(FBC_TAG + (i * 4), 0);
112
113 /* Set it up... */
114 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
115 fbc_ctl2 |= plane;
116 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
117 I915_WRITE(FBC_FENCE_OFF, crtc->y);
118
119 /* enable it... */
120 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
121 if (IS_I945GM(dev))
122 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
123 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
124 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
125 fbc_ctl |= obj->fence_reg;
126 I915_WRITE(FBC_CONTROL, fbc_ctl);
127
84f44ce7
VS		 128 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
129 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 130}
131
1fa61106 132static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 133{
134 struct drm_i915_private *dev_priv = dev->dev_private;
135
136 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
137}
138
1fa61106 139static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 140{
141 struct drm_device *dev = crtc->dev;
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 struct drm_framebuffer *fb = crtc->fb;
144 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
145 struct drm_i915_gem_object *obj = intel_fb->obj;
146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
147 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
148 unsigned long stall_watermark = 200;
149 u32 dpfc_ctl;
150
151 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
152 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
153 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
154
155 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
156 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
157 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
158 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
159
160 /* enable it... */
161 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
162
84f44ce7 163 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 164}
165
1fa61106 166static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 167{
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 u32 dpfc_ctl;
170
171 /* Disable compression */
172 dpfc_ctl = I915_READ(DPFC_CONTROL);
173 if (dpfc_ctl & DPFC_CTL_EN) {
174 dpfc_ctl &= ~DPFC_CTL_EN;
175 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
176
177 DRM_DEBUG_KMS("disabled FBC\n");
178 }
179}
180
1fa61106 181static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 182{
183 struct drm_i915_private *dev_priv = dev->dev_private;
184
185 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
186}
187
188static void sandybridge_blit_fbc_update(struct drm_device *dev)
189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 u32 blt_ecoskpd;
192
193 /* Make sure blitter notifies FBC of writes */
194 gen6_gt_force_wake_get(dev_priv);
195 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
196 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
197 GEN6_BLITTER_LOCK_SHIFT;
198 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
199 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
200 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
201 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
202 GEN6_BLITTER_LOCK_SHIFT);
203 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
204 POSTING_READ(GEN6_BLITTER_ECOSKPD);
205 gen6_gt_force_wake_put(dev_priv);
206}
207
1fa61106 208static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 209{
210 struct drm_device *dev = crtc->dev;
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 struct drm_framebuffer *fb = crtc->fb;
213 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
214 struct drm_i915_gem_object *obj = intel_fb->obj;
215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
216 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
217 unsigned long stall_watermark = 200;
218 u32 dpfc_ctl;
219
220 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
221 dpfc_ctl &= DPFC_RESERVED;
222 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
223 /* Set persistent mode for front-buffer rendering, ala X. */
224 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
225 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
226 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
227
228 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
229 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
230 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
231 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 232 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 233 /* enable it... */
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
235
236 if (IS_GEN6(dev)) {
237 I915_WRITE(SNB_DPFC_CTL_SA,
238 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
239 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
240 sandybridge_blit_fbc_update(dev);
241 }
242
84f44ce7 243 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 244}
245
1fa61106 246static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 247{
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 u32 dpfc_ctl;
250
251 /* Disable compression */
252 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
253 if (dpfc_ctl & DPFC_CTL_EN) {
254 dpfc_ctl &= ~DPFC_CTL_EN;
255 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
256
257 DRM_DEBUG_KMS("disabled FBC\n");
258 }
259}
260
1fa61106 261static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266}
267
abe959c7
RV		 268static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269{
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
f343c5f6 277 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
891348b2 283 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 286 } else {
7dd23ba0 287 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 288 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
289 HSW_BYPASS_FBC_QUEUE);
891348b2 290 }
b74ea102 291
abe959c7
RV		 292 I915_WRITE(SNB_DPFC_CTL_SA,
293 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
294 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
295
296 sandybridge_blit_fbc_update(dev);
297
298 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
299}
300
85208be0
ED		 301bool intel_fbc_enabled(struct drm_device *dev)
302{
303 struct drm_i915_private *dev_priv = dev->dev_private;
304
305 if (!dev_priv->display.fbc_enabled)
306 return false;
307
308 return dev_priv->display.fbc_enabled(dev);
309}
310
311static void intel_fbc_work_fn(struct work_struct *__work)
312{
313 struct intel_fbc_work *work =
314 container_of(to_delayed_work(__work),
315 struct intel_fbc_work, work);
316 struct drm_device *dev = work->crtc->dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318
319 mutex_lock(&dev->struct_mutex);
5c3fe8b0 320 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 321 /* Double check that we haven't switched fb without cancelling
322 * the prior work.
323 */
324 if (work->crtc->fb == work->fb) {
325 dev_priv->display.enable_fbc(work->crtc,
326 work->interval);
327
5c3fe8b0
BW		 328 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
329 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
330 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 331 }
332
5c3fe8b0 333 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 334 }
335 mutex_unlock(&dev->struct_mutex);
336
337 kfree(work);
338}
339
340static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
341{
5c3fe8b0 342 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 343 return;
344
345 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
346
347 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 348 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 349 * entirely asynchronously.
350 */
5c3fe8b0 351 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 352 /* tasklet was killed before being run, clean up */
5c3fe8b0 353 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 354
355 /* Mark the work as no longer wanted so that if it does
356 * wake-up (because the work was already running and waiting
357 * for our mutex), it will discover that is no longer
358 * necessary to run.
359 */
5c3fe8b0 360 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 361}
362
b63fb44c 363static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 364{
365 struct intel_fbc_work *work;
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368
369 if (!dev_priv->display.enable_fbc)
370 return;
371
372 intel_cancel_fbc_work(dev_priv);
373
b14c5679 374 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 375 if (work == NULL) {
6cdcb5e7 376 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 377 dev_priv->display.enable_fbc(crtc, interval);
378 return;
379 }
380
381 work->crtc = crtc;
382 work->fb = crtc->fb;
383 work->interval = interval;
384 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
385
5c3fe8b0 386 dev_priv->fbc.fbc_work = work;
85208be0 387
85208be0
ED		 388 /* Delay the actual enabling to let pageflipping cease and the
389 * display to settle before starting the compression. Note that
390 * this delay also serves a second purpose: it allows for a
391 * vblank to pass after disabling the FBC before we attempt
392 * to modify the control registers.
393 *
394 * A more complicated solution would involve tracking vblanks
395 * following the termination of the page-flipping sequence
396 * and indeed performing the enable as a co-routine and not
397 * waiting synchronously upon the vblank.
7457d617
DL		 398 *
399 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 400 */
401 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
402}
403
404void intel_disable_fbc(struct drm_device *dev)
405{
406 struct drm_i915_private *dev_priv = dev->dev_private;
407
408 intel_cancel_fbc_work(dev_priv);
409
410 if (!dev_priv->display.disable_fbc)
411 return;
412
413 dev_priv->display.disable_fbc(dev);
5c3fe8b0 414 dev_priv->fbc.plane = -1;
85208be0
ED		 415}
416
29ebf90f
CW		 417static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
418 enum no_fbc_reason reason)
419{
420 if (dev_priv->fbc.no_fbc_reason == reason)
421 return false;
422
423 dev_priv->fbc.no_fbc_reason = reason;
424 return true;
425}
426
85208be0
ED		 427/**
428 * intel_update_fbc - enable/disable FBC as needed
429 * @dev: the drm_device
430 *
431 * Set up the framebuffer compression hardware at mode set time. We
432 * enable it if possible:
433 * - plane A only (on pre-965)
434 * - no pixel mulitply/line duplication
435 * - no alpha buffer discard
436 * - no dual wide
f85da868 437 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 438 *
439 * We can't assume that any compression will take place (worst case),
440 * so the compressed buffer has to be the same size as the uncompressed
441 * one. It also must reside (along with the line length buffer) in
442 * stolen memory.
443 *
444 * We need to enable/disable FBC on a global basis.
445 */
446void intel_update_fbc(struct drm_device *dev)
447{
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 struct drm_crtc *crtc = NULL, *tmp_crtc;
450 struct intel_crtc *intel_crtc;
451 struct drm_framebuffer *fb;
452 struct intel_framebuffer *intel_fb;
453 struct drm_i915_gem_object *obj;
ef644fda 454 const struct drm_display_mode *adjusted_mode;
37327abd 455 unsigned int max_width, max_height;
85208be0 456
29ebf90f
CW		 457 if (!I915_HAS_FBC(dev)) {
458 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 459 return;
29ebf90f 460 }
85208be0 461
29ebf90f
CW		 462 if (!i915_powersave) {
463 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
464 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 465 return;
29ebf90f 466 }
85208be0
ED		 467
468 /*
469 * If FBC is already on, we just have to verify that we can
470 * keep it that way...
471 * Need to disable if:
472 * - more than one pipe is active
473 * - changing FBC params (stride, fence, mode)
474 * - new fb is too large to fit in compressed buffer
475 * - going to an unsupported config (interlace, pixel multiply, etc.)
476 */
477 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 478 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 479 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 480 if (crtc) {
29ebf90f
CW		 481 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
482 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 483 goto out_disable;
484 }
485 crtc = tmp_crtc;
486 }
487 }
488
489 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 490 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
491 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 492 goto out_disable;
493 }
494
495 intel_crtc = to_intel_crtc(crtc);
496 fb = crtc->fb;
497 intel_fb = to_intel_framebuffer(fb);
498 obj = intel_fb->obj;
ef644fda 499 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 500
8a5729a3
DL		 501 if (i915_enable_fbc < 0 &&
502 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
504 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 505 goto out_disable;
85208be0 506 }
8a5729a3 507 if (!i915_enable_fbc) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
509 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 510 goto out_disable;
511 }
ef644fda
VS		 512 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
513 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 514 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
515 DRM_DEBUG_KMS("mode incompatible with compression, "
516 "disabling\n");
85208be0
ED		 517 goto out_disable;
518 }
f85da868
PZ		 519
520 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 521 max_width = 4096;
522 max_height = 2048;
f85da868 523 } else {
37327abd
VS		 524 max_width = 2048;
525 max_height = 1536;
f85da868 526 }
37327abd
VS		 527 if (intel_crtc->config.pipe_src_w > max_width ||
528 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 529 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
530 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 531 goto out_disable;
532 }
891348b2
RV		 533 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
534 intel_crtc->plane != 0) {
29ebf90f
CW		 535 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
536 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 537 goto out_disable;
538 }
539
540 /* The use of a CPU fence is mandatory in order to detect writes
541 * by the CPU to the scanout and trigger updates to the FBC.
542 */
543 if (obj->tiling_mode != I915_TILING_X ||
544 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 545 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
546 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 547 goto out_disable;
548 }
549
550 /* If the kernel debugger is active, always disable compression */
551 if (in_dbg_master())
552 goto out_disable;
553
11be49eb 554 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 555 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
556 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 557 goto out_disable;
558 }
559
85208be0
ED		 560 /* If the scanout has not changed, don't modify the FBC settings.
561 * Note that we make the fundamental assumption that the fb->obj
562 * cannot be unpinned (and have its GTT offset and fence revoked)
563 * without first being decoupled from the scanout and FBC disabled.
564 */
5c3fe8b0
BW		 565 if (dev_priv->fbc.plane == intel_crtc->plane &&
566 dev_priv->fbc.fb_id == fb->base.id &&
567 dev_priv->fbc.y == crtc->y)
85208be0
ED		 568 return;
569
570 if (intel_fbc_enabled(dev)) {
571 /* We update FBC along two paths, after changing fb/crtc
572 * configuration (modeswitching) and after page-flipping
573 * finishes. For the latter, we know that not only did
574 * we disable the FBC at the start of the page-flip
575 * sequence, but also more than one vblank has passed.
576 *
577 * For the former case of modeswitching, it is possible
578 * to switch between two FBC valid configurations
579 * instantaneously so we do need to disable the FBC
580 * before we can modify its control registers. We also
581 * have to wait for the next vblank for that to take
582 * effect. However, since we delay enabling FBC we can
583 * assume that a vblank has passed since disabling and
584 * that we can safely alter the registers in the deferred
585 * callback.
586 *
587 * In the scenario that we go from a valid to invalid
588 * and then back to valid FBC configuration we have
589 * no strict enforcement that a vblank occurred since
590 * disabling the FBC. However, along all current pipe
591 * disabling paths we do need to wait for a vblank at
592 * some point. And we wait before enabling FBC anyway.
593 */
594 DRM_DEBUG_KMS("disabling active FBC for update\n");
595 intel_disable_fbc(dev);
596 }
597
598 intel_enable_fbc(crtc, 500);
29ebf90f 599 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 600 return;
601
602out_disable:
603 /* Multiple disables should be harmless */
604 if (intel_fbc_enabled(dev)) {
605 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
606 intel_disable_fbc(dev);
607 }
11be49eb 608 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 609}
610
c921aba8
DV		 611static void i915_pineview_get_mem_freq(struct drm_device *dev)
612{
613 drm_i915_private_t *dev_priv = dev->dev_private;
614 u32 tmp;
615
616 tmp = I915_READ(CLKCFG);
617
618 switch (tmp & CLKCFG_FSB_MASK) {
619 case CLKCFG_FSB_533:
620 dev_priv->fsb_freq = 533; /* 133*4 */
621 break;
622 case CLKCFG_FSB_800:
623 dev_priv->fsb_freq = 800; /* 200*4 */
624 break;
625 case CLKCFG_FSB_667:
626 dev_priv->fsb_freq = 667; /* 167*4 */
627 break;
628 case CLKCFG_FSB_400:
629 dev_priv->fsb_freq = 400; /* 100*4 */
630 break;
631 }
632
633 switch (tmp & CLKCFG_MEM_MASK) {
634 case CLKCFG_MEM_533:
635 dev_priv->mem_freq = 533;
636 break;
637 case CLKCFG_MEM_667:
638 dev_priv->mem_freq = 667;
639 break;
640 case CLKCFG_MEM_800:
641 dev_priv->mem_freq = 800;
642 break;
643 }
644
645 /* detect pineview DDR3 setting */
646 tmp = I915_READ(CSHRDDR3CTL);
647 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
648}
649
650static void i915_ironlake_get_mem_freq(struct drm_device *dev)
651{
652 drm_i915_private_t *dev_priv = dev->dev_private;
653 u16 ddrpll, csipll;
654
655 ddrpll = I915_READ16(DDRMPLL1);
656 csipll = I915_READ16(CSIPLL0);
657
658 switch (ddrpll & 0xff) {
659 case 0xc:
660 dev_priv->mem_freq = 800;
661 break;
662 case 0x10:
663 dev_priv->mem_freq = 1066;
664 break;
665 case 0x14:
666 dev_priv->mem_freq = 1333;
667 break;
668 case 0x18:
669 dev_priv->mem_freq = 1600;
670 break;
671 default:
672 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
673 ddrpll & 0xff);
674 dev_priv->mem_freq = 0;
675 break;
676 }
677
20e4d407 678 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 679
680 switch (csipll & 0x3ff) {
681 case 0x00c:
682 dev_priv->fsb_freq = 3200;
683 break;
684 case 0x00e:
685 dev_priv->fsb_freq = 3733;
686 break;
687 case 0x010:
688 dev_priv->fsb_freq = 4266;
689 break;
690 case 0x012:
691 dev_priv->fsb_freq = 4800;
692 break;
693 case 0x014:
694 dev_priv->fsb_freq = 5333;
695 break;
696 case 0x016:
697 dev_priv->fsb_freq = 5866;
698 break;
699 case 0x018:
700 dev_priv->fsb_freq = 6400;
701 break;
702 default:
703 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
704 csipll & 0x3ff);
705 dev_priv->fsb_freq = 0;
706 break;
707 }
708
709 if (dev_priv->fsb_freq == 3200) {
20e4d407 710 dev_priv->ips.c_m = 0;
c921aba8 711 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 712 dev_priv->ips.c_m = 1;
c921aba8 713 } else {
20e4d407 714 dev_priv->ips.c_m = 2;
c921aba8
DV		 715 }
716}
717
b445e3b0
ED		 718static const struct cxsr_latency cxsr_latency_table[] = {
719 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
720 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
721 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
722 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
723 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
724
725 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
726 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
727 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
728 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
729 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
730
731 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
732 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
733 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
734 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
735 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
736
737 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
738 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
739 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
740 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
741 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
742
743 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
744 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
745 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
746 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
747 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
748
749 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
750 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
751 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
752 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
753 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
754};
755
63c62275 756static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 757 int is_ddr3,
758 int fsb,
759 int mem)
760{
761 const struct cxsr_latency *latency;
762 int i;
763
764 if (fsb == 0 || mem == 0)
765 return NULL;
766
767 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
768 latency = &cxsr_latency_table[i];
769 if (is_desktop == latency->is_desktop &&
770 is_ddr3 == latency->is_ddr3 &&
771 fsb == latency->fsb_freq && mem == latency->mem_freq)
772 return latency;
773 }
774
775 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
776
777 return NULL;
778}
779
1fa61106 780static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 781{
782 struct drm_i915_private *dev_priv = dev->dev_private;
783
784 /* deactivate cxsr */
785 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
786}
787
788/*
789 * Latency for FIFO fetches is dependent on several factors:
790 * - memory configuration (speed, channels)
791 * - chipset
792 * - current MCH state
793 * It can be fairly high in some situations, so here we assume a fairly
794 * pessimal value. It's a tradeoff between extra memory fetches (if we
795 * set this value too high, the FIFO will fetch frequently to stay full)
796 * and power consumption (set it too low to save power and we might see
797 * FIFO underruns and display "flicker").
798 *
799 * A value of 5us seems to be a good balance; safe for very low end
800 * platforms but not overly aggressive on lower latency configs.
801 */
802static const int latency_ns = 5000;
803
1fa61106 804static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 805{
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 uint32_t dsparb = I915_READ(DSPARB);
808 int size;
809
810 size = dsparb & 0x7f;
811 if (plane)
812 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
813
814 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
815 plane ? "B" : "A", size);
816
817 return size;
818}
819
1fa61106 820static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 821{
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t dsparb = I915_READ(DSPARB);
824 int size;
825
826 size = dsparb & 0x1ff;
827 if (plane)
828 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
829 size >>= 1; /* Convert to cachelines */
830
831 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
832 plane ? "B" : "A", size);
833
834 return size;
835}
836
1fa61106 837static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 838{
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 uint32_t dsparb = I915_READ(DSPARB);
841 int size;
842
843 size = dsparb & 0x7f;
844 size >>= 2; /* Convert to cachelines */
845
846 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
847 plane ? "B" : "A",
848 size);
849
850 return size;
851}
852
1fa61106 853static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 uint32_t dsparb = I915_READ(DSPARB);
857 int size;
858
859 size = dsparb & 0x7f;
860 size >>= 1; /* Convert to cachelines */
861
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
863 plane ? "B" : "A", size);
864
865 return size;
866}
867
868/* Pineview has different values for various configs */
869static const struct intel_watermark_params pineview_display_wm = {
870 PINEVIEW_DISPLAY_FIFO,
871 PINEVIEW_MAX_WM,
872 PINEVIEW_DFT_WM,
873 PINEVIEW_GUARD_WM,
874 PINEVIEW_FIFO_LINE_SIZE
875};
876static const struct intel_watermark_params pineview_display_hplloff_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_HPLLOFF_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params pineview_cursor_wm = {
884 PINEVIEW_CURSOR_FIFO,
885 PINEVIEW_CURSOR_MAX_WM,
886 PINEVIEW_CURSOR_DFT_WM,
887 PINEVIEW_CURSOR_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE,
889};
890static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE
896};
897static const struct intel_watermark_params g4x_wm_info = {
898 G4X_FIFO_SIZE,
899 G4X_MAX_WM,
900 G4X_MAX_WM,
901 2,
902 G4X_FIFO_LINE_SIZE,
903};
904static const struct intel_watermark_params g4x_cursor_wm_info = {
905 I965_CURSOR_FIFO,
906 I965_CURSOR_MAX_WM,
907 I965_CURSOR_DFT_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910};
911static const struct intel_watermark_params valleyview_wm_info = {
912 VALLEYVIEW_FIFO_SIZE,
913 VALLEYVIEW_MAX_WM,
914 VALLEYVIEW_MAX_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917};
918static const struct intel_watermark_params valleyview_cursor_wm_info = {
919 I965_CURSOR_FIFO,
920 VALLEYVIEW_CURSOR_MAX_WM,
921 I965_CURSOR_DFT_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924};
925static const struct intel_watermark_params i965_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 I965_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 I915_FIFO_LINE_SIZE,
931};
932static const struct intel_watermark_params i945_wm_info = {
933 I945_FIFO_SIZE,
934 I915_MAX_WM,
935 1,
936 2,
937 I915_FIFO_LINE_SIZE
938};
939static const struct intel_watermark_params i915_wm_info = {
940 I915_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945};
946static const struct intel_watermark_params i855_wm_info = {
947 I855GM_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I830_FIFO_LINE_SIZE
952};
953static const struct intel_watermark_params i830_wm_info = {
954 I830_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959};
960
961static const struct intel_watermark_params ironlake_display_wm_info = {
962 ILK_DISPLAY_FIFO,
963 ILK_DISPLAY_MAXWM,
964 ILK_DISPLAY_DFTWM,
965 2,
966 ILK_FIFO_LINE_SIZE
967};
968static const struct intel_watermark_params ironlake_cursor_wm_info = {
969 ILK_CURSOR_FIFO,
970 ILK_CURSOR_MAXWM,
971 ILK_CURSOR_DFTWM,
972 2,
973 ILK_FIFO_LINE_SIZE
974};
975static const struct intel_watermark_params ironlake_display_srwm_info = {
976 ILK_DISPLAY_SR_FIFO,
977 ILK_DISPLAY_MAX_SRWM,
978 ILK_DISPLAY_DFT_SRWM,
979 2,
980 ILK_FIFO_LINE_SIZE
981};
982static const struct intel_watermark_params ironlake_cursor_srwm_info = {
983 ILK_CURSOR_SR_FIFO,
984 ILK_CURSOR_MAX_SRWM,
985 ILK_CURSOR_DFT_SRWM,
986 2,
987 ILK_FIFO_LINE_SIZE
988};
989
990static const struct intel_watermark_params sandybridge_display_wm_info = {
991 SNB_DISPLAY_FIFO,
992 SNB_DISPLAY_MAXWM,
993 SNB_DISPLAY_DFTWM,
994 2,
995 SNB_FIFO_LINE_SIZE
996};
997static const struct intel_watermark_params sandybridge_cursor_wm_info = {
998 SNB_CURSOR_FIFO,
999 SNB_CURSOR_MAXWM,
1000 SNB_CURSOR_DFTWM,
1001 2,
1002 SNB_FIFO_LINE_SIZE
1003};
1004static const struct intel_watermark_params sandybridge_display_srwm_info = {
1005 SNB_DISPLAY_SR_FIFO,
1006 SNB_DISPLAY_MAX_SRWM,
1007 SNB_DISPLAY_DFT_SRWM,
1008 2,
1009 SNB_FIFO_LINE_SIZE
1010};
1011static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1012 SNB_CURSOR_SR_FIFO,
1013 SNB_CURSOR_MAX_SRWM,
1014 SNB_CURSOR_DFT_SRWM,
1015 2,
1016 SNB_FIFO_LINE_SIZE
1017};
1018
1019
1020/**
1021 * intel_calculate_wm - calculate watermark level
1022 * @clock_in_khz: pixel clock
1023 * @wm: chip FIFO params
1024 * @pixel_size: display pixel size
1025 * @latency_ns: memory latency for the platform
1026 *
1027 * Calculate the watermark level (the level at which the display plane will
1028 * start fetching from memory again). Each chip has a different display
1029 * FIFO size and allocation, so the caller needs to figure that out and pass
1030 * in the correct intel_watermark_params structure.
1031 *
1032 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1033 * on the pixel size. When it reaches the watermark level, it'll start
1034 * fetching FIFO line sized based chunks from memory until the FIFO fills
1035 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1036 * will occur, and a display engine hang could result.
1037 */
1038static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1039 const struct intel_watermark_params *wm,
1040 int fifo_size,
1041 int pixel_size,
1042 unsigned long latency_ns)
1043{
1044 long entries_required, wm_size;
1045
1046 /*
1047 * Note: we need to make sure we don't overflow for various clock &
1048 * latency values.
1049 * clocks go from a few thousand to several hundred thousand.
1050 * latency is usually a few thousand
1051 */
1052 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1053 1000;
1054 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1055
1056 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1057
1058 wm_size = fifo_size - (entries_required + wm->guard_size);
1059
1060 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1061
1062 /* Don't promote wm_size to unsigned... */
1063 if (wm_size > (long)wm->max_wm)
1064 wm_size = wm->max_wm;
1065 if (wm_size <= 0)
1066 wm_size = wm->default_wm;
1067 return wm_size;
1068}
1069
1070static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1071{
1072 struct drm_crtc *crtc, *enabled = NULL;
1073
1074 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1075 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1076 if (enabled)
1077 return NULL;
1078 enabled = crtc;
1079 }
1080 }
1081
1082 return enabled;
1083}
1084
46ba614c 1085static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1086{
46ba614c 1087 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1088 struct drm_i915_private *dev_priv = dev->dev_private;
1089 struct drm_crtc *crtc;
1090 const struct cxsr_latency *latency;
1091 u32 reg;
1092 unsigned long wm;
1093
1094 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1095 dev_priv->fsb_freq, dev_priv->mem_freq);
1096 if (!latency) {
1097 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1098 pineview_disable_cxsr(dev);
1099 return;
1100 }
1101
1102 crtc = single_enabled_crtc(dev);
1103 if (crtc) {
241bfc38 1104 const struct drm_display_mode *adjusted_mode;
b445e3b0 1105 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1106 int clock;
1107
1108 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1109 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157}
1158
1159static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167{
1168 struct drm_crtc *crtc;
4fe8590a 1169 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1170 int htotal, hdisplay, clock, pixel_size;
1171 int line_time_us, line_count;
1172 int entries, tlb_miss;
1173
1174 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1175 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1176 *cursor_wm = cursor->guard_size;
1177 *plane_wm = display->guard_size;
1178 return false;
1179 }
1180
4fe8590a 1181 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1182 clock = adjusted_mode->crtc_clock;
4fe8590a 1183 htotal = adjusted_mode->htotal;
37327abd 1184 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1185 pixel_size = crtc->fb->bits_per_pixel / 8;
1186
1187 /* Use the small buffer method to calculate plane watermark */
1188 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1189 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1190 if (tlb_miss > 0)
1191 entries += tlb_miss;
1192 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1193 *plane_wm = entries + display->guard_size;
1194 if (*plane_wm > (int)display->max_wm)
1195 *plane_wm = display->max_wm;
1196
1197 /* Use the large buffer method to calculate cursor watermark */
1198 line_time_us = ((htotal * 1000) / clock);
1199 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1200 entries = line_count * 64 * pixel_size;
1201 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1202 if (tlb_miss > 0)
1203 entries += tlb_miss;
1204 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1205 *cursor_wm = entries + cursor->guard_size;
1206 if (*cursor_wm > (int)cursor->max_wm)
1207 *cursor_wm = (int)cursor->max_wm;
1208
1209 return true;
1210}
1211
1212/*
1213 * Check the wm result.
1214 *
1215 * If any calculated watermark values is larger than the maximum value that
1216 * can be programmed into the associated watermark register, that watermark
1217 * must be disabled.
1218 */
1219static bool g4x_check_srwm(struct drm_device *dev,
1220 int display_wm, int cursor_wm,
1221 const struct intel_watermark_params *display,
1222 const struct intel_watermark_params *cursor)
1223{
1224 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1225 display_wm, cursor_wm);
1226
1227 if (display_wm > display->max_wm) {
1228 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1229 display_wm, display->max_wm);
1230 return false;
1231 }
1232
1233 if (cursor_wm > cursor->max_wm) {
1234 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1235 cursor_wm, cursor->max_wm);
1236 return false;
1237 }
1238
1239 if (!(display_wm || cursor_wm)) {
1240 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1241 return false;
1242 }
1243
1244 return true;
1245}
1246
1247static bool g4x_compute_srwm(struct drm_device *dev,
1248 int plane,
1249 int latency_ns,
1250 const struct intel_watermark_params *display,
1251 const struct intel_watermark_params *cursor,
1252 int *display_wm, int *cursor_wm)
1253{
1254 struct drm_crtc *crtc;
4fe8590a 1255 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1256 int hdisplay, htotal, pixel_size, clock;
1257 unsigned long line_time_us;
1258 int line_count, line_size;
1259 int small, large;
1260 int entries;
1261
1262 if (!latency_ns) {
1263 *display_wm = *cursor_wm = 0;
1264 return false;
1265 }
1266
1267 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1268 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1269 clock = adjusted_mode->crtc_clock;
4fe8590a 1270 htotal = adjusted_mode->htotal;
37327abd 1271 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1272 pixel_size = crtc->fb->bits_per_pixel / 8;
1273
1274 line_time_us = (htotal * 1000) / clock;
1275 line_count = (latency_ns / line_time_us + 1000) / 1000;
1276 line_size = hdisplay * pixel_size;
1277
1278 /* Use the minimum of the small and large buffer method for primary */
1279 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1280 large = line_count * line_size;
1281
1282 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1283 *display_wm = entries + display->guard_size;
1284
1285 /* calculate the self-refresh watermark for display cursor */
1286 entries = line_count * pixel_size * 64;
1287 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1288 *cursor_wm = entries + cursor->guard_size;
1289
1290 return g4x_check_srwm(dev,
1291 *display_wm, *cursor_wm,
1292 display, cursor);
1293}
1294
1295static bool vlv_compute_drain_latency(struct drm_device *dev,
1296 int plane,
1297 int *plane_prec_mult,
1298 int *plane_dl,
1299 int *cursor_prec_mult,
1300 int *cursor_dl)
1301{
1302 struct drm_crtc *crtc;
1303 int clock, pixel_size;
1304 int entries;
1305
1306 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1307 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1308 return false;
1309
241bfc38 1310 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1311 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1312
1313 entries = (clock / 1000) * pixel_size;
1314 *plane_prec_mult = (entries > 256) ?
1315 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1316 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1317 pixel_size);
1318
1319 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1320 *cursor_prec_mult = (entries > 256) ?
1321 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1322 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1323
1324 return true;
1325}
1326
1327/*
1328 * Update drain latency registers of memory arbiter
1329 *
1330 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1331 * to be programmed. Each plane has a drain latency multiplier and a drain
1332 * latency value.
1333 */
1334
1335static void vlv_update_drain_latency(struct drm_device *dev)
1336{
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1339 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1340 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1341 either 16 or 32 */
1342
1343 /* For plane A, Cursor A */
1344 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1345 &cursor_prec_mult, &cursora_dl)) {
1346 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1347 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1348 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1349 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1350
1351 I915_WRITE(VLV_DDL1, cursora_prec |
1352 (cursora_dl << DDL_CURSORA_SHIFT) |
1353 planea_prec | planea_dl);
1354 }
1355
1356 /* For plane B, Cursor B */
1357 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1358 &cursor_prec_mult, &cursorb_dl)) {
1359 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1360 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1361 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1362 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1363
1364 I915_WRITE(VLV_DDL2, cursorb_prec |
1365 (cursorb_dl << DDL_CURSORB_SHIFT) |
1366 planeb_prec | planeb_dl);
1367 }
1368}
1369
1370#define single_plane_enabled(mask) is_power_of_2(mask)
1371
46ba614c 1372static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1373{
46ba614c 1374 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1375 static const int sr_latency_ns = 12000;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1378 int plane_sr, cursor_sr;
af6c4575 1379 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1380 unsigned int enabled = 0;
1381
1382 vlv_update_drain_latency(dev);
1383
51cea1f4 1384 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1385 &valleyview_wm_info, latency_ns,
1386 &valleyview_cursor_wm_info, latency_ns,
1387 &planea_wm, &cursora_wm))
51cea1f4 1388 enabled |= 1 << PIPE_A;
b445e3b0 1389
51cea1f4 1390 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1391 &valleyview_wm_info, latency_ns,
1392 &valleyview_cursor_wm_info, latency_ns,
1393 &planeb_wm, &cursorb_wm))
51cea1f4 1394 enabled |= 1 << PIPE_B;
b445e3b0 1395
b445e3b0
ED		 1396 if (single_plane_enabled(enabled) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
af6c4575
CW		 1401 &plane_sr, &ignore_cursor_sr) &&
1402 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 2*sr_latency_ns,
1404 &valleyview_wm_info,
1405 &valleyview_cursor_wm_info,
52bd02d8 1406 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1407 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1408 } else {
b445e3b0
ED		 1409 I915_WRITE(FW_BLC_SELF_VLV,
1410 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1411 plane_sr = cursor_sr = 0;
1412 }
b445e3b0
ED		 1413
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm, cursora_wm,
1416 planeb_wm, cursorb_wm,
1417 plane_sr, cursor_sr);
1418
1419 I915_WRITE(DSPFW1,
1420 (plane_sr << DSPFW_SR_SHIFT) |
1421 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1422 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1423 planea_wm);
1424 I915_WRITE(DSPFW2,
8c919b28 1425 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1426 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 I915_WRITE(DSPFW3,
8c919b28
CW		 1428 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1429 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1430}
1431
46ba614c 1432static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1433{
46ba614c 1434 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1435 static const int sr_latency_ns = 12000;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1438 int plane_sr, cursor_sr;
1439 unsigned int enabled = 0;
1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planea_wm, &cursora_wm))
51cea1f4 1445 enabled |= 1 << PIPE_A;
b445e3b0 1446
51cea1f4 1447 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1448 &g4x_wm_info, latency_ns,
1449 &g4x_cursor_wm_info, latency_ns,
1450 &planeb_wm, &cursorb_wm))
51cea1f4 1451 enabled |= 1 << PIPE_B;
b445e3b0 1452
b445e3b0
ED		 1453 if (single_plane_enabled(enabled) &&
1454 g4x_compute_srwm(dev, ffs(enabled) - 1,
1455 sr_latency_ns,
1456 &g4x_wm_info,
1457 &g4x_cursor_wm_info,
52bd02d8 1458 &plane_sr, &cursor_sr)) {
b445e3b0 1459 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1460 } else {
b445e3b0
ED		 1461 I915_WRITE(FW_BLC_SELF,
1462 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1463 plane_sr = cursor_sr = 0;
1464 }
b445e3b0
ED		 1465
1466 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1467 planea_wm, cursora_wm,
1468 planeb_wm, cursorb_wm,
1469 plane_sr, cursor_sr);
1470
1471 I915_WRITE(DSPFW1,
1472 (plane_sr << DSPFW_SR_SHIFT) |
1473 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1474 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1475 planea_wm);
1476 I915_WRITE(DSPFW2,
8c919b28 1477 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1478 (cursora_wm << DSPFW_CURSORA_SHIFT));
1479 /* HPLL off in SR has some issues on G4x... disable it */
1480 I915_WRITE(DSPFW3,
8c919b28 1481 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1482 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1483}
1484
46ba614c 1485static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1486{
46ba614c 1487 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct drm_crtc *crtc;
1490 int srwm = 1;
1491 int cursor_sr = 16;
1492
1493 /* Calc sr entries for one plane configs */
1494 crtc = single_enabled_crtc(dev);
1495 if (crtc) {
1496 /* self-refresh has much higher latency */
1497 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1498 const struct drm_display_mode *adjusted_mode =
1499 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1500 int clock = adjusted_mode->crtc_clock;
4fe8590a 1501 int htotal = adjusted_mode->htotal;
37327abd 1502 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1503 int pixel_size = crtc->fb->bits_per_pixel / 8;
1504 unsigned long line_time_us;
1505 int entries;
1506
1507 line_time_us = ((htotal * 1000) / clock);
1508
1509 /* Use ns/us then divide to preserve precision */
1510 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1511 pixel_size * hdisplay;
1512 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1513 srwm = I965_FIFO_SIZE - entries;
1514 if (srwm < 0)
1515 srwm = 1;
1516 srwm &= 0x1ff;
1517 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1518 entries, srwm);
1519
1520 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 pixel_size * 64;
1522 entries = DIV_ROUND_UP(entries,
1523 i965_cursor_wm_info.cacheline_size);
1524 cursor_sr = i965_cursor_wm_info.fifo_size -
1525 (entries + i965_cursor_wm_info.guard_size);
1526
1527 if (cursor_sr > i965_cursor_wm_info.max_wm)
1528 cursor_sr = i965_cursor_wm_info.max_wm;
1529
1530 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1531 "cursor %d\n", srwm, cursor_sr);
1532
1533 if (IS_CRESTLINE(dev))
1534 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1535 } else {
1536 /* Turn off self refresh if both pipes are enabled */
1537 if (IS_CRESTLINE(dev))
1538 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1539 & ~FW_BLC_SELF_EN);
1540 }
1541
1542 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1543 srwm);
1544
1545 /* 965 has limitations... */
1546 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1547 (8 << 16) | (8 << 8) | (8 << 0));
1548 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1549 /* update cursor SR watermark */
1550 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1551}
1552
46ba614c 1553static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1554{
46ba614c 1555 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 const struct intel_watermark_params *wm_info;
1558 uint32_t fwater_lo;
1559 uint32_t fwater_hi;
1560 int cwm, srwm = 1;
1561 int fifo_size;
1562 int planea_wm, planeb_wm;
1563 struct drm_crtc *crtc, *enabled = NULL;
1564
1565 if (IS_I945GM(dev))
1566 wm_info = &i945_wm_info;
1567 else if (!IS_GEN2(dev))
1568 wm_info = &i915_wm_info;
1569 else
1570 wm_info = &i855_wm_info;
1571
1572 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1573 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1574 if (intel_crtc_active(crtc)) {
241bfc38 1575 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1576 int cpp = crtc->fb->bits_per_pixel / 8;
1577 if (IS_GEN2(dev))
1578 cpp = 4;
1579
241bfc38
DL		 1580 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1581 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1582 wm_info, fifo_size, cpp,
b445e3b0
ED		 1583 latency_ns);
1584 enabled = crtc;
1585 } else
1586 planea_wm = fifo_size - wm_info->guard_size;
1587
1588 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1589 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1590 if (intel_crtc_active(crtc)) {
241bfc38 1591 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1592 int cpp = crtc->fb->bits_per_pixel / 8;
1593 if (IS_GEN2(dev))
1594 cpp = 4;
1595
241bfc38
DL		 1596 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1597 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1598 wm_info, fifo_size, cpp,
b445e3b0
ED		 1599 latency_ns);
1600 if (enabled == NULL)
1601 enabled = crtc;
1602 else
1603 enabled = NULL;
1604 } else
1605 planeb_wm = fifo_size - wm_info->guard_size;
1606
1607 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1608
1609 /*
1610 * Overlay gets an aggressive default since video jitter is bad.
1611 */
1612 cwm = 2;
1613
1614 /* Play safe and disable self-refresh before adjusting watermarks. */
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1619
1620 /* Calc sr entries for one plane configs */
1621 if (HAS_FW_BLC(dev) && enabled) {
1622 /* self-refresh has much higher latency */
1623 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1624 const struct drm_display_mode *adjusted_mode =
1625 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1626 int clock = adjusted_mode->crtc_clock;
4fe8590a 1627 int htotal = adjusted_mode->htotal;
37327abd 1628 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1629 int pixel_size = enabled->fb->bits_per_pixel / 8;
1630 unsigned long line_time_us;
1631 int entries;
1632
1633 line_time_us = (htotal * 1000) / clock;
1634
1635 /* Use ns/us then divide to preserve precision */
1636 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1637 pixel_size * hdisplay;
1638 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1639 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1640 srwm = wm_info->fifo_size - entries;
1641 if (srwm < 0)
1642 srwm = 1;
1643
1644 if (IS_I945G(dev) || IS_I945GM(dev))
1645 I915_WRITE(FW_BLC_SELF,
1646 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1647 else if (IS_I915GM(dev))
1648 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1649 }
1650
1651 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1652 planea_wm, planeb_wm, cwm, srwm);
1653
1654 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1655 fwater_hi = (cwm & 0x1f);
1656
1657 /* Set request length to 8 cachelines per fetch */
1658 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1659 fwater_hi = fwater_hi | (1 << 8);
1660
1661 I915_WRITE(FW_BLC, fwater_lo);
1662 I915_WRITE(FW_BLC2, fwater_hi);
1663
1664 if (HAS_FW_BLC(dev)) {
1665 if (enabled) {
1666 if (IS_I945G(dev) || IS_I945GM(dev))
1667 I915_WRITE(FW_BLC_SELF,
1668 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1669 else if (IS_I915GM(dev))
1670 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1671 DRM_DEBUG_KMS("memory self refresh enabled\n");
1672 } else
1673 DRM_DEBUG_KMS("memory self refresh disabled\n");
1674 }
1675}
1676
46ba614c 1677static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1678{
46ba614c 1679 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 struct drm_crtc *crtc;
241bfc38 1682 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1683 uint32_t fwater_lo;
1684 int planea_wm;
1685
1686 crtc = single_enabled_crtc(dev);
1687 if (crtc == NULL)
1688 return;
1689
241bfc38
DL		 1690 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1691 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1692 &i830_wm_info,
b445e3b0 1693 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1694 4, latency_ns);
b445e3b0
ED		 1695 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1696 fwater_lo |= (3<<8) | planea_wm;
1697
1698 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1699
1700 I915_WRITE(FW_BLC, fwater_lo);
1701}
1702
b445e3b0
ED		 1703/*
1704 * Check the wm result.
1705 *
1706 * If any calculated watermark values is larger than the maximum value that
1707 * can be programmed into the associated watermark register, that watermark
1708 * must be disabled.
1709 */
1710static bool ironlake_check_srwm(struct drm_device *dev, int level,
1711 int fbc_wm, int display_wm, int cursor_wm,
1712 const struct intel_watermark_params *display,
1713 const struct intel_watermark_params *cursor)
1714{
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1718 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1719
1720 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1721 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1722 fbc_wm, SNB_FBC_MAX_SRWM, level);
1723
1724 /* fbc has it's own way to disable FBC WM */
1725 I915_WRITE(DISP_ARB_CTL,
1726 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1727 return false;
615aaa5f
VS		 1728 } else if (INTEL_INFO(dev)->gen >= 6) {
1729 /* enable FBC WM (except on ILK, where it must remain off) */
1730 I915_WRITE(DISP_ARB_CTL,
1731 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1732 }
1733
1734 if (display_wm > display->max_wm) {
1735 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1736 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1737 return false;
1738 }
1739
1740 if (cursor_wm > cursor->max_wm) {
1741 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1742 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1743 return false;
1744 }
1745
1746 if (!(fbc_wm || display_wm || cursor_wm)) {
1747 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1748 return false;
1749 }
1750
1751 return true;
1752}
1753
1754/*
1755 * Compute watermark values of WM[1-3],
1756 */
1757static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1758 int latency_ns,
1759 const struct intel_watermark_params *display,
1760 const struct intel_watermark_params *cursor,
1761 int *fbc_wm, int *display_wm, int *cursor_wm)
1762{
1763 struct drm_crtc *crtc;
4fe8590a 1764 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1765 unsigned long line_time_us;
1766 int hdisplay, htotal, pixel_size, clock;
1767 int line_count, line_size;
1768 int small, large;
1769 int entries;
1770
1771 if (!latency_ns) {
1772 *fbc_wm = *display_wm = *cursor_wm = 0;
1773 return false;
1774 }
1775
1776 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1777 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1778 clock = adjusted_mode->crtc_clock;
4fe8590a 1779 htotal = adjusted_mode->htotal;
37327abd 1780 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1781 pixel_size = crtc->fb->bits_per_pixel / 8;
1782
1783 line_time_us = (htotal * 1000) / clock;
1784 line_count = (latency_ns / line_time_us + 1000) / 1000;
1785 line_size = hdisplay * pixel_size;
1786
1787 /* Use the minimum of the small and large buffer method for primary */
1788 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1789 large = line_count * line_size;
1790
1791 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1792 *display_wm = entries + display->guard_size;
1793
1794 /*
1795 * Spec says:
1796 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1797 */
1798 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1799
1800 /* calculate the self-refresh watermark for display cursor */
1801 entries = line_count * pixel_size * 64;
1802 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1803 *cursor_wm = entries + cursor->guard_size;
1804
1805 return ironlake_check_srwm(dev, level,
1806 *fbc_wm, *display_wm, *cursor_wm,
1807 display, cursor);
1808}
1809
46ba614c 1810static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1811{
46ba614c 1812 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 int fbc_wm, plane_wm, cursor_wm;
1815 unsigned int enabled;
1816
1817 enabled = 0;
51cea1f4 1818 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1819 &ironlake_display_wm_info,
b0aea5dc 1820 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1821 &ironlake_cursor_wm_info,
b0aea5dc 1822 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1823 &plane_wm, &cursor_wm)) {
1824 I915_WRITE(WM0_PIPEA_ILK,
1825 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1826 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1827 " plane %d, " "cursor: %d\n",
1828 plane_wm, cursor_wm);
51cea1f4 1829 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1830 }
1831
51cea1f4 1832 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1833 &ironlake_display_wm_info,
b0aea5dc 1834 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1835 &ironlake_cursor_wm_info,
b0aea5dc 1836 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1837 &plane_wm, &cursor_wm)) {
1838 I915_WRITE(WM0_PIPEB_ILK,
1839 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1840 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1841 " plane %d, cursor: %d\n",
1842 plane_wm, cursor_wm);
51cea1f4 1843 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1844 }
1845
1846 /*
1847 * Calculate and update the self-refresh watermark only when one
1848 * display plane is used.
1849 */
1850 I915_WRITE(WM3_LP_ILK, 0);
1851 I915_WRITE(WM2_LP_ILK, 0);
1852 I915_WRITE(WM1_LP_ILK, 0);
1853
1854 if (!single_plane_enabled(enabled))
1855 return;
1856 enabled = ffs(enabled) - 1;
1857
1858 /* WM1 */
1859 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1860 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1861 &ironlake_display_srwm_info,
1862 &ironlake_cursor_srwm_info,
1863 &fbc_wm, &plane_wm, &cursor_wm))
1864 return;
1865
1866 I915_WRITE(WM1_LP_ILK,
1867 WM1_LP_SR_EN |
b0aea5dc 1868 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1869 (fbc_wm << WM1_LP_FBC_SHIFT) |
1870 (plane_wm << WM1_LP_SR_SHIFT) |
1871 cursor_wm);
1872
1873 /* WM2 */
1874 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1875 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1876 &ironlake_display_srwm_info,
1877 &ironlake_cursor_srwm_info,
1878 &fbc_wm, &plane_wm, &cursor_wm))
1879 return;
1880
1881 I915_WRITE(WM2_LP_ILK,
1882 WM2_LP_EN |
b0aea5dc 1883 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1884 (fbc_wm << WM1_LP_FBC_SHIFT) |
1885 (plane_wm << WM1_LP_SR_SHIFT) |
1886 cursor_wm);
1887
1888 /*
1889 * WM3 is unsupported on ILK, probably because we don't have latency
1890 * data for that power state
1891 */
1892}
1893
46ba614c 1894static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1895{
46ba614c 1896 struct drm_device *dev = crtc->dev;
b445e3b0 1897 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1898 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1899 u32 val;
1900 int fbc_wm, plane_wm, cursor_wm;
1901 unsigned int enabled;
1902
1903 enabled = 0;
51cea1f4 1904 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1905 &sandybridge_display_wm_info, latency,
1906 &sandybridge_cursor_wm_info, latency,
1907 &plane_wm, &cursor_wm)) {
1908 val = I915_READ(WM0_PIPEA_ILK);
1909 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1910 I915_WRITE(WM0_PIPEA_ILK, val |
1911 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1912 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1913 " plane %d, " "cursor: %d\n",
1914 plane_wm, cursor_wm);
51cea1f4 1915 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1916 }
1917
51cea1f4 1918 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1919 &sandybridge_display_wm_info, latency,
1920 &sandybridge_cursor_wm_info, latency,
1921 &plane_wm, &cursor_wm)) {
1922 val = I915_READ(WM0_PIPEB_ILK);
1923 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1924 I915_WRITE(WM0_PIPEB_ILK, val |
1925 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1926 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1927 " plane %d, cursor: %d\n",
1928 plane_wm, cursor_wm);
51cea1f4 1929 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1930 }
1931
c43d0188
CW		 1932 /*
1933 * Calculate and update the self-refresh watermark only when one
1934 * display plane is used.
1935 *
1936 * SNB support 3 levels of watermark.
1937 *
1938 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1939 * and disabled in the descending order
1940 *
1941 */
1942 I915_WRITE(WM3_LP_ILK, 0);
1943 I915_WRITE(WM2_LP_ILK, 0);
1944 I915_WRITE(WM1_LP_ILK, 0);
1945
1946 if (!single_plane_enabled(enabled) ||
1947 dev_priv->sprite_scaling_enabled)
1948 return;
1949 enabled = ffs(enabled) - 1;
1950
1951 /* WM1 */
1952 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1953 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1954 &sandybridge_display_srwm_info,
1955 &sandybridge_cursor_srwm_info,
1956 &fbc_wm, &plane_wm, &cursor_wm))
1957 return;
1958
1959 I915_WRITE(WM1_LP_ILK,
1960 WM1_LP_SR_EN |
b0aea5dc 1961 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1962 (fbc_wm << WM1_LP_FBC_SHIFT) |
1963 (plane_wm << WM1_LP_SR_SHIFT) |
1964 cursor_wm);
1965
1966 /* WM2 */
1967 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1968 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1969 &sandybridge_display_srwm_info,
1970 &sandybridge_cursor_srwm_info,
1971 &fbc_wm, &plane_wm, &cursor_wm))
1972 return;
1973
1974 I915_WRITE(WM2_LP_ILK,
1975 WM2_LP_EN |
b0aea5dc 1976 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1977 (fbc_wm << WM1_LP_FBC_SHIFT) |
1978 (plane_wm << WM1_LP_SR_SHIFT) |
1979 cursor_wm);
1980
1981 /* WM3 */
1982 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1983 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1984 &sandybridge_display_srwm_info,
1985 &sandybridge_cursor_srwm_info,
1986 &fbc_wm, &plane_wm, &cursor_wm))
1987 return;
1988
1989 I915_WRITE(WM3_LP_ILK,
1990 WM3_LP_EN |
b0aea5dc 1991 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1992 (fbc_wm << WM1_LP_FBC_SHIFT) |
1993 (plane_wm << WM1_LP_SR_SHIFT) |
1994 cursor_wm);
1995}
1996
46ba614c 1997static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 1998{
46ba614c 1999 struct drm_device *dev = crtc->dev;
c43d0188 2000 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2001 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2002 u32 val;
2003 int fbc_wm, plane_wm, cursor_wm;
2004 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2005 unsigned int enabled;
2006
2007 enabled = 0;
51cea1f4 2008 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2009 &sandybridge_display_wm_info, latency,
2010 &sandybridge_cursor_wm_info, latency,
2011 &plane_wm, &cursor_wm)) {
2012 val = I915_READ(WM0_PIPEA_ILK);
2013 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2014 I915_WRITE(WM0_PIPEA_ILK, val |
2015 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2016 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2017 " plane %d, " "cursor: %d\n",
2018 plane_wm, cursor_wm);
51cea1f4 2019 enabled |= 1 << PIPE_A;
c43d0188
CW		 2020 }
2021
51cea1f4 2022 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2023 &sandybridge_display_wm_info, latency,
2024 &sandybridge_cursor_wm_info, latency,
2025 &plane_wm, &cursor_wm)) {
2026 val = I915_READ(WM0_PIPEB_ILK);
2027 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2028 I915_WRITE(WM0_PIPEB_ILK, val |
2029 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2030 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2031 " plane %d, cursor: %d\n",
2032 plane_wm, cursor_wm);
51cea1f4 2033 enabled |= 1 << PIPE_B;
c43d0188
CW		 2034 }
2035
51cea1f4 2036 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2037 &sandybridge_display_wm_info, latency,
2038 &sandybridge_cursor_wm_info, latency,
2039 &plane_wm, &cursor_wm)) {
2040 val = I915_READ(WM0_PIPEC_IVB);
2041 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2042 I915_WRITE(WM0_PIPEC_IVB, val |
2043 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2044 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2045 " plane %d, cursor: %d\n",
2046 plane_wm, cursor_wm);
51cea1f4 2047 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2048 }
2049
2050 /*
2051 * Calculate and update the self-refresh watermark only when one
2052 * display plane is used.
2053 *
2054 * SNB support 3 levels of watermark.
2055 *
2056 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2057 * and disabled in the descending order
2058 *
2059 */
2060 I915_WRITE(WM3_LP_ILK, 0);
2061 I915_WRITE(WM2_LP_ILK, 0);
2062 I915_WRITE(WM1_LP_ILK, 0);
2063
2064 if (!single_plane_enabled(enabled) ||
2065 dev_priv->sprite_scaling_enabled)
2066 return;
2067 enabled = ffs(enabled) - 1;
2068
2069 /* WM1 */
2070 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2071 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2072 &sandybridge_display_srwm_info,
2073 &sandybridge_cursor_srwm_info,
2074 &fbc_wm, &plane_wm, &cursor_wm))
2075 return;
2076
2077 I915_WRITE(WM1_LP_ILK,
2078 WM1_LP_SR_EN |
b0aea5dc 2079 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2080 (fbc_wm << WM1_LP_FBC_SHIFT) |
2081 (plane_wm << WM1_LP_SR_SHIFT) |
2082 cursor_wm);
2083
2084 /* WM2 */
2085 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2086 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2087 &sandybridge_display_srwm_info,
2088 &sandybridge_cursor_srwm_info,
2089 &fbc_wm, &plane_wm, &cursor_wm))
2090 return;
2091
2092 I915_WRITE(WM2_LP_ILK,
2093 WM2_LP_EN |
b0aea5dc 2094 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2095 (fbc_wm << WM1_LP_FBC_SHIFT) |
2096 (plane_wm << WM1_LP_SR_SHIFT) |
2097 cursor_wm);
2098
c43d0188 2099 /* WM3, note we have to correct the cursor latency */
b445e3b0 2100 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2101 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2102 &sandybridge_display_srwm_info,
2103 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2104 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2105 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2106 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2107 &sandybridge_display_srwm_info,
2108 &sandybridge_cursor_srwm_info,
2109 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2110 return;
2111
2112 I915_WRITE(WM3_LP_ILK,
2113 WM3_LP_EN |
b0aea5dc 2114 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2115 (fbc_wm << WM1_LP_FBC_SHIFT) |
2116 (plane_wm << WM1_LP_SR_SHIFT) |
2117 cursor_wm);
2118}
2119
3658729a
VS		 2120static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2121 struct drm_crtc *crtc)
801bcfff
PZ		 2122{
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2124 uint32_t pixel_rate;
801bcfff 2125
241bfc38 2126 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2127
2128 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2129 * adjust the pixel_rate here. */
2130
fd4daa9c 2131 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2132 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2133 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2134
37327abd
VS		 2135 pipe_w = intel_crtc->config.pipe_src_w;
2136 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2137 pfit_w = (pfit_size >> 16) & 0xFFFF;
2138 pfit_h = pfit_size & 0xFFFF;
2139 if (pipe_w < pfit_w)
2140 pipe_w = pfit_w;
2141 if (pipe_h < pfit_h)
2142 pipe_h = pfit_h;
2143
2144 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2145 pfit_w * pfit_h);
2146 }
2147
2148 return pixel_rate;
2149}
2150
37126462 2151/* latency must be in 0.1us units. */
23297044 2152static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2153 uint32_t latency)
2154{
2155 uint64_t ret;
2156
3312ba65
VS		 2157 if (WARN(latency == 0, "Latency value missing\n"))
2158 return UINT_MAX;
2159
801bcfff
PZ		 2160 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2161 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2162
2163 return ret;
2164}
2165
37126462 2166/* latency must be in 0.1us units. */
23297044 2167static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2168 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2169 uint32_t latency)
2170{
2171 uint32_t ret;
2172
3312ba65
VS		 2173 if (WARN(latency == 0, "Latency value missing\n"))
2174 return UINT_MAX;
2175
801bcfff
PZ		 2176 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2177 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2178 ret = DIV_ROUND_UP(ret, 64) + 2;
2179 return ret;
2180}
2181
23297044 2182static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2183 uint8_t bytes_per_pixel)
2184{
2185 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2186}
2187
801bcfff
PZ		 2188struct hsw_pipe_wm_parameters {
2189 bool active;
801bcfff
PZ		 2190 uint32_t pipe_htotal;
2191 uint32_t pixel_rate;
c35426d2
VS		 2192 struct intel_plane_wm_parameters pri;
2193 struct intel_plane_wm_parameters spr;
2194 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2195};
2196
cca32e9a
PZ		 2197struct hsw_wm_maximums {
2198 uint16_t pri;
2199 uint16_t spr;
2200 uint16_t cur;
2201 uint16_t fbc;
2202};
2203
240264f4
VS		 2204/* used in computing the new watermarks state */
2205struct intel_wm_config {
2206 unsigned int num_pipes_active;
2207 bool sprites_enabled;
2208 bool sprites_scaled;
240264f4
VS		 2209};
2210
37126462
VS		 2211/*
2212 * For both WM_PIPE and WM_LP.
2213 * mem_value must be in 0.1us units.
2214 */
ac830fe1 2215static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2216 uint32_t mem_value,
2217 bool is_lp)
801bcfff 2218{
cca32e9a
PZ		 2219 uint32_t method1, method2;
2220
c35426d2 2221 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2222 return 0;
2223
23297044 2224 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2225 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2226 mem_value);
2227
2228 if (!is_lp)
2229 return method1;
2230
23297044 2231 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2232 params->pipe_htotal,
c35426d2
VS		 2233 params->pri.horiz_pixels,
2234 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2235 mem_value);
2236
2237 return min(method1, method2);
801bcfff
PZ		 2238}
2239
37126462
VS		 2240/*
2241 * For both WM_PIPE and WM_LP.
2242 * mem_value must be in 0.1us units.
2243 */
ac830fe1 2244static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2245 uint32_t mem_value)
2246{
2247 uint32_t method1, method2;
2248
c35426d2 2249 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2250 return 0;
2251
23297044 2252 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2253 params->spr.bytes_per_pixel,
801bcfff 2254 mem_value);
23297044 2255 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2256 params->pipe_htotal,
c35426d2
VS		 2257 params->spr.horiz_pixels,
2258 params->spr.bytes_per_pixel,
801bcfff
PZ		 2259 mem_value);
2260 return min(method1, method2);
2261}
2262
37126462
VS		 2263/*
2264 * For both WM_PIPE and WM_LP.
2265 * mem_value must be in 0.1us units.
2266 */
ac830fe1 2267static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2268 uint32_t mem_value)
2269{
c35426d2 2270 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2271 return 0;
2272
23297044 2273 return ilk_wm_method2(params->pixel_rate,
801bcfff 2274 params->pipe_htotal,
c35426d2
VS		 2275 params->cur.horiz_pixels,
2276 params->cur.bytes_per_pixel,
801bcfff
PZ		 2277 mem_value);
2278}
2279
cca32e9a 2280/* Only for WM_LP. */
ac830fe1 2281static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2282 uint32_t pri_val)
cca32e9a 2283{
c35426d2 2284 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2285 return 0;
2286
23297044 2287 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2288 params->pri.horiz_pixels,
2289 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2290}
2291
158ae64f
VS		 2292static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2293{
416f4727
VS		 2294 if (INTEL_INFO(dev)->gen >= 8)
2295 return 3072;
2296 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2297 return 768;
2298 else
2299 return 512;
2300}
2301
2302/* Calculate the maximum primary/sprite plane watermark */
2303static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2304 int level,
240264f4 2305 const struct intel_wm_config *config,
158ae64f
VS		 2306 enum intel_ddb_partitioning ddb_partitioning,
2307 bool is_sprite)
2308{
2309 unsigned int fifo_size = ilk_display_fifo_size(dev);
2310 unsigned int max;
2311
2312 /* if sprites aren't enabled, sprites get nothing */
240264f4 2313 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2314 return 0;
2315
2316 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2317 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2318 fifo_size /= INTEL_INFO(dev)->num_pipes;
2319
2320 /*
2321 * For some reason the non self refresh
2322 * FIFO size is only half of the self
2323 * refresh FIFO size on ILK/SNB.
2324 */
2325 if (INTEL_INFO(dev)->gen <= 6)
2326 fifo_size /= 2;
2327 }
2328
240264f4 2329 if (config->sprites_enabled) {
158ae64f
VS		 2330 /* level 0 is always calculated with 1:1 split */
2331 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2332 if (is_sprite)
2333 fifo_size *= 5;
2334 fifo_size /= 6;
2335 } else {
2336 fifo_size /= 2;
2337 }
2338 }
2339
2340 /* clamp to max that the registers can hold */
416f4727
VS		 2341 if (INTEL_INFO(dev)->gen >= 8)
2342 max = level == 0 ? 255 : 2047;
2343 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2344 /* IVB/HSW primary/sprite plane watermarks */
2345 max = level == 0 ? 127 : 1023;
2346 else if (!is_sprite)
2347 /* ILK/SNB primary plane watermarks */
2348 max = level == 0 ? 127 : 511;
2349 else
2350 /* ILK/SNB sprite plane watermarks */
2351 max = level == 0 ? 63 : 255;
2352
2353 return min(fifo_size, max);
2354}
2355
2356/* Calculate the maximum cursor plane watermark */
2357static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2358 int level,
2359 const struct intel_wm_config *config)
158ae64f
VS		 2360{
2361 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2362 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2363 return 64;
2364
2365 /* otherwise just report max that registers can hold */
2366 if (INTEL_INFO(dev)->gen >= 7)
2367 return level == 0 ? 63 : 255;
2368 else
2369 return level == 0 ? 31 : 63;
2370}
2371
2372/* Calculate the maximum FBC watermark */
416f4727 2373static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
158ae64f
VS		 2374{
2375 /* max that registers can hold */
416f4727
VS		 2376 if (INTEL_INFO(dev)->gen >= 8)
2377 return 31;
2378 else
2379 return 15;
158ae64f
VS		 2380}
2381
34982fe1
VS		 2382static void ilk_compute_wm_maximums(struct drm_device *dev,
2383 int level,
2384 const struct intel_wm_config *config,
2385 enum intel_ddb_partitioning ddb_partitioning,
2386 struct hsw_wm_maximums *max)
158ae64f 2387{
240264f4
VS		 2388 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2389 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2390 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 2391 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 2392}
2393
d9395655
VS		 2394static bool ilk_validate_wm_level(int level,
2395 const struct hsw_wm_maximums *max,
2396 struct intel_wm_level *result)
a9786a11
VS		 2397{
2398 bool ret;
2399
2400 /* already determined to be invalid? */
2401 if (!result->enable)
2402 return false;
2403
2404 result->enable = result->pri_val <= max->pri &&
2405 result->spr_val <= max->spr &&
2406 result->cur_val <= max->cur;
2407
2408 ret = result->enable;
2409
2410 /*
2411 * HACK until we can pre-compute everything,
2412 * and thus fail gracefully if LP0 watermarks
2413 * are exceeded...
2414 */
2415 if (level == 0 && !result->enable) {
2416 if (result->pri_val > max->pri)
2417 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2418 level, result->pri_val, max->pri);
2419 if (result->spr_val > max->spr)
2420 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2421 level, result->spr_val, max->spr);
2422 if (result->cur_val > max->cur)
2423 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2424 level, result->cur_val, max->cur);
2425
2426 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2427 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2428 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2429 result->enable = true;
2430 }
2431
a9786a11
VS		 2432 return ret;
2433}
2434
6f5ddd17
VS		 2435static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2436 int level,
ac830fe1 2437 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2438 struct intel_wm_level *result)
6f5ddd17
VS		 2439{
2440 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2441 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2442 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2443
2444 /* WM1+ latency values stored in 0.5us units */
2445 if (level > 0) {
2446 pri_latency *= 5;
2447 spr_latency *= 5;
2448 cur_latency *= 5;
2449 }
2450
2451 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2452 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2453 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2454 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2455 result->enable = true;
2456}
2457
801bcfff
PZ		 2458static uint32_t
2459hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2460{
2461 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2463 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2464 u32 linetime, ips_linetime;
1f8eeabf 2465
801bcfff
PZ		 2466 if (!intel_crtc_active(crtc))
2467 return 0;
1011d8c4 2468
1f8eeabf
ED		 2469 /* The WM are computed with base on how long it takes to fill a single
2470 * row at the given clock rate, multiplied by 8.
2471 * */
85a02deb
PZ		 2472 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2473 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2474 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2475
801bcfff
PZ		 2476 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2477 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2478}
2479
12b134df
VS		 2480static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2481{
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483
2484 if (IS_HASWELL(dev)) {
2485 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2486
2487 wm[0] = (sskpd >> 56) & 0xFF;
2488 if (wm[0] == 0)
2489 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2490 wm[1] = (sskpd >> 4) & 0xFF;
2491 wm[2] = (sskpd >> 12) & 0xFF;
2492 wm[3] = (sskpd >> 20) & 0x1FF;
2493 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2494 } else if (INTEL_INFO(dev)->gen >= 6) {
2495 uint32_t sskpd = I915_READ(MCH_SSKPD);
2496
2497 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2498 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2499 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2500 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2501 } else if (INTEL_INFO(dev)->gen >= 5) {
2502 uint32_t mltr = I915_READ(MLTR_ILK);
2503
2504 /* ILK primary LP0 latency is 700 ns */
2505 wm[0] = 7;
2506 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2507 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2508 }
2509}
2510
53615a5e
VS		 2511static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2512{
2513 /* ILK sprite LP0 latency is 1300 ns */
2514 if (INTEL_INFO(dev)->gen == 5)
2515 wm[0] = 13;
2516}
2517
2518static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2519{
2520 /* ILK cursor LP0 latency is 1300 ns */
2521 if (INTEL_INFO(dev)->gen == 5)
2522 wm[0] = 13;
2523
2524 /* WaDoubleCursorLP3Latency:ivb */
2525 if (IS_IVYBRIDGE(dev))
2526 wm[3] *= 2;
2527}
2528
ad0d6dc4 2529static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2530{
26ec971e
VS		 2531 /* how many WM levels are we expecting */
2532 if (IS_HASWELL(dev))
ad0d6dc4 2533 return 4;
26ec971e 2534 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2535 return 3;
26ec971e 2536 else
ad0d6dc4
VS		 2537 return 2;
2538}
2539
2540static void intel_print_wm_latency(struct drm_device *dev,
2541 const char *name,
2542 const uint16_t wm[5])
2543{
2544 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2545
2546 for (level = 0; level <= max_level; level++) {
2547 unsigned int latency = wm[level];
2548
2549 if (latency == 0) {
2550 DRM_ERROR("%s WM%d latency not provided\n",
2551 name, level);
2552 continue;
2553 }
2554
2555 /* WM1+ latency values in 0.5us units */
2556 if (level > 0)
2557 latency *= 5;
2558
2559 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2560 name, level, wm[level],
2561 latency / 10, latency % 10);
2562 }
2563}
2564
53615a5e
VS		 2565static void intel_setup_wm_latency(struct drm_device *dev)
2566{
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568
2569 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2570
2571 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2572 sizeof(dev_priv->wm.pri_latency));
2573 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2574 sizeof(dev_priv->wm.pri_latency));
2575
2576 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2577 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2578
2579 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2580 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2581 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2582}
2583
7c4a395f
VS		 2584static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2585 struct hsw_pipe_wm_parameters *p,
a485bfb8 2586 struct intel_wm_config *config)
1011d8c4 2587{
7c4a395f
VS		 2588 struct drm_device *dev = crtc->dev;
2589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2590 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2591 struct drm_plane *plane;
1011d8c4 2592
7c4a395f
VS		 2593 p->active = intel_crtc_active(crtc);
2594 if (p->active) {
801bcfff 2595 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2596 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2597 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2598 p->cur.bytes_per_pixel = 4;
37327abd 2599 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2600 p->cur.horiz_pixels = 64;
2601 /* TODO: for now, assume primary and cursor planes are always enabled. */
2602 p->pri.enabled = true;
2603 p->cur.enabled = true;
801bcfff
PZ		 2604 }
2605
7c4a395f 2606 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2607 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2608
801bcfff
PZ		 2609 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2610 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2611
7c4a395f
VS		 2612 if (intel_plane->pipe == pipe)
2613 p->spr = intel_plane->wm;
cca32e9a 2614
a485bfb8
VS		 2615 config->sprites_enabled |= intel_plane->wm.enabled;
2616 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2617 }
801bcfff
PZ		 2618}
2619
0b2ae6d7
VS		 2620/* Compute new watermarks for the pipe */
2621static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2622 const struct hsw_pipe_wm_parameters *params,
2623 struct intel_pipe_wm *pipe_wm)
2624{
2625 struct drm_device *dev = crtc->dev;
2626 struct drm_i915_private *dev_priv = dev->dev_private;
2627 int level, max_level = ilk_wm_max_level(dev);
2628 /* LP0 watermark maximums depend on this pipe alone */
2629 struct intel_wm_config config = {
2630 .num_pipes_active = 1,
2631 .sprites_enabled = params->spr.enabled,
2632 .sprites_scaled = params->spr.scaled,
2633 };
2634 struct hsw_wm_maximums max;
2635
0b2ae6d7 2636 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2637 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7
VS		 2638
2639 for (level = 0; level <= max_level; level++)
2640 ilk_compute_wm_level(dev_priv, level, params,
2641 &pipe_wm->wm[level]);
2642
2643 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2644
2645 /* At least LP0 must be valid */
d9395655 2646 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2647}
2648
2649/*
2650 * Merge the watermarks from all active pipes for a specific level.
2651 */
2652static void ilk_merge_wm_level(struct drm_device *dev,
2653 int level,
2654 struct intel_wm_level *ret_wm)
2655{
2656 const struct intel_crtc *intel_crtc;
2657
2658 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2659 const struct intel_wm_level *wm =
2660 &intel_crtc->wm.active.wm[level];
2661
2662 if (!wm->enable)
2663 return;
2664
2665 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2666 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2667 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2668 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2669 }
2670
2671 ret_wm->enable = true;
2672}
2673
2674/*
2675 * Merge all low power watermarks for all active pipes.
2676 */
2677static void ilk_wm_merge(struct drm_device *dev,
2678 const struct hsw_wm_maximums *max,
2679 struct intel_pipe_wm *merged)
2680{
2681 int level, max_level = ilk_wm_max_level(dev);
2682
2683 merged->fbc_wm_enabled = true;
2684
2685 /* merge each WM1+ level */
2686 for (level = 1; level <= max_level; level++) {
2687 struct intel_wm_level *wm = &merged->wm[level];
2688
2689 ilk_merge_wm_level(dev, level, wm);
2690
d9395655 2691 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2692 break;
2693
2694 /*
2695 * The spec says it is preferred to disable
2696 * FBC WMs instead of disabling a WM level.
2697 */
2698 if (wm->fbc_val > max->fbc) {
2699 merged->fbc_wm_enabled = false;
2700 wm->fbc_val = 0;
2701 }
2702 }
2703}
2704
b380ca3c
VS		 2705static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2706{
2707 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2708 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2709}
2710
801bcfff 2711static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2712 const struct intel_pipe_wm *merged,
609cedef 2713 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2714 struct hsw_wm_values *results)
2715{
0b2ae6d7
VS		 2716 struct intel_crtc *intel_crtc;
2717 int level, wm_lp;
cca32e9a 2718
0362c781 2719 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2720 results->partitioning = partitioning;
cca32e9a 2721
0b2ae6d7 2722 /* LP1+ register values */
cca32e9a 2723 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2724 const struct intel_wm_level *r;
801bcfff 2725
b380ca3c 2726 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2727
0362c781 2728 r = &merged->wm[level];
0b2ae6d7 2729 if (!r->enable)
cca32e9a
PZ		 2730 break;
2731
416f4727
VS		 2732 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2733 ((level * 2) << WM1_LP_LATENCY_SHIFT) |
2734 (r->pri_val << WM1_LP_SR_SHIFT) |
2735 r->cur_val;
2736
2737 if (INTEL_INFO(dev)->gen >= 8)
2738 results->wm_lp[wm_lp - 1] |=
2739 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2740 else
2741 results->wm_lp[wm_lp - 1] |=
2742 r->fbc_val << WM1_LP_FBC_SHIFT;
2743
cca32e9a
PZ		 2744 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2745 }
801bcfff 2746
0b2ae6d7
VS		 2747 /* LP0 register values */
2748 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2749 enum pipe pipe = intel_crtc->pipe;
2750 const struct intel_wm_level *r =
2751 &intel_crtc->wm.active.wm[0];
2752
2753 if (WARN_ON(!r->enable))
2754 continue;
2755
2756 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2757
0b2ae6d7
VS		 2758 results->wm_pipe[pipe] =
2759 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2760 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2761 r->cur_val;
801bcfff
PZ		 2762 }
2763}
2764
861f3389
PZ		 2765/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2766 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2767static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2768 struct intel_pipe_wm *r1,
2769 struct intel_pipe_wm *r2)
861f3389 2770{
198a1e9b
VS		 2771 int level, max_level = ilk_wm_max_level(dev);
2772 int level1 = 0, level2 = 0;
861f3389 2773
198a1e9b
VS		 2774 for (level = 1; level <= max_level; level++) {
2775 if (r1->wm[level].enable)
2776 level1 = level;
2777 if (r2->wm[level].enable)
2778 level2 = level;
861f3389
PZ		 2779 }
2780
198a1e9b
VS		 2781 if (level1 == level2) {
2782 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2783 return r2;
2784 else
2785 return r1;
198a1e9b 2786 } else if (level1 > level2) {
861f3389
PZ		 2787 return r1;
2788 } else {
2789 return r2;
2790 }
2791}
2792
49a687c4
VS		 2793/* dirty bits used to track which watermarks need changes */
2794#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2795#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2796#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2797#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2798#define WM_DIRTY_FBC (1 << 24)
2799#define WM_DIRTY_DDB (1 << 25)
2800
2801static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2802 const struct hsw_wm_values *old,
2803 const struct hsw_wm_values *new)
2804{
2805 unsigned int dirty = 0;
2806 enum pipe pipe;
2807 int wm_lp;
2808
2809 for_each_pipe(pipe) {
2810 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2811 dirty |= WM_DIRTY_LINETIME(pipe);
2812 /* Must disable LP1+ watermarks too */
2813 dirty |= WM_DIRTY_LP_ALL;
2814 }
2815
2816 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2817 dirty |= WM_DIRTY_PIPE(pipe);
2818 /* Must disable LP1+ watermarks too */
2819 dirty |= WM_DIRTY_LP_ALL;
2820 }
2821 }
2822
2823 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2824 dirty |= WM_DIRTY_FBC;
2825 /* Must disable LP1+ watermarks too */
2826 dirty |= WM_DIRTY_LP_ALL;
2827 }
2828
2829 if (old->partitioning != new->partitioning) {
2830 dirty |= WM_DIRTY_DDB;
2831 /* Must disable LP1+ watermarks too */
2832 dirty |= WM_DIRTY_LP_ALL;
2833 }
2834
2835 /* LP1+ watermarks already deemed dirty, no need to continue */
2836 if (dirty & WM_DIRTY_LP_ALL)
2837 return dirty;
2838
2839 /* Find the lowest numbered LP1+ watermark in need of an update... */
2840 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2841 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2842 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2843 break;
2844 }
2845
2846 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2847 for (; wm_lp <= 3; wm_lp++)
2848 dirty |= WM_DIRTY_LP(wm_lp);
2849
2850 return dirty;
2851}
2852
801bcfff
PZ		 2853/*
2854 * The spec says we shouldn't write when we don't need, because every write
2855 * causes WMs to be re-evaluated, expending some power.
2856 */
2857static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
609cedef 2858 struct hsw_wm_values *results)
801bcfff 2859{
243e6a44 2860 struct hsw_wm_values *previous = &dev_priv->wm.hw;
49a687c4 2861 unsigned int dirty;
801bcfff 2862 uint32_t val;
801bcfff 2863
243e6a44 2864 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
49a687c4 2865 if (!dirty)
801bcfff
PZ		 2866 return;
2867
243e6a44 2868 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
801bcfff 2869 I915_WRITE(WM3_LP_ILK, 0);
243e6a44 2870 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
801bcfff 2871 I915_WRITE(WM2_LP_ILK, 0);
243e6a44 2872 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
801bcfff
PZ		 2873 I915_WRITE(WM1_LP_ILK, 0);
2874
49a687c4 2875 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2876 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2877 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2878 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2879 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2880 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2881
49a687c4 2882 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2883 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2884 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2885 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2886 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2887 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2888
49a687c4 2889 if (dirty & WM_DIRTY_DDB) {
801bcfff 2890 val = I915_READ(WM_MISC);
609cedef 2891 if (results->partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2892 val &= ~WM_MISC_DATA_PARTITION_5_6;
2893 else
2894 val |= WM_MISC_DATA_PARTITION_5_6;
2895 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2896 }
2897
49a687c4 2898 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2899 val = I915_READ(DISP_ARB_CTL);
2900 if (results->enable_fbc_wm)
2901 val &= ~DISP_FBC_WM_DIS;
2902 else
2903 val |= DISP_FBC_WM_DIS;
2904 I915_WRITE(DISP_ARB_CTL, val);
2905 }
2906
243e6a44 2907 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
801bcfff 2908 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
243e6a44 2909 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
801bcfff 2910 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
243e6a44 2911 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
801bcfff
PZ		 2912 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2913
49a687c4 2914 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
801bcfff 2915 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
49a687c4 2916 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
801bcfff 2917 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
49a687c4 2918 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
801bcfff 2919 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2920
2921 dev_priv->wm.hw = *results;
801bcfff
PZ		 2922}
2923
46ba614c 2924static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2925{
7c4a395f 2926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2927 struct drm_device *dev = crtc->dev;
801bcfff 2928 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 2929 struct hsw_wm_maximums max;
7c4a395f 2930 struct hsw_pipe_wm_parameters params = {};
198a1e9b 2931 struct hsw_wm_values results = {};
77c122bc 2932 enum intel_ddb_partitioning partitioning;
7c4a395f 2933 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2934 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2935 struct intel_wm_config config = {};
7c4a395f 2936
a485bfb8 2937 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2938
2939 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2940
2941 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2942 return;
861f3389 2943
7c4a395f 2944 intel_crtc->wm.active = pipe_wm;
861f3389 2945
34982fe1 2946 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
a485bfb8
VS		 2947 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2948
2949 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2950 if (INTEL_INFO(dev)->gen >= 7 &&
2951 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2952 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
a485bfb8 2953 ilk_wm_merge(dev, &max, &lp_wm_5_6);
0362c781 2954
198a1e9b 2955 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2956 } else {
198a1e9b 2957 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2958 }
2959
198a1e9b 2960 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2961 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2962
609cedef
VS		 2963 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2964
2965 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2966}
2967
adf3d35e
VS		 2968static void haswell_update_sprite_wm(struct drm_plane *plane,
2969 struct drm_crtc *crtc,
526682e9 2970 uint32_t sprite_width, int pixel_size,
bdd57d03 2971 bool enabled, bool scaled)
526682e9 2972{
adf3d35e 2973 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2974
adf3d35e
VS		 2975 intel_plane->wm.enabled = enabled;
2976 intel_plane->wm.scaled = scaled;
2977 intel_plane->wm.horiz_pixels = sprite_width;
2978 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2979
46ba614c 2980 haswell_update_wm(crtc);
526682e9
PZ		 2981}
2982
b445e3b0
ED		 2983static bool
2984sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2985 uint32_t sprite_width, int pixel_size,
2986 const struct intel_watermark_params *display,
2987 int display_latency_ns, int *sprite_wm)
2988{
2989 struct drm_crtc *crtc;
2990 int clock;
2991 int entries, tlb_miss;
2992
2993 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2994 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2995 *sprite_wm = display->guard_size;
2996 return false;
2997 }
2998
241bfc38 2999 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3000
3001 /* Use the small buffer method to calculate the sprite watermark */
3002 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3003 tlb_miss = display->fifo_size*display->cacheline_size -
3004 sprite_width * 8;
3005 if (tlb_miss > 0)
3006 entries += tlb_miss;
3007 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3008 *sprite_wm = entries + display->guard_size;
3009 if (*sprite_wm > (int)display->max_wm)
3010 *sprite_wm = display->max_wm;
3011
3012 return true;
3013}
3014
3015static bool
3016sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3017 uint32_t sprite_width, int pixel_size,
3018 const struct intel_watermark_params *display,
3019 int latency_ns, int *sprite_wm)
3020{
3021 struct drm_crtc *crtc;
3022 unsigned long line_time_us;
3023 int clock;
3024 int line_count, line_size;
3025 int small, large;
3026 int entries;
3027
3028 if (!latency_ns) {
3029 *sprite_wm = 0;
3030 return false;
3031 }
3032
3033 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 3034 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3035 if (!clock) {
3036 *sprite_wm = 0;
3037 return false;
3038 }
3039
3040 line_time_us = (sprite_width * 1000) / clock;
3041 if (!line_time_us) {
3042 *sprite_wm = 0;
3043 return false;
3044 }
3045
3046 line_count = (latency_ns / line_time_us + 1000) / 1000;
3047 line_size = sprite_width * pixel_size;
3048
3049 /* Use the minimum of the small and large buffer method for primary */
3050 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3051 large = line_count * line_size;
3052
3053 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3054 *sprite_wm = entries + display->guard_size;
3055
3056 return *sprite_wm > 0x3ff ? false : true;
3057}
3058
adf3d35e
VS		 3059static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3060 struct drm_crtc *crtc,
4c4ff43a 3061 uint32_t sprite_width, int pixel_size,
39db4a4d 3062 bool enabled, bool scaled)
b445e3b0 3063{
adf3d35e 3064 struct drm_device *dev = plane->dev;
b445e3b0 3065 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 3066 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 3067 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 3068 u32 val;
3069 int sprite_wm, reg;
3070 int ret;
3071
39db4a4d 3072 if (!enabled)
4c4ff43a
PZ		 3073 return;
3074
b445e3b0
ED		 3075 switch (pipe) {
3076 case 0:
3077 reg = WM0_PIPEA_ILK;
3078 break;
3079 case 1:
3080 reg = WM0_PIPEB_ILK;
3081 break;
3082 case 2:
3083 reg = WM0_PIPEC_IVB;
3084 break;
3085 default:
3086 return; /* bad pipe */
3087 }
3088
3089 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3090 &sandybridge_display_wm_info,
3091 latency, &sprite_wm);
3092 if (!ret) {
84f44ce7
VS		 3093 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3094 pipe_name(pipe));
b445e3b0
ED		 3095 return;
3096 }
3097
3098 val = I915_READ(reg);
3099 val &= ~WM0_PIPE_SPRITE_MASK;
3100 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3101 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3102
3103
3104 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3105 pixel_size,
3106 &sandybridge_display_srwm_info,
b0aea5dc 3107 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3108 &sprite_wm);
3109 if (!ret) {
84f44ce7
VS		 3110 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3111 pipe_name(pipe));
b445e3b0
ED		 3112 return;
3113 }
3114 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3115
3116 /* Only IVB has two more LP watermarks for sprite */
3117 if (!IS_IVYBRIDGE(dev))
3118 return;
3119
3120 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3121 pixel_size,
3122 &sandybridge_display_srwm_info,
b0aea5dc 3123 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3124 &sprite_wm);
3125 if (!ret) {
84f44ce7
VS		 3126 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3127 pipe_name(pipe));
b445e3b0
ED		 3128 return;
3129 }
3130 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3131
3132 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3133 pixel_size,
3134 &sandybridge_display_srwm_info,
b0aea5dc 3135 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3136 &sprite_wm);
3137 if (!ret) {
84f44ce7
VS		 3138 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3139 pipe_name(pipe));
b445e3b0
ED		 3140 return;
3141 }
3142 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3143}
3144
243e6a44
VS		 3145static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3146{
3147 struct drm_device *dev = crtc->dev;
3148 struct drm_i915_private *dev_priv = dev->dev_private;
3149 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3152 enum pipe pipe = intel_crtc->pipe;
3153 static const unsigned int wm0_pipe_reg[] = {
3154 [PIPE_A] = WM0_PIPEA_ILK,
3155 [PIPE_B] = WM0_PIPEB_ILK,
3156 [PIPE_C] = WM0_PIPEC_IVB,
3157 };
3158
3159 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3160 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3161
3162 if (intel_crtc_active(crtc)) {
3163 u32 tmp = hw->wm_pipe[pipe];
3164
3165 /*
3166 * For active pipes LP0 watermark is marked as
3167 * enabled, and LP1+ watermaks as disabled since
3168 * we can't really reverse compute them in case
3169 * multiple pipes are active.
3170 */
3171 active->wm[0].enable = true;
3172 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3173 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3174 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3175 active->linetime = hw->wm_linetime[pipe];
3176 } else {
3177 int level, max_level = ilk_wm_max_level(dev);
3178
3179 /*
3180 * For inactive pipes, all watermark levels
3181 * should be marked as enabled but zeroed,
3182 * which is what we'd compute them to.
3183 */
3184 for (level = 0; level <= max_level; level++)
3185 active->wm[level].enable = true;
3186 }
3187}
3188
3189void ilk_wm_get_hw_state(struct drm_device *dev)
3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3193 struct drm_crtc *crtc;
3194
3195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3196 ilk_pipe_wm_get_hw_state(crtc);
3197
3198 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3199 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3200 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3201
3202 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3203 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3204 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3205
3206 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3207 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3208
3209 hw->enable_fbc_wm =
3210 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3211}
3212
b445e3b0
ED		 3213/**
3214 * intel_update_watermarks - update FIFO watermark values based on current modes
3215 *
3216 * Calculate watermark values for the various WM regs based on current mode
3217 * and plane configuration.
3218 *
3219 * There are several cases to deal with here:
3220 * - normal (i.e. non-self-refresh)
3221 * - self-refresh (SR) mode
3222 * - lines are large relative to FIFO size (buffer can hold up to 2)
3223 * - lines are small relative to FIFO size (buffer can hold more than 2
3224 * lines), so need to account for TLB latency
3225 *
3226 * The normal calculation is:
3227 * watermark = dotclock * bytes per pixel * latency
3228 * where latency is platform & configuration dependent (we assume pessimal
3229 * values here).
3230 *
3231 * The SR calculation is:
3232 * watermark = (trunc(latency/line time)+1) * surface width *
3233 * bytes per pixel
3234 * where
3235 * line time = htotal / dotclock
3236 * surface width = hdisplay for normal plane and 64 for cursor
3237 * and latency is assumed to be high, as above.
3238 *
3239 * The final value programmed to the register should always be rounded up,
3240 * and include an extra 2 entries to account for clock crossings.
3241 *
3242 * We don't use the sprite, so we can ignore that. And on Crestline we have
3243 * to set the non-SR watermarks to 8.
3244 */
46ba614c 3245void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3246{
46ba614c 3247 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3248
3249 if (dev_priv->display.update_wm)
46ba614c 3250 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3251}
3252
adf3d35e
VS		 3253void intel_update_sprite_watermarks(struct drm_plane *plane,
3254 struct drm_crtc *crtc,
4c4ff43a 3255 uint32_t sprite_width, int pixel_size,
39db4a4d 3256 bool enabled, bool scaled)
b445e3b0 3257{
adf3d35e 3258 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3259
3260 if (dev_priv->display.update_sprite_wm)
adf3d35e 3261 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3262 pixel_size, enabled, scaled);
b445e3b0
ED		 3263}
3264
2b4e57bd
ED		 3265static struct drm_i915_gem_object *
3266intel_alloc_context_page(struct drm_device *dev)
3267{
3268 struct drm_i915_gem_object *ctx;
3269 int ret;
3270
3271 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3272
3273 ctx = i915_gem_alloc_object(dev, 4096);
3274 if (!ctx) {
3275 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3276 return NULL;
3277 }
3278
c37e2204 3279 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3280 if (ret) {
3281 DRM_ERROR("failed to pin power context: %d\n", ret);
3282 goto err_unref;
3283 }
3284
3285 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3286 if (ret) {
3287 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3288 goto err_unpin;
3289 }
3290
3291 return ctx;
3292
3293err_unpin:
3294 i915_gem_object_unpin(ctx);
3295err_unref:
3296 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3297 return NULL;
3298}
3299
9270388e
DV		 3300/**
3301 * Lock protecting IPS related data structures
9270388e
DV		 3302 */
3303DEFINE_SPINLOCK(mchdev_lock);
3304
3305/* Global for IPS driver to get at the current i915 device. Protected by
3306 * mchdev_lock. */
3307static struct drm_i915_private *i915_mch_dev;
3308
2b4e57bd
ED		 3309bool ironlake_set_drps(struct drm_device *dev, u8 val)
3310{
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 u16 rgvswctl;
3313
9270388e
DV		 3314 assert_spin_locked(&mchdev_lock);
3315
2b4e57bd
ED		 3316 rgvswctl = I915_READ16(MEMSWCTL);
3317 if (rgvswctl & MEMCTL_CMD_STS) {
3318 DRM_DEBUG("gpu busy, RCS change rejected\n");
3319 return false; /* still busy with another command */
3320 }
3321
3322 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3323 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3324 I915_WRITE16(MEMSWCTL, rgvswctl);
3325 POSTING_READ16(MEMSWCTL);
3326
3327 rgvswctl |= MEMCTL_CMD_STS;
3328 I915_WRITE16(MEMSWCTL, rgvswctl);
3329
3330 return true;
3331}
3332
8090c6b9 3333static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3334{
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 u32 rgvmodectl = I915_READ(MEMMODECTL);
3337 u8 fmax, fmin, fstart, vstart;
3338
9270388e
DV		 3339 spin_lock_irq(&mchdev_lock);
3340
2b4e57bd
ED		 3341 /* Enable temp reporting */
3342 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3343 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3344
3345 /* 100ms RC evaluation intervals */
3346 I915_WRITE(RCUPEI, 100000);
3347 I915_WRITE(RCDNEI, 100000);
3348
3349 /* Set max/min thresholds to 90ms and 80ms respectively */
3350 I915_WRITE(RCBMAXAVG, 90000);
3351 I915_WRITE(RCBMINAVG, 80000);
3352
3353 I915_WRITE(MEMIHYST, 1);
3354
3355 /* Set up min, max, and cur for interrupt handling */
3356 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3357 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3358 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3359 MEMMODE_FSTART_SHIFT;
3360
3361 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3362 PXVFREQ_PX_SHIFT;
3363
20e4d407
DV		 3364 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3365 dev_priv->ips.fstart = fstart;
2b4e57bd 3366
20e4d407
DV		 3367 dev_priv->ips.max_delay = fstart;
3368 dev_priv->ips.min_delay = fmin;
3369 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3370
3371 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3372 fmax, fmin, fstart);
3373
3374 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3375
3376 /*
3377 * Interrupts will be enabled in ironlake_irq_postinstall
3378 */
3379
3380 I915_WRITE(VIDSTART, vstart);
3381 POSTING_READ(VIDSTART);
3382
3383 rgvmodectl |= MEMMODE_SWMODE_EN;
3384 I915_WRITE(MEMMODECTL, rgvmodectl);
3385
9270388e 3386 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3387 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3388 mdelay(1);
2b4e57bd
ED		 3389
3390 ironlake_set_drps(dev, fstart);
3391
20e4d407 3392 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3393 I915_READ(0x112e0);
20e4d407
DV		 3394 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3395 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3396 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3397
3398 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3399}
3400
8090c6b9 3401static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3402{
3403 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3404 u16 rgvswctl;
3405
3406 spin_lock_irq(&mchdev_lock);
3407
3408 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3409
3410 /* Ack interrupts, disable EFC interrupt */
3411 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3412 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3413 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3414 I915_WRITE(DEIIR, DE_PCU_EVENT);
3415 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3416
3417 /* Go back to the starting frequency */
20e4d407 3418 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3419 mdelay(1);
2b4e57bd
ED		 3420 rgvswctl |= MEMCTL_CMD_STS;
3421 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3422 mdelay(1);
2b4e57bd 3423
9270388e 3424 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3425}
3426
acbe9475
DV		 3427/* There's a funny hw issue where the hw returns all 0 when reading from
3428 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3429 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3430 * all limits and the gpu stuck at whatever frequency it is at atm).
3431 */
6917c7b9 3432static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3433{
7b9e0ae6 3434 u32 limits;
2b4e57bd 3435
20b46e59
DV		 3436 /* Only set the down limit when we've reached the lowest level to avoid
3437 * getting more interrupts, otherwise leave this clear. This prevents a
3438 * race in the hw when coming out of rc6: There's a tiny window where
3439 * the hw runs at the minimal clock before selecting the desired
3440 * frequency, if the down threshold expires in that window we will not
3441 * receive a down interrupt. */
6917c7b9
CW		 3442 limits = dev_priv->rps.max_delay << 24;
3443 if (val <= dev_priv->rps.min_delay)
c6a828d3 3444 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3445
3446 return limits;
3447}
3448
dd75fdc8
CW		 3449static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3450{
3451 int new_power;
3452
3453 new_power = dev_priv->rps.power;
3454 switch (dev_priv->rps.power) {
3455 case LOW_POWER:
3456 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3457 new_power = BETWEEN;
3458 break;
3459
3460 case BETWEEN:
3461 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3462 new_power = LOW_POWER;
3463 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3464 new_power = HIGH_POWER;
3465 break;
3466
3467 case HIGH_POWER:
3468 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3469 new_power = BETWEEN;
3470 break;
3471 }
3472 /* Max/min bins are special */
3473 if (val == dev_priv->rps.min_delay)
3474 new_power = LOW_POWER;
3475 if (val == dev_priv->rps.max_delay)
3476 new_power = HIGH_POWER;
3477 if (new_power == dev_priv->rps.power)
3478 return;
3479
3480 /* Note the units here are not exactly 1us, but 1280ns. */
3481 switch (new_power) {
3482 case LOW_POWER:
3483 /* Upclock if more than 95% busy over 16ms */
3484 I915_WRITE(GEN6_RP_UP_EI, 12500);
3485 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3486
3487 /* Downclock if less than 85% busy over 32ms */
3488 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3489 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3490
3491 I915_WRITE(GEN6_RP_CONTROL,
3492 GEN6_RP_MEDIA_TURBO |
3493 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3494 GEN6_RP_MEDIA_IS_GFX |
3495 GEN6_RP_ENABLE |
3496 GEN6_RP_UP_BUSY_AVG |
3497 GEN6_RP_DOWN_IDLE_AVG);
3498 break;
3499
3500 case BETWEEN:
3501 /* Upclock if more than 90% busy over 13ms */
3502 I915_WRITE(GEN6_RP_UP_EI, 10250);
3503 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3504
3505 /* Downclock if less than 75% busy over 32ms */
3506 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3507 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3508
3509 I915_WRITE(GEN6_RP_CONTROL,
3510 GEN6_RP_MEDIA_TURBO |
3511 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3512 GEN6_RP_MEDIA_IS_GFX |
3513 GEN6_RP_ENABLE |
3514 GEN6_RP_UP_BUSY_AVG |
3515 GEN6_RP_DOWN_IDLE_AVG);
3516 break;
3517
3518 case HIGH_POWER:
3519 /* Upclock if more than 85% busy over 10ms */
3520 I915_WRITE(GEN6_RP_UP_EI, 8000);
3521 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3522
3523 /* Downclock if less than 60% busy over 32ms */
3524 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3525 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3526
3527 I915_WRITE(GEN6_RP_CONTROL,
3528 GEN6_RP_MEDIA_TURBO |
3529 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3530 GEN6_RP_MEDIA_IS_GFX |
3531 GEN6_RP_ENABLE |
3532 GEN6_RP_UP_BUSY_AVG |
3533 GEN6_RP_DOWN_IDLE_AVG);
3534 break;
3535 }
3536
3537 dev_priv->rps.power = new_power;
3538 dev_priv->rps.last_adj = 0;
3539}
3540
20b46e59
DV		 3541void gen6_set_rps(struct drm_device *dev, u8 val)
3542{
3543 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3544
4fc688ce 3545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3546 WARN_ON(val > dev_priv->rps.max_delay);
3547 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3548
c6a828d3 3549 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3550 return;
3551
dd75fdc8
CW		 3552 gen6_set_rps_thresholds(dev_priv, val);
3553
92bd1bf0
RV		 3554 if (IS_HASWELL(dev))
3555 I915_WRITE(GEN6_RPNSWREQ,
3556 HSW_FREQUENCY(val));
3557 else
3558 I915_WRITE(GEN6_RPNSWREQ,
3559 GEN6_FREQUENCY(val) |
3560 GEN6_OFFSET(0) |
3561 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3562
3563 /* Make sure we continue to get interrupts
3564 * until we hit the minimum or maximum frequencies.
3565 */
6917c7b9
CW		 3566 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3567 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3568
d5570a72
BW		 3569 POSTING_READ(GEN6_RPNSWREQ);
3570
c6a828d3 3571 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3572
3573 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3574}
3575
b29c19b6
CW		 3576void gen6_rps_idle(struct drm_i915_private *dev_priv)
3577{
3578 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3579 if (dev_priv->rps.enabled) {
3580 if (dev_priv->info->is_valleyview)
3581 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3582 else
3583 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3584 dev_priv->rps.last_adj = 0;
3585 }
b29c19b6
CW		 3586 mutex_unlock(&dev_priv->rps.hw_lock);
3587}
3588
3589void gen6_rps_boost(struct drm_i915_private *dev_priv)
3590{
3591 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3592 if (dev_priv->rps.enabled) {
3593 if (dev_priv->info->is_valleyview)
3594 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3595 else
3596 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3597 dev_priv->rps.last_adj = 0;
3598 }
b29c19b6
CW		 3599 mutex_unlock(&dev_priv->rps.hw_lock);
3600}
3601
0a073b84
JB		 3602void valleyview_set_rps(struct drm_device *dev, u8 val)
3603{
3604 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3605
0a073b84
JB		 3606 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3607 WARN_ON(val > dev_priv->rps.max_delay);
3608 WARN_ON(val < dev_priv->rps.min_delay);
3609
73008b98 3610 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3611 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3612 dev_priv->rps.cur_delay,
2ec3815f 3613 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3614
3615 if (val == dev_priv->rps.cur_delay)
3616 return;
3617
ae99258f 3618 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3619
80814ae4 3620 dev_priv->rps.cur_delay = val;
0a073b84 3621
2ec3815f 3622 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3623}
3624
44fc7d5c 3625static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3626{
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628
2b4e57bd 3629 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3630 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3631 /* Complete PM interrupt masking here doesn't race with the rps work
3632 * item again unmasking PM interrupts because that is using a different
3633 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3634 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3635
59cdb63d 3636 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3637 dev_priv->rps.pm_iir = 0;
59cdb63d 3638 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3639
4848405c 3640 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3641}
3642
44fc7d5c 3643static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3644{
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646
3647 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3648 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3649
44fc7d5c
DV		 3650 gen6_disable_rps_interrupts(dev);
3651}
3652
3653static void valleyview_disable_rps(struct drm_device *dev)
3654{
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656
3657 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3658
44fc7d5c 3659 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3660
3661 if (dev_priv->vlv_pctx) {
3662 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3663 dev_priv->vlv_pctx = NULL;
3664 }
d20d4f0c
JB		 3665}
3666
dc39fff7
BW		 3667static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3668{
3669 if (IS_GEN6(dev))
3670 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3671
3672 if (IS_HASWELL(dev))
3673 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3674
3675 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3676 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3677 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3678 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3679}
3680
2b4e57bd
ED		 3681int intel_enable_rc6(const struct drm_device *dev)
3682{
eb4926e4
DL		 3683 /* No RC6 before Ironlake */
3684 if (INTEL_INFO(dev)->gen < 5)
3685 return 0;
3686
456470eb 3687 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3688 if (i915_enable_rc6 >= 0)
3689 return i915_enable_rc6;
3690
6567d748
CW		 3691 /* Disable RC6 on Ironlake */
3692 if (INTEL_INFO(dev)->gen == 5)
3693 return 0;
2b4e57bd 3694
dc39fff7 3695 if (IS_HASWELL(dev))
4a637c2c 3696 return INTEL_RC6_ENABLE;
2b4e57bd 3697
456470eb 3698 /* snb/ivb have more than one rc6 state. */
dc39fff7 3699 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3700 return INTEL_RC6_ENABLE;
456470eb 3701
2b4e57bd
ED		 3702 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3703}
3704
44fc7d5c
DV		 3705static void gen6_enable_rps_interrupts(struct drm_device *dev)
3706{
3707 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3708 u32 enabled_intrs;
44fc7d5c
DV		 3709
3710 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3711 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3712 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3713 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3714 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3715
fd547d25 3716 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3717 enabled_intrs = GEN6_PM_RPS_EVENTS;
3718
3719 /* IVB and SNB hard hangs on looping batchbuffer
3720 * if GEN6_PM_UP_EI_EXPIRED is masked.
3721 */
3722 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3723 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3724
3725 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3726}
3727
6edee7f3
BW		 3728static void gen8_enable_rps(struct drm_device *dev)
3729{
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 struct intel_ring_buffer *ring;
3732 uint32_t rc6_mask = 0, rp_state_cap;
3733 int unused;
3734
3735 /* 1a: Software RC state - RC0 */
3736 I915_WRITE(GEN6_RC_STATE, 0);
3737
3738 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3739 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3740 gen6_gt_force_wake_get(dev_priv);
3741
3742 /* 2a: Disable RC states. */
3743 I915_WRITE(GEN6_RC_CONTROL, 0);
3744
3745 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3746
3747 /* 2b: Program RC6 thresholds.*/
3748 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3749 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3750 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3751 for_each_ring(ring, dev_priv, unused)
3752 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3753 I915_WRITE(GEN6_RC_SLEEP, 0);
3754 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3755
3756 /* 3: Enable RC6 */
3757 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3758 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3759 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3760 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3761 GEN6_RC_CTL_EI_MODE(1) |
3762 rc6_mask);
3763
3764 /* 4 Program defaults and thresholds for RPS*/
3765 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3766 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3767 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3768 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3769
3770 /* Docs recommend 900MHz, and 300 MHz respectively */
3771 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3772 dev_priv->rps.max_delay << 24 |
3773 dev_priv->rps.min_delay << 16);
3774
3775 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3776 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3777 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3778 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3779
3780 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3781
3782 /* 5: Enable RPS */
3783 I915_WRITE(GEN6_RP_CONTROL,
3784 GEN6_RP_MEDIA_TURBO |
3785 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3786 GEN6_RP_MEDIA_IS_GFX |
3787 GEN6_RP_ENABLE |
3788 GEN6_RP_UP_BUSY_AVG |
3789 GEN6_RP_DOWN_IDLE_AVG);
3790
3791 /* 6: Ring frequency + overclocking (our driver does this later */
3792
3793 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3794
3795 gen6_enable_rps_interrupts(dev);
3796
3797 gen6_gt_force_wake_put(dev_priv);
3798}
3799
79f5b2c7 3800static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3801{
79f5b2c7 3802 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3803 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3804 u32 rp_state_cap;
3805 u32 gt_perf_status;
31643d54 3806 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3807 u32 gtfifodbg;
2b4e57bd 3808 int rc6_mode;
42c0526c 3809 int i, ret;
2b4e57bd 3810
4fc688ce 3811 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3812
2b4e57bd
ED		 3813 /* Here begins a magic sequence of register writes to enable
3814 * auto-downclocking.
3815 *
3816 * Perhaps there might be some value in exposing these to
3817 * userspace...
3818 */
3819 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3820
3821 /* Clear the DBG now so we don't confuse earlier errors */
3822 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3823 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3824 I915_WRITE(GTFIFODBG, gtfifodbg);
3825 }
3826
3827 gen6_gt_force_wake_get(dev_priv);
3828
7b9e0ae6
CW		 3829 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3830 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3831
31c77388
BW		 3832 /* In units of 50MHz */
3833 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3834 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3835 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3836 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3837 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3838 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3839
2b4e57bd
ED		 3840 /* disable the counters and set deterministic thresholds */
3841 I915_WRITE(GEN6_RC_CONTROL, 0);
3842
3843 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3844 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3845 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3846 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3847 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3848
b4519513
CW		 3849 for_each_ring(ring, dev_priv, i)
3850 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3851
3852 I915_WRITE(GEN6_RC_SLEEP, 0);
3853 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3854 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3855 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3856 else
3857 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3858 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3859 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3860
5a7dc92a 3861 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3862 rc6_mode = intel_enable_rc6(dev_priv->dev);
3863 if (rc6_mode & INTEL_RC6_ENABLE)
3864 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3865
5a7dc92a
ED		 3866 /* We don't use those on Haswell */
3867 if (!IS_HASWELL(dev)) {
3868 if (rc6_mode & INTEL_RC6p_ENABLE)
3869 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3870
5a7dc92a
ED		 3871 if (rc6_mode & INTEL_RC6pp_ENABLE)
3872 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3873 }
2b4e57bd 3874
dc39fff7 3875 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3876
3877 I915_WRITE(GEN6_RC_CONTROL,
3878 rc6_mask |
3879 GEN6_RC_CTL_EI_MODE(1) |
3880 GEN6_RC_CTL_HW_ENABLE);
3881
dd75fdc8
CW		 3882 /* Power down if completely idle for over 50ms */
3883 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3884 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3885
42c0526c 3886 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3887 if (!ret) {
42c0526c
BW		 3888 pcu_mbox = 0;
3889 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3890 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3891 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3892 (dev_priv->rps.max_delay & 0xff) * 50,
3893 (pcu_mbox & 0xff) * 50);
31c77388 3894 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3895 }
3896 } else {
3897 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3898 }
3899
dd75fdc8
CW		 3900 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3901 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3902
44fc7d5c 3903 gen6_enable_rps_interrupts(dev);
2b4e57bd 3904
31643d54
BW		 3905 rc6vids = 0;
3906 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3907 if (IS_GEN6(dev) && ret) {
3908 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3909 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3910 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3911 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3912 rc6vids &= 0xffff00;
3913 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3914 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3915 if (ret)
3916 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3917 }
3918
2b4e57bd 3919 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3920}
3921
c67a470b 3922void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3923{
79f5b2c7 3924 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3925 int min_freq = 15;
3ebecd07
CW		 3926 unsigned int gpu_freq;
3927 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3928 int scaling_factor = 180;
eda79642 3929 struct cpufreq_policy *policy;
2b4e57bd 3930
4fc688ce 3931 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3932
eda79642
BW		 3933 policy = cpufreq_cpu_get(0);
3934 if (policy) {
3935 max_ia_freq = policy->cpuinfo.max_freq;
3936 cpufreq_cpu_put(policy);
3937 } else {
3938 /*
3939 * Default to measured freq if none found, PCU will ensure we
3940 * don't go over
3941 */
2b4e57bd 3942 max_ia_freq = tsc_khz;
eda79642 3943 }
2b4e57bd
ED		 3944
3945 /* Convert from kHz to MHz */
3946 max_ia_freq /= 1000;
3947
153b4b95 3948 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3949 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3950 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3951
2b4e57bd
ED		 3952 /*
3953 * For each potential GPU frequency, load a ring frequency we'd like
3954 * to use for memory access. We do this by specifying the IA frequency
3955 * the PCU should use as a reference to determine the ring frequency.
3956 */
c6a828d3 3957 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3958 gpu_freq--) {
c6a828d3 3959 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3960 unsigned int ia_freq = 0, ring_freq = 0;
3961
46c764d4
BW		 3962 if (INTEL_INFO(dev)->gen >= 8) {
3963 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3964 ring_freq = max(min_ring_freq, gpu_freq);
3965 } else if (IS_HASWELL(dev)) {
f6aca45c 3966 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3967 ring_freq = max(min_ring_freq, ring_freq);
3968 /* leave ia_freq as the default, chosen by cpufreq */
3969 } else {
3970 /* On older processors, there is no separate ring
3971 * clock domain, so in order to boost the bandwidth
3972 * of the ring, we need to upclock the CPU (ia_freq).
3973 *
3974 * For GPU frequencies less than 750MHz,
3975 * just use the lowest ring freq.
3976 */
3977 if (gpu_freq < min_freq)
3978 ia_freq = 800;
3979 else
3980 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3981 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3982 }
2b4e57bd 3983
42c0526c
BW		 3984 sandybridge_pcode_write(dev_priv,
3985 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3986 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3987 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3988 gpu_freq);
2b4e57bd 3989 }
2b4e57bd
ED		 3990}
3991
0a073b84
JB		 3992int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3993{
3994 u32 val, rp0;
3995
64936258 3996 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3997
3998 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3999 /* Clamp to max */
4000 rp0 = min_t(u32, rp0, 0xea);
4001
4002 return rp0;
4003}
4004
4005static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4006{
4007 u32 val, rpe;
4008
64936258 4009 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4010 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4011 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4012 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4013
4014 return rpe;
4015}
4016
4017int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4018{
64936258 4019 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4020}
4021
c9cddffc
JB		 4022static void valleyview_setup_pctx(struct drm_device *dev)
4023{
4024 struct drm_i915_private *dev_priv = dev->dev_private;
4025 struct drm_i915_gem_object *pctx;
4026 unsigned long pctx_paddr;
4027 u32 pcbr;
4028 int pctx_size = 24*1024;
4029
4030 pcbr = I915_READ(VLV_PCBR);
4031 if (pcbr) {
4032 /* BIOS set it up already, grab the pre-alloc'd space */
4033 int pcbr_offset;
4034
4035 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4036 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4037 pcbr_offset,
190d6cd5 4038 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4039 pctx_size);
4040 goto out;
4041 }
4042
4043 /*
4044 * From the Gunit register HAS:
4045 * The Gfx driver is expected to program this register and ensure
4046 * proper allocation within Gfx stolen memory. For example, this
4047 * register should be programmed such than the PCBR range does not
4048 * overlap with other ranges, such as the frame buffer, protected
4049 * memory, or any other relevant ranges.
4050 */
4051 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4052 if (!pctx) {
4053 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4054 return;
4055 }
4056
4057 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4058 I915_WRITE(VLV_PCBR, pctx_paddr);
4059
4060out:
4061 dev_priv->vlv_pctx = pctx;
4062}
4063
0a073b84
JB		 4064static void valleyview_enable_rps(struct drm_device *dev)
4065{
4066 struct drm_i915_private *dev_priv = dev->dev_private;
4067 struct intel_ring_buffer *ring;
a2b23fe0 4068 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4069 int i;
4070
4071 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4072
4073 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4074 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4075 gtfifodbg);
0a073b84
JB		 4076 I915_WRITE(GTFIFODBG, gtfifodbg);
4077 }
4078
c9cddffc
JB		 4079 valleyview_setup_pctx(dev);
4080
0a073b84
JB		 4081 gen6_gt_force_wake_get(dev_priv);
4082
4083 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4084 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4085 I915_WRITE(GEN6_RP_UP_EI, 66000);
4086 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4087
4088 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4089
4090 I915_WRITE(GEN6_RP_CONTROL,
4091 GEN6_RP_MEDIA_TURBO |
4092 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4093 GEN6_RP_MEDIA_IS_GFX |
4094 GEN6_RP_ENABLE |
4095 GEN6_RP_UP_BUSY_AVG |
4096 GEN6_RP_DOWN_IDLE_CONT);
4097
4098 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4099 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4100 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4101
4102 for_each_ring(ring, dev_priv, i)
4103 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4104
4105 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4106
4107 /* allows RC6 residency counter to work */
49798eb2
JB		 4108 I915_WRITE(VLV_COUNTER_CONTROL,
4109 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4110 VLV_MEDIA_RC6_COUNT_EN |
4111 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0
JB		 4112 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4113 rc6_mode = GEN7_RC_CTL_TO_MODE;
dc39fff7
BW		 4114
4115 intel_print_rc6_info(dev, rc6_mode);
4116
a2b23fe0 4117 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4118
64936258 4119 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4120
4121 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4122 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4123
0a073b84 4124 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 4125 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 4126 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 4127 dev_priv->rps.cur_delay);
0a073b84
JB		 4128
4129 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4130 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98 4131 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2ec3815f 4132 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
73008b98 4133 dev_priv->rps.max_delay);
0a073b84 4134
73008b98
VS		 4135 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4136 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 4137 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4138 dev_priv->rps.rpe_delay);
0a073b84 4139
73008b98
VS		 4140 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4141 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2ec3815f 4142 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
73008b98 4143 dev_priv->rps.min_delay);
0a073b84 4144
73008b98 4145 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 4146 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4147 dev_priv->rps.rpe_delay);
0a073b84 4148
73008b98 4149 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 4150
44fc7d5c 4151 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 4152
4153 gen6_gt_force_wake_put(dev_priv);
4154}
4155
930ebb46 4156void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4157{
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159
3e373948
DV		 4160 if (dev_priv->ips.renderctx) {
4161 i915_gem_object_unpin(dev_priv->ips.renderctx);
4162 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4163 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4164 }
4165
3e373948
DV		 4166 if (dev_priv->ips.pwrctx) {
4167 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4168 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4169 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4170 }
4171}
4172
930ebb46 4173static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4174{
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176
4177 if (I915_READ(PWRCTXA)) {
4178 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4179 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4180 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4181 50);
4182
4183 I915_WRITE(PWRCTXA, 0);
4184 POSTING_READ(PWRCTXA);
4185
4186 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4187 POSTING_READ(RSTDBYCTL);
4188 }
2b4e57bd
ED		 4189}
4190
4191static int ironlake_setup_rc6(struct drm_device *dev)
4192{
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4194
3e373948
DV		 4195 if (dev_priv->ips.renderctx == NULL)
4196 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4197 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4198 return -ENOMEM;
4199
3e373948
DV		 4200 if (dev_priv->ips.pwrctx == NULL)
4201 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4202 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4203 ironlake_teardown_rc6(dev);
4204 return -ENOMEM;
4205 }
4206
4207 return 0;
4208}
4209
930ebb46 4210static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4211{
4212 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 4213 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 4214 bool was_interruptible;
2b4e57bd
ED		 4215 int ret;
4216
4217 /* rc6 disabled by default due to repeated reports of hanging during
4218 * boot and resume.
4219 */
4220 if (!intel_enable_rc6(dev))
4221 return;
4222
79f5b2c7
DV		 4223 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4224
2b4e57bd 4225 ret = ironlake_setup_rc6(dev);
79f5b2c7 4226 if (ret)
2b4e57bd 4227 return;
2b4e57bd 4228
3e960501
CW		 4229 was_interruptible = dev_priv->mm.interruptible;
4230 dev_priv->mm.interruptible = false;
4231
2b4e57bd
ED		 4232 /*
4233 * GPU can automatically power down the render unit if given a page
4234 * to save state.
4235 */
6d90c952 4236 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4237 if (ret) {
4238 ironlake_teardown_rc6(dev);
3e960501 4239 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4240 return;
4241 }
4242
6d90c952
DV		 4243 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4244 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4245 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4246 MI_MM_SPACE_GTT |
4247 MI_SAVE_EXT_STATE_EN |
4248 MI_RESTORE_EXT_STATE_EN |
4249 MI_RESTORE_INHIBIT);
4250 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4251 intel_ring_emit(ring, MI_NOOP);
4252 intel_ring_emit(ring, MI_FLUSH);
4253 intel_ring_advance(ring);
2b4e57bd
ED		 4254
4255 /*
4256 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4257 * does an implicit flush, combined with MI_FLUSH above, it should be
4258 * safe to assume that renderctx is valid
4259 */
3e960501
CW		 4260 ret = intel_ring_idle(ring);
4261 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4262 if (ret) {
def27a58 4263 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4264 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4265 return;
4266 }
4267
f343c5f6 4268 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4269 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 4270
4271 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 4272}
4273
dde18883
ED		 4274static unsigned long intel_pxfreq(u32 vidfreq)
4275{
4276 unsigned long freq;
4277 int div = (vidfreq & 0x3f0000) >> 16;
4278 int post = (vidfreq & 0x3000) >> 12;
4279 int pre = (vidfreq & 0x7);
4280
4281 if (!pre)
4282 return 0;
4283
4284 freq = ((div * 133333) / ((1<<post) * pre));
4285
4286 return freq;
4287}
4288
eb48eb00
DV		 4289static const struct cparams {
4290 u16 i;
4291 u16 t;
4292 u16 m;
4293 u16 c;
4294} cparams[] = {
4295 { 1, 1333, 301, 28664 },
4296 { 1, 1066, 294, 24460 },
4297 { 1, 800, 294, 25192 },
4298 { 0, 1333, 276, 27605 },
4299 { 0, 1066, 276, 27605 },
4300 { 0, 800, 231, 23784 },
4301};
4302
f531dcb2 4303static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4304{
4305 u64 total_count, diff, ret;
4306 u32 count1, count2, count3, m = 0, c = 0;
4307 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4308 int i;
4309
02d71956
DV		 4310 assert_spin_locked(&mchdev_lock);
4311
20e4d407 4312 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4313
4314 /* Prevent division-by-zero if we are asking too fast.
4315 * Also, we don't get interesting results if we are polling
4316 * faster than once in 10ms, so just return the saved value
4317 * in such cases.
4318 */
4319 if (diff1 <= 10)
20e4d407 4320 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4321
4322 count1 = I915_READ(DMIEC);
4323 count2 = I915_READ(DDREC);
4324 count3 = I915_READ(CSIEC);
4325
4326 total_count = count1 + count2 + count3;
4327
4328 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4329 if (total_count < dev_priv->ips.last_count1) {
4330 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4331 diff += total_count;
4332 } else {
20e4d407 4333 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4334 }
4335
4336 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4337 if (cparams[i].i == dev_priv->ips.c_m &&
4338 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4339 m = cparams[i].m;
4340 c = cparams[i].c;
4341 break;
4342 }
4343 }
4344
4345 diff = div_u64(diff, diff1);
4346 ret = ((m * diff) + c);
4347 ret = div_u64(ret, 10);
4348
20e4d407
DV		 4349 dev_priv->ips.last_count1 = total_count;
4350 dev_priv->ips.last_time1 = now;
eb48eb00 4351
20e4d407 4352 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4353
4354 return ret;
4355}
4356
f531dcb2
CW		 4357unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4358{
4359 unsigned long val;
4360
4361 if (dev_priv->info->gen != 5)
4362 return 0;
4363
4364 spin_lock_irq(&mchdev_lock);
4365
4366 val = __i915_chipset_val(dev_priv);
4367
4368 spin_unlock_irq(&mchdev_lock);
4369
4370 return val;
4371}
4372
eb48eb00
DV		 4373unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4374{
4375 unsigned long m, x, b;
4376 u32 tsfs;
4377
4378 tsfs = I915_READ(TSFS);
4379
4380 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4381 x = I915_READ8(TR1);
4382
4383 b = tsfs & TSFS_INTR_MASK;
4384
4385 return ((m * x) / 127) - b;
4386}
4387
4388static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4389{
4390 static const struct v_table {
4391 u16 vd; /* in .1 mil */
4392 u16 vm; /* in .1 mil */
4393 } v_table[] = {
4394 { 0, 0, },
4395 { 375, 0, },
4396 { 500, 0, },
4397 { 625, 0, },
4398 { 750, 0, },
4399 { 875, 0, },
4400 { 1000, 0, },
4401 { 1125, 0, },
4402 { 4125, 3000, },
4403 { 4125, 3000, },
4404 { 4125, 3000, },
4405 { 4125, 3000, },
4406 { 4125, 3000, },
4407 { 4125, 3000, },
4408 { 4125, 3000, },
4409 { 4125, 3000, },
4410 { 4125, 3000, },
4411 { 4125, 3000, },
4412 { 4125, 3000, },
4413 { 4125, 3000, },
4414 { 4125, 3000, },
4415 { 4125, 3000, },
4416 { 4125, 3000, },
4417 { 4125, 3000, },
4418 { 4125, 3000, },
4419 { 4125, 3000, },
4420 { 4125, 3000, },
4421 { 4125, 3000, },
4422 { 4125, 3000, },
4423 { 4125, 3000, },
4424 { 4125, 3000, },
4425 { 4125, 3000, },
4426 { 4250, 3125, },
4427 { 4375, 3250, },
4428 { 4500, 3375, },
4429 { 4625, 3500, },
4430 { 4750, 3625, },
4431 { 4875, 3750, },
4432 { 5000, 3875, },
4433 { 5125, 4000, },
4434 { 5250, 4125, },
4435 { 5375, 4250, },
4436 { 5500, 4375, },
4437 { 5625, 4500, },
4438 { 5750, 4625, },
4439 { 5875, 4750, },
4440 { 6000, 4875, },
4441 { 6125, 5000, },
4442 { 6250, 5125, },
4443 { 6375, 5250, },
4444 { 6500, 5375, },
4445 { 6625, 5500, },
4446 { 6750, 5625, },
4447 { 6875, 5750, },
4448 { 7000, 5875, },
4449 { 7125, 6000, },
4450 { 7250, 6125, },
4451 { 7375, 6250, },
4452 { 7500, 6375, },
4453 { 7625, 6500, },
4454 { 7750, 6625, },
4455 { 7875, 6750, },
4456 { 8000, 6875, },
4457 { 8125, 7000, },
4458 { 8250, 7125, },
4459 { 8375, 7250, },
4460 { 8500, 7375, },
4461 { 8625, 7500, },
4462 { 8750, 7625, },
4463 { 8875, 7750, },
4464 { 9000, 7875, },
4465 { 9125, 8000, },
4466 { 9250, 8125, },
4467 { 9375, 8250, },
4468 { 9500, 8375, },
4469 { 9625, 8500, },
4470 { 9750, 8625, },
4471 { 9875, 8750, },
4472 { 10000, 8875, },
4473 { 10125, 9000, },
4474 { 10250, 9125, },
4475 { 10375, 9250, },
4476 { 10500, 9375, },
4477 { 10625, 9500, },
4478 { 10750, 9625, },
4479 { 10875, 9750, },
4480 { 11000, 9875, },
4481 { 11125, 10000, },
4482 { 11250, 10125, },
4483 { 11375, 10250, },
4484 { 11500, 10375, },
4485 { 11625, 10500, },
4486 { 11750, 10625, },
4487 { 11875, 10750, },
4488 { 12000, 10875, },
4489 { 12125, 11000, },
4490 { 12250, 11125, },
4491 { 12375, 11250, },
4492 { 12500, 11375, },
4493 { 12625, 11500, },
4494 { 12750, 11625, },
4495 { 12875, 11750, },
4496 { 13000, 11875, },
4497 { 13125, 12000, },
4498 { 13250, 12125, },
4499 { 13375, 12250, },
4500 { 13500, 12375, },
4501 { 13625, 12500, },
4502 { 13750, 12625, },
4503 { 13875, 12750, },
4504 { 14000, 12875, },
4505 { 14125, 13000, },
4506 { 14250, 13125, },
4507 { 14375, 13250, },
4508 { 14500, 13375, },
4509 { 14625, 13500, },
4510 { 14750, 13625, },
4511 { 14875, 13750, },
4512 { 15000, 13875, },
4513 { 15125, 14000, },
4514 { 15250, 14125, },
4515 { 15375, 14250, },
4516 { 15500, 14375, },
4517 { 15625, 14500, },
4518 { 15750, 14625, },
4519 { 15875, 14750, },
4520 { 16000, 14875, },
4521 { 16125, 15000, },
4522 };
4523 if (dev_priv->info->is_mobile)
4524 return v_table[pxvid].vm;
4525 else
4526 return v_table[pxvid].vd;
4527}
4528
02d71956 4529static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4530{
4531 struct timespec now, diff1;
4532 u64 diff;
4533 unsigned long diffms;
4534 u32 count;
4535
02d71956 4536 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4537
4538 getrawmonotonic(&now);
20e4d407 4539 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4540
4541 /* Don't divide by 0 */
4542 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4543 if (!diffms)
4544 return;
4545
4546 count = I915_READ(GFXEC);
4547
20e4d407
DV		 4548 if (count < dev_priv->ips.last_count2) {
4549 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4550 diff += count;
4551 } else {
20e4d407 4552 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4553 }
4554
20e4d407
DV		 4555 dev_priv->ips.last_count2 = count;
4556 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4557
4558 /* More magic constants... */
4559 diff = diff * 1181;
4560 diff = div_u64(diff, diffms * 10);
20e4d407 4561 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4562}
4563
02d71956
DV		 4564void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4565{
4566 if (dev_priv->info->gen != 5)
4567 return;
4568
9270388e 4569 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4570
4571 __i915_update_gfx_val(dev_priv);
4572
9270388e 4573 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4574}
4575
f531dcb2 4576static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4577{
4578 unsigned long t, corr, state1, corr2, state2;
4579 u32 pxvid, ext_v;
4580
02d71956
DV		 4581 assert_spin_locked(&mchdev_lock);
4582
c6a828d3 4583 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4584 pxvid = (pxvid >> 24) & 0x7f;
4585 ext_v = pvid_to_extvid(dev_priv, pxvid);
4586
4587 state1 = ext_v;
4588
4589 t = i915_mch_val(dev_priv);
4590
4591 /* Revel in the empirically derived constants */
4592
4593 /* Correction factor in 1/100000 units */
4594 if (t > 80)
4595 corr = ((t * 2349) + 135940);
4596 else if (t >= 50)
4597 corr = ((t * 964) + 29317);
4598 else /* < 50 */
4599 corr = ((t * 301) + 1004);
4600
4601 corr = corr * ((150142 * state1) / 10000 - 78642);
4602 corr /= 100000;
20e4d407 4603 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4604
4605 state2 = (corr2 * state1) / 10000;
4606 state2 /= 100; /* convert to mW */
4607
02d71956 4608 __i915_update_gfx_val(dev_priv);
eb48eb00 4609
20e4d407 4610 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4611}
4612
f531dcb2
CW		 4613unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4614{
4615 unsigned long val;
4616
4617 if (dev_priv->info->gen != 5)
4618 return 0;
4619
4620 spin_lock_irq(&mchdev_lock);
4621
4622 val = __i915_gfx_val(dev_priv);
4623
4624 spin_unlock_irq(&mchdev_lock);
4625
4626 return val;
4627}
4628
eb48eb00
DV		 4629/**
4630 * i915_read_mch_val - return value for IPS use
4631 *
4632 * Calculate and return a value for the IPS driver to use when deciding whether
4633 * we have thermal and power headroom to increase CPU or GPU power budget.
4634 */
4635unsigned long i915_read_mch_val(void)
4636{
4637 struct drm_i915_private *dev_priv;
4638 unsigned long chipset_val, graphics_val, ret = 0;
4639
9270388e 4640 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4641 if (!i915_mch_dev)
4642 goto out_unlock;
4643 dev_priv = i915_mch_dev;
4644
f531dcb2
CW		 4645 chipset_val = __i915_chipset_val(dev_priv);
4646 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4647
4648 ret = chipset_val + graphics_val;
4649
4650out_unlock:
9270388e 4651 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4652
4653 return ret;
4654}
4655EXPORT_SYMBOL_GPL(i915_read_mch_val);
4656
4657/**
4658 * i915_gpu_raise - raise GPU frequency limit
4659 *
4660 * Raise the limit; IPS indicates we have thermal headroom.
4661 */
4662bool i915_gpu_raise(void)
4663{
4664 struct drm_i915_private *dev_priv;
4665 bool ret = true;
4666
9270388e 4667 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4668 if (!i915_mch_dev) {
4669 ret = false;
4670 goto out_unlock;
4671 }
4672 dev_priv = i915_mch_dev;
4673
20e4d407
DV		 4674 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4675 dev_priv->ips.max_delay--;
eb48eb00
DV		 4676
4677out_unlock:
9270388e 4678 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4679
4680 return ret;
4681}
4682EXPORT_SYMBOL_GPL(i915_gpu_raise);
4683
4684/**
4685 * i915_gpu_lower - lower GPU frequency limit
4686 *
4687 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4688 * frequency maximum.
4689 */
4690bool i915_gpu_lower(void)
4691{
4692 struct drm_i915_private *dev_priv;
4693 bool ret = true;
4694
9270388e 4695 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4696 if (!i915_mch_dev) {
4697 ret = false;
4698 goto out_unlock;
4699 }
4700 dev_priv = i915_mch_dev;
4701
20e4d407
DV		 4702 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4703 dev_priv->ips.max_delay++;
eb48eb00
DV		 4704
4705out_unlock:
9270388e 4706 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4707
4708 return ret;
4709}
4710EXPORT_SYMBOL_GPL(i915_gpu_lower);
4711
4712/**
4713 * i915_gpu_busy - indicate GPU business to IPS
4714 *
4715 * Tell the IPS driver whether or not the GPU is busy.
4716 */
4717bool i915_gpu_busy(void)
4718{
4719 struct drm_i915_private *dev_priv;
f047e395 4720 struct intel_ring_buffer *ring;
eb48eb00 4721 bool ret = false;
f047e395 4722 int i;
eb48eb00 4723
9270388e 4724 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4725 if (!i915_mch_dev)
4726 goto out_unlock;
4727 dev_priv = i915_mch_dev;
4728
f047e395
CW		 4729 for_each_ring(ring, dev_priv, i)
4730 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4731
4732out_unlock:
9270388e 4733 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4734
4735 return ret;
4736}
4737EXPORT_SYMBOL_GPL(i915_gpu_busy);
4738
4739/**
4740 * i915_gpu_turbo_disable - disable graphics turbo
4741 *
4742 * Disable graphics turbo by resetting the max frequency and setting the
4743 * current frequency to the default.
4744 */
4745bool i915_gpu_turbo_disable(void)
4746{
4747 struct drm_i915_private *dev_priv;
4748 bool ret = true;
4749
9270388e 4750 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4751 if (!i915_mch_dev) {
4752 ret = false;
4753 goto out_unlock;
4754 }
4755 dev_priv = i915_mch_dev;
4756
20e4d407 4757 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4758
20e4d407 4759 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4760 ret = false;
4761
4762out_unlock:
9270388e 4763 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4764
4765 return ret;
4766}
4767EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4768
4769/**
4770 * Tells the intel_ips driver that the i915 driver is now loaded, if
4771 * IPS got loaded first.
4772 *
4773 * This awkward dance is so that neither module has to depend on the
4774 * other in order for IPS to do the appropriate communication of
4775 * GPU turbo limits to i915.
4776 */
4777static void
4778ips_ping_for_i915_load(void)
4779{
4780 void (*link)(void);
4781
4782 link = symbol_get(ips_link_to_i915_driver);
4783 if (link) {
4784 link();
4785 symbol_put(ips_link_to_i915_driver);
4786 }
4787}
4788
4789void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4790{
02d71956
DV		 4791 /* We only register the i915 ips part with intel-ips once everything is
4792 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4793 spin_lock_irq(&mchdev_lock);
eb48eb00 4794 i915_mch_dev = dev_priv;
9270388e 4795 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4796
4797 ips_ping_for_i915_load();
4798}
4799
4800void intel_gpu_ips_teardown(void)
4801{
9270388e 4802 spin_lock_irq(&mchdev_lock);
eb48eb00 4803 i915_mch_dev = NULL;
9270388e 4804 spin_unlock_irq(&mchdev_lock);
eb48eb00 4805}
8090c6b9 4806static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4807{
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809 u32 lcfuse;
4810 u8 pxw[16];
4811 int i;
4812
4813 /* Disable to program */
4814 I915_WRITE(ECR, 0);
4815 POSTING_READ(ECR);
4816
4817 /* Program energy weights for various events */
4818 I915_WRITE(SDEW, 0x15040d00);
4819 I915_WRITE(CSIEW0, 0x007f0000);
4820 I915_WRITE(CSIEW1, 0x1e220004);
4821 I915_WRITE(CSIEW2, 0x04000004);
4822
4823 for (i = 0; i < 5; i++)
4824 I915_WRITE(PEW + (i * 4), 0);
4825 for (i = 0; i < 3; i++)
4826 I915_WRITE(DEW + (i * 4), 0);
4827
4828 /* Program P-state weights to account for frequency power adjustment */
4829 for (i = 0; i < 16; i++) {
4830 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4831 unsigned long freq = intel_pxfreq(pxvidfreq);
4832 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4833 PXVFREQ_PX_SHIFT;
4834 unsigned long val;
4835
4836 val = vid * vid;
4837 val *= (freq / 1000);
4838 val *= 255;
4839 val /= (127*127*900);
4840 if (val > 0xff)
4841 DRM_ERROR("bad pxval: %ld\n", val);
4842 pxw[i] = val;
4843 }
4844 /* Render standby states get 0 weight */
4845 pxw[14] = 0;
4846 pxw[15] = 0;
4847
4848 for (i = 0; i < 4; i++) {
4849 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4850 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4851 I915_WRITE(PXW + (i * 4), val);
4852 }
4853
4854 /* Adjust magic regs to magic values (more experimental results) */
4855 I915_WRITE(OGW0, 0);
4856 I915_WRITE(OGW1, 0);
4857 I915_WRITE(EG0, 0x00007f00);
4858 I915_WRITE(EG1, 0x0000000e);
4859 I915_WRITE(EG2, 0x000e0000);
4860 I915_WRITE(EG3, 0x68000300);
4861 I915_WRITE(EG4, 0x42000000);
4862 I915_WRITE(EG5, 0x00140031);
4863 I915_WRITE(EG6, 0);
4864 I915_WRITE(EG7, 0);
4865
4866 for (i = 0; i < 8; i++)
4867 I915_WRITE(PXWL + (i * 4), 0);
4868
4869 /* Enable PMON + select events */
4870 I915_WRITE(ECR, 0x80000019);
4871
4872 lcfuse = I915_READ(LCFUSE02);
4873
20e4d407 4874 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4875}
4876
8090c6b9
DV		 4877void intel_disable_gt_powersave(struct drm_device *dev)
4878{
1a01ab3b
JB		 4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880
fd0c0642
DV		 4881 /* Interrupts should be disabled already to avoid re-arming. */
4882 WARN_ON(dev->irq_enabled);
4883
930ebb46 4884 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4885 ironlake_disable_drps(dev);
930ebb46 4886 ironlake_disable_rc6(dev);
0a073b84 4887 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4888 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4889 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4890 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4891 if (IS_VALLEYVIEW(dev))
4892 valleyview_disable_rps(dev);
4893 else
4894 gen6_disable_rps(dev);
c0951f0c 4895 dev_priv->rps.enabled = false;
4fc688ce 4896 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4897 }
8090c6b9
DV		 4898}
4899
1a01ab3b
JB		 4900static void intel_gen6_powersave_work(struct work_struct *work)
4901{
4902 struct drm_i915_private *dev_priv =
4903 container_of(work, struct drm_i915_private,
4904 rps.delayed_resume_work.work);
4905 struct drm_device *dev = dev_priv->dev;
4906
4fc688ce 4907 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4908
4909 if (IS_VALLEYVIEW(dev)) {
4910 valleyview_enable_rps(dev);
6edee7f3
BW		 4911 } else if (IS_BROADWELL(dev)) {
4912 gen8_enable_rps(dev);
4913 gen6_update_ring_freq(dev);
0a073b84
JB		 4914 } else {
4915 gen6_enable_rps(dev);
4916 gen6_update_ring_freq(dev);
4917 }
c0951f0c 4918 dev_priv->rps.enabled = true;
4fc688ce 4919 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4920}
4921
8090c6b9
DV		 4922void intel_enable_gt_powersave(struct drm_device *dev)
4923{
1a01ab3b
JB		 4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925
8090c6b9
DV		 4926 if (IS_IRONLAKE_M(dev)) {
4927 ironlake_enable_drps(dev);
4928 ironlake_enable_rc6(dev);
4929 intel_init_emon(dev);
0a073b84 4930 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4931 /*
4932 * PCU communication is slow and this doesn't need to be
4933 * done at any specific time, so do this out of our fast path
4934 * to make resume and init faster.
4935 */
4936 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4937 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4938 }
4939}
4940
3107bd48
DV		 4941static void ibx_init_clock_gating(struct drm_device *dev)
4942{
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944
4945 /*
4946 * On Ibex Peak and Cougar Point, we need to disable clock
4947 * gating for the panel power sequencer or it will fail to
4948 * start up when no ports are active.
4949 */
4950 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4951}
4952
0e088b8f
VS		 4953static void g4x_disable_trickle_feed(struct drm_device *dev)
4954{
4955 struct drm_i915_private *dev_priv = dev->dev_private;
4956 int pipe;
4957
4958 for_each_pipe(pipe) {
4959 I915_WRITE(DSPCNTR(pipe),
4960 I915_READ(DSPCNTR(pipe)) |
4961 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4962 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4963 }
4964}
4965
1fa61106 4966static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4967{
4968 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4969 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4970
f1e8fa56
DL		 4971 /*
4972 * Required for FBC
4973 * WaFbcDisableDpfcClockGating:ilk
4974 */
4d47e4f5
DL		 4975 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4976 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4977 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4978
4979 I915_WRITE(PCH_3DCGDIS0,
4980 MARIUNIT_CLOCK_GATE_DISABLE |
4981 SVSMUNIT_CLOCK_GATE_DISABLE);
4982 I915_WRITE(PCH_3DCGDIS1,
4983 VFMUNIT_CLOCK_GATE_DISABLE);
4984
6f1d69b0
ED		 4985 /*
4986 * According to the spec the following bits should be set in
4987 * order to enable memory self-refresh
4988 * The bit 22/21 of 0x42004
4989 * The bit 5 of 0x42020
4990 * The bit 15 of 0x45000
4991 */
4992 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4993 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4994 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4995 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4996 I915_WRITE(DISP_ARB_CTL,
4997 (I915_READ(DISP_ARB_CTL) |
4998 DISP_FBC_WM_DIS));
4999 I915_WRITE(WM3_LP_ILK, 0);
5000 I915_WRITE(WM2_LP_ILK, 0);
5001 I915_WRITE(WM1_LP_ILK, 0);
5002
5003 /*
5004 * Based on the document from hardware guys the following bits
5005 * should be set unconditionally in order to enable FBC.
5006 * The bit 22 of 0x42000
5007 * The bit 22 of 0x42004
5008 * The bit 7,8,9 of 0x42020.
5009 */
5010 if (IS_IRONLAKE_M(dev)) {
4bb35334 5011 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5012 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5013 I915_READ(ILK_DISPLAY_CHICKEN1) |
5014 ILK_FBCQ_DIS);
5015 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5016 I915_READ(ILK_DISPLAY_CHICKEN2) |
5017 ILK_DPARB_GATE);
6f1d69b0
ED		 5018 }
5019
4d47e4f5
DL		 5020 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5021
6f1d69b0
ED		 5022 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5023 I915_READ(ILK_DISPLAY_CHICKEN2) |
5024 ILK_ELPIN_409_SELECT);
5025 I915_WRITE(_3D_CHICKEN2,
5026 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5027 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5028
ecdb4eb7 5029 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5030 I915_WRITE(CACHE_MODE_0,
5031 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5032
0e088b8f 5033 g4x_disable_trickle_feed(dev);
bdad2b2f 5034
3107bd48
DV		 5035 ibx_init_clock_gating(dev);
5036}
5037
5038static void cpt_init_clock_gating(struct drm_device *dev)
5039{
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041 int pipe;
3f704fa2 5042 uint32_t val;
3107bd48
DV		 5043
5044 /*
5045 * On Ibex Peak and Cougar Point, we need to disable clock
5046 * gating for the panel power sequencer or it will fail to
5047 * start up when no ports are active.
5048 */
cd664078
JB		 5049 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5050 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5051 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5052 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5053 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5054 /* The below fixes the weird display corruption, a few pixels shifted
5055 * downward, on (only) LVDS of some HP laptops with IVY.
5056 */
3f704fa2 5057 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5058 val = I915_READ(TRANS_CHICKEN2(pipe));
5059 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5060 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5061 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5062 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5063 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5064 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5065 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5066 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5067 }
3107bd48
DV		 5068 /* WADP0ClockGatingDisable */
5069 for_each_pipe(pipe) {
5070 I915_WRITE(TRANS_CHICKEN1(pipe),
5071 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5072 }
6f1d69b0
ED		 5073}
5074
1d7aaa0c
DV		 5075static void gen6_check_mch_setup(struct drm_device *dev)
5076{
5077 struct drm_i915_private *dev_priv = dev->dev_private;
5078 uint32_t tmp;
5079
5080 tmp = I915_READ(MCH_SSKPD);
5081 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5082 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5083 DRM_INFO("This can cause pipe underruns and display issues.\n");
5084 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5085 }
5086}
5087
1fa61106 5088static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5089{
5090 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5091 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5092
231e54f6 5093 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5094
5095 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5096 I915_READ(ILK_DISPLAY_CHICKEN2) |
5097 ILK_ELPIN_409_SELECT);
5098
ecdb4eb7 5099 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5100 I915_WRITE(_3D_CHICKEN,
5101 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5102
ecdb4eb7 5103 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5104 if (IS_SNB_GT1(dev))
5105 I915_WRITE(GEN6_GT_MODE,
5106 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5107
6f1d69b0
ED		 5108 I915_WRITE(WM3_LP_ILK, 0);
5109 I915_WRITE(WM2_LP_ILK, 0);
5110 I915_WRITE(WM1_LP_ILK, 0);
5111
6f1d69b0 5112 I915_WRITE(CACHE_MODE_0,
50743298 5113 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5114
5115 I915_WRITE(GEN6_UCGCTL1,
5116 I915_READ(GEN6_UCGCTL1) |
5117 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5118 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5119
5120 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5121 * gating disable must be set. Failure to set it results in
5122 * flickering pixels due to Z write ordering failures after
5123 * some amount of runtime in the Mesa "fire" demo, and Unigine
5124 * Sanctuary and Tropics, and apparently anything else with
5125 * alpha test or pixel discard.
5126 *
5127 * According to the spec, bit 11 (RCCUNIT) must also be set,
5128 * but we didn't debug actual testcases to find it out.
0f846f81 5129 *
ecdb4eb7
DL		 5130 * Also apply WaDisableVDSUnitClockGating:snb and
5131 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 5132 */
5133 I915_WRITE(GEN6_UCGCTL2,
0f846f81 5134 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 5135 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5136 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5137
5138 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 5139 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5140 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 5141
5142 /*
5143 * According to the spec the following bits should be
5144 * set in order to enable memory self-refresh and fbc:
5145 * The bit21 and bit22 of 0x42000
5146 * The bit21 and bit22 of 0x42004
5147 * The bit5 and bit7 of 0x42020
5148 * The bit14 of 0x70180
5149 * The bit14 of 0x71180
4bb35334
DL		 5150 *
5151 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5152 */
5153 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5154 I915_READ(ILK_DISPLAY_CHICKEN1) |
5155 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5156 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5157 I915_READ(ILK_DISPLAY_CHICKEN2) |
5158 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5159 I915_WRITE(ILK_DSPCLK_GATE_D,
5160 I915_READ(ILK_DSPCLK_GATE_D) |
5161 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5162 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5163
0e088b8f 5164 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 5165
5166 /* The default value should be 0x200 according to docs, but the two
5167 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5168 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5169 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 5170
5171 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5172
5173 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5174}
5175
5176static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5177{
5178 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5179
5180 reg &= ~GEN7_FF_SCHED_MASK;
5181 reg |= GEN7_FF_TS_SCHED_HW;
5182 reg |= GEN7_FF_VS_SCHED_HW;
5183 reg |= GEN7_FF_DS_SCHED_HW;
5184
41c0b3a8
BW		 5185 if (IS_HASWELL(dev_priv->dev))
5186 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5187
6f1d69b0
ED		 5188 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5189}
5190
17a303ec
PZ		 5191static void lpt_init_clock_gating(struct drm_device *dev)
5192{
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194
5195 /*
5196 * TODO: this bit should only be enabled when really needed, then
5197 * disabled when not needed anymore in order to save power.
5198 */
5199 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5200 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5201 I915_READ(SOUTH_DSPCLK_GATE_D) |
5202 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5203
5204 /* WADPOClockGatingDisable:hsw */
5205 I915_WRITE(_TRANSA_CHICKEN1,
5206 I915_READ(_TRANSA_CHICKEN1) |
5207 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5208}
5209
7d708ee4
ID		 5210static void lpt_suspend_hw(struct drm_device *dev)
5211{
5212 struct drm_i915_private *dev_priv = dev->dev_private;
5213
5214 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5215 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5216
5217 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5218 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5219 }
5220}
5221
1020a5c2
BW		 5222static void gen8_init_clock_gating(struct drm_device *dev)
5223{
5224 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 5225 enum pipe i;
1020a5c2
BW		 5226
5227 I915_WRITE(WM3_LP_ILK, 0);
5228 I915_WRITE(WM2_LP_ILK, 0);
5229 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5230
5231 /* FIXME(BDW): Check all the w/a, some might only apply to
5232 * pre-production hw. */
5233
fd392b60
BW		 5234 WARN(!i915_preliminary_hw_support,
5235 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5236 I915_WRITE(HALF_SLICE_CHICKEN3,
5237 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5238 I915_WRITE(HALF_SLICE_CHICKEN3,
5239 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5240 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5241
7f88da0c
BW		 5242 I915_WRITE(_3D_CHICKEN3,
5243 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5244
a75f3628
BW		 5245 I915_WRITE(COMMON_SLICE_CHICKEN2,
5246 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5247
4c2e7a5f
BW		 5248 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5249 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5250
50ed5fbd
BW		 5251 /* WaSwitchSolVfFArbitrationPriority */
5252 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce
BW		 5253
5254 /* WaPsrDPAMaskVBlankInSRD */
5255 I915_WRITE(CHICKEN_PAR1_1,
5256 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5257
5258 /* WaPsrDPRSUnmaskVBlankInSRD */
5259 for_each_pipe(i) {
5260 I915_WRITE(CHICKEN_PIPESL_1(i),
5261 I915_READ(CHICKEN_PIPESL_1(i) |
5262 DPRS_MASK_VBLANK_SRD));
5263 }
1020a5c2
BW		 5264}
5265
cad2a2d7
ED		 5266static void haswell_init_clock_gating(struct drm_device *dev)
5267{
5268 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 5269
5270 I915_WRITE(WM3_LP_ILK, 0);
5271 I915_WRITE(WM2_LP_ILK, 0);
5272 I915_WRITE(WM1_LP_ILK, 0);
5273
5274 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5275 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 5276 */
5277 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5278
ecdb4eb7 5279 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 5280 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5281 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5282
ecdb4eb7 5283 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 5284 I915_WRITE(GEN7_L3CNTLREG1,
5285 GEN7_WA_FOR_GEN7_L3_CONTROL);
5286 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5287 GEN7_WA_L3_CHICKEN_MODE);
5288
f3fc4884
FJ		 5289 /* L3 caching of data atomics doesn't work -- disable it. */
5290 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5291 I915_WRITE(HSW_ROW_CHICKEN3,
5292 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5293
ecdb4eb7 5294 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5295 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5296 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5297 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5298
ecdb4eb7 5299 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 5300 gen7_setup_fixed_func_scheduler(dev_priv);
5301
ecdb4eb7 5302 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5303 I915_WRITE(CACHE_MODE_1,
5304 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5305
ecdb4eb7 5306 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5307 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5308
90a88643
PZ		 5309 /* WaRsPkgCStateDisplayPMReq:hsw */
5310 I915_WRITE(CHICKEN_PAR1_1,
5311 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5312
17a303ec 5313 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5314}
5315
1fa61106 5316static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5317{
5318 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5319 uint32_t snpcr;
6f1d69b0 5320
6f1d69b0
ED		 5321 I915_WRITE(WM3_LP_ILK, 0);
5322 I915_WRITE(WM2_LP_ILK, 0);
5323 I915_WRITE(WM1_LP_ILK, 0);
5324
231e54f6 5325 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5326
ecdb4eb7 5327 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5328 I915_WRITE(_3D_CHICKEN3,
5329 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5330
ecdb4eb7 5331 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5332 I915_WRITE(IVB_CHICKEN3,
5333 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5334 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5335
ecdb4eb7 5336 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5337 if (IS_IVB_GT1(dev))
5338 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5339 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5340 else
5341 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5342 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5343
ecdb4eb7 5344 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5345 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5346 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5347
ecdb4eb7 5348 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5349 I915_WRITE(GEN7_L3CNTLREG1,
5350 GEN7_WA_FOR_GEN7_L3_CONTROL);
5351 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5352 GEN7_WA_L3_CHICKEN_MODE);
5353 if (IS_IVB_GT1(dev))
5354 I915_WRITE(GEN7_ROW_CHICKEN2,
5355 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5356 else
5357 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5358 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5359
6f1d69b0 5360
ecdb4eb7 5361 /* WaForceL3Serialization:ivb */
61939d97
JB		 5362 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5363 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5364
0f846f81
JB		 5365 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5366 * gating disable must be set. Failure to set it results in
5367 * flickering pixels due to Z write ordering failures after
5368 * some amount of runtime in the Mesa "fire" demo, and Unigine
5369 * Sanctuary and Tropics, and apparently anything else with
5370 * alpha test or pixel discard.
5371 *
5372 * According to the spec, bit 11 (RCCUNIT) must also be set,
5373 * but we didn't debug actual testcases to find it out.
5374 *
5375 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5376 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5377 */
5378 I915_WRITE(GEN6_UCGCTL2,
5379 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5380 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5381
ecdb4eb7 5382 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5383 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5384 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5385 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5386
0e088b8f 5387 g4x_disable_trickle_feed(dev);
6f1d69b0 5388
ecdb4eb7 5389 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5390 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5391
ecdb4eb7 5392 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5393 I915_WRITE(CACHE_MODE_1,
5394 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5395
5396 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5397 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5398 snpcr |= GEN6_MBC_SNPCR_MED;
5399 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5400
ab5c608b
BW		 5401 if (!HAS_PCH_NOP(dev))
5402 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5403
5404 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5405}
5406
1fa61106 5407static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5408{
5409 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5410 u32 val;
5411
5412 mutex_lock(&dev_priv->rps.hw_lock);
5413 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5415 switch ((val >> 6) & 3) {
5416 case 0:
85b1d7b3
JB		 5417 dev_priv->mem_freq = 800;
5418 break;
f64a28a7 5419 case 1:
85b1d7b3
JB		 5420 dev_priv->mem_freq = 1066;
5421 break;
f64a28a7 5422 case 2:
85b1d7b3
JB		 5423 dev_priv->mem_freq = 1333;
5424 break;
f64a28a7 5425 case 3:
2325991e 5426 dev_priv->mem_freq = 1333;
f64a28a7 5427 break;
85b1d7b3
JB		 5428 }
5429 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5430
d7fe0cc0 5431 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5432
ecdb4eb7 5433 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5434 I915_WRITE(_3D_CHICKEN3,
5435 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5436
ecdb4eb7 5437 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5438 I915_WRITE(IVB_CHICKEN3,
5439 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5440 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5441
ecdb4eb7 5442 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5443 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5444 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5445 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5446
ecdb4eb7 5447 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5448 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5449 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5450
ecdb4eb7 5451 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5452 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5453 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5454
ecdb4eb7 5455 /* WaForceL3Serialization:vlv */
61939d97
JB		 5456 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5457 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5458
ecdb4eb7 5459 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5460 I915_WRITE(GEN7_ROW_CHICKEN2,
5461 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5462
ecdb4eb7 5463 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5464 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5465 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5466 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5467
0f846f81
JB		 5468 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5469 * gating disable must be set. Failure to set it results in
5470 * flickering pixels due to Z write ordering failures after
5471 * some amount of runtime in the Mesa "fire" demo, and Unigine
5472 * Sanctuary and Tropics, and apparently anything else with
5473 * alpha test or pixel discard.
5474 *
5475 * According to the spec, bit 11 (RCCUNIT) must also be set,
5476 * but we didn't debug actual testcases to find it out.
5477 *
5478 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5479 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5480 *
ecdb4eb7
DL		 5481 * Also apply WaDisableVDSUnitClockGating:vlv and
5482 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5483 */
5484 I915_WRITE(GEN6_UCGCTL2,
5485 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5486 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5487 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5488 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5489 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5490
e3f33d46
JB		 5491 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5492
e0d8d59b 5493 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5494
6b26c86d
DV		 5495 I915_WRITE(CACHE_MODE_1,
5496 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5497
2d809570 5498 /*
ecdb4eb7 5499 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5500 * Disable clock gating on th GCFG unit to prevent a delay
5501 * in the reporting of vblank events.
5502 */
4e8c84a5
JB		 5503 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5504
5505 /* Conservative clock gating settings for now */
5506 I915_WRITE(0x9400, 0xffffffff);
5507 I915_WRITE(0x9404, 0xffffffff);
5508 I915_WRITE(0x9408, 0xffffffff);
5509 I915_WRITE(0x940c, 0xffffffff);
5510 I915_WRITE(0x9410, 0xffffffff);
5511 I915_WRITE(0x9414, 0xffffffff);
5512 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5513}
5514
1fa61106 5515static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5516{
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 uint32_t dspclk_gate;
5519
5520 I915_WRITE(RENCLK_GATE_D1, 0);
5521 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5522 GS_UNIT_CLOCK_GATE_DISABLE |
5523 CL_UNIT_CLOCK_GATE_DISABLE);
5524 I915_WRITE(RAMCLK_GATE_D, 0);
5525 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5526 OVRUNIT_CLOCK_GATE_DISABLE |
5527 OVCUNIT_CLOCK_GATE_DISABLE;
5528 if (IS_GM45(dev))
5529 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5530 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5531
5532 /* WaDisableRenderCachePipelinedFlush */
5533 I915_WRITE(CACHE_MODE_0,
5534 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5535
0e088b8f 5536 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5537}
5538
1fa61106 5539static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5540{
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542
5543 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5544 I915_WRITE(RENCLK_GATE_D2, 0);
5545 I915_WRITE(DSPCLK_GATE_D, 0);
5546 I915_WRITE(RAMCLK_GATE_D, 0);
5547 I915_WRITE16(DEUC, 0);
20f94967
VS		 5548 I915_WRITE(MI_ARB_STATE,
5549 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5550}
5551
1fa61106 5552static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5553{
5554 struct drm_i915_private *dev_priv = dev->dev_private;
5555
5556 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5557 I965_RCC_CLOCK_GATE_DISABLE |
5558 I965_RCPB_CLOCK_GATE_DISABLE |
5559 I965_ISC_CLOCK_GATE_DISABLE |
5560 I965_FBC_CLOCK_GATE_DISABLE);
5561 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5562 I915_WRITE(MI_ARB_STATE,
5563 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5564}
5565
1fa61106 5566static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5567{
5568 struct drm_i915_private *dev_priv = dev->dev_private;
5569 u32 dstate = I915_READ(D_STATE);
5570
5571 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5572 DSTATE_DOT_CLOCK_GATING;
5573 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5574
5575 if (IS_PINEVIEW(dev))
5576 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5577
5578 /* IIR "flip pending" means done if this bit is set */
5579 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5580}
5581
1fa61106 5582static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5583{
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585
5586 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5587}
5588
1fa61106 5589static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5590{
5591 struct drm_i915_private *dev_priv = dev->dev_private;
5592
5593 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5594}
5595
6f1d69b0
ED		 5596void intel_init_clock_gating(struct drm_device *dev)
5597{
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599
5600 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5601}
5602
7d708ee4
ID		 5603void intel_suspend_hw(struct drm_device *dev)
5604{
5605 if (HAS_PCH_LPT(dev))
5606 lpt_suspend_hw(dev);
5607}
5608
bddc7645
ID		 5609static bool is_always_on_power_domain(struct drm_device *dev,
5610 enum intel_display_power_domain domain)
5611{
5612 unsigned long always_on_domains;
5613
5614 BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
5615
6745a2ce
PZ		 5616 if (IS_BROADWELL(dev)) {
5617 always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS;
5618 } else if (IS_HASWELL(dev)) {
bddc7645
ID		 5619 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
5620 } else {
5621 WARN_ON(1);
5622 return true;
5623 }
5624
5625 return BIT(domain) & always_on_domains;
5626}
5627
15d199ea
PZ		 5628/**
5629 * We should only use the power well if we explicitly asked the hardware to
5630 * enable it, so check if it's enabled and also check if we've requested it to
5631 * be enabled.
5632 */
b97186f0
PZ		 5633bool intel_display_power_enabled(struct drm_device *dev,
5634 enum intel_display_power_domain domain)
15d199ea
PZ		 5635{
5636 struct drm_i915_private *dev_priv = dev->dev_private;
5637
b97186f0
PZ		 5638 if (!HAS_POWER_WELL(dev))
5639 return true;
5640
bddc7645 5641 if (is_always_on_power_domain(dev, domain))
b97186f0 5642 return true;
bddc7645
ID		 5643
5644 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6aedd1f5 5645 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
15d199ea
PZ		 5646}
5647
a38911a3 5648static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5649{
5650 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c 5651 bool is_enabled, enable_requested;
596cc11e 5652 unsigned long irqflags;
fa42e23c 5653 uint32_t tmp;
d0d3e513 5654
fa42e23c 5655 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5656 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5657 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5658
fa42e23c
PZ		 5659 if (enable) {
5660 if (!enable_requested)
6aedd1f5
PZ		 5661 I915_WRITE(HSW_PWR_WELL_DRIVER,
5662 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5663
fa42e23c
PZ		 5664 if (!is_enabled) {
5665 DRM_DEBUG_KMS("Enabling power well\n");
5666 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5667 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5668 DRM_ERROR("Timeout enabling power well\n");
5669 }
596cc11e
BW		 5670
5671 if (IS_BROADWELL(dev)) {
5672 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5673 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5674 dev_priv->de_irq_mask[PIPE_B]);
5675 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5676 ~dev_priv->de_irq_mask[PIPE_B] |
5677 GEN8_PIPE_VBLANK);
5678 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5679 dev_priv->de_irq_mask[PIPE_C]);
5680 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5681 ~dev_priv->de_irq_mask[PIPE_C] |
5682 GEN8_PIPE_VBLANK);
5683 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5684 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5685 }
fa42e23c
PZ		 5686 } else {
5687 if (enable_requested) {
9dbd8feb
PZ		 5688 enum pipe p;
5689
fa42e23c 5690 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5691 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5692 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5693
5694 /*
5695 * After this, the registers on the pipes that are part
5696 * of the power well will become zero, so we have to
5697 * adjust our counters according to that.
5698 *
5699 * FIXME: Should we do this in general in
5700 * drm_vblank_post_modeset?
5701 */
5702 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5703 for_each_pipe(p)
5704 if (p != PIPE_A)
5380e929 5705 dev->vblank[p].last = 0;
9dbd8feb 5706 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5707 }
5708 }
fa42e23c 5709}
d0d3e513 5710
b4ed4484
ID		 5711static void __intel_power_well_get(struct drm_device *dev,
5712 struct i915_power_well *power_well)
2d66aef5
VS		 5713{
5714 if (!power_well->count++)
b4ed4484 5715 __intel_set_power_well(dev, true);
2d66aef5
VS		 5716}
5717
b4ed4484
ID		 5718static void __intel_power_well_put(struct drm_device *dev,
5719 struct i915_power_well *power_well)
2d66aef5
VS		 5720{
5721 WARN_ON(!power_well->count);
1ad577ac 5722 if (!--power_well->count && i915_disable_power_well)
b4ed4484 5723 __intel_set_power_well(dev, false);
2d66aef5
VS		 5724}
5725
6765625e
VS		 5726void intel_display_power_get(struct drm_device *dev,
5727 enum intel_display_power_domain domain)
5728{
5729 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5730 struct i915_power_domains *power_domains;
6765625e
VS		 5731
5732 if (!HAS_POWER_WELL(dev))
5733 return;
5734
bddc7645 5735 if (is_always_on_power_domain(dev, domain))
6765625e 5736 return;
bddc7645 5737
83c00f55
ID		 5738 power_domains = &dev_priv->power_domains;
5739
5740 mutex_lock(&power_domains->lock);
b4ed4484 5741 __intel_power_well_get(dev, &power_domains->power_wells[0]);
83c00f55 5742 mutex_unlock(&power_domains->lock);
6765625e
VS		 5743}
5744
5745void intel_display_power_put(struct drm_device *dev,
5746 enum intel_display_power_domain domain)
5747{
5748 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5749 struct i915_power_domains *power_domains;
6765625e
VS		 5750
5751 if (!HAS_POWER_WELL(dev))
5752 return;
5753
bddc7645 5754 if (is_always_on_power_domain(dev, domain))
6765625e 5755 return;
bddc7645 5756
83c00f55
ID		 5757 power_domains = &dev_priv->power_domains;
5758
5759 mutex_lock(&power_domains->lock);
b4ed4484 5760 __intel_power_well_put(dev, &power_domains->power_wells[0]);
83c00f55 5761 mutex_unlock(&power_domains->lock);
6765625e
VS		 5762}
5763
83c00f55 5764static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5765
5766/* Display audio driver power well request */
5767void i915_request_power_well(void)
5768{
b4ed4484
ID		 5769 struct drm_i915_private *dev_priv;
5770
a38911a3
WX		 5771 if (WARN_ON(!hsw_pwr))
5772 return;
5773
b4ed4484
ID		 5774 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5775 power_domains);
5776
959cbc1b 5777 mutex_lock(&hsw_pwr->lock);
b4ed4484 5778 __intel_power_well_get(dev_priv->dev, &hsw_pwr->power_wells[0]);
959cbc1b 5779 mutex_unlock(&hsw_pwr->lock);
a38911a3
WX		 5780}
5781EXPORT_SYMBOL_GPL(i915_request_power_well);
5782
5783/* Display audio driver power well release */
5784void i915_release_power_well(void)
5785{
b4ed4484
ID		 5786 struct drm_i915_private *dev_priv;
5787
a38911a3
WX		 5788 if (WARN_ON(!hsw_pwr))
5789 return;
5790
b4ed4484
ID		 5791 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5792 power_domains);
5793
959cbc1b 5794 mutex_lock(&hsw_pwr->lock);
b4ed4484 5795 __intel_power_well_put(dev_priv->dev, &hsw_pwr->power_wells[0]);
959cbc1b 5796 mutex_unlock(&hsw_pwr->lock);
a38911a3
WX		 5797}
5798EXPORT_SYMBOL_GPL(i915_release_power_well);
5799
ddb642fb 5800int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5801{
5802 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5803 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5804 struct i915_power_well *power_well;
a38911a3 5805
83c00f55
ID		 5806 mutex_init(&power_domains->lock);
5807 hsw_pwr = power_domains;
a38911a3 5808
83c00f55 5809 power_well = &power_domains->power_wells[0];
83c00f55 5810 power_well->count = 0;
a38911a3
WX		 5811
5812 return 0;
5813}
5814
ddb642fb 5815void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5816{
5817 hsw_pwr = NULL;
5818}
5819
ddb642fb 5820static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5821{
5822 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5823 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5824 struct i915_power_well *power_well;
9cdb826c
VS		 5825
5826 if (!HAS_POWER_WELL(dev))
5827 return;
5828
83c00f55
ID		 5829 mutex_lock(&power_domains->lock);
5830
5831 power_well = &power_domains->power_wells[0];
9cdb826c 5832 __intel_set_power_well(dev, power_well->count > 0);
83c00f55
ID		 5833
5834 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5835}
5836
fa42e23c
PZ		 5837/*
5838 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5839 * when not needed anymore. We have 4 registers that can request the power well
5840 * to be enabled, and it will only be disabled if none of the registers is
5841 * requesting it to be enabled.
d0d3e513 5842 */
ddb642fb 5843void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5844{
5845 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5846
86d52df6 5847 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5848 return;
5849
fa42e23c 5850 /* For now, we need the power well to be always enabled. */
baa70707 5851 intel_display_set_init_power(dev, true);
ddb642fb 5852 intel_power_domains_resume(dev);
d0d3e513 5853
fa42e23c
PZ		 5854 /* We're taking over the BIOS, so clear any requests made by it since
5855 * the driver is in charge now. */
6aedd1f5 5856 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5857 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5858}
5859
c67a470b
PZ		 5860/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5861void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5862{
5863 hsw_disable_package_c8(dev_priv);
5864}
5865
5866void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5867{
5868 hsw_enable_package_c8(dev_priv);
5869}
5870
1fa61106
ED		 5871/* Set up chip specific power management-related functions */
5872void intel_init_pm(struct drm_device *dev)
5873{
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875
5876 if (I915_HAS_FBC(dev)) {
5877 if (HAS_PCH_SPLIT(dev)) {
5878 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5879 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5880 dev_priv->display.enable_fbc =
5881 gen7_enable_fbc;
5882 else
5883 dev_priv->display.enable_fbc =
5884 ironlake_enable_fbc;
1fa61106
ED		 5885 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5886 } else if (IS_GM45(dev)) {
5887 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5888 dev_priv->display.enable_fbc = g4x_enable_fbc;
5889 dev_priv->display.disable_fbc = g4x_disable_fbc;
5890 } else if (IS_CRESTLINE(dev)) {
5891 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5892 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5893 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5894 }
5895 /* 855GM needs testing */
5896 }
5897
c921aba8
DV		 5898 /* For cxsr */
5899 if (IS_PINEVIEW(dev))
5900 i915_pineview_get_mem_freq(dev);
5901 else if (IS_GEN5(dev))
5902 i915_ironlake_get_mem_freq(dev);
5903
1fa61106
ED		 5904 /* For FIFO watermark updates */
5905 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5906 intel_setup_wm_latency(dev);
5907
1fa61106 5908 if (IS_GEN5(dev)) {
53615a5e
VS		 5909 if (dev_priv->wm.pri_latency[1] &&
5910 dev_priv->wm.spr_latency[1] &&
5911 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5912 dev_priv->display.update_wm = ironlake_update_wm;
5913 else {
5914 DRM_DEBUG_KMS("Failed to get proper latency. "
5915 "Disable CxSR\n");
5916 dev_priv->display.update_wm = NULL;
5917 }
5918 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5919 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5920 if (dev_priv->wm.pri_latency[0] &&
5921 dev_priv->wm.spr_latency[0] &&
5922 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5923 dev_priv->display.update_wm = sandybridge_update_wm;
5924 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5925 } else {
5926 DRM_DEBUG_KMS("Failed to read display plane latency. "
5927 "Disable CxSR\n");
5928 dev_priv->display.update_wm = NULL;
5929 }
5930 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5931 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5932 if (dev_priv->wm.pri_latency[0] &&
5933 dev_priv->wm.spr_latency[0] &&
5934 dev_priv->wm.cur_latency[0]) {
c43d0188 5935 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5936 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5937 } else {
5938 DRM_DEBUG_KMS("Failed to read display plane latency. "
5939 "Disable CxSR\n");
5940 dev_priv->display.update_wm = NULL;
5941 }
5942 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5943 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5944 if (dev_priv->wm.pri_latency[0] &&
5945 dev_priv->wm.spr_latency[0] &&
5946 dev_priv->wm.cur_latency[0]) {
1011d8c4 5947 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5948 dev_priv->display.update_sprite_wm =
5949 haswell_update_sprite_wm;
6b8a5eeb
ED		 5950 } else {
5951 DRM_DEBUG_KMS("Failed to read display plane latency. "
5952 "Disable CxSR\n");
5953 dev_priv->display.update_wm = NULL;
5954 }
cad2a2d7 5955 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1020a5c2
BW		 5956 } else if (INTEL_INFO(dev)->gen == 8) {
5957 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 5958 } else
5959 dev_priv->display.update_wm = NULL;
5960 } else if (IS_VALLEYVIEW(dev)) {
5961 dev_priv->display.update_wm = valleyview_update_wm;
5962 dev_priv->display.init_clock_gating =
5963 valleyview_init_clock_gating;
1fa61106
ED		 5964 } else if (IS_PINEVIEW(dev)) {
5965 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5966 dev_priv->is_ddr3,
5967 dev_priv->fsb_freq,
5968 dev_priv->mem_freq)) {
5969 DRM_INFO("failed to find known CxSR latency "
5970 "(found ddr%s fsb freq %d, mem freq %d), "
5971 "disabling CxSR\n",
5972 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5973 dev_priv->fsb_freq, dev_priv->mem_freq);
5974 /* Disable CxSR and never update its watermark again */
5975 pineview_disable_cxsr(dev);
5976 dev_priv->display.update_wm = NULL;
5977 } else
5978 dev_priv->display.update_wm = pineview_update_wm;
5979 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5980 } else if (IS_G4X(dev)) {
5981 dev_priv->display.update_wm = g4x_update_wm;
5982 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5983 } else if (IS_GEN4(dev)) {
5984 dev_priv->display.update_wm = i965_update_wm;
5985 if (IS_CRESTLINE(dev))
5986 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5987 else if (IS_BROADWATER(dev))
5988 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5989 } else if (IS_GEN3(dev)) {
5990 dev_priv->display.update_wm = i9xx_update_wm;
5991 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5992 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5993 } else if (IS_I865G(dev)) {
5994 dev_priv->display.update_wm = i830_update_wm;
5995 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5996 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5997 } else if (IS_I85X(dev)) {
5998 dev_priv->display.update_wm = i9xx_update_wm;
5999 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6000 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6001 } else {
6002 dev_priv->display.update_wm = i830_update_wm;
6003 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6004 if (IS_845G(dev))
6005 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6006 else
6007 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6008 }
6009}
6010
42c0526c
BW		 6011int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6012{
4fc688ce 6013 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6014
6015 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6016 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6017 return -EAGAIN;
6018 }
6019
6020 I915_WRITE(GEN6_PCODE_DATA, *val);
6021 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6022
6023 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6024 500)) {
6025 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6026 return -ETIMEDOUT;
6027 }
6028
6029 *val = I915_READ(GEN6_PCODE_DATA);
6030 I915_WRITE(GEN6_PCODE_DATA, 0);
6031
6032 return 0;
6033}
6034
6035int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6036{
4fc688ce 6037 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6038
6039 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6040 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6041 return -EAGAIN;
6042 }
6043
6044 I915_WRITE(GEN6_PCODE_DATA, val);
6045 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6046
6047 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6048 500)) {
6049 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6050 return -ETIMEDOUT;
6051 }
6052
6053 I915_WRITE(GEN6_PCODE_DATA, 0);
6054
6055 return 0;
6056}
a0e4e199 6057
2ec3815f 6058int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6059{
07ab118b 6060 int div;
855ba3be 6061
07ab118b 6062 /* 4 x czclk */
2ec3815f 6063 switch (dev_priv->mem_freq) {
855ba3be 6064 case 800:
07ab118b 6065 div = 10;
855ba3be
JB		 6066 break;
6067 case 1066:
07ab118b 6068 div = 12;
855ba3be
JB		 6069 break;
6070 case 1333:
07ab118b 6071 div = 16;
855ba3be
JB		 6072 break;
6073 default:
6074 return -1;
6075 }
6076
2ec3815f 6077 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6078}
6079
2ec3815f 6080int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6081{
07ab118b 6082 int mul;
855ba3be 6083
07ab118b 6084 /* 4 x czclk */
2ec3815f 6085 switch (dev_priv->mem_freq) {
855ba3be 6086 case 800:
07ab118b 6087 mul = 10;
855ba3be
JB		 6088 break;
6089 case 1066:
07ab118b 6090 mul = 12;
855ba3be
JB		 6091 break;
6092 case 1333:
07ab118b 6093 mul = 16;
855ba3be
JB		 6094 break;
6095 default:
6096 return -1;
6097 }
6098
2ec3815f 6099 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6100}
6101
907b28c5
CW		 6102void intel_pm_init(struct drm_device *dev)
6103{
6104 struct drm_i915_private *dev_priv = dev->dev_private;
6105
6106 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6107 intel_gen6_powersave_work);
6108}
Linux kernel - Deliverables
This page took 0.596054 seconds and 5 git commands to generate.