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drm/i915: Sanity check DP AUX message buffer and size
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 491 .fifo_size = VALLEYVIEW_FIFO_SIZE,
492 .max_wm = VALLEYVIEW_MAX_WM,
493 .default_wm = VALLEYVIEW_MAX_WM,
494 .guard_size = 2,
495 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 498 .fifo_size = I965_CURSOR_FIFO,
499 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
500 .default_wm = I965_CURSOR_DFT_WM,
501 .guard_size = 2,
502 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 505 .fifo_size = I965_CURSOR_FIFO,
506 .max_wm = I965_CURSOR_MAX_WM,
507 .default_wm = I965_CURSOR_DFT_WM,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 512 .fifo_size = I945_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 519 .fifo_size = I915_FIFO_SIZE,
520 .max_wm = I915_MAX_WM,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 524};
9d539105 525static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 526 .fifo_size = I855GM_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 531};
9d539105
VS		 532static const struct intel_watermark_params i830_bc_wm_info = {
533 .fifo_size = I855GM_FIFO_SIZE,
534 .max_wm = I915_MAX_WM/2,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I830_FIFO_LINE_SIZE,
538};
feb56b93 539static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 540 .fifo_size = I830_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 545};
546
b445e3b0
ED		 547/**
548 * intel_calculate_wm - calculate watermark level
549 * @clock_in_khz: pixel clock
550 * @wm: chip FIFO params
ac484963 551 * @cpp: bytes per pixel
b445e3b0
ED		 552 * @latency_ns: memory latency for the platform
553 *
554 * Calculate the watermark level (the level at which the display plane will
555 * start fetching from memory again). Each chip has a different display
556 * FIFO size and allocation, so the caller needs to figure that out and pass
557 * in the correct intel_watermark_params structure.
558 *
559 * As the pixel clock runs, the FIFO will be drained at a rate that depends
560 * on the pixel size. When it reaches the watermark level, it'll start
561 * fetching FIFO line sized based chunks from memory until the FIFO fills
562 * past the watermark point. If the FIFO drains completely, a FIFO underrun
563 * will occur, and a display engine hang could result.
564 */
565static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
566 const struct intel_watermark_params *wm,
ac484963 567 int fifo_size, int cpp,
b445e3b0
ED		 568 unsigned long latency_ns)
569{
570 long entries_required, wm_size;
571
572 /*
573 * Note: we need to make sure we don't overflow for various clock &
574 * latency values.
575 * clocks go from a few thousand to several hundred thousand.
576 * latency is usually a few thousand
577 */
ac484963 578 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 579 1000;
580 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
581
582 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
583
584 wm_size = fifo_size - (entries_required + wm->guard_size);
585
586 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
587
588 /* Don't promote wm_size to unsigned... */
589 if (wm_size > (long)wm->max_wm)
590 wm_size = wm->max_wm;
591 if (wm_size <= 0)
592 wm_size = wm->default_wm;
d6feb196
VS		 593
594 /*
595 * Bspec seems to indicate that the value shouldn't be lower than
596 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
597 * Lets go for 8 which is the burst size since certain platforms
598 * already use a hardcoded 8 (which is what the spec says should be
599 * done).
600 */
601 if (wm_size <= 8)
602 wm_size = 8;
603
b445e3b0
ED		 604 return wm_size;
605}
606
607static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
608{
609 struct drm_crtc *crtc, *enabled = NULL;
610
70e1e0ec 611 for_each_crtc(dev, crtc) {
3490ea5d 612 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 613 if (enabled)
614 return NULL;
615 enabled = crtc;
616 }
617 }
618
619 return enabled;
620}
621
46ba614c 622static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 623{
46ba614c 624 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 625 struct drm_i915_private *dev_priv = dev->dev_private;
626 struct drm_crtc *crtc;
627 const struct cxsr_latency *latency;
628 u32 reg;
629 unsigned long wm;
630
631 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
632 dev_priv->fsb_freq, dev_priv->mem_freq);
633 if (!latency) {
634 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 635 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 636 return;
637 }
638
639 crtc = single_enabled_crtc(dev);
640 if (crtc) {
7c5f93b0 641 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 642 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 643 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 644
645 /* Display SR */
646 wm = intel_calculate_wm(clock, &pineview_display_wm,
647 pineview_display_wm.fifo_size,
ac484963 648 cpp, latency->display_sr);
b445e3b0
ED		 649 reg = I915_READ(DSPFW1);
650 reg &= ~DSPFW_SR_MASK;
f4998963 651 reg |= FW_WM(wm, SR);
b445e3b0
ED		 652 I915_WRITE(DSPFW1, reg);
653 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
654
655 /* cursor SR */
656 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
657 pineview_display_wm.fifo_size,
ac484963 658 cpp, latency->cursor_sr);
b445e3b0
ED		 659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 661 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 662 I915_WRITE(DSPFW3, reg);
663
664 /* Display HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
ac484963 667 cpp, latency->display_hpll_disable);
b445e3b0
ED		 668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 670 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 671 I915_WRITE(DSPFW3, reg);
672
673 /* cursor HPLL off SR */
674 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
675 pineview_display_hplloff_wm.fifo_size,
ac484963 676 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 677 reg = I915_READ(DSPFW3);
678 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 679 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 680 I915_WRITE(DSPFW3, reg);
681 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
682
5209b1f4 683 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 684 } else {
5209b1f4 685 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 686 }
687}
688
689static bool g4x_compute_wm0(struct drm_device *dev,
690 int plane,
691 const struct intel_watermark_params *display,
692 int display_latency_ns,
693 const struct intel_watermark_params *cursor,
694 int cursor_latency_ns,
695 int *plane_wm,
696 int *cursor_wm)
697{
698 struct drm_crtc *crtc;
4fe8590a 699 const struct drm_display_mode *adjusted_mode;
ac484963 700 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 701 int line_time_us, line_count;
702 int entries, tlb_miss;
703
704 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 705 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 706 *cursor_wm = cursor->guard_size;
707 *plane_wm = display->guard_size;
708 return false;
709 }
710
6e3c9717 711 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 712 clock = adjusted_mode->crtc_clock;
fec8cba3 713 htotal = adjusted_mode->crtc_htotal;
6e3c9717 714 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 715 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 716
717 /* Use the small buffer method to calculate plane watermark */
ac484963 718 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 719 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
720 if (tlb_miss > 0)
721 entries += tlb_miss;
722 entries = DIV_ROUND_UP(entries, display->cacheline_size);
723 *plane_wm = entries + display->guard_size;
724 if (*plane_wm > (int)display->max_wm)
725 *plane_wm = display->max_wm;
726
727 /* Use the large buffer method to calculate cursor watermark */
922044c9 728 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 729 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 730 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 731 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
732 if (tlb_miss > 0)
733 entries += tlb_miss;
734 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
735 *cursor_wm = entries + cursor->guard_size;
736 if (*cursor_wm > (int)cursor->max_wm)
737 *cursor_wm = (int)cursor->max_wm;
738
739 return true;
740}
741
742/*
743 * Check the wm result.
744 *
745 * If any calculated watermark values is larger than the maximum value that
746 * can be programmed into the associated watermark register, that watermark
747 * must be disabled.
748 */
749static bool g4x_check_srwm(struct drm_device *dev,
750 int display_wm, int cursor_wm,
751 const struct intel_watermark_params *display,
752 const struct intel_watermark_params *cursor)
753{
754 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
755 display_wm, cursor_wm);
756
757 if (display_wm > display->max_wm) {
758 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
759 display_wm, display->max_wm);
760 return false;
761 }
762
763 if (cursor_wm > cursor->max_wm) {
764 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
765 cursor_wm, cursor->max_wm);
766 return false;
767 }
768
769 if (!(display_wm || cursor_wm)) {
770 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
771 return false;
772 }
773
774 return true;
775}
776
777static bool g4x_compute_srwm(struct drm_device *dev,
778 int plane,
779 int latency_ns,
780 const struct intel_watermark_params *display,
781 const struct intel_watermark_params *cursor,
782 int *display_wm, int *cursor_wm)
783{
784 struct drm_crtc *crtc;
4fe8590a 785 const struct drm_display_mode *adjusted_mode;
ac484963 786 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 787 unsigned long line_time_us;
788 int line_count, line_size;
789 int small, large;
790 int entries;
791
792 if (!latency_ns) {
793 *display_wm = *cursor_wm = 0;
794 return false;
795 }
796
797 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 798 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 799 clock = adjusted_mode->crtc_clock;
fec8cba3 800 htotal = adjusted_mode->crtc_htotal;
6e3c9717 801 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 802 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 803
922044c9 804 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 805 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 806 line_size = hdisplay * cpp;
b445e3b0
ED		 807
808 /* Use the minimum of the small and large buffer method for primary */
ac484963 809 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 810 large = line_count * line_size;
811
812 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
813 *display_wm = entries + display->guard_size;
814
815 /* calculate the self-refresh watermark for display cursor */
ac484963 816 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 817 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
818 *cursor_wm = entries + cursor->guard_size;
819
820 return g4x_check_srwm(dev,
821 *display_wm, *cursor_wm,
822 display, cursor);
823}
824
15665979
VS		 825#define FW_WM_VLV(value, plane) \
826 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
827
0018fda1
VS		 828static void vlv_write_wm_values(struct intel_crtc *crtc,
829 const struct vlv_wm_values *wm)
830{
831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
832 enum pipe pipe = crtc->pipe;
833
834 I915_WRITE(VLV_DDL(pipe),
835 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
836 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
837 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
838 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
839
ae80152d 840 I915_WRITE(DSPFW1,
15665979
VS		 841 FW_WM(wm->sr.plane, SR) |
842 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
843 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
844 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 845 I915_WRITE(DSPFW2,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
847 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
848 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 849 I915_WRITE(DSPFW3,
15665979 850 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 851
852 if (IS_CHERRYVIEW(dev_priv)) {
853 I915_WRITE(DSPFW7_CHV,
15665979
VS		 854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
855 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 856 I915_WRITE(DSPFW8_CHV,
15665979
VS		 857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
858 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 859 I915_WRITE(DSPFW9_CHV,
15665979
VS		 860 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
861 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 862 I915_WRITE(DSPHOWM,
15665979
VS		 863 FW_WM(wm->sr.plane >> 9, SR_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
865 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
866 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
868 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
869 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
871 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
872 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 873 } else {
874 I915_WRITE(DSPFW7,
15665979
VS		 875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 877 I915_WRITE(DSPHOWM,
15665979
VS		 878 FW_WM(wm->sr.plane >> 9, SR_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
880 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
881 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
883 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
884 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 885 }
886
2cb389b7
VS		 887 /* zero (unused) WM1 watermarks */
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891 I915_WRITE(DSPHOWM1, 0);
892
ae80152d 893 POSTING_READ(DSPFW1);
0018fda1
VS		 894}
895
15665979
VS		 896#undef FW_WM_VLV
897
6eb1a681
VS		 898enum vlv_wm_level {
899 VLV_WM_LEVEL_PM2,
900 VLV_WM_LEVEL_PM5,
901 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 902};
903
262cd2e1
VS		 904/* latency must be in 0.1us units. */
905static unsigned int vlv_wm_method2(unsigned int pixel_rate,
906 unsigned int pipe_htotal,
907 unsigned int horiz_pixels,
ac484963 908 unsigned int cpp,
262cd2e1
VS		 909 unsigned int latency)
910{
911 unsigned int ret;
912
913 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 914 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 915 ret = DIV_ROUND_UP(ret, 64);
916
917 return ret;
918}
919
920static void vlv_setup_wm_latency(struct drm_device *dev)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923
924 /* all latencies in usec */
925 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
926
58590c14
VS		 927 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
928
262cd2e1
VS		 929 if (IS_CHERRYVIEW(dev_priv)) {
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
931 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 932
933 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 934 }
935}
936
937static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
938 struct intel_crtc *crtc,
939 const struct intel_plane_state *state,
940 int level)
941{
942 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 943 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 944
945 if (dev_priv->wm.pri_latency[level] == 0)
946 return USHRT_MAX;
947
948 if (!state->visible)
949 return 0;
950
ac484963 951 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 952 clock = crtc->config->base.adjusted_mode.crtc_clock;
953 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
954 width = crtc->config->pipe_src_w;
955 if (WARN_ON(htotal == 0))
956 htotal = 1;
957
958 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
959 /*
960 * FIXME the formula gives values that are
961 * too big for the cursor FIFO, and hence we
962 * would never be able to use cursors. For
963 * now just hardcode the watermark.
964 */
965 wm = 63;
966 } else {
ac484963 967 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 968 dev_priv->wm.pri_latency[level] * 10);
969 }
970
971 return min_t(int, wm, USHRT_MAX);
972}
973
54f1b6e1
VS		 974static void vlv_compute_fifo(struct intel_crtc *crtc)
975{
976 struct drm_device *dev = crtc->base.dev;
977 struct vlv_wm_state *wm_state = &crtc->wm_state;
978 struct intel_plane *plane;
979 unsigned int total_rate = 0;
980 const int fifo_size = 512 - 1;
981 int fifo_extra, fifo_left = fifo_size;
982
983 for_each_intel_plane_on_crtc(dev, crtc, plane) {
984 struct intel_plane_state *state =
985 to_intel_plane_state(plane->base.state);
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
988 continue;
989
990 if (state->visible) {
991 wm_state->num_active_planes++;
992 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 }
994 }
995
996 for_each_intel_plane_on_crtc(dev, crtc, plane) {
997 struct intel_plane_state *state =
998 to_intel_plane_state(plane->base.state);
999 unsigned int rate;
1000
1001 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1002 plane->wm.fifo_size = 63;
1003 continue;
1004 }
1005
1006 if (!state->visible) {
1007 plane->wm.fifo_size = 0;
1008 continue;
1009 }
1010
1011 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1012 plane->wm.fifo_size = fifo_size * rate / total_rate;
1013 fifo_left -= plane->wm.fifo_size;
1014 }
1015
1016 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1017
1018 /* spread the remainder evenly */
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 int plane_extra;
1021
1022 if (fifo_left == 0)
1023 break;
1024
1025 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1026 continue;
1027
1028 /* give it all to the first plane if none are active */
1029 if (plane->wm.fifo_size == 0 &&
1030 wm_state->num_active_planes)
1031 continue;
1032
1033 plane_extra = min(fifo_extra, fifo_left);
1034 plane->wm.fifo_size += plane_extra;
1035 fifo_left -= plane_extra;
1036 }
1037
1038 WARN_ON(fifo_left != 0);
1039}
1040
262cd2e1
VS		 1041static void vlv_invert_wms(struct intel_crtc *crtc)
1042{
1043 struct vlv_wm_state *wm_state = &crtc->wm_state;
1044 int level;
1045
1046 for (level = 0; level < wm_state->num_levels; level++) {
1047 struct drm_device *dev = crtc->base.dev;
1048 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1049 struct intel_plane *plane;
1050
1051 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1052 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 switch (plane->base.type) {
1056 int sprite;
1057 case DRM_PLANE_TYPE_CURSOR:
1058 wm_state->wm[level].cursor = plane->wm.fifo_size -
1059 wm_state->wm[level].cursor;
1060 break;
1061 case DRM_PLANE_TYPE_PRIMARY:
1062 wm_state->wm[level].primary = plane->wm.fifo_size -
1063 wm_state->wm[level].primary;
1064 break;
1065 case DRM_PLANE_TYPE_OVERLAY:
1066 sprite = plane->plane;
1067 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1068 wm_state->wm[level].sprite[sprite];
1069 break;
1070 }
1071 }
1072 }
1073}
1074
26e1fe4f 1075static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1076{
1077 struct drm_device *dev = crtc->base.dev;
1078 struct vlv_wm_state *wm_state = &crtc->wm_state;
1079 struct intel_plane *plane;
1080 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1081 int level;
1082
1083 memset(wm_state, 0, sizeof(*wm_state));
1084
852eb00d 1085 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1086 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1087
1088 wm_state->num_active_planes = 0;
262cd2e1 1089
54f1b6e1 1090 vlv_compute_fifo(crtc);
262cd2e1
VS		 1091
1092 if (wm_state->num_active_planes != 1)
1093 wm_state->cxsr = false;
1094
1095 if (wm_state->cxsr) {
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 wm_state->sr[level].plane = sr_fifo_size;
1098 wm_state->sr[level].cursor = 63;
1099 }
1100 }
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 struct intel_plane_state *state =
1104 to_intel_plane_state(plane->base.state);
1105
1106 if (!state->visible)
1107 continue;
1108
1109 /* normal watermarks */
1110 for (level = 0; level < wm_state->num_levels; level++) {
1111 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1112 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1113
1114 /* hack */
1115 if (WARN_ON(level == 0 && wm > max_wm))
1116 wm = max_wm;
1117
1118 if (wm > plane->wm.fifo_size)
1119 break;
1120
1121 switch (plane->base.type) {
1122 int sprite;
1123 case DRM_PLANE_TYPE_CURSOR:
1124 wm_state->wm[level].cursor = wm;
1125 break;
1126 case DRM_PLANE_TYPE_PRIMARY:
1127 wm_state->wm[level].primary = wm;
1128 break;
1129 case DRM_PLANE_TYPE_OVERLAY:
1130 sprite = plane->plane;
1131 wm_state->wm[level].sprite[sprite] = wm;
1132 break;
1133 }
1134 }
1135
1136 wm_state->num_levels = level;
1137
1138 if (!wm_state->cxsr)
1139 continue;
1140
1141 /* maxfifo watermarks */
1142 switch (plane->base.type) {
1143 int sprite, level;
1144 case DRM_PLANE_TYPE_CURSOR:
1145 for (level = 0; level < wm_state->num_levels; level++)
1146 wm_state->sr[level].cursor =
5a37ed0a 1147 wm_state->wm[level].cursor;
262cd2e1
VS		 1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 for (level = 0; level < wm_state->num_levels; level++)
1151 wm_state->sr[level].plane =
1152 min(wm_state->sr[level].plane,
1153 wm_state->wm[level].primary);
1154 break;
1155 case DRM_PLANE_TYPE_OVERLAY:
1156 sprite = plane->plane;
1157 for (level = 0; level < wm_state->num_levels; level++)
1158 wm_state->sr[level].plane =
1159 min(wm_state->sr[level].plane,
1160 wm_state->wm[level].sprite[sprite]);
1161 break;
1162 }
1163 }
1164
1165 /* clear any (partially) filled invalid levels */
58590c14 1166 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1167 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1168 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1169 }
1170
1171 vlv_invert_wms(crtc);
1172}
1173
54f1b6e1
VS		 1174#define VLV_FIFO(plane, value) \
1175 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176
1177static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1178{
1179 struct drm_device *dev = crtc->base.dev;
1180 struct drm_i915_private *dev_priv = to_i915(dev);
1181 struct intel_plane *plane;
1182 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1183
1184 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1185 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1186 WARN_ON(plane->wm.fifo_size != 63);
1187 continue;
1188 }
1189
1190 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1191 sprite0_start = plane->wm.fifo_size;
1192 else if (plane->plane == 0)
1193 sprite1_start = sprite0_start + plane->wm.fifo_size;
1194 else
1195 fifo_size = sprite1_start + plane->wm.fifo_size;
1196 }
1197
1198 WARN_ON(fifo_size != 512 - 1);
1199
1200 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1201 pipe_name(crtc->pipe), sprite0_start,
1202 sprite1_start, fifo_size);
1203
1204 switch (crtc->pipe) {
1205 uint32_t dsparb, dsparb2, dsparb3;
1206 case PIPE_A:
1207 dsparb = I915_READ(DSPARB);
1208 dsparb2 = I915_READ(DSPARB2);
1209
1210 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1211 VLV_FIFO(SPRITEB, 0xff));
1212 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1213 VLV_FIFO(SPRITEB, sprite1_start));
1214
1215 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1216 VLV_FIFO(SPRITEB_HI, 0x1));
1217 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1218 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1219
1220 I915_WRITE(DSPARB, dsparb);
1221 I915_WRITE(DSPARB2, dsparb2);
1222 break;
1223 case PIPE_B:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1228 VLV_FIFO(SPRITED, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1230 VLV_FIFO(SPRITED, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1233 VLV_FIFO(SPRITED_HI, 0xff));
1234 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_C:
1241 dsparb3 = I915_READ(DSPARB3);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1245 VLV_FIFO(SPRITEF, 0xff));
1246 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1247 VLV_FIFO(SPRITEF, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1250 VLV_FIFO(SPRITEF_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB3, dsparb3);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 default:
1258 break;
1259 }
1260}
1261
1262#undef VLV_FIFO
1263
262cd2e1
VS		 1264static void vlv_merge_wm(struct drm_device *dev,
1265 struct vlv_wm_values *wm)
1266{
1267 struct intel_crtc *crtc;
1268 int num_active_crtcs = 0;
1269
58590c14 1270 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1271 wm->cxsr = true;
1272
1273 for_each_intel_crtc(dev, crtc) {
1274 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1275
1276 if (!crtc->active)
1277 continue;
1278
1279 if (!wm_state->cxsr)
1280 wm->cxsr = false;
1281
1282 num_active_crtcs++;
1283 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1284 }
1285
1286 if (num_active_crtcs != 1)
1287 wm->cxsr = false;
1288
6f9c784b
VS		 1289 if (num_active_crtcs > 1)
1290 wm->level = VLV_WM_LEVEL_PM2;
1291
262cd2e1
VS		 1292 for_each_intel_crtc(dev, crtc) {
1293 struct vlv_wm_state *wm_state = &crtc->wm_state;
1294 enum pipe pipe = crtc->pipe;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 wm->pipe[pipe] = wm_state->wm[wm->level];
1300 if (wm->cxsr)
1301 wm->sr = wm_state->sr[wm->level];
1302
1303 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1306 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1307 }
1308}
1309
1310static void vlv_update_wm(struct drm_crtc *crtc)
1311{
1312 struct drm_device *dev = crtc->dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315 enum pipe pipe = intel_crtc->pipe;
1316 struct vlv_wm_values wm = {};
1317
26e1fe4f 1318 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1319 vlv_merge_wm(dev, &wm);
1320
54f1b6e1
VS		 1321 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1322 /* FIXME should be part of crtc atomic commit */
1323 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1324 return;
54f1b6e1 1325 }
262cd2e1
VS		 1326
1327 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1328 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1329 chv_set_memory_dvfs(dev_priv, false);
1330
1331 if (wm.level < VLV_WM_LEVEL_PM5 &&
1332 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1333 chv_set_memory_pm5(dev_priv, false);
1334
852eb00d 1335 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1337
54f1b6e1
VS		 1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(intel_crtc);
1340
262cd2e1
VS		 1341 vlv_write_wm_values(intel_crtc, &wm);
1342
1343 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1344 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1345 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1346 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1347 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1348
852eb00d 1349 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1350 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1351
1352 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1353 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1354 chv_set_memory_pm5(dev_priv, true);
1355
1356 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1357 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1358 chv_set_memory_dvfs(dev_priv, true);
1359
1360 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1361}
1362
ae80152d
VS		 1363#define single_plane_enabled(mask) is_power_of_2(mask)
1364
46ba614c 1365static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1366{
46ba614c 1367 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1368 static const int sr_latency_ns = 12000;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371 int plane_sr, cursor_sr;
1372 unsigned int enabled = 0;
9858425c 1373 bool cxsr_enabled;
b445e3b0 1374
51cea1f4 1375 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1376 &g4x_wm_info, pessimal_latency_ns,
1377 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1378 &planea_wm, &cursora_wm))
51cea1f4 1379 enabled |= 1 << PIPE_A;
b445e3b0 1380
51cea1f4 1381 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1382 &g4x_wm_info, pessimal_latency_ns,
1383 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1384 &planeb_wm, &cursorb_wm))
51cea1f4 1385 enabled |= 1 << PIPE_B;
b445e3b0 1386
b445e3b0
ED		 1387 if (single_plane_enabled(enabled) &&
1388 g4x_compute_srwm(dev, ffs(enabled) - 1,
1389 sr_latency_ns,
1390 &g4x_wm_info,
1391 &g4x_cursor_wm_info,
52bd02d8 1392 &plane_sr, &cursor_sr)) {
9858425c 1393 cxsr_enabled = true;
52bd02d8 1394 } else {
9858425c 1395 cxsr_enabled = false;
5209b1f4 1396 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1397 plane_sr = cursor_sr = 0;
1398 }
b445e3b0 1399
a5043453
VS		 1400 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1401 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1402 planea_wm, cursora_wm,
1403 planeb_wm, cursorb_wm,
1404 plane_sr, cursor_sr);
1405
1406 I915_WRITE(DSPFW1,
f4998963
VS		 1407 FW_WM(plane_sr, SR) |
1408 FW_WM(cursorb_wm, CURSORB) |
1409 FW_WM(planeb_wm, PLANEB) |
1410 FW_WM(planea_wm, PLANEA));
b445e3b0 1411 I915_WRITE(DSPFW2,
8c919b28 1412 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1413 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1414 /* HPLL off in SR has some issues on G4x... disable it */
1415 I915_WRITE(DSPFW3,
8c919b28 1416 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1417 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1418
1419 if (cxsr_enabled)
1420 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1421}
1422
46ba614c 1423static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1424{
46ba614c 1425 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct drm_crtc *crtc;
1428 int srwm = 1;
1429 int cursor_sr = 16;
9858425c 1430 bool cxsr_enabled;
b445e3b0
ED		 1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
124abe07 1437 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1438 int clock = adjusted_mode->crtc_clock;
fec8cba3 1439 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1440 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1441 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1442 unsigned long line_time_us;
1443 int entries;
1444
922044c9 1445 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1446
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1449 cpp * hdisplay;
b445e3b0
ED		 1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1452 if (srwm < 0)
1453 srwm = 1;
1454 srwm &= 0x1ff;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456 entries, srwm);
1457
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1459 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1464
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1470
9858425c 1471 cxsr_enabled = true;
b445e3b0 1472 } else {
9858425c 1473 cxsr_enabled = false;
b445e3b0 1474 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1475 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
f4998963
VS		 1482 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1483 FW_WM(8, CURSORB) |
1484 FW_WM(8, PLANEB) |
1485 FW_WM(8, PLANEA));
1486 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1487 FW_WM(8, PLANEC_OLD));
b445e3b0 1488 /* update cursor SR watermark */
f4998963 1489 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1493}
1494
f4998963
VS		 1495#undef FW_WM
1496
46ba614c 1497static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1498{
46ba614c 1499 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 const struct intel_watermark_params *wm_info;
1502 uint32_t fwater_lo;
1503 uint32_t fwater_hi;
1504 int cwm, srwm = 1;
1505 int fifo_size;
1506 int planea_wm, planeb_wm;
1507 struct drm_crtc *crtc, *enabled = NULL;
1508
1509 if (IS_I945GM(dev))
1510 wm_info = &i945_wm_info;
1511 else if (!IS_GEN2(dev))
1512 wm_info = &i915_wm_info;
1513 else
9d539105 1514 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1515
1516 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1517 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1518 if (intel_crtc_active(crtc)) {
241bfc38 1519 const struct drm_display_mode *adjusted_mode;
ac484963 1520 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1521 if (IS_GEN2(dev))
1522 cpp = 4;
1523
6e3c9717 1524 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1525 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1526 wm_info, fifo_size, cpp,
5aef6003 1527 pessimal_latency_ns);
b445e3b0 1528 enabled = crtc;
9d539105 1529 } else {
b445e3b0 1530 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1531 if (planea_wm > (long)wm_info->max_wm)
1532 planea_wm = wm_info->max_wm;
1533 }
1534
1535 if (IS_GEN2(dev))
1536 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1539 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1540 if (intel_crtc_active(crtc)) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0
ED		 1550 if (enabled == NULL)
1551 enabled = crtc;
1552 else
1553 enabled = NULL;
9d539105 1554 } else {
b445e3b0 1555 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1556 if (planeb_wm > (long)wm_info->max_wm)
1557 planeb_wm = wm_info->max_wm;
1558 }
b445e3b0
ED		 1559
1560 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1561
2ab1bc9d 1562 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1563 struct drm_i915_gem_object *obj;
2ab1bc9d 1564
59bea882 1565 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1566
1567 /* self-refresh seems busted with untiled */
2ff8fde1 1568 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1569 enabled = NULL;
1570 }
1571
b445e3b0
ED		 1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1578 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1579
1580 /* Calc sr entries for one plane configs */
1581 if (HAS_FW_BLC(dev) && enabled) {
1582 /* self-refresh has much higher latency */
1583 static const int sr_latency_ns = 6000;
124abe07 1584 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1585 int clock = adjusted_mode->crtc_clock;
fec8cba3 1586 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1587 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1588 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1589 unsigned long line_time_us;
1590 int entries;
1591
922044c9 1592 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1593
1594 /* Use ns/us then divide to preserve precision */
1595 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1596 cpp * hdisplay;
b445e3b0
ED		 1597 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1598 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1599 srwm = wm_info->fifo_size - entries;
1600 if (srwm < 0)
1601 srwm = 1;
1602
1603 if (IS_I945G(dev) || IS_I945GM(dev))
1604 I915_WRITE(FW_BLC_SELF,
1605 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1606 else if (IS_I915GM(dev))
1607 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1608 }
1609
1610 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1611 planea_wm, planeb_wm, cwm, srwm);
1612
1613 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1614 fwater_hi = (cwm & 0x1f);
1615
1616 /* Set request length to 8 cachelines per fetch */
1617 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1618 fwater_hi = fwater_hi | (1 << 8);
1619
1620 I915_WRITE(FW_BLC, fwater_lo);
1621 I915_WRITE(FW_BLC2, fwater_hi);
1622
5209b1f4
ID		 1623 if (enabled)
1624 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1625}
1626
feb56b93 1627static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1628{
46ba614c 1629 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct drm_crtc *crtc;
241bfc38 1632 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1633 uint32_t fwater_lo;
1634 int planea_wm;
1635
1636 crtc = single_enabled_crtc(dev);
1637 if (crtc == NULL)
1638 return;
1639
6e3c9717 1640 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1641 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1642 &i845_wm_info,
b445e3b0 1643 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1644 4, pessimal_latency_ns);
b445e3b0
ED		 1645 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1646 fwater_lo |= (3<<8) | planea_wm;
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649
1650 I915_WRITE(FW_BLC, fwater_lo);
1651}
1652
8cfb3407 1653uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1654{
fd4daa9c 1655 uint32_t pixel_rate;
801bcfff 1656
8cfb3407 1657 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
8cfb3407 1662 if (pipe_config->pch_pfit.enabled) {
801bcfff 1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1664 uint32_t pfit_size = pipe_config->pch_pfit.size;
1665
1666 pipe_w = pipe_config->pipe_src_w;
1667 pipe_h = pipe_config->pipe_src_h;
801bcfff 1668
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
15126882
MR		 1676 if (WARN_ON(!pfit_w || !pfit_h))
1677 return pixel_rate;
1678
801bcfff
PZ		 1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680 pfit_w * pfit_h);
1681 }
1682
1683 return pixel_rate;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
ac484963 1687static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1688{
1689 uint64_t ret;
1690
3312ba65
VS		 1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
ac484963 1694 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698}
1699
37126462 1700/* latency must be in 0.1us units. */
23297044 1701static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1702 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1703 uint32_t latency)
1704{
1705 uint32_t ret;
1706
3312ba65
VS		 1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
15126882
MR		 1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
3312ba65 1711
801bcfff 1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1713 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716}
1717
23297044 1718static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1719 uint8_t cpp)
cca32e9a 1720{
15126882
MR		 1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
ac484963 1727 if (WARN_ON(!cpp))
15126882
MR		 1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
ac484963 1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1733}
1734
820c1980 1735struct ilk_wm_maximums {
cca32e9a
PZ		 1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
7221fc33 1746static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1747 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
ac484963
VS		 1751 int cpp = pstate->base.fb ?
1752 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1753 uint32_t method1, method2;
1754
7221fc33 1755 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1756 return 0;
1757
ac484963 1758 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1759
1760 if (!is_lp)
1761 return method1;
1762
7221fc33
MR		 1763 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1765 drm_rect_width(&pstate->dst),
ac484963 1766 cpp, mem_value);
cca32e9a
PZ		 1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
7221fc33 1775static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1776 const struct intel_plane_state *pstate,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
ac484963
VS		 1779 int cpp = pstate->base.fb ?
1780 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1781 uint32_t method1, method2;
1782
7221fc33 1783 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1784 return 0;
1785
ac484963 1786 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1787 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1789 drm_rect_width(&pstate->dst),
ac484963 1790 cpp, mem_value);
801bcfff
PZ		 1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1804
7221fc33 1805 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1806 return 0;
1807
7221fc33
MR		 1808 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1809 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1810 drm_rect_width(&pstate->dst),
ac484963 1811 cpp, mem_value);
801bcfff
PZ		 1812}
1813
cca32e9a 1814/* Only for WM_LP. */
7221fc33 1815static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1816 const struct intel_plane_state *pstate,
1fda9882 1817 uint32_t pri_val)
cca32e9a 1818{
ac484963
VS		 1819 int cpp = pstate->base.fb ?
1820 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1821
7221fc33 1822 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1823 return 0;
1824
ac484963 1825 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1826}
1827
158ae64f
VS		 1828static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1829{
416f4727
VS		 1830 if (INTEL_INFO(dev)->gen >= 8)
1831 return 3072;
1832 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1833 return 768;
1834 else
1835 return 512;
1836}
1837
4e975081
VS		 1838static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1839 int level, bool is_sprite)
1840{
1841 if (INTEL_INFO(dev)->gen >= 8)
1842 /* BDW primary/sprite plane watermarks */
1843 return level == 0 ? 255 : 2047;
1844 else if (INTEL_INFO(dev)->gen >= 7)
1845 /* IVB/HSW primary/sprite plane watermarks */
1846 return level == 0 ? 127 : 1023;
1847 else if (!is_sprite)
1848 /* ILK/SNB primary plane watermarks */
1849 return level == 0 ? 127 : 511;
1850 else
1851 /* ILK/SNB sprite plane watermarks */
1852 return level == 0 ? 63 : 255;
1853}
1854
1855static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1856 int level)
1857{
1858 if (INTEL_INFO(dev)->gen >= 7)
1859 return level == 0 ? 63 : 255;
1860 else
1861 return level == 0 ? 31 : 63;
1862}
1863
1864static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1865{
1866 if (INTEL_INFO(dev)->gen >= 8)
1867 return 31;
1868 else
1869 return 15;
1870}
1871
158ae64f
VS		 1872/* Calculate the maximum primary/sprite plane watermark */
1873static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1874 int level,
240264f4 1875 const struct intel_wm_config *config,
158ae64f
VS		 1876 enum intel_ddb_partitioning ddb_partitioning,
1877 bool is_sprite)
1878{
1879 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1880
1881 /* if sprites aren't enabled, sprites get nothing */
240264f4 1882 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1883 return 0;
1884
1885 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1886 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1887 fifo_size /= INTEL_INFO(dev)->num_pipes;
1888
1889 /*
1890 * For some reason the non self refresh
1891 * FIFO size is only half of the self
1892 * refresh FIFO size on ILK/SNB.
1893 */
1894 if (INTEL_INFO(dev)->gen <= 6)
1895 fifo_size /= 2;
1896 }
1897
240264f4 1898 if (config->sprites_enabled) {
158ae64f
VS		 1899 /* level 0 is always calculated with 1:1 split */
1900 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1901 if (is_sprite)
1902 fifo_size *= 5;
1903 fifo_size /= 6;
1904 } else {
1905 fifo_size /= 2;
1906 }
1907 }
1908
1909 /* clamp to max that the registers can hold */
4e975081 1910 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1911}
1912
1913/* Calculate the maximum cursor plane watermark */
1914static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1915 int level,
1916 const struct intel_wm_config *config)
158ae64f
VS		 1917{
1918 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1919 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1920 return 64;
1921
1922 /* otherwise just report max that registers can hold */
4e975081 1923 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1924}
1925
d34ff9c6 1926static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1927 int level,
1928 const struct intel_wm_config *config,
1929 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1930 struct ilk_wm_maximums *max)
158ae64f 1931{
240264f4
VS		 1932 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1933 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1934 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1935 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1936}
1937
a3cb4048
VS		 1938static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1939 int level,
1940 struct ilk_wm_maximums *max)
1941{
1942 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1943 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1944 max->cur = ilk_cursor_wm_reg_max(dev, level);
1945 max->fbc = ilk_fbc_wm_reg_max(dev);
1946}
1947
d9395655 1948static bool ilk_validate_wm_level(int level,
820c1980 1949 const struct ilk_wm_maximums *max,
d9395655 1950 struct intel_wm_level *result)
a9786a11
VS		 1951{
1952 bool ret;
1953
1954 /* already determined to be invalid? */
1955 if (!result->enable)
1956 return false;
1957
1958 result->enable = result->pri_val <= max->pri &&
1959 result->spr_val <= max->spr &&
1960 result->cur_val <= max->cur;
1961
1962 ret = result->enable;
1963
1964 /*
1965 * HACK until we can pre-compute everything,
1966 * and thus fail gracefully if LP0 watermarks
1967 * are exceeded...
1968 */
1969 if (level == 0 && !result->enable) {
1970 if (result->pri_val > max->pri)
1971 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1972 level, result->pri_val, max->pri);
1973 if (result->spr_val > max->spr)
1974 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1975 level, result->spr_val, max->spr);
1976 if (result->cur_val > max->cur)
1977 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1978 level, result->cur_val, max->cur);
1979
1980 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1981 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1982 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1983 result->enable = true;
1984 }
1985
a9786a11
VS		 1986 return ret;
1987}
1988
d34ff9c6 1989static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1990 const struct intel_crtc *intel_crtc,
6f5ddd17 1991 int level,
7221fc33 1992 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1993 struct intel_plane_state *pristate,
1994 struct intel_plane_state *sprstate,
1995 struct intel_plane_state *curstate,
1fd527cc 1996 struct intel_wm_level *result)
6f5ddd17
VS		 1997{
1998 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1999 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2000 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2001
2002 /* WM1+ latency values stored in 0.5us units */
2003 if (level > 0) {
2004 pri_latency *= 5;
2005 spr_latency *= 5;
2006 cur_latency *= 5;
2007 }
2008
86c8bbbe
MR		 2009 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2010 pri_latency, level);
2011 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2012 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2013 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 2014 result->enable = true;
2015}
2016
801bcfff 2017static uint32_t
ee91a159
MR		 2018hsw_compute_linetime_wm(struct drm_device *dev,
2019 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2020{
2021 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2022 const struct drm_display_mode *adjusted_mode =
2023 &cstate->base.adjusted_mode;
85a02deb 2024 u32 linetime, ips_linetime;
1f8eeabf 2025
ee91a159
MR		 2026 if (!cstate->base.active)
2027 return 0;
2028 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2029 return 0;
2030 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2031 return 0;
1011d8c4 2032
1f8eeabf
ED		 2033 /* The WM are computed with base on how long it takes to fill a single
2034 * row at the given clock rate, multiplied by 8.
2035 * */
124abe07
VS		 2036 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2037 adjusted_mode->crtc_clock);
2038 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2039 dev_priv->cdclk_freq);
1f8eeabf 2040
801bcfff
PZ		 2041 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2042 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2043}
2044
2af30a5c 2045static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2046{
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048
2af30a5c
PB		 2049 if (IS_GEN9(dev)) {
2050 uint32_t val;
4f947386 2051 int ret, i;
367294be 2052 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2053
2054 /* read the first set of memory latencies[0:3] */
2055 val = 0; /* data0 to be programmed to 0 for first set */
2056 mutex_lock(&dev_priv->rps.hw_lock);
2057 ret = sandybridge_pcode_read(dev_priv,
2058 GEN9_PCODE_READ_MEM_LATENCY,
2059 &val);
2060 mutex_unlock(&dev_priv->rps.hw_lock);
2061
2062 if (ret) {
2063 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2064 return;
2065 }
2066
2067 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2068 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2069 GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074
2075 /* read the second set of memory latencies[4:7] */
2076 val = 1; /* data0 to be programmed to 1 for second set */
2077 mutex_lock(&dev_priv->rps.hw_lock);
2078 ret = sandybridge_pcode_read(dev_priv,
2079 GEN9_PCODE_READ_MEM_LATENCY,
2080 &val);
2081 mutex_unlock(&dev_priv->rps.hw_lock);
2082 if (ret) {
2083 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2084 return;
2085 }
2086
2087 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2088 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2089 GEN9_MEM_LATENCY_LEVEL_MASK;
2090 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2091 GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094
367294be 2095 /*
6f97235b
DL		 2096 * WaWmMemoryReadLatency:skl
2097 *
367294be
VK		 2098 * punit doesn't take into account the read latency so we need
2099 * to add 2us to the various latency levels we retrieve from
2100 * the punit.
2101 * - W0 is a bit special in that it's the only level that
2102 * can't be disabled if we want to have display working, so
2103 * we always add 2us there.
2104 * - For levels >=1, punit returns 0us latency when they are
2105 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2106 *
2107 * Additionally, if a level n (n > 1) has a 0us latency, all
2108 * levels m (m >= n) need to be disabled. We make sure to
2109 * sanitize the values out of the punit to satisfy this
2110 * requirement.
367294be
VK		 2111 */
2112 wm[0] += 2;
2113 for (level = 1; level <= max_level; level++)
2114 if (wm[level] != 0)
2115 wm[level] += 2;
4f947386
VK		 2116 else {
2117 for (i = level + 1; i <= max_level; i++)
2118 wm[i] = 0;
367294be 2119
4f947386
VK		 2120 break;
2121 }
2af30a5c 2122 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2123 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2124
2125 wm[0] = (sskpd >> 56) & 0xFF;
2126 if (wm[0] == 0)
2127 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2128 wm[1] = (sskpd >> 4) & 0xFF;
2129 wm[2] = (sskpd >> 12) & 0xFF;
2130 wm[3] = (sskpd >> 20) & 0x1FF;
2131 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2132 } else if (INTEL_INFO(dev)->gen >= 6) {
2133 uint32_t sskpd = I915_READ(MCH_SSKPD);
2134
2135 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2136 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2137 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2138 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2139 } else if (INTEL_INFO(dev)->gen >= 5) {
2140 uint32_t mltr = I915_READ(MLTR_ILK);
2141
2142 /* ILK primary LP0 latency is 700 ns */
2143 wm[0] = 7;
2144 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2145 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2146 }
2147}
2148
53615a5e
VS		 2149static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2150{
2151 /* ILK sprite LP0 latency is 1300 ns */
2152 if (INTEL_INFO(dev)->gen == 5)
2153 wm[0] = 13;
2154}
2155
2156static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2157{
2158 /* ILK cursor LP0 latency is 1300 ns */
2159 if (INTEL_INFO(dev)->gen == 5)
2160 wm[0] = 13;
2161
2162 /* WaDoubleCursorLP3Latency:ivb */
2163 if (IS_IVYBRIDGE(dev))
2164 wm[3] *= 2;
2165}
2166
546c81fd 2167int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2168{
26ec971e 2169 /* how many WM levels are we expecting */
b6e742f6 2170 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2171 return 7;
2172 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2173 return 4;
26ec971e 2174 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2175 return 3;
26ec971e 2176 else
ad0d6dc4
VS		 2177 return 2;
2178}
7526ed79 2179
ad0d6dc4
VS		 2180static void intel_print_wm_latency(struct drm_device *dev,
2181 const char *name,
2af30a5c 2182 const uint16_t wm[8])
ad0d6dc4
VS		 2183{
2184 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2185
2186 for (level = 0; level <= max_level; level++) {
2187 unsigned int latency = wm[level];
2188
2189 if (latency == 0) {
2190 DRM_ERROR("%s WM%d latency not provided\n",
2191 name, level);
2192 continue;
2193 }
2194
2af30a5c
PB		 2195 /*
2196 * - latencies are in us on gen9.
2197 * - before then, WM1+ latency values are in 0.5us units
2198 */
2199 if (IS_GEN9(dev))
2200 latency *= 10;
2201 else if (level > 0)
26ec971e
VS		 2202 latency *= 5;
2203
2204 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2205 name, level, wm[level],
2206 latency / 10, latency % 10);
2207 }
2208}
2209
e95a2f75
VS		 2210static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2211 uint16_t wm[5], uint16_t min)
2212{
2213 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2214
2215 if (wm[0] >= min)
2216 return false;
2217
2218 wm[0] = max(wm[0], min);
2219 for (level = 1; level <= max_level; level++)
2220 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2221
2222 return true;
2223}
2224
2225static void snb_wm_latency_quirk(struct drm_device *dev)
2226{
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 bool changed;
2229
2230 /*
2231 * The BIOS provided WM memory latency values are often
2232 * inadequate for high resolution displays. Adjust them.
2233 */
2234 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2235 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2236 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2237
2238 if (!changed)
2239 return;
2240
2241 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2242 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2243 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2244 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2245}
2246
fa50ad61 2247static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2248{
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250
2251 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2252
2253 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2254 sizeof(dev_priv->wm.pri_latency));
2255 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2256 sizeof(dev_priv->wm.pri_latency));
2257
2258 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2259 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2260
2261 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2262 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2263 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2264
2265 if (IS_GEN6(dev))
2266 snb_wm_latency_quirk(dev);
53615a5e
VS		 2267}
2268
2af30a5c
PB		 2269static void skl_setup_wm_latency(struct drm_device *dev)
2270{
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2274 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2275}
2276
0b2ae6d7 2277/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2278static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2279 struct drm_atomic_state *state)
0b2ae6d7 2280{
86c8bbbe
MR		 2281 struct intel_pipe_wm *pipe_wm;
2282 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2283 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2284 struct intel_crtc_state *cstate = NULL;
43d59eda 2285 struct intel_plane *intel_plane;
86c8bbbe
MR		 2286 struct drm_plane_state *ps;
2287 struct intel_plane_state *pristate = NULL;
43d59eda 2288 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2289 struct intel_plane_state *curstate = NULL;
0b2ae6d7 2290 int level, max_level = ilk_wm_max_level(dev);
bf220452
MR		 2291 /* LP0 watermark maximums depend on this pipe alone */
2292 struct intel_wm_config config = {
2293 .num_pipes_active = 1,
2294 };
820c1980 2295 struct ilk_wm_maximums max;
0b2ae6d7 2296
86c8bbbe
MR		 2297 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2298 if (IS_ERR(cstate))
2299 return PTR_ERR(cstate);
2300
2301 pipe_wm = &cstate->wm.optimal.ilk;
f1ecaf8f 2302 memset(pipe_wm, 0, sizeof(*pipe_wm));
86c8bbbe 2303
43d59eda 2304 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2305 ps = drm_atomic_get_plane_state(state,
2306 &intel_plane->base);
2307 if (IS_ERR(ps))
2308 return PTR_ERR(ps);
2309
2310 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2311 pristate = to_intel_plane_state(ps);
2312 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2313 sprstate = to_intel_plane_state(ps);
2314 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2315 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2316 }
2317
bf220452
MR		 2318 config.sprites_enabled = sprstate->visible;
2319 config.sprites_scaled = sprstate->visible &&
43d59eda
MR		 2320 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2321 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2322
bf220452
MR		 2323 pipe_wm->pipe_enabled = cstate->base.active;
2324 pipe_wm->sprites_enabled = config.sprites_enabled;
2325 pipe_wm->sprites_scaled = config.sprites_scaled;
2326
7b39a0b7 2327 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2328 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2329 max_level = 1;
2330
2331 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
bf220452 2332 if (config.sprites_scaled)
7b39a0b7
VS		 2333 max_level = 0;
2334
86c8bbbe
MR		 2335 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2336 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2337
a42a5719 2338 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2339 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2340
bf220452
MR		 2341 /* LP0 watermarks always use 1/2 DDB partitioning */
2342 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2343
2344 /* At least LP0 must be valid */
2345 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2346 return -EINVAL;
a3cb4048
VS		 2347
2348 ilk_compute_wm_reg_maximums(dev, 1, &max);
2349
2350 for (level = 1; level <= max_level; level++) {
2351 struct intel_wm_level wm = {};
2352
86c8bbbe
MR		 2353 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2354 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2355
2356 /*
2357 * Disable any watermark level that exceeds the
2358 * register maximums since such watermarks are
2359 * always invalid.
2360 */
2361 if (!ilk_validate_wm_level(level, &max, &wm))
2362 break;
2363
2364 pipe_wm->wm[level] = wm;
2365 }
2366
86c8bbbe 2367 return 0;
0b2ae6d7
VS		 2368}
2369
2370/*
2371 * Merge the watermarks from all active pipes for a specific level.
2372 */
2373static void ilk_merge_wm_level(struct drm_device *dev,
2374 int level,
2375 struct intel_wm_level *ret_wm)
2376{
2377 const struct intel_crtc *intel_crtc;
2378
d52fea5b
VS		 2379 ret_wm->enable = true;
2380
d3fcc808 2381 for_each_intel_crtc(dev, intel_crtc) {
bf220452
MR		 2382 const struct intel_crtc_state *cstate =
2383 to_intel_crtc_state(intel_crtc->base.state);
2384 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2385 const struct intel_wm_level *wm = &active->wm[level];
2386
2387 if (!active->pipe_enabled)
2388 continue;
0b2ae6d7 2389
d52fea5b
VS		 2390 /*
2391 * The watermark values may have been used in the past,
2392 * so we must maintain them in the registers for some
2393 * time even if the level is now disabled.
2394 */
0b2ae6d7 2395 if (!wm->enable)
d52fea5b 2396 ret_wm->enable = false;
0b2ae6d7
VS		 2397
2398 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2399 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2400 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2401 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2402 }
0b2ae6d7
VS		 2403}
2404
2405/*
2406 * Merge all low power watermarks for all active pipes.
2407 */
2408static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2409 const struct intel_wm_config *config,
820c1980 2410 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2411 struct intel_pipe_wm *merged)
2412{
7733b49b 2413 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2414 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2415 int last_enabled_level = max_level;
0b2ae6d7 2416
0ba22e26
VS		 2417 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2418 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2419 config->num_pipes_active > 1)
2420 return;
2421
6c8b6c28
VS		 2422 /* ILK: FBC WM must be disabled always */
2423 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2424
2425 /* merge each WM1+ level */
2426 for (level = 1; level <= max_level; level++) {
2427 struct intel_wm_level *wm = &merged->wm[level];
2428
2429 ilk_merge_wm_level(dev, level, wm);
2430
d52fea5b
VS		 2431 if (level > last_enabled_level)
2432 wm->enable = false;
2433 else if (!ilk_validate_wm_level(level, max, wm))
2434 /* make sure all following levels get disabled */
2435 last_enabled_level = level - 1;
0b2ae6d7
VS		 2436
2437 /*
2438 * The spec says it is preferred to disable
2439 * FBC WMs instead of disabling a WM level.
2440 */
2441 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2442 if (wm->enable)
2443 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2444 wm->fbc_val = 0;
2445 }
2446 }
6c8b6c28
VS		 2447
2448 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2449 /*
2450 * FIXME this is racy. FBC might get enabled later.
2451 * What we should check here is whether FBC can be
2452 * enabled sometime later.
2453 */
7733b49b 2454 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2455 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2456 for (level = 2; level <= max_level; level++) {
2457 struct intel_wm_level *wm = &merged->wm[level];
2458
2459 wm->enable = false;
2460 }
2461 }
0b2ae6d7
VS		 2462}
2463
b380ca3c
VS		 2464static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2465{
2466 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2467 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2468}
2469
a68d68ee
VS		 2470/* The value we need to program into the WM_LPx latency field */
2471static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2472{
2473 struct drm_i915_private *dev_priv = dev->dev_private;
2474
a42a5719 2475 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2476 return 2 * level;
2477 else
2478 return dev_priv->wm.pri_latency[level];
2479}
2480
820c1980 2481static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2482 const struct intel_pipe_wm *merged,
609cedef 2483 enum intel_ddb_partitioning partitioning,
820c1980 2484 struct ilk_wm_values *results)
801bcfff 2485{
0b2ae6d7
VS		 2486 struct intel_crtc *intel_crtc;
2487 int level, wm_lp;
cca32e9a 2488
0362c781 2489 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2490 results->partitioning = partitioning;
cca32e9a 2491
0b2ae6d7 2492 /* LP1+ register values */
cca32e9a 2493 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2494 const struct intel_wm_level *r;
801bcfff 2495
b380ca3c 2496 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2497
0362c781 2498 r = &merged->wm[level];
cca32e9a 2499
d52fea5b
VS		 2500 /*
2501 * Maintain the watermark values even if the level is
2502 * disabled. Doing otherwise could cause underruns.
2503 */
2504 results->wm_lp[wm_lp - 1] =
a68d68ee 2505 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2506 (r->pri_val << WM1_LP_SR_SHIFT) |
2507 r->cur_val;
2508
d52fea5b
VS		 2509 if (r->enable)
2510 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2511
416f4727
VS		 2512 if (INTEL_INFO(dev)->gen >= 8)
2513 results->wm_lp[wm_lp - 1] |=
2514 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2515 else
2516 results->wm_lp[wm_lp - 1] |=
2517 r->fbc_val << WM1_LP_FBC_SHIFT;
2518
d52fea5b
VS		 2519 /*
2520 * Always set WM1S_LP_EN when spr_val != 0, even if the
2521 * level is disabled. Doing otherwise could cause underruns.
2522 */
6cef2b8a
VS		 2523 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2524 WARN_ON(wm_lp != 1);
2525 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2526 } else
2527 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2528 }
801bcfff 2529
0b2ae6d7 2530 /* LP0 register values */
d3fcc808 2531 for_each_intel_crtc(dev, intel_crtc) {
bf220452
MR		 2532 const struct intel_crtc_state *cstate =
2533 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2534 enum pipe pipe = intel_crtc->pipe;
bf220452 2535 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2536
2537 if (WARN_ON(!r->enable))
2538 continue;
2539
bf220452 2540 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2541
0b2ae6d7
VS		 2542 results->wm_pipe[pipe] =
2543 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2544 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2545 r->cur_val;
801bcfff
PZ		 2546 }
2547}
2548
861f3389
PZ		 2549/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2550 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2551static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2552 struct intel_pipe_wm *r1,
2553 struct intel_pipe_wm *r2)
861f3389 2554{
198a1e9b
VS		 2555 int level, max_level = ilk_wm_max_level(dev);
2556 int level1 = 0, level2 = 0;
861f3389 2557
198a1e9b
VS		 2558 for (level = 1; level <= max_level; level++) {
2559 if (r1->wm[level].enable)
2560 level1 = level;
2561 if (r2->wm[level].enable)
2562 level2 = level;
861f3389
PZ		 2563 }
2564
198a1e9b
VS		 2565 if (level1 == level2) {
2566 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2567 return r2;
2568 else
2569 return r1;
198a1e9b 2570 } else if (level1 > level2) {
861f3389
PZ		 2571 return r1;
2572 } else {
2573 return r2;
2574 }
2575}
2576
49a687c4
VS		 2577/* dirty bits used to track which watermarks need changes */
2578#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2579#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2580#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2581#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2582#define WM_DIRTY_FBC (1 << 24)
2583#define WM_DIRTY_DDB (1 << 25)
2584
055e393f 2585static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2586 const struct ilk_wm_values *old,
2587 const struct ilk_wm_values *new)
49a687c4
VS		 2588{
2589 unsigned int dirty = 0;
2590 enum pipe pipe;
2591 int wm_lp;
2592
055e393f 2593 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2594 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2595 dirty |= WM_DIRTY_LINETIME(pipe);
2596 /* Must disable LP1+ watermarks too */
2597 dirty |= WM_DIRTY_LP_ALL;
2598 }
2599
2600 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2601 dirty |= WM_DIRTY_PIPE(pipe);
2602 /* Must disable LP1+ watermarks too */
2603 dirty |= WM_DIRTY_LP_ALL;
2604 }
2605 }
2606
2607 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2608 dirty |= WM_DIRTY_FBC;
2609 /* Must disable LP1+ watermarks too */
2610 dirty |= WM_DIRTY_LP_ALL;
2611 }
2612
2613 if (old->partitioning != new->partitioning) {
2614 dirty |= WM_DIRTY_DDB;
2615 /* Must disable LP1+ watermarks too */
2616 dirty |= WM_DIRTY_LP_ALL;
2617 }
2618
2619 /* LP1+ watermarks already deemed dirty, no need to continue */
2620 if (dirty & WM_DIRTY_LP_ALL)
2621 return dirty;
2622
2623 /* Find the lowest numbered LP1+ watermark in need of an update... */
2624 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2625 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2626 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2627 break;
2628 }
2629
2630 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2631 for (; wm_lp <= 3; wm_lp++)
2632 dirty |= WM_DIRTY_LP(wm_lp);
2633
2634 return dirty;
2635}
2636
8553c18e
VS		 2637static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2638 unsigned int dirty)
801bcfff 2639{
820c1980 2640 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2641 bool changed = false;
801bcfff 2642
facd619b
VS		 2643 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2644 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2645 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2646 changed = true;
facd619b
VS		 2647 }
2648 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2649 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2650 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2651 changed = true;
facd619b
VS		 2652 }
2653 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2654 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2655 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2656 changed = true;
facd619b 2657 }
801bcfff 2658
facd619b
VS		 2659 /*
2660 * Don't touch WM1S_LP_EN here.
2661 * Doing so could cause underruns.
2662 */
6cef2b8a 2663
8553c18e
VS		 2664 return changed;
2665}
2666
2667/*
2668 * The spec says we shouldn't write when we don't need, because every write
2669 * causes WMs to be re-evaluated, expending some power.
2670 */
820c1980
ID		 2671static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2672 struct ilk_wm_values *results)
8553c18e
VS		 2673{
2674 struct drm_device *dev = dev_priv->dev;
820c1980 2675 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2676 unsigned int dirty;
2677 uint32_t val;
2678
055e393f 2679 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2680 if (!dirty)
2681 return;
2682
2683 _ilk_disable_lp_wm(dev_priv, dirty);
2684
49a687c4 2685 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2686 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2687 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2688 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2689 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2690 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2691
49a687c4 2692 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2693 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2694 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2695 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2696 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2697 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2698
49a687c4 2699 if (dirty & WM_DIRTY_DDB) {
a42a5719 2700 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2701 val = I915_READ(WM_MISC);
2702 if (results->partitioning == INTEL_DDB_PART_1_2)
2703 val &= ~WM_MISC_DATA_PARTITION_5_6;
2704 else
2705 val |= WM_MISC_DATA_PARTITION_5_6;
2706 I915_WRITE(WM_MISC, val);
2707 } else {
2708 val = I915_READ(DISP_ARB_CTL2);
2709 if (results->partitioning == INTEL_DDB_PART_1_2)
2710 val &= ~DISP_DATA_PARTITION_5_6;
2711 else
2712 val |= DISP_DATA_PARTITION_5_6;
2713 I915_WRITE(DISP_ARB_CTL2, val);
2714 }
1011d8c4
PZ		 2715 }
2716
49a687c4 2717 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2718 val = I915_READ(DISP_ARB_CTL);
2719 if (results->enable_fbc_wm)
2720 val &= ~DISP_FBC_WM_DIS;
2721 else
2722 val |= DISP_FBC_WM_DIS;
2723 I915_WRITE(DISP_ARB_CTL, val);
2724 }
2725
954911eb
ID		 2726 if (dirty & WM_DIRTY_LP(1) &&
2727 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2728 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2729
2730 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2731 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2732 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2733 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2734 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2735 }
801bcfff 2736
facd619b 2737 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2738 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2739 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2740 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2741 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2742 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2743
2744 dev_priv->wm.hw = *results;
801bcfff
PZ		 2745}
2746
bf220452 2747static bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2748{
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750
2751 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2752}
2753
b9cec075
DL		 2754/*
2755 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2756 * different active planes.
2757 */
2758
2759#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2760#define BXT_DDB_SIZE 512
b9cec075 2761
024c9045
MR		 2762/*
2763 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2764 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2765 * other universal planes are in indices 1..n. Note that this may leave unused
2766 * indices between the top "sprite" plane and the cursor.
2767 */
2768static int
2769skl_wm_plane_id(const struct intel_plane *plane)
2770{
2771 switch (plane->base.type) {
2772 case DRM_PLANE_TYPE_PRIMARY:
2773 return 0;
2774 case DRM_PLANE_TYPE_CURSOR:
2775 return PLANE_CURSOR;
2776 case DRM_PLANE_TYPE_OVERLAY:
2777 return plane->plane + 1;
2778 default:
2779 MISSING_CASE(plane->base.type);
2780 return plane->plane;
2781 }
2782}
2783
b9cec075
DL		 2784static void
2785skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2786 const struct intel_crtc_state *cstate,
b9cec075 2787 const struct intel_wm_config *config,
b9cec075
DL		 2788 struct skl_ddb_entry *alloc /* out */)
2789{
024c9045 2790 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2791 struct drm_crtc *crtc;
2792 unsigned int pipe_size, ddb_size;
2793 int nth_active_pipe;
2794
024c9045 2795 if (!cstate->base.active) {
b9cec075
DL		 2796 alloc->start = 0;
2797 alloc->end = 0;
2798 return;
2799 }
2800
43d735a6
DL		 2801 if (IS_BROXTON(dev))
2802 ddb_size = BXT_DDB_SIZE;
2803 else
2804 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2805
2806 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2807
2808 nth_active_pipe = 0;
2809 for_each_crtc(dev, crtc) {
3ef00284 2810 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2811 continue;
2812
2813 if (crtc == for_crtc)
2814 break;
2815
2816 nth_active_pipe++;
2817 }
2818
2819 pipe_size = ddb_size / config->num_pipes_active;
2820 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2821 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2822}
2823
2824static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2825{
2826 if (config->num_pipes_active == 1)
2827 return 32;
2828
2829 return 8;
2830}
2831
a269c583
DL		 2832static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2833{
2834 entry->start = reg & 0x3ff;
2835 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2836 if (entry->end)
2837 entry->end += 1;
a269c583
DL		 2838}
2839
08db6652
DL		 2840void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2841 struct skl_ddb_allocation *ddb /* out */)
a269c583 2842{
a269c583
DL		 2843 enum pipe pipe;
2844 int plane;
2845 u32 val;
2846
b10f1b20
ML		 2847 memset(ddb, 0, sizeof(*ddb));
2848
a269c583 2849 for_each_pipe(dev_priv, pipe) {
b10f1b20
ML		 2850 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2851 continue;
2852
dd740780 2853 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2854 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2855 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2856 val);
2857 }
2858
2859 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2860 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2861 val);
a269c583
DL		 2862 }
2863}
2864
b9cec075 2865static unsigned int
024c9045
MR		 2866skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2867 const struct drm_plane_state *pstate,
2868 int y)
b9cec075 2869{
024c9045
MR		 2870 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2871 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2872
2873 /* for planar format */
024c9045 2874 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2875 if (y) /* y-plane data rate */
024c9045
MR		 2876 return intel_crtc->config->pipe_src_w *
2877 intel_crtc->config->pipe_src_h *
2878 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2879 else /* uv-plane data rate */
024c9045
MR		 2880 return (intel_crtc->config->pipe_src_w/2) *
2881 (intel_crtc->config->pipe_src_h/2) *
2882 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2883 }
2884
2885 /* for packed formats */
024c9045
MR		 2886 return intel_crtc->config->pipe_src_w *
2887 intel_crtc->config->pipe_src_h *
2888 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2889}
2890
2891/*
2892 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2893 * a 8192x4096@32bpp framebuffer:
2894 * 3 * 4096 * 8192 * 4 < 2^32
2895 */
2896static unsigned int
024c9045 2897skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2898{
024c9045
MR		 2899 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2900 struct drm_device *dev = intel_crtc->base.dev;
2901 const struct intel_plane *intel_plane;
b9cec075 2902 unsigned int total_data_rate = 0;
b9cec075 2903
024c9045
MR		 2904 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2905 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2906
024c9045 2907 if (pstate->fb == NULL)
b9cec075
DL		 2908 continue;
2909
024c9045
MR		 2910 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2911 continue;
2912
2913 /* packed/uv */
2914 total_data_rate += skl_plane_relative_data_rate(cstate,
2915 pstate,
2916 0);
2917
2918 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2919 /* y-plane */
2920 total_data_rate += skl_plane_relative_data_rate(cstate,
2921 pstate,
2922 1);
b9cec075
DL		 2923 }
2924
2925 return total_data_rate;
2926}
2927
2928static void
024c9045 2929skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2930 struct skl_ddb_allocation *ddb /* out */)
2931{
024c9045 2932 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2933 struct drm_device *dev = crtc->dev;
aa363136
MR		 2934 struct drm_i915_private *dev_priv = to_i915(dev);
2935 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2937 struct intel_plane *intel_plane;
b9cec075 2938 enum pipe pipe = intel_crtc->pipe;
34bb56af 2939 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2940 uint16_t alloc_size, start, cursor_blocks;
80958155 2941 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2942 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2943 unsigned int total_data_rate;
b9cec075 2944
024c9045 2945 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2946 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2947 if (alloc_size == 0) {
2948 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2949 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2950 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2951 return;
2952 }
2953
2954 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2955 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2956 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2957
2958 alloc_size -= cursor_blocks;
34bb56af 2959 alloc->end -= cursor_blocks;
b9cec075 2960
80958155 2961 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2962 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2963 struct drm_plane *plane = &intel_plane->base;
2964 struct drm_framebuffer *fb = plane->state->fb;
2965 int id = skl_wm_plane_id(intel_plane);
80958155 2966
024c9045
MR		 2967 if (fb == NULL)
2968 continue;
2969 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2970 continue;
2971
024c9045
MR		 2972 minimum[id] = 8;
2973 alloc_size -= minimum[id];
2974 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2975 alloc_size -= y_minimum[id];
80958155
DL		 2976 }
2977
b9cec075 2978 /*
80958155
DL		 2979 * 2. Distribute the remaining space in proportion to the amount of
2980 * data each plane needs to fetch from memory.
b9cec075
DL		 2981 *
2982 * FIXME: we may not allocate every single block here.
2983 */
024c9045 2984 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2985
34bb56af 2986 start = alloc->start;
024c9045
MR		 2987 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2988 struct drm_plane *plane = &intel_plane->base;
2989 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2990 unsigned int data_rate, y_data_rate;
2991 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2992 int id = skl_wm_plane_id(intel_plane);
b9cec075 2993
024c9045
MR		 2994 if (pstate->fb == NULL)
2995 continue;
2996 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 2997 continue;
2998
024c9045 2999 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3000
3001 /*
2cd601c6 3002 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3003 * promote the expression to 64 bits to avoid overflowing, the
3004 * result is < available as data_rate / total_data_rate < 1
3005 */
024c9045 3006 plane_blocks = minimum[id];
80958155
DL		 3007 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3008 total_data_rate);
b9cec075 3009
024c9045
MR		 3010 ddb->plane[pipe][id].start = start;
3011 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3012
3013 start += plane_blocks;
2cd601c6
CK		 3014
3015 /*
3016 * allocation for y_plane part of planar format:
3017 */
024c9045
MR		 3018 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3019 y_data_rate = skl_plane_relative_data_rate(cstate,
3020 pstate,
3021 1);
3022 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3023 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3024 total_data_rate);
3025
024c9045
MR		 3026 ddb->y_plane[pipe][id].start = start;
3027 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3028
3029 start += y_plane_blocks;
3030 }
3031
b9cec075
DL		 3032 }
3033
3034}
3035
5cec258b 3036static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3037{
3038 /* TODO: Take into account the scalers once we support them */
2d112de7 3039 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3040}
3041
3042/*
3043 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3044 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3045 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3046 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3047*/
ac484963 3048static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3049{
3050 uint32_t wm_intermediate_val, ret;
3051
3052 if (latency == 0)
3053 return UINT_MAX;
3054
ac484963 3055 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3056 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3057
3058 return ret;
3059}
3060
3061static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3062 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3063 uint64_t tiling, uint32_t latency)
2d41c0b5 3064{
d4c2aa60
TU		 3065 uint32_t ret;
3066 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3067 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3068
3069 if (latency == 0)
3070 return UINT_MAX;
3071
ac484963 3072 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3073
3074 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3075 tiling == I915_FORMAT_MOD_Yf_TILED) {
3076 plane_bytes_per_line *= 4;
3077 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3078 plane_blocks_per_line /= 4;
3079 } else {
3080 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3081 }
3082
2d41c0b5
PB		 3083 wm_intermediate_val = latency * pixel_rate;
3084 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3085 plane_blocks_per_line;
2d41c0b5
PB		 3086
3087 return ret;
3088}
3089
2d41c0b5
PB		 3090static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3091 const struct intel_crtc *intel_crtc)
3092{
3093 struct drm_device *dev = intel_crtc->base.dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3096
e6d90023
KM		 3097 /*
3098 * If ddb allocation of pipes changed, it may require recalculation of
3099 * watermarks
3100 */
3101 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3102 return true;
3103
3104 return false;
3105}
3106
d4c2aa60 3107static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3108 struct intel_crtc_state *cstate,
3109 struct intel_plane *intel_plane,
afb024aa 3110 uint16_t ddb_allocation,
d4c2aa60 3111 int level,
afb024aa
DL		 3112 uint16_t *out_blocks, /* out */
3113 uint8_t *out_lines /* out */)
2d41c0b5 3114{
024c9045
MR		 3115 struct drm_plane *plane = &intel_plane->base;
3116 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3117 uint32_t latency = dev_priv->wm.skl_latency[level];
3118 uint32_t method1, method2;
3119 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3120 uint32_t res_blocks, res_lines;
3121 uint32_t selected_result;
ac484963 3122 uint8_t cpp;
2d41c0b5 3123
024c9045 3124 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3125 return false;
3126
ac484963 3127 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3128 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3129 cpp, latency);
024c9045
MR		 3130 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3131 cstate->base.adjusted_mode.crtc_htotal,
3132 cstate->pipe_src_w,
ac484963 3133 cpp, fb->modifier[0],
d4c2aa60 3134 latency);
2d41c0b5 3135
ac484963 3136 plane_bytes_per_line = cstate->pipe_src_w * cpp;
d4c2aa60 3137 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3138
024c9045
MR		 3139 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3140 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3141 uint32_t min_scanlines = 4;
3142 uint32_t y_tile_minimum;
024c9045 3143 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3144 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3145 drm_format_plane_cpp(fb->pixel_format, 1) :
3146 drm_format_plane_cpp(fb->pixel_format, 0);
3147
ac484963 3148 switch (cpp) {
1fc0a8f7
TU		 3149 case 1:
3150 min_scanlines = 16;
3151 break;
3152 case 2:
3153 min_scanlines = 8;
3154 break;
3155 case 8:
3156 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3157 }
1fc0a8f7
TU		 3158 }
3159 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3160 selected_result = max(method2, y_tile_minimum);
3161 } else {
3162 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3163 selected_result = min(method1, method2);
3164 else
3165 selected_result = method1;
3166 }
2d41c0b5 3167
d4c2aa60
TU		 3168 res_blocks = selected_result + 1;
3169 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3170
0fda6568 3171 if (level >= 1 && level <= 7) {
024c9045
MR		 3172 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3173 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3174 res_lines += 4;
3175 else
3176 res_blocks++;
3177 }
e6d66171 3178
d4c2aa60 3179 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3180 return false;
3181
3182 *out_blocks = res_blocks;
3183 *out_lines = res_lines;
2d41c0b5
PB		 3184
3185 return true;
3186}
3187
3188static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3189 struct skl_ddb_allocation *ddb,
024c9045 3190 struct intel_crtc_state *cstate,
2d41c0b5 3191 int level,
2d41c0b5
PB		 3192 struct skl_wm_level *result)
3193{
024c9045
MR		 3194 struct drm_device *dev = dev_priv->dev;
3195 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3196 struct intel_plane *intel_plane;
2d41c0b5 3197 uint16_t ddb_blocks;
024c9045
MR		 3198 enum pipe pipe = intel_crtc->pipe;
3199
3200 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3201 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3202
2d41c0b5
PB		 3203 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3204
d4c2aa60 3205 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3206 cstate,
3207 intel_plane,
2d41c0b5 3208 ddb_blocks,
d4c2aa60 3209 level,
2d41c0b5
PB		 3210 &result->plane_res_b[i],
3211 &result->plane_res_l[i]);
3212 }
2d41c0b5
PB		 3213}
3214
407b50f3 3215static uint32_t
024c9045 3216skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3217{
024c9045 3218 if (!cstate->base.active)
407b50f3
DL		 3219 return 0;
3220
024c9045 3221 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3222 return 0;
407b50f3 3223
024c9045
MR		 3224 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3225 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3226}
3227
024c9045 3228static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3229 struct skl_wm_level *trans_wm /* out */)
407b50f3 3230{
024c9045 3231 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3233 struct intel_plane *intel_plane;
9414f563 3234
024c9045 3235 if (!cstate->base.active)
407b50f3 3236 return;
9414f563
DL		 3237
3238 /* Until we know more, just disable transition WMs */
024c9045
MR		 3239 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3240 int i = skl_wm_plane_id(intel_plane);
3241
9414f563 3242 trans_wm->plane_en[i] = false;
024c9045 3243 }
407b50f3
DL		 3244}
3245
024c9045 3246static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3247 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3248 struct skl_pipe_wm *pipe_wm)
3249{
024c9045 3250 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3251 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3252 int level, max_level = ilk_wm_max_level(dev);
3253
3254 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3255 skl_compute_wm_level(dev_priv, ddb, cstate,
3256 level, &pipe_wm->wm[level]);
2d41c0b5 3257 }
024c9045 3258 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3259
024c9045 3260 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3261}
3262
3263static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3264 struct skl_pipe_wm *p_wm,
3265 struct skl_wm_values *r,
3266 struct intel_crtc *intel_crtc)
3267{
3268 int level, max_level = ilk_wm_max_level(dev);
3269 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3270 uint32_t temp;
3271 int i;
2d41c0b5
PB		 3272
3273 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3274 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3275 temp = 0;
2d41c0b5
PB		 3276
3277 temp |= p_wm->wm[level].plane_res_l[i] <<
3278 PLANE_WM_LINES_SHIFT;
3279 temp |= p_wm->wm[level].plane_res_b[i];
3280 if (p_wm->wm[level].plane_en[i])
3281 temp |= PLANE_WM_EN;
3282
3283 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3284 }
3285
3286 temp = 0;
2d41c0b5 3287
4969d33e
MR		 3288 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3289 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3290
4969d33e 3291 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3292 temp |= PLANE_WM_EN;
3293
4969d33e 3294 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3295
3296 }
3297
9414f563
DL		 3298 /* transition WMs */
3299 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3300 temp = 0;
3301 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3302 temp |= p_wm->trans_wm.plane_res_b[i];
3303 if (p_wm->trans_wm.plane_en[i])
3304 temp |= PLANE_WM_EN;
3305
3306 r->plane_trans[pipe][i] = temp;
3307 }
3308
3309 temp = 0;
4969d33e
MR		 3310 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3311 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3312 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3313 temp |= PLANE_WM_EN;
3314
4969d33e 3315 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3316
2d41c0b5
PB		 3317 r->wm_linetime[pipe] = p_wm->linetime;
3318}
3319
f0f59a00
VS		 3320static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3321 i915_reg_t reg,
16160e3d
DL		 3322 const struct skl_ddb_entry *entry)
3323{
3324 if (entry->end)
3325 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3326 else
3327 I915_WRITE(reg, 0);
3328}
3329
2d41c0b5
PB		 3330static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3331 const struct skl_wm_values *new)
3332{
3333 struct drm_device *dev = dev_priv->dev;
3334 struct intel_crtc *crtc;
3335
19c8054c 3336 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3337 int i, level, max_level = ilk_wm_max_level(dev);
3338 enum pipe pipe = crtc->pipe;
3339
5d374d96
DL		 3340 if (!new->dirty[pipe])
3341 continue;
8211bd5b 3342
5d374d96 3343 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3344
5d374d96
DL		 3345 for (level = 0; level <= max_level; level++) {
3346 for (i = 0; i < intel_num_planes(crtc); i++)
3347 I915_WRITE(PLANE_WM(pipe, i, level),
3348 new->plane[pipe][i][level]);
3349 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3350 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3351 }
5d374d96
DL		 3352 for (i = 0; i < intel_num_planes(crtc); i++)
3353 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3354 new->plane_trans[pipe][i]);
4969d33e
MR		 3355 I915_WRITE(CUR_WM_TRANS(pipe),
3356 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3357
2cd601c6 3358 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3359 skl_ddb_entry_write(dev_priv,
3360 PLANE_BUF_CFG(pipe, i),
3361 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3362 skl_ddb_entry_write(dev_priv,
3363 PLANE_NV12_BUF_CFG(pipe, i),
3364 &new->ddb.y_plane[pipe][i]);
3365 }
5d374d96
DL		 3366
3367 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3368 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3369 }
2d41c0b5
PB		 3370}
3371
0e8fb7ba
DL		 3372/*
3373 * When setting up a new DDB allocation arrangement, we need to correctly
3374 * sequence the times at which the new allocations for the pipes are taken into
3375 * account or we'll have pipes fetching from space previously allocated to
3376 * another pipe.
3377 *
3378 * Roughly the sequence looks like:
3379 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3380 * overlapping with a previous light-up pipe (another way to put it is:
3381 * pipes with their new allocation strickly included into their old ones).
3382 * 2. re-allocate the other pipes that get their allocation reduced
3383 * 3. allocate the pipes having their allocation increased
3384 *
3385 * Steps 1. and 2. are here to take care of the following case:
3386 * - Initially DDB looks like this:
3387 * | B | C |
3388 * - enable pipe A.
3389 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3390 * allocation
3391 * | A | B | C |
3392 *
3393 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3394 */
3395
d21b795c
DL		 3396static void
3397skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3398{
0e8fb7ba
DL		 3399 int plane;
3400
d21b795c
DL		 3401 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3402
dd740780 3403 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3404 I915_WRITE(PLANE_SURF(pipe, plane),
3405 I915_READ(PLANE_SURF(pipe, plane)));
3406 }
3407 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3408}
3409
3410static bool
3411skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3412 const struct skl_ddb_allocation *new,
3413 enum pipe pipe)
3414{
3415 uint16_t old_size, new_size;
3416
3417 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3418 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3419
3420 return old_size != new_size &&
3421 new->pipe[pipe].start >= old->pipe[pipe].start &&
3422 new->pipe[pipe].end <= old->pipe[pipe].end;
3423}
3424
3425static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3426 struct skl_wm_values *new_values)
3427{
3428 struct drm_device *dev = dev_priv->dev;
3429 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3430 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3431 struct intel_crtc *crtc;
3432 enum pipe pipe;
3433
3434 new_ddb = &new_values->ddb;
3435 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3436
3437 /*
3438 * First pass: flush the pipes with the new allocation contained into
3439 * the old space.
3440 *
3441 * We'll wait for the vblank on those pipes to ensure we can safely
3442 * re-allocate the freed space without this pipe fetching from it.
3443 */
3444 for_each_intel_crtc(dev, crtc) {
3445 if (!crtc->active)
3446 continue;
3447
3448 pipe = crtc->pipe;
3449
3450 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3451 continue;
3452
d21b795c 3453 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3454 intel_wait_for_vblank(dev, pipe);
3455
3456 reallocated[pipe] = true;
3457 }
3458
3459
3460 /*
3461 * Second pass: flush the pipes that are having their allocation
3462 * reduced, but overlapping with a previous allocation.
3463 *
3464 * Here as well we need to wait for the vblank to make sure the freed
3465 * space is not used anymore.
3466 */
3467 for_each_intel_crtc(dev, crtc) {
3468 if (!crtc->active)
3469 continue;
3470
3471 pipe = crtc->pipe;
3472
3473 if (reallocated[pipe])
3474 continue;
3475
3476 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3477 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3478 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3479 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3480 reallocated[pipe] = true;
0e8fb7ba 3481 }
0e8fb7ba
DL		 3482 }
3483
3484 /*
3485 * Third pass: flush the pipes that got more space allocated.
3486 *
3487 * We don't need to actively wait for the update here, next vblank
3488 * will just get more DDB space with the correct WM values.
3489 */
3490 for_each_intel_crtc(dev, crtc) {
3491 if (!crtc->active)
3492 continue;
3493
3494 pipe = crtc->pipe;
3495
3496 /*
3497 * At this point, only the pipes more space than before are
3498 * left to re-allocate.
3499 */
3500 if (reallocated[pipe])
3501 continue;
3502
d21b795c 3503 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3504 }
3505}
3506
2d41c0b5 3507static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3508 struct skl_ddb_allocation *ddb, /* out */
3509 struct skl_pipe_wm *pipe_wm /* out */)
3510{
3511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3512 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3513
aa363136 3514 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3515 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3516
4e0963c7 3517 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3518 return false;
3519
4e0963c7 3520 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3521
2d41c0b5
PB		 3522 return true;
3523}
3524
3525static void skl_update_other_pipe_wm(struct drm_device *dev,
3526 struct drm_crtc *crtc,
2d41c0b5
PB		 3527 struct skl_wm_values *r)
3528{
3529 struct intel_crtc *intel_crtc;
3530 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3531
3532 /*
3533 * If the WM update hasn't changed the allocation for this_crtc (the
3534 * crtc we are currently computing the new WM values for), other
3535 * enabled crtcs will keep the same allocation and we don't need to
3536 * recompute anything for them.
3537 */
3538 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3539 return;
3540
3541 /*
3542 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3543 * other active pipes need new DDB allocation and WM values.
3544 */
19c8054c 3545 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3546 struct skl_pipe_wm pipe_wm = {};
3547 bool wm_changed;
3548
3549 if (this_crtc->pipe == intel_crtc->pipe)
3550 continue;
3551
3552 if (!intel_crtc->active)
3553 continue;
3554
aa363136 3555 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3556 &r->ddb, &pipe_wm);
3557
3558 /*
3559 * If we end up re-computing the other pipe WM values, it's
3560 * because it was really needed, so we expect the WM values to
3561 * be different.
3562 */
3563 WARN_ON(!wm_changed);
3564
024c9045 3565 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3566 r->dirty[intel_crtc->pipe] = true;
3567 }
3568}
3569
adda50b8
BP		 3570static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3571{
3572 watermarks->wm_linetime[pipe] = 0;
3573 memset(watermarks->plane[pipe], 0,
3574 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3575 memset(watermarks->plane_trans[pipe],
3576 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3577 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3578
3579 /* Clear ddb entries for pipe */
3580 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3581 memset(&watermarks->ddb.plane[pipe], 0,
3582 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3583 memset(&watermarks->ddb.y_plane[pipe], 0,
3584 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3585 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3586 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3587
3588}
3589
2d41c0b5
PB		 3590static void skl_update_wm(struct drm_crtc *crtc)
3591{
3592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593 struct drm_device *dev = crtc->dev;
3594 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3595 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3596 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3597 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3598
adda50b8
BP		 3599
3600 /* Clear all dirty flags */
3601 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3602
3603 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3604
aa363136 3605 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3606 return;
3607
4e0963c7 3608 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3609 results->dirty[intel_crtc->pipe] = true;
3610
aa363136 3611 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3612 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3613 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3614
3615 /* store the new configuration */
3616 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3617}
3618
d890565c
VS		 3619static void ilk_compute_wm_config(struct drm_device *dev,
3620 struct intel_wm_config *config)
3621{
3622 struct intel_crtc *crtc;
3623
3624 /* Compute the currently _active_ config */
3625 for_each_intel_crtc(dev, crtc) {
3626 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3627
3628 if (!wm->pipe_enabled)
3629 continue;
3630
3631 config->sprites_enabled |= wm->sprites_enabled;
3632 config->sprites_scaled |= wm->sprites_scaled;
3633 config->num_pipes_active++;
3634 }
3635}
3636
bf220452 3637static void ilk_program_watermarks(struct intel_crtc_state *cstate)
801bcfff 3638{
bf220452
MR		 3639 struct drm_crtc *crtc = cstate->base.crtc;
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = to_i915(dev);
b9d5c839 3642 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3643 struct ilk_wm_maximums max;
d890565c 3644 struct intel_wm_config config = {};
820c1980 3645 struct ilk_wm_values results = {};
77c122bc 3646 enum intel_ddb_partitioning partitioning;
261a27d1 3647
d890565c
VS		 3648 ilk_compute_wm_config(dev, &config);
3649
3650 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3651 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3652
3653 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3654 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3655 config.num_pipes_active == 1 && config.sprites_enabled) {
3656 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3657 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3658
820c1980 3659 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3660 } else {
198a1e9b 3661 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3662 }
3663
198a1e9b 3664 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3665 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3666
820c1980 3667 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3668
820c1980 3669 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3670}
3671
bf220452 3672static void ilk_update_wm(struct drm_crtc *crtc)
b9d5c839 3673{
bf220452
MR		 3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
b9d5c839 3676
bf220452 3677 WARN_ON(cstate->base.active != intel_crtc->active);
b9d5c839 3678
bf220452
MR		 3679 /*
3680 * IVB workaround: must disable low power watermarks for at least
3681 * one frame before enabling scaling. LP watermarks can be re-enabled
3682 * when scaling is disabled.
3683 *
3684 * WaCxSRDisabledForSpriteScaling:ivb
3685 */
3686 if (cstate->disable_lp_wm) {
3687 ilk_disable_lp_wm(crtc->dev);
3688 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
396e33ae 3689 }
bf220452
MR		 3690
3691 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3692
3693 ilk_program_watermarks(cstate);
b9d5c839
VS		 3694}
3695
3078999f
PB		 3696static void skl_pipe_wm_active_state(uint32_t val,
3697 struct skl_pipe_wm *active,
3698 bool is_transwm,
3699 bool is_cursor,
3700 int i,
3701 int level)
3702{
3703 bool is_enabled = (val & PLANE_WM_EN) != 0;
3704
3705 if (!is_transwm) {
3706 if (!is_cursor) {
3707 active->wm[level].plane_en[i] = is_enabled;
3708 active->wm[level].plane_res_b[i] =
3709 val & PLANE_WM_BLOCKS_MASK;
3710 active->wm[level].plane_res_l[i] =
3711 (val >> PLANE_WM_LINES_SHIFT) &
3712 PLANE_WM_LINES_MASK;
3713 } else {
4969d33e
MR		 3714 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3715 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3716 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3717 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3718 (val >> PLANE_WM_LINES_SHIFT) &
3719 PLANE_WM_LINES_MASK;
3720 }
3721 } else {
3722 if (!is_cursor) {
3723 active->trans_wm.plane_en[i] = is_enabled;
3724 active->trans_wm.plane_res_b[i] =
3725 val & PLANE_WM_BLOCKS_MASK;
3726 active->trans_wm.plane_res_l[i] =
3727 (val >> PLANE_WM_LINES_SHIFT) &
3728 PLANE_WM_LINES_MASK;
3729 } else {
4969d33e
MR		 3730 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3731 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3732 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3733 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3734 (val >> PLANE_WM_LINES_SHIFT) &
3735 PLANE_WM_LINES_MASK;
3736 }
3737 }
3738}
3739
3740static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3746 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3747 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3748 enum pipe pipe = intel_crtc->pipe;
3749 int level, i, max_level;
3750 uint32_t temp;
3751
3752 max_level = ilk_wm_max_level(dev);
3753
3754 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3755
3756 for (level = 0; level <= max_level; level++) {
3757 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3758 hw->plane[pipe][i][level] =
3759 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3760 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3761 }
3762
3763 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3764 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3765 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3766
3ef00284 3767 if (!intel_crtc->active)
3078999f
PB		 3768 return;
3769
3770 hw->dirty[pipe] = true;
3771
3772 active->linetime = hw->wm_linetime[pipe];
3773
3774 for (level = 0; level <= max_level; level++) {
3775 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3776 temp = hw->plane[pipe][i][level];
3777 skl_pipe_wm_active_state(temp, active, false,
3778 false, i, level);
3779 }
4969d33e 3780 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3781 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3782 }
3783
3784 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3785 temp = hw->plane_trans[pipe][i];
3786 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3787 }
3788
4969d33e 3789 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3790 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3791
3792 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3793}
3794
3795void skl_wm_get_hw_state(struct drm_device *dev)
3796{
a269c583
DL		 3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3799 struct drm_crtc *crtc;
3800
a269c583 3801 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3802 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3803 skl_pipe_wm_get_hw_state(crtc);
3804}
3805
243e6a44
VS		 3806static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3807{
3808 struct drm_device *dev = crtc->dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3810 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3812 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3813 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3814 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3815 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3816 [PIPE_A] = WM0_PIPEA_ILK,
3817 [PIPE_B] = WM0_PIPEB_ILK,
3818 [PIPE_C] = WM0_PIPEC_IVB,
3819 };
3820
3821 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3822 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3823 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3824
3ef00284 3825 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3826
3827 if (active->pipe_enabled) {
243e6a44
VS		 3828 u32 tmp = hw->wm_pipe[pipe];
3829
3830 /*
3831 * For active pipes LP0 watermark is marked as
3832 * enabled, and LP1+ watermaks as disabled since
3833 * we can't really reverse compute them in case
3834 * multiple pipes are active.
3835 */
3836 active->wm[0].enable = true;
3837 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3838 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3839 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3840 active->linetime = hw->wm_linetime[pipe];
3841 } else {
3842 int level, max_level = ilk_wm_max_level(dev);
3843
3844 /*
3845 * For inactive pipes, all watermark levels
3846 * should be marked as enabled but zeroed,
3847 * which is what we'd compute them to.
3848 */
3849 for (level = 0; level <= max_level; level++)
3850 active->wm[level].enable = true;
3851 }
4e0963c7
MR		 3852
3853 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3854}
3855
6eb1a681
VS		 3856#define _FW_WM(value, plane) \
3857 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3858#define _FW_WM_VLV(value, plane) \
3859 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3860
3861static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3862 struct vlv_wm_values *wm)
3863{
3864 enum pipe pipe;
3865 uint32_t tmp;
3866
3867 for_each_pipe(dev_priv, pipe) {
3868 tmp = I915_READ(VLV_DDL(pipe));
3869
3870 wm->ddl[pipe].primary =
3871 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3872 wm->ddl[pipe].cursor =
3873 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3874 wm->ddl[pipe].sprite[0] =
3875 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3876 wm->ddl[pipe].sprite[1] =
3877 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3878 }
3879
3880 tmp = I915_READ(DSPFW1);
3881 wm->sr.plane = _FW_WM(tmp, SR);
3882 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3883 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3884 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3885
3886 tmp = I915_READ(DSPFW2);
3887 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3888 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3889 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3890
3891 tmp = I915_READ(DSPFW3);
3892 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3893
3894 if (IS_CHERRYVIEW(dev_priv)) {
3895 tmp = I915_READ(DSPFW7_CHV);
3896 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3897 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3898
3899 tmp = I915_READ(DSPFW8_CHV);
3900 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3901 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3902
3903 tmp = I915_READ(DSPFW9_CHV);
3904 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3905 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3906
3907 tmp = I915_READ(DSPHOWM);
3908 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3909 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3910 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3911 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3912 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3913 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3914 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3915 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3916 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3917 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3918 } else {
3919 tmp = I915_READ(DSPFW7);
3920 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3921 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3922
3923 tmp = I915_READ(DSPHOWM);
3924 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3925 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3926 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3927 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3928 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3929 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3930 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3931 }
3932}
3933
3934#undef _FW_WM
3935#undef _FW_WM_VLV
3936
3937void vlv_wm_get_hw_state(struct drm_device *dev)
3938{
3939 struct drm_i915_private *dev_priv = to_i915(dev);
3940 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3941 struct intel_plane *plane;
3942 enum pipe pipe;
3943 u32 val;
3944
3945 vlv_read_wm_values(dev_priv, wm);
3946
3947 for_each_intel_plane(dev, plane) {
3948 switch (plane->base.type) {
3949 int sprite;
3950 case DRM_PLANE_TYPE_CURSOR:
3951 plane->wm.fifo_size = 63;
3952 break;
3953 case DRM_PLANE_TYPE_PRIMARY:
3954 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3955 break;
3956 case DRM_PLANE_TYPE_OVERLAY:
3957 sprite = plane->plane;
3958 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3959 break;
3960 }
3961 }
3962
3963 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3964 wm->level = VLV_WM_LEVEL_PM2;
3965
3966 if (IS_CHERRYVIEW(dev_priv)) {
3967 mutex_lock(&dev_priv->rps.hw_lock);
3968
3969 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3970 if (val & DSP_MAXFIFO_PM5_ENABLE)
3971 wm->level = VLV_WM_LEVEL_PM5;
3972
58590c14
VS		 3973 /*
3974 * If DDR DVFS is disabled in the BIOS, Punit
3975 * will never ack the request. So if that happens
3976 * assume we don't have to enable/disable DDR DVFS
3977 * dynamically. To test that just set the REQ_ACK
3978 * bit to poke the Punit, but don't change the
3979 * HIGH/LOW bits so that we don't actually change
3980 * the current state.
3981 */
6eb1a681 3982 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3983 val |= FORCE_DDR_FREQ_REQ_ACK;
3984 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3985
3986 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3987 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3988 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3989 "assuming DDR DVFS is disabled\n");
3990 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3991 } else {
3992 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3993 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3994 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3995 }
6eb1a681
VS		 3996
3997 mutex_unlock(&dev_priv->rps.hw_lock);
3998 }
3999
4000 for_each_pipe(dev_priv, pipe)
4001 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4002 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4003 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4004
4005 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4006 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4007}
4008
243e6a44
VS		 4009void ilk_wm_get_hw_state(struct drm_device *dev)
4010{
4011 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4012 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4013 struct drm_crtc *crtc;
4014
70e1e0ec 4015 for_each_crtc(dev, crtc)
243e6a44
VS		 4016 ilk_pipe_wm_get_hw_state(crtc);
4017
4018 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4019 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4020 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4021
4022 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4023 if (INTEL_INFO(dev)->gen >= 7) {
4024 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4025 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4026 }
243e6a44 4027
a42a5719 4028 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4029 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4030 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4031 else if (IS_IVYBRIDGE(dev))
4032 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4033 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4034
4035 hw->enable_fbc_wm =
4036 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4037}
4038
b445e3b0
ED		 4039/**
4040 * intel_update_watermarks - update FIFO watermark values based on current modes
4041 *
4042 * Calculate watermark values for the various WM regs based on current mode
4043 * and plane configuration.
4044 *
4045 * There are several cases to deal with here:
4046 * - normal (i.e. non-self-refresh)
4047 * - self-refresh (SR) mode
4048 * - lines are large relative to FIFO size (buffer can hold up to 2)
4049 * - lines are small relative to FIFO size (buffer can hold more than 2
4050 * lines), so need to account for TLB latency
4051 *
4052 * The normal calculation is:
4053 * watermark = dotclock * bytes per pixel * latency
4054 * where latency is platform & configuration dependent (we assume pessimal
4055 * values here).
4056 *
4057 * The SR calculation is:
4058 * watermark = (trunc(latency/line time)+1) * surface width *
4059 * bytes per pixel
4060 * where
4061 * line time = htotal / dotclock
4062 * surface width = hdisplay for normal plane and 64 for cursor
4063 * and latency is assumed to be high, as above.
4064 *
4065 * The final value programmed to the register should always be rounded up,
4066 * and include an extra 2 entries to account for clock crossings.
4067 *
4068 * We don't use the sprite, so we can ignore that. And on Crestline we have
4069 * to set the non-SR watermarks to 8.
4070 */
46ba614c 4071void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4072{
46ba614c 4073 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4074
4075 if (dev_priv->display.update_wm)
46ba614c 4076 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4077}
4078
e2828914 4079/*
9270388e 4080 * Lock protecting IPS related data structures
9270388e
DV		 4081 */
4082DEFINE_SPINLOCK(mchdev_lock);
4083
4084/* Global for IPS driver to get at the current i915 device. Protected by
4085 * mchdev_lock. */
4086static struct drm_i915_private *i915_mch_dev;
4087
2b4e57bd
ED		 4088bool ironlake_set_drps(struct drm_device *dev, u8 val)
4089{
4090 struct drm_i915_private *dev_priv = dev->dev_private;
4091 u16 rgvswctl;
4092
9270388e
DV		 4093 assert_spin_locked(&mchdev_lock);
4094
2b4e57bd
ED		 4095 rgvswctl = I915_READ16(MEMSWCTL);
4096 if (rgvswctl & MEMCTL_CMD_STS) {
4097 DRM_DEBUG("gpu busy, RCS change rejected\n");
4098 return false; /* still busy with another command */
4099 }
4100
4101 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4102 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4103 I915_WRITE16(MEMSWCTL, rgvswctl);
4104 POSTING_READ16(MEMSWCTL);
4105
4106 rgvswctl |= MEMCTL_CMD_STS;
4107 I915_WRITE16(MEMSWCTL, rgvswctl);
4108
4109 return true;
4110}
4111
8090c6b9 4112static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4113{
4114 struct drm_i915_private *dev_priv = dev->dev_private;
4115 u32 rgvmodectl = I915_READ(MEMMODECTL);
4116 u8 fmax, fmin, fstart, vstart;
4117
9270388e
DV		 4118 spin_lock_irq(&mchdev_lock);
4119
2b4e57bd
ED		 4120 /* Enable temp reporting */
4121 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4122 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4123
4124 /* 100ms RC evaluation intervals */
4125 I915_WRITE(RCUPEI, 100000);
4126 I915_WRITE(RCDNEI, 100000);
4127
4128 /* Set max/min thresholds to 90ms and 80ms respectively */
4129 I915_WRITE(RCBMAXAVG, 90000);
4130 I915_WRITE(RCBMINAVG, 80000);
4131
4132 I915_WRITE(MEMIHYST, 1);
4133
4134 /* Set up min, max, and cur for interrupt handling */
4135 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4136 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4137 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4138 MEMMODE_FSTART_SHIFT;
4139
616847e7 4140 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4141 PXVFREQ_PX_SHIFT;
4142
20e4d407
DV		 4143 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4144 dev_priv->ips.fstart = fstart;
2b4e57bd 4145
20e4d407
DV		 4146 dev_priv->ips.max_delay = fstart;
4147 dev_priv->ips.min_delay = fmin;
4148 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4149
4150 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4151 fmax, fmin, fstart);
4152
4153 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4154
4155 /*
4156 * Interrupts will be enabled in ironlake_irq_postinstall
4157 */
4158
4159 I915_WRITE(VIDSTART, vstart);
4160 POSTING_READ(VIDSTART);
4161
4162 rgvmodectl |= MEMMODE_SWMODE_EN;
4163 I915_WRITE(MEMMODECTL, rgvmodectl);
4164
9270388e 4165 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4166 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4167 mdelay(1);
2b4e57bd
ED		 4168
4169 ironlake_set_drps(dev, fstart);
4170
7d81c3e0
VS		 4171 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4172 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4173 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4174 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4175 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4176
4177 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4178}
4179
8090c6b9 4180static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4181{
4182 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4183 u16 rgvswctl;
4184
4185 spin_lock_irq(&mchdev_lock);
4186
4187 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4188
4189 /* Ack interrupts, disable EFC interrupt */
4190 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4191 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4192 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4193 I915_WRITE(DEIIR, DE_PCU_EVENT);
4194 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4195
4196 /* Go back to the starting frequency */
20e4d407 4197 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4198 mdelay(1);
2b4e57bd
ED		 4199 rgvswctl |= MEMCTL_CMD_STS;
4200 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4201 mdelay(1);
2b4e57bd 4202
9270388e 4203 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4204}
4205
acbe9475
DV		 4206/* There's a funny hw issue where the hw returns all 0 when reading from
4207 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4208 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4209 * all limits and the gpu stuck at whatever frequency it is at atm).
4210 */
74ef1173 4211static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4212{
7b9e0ae6 4213 u32 limits;
2b4e57bd 4214
20b46e59
DV		 4215 /* Only set the down limit when we've reached the lowest level to avoid
4216 * getting more interrupts, otherwise leave this clear. This prevents a
4217 * race in the hw when coming out of rc6: There's a tiny window where
4218 * the hw runs at the minimal clock before selecting the desired
4219 * frequency, if the down threshold expires in that window we will not
4220 * receive a down interrupt. */
74ef1173
AG		 4221 if (IS_GEN9(dev_priv->dev)) {
4222 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4223 if (val <= dev_priv->rps.min_freq_softlimit)
4224 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4225 } else {
4226 limits = dev_priv->rps.max_freq_softlimit << 24;
4227 if (val <= dev_priv->rps.min_freq_softlimit)
4228 limits |= dev_priv->rps.min_freq_softlimit << 16;
4229 }
20b46e59
DV		 4230
4231 return limits;
4232}
4233
dd75fdc8
CW		 4234static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4235{
4236 int new_power;
8a586437
AG		 4237 u32 threshold_up = 0, threshold_down = 0; /* in % */
4238 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4239
4240 new_power = dev_priv->rps.power;
4241 switch (dev_priv->rps.power) {
4242 case LOW_POWER:
b39fb297 4243 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4244 new_power = BETWEEN;
4245 break;
4246
4247 case BETWEEN:
b39fb297 4248 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4249 new_power = LOW_POWER;
b39fb297 4250 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4251 new_power = HIGH_POWER;
4252 break;
4253
4254 case HIGH_POWER:
b39fb297 4255 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4256 new_power = BETWEEN;
4257 break;
4258 }
4259 /* Max/min bins are special */
aed242ff 4260 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4261 new_power = LOW_POWER;
aed242ff 4262 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4263 new_power = HIGH_POWER;
4264 if (new_power == dev_priv->rps.power)
4265 return;
4266
4267 /* Note the units here are not exactly 1us, but 1280ns. */
4268 switch (new_power) {
4269 case LOW_POWER:
4270 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4271 ei_up = 16000;
4272 threshold_up = 95;
dd75fdc8
CW		 4273
4274 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4275 ei_down = 32000;
4276 threshold_down = 85;
dd75fdc8
CW		 4277 break;
4278
4279 case BETWEEN:
4280 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4281 ei_up = 13000;
4282 threshold_up = 90;
dd75fdc8
CW		 4283
4284 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4285 ei_down = 32000;
4286 threshold_down = 75;
dd75fdc8
CW		 4287 break;
4288
4289 case HIGH_POWER:
4290 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4291 ei_up = 10000;
4292 threshold_up = 85;
dd75fdc8
CW		 4293
4294 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4295 ei_down = 32000;
4296 threshold_down = 60;
dd75fdc8
CW		 4297 break;
4298 }
4299
8a586437
AG		 4300 I915_WRITE(GEN6_RP_UP_EI,
4301 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4302 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4303 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4304
4305 I915_WRITE(GEN6_RP_DOWN_EI,
4306 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4307 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4308 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4309
4310 I915_WRITE(GEN6_RP_CONTROL,
4311 GEN6_RP_MEDIA_TURBO |
4312 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4313 GEN6_RP_MEDIA_IS_GFX |
4314 GEN6_RP_ENABLE |
4315 GEN6_RP_UP_BUSY_AVG |
4316 GEN6_RP_DOWN_IDLE_AVG);
4317
dd75fdc8 4318 dev_priv->rps.power = new_power;
8fb55197
CW		 4319 dev_priv->rps.up_threshold = threshold_up;
4320 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4321 dev_priv->rps.last_adj = 0;
4322}
4323
2876ce73
CW		 4324static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4325{
4326 u32 mask = 0;
4327
4328 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4329 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4330 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4331 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4332
7b3c29f6
CW		 4333 mask &= dev_priv->pm_rps_events;
4334
59d02a1f 4335 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4336}
4337
b8a5ff8d
JM		 4338/* gen6_set_rps is called to update the frequency request, but should also be
4339 * called when the range (min_delay and max_delay) is modified so that we can
4340 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4341static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4342{
4343 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4344
23eafea6 4345 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4346 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4347 return;
4348
4fc688ce 4349 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4350 WARN_ON(val > dev_priv->rps.max_freq);
4351 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4352
eb64cad1
CW		 4353 /* min/max delay may still have been modified so be sure to
4354 * write the limits value.
4355 */
4356 if (val != dev_priv->rps.cur_freq) {
4357 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4358
5704195c
AG		 4359 if (IS_GEN9(dev))
4360 I915_WRITE(GEN6_RPNSWREQ,
4361 GEN9_FREQUENCY(val));
4362 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4363 I915_WRITE(GEN6_RPNSWREQ,
4364 HSW_FREQUENCY(val));
4365 else
4366 I915_WRITE(GEN6_RPNSWREQ,
4367 GEN6_FREQUENCY(val) |
4368 GEN6_OFFSET(0) |
4369 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4370 }
7b9e0ae6 4371
7b9e0ae6
CW		 4372 /* Make sure we continue to get interrupts
4373 * until we hit the minimum or maximum frequencies.
4374 */
74ef1173 4375 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4376 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4377
d5570a72
BW		 4378 POSTING_READ(GEN6_RPNSWREQ);
4379
b39fb297 4380 dev_priv->rps.cur_freq = val;
0f94592e 4381 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4382}
4383
ffe02b40
VS		 4384static void valleyview_set_rps(struct drm_device *dev, u8 val)
4385{
4386 struct drm_i915_private *dev_priv = dev->dev_private;
4387
4388 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4389 WARN_ON(val > dev_priv->rps.max_freq);
4390 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4391
4392 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4393 "Odd GPU freq value\n"))
4394 val &= ~1;
4395
cd25dd5b
D		 4396 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4397
8fb55197 4398 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4399 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4400 if (!IS_CHERRYVIEW(dev_priv))
4401 gen6_set_rps_thresholds(dev_priv, val);
4402 }
ffe02b40 4403
ffe02b40
VS		 4404 dev_priv->rps.cur_freq = val;
4405 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4406}
4407
a7f6e231 4408/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4409 *
4410 * * If Gfx is Idle, then
a7f6e231
D		 4411 * 1. Forcewake Media well.
4412 * 2. Request idle freq.
4413 * 3. Release Forcewake of Media well.
76c3552f
D		 4414*/
4415static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4416{
aed242ff 4417 u32 val = dev_priv->rps.idle_freq;
5549d25f 4418
aed242ff 4419 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4420 return;
4421
a7f6e231
D		 4422 /* Wake up the media well, as that takes a lot less
4423 * power than the Render well. */
4424 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4425 valleyview_set_rps(dev_priv->dev, val);
4426 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4427}
4428
43cf3bf0
CW		 4429void gen6_rps_busy(struct drm_i915_private *dev_priv)
4430{
4431 mutex_lock(&dev_priv->rps.hw_lock);
4432 if (dev_priv->rps.enabled) {
4433 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4434 gen6_rps_reset_ei(dev_priv);
4435 I915_WRITE(GEN6_PMINTRMSK,
4436 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4437 }
4438 mutex_unlock(&dev_priv->rps.hw_lock);
4439}
4440
b29c19b6
CW		 4441void gen6_rps_idle(struct drm_i915_private *dev_priv)
4442{
691bb717
DL		 4443 struct drm_device *dev = dev_priv->dev;
4444
b29c19b6 4445 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4446 if (dev_priv->rps.enabled) {
666a4537 4447 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4448 vlv_set_rps_idle(dev_priv);
7526ed79 4449 else
aed242ff 4450 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4451 dev_priv->rps.last_adj = 0;
43cf3bf0 4452 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4453 }
8d3afd7d 4454 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4455
8d3afd7d 4456 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4457 while (!list_empty(&dev_priv->rps.clients))
4458 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4459 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4460}
4461
1854d5ca 4462void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4463 struct intel_rps_client *rps,
4464 unsigned long submitted)
b29c19b6 4465{
8d3afd7d
CW		 4466 /* This is intentionally racy! We peek at the state here, then
4467 * validate inside the RPS worker.
4468 */
4469 if (!(dev_priv->mm.busy &&
4470 dev_priv->rps.enabled &&
4471 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4472 return;
43cf3bf0 4473
e61b9958
CW		 4474 /* Force a RPS boost (and don't count it against the client) if
4475 * the GPU is severely congested.
4476 */
d0bc54f2 4477 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4478 rps = NULL;
4479
8d3afd7d
CW		 4480 spin_lock(&dev_priv->rps.client_lock);
4481 if (rps == NULL || list_empty(&rps->link)) {
4482 spin_lock_irq(&dev_priv->irq_lock);
4483 if (dev_priv->rps.interrupts_enabled) {
4484 dev_priv->rps.client_boost = true;
4485 queue_work(dev_priv->wq, &dev_priv->rps.work);
4486 }
4487 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4488
2e1b8730
CW		 4489 if (rps != NULL) {
4490 list_add(&rps->link, &dev_priv->rps.clients);
4491 rps->boosts++;
1854d5ca
CW		 4492 } else
4493 dev_priv->rps.boosts++;
c0951f0c 4494 }
8d3afd7d 4495 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4496}
4497
ffe02b40 4498void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4499{
666a4537 4500 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4501 valleyview_set_rps(dev, val);
4502 else
4503 gen6_set_rps(dev, val);
0a073b84
JB		 4504}
4505
20e49366
ZW		 4506static void gen9_disable_rps(struct drm_device *dev)
4507{
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509
4510 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4511 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4512}
4513
44fc7d5c 4514static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4515{
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517
4518 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4519 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4520}
4521
38807746
D		 4522static void cherryview_disable_rps(struct drm_device *dev)
4523{
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525
4526 I915_WRITE(GEN6_RC_CONTROL, 0);
4527}
4528
44fc7d5c
DV		 4529static void valleyview_disable_rps(struct drm_device *dev)
4530{
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532
98a2e5f9
D		 4533 /* we're doing forcewake before Disabling RC6,
4534 * This what the BIOS expects when going into suspend */
59bad947 4535 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4536
44fc7d5c 4537 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4538
59bad947 4539 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4540}
4541
dc39fff7
BW		 4542static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4543{
666a4537 4544 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4545 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4546 mode = GEN6_RC_CTL_RC6_ENABLE;
4547 else
4548 mode = 0;
4549 }
58abf1da
RV		 4550 if (HAS_RC6p(dev))
4551 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4552 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4553 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4554 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4555
4556 else
4557 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4558 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4559}
4560
e6069ca8 4561static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4562{
e7d66d89
DV		 4563 /* No RC6 before Ironlake and code is gone for ilk. */
4564 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4565 return 0;
4566
456470eb 4567 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4568 if (enable_rc6 >= 0) {
4569 int mask;
4570
58abf1da 4571 if (HAS_RC6p(dev))
e6069ca8
ID		 4572 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4573 INTEL_RC6pp_ENABLE;
4574 else
4575 mask = INTEL_RC6_ENABLE;
4576
4577 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4578 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4579 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4580
4581 return enable_rc6 & mask;
4582 }
2b4e57bd 4583
8bade1ad 4584 if (IS_IVYBRIDGE(dev))
cca84a1f 4585 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4586
4587 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4588}
4589
e6069ca8
ID		 4590int intel_enable_rc6(const struct drm_device *dev)
4591{
4592 return i915.enable_rc6;
4593}
4594
93ee2920 4595static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4596{
93ee2920
TR		 4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 uint32_t rp_state_cap;
4599 u32 ddcc_status = 0;
4600 int ret;
4601
3280e8b0
BW		 4602 /* All of these values are in units of 50MHz */
4603 dev_priv->rps.cur_freq = 0;
93ee2920 4604 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4605 if (IS_BROXTON(dev)) {
4606 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4607 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4608 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4609 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4610 } else {
4611 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4612 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4613 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4614 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4615 }
4616
3280e8b0
BW		 4617 /* hw_max = RP0 until we check for overclocking */
4618 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4619
93ee2920 4620 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4621 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4622 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4623 ret = sandybridge_pcode_read(dev_priv,
4624 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4625 &ddcc_status);
4626 if (0 == ret)
4627 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4628 clamp_t(u8,
4629 ((ddcc_status >> 8) & 0xff),
4630 dev_priv->rps.min_freq,
4631 dev_priv->rps.max_freq);
93ee2920
TR		 4632 }
4633
ef11bdb3 4634 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4635 /* Store the frequency values in 16.66 MHZ units, which is
4636 the natural hardware unit for SKL */
4637 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4638 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4639 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4640 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4641 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4642 }
4643
aed242ff
CW		 4644 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4645
3280e8b0
BW		 4646 /* Preserve min/max settings in case of re-init */
4647 if (dev_priv->rps.max_freq_softlimit == 0)
4648 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4649
93ee2920
TR		 4650 if (dev_priv->rps.min_freq_softlimit == 0) {
4651 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4652 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4653 max_t(int, dev_priv->rps.efficient_freq,
4654 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4655 else
4656 dev_priv->rps.min_freq_softlimit =
4657 dev_priv->rps.min_freq;
4658 }
3280e8b0
BW		 4659}
4660
b6fef0ef 4661/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4662static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4663{
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4667
ba1c554c
DL		 4668 gen6_init_rps_frequencies(dev);
4669
23eafea6 4670 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4671 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4672 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4673 return;
4674 }
4675
0beb059a
AG		 4676 /* Program defaults and thresholds for RPS*/
4677 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4678 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4679
4680 /* 1 second timeout*/
4681 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4682 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4683
b6fef0ef 4684 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4685
0beb059a
AG		 4686 /* Leaning on the below call to gen6_set_rps to program/setup the
4687 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4688 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4689 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4690 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4691
4692 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4693}
4694
4695static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4696{
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_engine_cs *ring;
4699 uint32_t rc6_mask = 0;
4700 int unused;
4701
4702 /* 1a: Software RC state - RC0 */
4703 I915_WRITE(GEN6_RC_STATE, 0);
4704
4705 /* 1b: Get forcewake during program sequence. Although the driver
4706 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4707 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4708
4709 /* 2a: Disable RC states. */
4710 I915_WRITE(GEN6_RC_CONTROL, 0);
4711
4712 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4713
4714 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4715 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4716 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4717 else
4718 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4719 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4720 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4721 for_each_ring(ring, dev_priv, unused)
4722 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4723
4724 if (HAS_GUC_UCODE(dev))
4725 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4726
20e49366 4727 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4728
38c23527
ZW		 4729 /* 2c: Program Coarse Power Gating Policies. */
4730 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4731 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4732
20e49366
ZW		 4733 /* 3a: Enable RC6 */
4734 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4735 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 4736 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 4737 /* WaRsUseTimeoutMode */
e87a005d 4738 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4739 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4740 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4741 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4742 GEN7_RC_CTL_TO_MODE |
4743 rc6_mask);
3e7732a0
SAK		 4744 } else {
4745 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4746 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4747 GEN6_RC_CTL_EI_MODE(1) |
4748 rc6_mask);
3e7732a0 4749 }
20e49366 4750
cb07bae0
SK		 4751 /*
4752 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4753 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4754 */
06e668ac 4755 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4756 I915_WRITE(GEN9_PG_ENABLE, 0);
4757 else
4758 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4759 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4760
59bad947 4761 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4762
4763}
4764
6edee7f3
BW		 4765static void gen8_enable_rps(struct drm_device *dev)
4766{
4767 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4768 struct intel_engine_cs *ring;
93ee2920 4769 uint32_t rc6_mask = 0;
6edee7f3
BW		 4770 int unused;
4771
4772 /* 1a: Software RC state - RC0 */
4773 I915_WRITE(GEN6_RC_STATE, 0);
4774
4775 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4776 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4777 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4778
4779 /* 2a: Disable RC states. */
4780 I915_WRITE(GEN6_RC_CONTROL, 0);
4781
93ee2920
TR		 4782 /* Initialize rps frequencies */
4783 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4784
4785 /* 2b: Program RC6 thresholds.*/
4786 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4787 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4788 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4789 for_each_ring(ring, dev_priv, unused)
4790 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4791 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4792 if (IS_BROADWELL(dev))
4793 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4794 else
4795 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4796
4797 /* 3: Enable RC6 */
4798 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4799 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4800 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4801 if (IS_BROADWELL(dev))
4802 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4803 GEN7_RC_CTL_TO_MODE |
4804 rc6_mask);
4805 else
4806 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4807 GEN6_RC_CTL_EI_MODE(1) |
4808 rc6_mask);
6edee7f3
BW		 4809
4810 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4811 I915_WRITE(GEN6_RPNSWREQ,
4812 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4813 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4814 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4815 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4816 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4817
4818 /* Docs recommend 900MHz, and 300 MHz respectively */
4819 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4820 dev_priv->rps.max_freq_softlimit << 24 |
4821 dev_priv->rps.min_freq_softlimit << 16);
4822
4823 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4824 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4825 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4826 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4827
4828 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4829
4830 /* 5: Enable RPS */
7526ed79
DV		 4831 I915_WRITE(GEN6_RP_CONTROL,
4832 GEN6_RP_MEDIA_TURBO |
4833 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4834 GEN6_RP_MEDIA_IS_GFX |
4835 GEN6_RP_ENABLE |
4836 GEN6_RP_UP_BUSY_AVG |
4837 GEN6_RP_DOWN_IDLE_AVG);
4838
4839 /* 6: Ring frequency + overclocking (our driver does this later */
4840
c7f3153a 4841 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4842 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4843
59bad947 4844 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4845}
4846
79f5b2c7 4847static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4848{
79f5b2c7 4849 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4850 struct intel_engine_cs *ring;
d060c169 4851 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4852 u32 gtfifodbg;
2b4e57bd 4853 int rc6_mode;
42c0526c 4854 int i, ret;
2b4e57bd 4855
4fc688ce 4856 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4857
2b4e57bd
ED		 4858 /* Here begins a magic sequence of register writes to enable
4859 * auto-downclocking.
4860 *
4861 * Perhaps there might be some value in exposing these to
4862 * userspace...
4863 */
4864 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4865
4866 /* Clear the DBG now so we don't confuse earlier errors */
4867 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4868 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4869 I915_WRITE(GTFIFODBG, gtfifodbg);
4870 }
4871
59bad947 4872 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4873
93ee2920
TR		 4874 /* Initialize rps frequencies */
4875 gen6_init_rps_frequencies(dev);
dd0a1aa1 4876
2b4e57bd
ED		 4877 /* disable the counters and set deterministic thresholds */
4878 I915_WRITE(GEN6_RC_CONTROL, 0);
4879
4880 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4881 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4882 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4883 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4884 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4885
b4519513
CW		 4886 for_each_ring(ring, dev_priv, i)
4887 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4888
4889 I915_WRITE(GEN6_RC_SLEEP, 0);
4890 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4891 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4892 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4893 else
4894 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4895 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4896 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4897
5a7dc92a 4898 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4899 rc6_mode = intel_enable_rc6(dev_priv->dev);
4900 if (rc6_mode & INTEL_RC6_ENABLE)
4901 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4902
5a7dc92a
ED		 4903 /* We don't use those on Haswell */
4904 if (!IS_HASWELL(dev)) {
4905 if (rc6_mode & INTEL_RC6p_ENABLE)
4906 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4907
5a7dc92a
ED		 4908 if (rc6_mode & INTEL_RC6pp_ENABLE)
4909 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4910 }
2b4e57bd 4911
dc39fff7 4912 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4913
4914 I915_WRITE(GEN6_RC_CONTROL,
4915 rc6_mask |
4916 GEN6_RC_CTL_EI_MODE(1) |
4917 GEN6_RC_CTL_HW_ENABLE);
4918
dd75fdc8
CW		 4919 /* Power down if completely idle for over 50ms */
4920 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4921 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4922
42c0526c 4923 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4924 if (ret)
42c0526c 4925 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4926
4927 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4928 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4929 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4930 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4931 (pcu_mbox & 0xff) * 50);
b39fb297 4932 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4933 }
4934
dd75fdc8 4935 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4936 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4937
31643d54
BW		 4938 rc6vids = 0;
4939 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4940 if (IS_GEN6(dev) && ret) {
4941 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4942 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4943 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4944 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4945 rc6vids &= 0xffff00;
4946 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4947 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4948 if (ret)
4949 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4950 }
4951
59bad947 4952 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4953}
4954
c2bc2fc5 4955static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4956{
79f5b2c7 4957 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4958 int min_freq = 15;
3ebecd07
CW		 4959 unsigned int gpu_freq;
4960 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4961 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4962 int scaling_factor = 180;
eda79642 4963 struct cpufreq_policy *policy;
2b4e57bd 4964
4fc688ce 4965 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4966
eda79642
BW		 4967 policy = cpufreq_cpu_get(0);
4968 if (policy) {
4969 max_ia_freq = policy->cpuinfo.max_freq;
4970 cpufreq_cpu_put(policy);
4971 } else {
4972 /*
4973 * Default to measured freq if none found, PCU will ensure we
4974 * don't go over
4975 */
2b4e57bd 4976 max_ia_freq = tsc_khz;
eda79642 4977 }
2b4e57bd
ED		 4978
4979 /* Convert from kHz to MHz */
4980 max_ia_freq /= 1000;
4981
153b4b95 4982 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4983 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4984 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4985
ef11bdb3 4986 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4987 /* Convert GT frequency to 50 HZ units */
4988 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4989 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4990 } else {
4991 min_gpu_freq = dev_priv->rps.min_freq;
4992 max_gpu_freq = dev_priv->rps.max_freq;
4993 }
4994
2b4e57bd
ED		 4995 /*
4996 * For each potential GPU frequency, load a ring frequency we'd like
4997 * to use for memory access. We do this by specifying the IA frequency
4998 * the PCU should use as a reference to determine the ring frequency.
4999 */
4c8c7743
AG		 5000 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5001 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5002 unsigned int ia_freq = 0, ring_freq = 0;
5003
ef11bdb3 5004 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5005 /*
5006 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5007 * No floor required for ring frequency on SKL.
5008 */
5009 ring_freq = gpu_freq;
5010 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5011 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5012 ring_freq = max(min_ring_freq, gpu_freq);
5013 } else if (IS_HASWELL(dev)) {
f6aca45c 5014 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5015 ring_freq = max(min_ring_freq, ring_freq);
5016 /* leave ia_freq as the default, chosen by cpufreq */
5017 } else {
5018 /* On older processors, there is no separate ring
5019 * clock domain, so in order to boost the bandwidth
5020 * of the ring, we need to upclock the CPU (ia_freq).
5021 *
5022 * For GPU frequencies less than 750MHz,
5023 * just use the lowest ring freq.
5024 */
5025 if (gpu_freq < min_freq)
5026 ia_freq = 800;
5027 else
5028 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5029 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5030 }
2b4e57bd 5031
42c0526c
BW		 5032 sandybridge_pcode_write(dev_priv,
5033 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5034 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5035 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5036 gpu_freq);
2b4e57bd 5037 }
2b4e57bd
ED		 5038}
5039
c2bc2fc5
ID		 5040void gen6_update_ring_freq(struct drm_device *dev)
5041{
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5043
97d3308a 5044 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5045 return;
5046
5047 mutex_lock(&dev_priv->rps.hw_lock);
5048 __gen6_update_ring_freq(dev);
5049 mutex_unlock(&dev_priv->rps.hw_lock);
5050}
5051
03af2045 5052static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5053{
095acd5f 5054 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5055 u32 val, rp0;
5056
5b5929cb 5057 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5058
5b5929cb
JN		 5059 switch (INTEL_INFO(dev)->eu_total) {
5060 case 8:
5061 /* (2 * 4) config */
5062 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5063 break;
5064 case 12:
5065 /* (2 * 6) config */
5066 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5067 break;
5068 case 16:
5069 /* (2 * 8) config */
5070 default:
5071 /* Setting (2 * 8) Min RP0 for any other combination */
5072 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5073 break;
095acd5f 5074 }
5b5929cb
JN		 5075
5076 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5077
2b6b3a09
D		 5078 return rp0;
5079}
5080
5081static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5082{
5083 u32 val, rpe;
5084
5085 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5086 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5087
5088 return rpe;
5089}
5090
7707df4a
D		 5091static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5092{
5093 u32 val, rp1;
5094
5b5929cb
JN		 5095 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5096 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5097
7707df4a
D		 5098 return rp1;
5099}
5100
f8f2b001
D		 5101static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5102{
5103 u32 val, rp1;
5104
5105 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5106
5107 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5108
5109 return rp1;
5110}
5111
03af2045 5112static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5113{
5114 u32 val, rp0;
5115
64936258 5116 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5117
5118 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5119 /* Clamp to max */
5120 rp0 = min_t(u32, rp0, 0xea);
5121
5122 return rp0;
5123}
5124
5125static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5126{
5127 u32 val, rpe;
5128
64936258 5129 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5130 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5131 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5132 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5133
5134 return rpe;
5135}
5136
03af2045 5137static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5138{
36146035
ID		 5139 u32 val;
5140
5141 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5142 /*
5143 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5144 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5145 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5146 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5147 * to make sure it matches what Punit accepts.
5148 */
5149 return max_t(u32, val, 0xc0);
0a073b84
JB		 5150}
5151
ae48434c
ID		 5152/* Check that the pctx buffer wasn't move under us. */
5153static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5154{
5155 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5156
5157 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5158 dev_priv->vlv_pctx->stolen->start);
5159}
5160
38807746
D		 5161
5162/* Check that the pcbr address is not empty. */
5163static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5164{
5165 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5166
5167 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5168}
5169
5170static void cherryview_setup_pctx(struct drm_device *dev)
5171{
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 unsigned long pctx_paddr, paddr;
5174 struct i915_gtt *gtt = &dev_priv->gtt;
5175 u32 pcbr;
5176 int pctx_size = 32*1024;
5177
5178 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5179
5180 pcbr = I915_READ(VLV_PCBR);
5181 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5182 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5183 paddr = (dev_priv->mm.stolen_base +
5184 (gtt->stolen_size - pctx_size));
5185
5186 pctx_paddr = (paddr & (~4095));
5187 I915_WRITE(VLV_PCBR, pctx_paddr);
5188 }
ce611ef8
VS		 5189
5190 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5191}
5192
c9cddffc
JB		 5193static void valleyview_setup_pctx(struct drm_device *dev)
5194{
5195 struct drm_i915_private *dev_priv = dev->dev_private;
5196 struct drm_i915_gem_object *pctx;
5197 unsigned long pctx_paddr;
5198 u32 pcbr;
5199 int pctx_size = 24*1024;
5200
17b0c1f7
ID		 5201 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5202
c9cddffc
JB		 5203 pcbr = I915_READ(VLV_PCBR);
5204 if (pcbr) {
5205 /* BIOS set it up already, grab the pre-alloc'd space */
5206 int pcbr_offset;
5207
5208 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5209 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5210 pcbr_offset,
190d6cd5 5211 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5212 pctx_size);
5213 goto out;
5214 }
5215
ce611ef8
VS		 5216 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5217
c9cddffc
JB		 5218 /*
5219 * From the Gunit register HAS:
5220 * The Gfx driver is expected to program this register and ensure
5221 * proper allocation within Gfx stolen memory. For example, this
5222 * register should be programmed such than the PCBR range does not
5223 * overlap with other ranges, such as the frame buffer, protected
5224 * memory, or any other relevant ranges.
5225 */
5226 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5227 if (!pctx) {
5228 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5229 return;
5230 }
5231
5232 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5233 I915_WRITE(VLV_PCBR, pctx_paddr);
5234
5235out:
ce611ef8 5236 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5237 dev_priv->vlv_pctx = pctx;
5238}
5239
ae48434c
ID		 5240static void valleyview_cleanup_pctx(struct drm_device *dev)
5241{
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243
5244 if (WARN_ON(!dev_priv->vlv_pctx))
5245 return;
5246
5247 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5248 dev_priv->vlv_pctx = NULL;
5249}
5250
4e80519e
ID		 5251static void valleyview_init_gt_powersave(struct drm_device *dev)
5252{
5253 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5254 u32 val;
4e80519e
ID		 5255
5256 valleyview_setup_pctx(dev);
5257
5258 mutex_lock(&dev_priv->rps.hw_lock);
5259
2bb25c17
VS		 5260 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5261 switch ((val >> 6) & 3) {
5262 case 0:
5263 case 1:
5264 dev_priv->mem_freq = 800;
5265 break;
5266 case 2:
5267 dev_priv->mem_freq = 1066;
5268 break;
5269 case 3:
5270 dev_priv->mem_freq = 1333;
5271 break;
5272 }
80b83b62 5273 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5274
4e80519e
ID		 5275 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5276 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5277 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5278 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5279 dev_priv->rps.max_freq);
5280
5281 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5282 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5283 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5284 dev_priv->rps.efficient_freq);
5285
f8f2b001
D		 5286 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5287 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5288 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5289 dev_priv->rps.rp1_freq);
5290
4e80519e
ID		 5291 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5292 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5293 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5294 dev_priv->rps.min_freq);
5295
aed242ff
CW		 5296 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5297
4e80519e
ID		 5298 /* Preserve min/max settings in case of re-init */
5299 if (dev_priv->rps.max_freq_softlimit == 0)
5300 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5301
5302 if (dev_priv->rps.min_freq_softlimit == 0)
5303 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5304
5305 mutex_unlock(&dev_priv->rps.hw_lock);
5306}
5307
38807746
D		 5308static void cherryview_init_gt_powersave(struct drm_device *dev)
5309{
2b6b3a09 5310 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5311 u32 val;
2b6b3a09 5312
38807746 5313 cherryview_setup_pctx(dev);
2b6b3a09
D		 5314
5315 mutex_lock(&dev_priv->rps.hw_lock);
5316
a580516d 5317 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5318 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5319 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5320
2bb25c17 5321 switch ((val >> 2) & 0x7) {
2bb25c17 5322 case 3:
2bb25c17
VS		 5323 dev_priv->mem_freq = 2000;
5324 break;
bfa7df01 5325 default:
2bb25c17
VS		 5326 dev_priv->mem_freq = 1600;
5327 break;
5328 }
80b83b62 5329 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5330
2b6b3a09
D		 5331 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5332 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5333 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5334 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5335 dev_priv->rps.max_freq);
5336
5337 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5338 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5339 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5340 dev_priv->rps.efficient_freq);
5341
7707df4a
D		 5342 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5343 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5344 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5345 dev_priv->rps.rp1_freq);
5346
5b7c91b7
D		 5347 /* PUnit validated range is only [RPe, RP0] */
5348 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5349 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5350 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5351 dev_priv->rps.min_freq);
5352
1c14762d
VS		 5353 WARN_ONCE((dev_priv->rps.max_freq |
5354 dev_priv->rps.efficient_freq |
5355 dev_priv->rps.rp1_freq |
5356 dev_priv->rps.min_freq) & 1,
5357 "Odd GPU freq values\n");
5358
aed242ff
CW		 5359 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5360
2b6b3a09
D		 5361 /* Preserve min/max settings in case of re-init */
5362 if (dev_priv->rps.max_freq_softlimit == 0)
5363 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5364
5365 if (dev_priv->rps.min_freq_softlimit == 0)
5366 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5367
5368 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5369}
5370
4e80519e
ID		 5371static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5372{
5373 valleyview_cleanup_pctx(dev);
5374}
5375
38807746
D		 5376static void cherryview_enable_rps(struct drm_device *dev)
5377{
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379 struct intel_engine_cs *ring;
2b6b3a09 5380 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5381 int i;
5382
5383 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5384
5385 gtfifodbg = I915_READ(GTFIFODBG);
5386 if (gtfifodbg) {
5387 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5388 gtfifodbg);
5389 I915_WRITE(GTFIFODBG, gtfifodbg);
5390 }
5391
5392 cherryview_check_pctx(dev_priv);
5393
5394 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5395 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5396 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5397
160614a2
VS		 5398 /* Disable RC states. */
5399 I915_WRITE(GEN6_RC_CONTROL, 0);
5400
38807746
D		 5401 /* 2a: Program RC6 thresholds.*/
5402 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5403 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5404 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5405
5406 for_each_ring(ring, dev_priv, i)
5407 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5408 I915_WRITE(GEN6_RC_SLEEP, 0);
5409
f4f71c7d
D		 5410 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5411 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5412
5413 /* allows RC6 residency counter to work */
5414 I915_WRITE(VLV_COUNTER_CONTROL,
5415 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5416 VLV_MEDIA_RC6_COUNT_EN |
5417 VLV_RENDER_RC6_COUNT_EN));
5418
5419 /* For now we assume BIOS is allocating and populating the PCBR */
5420 pcbr = I915_READ(VLV_PCBR);
5421
38807746
D		 5422 /* 3: Enable RC6 */
5423 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5424 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5425 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5426
5427 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5428
2b6b3a09 5429 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5430 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5431 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5432 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5433 I915_WRITE(GEN6_RP_UP_EI, 66000);
5434 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5435
5436 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5437
5438 /* 5: Enable RPS */
5439 I915_WRITE(GEN6_RP_CONTROL,
5440 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5441 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5442 GEN6_RP_ENABLE |
5443 GEN6_RP_UP_BUSY_AVG |
5444 GEN6_RP_DOWN_IDLE_AVG);
5445
3ef62342
D		 5446 /* Setting Fixed Bias */
5447 val = VLV_OVERRIDE_EN |
5448 VLV_SOC_TDP_EN |
5449 CHV_BIAS_CPU_50_SOC_50;
5450 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5451
2b6b3a09
D		 5452 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5453
8d40c3ae
VS		 5454 /* RPS code assumes GPLL is used */
5455 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5456
742f491d 5457 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5458 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5459
5460 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5461 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5462 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5463 dev_priv->rps.cur_freq);
5464
5465 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5466 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5467 dev_priv->rps.efficient_freq);
5468
5469 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5470
59bad947 5471 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5472}
5473
0a073b84
JB		 5474static void valleyview_enable_rps(struct drm_device *dev)
5475{
5476 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5477 struct intel_engine_cs *ring;
2a5913a8 5478 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5479 int i;
5480
5481 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5482
ae48434c
ID		 5483 valleyview_check_pctx(dev_priv);
5484
0a073b84 5485 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5486 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5487 gtfifodbg);
0a073b84
JB		 5488 I915_WRITE(GTFIFODBG, gtfifodbg);
5489 }
5490
c8d9a590 5491 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5492 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5493
160614a2
VS		 5494 /* Disable RC states. */
5495 I915_WRITE(GEN6_RC_CONTROL, 0);
5496
cad725fe 5497 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5498 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5499 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5500 I915_WRITE(GEN6_RP_UP_EI, 66000);
5501 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5502
5503 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5504
5505 I915_WRITE(GEN6_RP_CONTROL,
5506 GEN6_RP_MEDIA_TURBO |
5507 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5508 GEN6_RP_MEDIA_IS_GFX |
5509 GEN6_RP_ENABLE |
5510 GEN6_RP_UP_BUSY_AVG |
5511 GEN6_RP_DOWN_IDLE_CONT);
5512
5513 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5514 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5515 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5516
5517 for_each_ring(ring, dev_priv, i)
5518 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5519
2f0aa304 5520 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5521
5522 /* allows RC6 residency counter to work */
49798eb2 5523 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5524 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5525 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5526 VLV_MEDIA_RC6_COUNT_EN |
5527 VLV_RENDER_RC6_COUNT_EN));
31685c25 5528
a2b23fe0 5529 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5530 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5531
5532 intel_print_rc6_info(dev, rc6_mode);
5533
a2b23fe0 5534 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5535
3ef62342
D		 5536 /* Setting Fixed Bias */
5537 val = VLV_OVERRIDE_EN |
5538 VLV_SOC_TDP_EN |
5539 VLV_BIAS_CPU_125_SOC_875;
5540 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5541
64936258 5542 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5543
8d40c3ae
VS		 5544 /* RPS code assumes GPLL is used */
5545 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5546
742f491d 5547 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5548 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5549
b39fb297 5550 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5551 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5552 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5553 dev_priv->rps.cur_freq);
0a073b84 5554
73008b98 5555 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5556 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5557 dev_priv->rps.efficient_freq);
0a073b84 5558
b39fb297 5559 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5560
59bad947 5561 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5562}
5563
dde18883
ED		 5564static unsigned long intel_pxfreq(u32 vidfreq)
5565{
5566 unsigned long freq;
5567 int div = (vidfreq & 0x3f0000) >> 16;
5568 int post = (vidfreq & 0x3000) >> 12;
5569 int pre = (vidfreq & 0x7);
5570
5571 if (!pre)
5572 return 0;
5573
5574 freq = ((div * 133333) / ((1<<post) * pre));
5575
5576 return freq;
5577}
5578
eb48eb00
DV		 5579static const struct cparams {
5580 u16 i;
5581 u16 t;
5582 u16 m;
5583 u16 c;
5584} cparams[] = {
5585 { 1, 1333, 301, 28664 },
5586 { 1, 1066, 294, 24460 },
5587 { 1, 800, 294, 25192 },
5588 { 0, 1333, 276, 27605 },
5589 { 0, 1066, 276, 27605 },
5590 { 0, 800, 231, 23784 },
5591};
5592
f531dcb2 5593static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5594{
5595 u64 total_count, diff, ret;
5596 u32 count1, count2, count3, m = 0, c = 0;
5597 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5598 int i;
5599
02d71956
DV		 5600 assert_spin_locked(&mchdev_lock);
5601
20e4d407 5602 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5603
5604 /* Prevent division-by-zero if we are asking too fast.
5605 * Also, we don't get interesting results if we are polling
5606 * faster than once in 10ms, so just return the saved value
5607 * in such cases.
5608 */
5609 if (diff1 <= 10)
20e4d407 5610 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5611
5612 count1 = I915_READ(DMIEC);
5613 count2 = I915_READ(DDREC);
5614 count3 = I915_READ(CSIEC);
5615
5616 total_count = count1 + count2 + count3;
5617
5618 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5619 if (total_count < dev_priv->ips.last_count1) {
5620 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5621 diff += total_count;
5622 } else {
20e4d407 5623 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5624 }
5625
5626 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5627 if (cparams[i].i == dev_priv->ips.c_m &&
5628 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5629 m = cparams[i].m;
5630 c = cparams[i].c;
5631 break;
5632 }
5633 }
5634
5635 diff = div_u64(diff, diff1);
5636 ret = ((m * diff) + c);
5637 ret = div_u64(ret, 10);
5638
20e4d407
DV		 5639 dev_priv->ips.last_count1 = total_count;
5640 dev_priv->ips.last_time1 = now;
eb48eb00 5641
20e4d407 5642 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5643
5644 return ret;
5645}
5646
f531dcb2
CW		 5647unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5648{
3d13ef2e 5649 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5650 unsigned long val;
5651
3d13ef2e 5652 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5653 return 0;
5654
5655 spin_lock_irq(&mchdev_lock);
5656
5657 val = __i915_chipset_val(dev_priv);
5658
5659 spin_unlock_irq(&mchdev_lock);
5660
5661 return val;
5662}
5663
eb48eb00
DV		 5664unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5665{
5666 unsigned long m, x, b;
5667 u32 tsfs;
5668
5669 tsfs = I915_READ(TSFS);
5670
5671 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5672 x = I915_READ8(TR1);
5673
5674 b = tsfs & TSFS_INTR_MASK;
5675
5676 return ((m * x) / 127) - b;
5677}
5678
d972d6ee
MK		 5679static int _pxvid_to_vd(u8 pxvid)
5680{
5681 if (pxvid == 0)
5682 return 0;
5683
5684 if (pxvid >= 8 && pxvid < 31)
5685 pxvid = 31;
5686
5687 return (pxvid + 2) * 125;
5688}
5689
5690static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5691{
3d13ef2e 5692 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5693 const int vd = _pxvid_to_vd(pxvid);
5694 const int vm = vd - 1125;
5695
3d13ef2e 5696 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5697 return vm > 0 ? vm : 0;
5698
5699 return vd;
eb48eb00
DV		 5700}
5701
02d71956 5702static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5703{
5ed0bdf2 5704 u64 now, diff, diffms;
eb48eb00
DV		 5705 u32 count;
5706
02d71956 5707 assert_spin_locked(&mchdev_lock);
eb48eb00 5708
5ed0bdf2
TG		 5709 now = ktime_get_raw_ns();
5710 diffms = now - dev_priv->ips.last_time2;
5711 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5712
5713 /* Don't divide by 0 */
eb48eb00
DV		 5714 if (!diffms)
5715 return;
5716
5717 count = I915_READ(GFXEC);
5718
20e4d407
DV		 5719 if (count < dev_priv->ips.last_count2) {
5720 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5721 diff += count;
5722 } else {
20e4d407 5723 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5724 }
5725
20e4d407
DV		 5726 dev_priv->ips.last_count2 = count;
5727 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5728
5729 /* More magic constants... */
5730 diff = diff * 1181;
5731 diff = div_u64(diff, diffms * 10);
20e4d407 5732 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5733}
5734
02d71956
DV		 5735void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5736{
3d13ef2e
DL		 5737 struct drm_device *dev = dev_priv->dev;
5738
5739 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5740 return;
5741
9270388e 5742 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5743
5744 __i915_update_gfx_val(dev_priv);
5745
9270388e 5746 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5747}
5748
f531dcb2 5749static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5750{
5751 unsigned long t, corr, state1, corr2, state2;
5752 u32 pxvid, ext_v;
5753
02d71956
DV		 5754 assert_spin_locked(&mchdev_lock);
5755
616847e7 5756 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5757 pxvid = (pxvid >> 24) & 0x7f;
5758 ext_v = pvid_to_extvid(dev_priv, pxvid);
5759
5760 state1 = ext_v;
5761
5762 t = i915_mch_val(dev_priv);
5763
5764 /* Revel in the empirically derived constants */
5765
5766 /* Correction factor in 1/100000 units */
5767 if (t > 80)
5768 corr = ((t * 2349) + 135940);
5769 else if (t >= 50)
5770 corr = ((t * 964) + 29317);
5771 else /* < 50 */
5772 corr = ((t * 301) + 1004);
5773
5774 corr = corr * ((150142 * state1) / 10000 - 78642);
5775 corr /= 100000;
20e4d407 5776 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5777
5778 state2 = (corr2 * state1) / 10000;
5779 state2 /= 100; /* convert to mW */
5780
02d71956 5781 __i915_update_gfx_val(dev_priv);
eb48eb00 5782
20e4d407 5783 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5784}
5785
f531dcb2
CW		 5786unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5787{
3d13ef2e 5788 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5789 unsigned long val;
5790
3d13ef2e 5791 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5792 return 0;
5793
5794 spin_lock_irq(&mchdev_lock);
5795
5796 val = __i915_gfx_val(dev_priv);
5797
5798 spin_unlock_irq(&mchdev_lock);
5799
5800 return val;
5801}
5802
eb48eb00
DV		 5803/**
5804 * i915_read_mch_val - return value for IPS use
5805 *
5806 * Calculate and return a value for the IPS driver to use when deciding whether
5807 * we have thermal and power headroom to increase CPU or GPU power budget.
5808 */
5809unsigned long i915_read_mch_val(void)
5810{
5811 struct drm_i915_private *dev_priv;
5812 unsigned long chipset_val, graphics_val, ret = 0;
5813
9270388e 5814 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5815 if (!i915_mch_dev)
5816 goto out_unlock;
5817 dev_priv = i915_mch_dev;
5818
f531dcb2
CW		 5819 chipset_val = __i915_chipset_val(dev_priv);
5820 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5821
5822 ret = chipset_val + graphics_val;
5823
5824out_unlock:
9270388e 5825 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5826
5827 return ret;
5828}
5829EXPORT_SYMBOL_GPL(i915_read_mch_val);
5830
5831/**
5832 * i915_gpu_raise - raise GPU frequency limit
5833 *
5834 * Raise the limit; IPS indicates we have thermal headroom.
5835 */
5836bool i915_gpu_raise(void)
5837{
5838 struct drm_i915_private *dev_priv;
5839 bool ret = true;
5840
9270388e 5841 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5842 if (!i915_mch_dev) {
5843 ret = false;
5844 goto out_unlock;
5845 }
5846 dev_priv = i915_mch_dev;
5847
20e4d407
DV		 5848 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5849 dev_priv->ips.max_delay--;
eb48eb00
DV		 5850
5851out_unlock:
9270388e 5852 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5853
5854 return ret;
5855}
5856EXPORT_SYMBOL_GPL(i915_gpu_raise);
5857
5858/**
5859 * i915_gpu_lower - lower GPU frequency limit
5860 *
5861 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5862 * frequency maximum.
5863 */
5864bool i915_gpu_lower(void)
5865{
5866 struct drm_i915_private *dev_priv;
5867 bool ret = true;
5868
9270388e 5869 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5870 if (!i915_mch_dev) {
5871 ret = false;
5872 goto out_unlock;
5873 }
5874 dev_priv = i915_mch_dev;
5875
20e4d407
DV		 5876 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5877 dev_priv->ips.max_delay++;
eb48eb00
DV		 5878
5879out_unlock:
9270388e 5880 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5881
5882 return ret;
5883}
5884EXPORT_SYMBOL_GPL(i915_gpu_lower);
5885
5886/**
5887 * i915_gpu_busy - indicate GPU business to IPS
5888 *
5889 * Tell the IPS driver whether or not the GPU is busy.
5890 */
5891bool i915_gpu_busy(void)
5892{
5893 struct drm_i915_private *dev_priv;
a4872ba6 5894 struct intel_engine_cs *ring;
eb48eb00 5895 bool ret = false;
f047e395 5896 int i;
eb48eb00 5897
9270388e 5898 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5899 if (!i915_mch_dev)
5900 goto out_unlock;
5901 dev_priv = i915_mch_dev;
5902
f047e395
CW		 5903 for_each_ring(ring, dev_priv, i)
5904 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5905
5906out_unlock:
9270388e 5907 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5908
5909 return ret;
5910}
5911EXPORT_SYMBOL_GPL(i915_gpu_busy);
5912
5913/**
5914 * i915_gpu_turbo_disable - disable graphics turbo
5915 *
5916 * Disable graphics turbo by resetting the max frequency and setting the
5917 * current frequency to the default.
5918 */
5919bool i915_gpu_turbo_disable(void)
5920{
5921 struct drm_i915_private *dev_priv;
5922 bool ret = true;
5923
9270388e 5924 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5925 if (!i915_mch_dev) {
5926 ret = false;
5927 goto out_unlock;
5928 }
5929 dev_priv = i915_mch_dev;
5930
20e4d407 5931 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5932
20e4d407 5933 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5934 ret = false;
5935
5936out_unlock:
9270388e 5937 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5938
5939 return ret;
5940}
5941EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5942
5943/**
5944 * Tells the intel_ips driver that the i915 driver is now loaded, if
5945 * IPS got loaded first.
5946 *
5947 * This awkward dance is so that neither module has to depend on the
5948 * other in order for IPS to do the appropriate communication of
5949 * GPU turbo limits to i915.
5950 */
5951static void
5952ips_ping_for_i915_load(void)
5953{
5954 void (*link)(void);
5955
5956 link = symbol_get(ips_link_to_i915_driver);
5957 if (link) {
5958 link();
5959 symbol_put(ips_link_to_i915_driver);
5960 }
5961}
5962
5963void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5964{
02d71956
DV		 5965 /* We only register the i915 ips part with intel-ips once everything is
5966 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5967 spin_lock_irq(&mchdev_lock);
eb48eb00 5968 i915_mch_dev = dev_priv;
9270388e 5969 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5970
5971 ips_ping_for_i915_load();
5972}
5973
5974void intel_gpu_ips_teardown(void)
5975{
9270388e 5976 spin_lock_irq(&mchdev_lock);
eb48eb00 5977 i915_mch_dev = NULL;
9270388e 5978 spin_unlock_irq(&mchdev_lock);
eb48eb00 5979}
76c3552f 5980
8090c6b9 5981static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5982{
5983 struct drm_i915_private *dev_priv = dev->dev_private;
5984 u32 lcfuse;
5985 u8 pxw[16];
5986 int i;
5987
5988 /* Disable to program */
5989 I915_WRITE(ECR, 0);
5990 POSTING_READ(ECR);
5991
5992 /* Program energy weights for various events */
5993 I915_WRITE(SDEW, 0x15040d00);
5994 I915_WRITE(CSIEW0, 0x007f0000);
5995 I915_WRITE(CSIEW1, 0x1e220004);
5996 I915_WRITE(CSIEW2, 0x04000004);
5997
5998 for (i = 0; i < 5; i++)
616847e7 5999 I915_WRITE(PEW(i), 0);
dde18883 6000 for (i = 0; i < 3; i++)
616847e7 6001 I915_WRITE(DEW(i), 0);
dde18883
ED		 6002
6003 /* Program P-state weights to account for frequency power adjustment */
6004 for (i = 0; i < 16; i++) {
616847e7 6005 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6006 unsigned long freq = intel_pxfreq(pxvidfreq);
6007 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6008 PXVFREQ_PX_SHIFT;
6009 unsigned long val;
6010
6011 val = vid * vid;
6012 val *= (freq / 1000);
6013 val *= 255;
6014 val /= (127*127*900);
6015 if (val > 0xff)
6016 DRM_ERROR("bad pxval: %ld\n", val);
6017 pxw[i] = val;
6018 }
6019 /* Render standby states get 0 weight */
6020 pxw[14] = 0;
6021 pxw[15] = 0;
6022
6023 for (i = 0; i < 4; i++) {
6024 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6025 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6026 I915_WRITE(PXW(i), val);
dde18883
ED		 6027 }
6028
6029 /* Adjust magic regs to magic values (more experimental results) */
6030 I915_WRITE(OGW0, 0);
6031 I915_WRITE(OGW1, 0);
6032 I915_WRITE(EG0, 0x00007f00);
6033 I915_WRITE(EG1, 0x0000000e);
6034 I915_WRITE(EG2, 0x000e0000);
6035 I915_WRITE(EG3, 0x68000300);
6036 I915_WRITE(EG4, 0x42000000);
6037 I915_WRITE(EG5, 0x00140031);
6038 I915_WRITE(EG6, 0);
6039 I915_WRITE(EG7, 0);
6040
6041 for (i = 0; i < 8; i++)
616847e7 6042 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6043
6044 /* Enable PMON + select events */
6045 I915_WRITE(ECR, 0x80000019);
6046
6047 lcfuse = I915_READ(LCFUSE02);
6048
20e4d407 6049 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6050}
6051
ae48434c
ID		 6052void intel_init_gt_powersave(struct drm_device *dev)
6053{
b268c699
ID		 6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055
e6069ca8 6056 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
b268c699
ID		 6057 /*
6058 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6059 * requirement.
6060 */
6061 if (!i915.enable_rc6) {
6062 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6063 intel_runtime_pm_get(dev_priv);
6064 }
e6069ca8 6065
38807746
D		 6066 if (IS_CHERRYVIEW(dev))
6067 cherryview_init_gt_powersave(dev);
6068 else if (IS_VALLEYVIEW(dev))
4e80519e 6069 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6070}
6071
6072void intel_cleanup_gt_powersave(struct drm_device *dev)
6073{
b268c699
ID		 6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075
38807746
D		 6076 if (IS_CHERRYVIEW(dev))
6077 return;
6078 else if (IS_VALLEYVIEW(dev))
4e80519e 6079 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6080
6081 if (!i915.enable_rc6)
6082 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6083}
6084
dbea3cea
ID		 6085static void gen6_suspend_rps(struct drm_device *dev)
6086{
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088
6089 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6090
4c2a8897 6091 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6092}
6093
156c7ca0
JB		 6094/**
6095 * intel_suspend_gt_powersave - suspend PM work and helper threads
6096 * @dev: drm device
6097 *
6098 * We don't want to disable RC6 or other features here, we just want
6099 * to make sure any work we've queued has finished and won't bother
6100 * us while we're suspended.
6101 */
6102void intel_suspend_gt_powersave(struct drm_device *dev)
6103{
6104 struct drm_i915_private *dev_priv = dev->dev_private;
6105
d4d70aa5
ID		 6106 if (INTEL_INFO(dev)->gen < 6)
6107 return;
6108
dbea3cea 6109 gen6_suspend_rps(dev);
b47adc17
D		 6110
6111 /* Force GPU to min freq during suspend */
6112 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6113}
6114
8090c6b9
DV		 6115void intel_disable_gt_powersave(struct drm_device *dev)
6116{
1a01ab3b
JB		 6117 struct drm_i915_private *dev_priv = dev->dev_private;
6118
930ebb46 6119 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6120 ironlake_disable_drps(dev);
38807746 6121 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6122 intel_suspend_gt_powersave(dev);
e494837a 6123
4fc688ce 6124 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6125 if (INTEL_INFO(dev)->gen >= 9)
6126 gen9_disable_rps(dev);
6127 else if (IS_CHERRYVIEW(dev))
38807746
D		 6128 cherryview_disable_rps(dev);
6129 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6130 valleyview_disable_rps(dev);
6131 else
6132 gen6_disable_rps(dev);
e534770a 6133
c0951f0c 6134 dev_priv->rps.enabled = false;
4fc688ce 6135 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6136 }
8090c6b9
DV		 6137}
6138
1a01ab3b
JB		 6139static void intel_gen6_powersave_work(struct work_struct *work)
6140{
6141 struct drm_i915_private *dev_priv =
6142 container_of(work, struct drm_i915_private,
6143 rps.delayed_resume_work.work);
6144 struct drm_device *dev = dev_priv->dev;
6145
4fc688ce 6146 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6147
4c2a8897 6148 gen6_reset_rps_interrupts(dev);
3cc134e3 6149
38807746
D		 6150 if (IS_CHERRYVIEW(dev)) {
6151 cherryview_enable_rps(dev);
6152 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6153 valleyview_enable_rps(dev);
20e49366 6154 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6155 gen9_enable_rc6(dev);
20e49366 6156 gen9_enable_rps(dev);
ef11bdb3 6157 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6158 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6159 } else if (IS_BROADWELL(dev)) {
6160 gen8_enable_rps(dev);
c2bc2fc5 6161 __gen6_update_ring_freq(dev);
0a073b84
JB		 6162 } else {
6163 gen6_enable_rps(dev);
c2bc2fc5 6164 __gen6_update_ring_freq(dev);
0a073b84 6165 }
aed242ff
CW		 6166
6167 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6168 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6169
6170 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6171 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6172
c0951f0c 6173 dev_priv->rps.enabled = true;
3cc134e3 6174
4c2a8897 6175 gen6_enable_rps_interrupts(dev);
3cc134e3 6176
4fc688ce 6177 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6178
6179 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6180}
6181
8090c6b9
DV		 6182void intel_enable_gt_powersave(struct drm_device *dev)
6183{
1a01ab3b
JB		 6184 struct drm_i915_private *dev_priv = dev->dev_private;
6185
f61018b1
YZ		 6186 /* Powersaving is controlled by the host when inside a VM */
6187 if (intel_vgpu_active(dev))
6188 return;
6189
8090c6b9 6190 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6191 mutex_lock(&dev->struct_mutex);
8090c6b9 6192 ironlake_enable_drps(dev);
8090c6b9 6193 intel_init_emon(dev);
dc1d0136 6194 mutex_unlock(&dev->struct_mutex);
38807746 6195 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6196 /*
6197 * PCU communication is slow and this doesn't need to be
6198 * done at any specific time, so do this out of our fast path
6199 * to make resume and init faster.
c6df39b5
ID		 6200 *
6201 * We depend on the HW RC6 power context save/restore
6202 * mechanism when entering D3 through runtime PM suspend. So
6203 * disable RPM until RPS/RC6 is properly setup. We can only
6204 * get here via the driver load/system resume/runtime resume
6205 * paths, so the _noresume version is enough (and in case of
6206 * runtime resume it's necessary).
1a01ab3b 6207 */
c6df39b5
ID		 6208 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6209 round_jiffies_up_relative(HZ)))
6210 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6211 }
6212}
6213
c6df39b5
ID		 6214void intel_reset_gt_powersave(struct drm_device *dev)
6215{
6216 struct drm_i915_private *dev_priv = dev->dev_private;
6217
dbea3cea
ID		 6218 if (INTEL_INFO(dev)->gen < 6)
6219 return;
6220
6221 gen6_suspend_rps(dev);
c6df39b5 6222 dev_priv->rps.enabled = false;
c6df39b5
ID		 6223}
6224
3107bd48
DV		 6225static void ibx_init_clock_gating(struct drm_device *dev)
6226{
6227 struct drm_i915_private *dev_priv = dev->dev_private;
6228
6229 /*
6230 * On Ibex Peak and Cougar Point, we need to disable clock
6231 * gating for the panel power sequencer or it will fail to
6232 * start up when no ports are active.
6233 */
6234 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6235}
6236
0e088b8f
VS		 6237static void g4x_disable_trickle_feed(struct drm_device *dev)
6238{
6239 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6240 enum pipe pipe;
0e088b8f 6241
055e393f 6242 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6243 I915_WRITE(DSPCNTR(pipe),
6244 I915_READ(DSPCNTR(pipe)) |
6245 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6246
6247 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6248 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6249 }
6250}
6251
017636cc
VS		 6252static void ilk_init_lp_watermarks(struct drm_device *dev)
6253{
6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255
6256 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6257 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6258 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6259
6260 /*
6261 * Don't touch WM1S_LP_EN here.
6262 * Doing so could cause underruns.
6263 */
6264}
6265
1fa61106 6266static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6267{
6268 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6269 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6270
f1e8fa56
DL		 6271 /*
6272 * Required for FBC
6273 * WaFbcDisableDpfcClockGating:ilk
6274 */
4d47e4f5
DL		 6275 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6276 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6277 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6278
6279 I915_WRITE(PCH_3DCGDIS0,
6280 MARIUNIT_CLOCK_GATE_DISABLE |
6281 SVSMUNIT_CLOCK_GATE_DISABLE);
6282 I915_WRITE(PCH_3DCGDIS1,
6283 VFMUNIT_CLOCK_GATE_DISABLE);
6284
6f1d69b0
ED		 6285 /*
6286 * According to the spec the following bits should be set in
6287 * order to enable memory self-refresh
6288 * The bit 22/21 of 0x42004
6289 * The bit 5 of 0x42020
6290 * The bit 15 of 0x45000
6291 */
6292 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6293 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6294 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6295 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6296 I915_WRITE(DISP_ARB_CTL,
6297 (I915_READ(DISP_ARB_CTL) |
6298 DISP_FBC_WM_DIS));
017636cc
VS		 6299
6300 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6301
6302 /*
6303 * Based on the document from hardware guys the following bits
6304 * should be set unconditionally in order to enable FBC.
6305 * The bit 22 of 0x42000
6306 * The bit 22 of 0x42004
6307 * The bit 7,8,9 of 0x42020.
6308 */
6309 if (IS_IRONLAKE_M(dev)) {
4bb35334 6310 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6311 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6312 I915_READ(ILK_DISPLAY_CHICKEN1) |
6313 ILK_FBCQ_DIS);
6314 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6315 I915_READ(ILK_DISPLAY_CHICKEN2) |
6316 ILK_DPARB_GATE);
6f1d69b0
ED		 6317 }
6318
4d47e4f5
DL		 6319 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6320
6f1d69b0
ED		 6321 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6322 I915_READ(ILK_DISPLAY_CHICKEN2) |
6323 ILK_ELPIN_409_SELECT);
6324 I915_WRITE(_3D_CHICKEN2,
6325 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6326 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6327
ecdb4eb7 6328 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6329 I915_WRITE(CACHE_MODE_0,
6330 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6331
4e04632e
AG		 6332 /* WaDisable_RenderCache_OperationalFlush:ilk */
6333 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6334
0e088b8f 6335 g4x_disable_trickle_feed(dev);
bdad2b2f 6336
3107bd48
DV		 6337 ibx_init_clock_gating(dev);
6338}
6339
6340static void cpt_init_clock_gating(struct drm_device *dev)
6341{
6342 struct drm_i915_private *dev_priv = dev->dev_private;
6343 int pipe;
3f704fa2 6344 uint32_t val;
3107bd48
DV		 6345
6346 /*
6347 * On Ibex Peak and Cougar Point, we need to disable clock
6348 * gating for the panel power sequencer or it will fail to
6349 * start up when no ports are active.
6350 */
cd664078
JB		 6351 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6352 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6353 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6354 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6355 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6356 /* The below fixes the weird display corruption, a few pixels shifted
6357 * downward, on (only) LVDS of some HP laptops with IVY.
6358 */
055e393f 6359 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6360 val = I915_READ(TRANS_CHICKEN2(pipe));
6361 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6362 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6363 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6364 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6365 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6366 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6367 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6368 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6369 }
3107bd48 6370 /* WADP0ClockGatingDisable */
055e393f 6371 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6372 I915_WRITE(TRANS_CHICKEN1(pipe),
6373 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6374 }
6f1d69b0
ED		 6375}
6376
1d7aaa0c
DV		 6377static void gen6_check_mch_setup(struct drm_device *dev)
6378{
6379 struct drm_i915_private *dev_priv = dev->dev_private;
6380 uint32_t tmp;
6381
6382 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6383 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6384 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6385 tmp);
1d7aaa0c
DV		 6386}
6387
1fa61106 6388static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6389{
6390 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6391 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6392
231e54f6 6393 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6394
6395 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6396 I915_READ(ILK_DISPLAY_CHICKEN2) |
6397 ILK_ELPIN_409_SELECT);
6398
ecdb4eb7 6399 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6400 I915_WRITE(_3D_CHICKEN,
6401 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6402
4e04632e
AG		 6403 /* WaDisable_RenderCache_OperationalFlush:snb */
6404 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6405
8d85d272
VS		 6406 /*
6407 * BSpec recoomends 8x4 when MSAA is used,
6408 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6409 *
6410 * Note that PS/WM thread counts depend on the WIZ hashing
6411 * disable bit, which we don't touch here, but it's good
6412 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6413 */
6414 I915_WRITE(GEN6_GT_MODE,
98533251 6415 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6416
017636cc 6417 ilk_init_lp_watermarks(dev);
6f1d69b0 6418
6f1d69b0 6419 I915_WRITE(CACHE_MODE_0,
50743298 6420 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6421
6422 I915_WRITE(GEN6_UCGCTL1,
6423 I915_READ(GEN6_UCGCTL1) |
6424 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6425 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6426
6427 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6428 * gating disable must be set. Failure to set it results in
6429 * flickering pixels due to Z write ordering failures after
6430 * some amount of runtime in the Mesa "fire" demo, and Unigine
6431 * Sanctuary and Tropics, and apparently anything else with
6432 * alpha test or pixel discard.
6433 *
6434 * According to the spec, bit 11 (RCCUNIT) must also be set,
6435 * but we didn't debug actual testcases to find it out.
0f846f81 6436 *
ef59318c
VS		 6437 * WaDisableRCCUnitClockGating:snb
6438 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6439 */
6440 I915_WRITE(GEN6_UCGCTL2,
6441 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6442 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6443
5eb146dd 6444 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6445 I915_WRITE(_3D_CHICKEN3,
6446 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6447
e927ecde
VS		 6448 /*
6449 * Bspec says:
6450 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6451 * 3DSTATE_SF number of SF output attributes is more than 16."
6452 */
6453 I915_WRITE(_3D_CHICKEN3,
6454 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6455
6f1d69b0
ED		 6456 /*
6457 * According to the spec the following bits should be
6458 * set in order to enable memory self-refresh and fbc:
6459 * The bit21 and bit22 of 0x42000
6460 * The bit21 and bit22 of 0x42004
6461 * The bit5 and bit7 of 0x42020
6462 * The bit14 of 0x70180
6463 * The bit14 of 0x71180
4bb35334
DL		 6464 *
6465 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6466 */
6467 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6468 I915_READ(ILK_DISPLAY_CHICKEN1) |
6469 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6470 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6471 I915_READ(ILK_DISPLAY_CHICKEN2) |
6472 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6473 I915_WRITE(ILK_DSPCLK_GATE_D,
6474 I915_READ(ILK_DSPCLK_GATE_D) |
6475 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6476 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6477
0e088b8f 6478 g4x_disable_trickle_feed(dev);
f8f2ac9a 6479
3107bd48 6480 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6481
6482 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6483}
6484
6485static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6486{
6487 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6488
3aad9059 6489 /*
46680e0a 6490 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6491 *
6492 * This actually overrides the dispatch
6493 * mode for all thread types.
6494 */
6f1d69b0
ED		 6495 reg &= ~GEN7_FF_SCHED_MASK;
6496 reg |= GEN7_FF_TS_SCHED_HW;
6497 reg |= GEN7_FF_VS_SCHED_HW;
6498 reg |= GEN7_FF_DS_SCHED_HW;
6499
6500 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6501}
6502
17a303ec
PZ		 6503static void lpt_init_clock_gating(struct drm_device *dev)
6504{
6505 struct drm_i915_private *dev_priv = dev->dev_private;
6506
6507 /*
6508 * TODO: this bit should only be enabled when really needed, then
6509 * disabled when not needed anymore in order to save power.
6510 */
c2699524 6511 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6512 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6513 I915_READ(SOUTH_DSPCLK_GATE_D) |
6514 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6515
6516 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6517 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6518 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6519 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6520}
6521
7d708ee4
ID		 6522static void lpt_suspend_hw(struct drm_device *dev)
6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525
c2699524 6526 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6527 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6528
6529 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6530 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6531 }
6532}
6533
47c2bd97 6534static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6535{
6536 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6537 enum pipe pipe;
4d487cff 6538 uint32_t misccpctl;
1020a5c2 6539
7ad0dbab 6540 ilk_init_lp_watermarks(dev);
50ed5fbd 6541
ab57fff1 6542 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6543 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6544
ab57fff1 6545 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6546 I915_WRITE(CHICKEN_PAR1_1,
6547 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6548
ab57fff1 6549 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6550 for_each_pipe(dev_priv, pipe) {
07d27e20 6551 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6552 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6553 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6554 }
63801f21 6555
ab57fff1
BW		 6556 /* WaVSRefCountFullforceMissDisable:bdw */
6557 /* WaDSRefCountFullforceMissDisable:bdw */
6558 I915_WRITE(GEN7_FF_THREAD_MODE,
6559 I915_READ(GEN7_FF_THREAD_MODE) &
6560 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6561
295e8bb7
VS		 6562 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6563 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6564
6565 /* WaDisableSDEUnitClockGating:bdw */
6566 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6567 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6568
4d487cff
VS		 6569 /*
6570 * WaProgramL3SqcReg1Default:bdw
6571 * WaTempDisableDOPClkGating:bdw
6572 */
6573 misccpctl = I915_READ(GEN7_MISCCPCTL);
6574 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6575 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6576 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6577
6d50b065
VS		 6578 /*
6579 * WaGttCachingOffByDefault:bdw
6580 * GTT cache may not work with big pages, so if those
6581 * are ever enabled GTT cache may need to be disabled.
6582 */
6583 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6584
89d6b2b8 6585 lpt_init_clock_gating(dev);
1020a5c2
BW		 6586}
6587
cad2a2d7
ED		 6588static void haswell_init_clock_gating(struct drm_device *dev)
6589{
6590 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6591
017636cc 6592 ilk_init_lp_watermarks(dev);
cad2a2d7 6593
f3fc4884
FJ		 6594 /* L3 caching of data atomics doesn't work -- disable it. */
6595 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6596 I915_WRITE(HSW_ROW_CHICKEN3,
6597 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6598
ecdb4eb7 6599 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6600 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6601 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6602 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6603
e36ea7ff
VS		 6604 /* WaVSRefCountFullforceMissDisable:hsw */
6605 I915_WRITE(GEN7_FF_THREAD_MODE,
6606 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6607
4e04632e
AG		 6608 /* WaDisable_RenderCache_OperationalFlush:hsw */
6609 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6610
fe27c606
CW		 6611 /* enable HiZ Raw Stall Optimization */
6612 I915_WRITE(CACHE_MODE_0_GEN7,
6613 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6614
ecdb4eb7 6615 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6616 I915_WRITE(CACHE_MODE_1,
6617 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6618
a12c4967
VS		 6619 /*
6620 * BSpec recommends 8x4 when MSAA is used,
6621 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6622 *
6623 * Note that PS/WM thread counts depend on the WIZ hashing
6624 * disable bit, which we don't touch here, but it's good
6625 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6626 */
6627 I915_WRITE(GEN7_GT_MODE,
98533251 6628 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6629
94411593
KG		 6630 /* WaSampleCChickenBitEnable:hsw */
6631 I915_WRITE(HALF_SLICE_CHICKEN3,
6632 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6633
ecdb4eb7 6634 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6635 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6636
90a88643
PZ		 6637 /* WaRsPkgCStateDisplayPMReq:hsw */
6638 I915_WRITE(CHICKEN_PAR1_1,
6639 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6640
17a303ec 6641 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6642}
6643
1fa61106 6644static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6645{
6646 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6647 uint32_t snpcr;
6f1d69b0 6648
017636cc 6649 ilk_init_lp_watermarks(dev);
6f1d69b0 6650
231e54f6 6651 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6652
ecdb4eb7 6653 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6654 I915_WRITE(_3D_CHICKEN3,
6655 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6656
ecdb4eb7 6657 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6658 I915_WRITE(IVB_CHICKEN3,
6659 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6660 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6661
ecdb4eb7 6662 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6663 if (IS_IVB_GT1(dev))
6664 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6665 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6666
4e04632e
AG		 6667 /* WaDisable_RenderCache_OperationalFlush:ivb */
6668 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6669
ecdb4eb7 6670 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6671 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6672 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6673
ecdb4eb7 6674 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6675 I915_WRITE(GEN7_L3CNTLREG1,
6676 GEN7_WA_FOR_GEN7_L3_CONTROL);
6677 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6678 GEN7_WA_L3_CHICKEN_MODE);
6679 if (IS_IVB_GT1(dev))
6680 I915_WRITE(GEN7_ROW_CHICKEN2,
6681 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6682 else {
6683 /* must write both registers */
6684 I915_WRITE(GEN7_ROW_CHICKEN2,
6685 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6686 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6687 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6688 }
6f1d69b0 6689
ecdb4eb7 6690 /* WaForceL3Serialization:ivb */
61939d97
JB		 6691 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6692 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6693
1b80a19a 6694 /*
0f846f81 6695 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6696 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6697 */
6698 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6699 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6700
ecdb4eb7 6701 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6702 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6703 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6704 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6705
0e088b8f 6706 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6707
6708 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6709
22721343
CW		 6710 if (0) { /* causes HiZ corruption on ivb:gt1 */
6711 /* enable HiZ Raw Stall Optimization */
6712 I915_WRITE(CACHE_MODE_0_GEN7,
6713 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6714 }
116f2b6d 6715
ecdb4eb7 6716 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6717 I915_WRITE(CACHE_MODE_1,
6718 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6719
a607c1a4
VS		 6720 /*
6721 * BSpec recommends 8x4 when MSAA is used,
6722 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6723 *
6724 * Note that PS/WM thread counts depend on the WIZ hashing
6725 * disable bit, which we don't touch here, but it's good
6726 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6727 */
6728 I915_WRITE(GEN7_GT_MODE,
98533251 6729 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6730
20848223
BW		 6731 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6732 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6733 snpcr |= GEN6_MBC_SNPCR_MED;
6734 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6735
ab5c608b
BW		 6736 if (!HAS_PCH_NOP(dev))
6737 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6738
6739 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6740}
6741
c6beb13e
VS		 6742static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6743{
6744 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6745
6746 /*
6747 * Disable trickle feed and enable pnd deadline calculation
6748 */
6749 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6750 I915_WRITE(CBR1_VLV, 0);
6751}
6752
1fa61106 6753static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6754{
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6756
c6beb13e 6757 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6758
ecdb4eb7 6759 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6760 I915_WRITE(_3D_CHICKEN3,
6761 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6762
ecdb4eb7 6763 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6764 I915_WRITE(IVB_CHICKEN3,
6765 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6766 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6767
fad7d36e 6768 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6769 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6770 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6771 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6772 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6773
4e04632e
AG		 6774 /* WaDisable_RenderCache_OperationalFlush:vlv */
6775 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6776
ecdb4eb7 6777 /* WaForceL3Serialization:vlv */
61939d97
JB		 6778 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6779 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6780
ecdb4eb7 6781 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6782 I915_WRITE(GEN7_ROW_CHICKEN2,
6783 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6784
ecdb4eb7 6785 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6786 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6787 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6788 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6789
46680e0a
VS		 6790 gen7_setup_fixed_func_scheduler(dev_priv);
6791
3c0edaeb 6792 /*
0f846f81 6793 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6794 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6795 */
6796 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6797 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6798
c98f5062
AG		 6799 /* WaDisableL3Bank2xClockGate:vlv
6800 * Disabling L3 clock gating- MMIO 940c[25] = 1
6801 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6802 I915_WRITE(GEN7_UCGCTL4,
6803 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6804
afd58e79
VS		 6805 /*
6806 * BSpec says this must be set, even though
6807 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6808 */
6b26c86d
DV		 6809 I915_WRITE(CACHE_MODE_1,
6810 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6811
da2518f9
VS		 6812 /*
6813 * BSpec recommends 8x4 when MSAA is used,
6814 * however in practice 16x4 seems fastest.
6815 *
6816 * Note that PS/WM thread counts depend on the WIZ hashing
6817 * disable bit, which we don't touch here, but it's good
6818 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6819 */
6820 I915_WRITE(GEN7_GT_MODE,
6821 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6822
031994ee
VS		 6823 /*
6824 * WaIncreaseL3CreditsForVLVB0:vlv
6825 * This is the hardware default actually.
6826 */
6827 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6828
2d809570 6829 /*
ecdb4eb7 6830 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6831 * Disable clock gating on th GCFG unit to prevent a delay
6832 * in the reporting of vblank events.
6833 */
7a0d1eed 6834 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6835}
6836
a4565da8
VS		 6837static void cherryview_init_clock_gating(struct drm_device *dev)
6838{
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840
c6beb13e 6841 vlv_init_display_clock_gating(dev_priv);
dd811e70 6842
232ce337
VS		 6843 /* WaVSRefCountFullforceMissDisable:chv */
6844 /* WaDSRefCountFullforceMissDisable:chv */
6845 I915_WRITE(GEN7_FF_THREAD_MODE,
6846 I915_READ(GEN7_FF_THREAD_MODE) &
6847 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6848
6849 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6850 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6851 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6852
6853 /* WaDisableCSUnitClockGating:chv */
6854 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6855 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6856
6857 /* WaDisableSDEUnitClockGating:chv */
6858 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6859 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6860
6861 /*
6862 * GTT cache may not work with big pages, so if those
6863 * are ever enabled GTT cache may need to be disabled.
6864 */
6865 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6866}
6867
1fa61106 6868static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6869{
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 uint32_t dspclk_gate;
6872
6873 I915_WRITE(RENCLK_GATE_D1, 0);
6874 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6875 GS_UNIT_CLOCK_GATE_DISABLE |
6876 CL_UNIT_CLOCK_GATE_DISABLE);
6877 I915_WRITE(RAMCLK_GATE_D, 0);
6878 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6879 OVRUNIT_CLOCK_GATE_DISABLE |
6880 OVCUNIT_CLOCK_GATE_DISABLE;
6881 if (IS_GM45(dev))
6882 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6883 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6884
6885 /* WaDisableRenderCachePipelinedFlush */
6886 I915_WRITE(CACHE_MODE_0,
6887 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6888
4e04632e
AG		 6889 /* WaDisable_RenderCache_OperationalFlush:g4x */
6890 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6891
0e088b8f 6892 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6893}
6894
1fa61106 6895static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6896{
6897 struct drm_i915_private *dev_priv = dev->dev_private;
6898
6899 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6900 I915_WRITE(RENCLK_GATE_D2, 0);
6901 I915_WRITE(DSPCLK_GATE_D, 0);
6902 I915_WRITE(RAMCLK_GATE_D, 0);
6903 I915_WRITE16(DEUC, 0);
20f94967
VS		 6904 I915_WRITE(MI_ARB_STATE,
6905 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6906
6907 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6908 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6909}
6910
1fa61106 6911static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6912{
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914
6915 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6916 I965_RCC_CLOCK_GATE_DISABLE |
6917 I965_RCPB_CLOCK_GATE_DISABLE |
6918 I965_ISC_CLOCK_GATE_DISABLE |
6919 I965_FBC_CLOCK_GATE_DISABLE);
6920 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6921 I915_WRITE(MI_ARB_STATE,
6922 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6923
6924 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6925 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6926}
6927
1fa61106 6928static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6929{
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931 u32 dstate = I915_READ(D_STATE);
6932
6933 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6934 DSTATE_DOT_CLOCK_GATING;
6935 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6936
6937 if (IS_PINEVIEW(dev))
6938 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6939
6940 /* IIR "flip pending" means done if this bit is set */
6941 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6942
6943 /* interrupts should cause a wake up from C3 */
3299254f 6944 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6945
6946 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6947 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6948
6949 I915_WRITE(MI_ARB_STATE,
6950 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6951}
6952
1fa61106 6953static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6954{
6955 struct drm_i915_private *dev_priv = dev->dev_private;
6956
6957 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6958
6959 /* interrupts should cause a wake up from C3 */
6960 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6961 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6962
6963 I915_WRITE(MEM_MODE,
6964 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6965}
6966
1fa61106 6967static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6968{
6969 struct drm_i915_private *dev_priv = dev->dev_private;
6970
6971 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6972
6973 I915_WRITE(MEM_MODE,
6974 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6975 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6976}
6977
6f1d69b0
ED		 6978void intel_init_clock_gating(struct drm_device *dev)
6979{
6980 struct drm_i915_private *dev_priv = dev->dev_private;
6981
c57e3551
DL		 6982 if (dev_priv->display.init_clock_gating)
6983 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6984}
6985
7d708ee4
ID		 6986void intel_suspend_hw(struct drm_device *dev)
6987{
6988 if (HAS_PCH_LPT(dev))
6989 lpt_suspend_hw(dev);
6990}
6991
1fa61106
ED		 6992/* Set up chip specific power management-related functions */
6993void intel_init_pm(struct drm_device *dev)
6994{
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996
7ff0ebcc 6997 intel_fbc_init(dev_priv);
1fa61106 6998
c921aba8
DV		 6999 /* For cxsr */
7000 if (IS_PINEVIEW(dev))
7001 i915_pineview_get_mem_freq(dev);
7002 else if (IS_GEN5(dev))
7003 i915_ironlake_get_mem_freq(dev);
7004
1fa61106 7005 /* For FIFO watermark updates */
f5ed50cb 7006 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7007 skl_setup_wm_latency(dev);
7008
a82abe43
ID		 7009 if (IS_BROXTON(dev))
7010 dev_priv->display.init_clock_gating =
7011 bxt_init_clock_gating;
2d41c0b5 7012 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7013 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7014 ilk_setup_wm_latency(dev);
53615a5e 7015
bd602544
VS		 7016 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7017 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7018 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7019 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
bf220452 7020 dev_priv->display.update_wm = ilk_update_wm;
86c8bbbe 7021 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
bf220452 7022 dev_priv->display.program_watermarks = ilk_program_watermarks;
bd602544
VS		 7023 } else {
7024 DRM_DEBUG_KMS("Failed to read display plane latency. "
7025 "Disable CxSR\n");
7026 }
7027
7028 if (IS_GEN5(dev))
1fa61106 7029 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7030 else if (IS_GEN6(dev))
1fa61106 7031 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7032 else if (IS_IVYBRIDGE(dev))
1fa61106 7033 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7034 else if (IS_HASWELL(dev))
cad2a2d7 7035 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7036 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7037 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7038 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7039 vlv_setup_wm_latency(dev);
7040
7041 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7042 dev_priv->display.init_clock_gating =
7043 cherryview_init_clock_gating;
1fa61106 7044 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7045 vlv_setup_wm_latency(dev);
7046
7047 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7048 dev_priv->display.init_clock_gating =
7049 valleyview_init_clock_gating;
1fa61106
ED		 7050 } else if (IS_PINEVIEW(dev)) {
7051 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7052 dev_priv->is_ddr3,
7053 dev_priv->fsb_freq,
7054 dev_priv->mem_freq)) {
7055 DRM_INFO("failed to find known CxSR latency "
7056 "(found ddr%s fsb freq %d, mem freq %d), "
7057 "disabling CxSR\n",
7058 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7059 dev_priv->fsb_freq, dev_priv->mem_freq);
7060 /* Disable CxSR and never update its watermark again */
5209b1f4 7061 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7062 dev_priv->display.update_wm = NULL;
7063 } else
7064 dev_priv->display.update_wm = pineview_update_wm;
7065 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7066 } else if (IS_G4X(dev)) {
7067 dev_priv->display.update_wm = g4x_update_wm;
7068 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7069 } else if (IS_GEN4(dev)) {
7070 dev_priv->display.update_wm = i965_update_wm;
7071 if (IS_CRESTLINE(dev))
7072 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7073 else if (IS_BROADWATER(dev))
7074 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7075 } else if (IS_GEN3(dev)) {
7076 dev_priv->display.update_wm = i9xx_update_wm;
7077 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7078 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7079 } else if (IS_GEN2(dev)) {
7080 if (INTEL_INFO(dev)->num_pipes == 1) {
7081 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7082 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7083 } else {
7084 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7085 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7086 }
7087
7088 if (IS_I85X(dev) || IS_I865G(dev))
7089 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7090 else
7091 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7092 } else {
7093 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7094 }
7095}
7096
151a49d0 7097int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7098{
4fc688ce 7099 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7100
7101 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7102 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7103 return -EAGAIN;
7104 }
7105
7106 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7107 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7108 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7109
7110 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7111 500)) {
7112 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7113 return -ETIMEDOUT;
7114 }
7115
7116 *val = I915_READ(GEN6_PCODE_DATA);
7117 I915_WRITE(GEN6_PCODE_DATA, 0);
7118
7119 return 0;
7120}
7121
151a49d0 7122int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7123{
4fc688ce 7124 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7125
7126 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7127 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7128 return -EAGAIN;
7129 }
7130
7131 I915_WRITE(GEN6_PCODE_DATA, val);
7132 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7133
7134 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7135 500)) {
7136 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7137 return -ETIMEDOUT;
7138 }
7139
7140 I915_WRITE(GEN6_PCODE_DATA, 0);
7141
7142 return 0;
7143}
a0e4e199 7144
dd06f88c 7145static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7146{
dd06f88c
VS		 7147 switch (czclk_freq) {
7148 case 200:
7149 return 10;
7150 case 267:
7151 return 12;
7152 case 320:
7153 case 333:
dd06f88c 7154 return 16;
ab3fb157
VS		 7155 case 400:
7156 return 20;
855ba3be
JB		 7157 default:
7158 return -1;
7159 }
dd06f88c 7160}
855ba3be 7161
dd06f88c
VS		 7162static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7163{
bfa7df01 7164 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7165
7166 div = vlv_gpu_freq_div(czclk_freq);
7167 if (div < 0)
7168 return div;
7169
7170 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7171}
7172
b55dd647 7173static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7174{
bfa7df01 7175 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7176
dd06f88c
VS		 7177 mul = vlv_gpu_freq_div(czclk_freq);
7178 if (mul < 0)
7179 return mul;
855ba3be 7180
dd06f88c 7181 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7182}
7183
b55dd647 7184static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7185{
bfa7df01 7186 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7187
dd06f88c
VS		 7188 div = vlv_gpu_freq_div(czclk_freq) / 2;
7189 if (div < 0)
7190 return div;
22b1b2f8 7191
dd06f88c 7192 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7193}
7194
b55dd647 7195static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7196{
bfa7df01 7197 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7198
dd06f88c
VS		 7199 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7200 if (mul < 0)
7201 return mul;
22b1b2f8 7202
1c14762d 7203 /* CHV needs even values */
dd06f88c 7204 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7205}
7206
616bc820 7207int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7208{
80b6dda4 7209 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7210 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7211 GEN9_FREQ_SCALER);
80b6dda4 7212 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7213 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7214 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7215 return byt_gpu_freq(dev_priv, val);
7216 else
7217 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7218}
7219
616bc820
VS		 7220int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7221{
80b6dda4 7222 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7223 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7224 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7225 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7226 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7227 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7228 return byt_freq_opcode(dev_priv, val);
7229 else
500a3d2e 7230 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7231}
22b1b2f8 7232
6ad790c0
CW		 7233struct request_boost {
7234 struct work_struct work;
eed29a5b 7235 struct drm_i915_gem_request *req;
6ad790c0
CW		 7236};
7237
7238static void __intel_rps_boost_work(struct work_struct *work)
7239{
7240 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7241 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7242
e61b9958
CW		 7243 if (!i915_gem_request_completed(req, true))
7244 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7245 req->emitted_jiffies);
6ad790c0 7246
e61b9958 7247 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7248 kfree(boost);
7249}
7250
7251void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7252 struct drm_i915_gem_request *req)
6ad790c0
CW		 7253{
7254 struct request_boost *boost;
7255
eed29a5b 7256 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7257 return;
7258
e61b9958
CW		 7259 if (i915_gem_request_completed(req, true))
7260 return;
7261
6ad790c0
CW		 7262 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7263 if (boost == NULL)
7264 return;
7265
eed29a5b
DV		 7266 i915_gem_request_reference(req);
7267 boost->req = req;
6ad790c0
CW		 7268
7269 INIT_WORK(&boost->work, __intel_rps_boost_work);
7270 queue_work(to_i915(dev)->wq, &boost->work);
7271}
7272
f742a552 7273void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7274{
7275 struct drm_i915_private *dev_priv = dev->dev_private;
7276
f742a552 7277 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7278 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7279
907b28c5
CW		 7280 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7281 intel_gen6_powersave_work);
1854d5ca 7282 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7283 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7284 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7285
33688d95 7286 dev_priv->pm.suspended = false;
1f814dac 7287 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7288 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7289}
Linux kernel - Deliverables
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