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drm/i915/skl: Double RC6 WRL always on
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
a82abe43
ID		 55static void bxt_init_clock_gating(struct drm_device *dev)
56{
32608ca2
ID		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
a7546159
NH		 59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
32608ca2
ID		 63 /*
64 * FIXME:
868434c5 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 66 */
32608ca2 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 69
70 /*
71 * Wa: Backlight PWM may stop in the asserted state, causing backlight
72 * to stay fully on.
73 */
74 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
75 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
76 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 77}
78
c921aba8
DV		 79static void i915_pineview_get_mem_freq(struct drm_device *dev)
80{
50227e1c 81 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 82 u32 tmp;
83
84 tmp = I915_READ(CLKCFG);
85
86 switch (tmp & CLKCFG_FSB_MASK) {
87 case CLKCFG_FSB_533:
88 dev_priv->fsb_freq = 533; /* 133*4 */
89 break;
90 case CLKCFG_FSB_800:
91 dev_priv->fsb_freq = 800; /* 200*4 */
92 break;
93 case CLKCFG_FSB_667:
94 dev_priv->fsb_freq = 667; /* 167*4 */
95 break;
96 case CLKCFG_FSB_400:
97 dev_priv->fsb_freq = 400; /* 100*4 */
98 break;
99 }
100
101 switch (tmp & CLKCFG_MEM_MASK) {
102 case CLKCFG_MEM_533:
103 dev_priv->mem_freq = 533;
104 break;
105 case CLKCFG_MEM_667:
106 dev_priv->mem_freq = 667;
107 break;
108 case CLKCFG_MEM_800:
109 dev_priv->mem_freq = 800;
110 break;
111 }
112
113 /* detect pineview DDR3 setting */
114 tmp = I915_READ(CSHRDDR3CTL);
115 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
116}
117
118static void i915_ironlake_get_mem_freq(struct drm_device *dev)
119{
50227e1c 120 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 121 u16 ddrpll, csipll;
122
123 ddrpll = I915_READ16(DDRMPLL1);
124 csipll = I915_READ16(CSIPLL0);
125
126 switch (ddrpll & 0xff) {
127 case 0xc:
128 dev_priv->mem_freq = 800;
129 break;
130 case 0x10:
131 dev_priv->mem_freq = 1066;
132 break;
133 case 0x14:
134 dev_priv->mem_freq = 1333;
135 break;
136 case 0x18:
137 dev_priv->mem_freq = 1600;
138 break;
139 default:
140 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
141 ddrpll & 0xff);
142 dev_priv->mem_freq = 0;
143 break;
144 }
145
20e4d407 146 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 147
148 switch (csipll & 0x3ff) {
149 case 0x00c:
150 dev_priv->fsb_freq = 3200;
151 break;
152 case 0x00e:
153 dev_priv->fsb_freq = 3733;
154 break;
155 case 0x010:
156 dev_priv->fsb_freq = 4266;
157 break;
158 case 0x012:
159 dev_priv->fsb_freq = 4800;
160 break;
161 case 0x014:
162 dev_priv->fsb_freq = 5333;
163 break;
164 case 0x016:
165 dev_priv->fsb_freq = 5866;
166 break;
167 case 0x018:
168 dev_priv->fsb_freq = 6400;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
172 csipll & 0x3ff);
173 dev_priv->fsb_freq = 0;
174 break;
175 }
176
177 if (dev_priv->fsb_freq == 3200) {
20e4d407 178 dev_priv->ips.c_m = 0;
c921aba8 179 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 180 dev_priv->ips.c_m = 1;
c921aba8 181 } else {
20e4d407 182 dev_priv->ips.c_m = 2;
c921aba8
DV		 183 }
184}
185
b445e3b0
ED		 186static const struct cxsr_latency cxsr_latency_table[] = {
187 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
188 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
189 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
190 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
191 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
192
193 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
194 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
195 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
196 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
197 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
198
199 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
200 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
201 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
202 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
203 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
204
205 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
206 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
207 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
208 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
209 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
210
211 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
212 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
213 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
214 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
215 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
216
217 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
218 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
219 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
220 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
221 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
222};
223
63c62275 224static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 225 int is_ddr3,
226 int fsb,
227 int mem)
228{
229 const struct cxsr_latency *latency;
230 int i;
231
232 if (fsb == 0 || mem == 0)
233 return NULL;
234
235 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
236 latency = &cxsr_latency_table[i];
237 if (is_desktop == latency->is_desktop &&
238 is_ddr3 == latency->is_ddr3 &&
239 fsb == latency->fsb_freq && mem == latency->mem_freq)
240 return latency;
241 }
242
243 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
244
245 return NULL;
246}
247
fc1ac8de
VS		 248static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
249{
250 u32 val;
251
252 mutex_lock(&dev_priv->rps.hw_lock);
253
254 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
255 if (enable)
256 val &= ~FORCE_DDR_HIGH_FREQ;
257 else
258 val |= FORCE_DDR_HIGH_FREQ;
259 val &= ~FORCE_DDR_LOW_FREQ;
260 val |= FORCE_DDR_FREQ_REQ_ACK;
261 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
262
263 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
264 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
265 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
266
267 mutex_unlock(&dev_priv->rps.hw_lock);
268}
269
cfb41411
VS		 270static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
271{
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
277 if (enable)
278 val |= DSP_MAXFIFO_PM5_ENABLE;
279 else
280 val &= ~DSP_MAXFIFO_PM5_ENABLE;
281 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
282
283 mutex_unlock(&dev_priv->rps.hw_lock);
284}
285
f4998963
VS		 286#define FW_WM(value, plane) \
287 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
288
5209b1f4 289void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 290{
5209b1f4
ID		 291 struct drm_device *dev = dev_priv->dev;
292 u32 val;
b445e3b0 293
5209b1f4
ID		 294 if (IS_VALLEYVIEW(dev)) {
295 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 296 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 297 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 298 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
299 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 300 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 301 } else if (IS_PINEVIEW(dev)) {
302 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
303 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
304 I915_WRITE(DSPFW3, val);
a7a6c498 305 POSTING_READ(DSPFW3);
5209b1f4
ID		 306 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
307 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
308 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
309 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 310 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 311 } else if (IS_I915GM(dev)) {
312 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
313 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
314 I915_WRITE(INSTPM, val);
a7a6c498 315 POSTING_READ(INSTPM);
5209b1f4
ID		 316 } else {
317 return;
318 }
b445e3b0 319
5209b1f4
ID		 320 DRM_DEBUG_KMS("memory self-refresh is %s\n",
321 enable ? "enabled" : "disabled");
b445e3b0
ED		 322}
323
fc1ac8de 324
b445e3b0
ED		 325/*
326 * Latency for FIFO fetches is dependent on several factors:
327 * - memory configuration (speed, channels)
328 * - chipset
329 * - current MCH state
330 * It can be fairly high in some situations, so here we assume a fairly
331 * pessimal value. It's a tradeoff between extra memory fetches (if we
332 * set this value too high, the FIFO will fetch frequently to stay full)
333 * and power consumption (set it too low to save power and we might see
334 * FIFO underruns and display "flicker").
335 *
336 * A value of 5us seems to be a good balance; safe for very low end
337 * platforms but not overly aggressive on lower latency configs.
338 */
5aef6003 339static const int pessimal_latency_ns = 5000;
b445e3b0 340
b5004720
VS		 341#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
342 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
343
344static int vlv_get_fifo_size(struct drm_device *dev,
345 enum pipe pipe, int plane)
346{
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 int sprite0_start, sprite1_start, size;
349
350 switch (pipe) {
351 uint32_t dsparb, dsparb2, dsparb3;
352 case PIPE_A:
353 dsparb = I915_READ(DSPARB);
354 dsparb2 = I915_READ(DSPARB2);
355 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
356 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
357 break;
358 case PIPE_B:
359 dsparb = I915_READ(DSPARB);
360 dsparb2 = I915_READ(DSPARB2);
361 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
362 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
363 break;
364 case PIPE_C:
365 dsparb2 = I915_READ(DSPARB2);
366 dsparb3 = I915_READ(DSPARB3);
367 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
368 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
369 break;
370 default:
371 return 0;
372 }
373
374 switch (plane) {
375 case 0:
376 size = sprite0_start;
377 break;
378 case 1:
379 size = sprite1_start - sprite0_start;
380 break;
381 case 2:
382 size = 512 - 1 - sprite1_start;
383 break;
384 default:
385 return 0;
386 }
387
388 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
389 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
390 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
391 size);
392
393 return size;
394}
395
1fa61106 396static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 397{
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 uint32_t dsparb = I915_READ(DSPARB);
400 int size;
401
402 size = dsparb & 0x7f;
403 if (plane)
404 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
405
406 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
407 plane ? "B" : "A", size);
408
409 return size;
410}
411
feb56b93 412static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 413{
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t dsparb = I915_READ(DSPARB);
416 int size;
417
418 size = dsparb & 0x1ff;
419 if (plane)
420 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
421 size >>= 1; /* Convert to cachelines */
422
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
424 plane ? "B" : "A", size);
425
426 return size;
427}
428
1fa61106 429static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 430{
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 uint32_t dsparb = I915_READ(DSPARB);
433 int size;
434
435 size = dsparb & 0x7f;
436 size >>= 2; /* Convert to cachelines */
437
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
439 plane ? "B" : "A",
440 size);
441
442 return size;
443}
444
b445e3b0
ED		 445/* Pineview has different values for various configs */
446static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 447 .fifo_size = PINEVIEW_DISPLAY_FIFO,
448 .max_wm = PINEVIEW_MAX_WM,
449 .default_wm = PINEVIEW_DFT_WM,
450 .guard_size = PINEVIEW_GUARD_WM,
451 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 452};
453static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 459};
460static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 461 .fifo_size = PINEVIEW_CURSOR_FIFO,
462 .max_wm = PINEVIEW_CURSOR_MAX_WM,
463 .default_wm = PINEVIEW_CURSOR_DFT_WM,
464 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 466};
467static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 475 .fifo_size = G4X_FIFO_SIZE,
476 .max_wm = G4X_MAX_WM,
477 .default_wm = G4X_MAX_WM,
478 .guard_size = 2,
479 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 482 .fifo_size = I965_CURSOR_FIFO,
483 .max_wm = I965_CURSOR_MAX_WM,
484 .default_wm = I965_CURSOR_DFT_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 489 .fifo_size = VALLEYVIEW_FIFO_SIZE,
490 .max_wm = VALLEYVIEW_MAX_WM,
491 .default_wm = VALLEYVIEW_MAX_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 494};
495static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 503 .fifo_size = I965_CURSOR_FIFO,
504 .max_wm = I965_CURSOR_MAX_WM,
505 .default_wm = I965_CURSOR_DFT_WM,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 510 .fifo_size = I945_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 517 .fifo_size = I915_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 522};
9d539105 523static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 529};
9d539105
VS		 530static const struct intel_watermark_params i830_bc_wm_info = {
531 .fifo_size = I855GM_FIFO_SIZE,
532 .max_wm = I915_MAX_WM/2,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
536};
feb56b93 537static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 538 .fifo_size = I830_FIFO_SIZE,
539 .max_wm = I915_MAX_WM,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 543};
544
b445e3b0
ED		 545/**
546 * intel_calculate_wm - calculate watermark level
547 * @clock_in_khz: pixel clock
548 * @wm: chip FIFO params
549 * @pixel_size: display pixel size
550 * @latency_ns: memory latency for the platform
551 *
552 * Calculate the watermark level (the level at which the display plane will
553 * start fetching from memory again). Each chip has a different display
554 * FIFO size and allocation, so the caller needs to figure that out and pass
555 * in the correct intel_watermark_params structure.
556 *
557 * As the pixel clock runs, the FIFO will be drained at a rate that depends
558 * on the pixel size. When it reaches the watermark level, it'll start
559 * fetching FIFO line sized based chunks from memory until the FIFO fills
560 * past the watermark point. If the FIFO drains completely, a FIFO underrun
561 * will occur, and a display engine hang could result.
562 */
563static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
564 const struct intel_watermark_params *wm,
565 int fifo_size,
566 int pixel_size,
567 unsigned long latency_ns)
568{
569 long entries_required, wm_size;
570
571 /*
572 * Note: we need to make sure we don't overflow for various clock &
573 * latency values.
574 * clocks go from a few thousand to several hundred thousand.
575 * latency is usually a few thousand
576 */
577 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
578 1000;
579 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
580
581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
582
583 wm_size = fifo_size - (entries_required + wm->guard_size);
584
585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
586
587 /* Don't promote wm_size to unsigned... */
588 if (wm_size > (long)wm->max_wm)
589 wm_size = wm->max_wm;
590 if (wm_size <= 0)
591 wm_size = wm->default_wm;
d6feb196
VS		 592
593 /*
594 * Bspec seems to indicate that the value shouldn't be lower than
595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
596 * Lets go for 8 which is the burst size since certain platforms
597 * already use a hardcoded 8 (which is what the spec says should be
598 * done).
599 */
600 if (wm_size <= 8)
601 wm_size = 8;
602
b445e3b0
ED		 603 return wm_size;
604}
605
606static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
607{
608 struct drm_crtc *crtc, *enabled = NULL;
609
70e1e0ec 610 for_each_crtc(dev, crtc) {
3490ea5d 611 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 612 if (enabled)
613 return NULL;
614 enabled = crtc;
615 }
616 }
617
618 return enabled;
619}
620
46ba614c 621static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 622{
46ba614c 623 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 624 struct drm_i915_private *dev_priv = dev->dev_private;
625 struct drm_crtc *crtc;
626 const struct cxsr_latency *latency;
627 u32 reg;
628 unsigned long wm;
629
630 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
631 dev_priv->fsb_freq, dev_priv->mem_freq);
632 if (!latency) {
633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 634 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 635 return;
636 }
637
638 crtc = single_enabled_crtc(dev);
639 if (crtc) {
7c5f93b0 640 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 641 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 642 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 643
644 /* Display SR */
645 wm = intel_calculate_wm(clock, &pineview_display_wm,
646 pineview_display_wm.fifo_size,
647 pixel_size, latency->display_sr);
648 reg = I915_READ(DSPFW1);
649 reg &= ~DSPFW_SR_MASK;
f4998963 650 reg |= FW_WM(wm, SR);
b445e3b0
ED		 651 I915_WRITE(DSPFW1, reg);
652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
653
654 /* cursor SR */
655 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
656 pineview_display_wm.fifo_size,
657 pixel_size, latency->cursor_sr);
658 reg = I915_READ(DSPFW3);
659 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 660 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 661 I915_WRITE(DSPFW3, reg);
662
663 /* Display HPLL off SR */
664 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
665 pineview_display_hplloff_wm.fifo_size,
666 pixel_size, latency->display_hpll_disable);
667 reg = I915_READ(DSPFW3);
668 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 669 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 670 I915_WRITE(DSPFW3, reg);
671
672 /* cursor HPLL off SR */
673 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
674 pineview_display_hplloff_wm.fifo_size,
675 pixel_size, latency->cursor_hpll_disable);
676 reg = I915_READ(DSPFW3);
677 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 678 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 679 I915_WRITE(DSPFW3, reg);
680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
681
5209b1f4 682 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 683 } else {
5209b1f4 684 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 685 }
686}
687
688static bool g4x_compute_wm0(struct drm_device *dev,
689 int plane,
690 const struct intel_watermark_params *display,
691 int display_latency_ns,
692 const struct intel_watermark_params *cursor,
693 int cursor_latency_ns,
694 int *plane_wm,
695 int *cursor_wm)
696{
697 struct drm_crtc *crtc;
4fe8590a 698 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 699 int htotal, hdisplay, clock, pixel_size;
700 int line_time_us, line_count;
701 int entries, tlb_miss;
702
703 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 704 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 705 *cursor_wm = cursor->guard_size;
706 *plane_wm = display->guard_size;
707 return false;
708 }
709
6e3c9717 710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 711 clock = adjusted_mode->crtc_clock;
fec8cba3 712 htotal = adjusted_mode->crtc_htotal;
6e3c9717 713 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 714 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 715
716 /* Use the small buffer method to calculate plane watermark */
717 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
718 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
719 if (tlb_miss > 0)
720 entries += tlb_miss;
721 entries = DIV_ROUND_UP(entries, display->cacheline_size);
722 *plane_wm = entries + display->guard_size;
723 if (*plane_wm > (int)display->max_wm)
724 *plane_wm = display->max_wm;
725
726 /* Use the large buffer method to calculate cursor watermark */
922044c9 727 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 728 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 729 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 730 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
731 if (tlb_miss > 0)
732 entries += tlb_miss;
733 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
734 *cursor_wm = entries + cursor->guard_size;
735 if (*cursor_wm > (int)cursor->max_wm)
736 *cursor_wm = (int)cursor->max_wm;
737
738 return true;
739}
740
741/*
742 * Check the wm result.
743 *
744 * If any calculated watermark values is larger than the maximum value that
745 * can be programmed into the associated watermark register, that watermark
746 * must be disabled.
747 */
748static bool g4x_check_srwm(struct drm_device *dev,
749 int display_wm, int cursor_wm,
750 const struct intel_watermark_params *display,
751 const struct intel_watermark_params *cursor)
752{
753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
754 display_wm, cursor_wm);
755
756 if (display_wm > display->max_wm) {
757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
758 display_wm, display->max_wm);
759 return false;
760 }
761
762 if (cursor_wm > cursor->max_wm) {
763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
764 cursor_wm, cursor->max_wm);
765 return false;
766 }
767
768 if (!(display_wm || cursor_wm)) {
769 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
770 return false;
771 }
772
773 return true;
774}
775
776static bool g4x_compute_srwm(struct drm_device *dev,
777 int plane,
778 int latency_ns,
779 const struct intel_watermark_params *display,
780 const struct intel_watermark_params *cursor,
781 int *display_wm, int *cursor_wm)
782{
783 struct drm_crtc *crtc;
4fe8590a 784 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 785 int hdisplay, htotal, pixel_size, clock;
786 unsigned long line_time_us;
787 int line_count, line_size;
788 int small, large;
789 int entries;
790
791 if (!latency_ns) {
792 *display_wm = *cursor_wm = 0;
793 return false;
794 }
795
796 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 797 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 798 clock = adjusted_mode->crtc_clock;
fec8cba3 799 htotal = adjusted_mode->crtc_htotal;
6e3c9717 800 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 801 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 802
922044c9 803 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 804 line_count = (latency_ns / line_time_us + 1000) / 1000;
805 line_size = hdisplay * pixel_size;
806
807 /* Use the minimum of the small and large buffer method for primary */
808 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
809 large = line_count * line_size;
810
811 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
812 *display_wm = entries + display->guard_size;
813
814 /* calculate the self-refresh watermark for display cursor */
3dd512fb 815 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 816 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
817 *cursor_wm = entries + cursor->guard_size;
818
819 return g4x_check_srwm(dev,
820 *display_wm, *cursor_wm,
821 display, cursor);
822}
823
15665979
VS		 824#define FW_WM_VLV(value, plane) \
825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
826
0018fda1
VS		 827static void vlv_write_wm_values(struct intel_crtc *crtc,
828 const struct vlv_wm_values *wm)
829{
830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
831 enum pipe pipe = crtc->pipe;
832
833 I915_WRITE(VLV_DDL(pipe),
834 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
835 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
836 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
837 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
838
ae80152d 839 I915_WRITE(DSPFW1,
15665979
VS		 840 FW_WM(wm->sr.plane, SR) |
841 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
842 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
843 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 844 I915_WRITE(DSPFW2,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
846 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
847 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 848 I915_WRITE(DSPFW3,
15665979 849 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 850
851 if (IS_CHERRYVIEW(dev_priv)) {
852 I915_WRITE(DSPFW7_CHV,
15665979
VS		 853 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 855 I915_WRITE(DSPFW8_CHV,
15665979
VS		 856 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 858 I915_WRITE(DSPFW9_CHV,
15665979
VS		 859 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
860 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 861 I915_WRITE(DSPHOWM,
15665979
VS		 862 FW_WM(wm->sr.plane >> 9, SR_HI) |
863 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
865 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
868 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
871 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 872 } else {
873 I915_WRITE(DSPFW7,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPHOWM,
15665979
VS		 877 FW_WM(wm->sr.plane >> 9, SR_HI) |
878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 884 }
885
2cb389b7
VS		 886 /* zero (unused) WM1 watermarks */
887 I915_WRITE(DSPFW4, 0);
888 I915_WRITE(DSPFW5, 0);
889 I915_WRITE(DSPFW6, 0);
890 I915_WRITE(DSPHOWM1, 0);
891
ae80152d 892 POSTING_READ(DSPFW1);
0018fda1
VS		 893}
894
15665979
VS		 895#undef FW_WM_VLV
896
6eb1a681
VS		 897enum vlv_wm_level {
898 VLV_WM_LEVEL_PM2,
899 VLV_WM_LEVEL_PM5,
900 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 901};
902
262cd2e1
VS		 903/* latency must be in 0.1us units. */
904static unsigned int vlv_wm_method2(unsigned int pixel_rate,
905 unsigned int pipe_htotal,
906 unsigned int horiz_pixels,
907 unsigned int bytes_per_pixel,
908 unsigned int latency)
909{
910 unsigned int ret;
911
912 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
913 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
914 ret = DIV_ROUND_UP(ret, 64);
915
916 return ret;
917}
918
919static void vlv_setup_wm_latency(struct drm_device *dev)
920{
921 struct drm_i915_private *dev_priv = dev->dev_private;
922
923 /* all latencies in usec */
924 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
925
58590c14
VS		 926 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
927
262cd2e1
VS		 928 if (IS_CHERRYVIEW(dev_priv)) {
929 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 931
932 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 933 }
934}
935
936static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
937 struct intel_crtc *crtc,
938 const struct intel_plane_state *state,
939 int level)
940{
941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
942 int clock, htotal, pixel_size, width, wm;
943
944 if (dev_priv->wm.pri_latency[level] == 0)
945 return USHRT_MAX;
946
947 if (!state->visible)
948 return 0;
949
950 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
951 clock = crtc->config->base.adjusted_mode.crtc_clock;
952 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
953 width = crtc->config->pipe_src_w;
954 if (WARN_ON(htotal == 0))
955 htotal = 1;
956
957 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
958 /*
959 * FIXME the formula gives values that are
960 * too big for the cursor FIFO, and hence we
961 * would never be able to use cursors. For
962 * now just hardcode the watermark.
963 */
964 wm = 63;
965 } else {
966 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
967 dev_priv->wm.pri_latency[level] * 10);
968 }
969
970 return min_t(int, wm, USHRT_MAX);
971}
972
54f1b6e1
VS		 973static void vlv_compute_fifo(struct intel_crtc *crtc)
974{
975 struct drm_device *dev = crtc->base.dev;
976 struct vlv_wm_state *wm_state = &crtc->wm_state;
977 struct intel_plane *plane;
978 unsigned int total_rate = 0;
979 const int fifo_size = 512 - 1;
980 int fifo_extra, fifo_left = fifo_size;
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985
986 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
987 continue;
988
989 if (state->visible) {
990 wm_state->num_active_planes++;
991 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
992 }
993 }
994
995 for_each_intel_plane_on_crtc(dev, crtc, plane) {
996 struct intel_plane_state *state =
997 to_intel_plane_state(plane->base.state);
998 unsigned int rate;
999
1000 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1001 plane->wm.fifo_size = 63;
1002 continue;
1003 }
1004
1005 if (!state->visible) {
1006 plane->wm.fifo_size = 0;
1007 continue;
1008 }
1009
1010 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1011 plane->wm.fifo_size = fifo_size * rate / total_rate;
1012 fifo_left -= plane->wm.fifo_size;
1013 }
1014
1015 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1016
1017 /* spread the remainder evenly */
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 int plane_extra;
1020
1021 if (fifo_left == 0)
1022 break;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1025 continue;
1026
1027 /* give it all to the first plane if none are active */
1028 if (plane->wm.fifo_size == 0 &&
1029 wm_state->num_active_planes)
1030 continue;
1031
1032 plane_extra = min(fifo_extra, fifo_left);
1033 plane->wm.fifo_size += plane_extra;
1034 fifo_left -= plane_extra;
1035 }
1036
1037 WARN_ON(fifo_left != 0);
1038}
1039
262cd2e1
VS		 1040static void vlv_invert_wms(struct intel_crtc *crtc)
1041{
1042 struct vlv_wm_state *wm_state = &crtc->wm_state;
1043 int level;
1044
1045 for (level = 0; level < wm_state->num_levels; level++) {
1046 struct drm_device *dev = crtc->base.dev;
1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1048 struct intel_plane *plane;
1049
1050 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1051 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1052
1053 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1054 switch (plane->base.type) {
1055 int sprite;
1056 case DRM_PLANE_TYPE_CURSOR:
1057 wm_state->wm[level].cursor = plane->wm.fifo_size -
1058 wm_state->wm[level].cursor;
1059 break;
1060 case DRM_PLANE_TYPE_PRIMARY:
1061 wm_state->wm[level].primary = plane->wm.fifo_size -
1062 wm_state->wm[level].primary;
1063 break;
1064 case DRM_PLANE_TYPE_OVERLAY:
1065 sprite = plane->plane;
1066 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1067 wm_state->wm[level].sprite[sprite];
1068 break;
1069 }
1070 }
1071 }
1072}
1073
26e1fe4f 1074static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1075{
1076 struct drm_device *dev = crtc->base.dev;
1077 struct vlv_wm_state *wm_state = &crtc->wm_state;
1078 struct intel_plane *plane;
1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1080 int level;
1081
1082 memset(wm_state, 0, sizeof(*wm_state));
1083
852eb00d 1084 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1085 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1086
1087 wm_state->num_active_planes = 0;
262cd2e1 1088
54f1b6e1 1089 vlv_compute_fifo(crtc);
262cd2e1
VS		 1090
1091 if (wm_state->num_active_planes != 1)
1092 wm_state->cxsr = false;
1093
1094 if (wm_state->cxsr) {
1095 for (level = 0; level < wm_state->num_levels; level++) {
1096 wm_state->sr[level].plane = sr_fifo_size;
1097 wm_state->sr[level].cursor = 63;
1098 }
1099 }
1100
1101 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1102 struct intel_plane_state *state =
1103 to_intel_plane_state(plane->base.state);
1104
1105 if (!state->visible)
1106 continue;
1107
1108 /* normal watermarks */
1109 for (level = 0; level < wm_state->num_levels; level++) {
1110 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1111 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1112
1113 /* hack */
1114 if (WARN_ON(level == 0 && wm > max_wm))
1115 wm = max_wm;
1116
1117 if (wm > plane->wm.fifo_size)
1118 break;
1119
1120 switch (plane->base.type) {
1121 int sprite;
1122 case DRM_PLANE_TYPE_CURSOR:
1123 wm_state->wm[level].cursor = wm;
1124 break;
1125 case DRM_PLANE_TYPE_PRIMARY:
1126 wm_state->wm[level].primary = wm;
1127 break;
1128 case DRM_PLANE_TYPE_OVERLAY:
1129 sprite = plane->plane;
1130 wm_state->wm[level].sprite[sprite] = wm;
1131 break;
1132 }
1133 }
1134
1135 wm_state->num_levels = level;
1136
1137 if (!wm_state->cxsr)
1138 continue;
1139
1140 /* maxfifo watermarks */
1141 switch (plane->base.type) {
1142 int sprite, level;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 for (level = 0; level < wm_state->num_levels; level++)
1145 wm_state->sr[level].cursor =
5a37ed0a 1146 wm_state->wm[level].cursor;
262cd2e1
VS		 1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 for (level = 0; level < wm_state->num_levels; level++)
1150 wm_state->sr[level].plane =
1151 min(wm_state->sr[level].plane,
1152 wm_state->wm[level].primary);
1153 break;
1154 case DRM_PLANE_TYPE_OVERLAY:
1155 sprite = plane->plane;
1156 for (level = 0; level < wm_state->num_levels; level++)
1157 wm_state->sr[level].plane =
1158 min(wm_state->sr[level].plane,
1159 wm_state->wm[level].sprite[sprite]);
1160 break;
1161 }
1162 }
1163
1164 /* clear any (partially) filled invalid levels */
58590c14 1165 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1166 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1167 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1168 }
1169
1170 vlv_invert_wms(crtc);
1171}
1172
54f1b6e1
VS		 1173#define VLV_FIFO(plane, value) \
1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1175
1176static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1177{
1178 struct drm_device *dev = crtc->base.dev;
1179 struct drm_i915_private *dev_priv = to_i915(dev);
1180 struct intel_plane *plane;
1181 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1182
1183 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1184 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1185 WARN_ON(plane->wm.fifo_size != 63);
1186 continue;
1187 }
1188
1189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1190 sprite0_start = plane->wm.fifo_size;
1191 else if (plane->plane == 0)
1192 sprite1_start = sprite0_start + plane->wm.fifo_size;
1193 else
1194 fifo_size = sprite1_start + plane->wm.fifo_size;
1195 }
1196
1197 WARN_ON(fifo_size != 512 - 1);
1198
1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1200 pipe_name(crtc->pipe), sprite0_start,
1201 sprite1_start, fifo_size);
1202
1203 switch (crtc->pipe) {
1204 uint32_t dsparb, dsparb2, dsparb3;
1205 case PIPE_A:
1206 dsparb = I915_READ(DSPARB);
1207 dsparb2 = I915_READ(DSPARB2);
1208
1209 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1210 VLV_FIFO(SPRITEB, 0xff));
1211 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1212 VLV_FIFO(SPRITEB, sprite1_start));
1213
1214 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1215 VLV_FIFO(SPRITEB_HI, 0x1));
1216 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1217 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1218
1219 I915_WRITE(DSPARB, dsparb);
1220 I915_WRITE(DSPARB2, dsparb2);
1221 break;
1222 case PIPE_B:
1223 dsparb = I915_READ(DSPARB);
1224 dsparb2 = I915_READ(DSPARB2);
1225
1226 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1227 VLV_FIFO(SPRITED, 0xff));
1228 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1229 VLV_FIFO(SPRITED, sprite1_start));
1230
1231 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1232 VLV_FIFO(SPRITED_HI, 0xff));
1233 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1234 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1235
1236 I915_WRITE(DSPARB, dsparb);
1237 I915_WRITE(DSPARB2, dsparb2);
1238 break;
1239 case PIPE_C:
1240 dsparb3 = I915_READ(DSPARB3);
1241 dsparb2 = I915_READ(DSPARB2);
1242
1243 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1244 VLV_FIFO(SPRITEF, 0xff));
1245 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1246 VLV_FIFO(SPRITEF, sprite1_start));
1247
1248 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1249 VLV_FIFO(SPRITEF_HI, 0xff));
1250 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1251 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1252
1253 I915_WRITE(DSPARB3, dsparb3);
1254 I915_WRITE(DSPARB2, dsparb2);
1255 break;
1256 default:
1257 break;
1258 }
1259}
1260
1261#undef VLV_FIFO
1262
262cd2e1
VS		 1263static void vlv_merge_wm(struct drm_device *dev,
1264 struct vlv_wm_values *wm)
1265{
1266 struct intel_crtc *crtc;
1267 int num_active_crtcs = 0;
1268
58590c14 1269 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1270 wm->cxsr = true;
1271
1272 for_each_intel_crtc(dev, crtc) {
1273 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1274
1275 if (!crtc->active)
1276 continue;
1277
1278 if (!wm_state->cxsr)
1279 wm->cxsr = false;
1280
1281 num_active_crtcs++;
1282 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1283 }
1284
1285 if (num_active_crtcs != 1)
1286 wm->cxsr = false;
1287
6f9c784b
VS		 1288 if (num_active_crtcs > 1)
1289 wm->level = VLV_WM_LEVEL_PM2;
1290
262cd2e1
VS		 1291 for_each_intel_crtc(dev, crtc) {
1292 struct vlv_wm_state *wm_state = &crtc->wm_state;
1293 enum pipe pipe = crtc->pipe;
1294
1295 if (!crtc->active)
1296 continue;
1297
1298 wm->pipe[pipe] = wm_state->wm[wm->level];
1299 if (wm->cxsr)
1300 wm->sr = wm_state->sr[wm->level];
1301
1302 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1303 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1306 }
1307}
1308
1309static void vlv_update_wm(struct drm_crtc *crtc)
1310{
1311 struct drm_device *dev = crtc->dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 enum pipe pipe = intel_crtc->pipe;
1315 struct vlv_wm_values wm = {};
1316
26e1fe4f 1317 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1318 vlv_merge_wm(dev, &wm);
1319
54f1b6e1
VS		 1320 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1321 /* FIXME should be part of crtc atomic commit */
1322 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1323 return;
54f1b6e1 1324 }
262cd2e1
VS		 1325
1326 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1327 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1328 chv_set_memory_dvfs(dev_priv, false);
1329
1330 if (wm.level < VLV_WM_LEVEL_PM5 &&
1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1332 chv_set_memory_pm5(dev_priv, false);
1333
852eb00d 1334 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1335 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1336
54f1b6e1
VS		 1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc);
1339
262cd2e1
VS		 1340 vlv_write_wm_values(intel_crtc, &wm);
1341
1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1344 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1345 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1346 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1347
852eb00d 1348 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1349 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1350
1351 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, true);
1354
1355 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1357 chv_set_memory_dvfs(dev_priv, true);
1358
1359 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1360}
1361
ae80152d
VS		 1362#define single_plane_enabled(mask) is_power_of_2(mask)
1363
46ba614c 1364static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1365{
46ba614c 1366 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1367 static const int sr_latency_ns = 12000;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1370 int plane_sr, cursor_sr;
1371 unsigned int enabled = 0;
9858425c 1372 bool cxsr_enabled;
b445e3b0 1373
51cea1f4 1374 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1375 &g4x_wm_info, pessimal_latency_ns,
1376 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1377 &planea_wm, &cursora_wm))
51cea1f4 1378 enabled |= 1 << PIPE_A;
b445e3b0 1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1381 &g4x_wm_info, pessimal_latency_ns,
1382 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1383 &planeb_wm, &cursorb_wm))
51cea1f4 1384 enabled |= 1 << PIPE_B;
b445e3b0 1385
b445e3b0
ED		 1386 if (single_plane_enabled(enabled) &&
1387 g4x_compute_srwm(dev, ffs(enabled) - 1,
1388 sr_latency_ns,
1389 &g4x_wm_info,
1390 &g4x_cursor_wm_info,
52bd02d8 1391 &plane_sr, &cursor_sr)) {
9858425c 1392 cxsr_enabled = true;
52bd02d8 1393 } else {
9858425c 1394 cxsr_enabled = false;
5209b1f4 1395 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1396 plane_sr = cursor_sr = 0;
1397 }
b445e3b0 1398
a5043453
VS		 1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1401 planea_wm, cursora_wm,
1402 planeb_wm, cursorb_wm,
1403 plane_sr, cursor_sr);
1404
1405 I915_WRITE(DSPFW1,
f4998963
VS		 1406 FW_WM(plane_sr, SR) |
1407 FW_WM(cursorb_wm, CURSORB) |
1408 FW_WM(planeb_wm, PLANEB) |
1409 FW_WM(planea_wm, PLANEA));
b445e3b0 1410 I915_WRITE(DSPFW2,
8c919b28 1411 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1412 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1413 /* HPLL off in SR has some issues on G4x... disable it */
1414 I915_WRITE(DSPFW3,
8c919b28 1415 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1416 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1417
1418 if (cxsr_enabled)
1419 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1420}
1421
46ba614c 1422static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1423{
46ba614c 1424 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 struct drm_crtc *crtc;
1427 int srwm = 1;
1428 int cursor_sr = 16;
9858425c 1429 bool cxsr_enabled;
b445e3b0
ED		 1430
1431 /* Calc sr entries for one plane configs */
1432 crtc = single_enabled_crtc(dev);
1433 if (crtc) {
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns = 12000;
124abe07 1436 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1437 int clock = adjusted_mode->crtc_clock;
fec8cba3 1438 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1439 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1440 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1441 unsigned long line_time_us;
1442 int entries;
1443
922044c9 1444 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1445
1446 /* Use ns/us then divide to preserve precision */
1447 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1448 pixel_size * hdisplay;
1449 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450 srwm = I965_FIFO_SIZE - entries;
1451 if (srwm < 0)
1452 srwm = 1;
1453 srwm &= 0x1ff;
1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1455 entries, srwm);
1456
1457 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1458 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1459 entries = DIV_ROUND_UP(entries,
1460 i965_cursor_wm_info.cacheline_size);
1461 cursor_sr = i965_cursor_wm_info.fifo_size -
1462 (entries + i965_cursor_wm_info.guard_size);
1463
1464 if (cursor_sr > i965_cursor_wm_info.max_wm)
1465 cursor_sr = i965_cursor_wm_info.max_wm;
1466
1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468 "cursor %d\n", srwm, cursor_sr);
1469
9858425c 1470 cxsr_enabled = true;
b445e3b0 1471 } else {
9858425c 1472 cxsr_enabled = false;
b445e3b0 1473 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1474 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1475 }
1476
1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1478 srwm);
1479
1480 /* 965 has limitations... */
f4998963
VS		 1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1482 FW_WM(8, CURSORB) |
1483 FW_WM(8, PLANEB) |
1484 FW_WM(8, PLANEA));
1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1486 FW_WM(8, PLANEC_OLD));
b445e3b0 1487 /* update cursor SR watermark */
f4998963 1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1489
1490 if (cxsr_enabled)
1491 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1492}
1493
f4998963
VS		 1494#undef FW_WM
1495
46ba614c 1496static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1497{
46ba614c 1498 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 const struct intel_watermark_params *wm_info;
1501 uint32_t fwater_lo;
1502 uint32_t fwater_hi;
1503 int cwm, srwm = 1;
1504 int fifo_size;
1505 int planea_wm, planeb_wm;
1506 struct drm_crtc *crtc, *enabled = NULL;
1507
1508 if (IS_I945GM(dev))
1509 wm_info = &i945_wm_info;
1510 else if (!IS_GEN2(dev))
1511 wm_info = &i915_wm_info;
1512 else
9d539105 1513 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1514
1515 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1516 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1517 if (intel_crtc_active(crtc)) {
241bfc38 1518 const struct drm_display_mode *adjusted_mode;
59bea882 1519 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1520 if (IS_GEN2(dev))
1521 cpp = 4;
1522
6e3c9717 1523 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1524 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1525 wm_info, fifo_size, cpp,
5aef6003 1526 pessimal_latency_ns);
b445e3b0 1527 enabled = crtc;
9d539105 1528 } else {
b445e3b0 1529 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1530 if (planea_wm > (long)wm_info->max_wm)
1531 planea_wm = wm_info->max_wm;
1532 }
1533
1534 if (IS_GEN2(dev))
1535 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1536
1537 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1538 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1539 if (intel_crtc_active(crtc)) {
241bfc38 1540 const struct drm_display_mode *adjusted_mode;
59bea882 1541 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1542 if (IS_GEN2(dev))
1543 cpp = 4;
1544
6e3c9717 1545 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1546 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
5aef6003 1548 pessimal_latency_ns);
b445e3b0
ED		 1549 if (enabled == NULL)
1550 enabled = crtc;
1551 else
1552 enabled = NULL;
9d539105 1553 } else {
b445e3b0 1554 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1555 if (planeb_wm > (long)wm_info->max_wm)
1556 planeb_wm = wm_info->max_wm;
1557 }
b445e3b0
ED		 1558
1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1560
2ab1bc9d 1561 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1562 struct drm_i915_gem_object *obj;
2ab1bc9d 1563
59bea882 1564 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1565
1566 /* self-refresh seems busted with untiled */
2ff8fde1 1567 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1568 enabled = NULL;
1569 }
1570
b445e3b0
ED		 1571 /*
1572 * Overlay gets an aggressive default since video jitter is bad.
1573 */
1574 cwm = 2;
1575
1576 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1577 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1578
1579 /* Calc sr entries for one plane configs */
1580 if (HAS_FW_BLC(dev) && enabled) {
1581 /* self-refresh has much higher latency */
1582 static const int sr_latency_ns = 6000;
124abe07 1583 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1584 int clock = adjusted_mode->crtc_clock;
fec8cba3 1585 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1586 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1587 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1588 unsigned long line_time_us;
1589 int entries;
1590
922044c9 1591 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1592
1593 /* Use ns/us then divide to preserve precision */
1594 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1595 pixel_size * hdisplay;
1596 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1598 srwm = wm_info->fifo_size - entries;
1599 if (srwm < 0)
1600 srwm = 1;
1601
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1605 else if (IS_I915GM(dev))
1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1607 }
1608
1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1610 planea_wm, planeb_wm, cwm, srwm);
1611
1612 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1613 fwater_hi = (cwm & 0x1f);
1614
1615 /* Set request length to 8 cachelines per fetch */
1616 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1617 fwater_hi = fwater_hi | (1 << 8);
1618
1619 I915_WRITE(FW_BLC, fwater_lo);
1620 I915_WRITE(FW_BLC2, fwater_hi);
1621
5209b1f4
ID		 1622 if (enabled)
1623 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
6e3c9717 1639 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1643 4, pessimal_latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
8cfb3407 1652uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1653{
fd4daa9c 1654 uint32_t pixel_rate;
801bcfff 1655
8cfb3407 1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1657
1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659 * adjust the pixel_rate here. */
1660
8cfb3407 1661 if (pipe_config->pch_pfit.enabled) {
801bcfff 1662 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1663 uint32_t pfit_size = pipe_config->pch_pfit.size;
1664
1665 pipe_w = pipe_config->pipe_src_w;
1666 pipe_h = pipe_config->pipe_src_h;
801bcfff 1667
801bcfff
PZ		 1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
1675 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1676 pfit_w * pfit_h);
1677 }
1678
1679 return pixel_rate;
1680}
1681
37126462 1682/* latency must be in 0.1us units. */
23297044 1683static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1684 uint32_t latency)
1685{
1686 uint64_t ret;
1687
3312ba65
VS		 1688 if (WARN(latency == 0, "Latency value missing\n"))
1689 return UINT_MAX;
1690
801bcfff
PZ		 1691 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1693
1694 return ret;
1695}
1696
37126462 1697/* latency must be in 0.1us units. */
23297044 1698static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1699 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1700 uint32_t latency)
1701{
1702 uint32_t ret;
1703
3312ba65
VS		 1704 if (WARN(latency == 0, "Latency value missing\n"))
1705 return UINT_MAX;
1706
801bcfff
PZ		 1707 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709 ret = DIV_ROUND_UP(ret, 64) + 2;
1710 return ret;
1711}
1712
23297044 1713static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1714 uint8_t bytes_per_pixel)
1715{
1716 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1717}
1718
820c1980 1719struct ilk_wm_maximums {
cca32e9a
PZ		 1720 uint16_t pri;
1721 uint16_t spr;
1722 uint16_t cur;
1723 uint16_t fbc;
1724};
1725
37126462
VS		 1726/*
1727 * For both WM_PIPE and WM_LP.
1728 * mem_value must be in 0.1us units.
1729 */
7221fc33 1730static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1731 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1732 uint32_t mem_value,
1733 bool is_lp)
801bcfff 1734{
43d59eda 1735 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1736 uint32_t method1, method2;
1737
7221fc33 1738 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1739 return 0;
1740
7221fc33 1741 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1742
1743 if (!is_lp)
1744 return method1;
1745
7221fc33
MR		 1746 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1747 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1748 drm_rect_width(&pstate->dst),
1749 bpp,
cca32e9a
PZ		 1750 mem_value);
1751
1752 return min(method1, method2);
801bcfff
PZ		 1753}
1754
37126462
VS		 1755/*
1756 * For both WM_PIPE and WM_LP.
1757 * mem_value must be in 0.1us units.
1758 */
7221fc33 1759static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1760 const struct intel_plane_state *pstate,
801bcfff
PZ		 1761 uint32_t mem_value)
1762{
43d59eda 1763 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1764 uint32_t method1, method2;
1765
7221fc33 1766 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1767 return 0;
1768
7221fc33
MR		 1769 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1770 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1771 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1772 drm_rect_width(&pstate->dst),
1773 bpp,
801bcfff
PZ		 1774 mem_value);
1775 return min(method1, method2);
1776}
1777
37126462
VS		 1778/*
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1781 */
7221fc33 1782static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1783 const struct intel_plane_state *pstate,
801bcfff
PZ		 1784 uint32_t mem_value)
1785{
43d59eda
MR		 1786 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1787
7221fc33 1788 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1789 return 0;
1790
7221fc33
MR		 1791 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1792 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1793 drm_rect_width(&pstate->dst),
1794 bpp,
801bcfff
PZ		 1795 mem_value);
1796}
1797
cca32e9a 1798/* Only for WM_LP. */
7221fc33 1799static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1800 const struct intel_plane_state *pstate,
1fda9882 1801 uint32_t pri_val)
cca32e9a 1802{
43d59eda
MR		 1803 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1804
7221fc33 1805 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1806 return 0;
1807
43d59eda 1808 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1809}
1810
158ae64f
VS		 1811static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1812{
416f4727
VS		 1813 if (INTEL_INFO(dev)->gen >= 8)
1814 return 3072;
1815 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1816 return 768;
1817 else
1818 return 512;
1819}
1820
4e975081
VS		 1821static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1822 int level, bool is_sprite)
1823{
1824 if (INTEL_INFO(dev)->gen >= 8)
1825 /* BDW primary/sprite plane watermarks */
1826 return level == 0 ? 255 : 2047;
1827 else if (INTEL_INFO(dev)->gen >= 7)
1828 /* IVB/HSW primary/sprite plane watermarks */
1829 return level == 0 ? 127 : 1023;
1830 else if (!is_sprite)
1831 /* ILK/SNB primary plane watermarks */
1832 return level == 0 ? 127 : 511;
1833 else
1834 /* ILK/SNB sprite plane watermarks */
1835 return level == 0 ? 63 : 255;
1836}
1837
1838static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1839 int level)
1840{
1841 if (INTEL_INFO(dev)->gen >= 7)
1842 return level == 0 ? 63 : 255;
1843 else
1844 return level == 0 ? 31 : 63;
1845}
1846
1847static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1848{
1849 if (INTEL_INFO(dev)->gen >= 8)
1850 return 31;
1851 else
1852 return 15;
1853}
1854
158ae64f
VS		 1855/* Calculate the maximum primary/sprite plane watermark */
1856static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1857 int level,
240264f4 1858 const struct intel_wm_config *config,
158ae64f
VS		 1859 enum intel_ddb_partitioning ddb_partitioning,
1860 bool is_sprite)
1861{
1862 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1863
1864 /* if sprites aren't enabled, sprites get nothing */
240264f4 1865 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1866 return 0;
1867
1868 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1869 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1870 fifo_size /= INTEL_INFO(dev)->num_pipes;
1871
1872 /*
1873 * For some reason the non self refresh
1874 * FIFO size is only half of the self
1875 * refresh FIFO size on ILK/SNB.
1876 */
1877 if (INTEL_INFO(dev)->gen <= 6)
1878 fifo_size /= 2;
1879 }
1880
240264f4 1881 if (config->sprites_enabled) {
158ae64f
VS		 1882 /* level 0 is always calculated with 1:1 split */
1883 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1884 if (is_sprite)
1885 fifo_size *= 5;
1886 fifo_size /= 6;
1887 } else {
1888 fifo_size /= 2;
1889 }
1890 }
1891
1892 /* clamp to max that the registers can hold */
4e975081 1893 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1894}
1895
1896/* Calculate the maximum cursor plane watermark */
1897static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1898 int level,
1899 const struct intel_wm_config *config)
158ae64f
VS		 1900{
1901 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1902 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1903 return 64;
1904
1905 /* otherwise just report max that registers can hold */
4e975081 1906 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1907}
1908
d34ff9c6 1909static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1910 int level,
1911 const struct intel_wm_config *config,
1912 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1913 struct ilk_wm_maximums *max)
158ae64f 1914{
240264f4
VS		 1915 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1916 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1917 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1918 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1919}
1920
a3cb4048
VS		 1921static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1922 int level,
1923 struct ilk_wm_maximums *max)
1924{
1925 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1926 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1927 max->cur = ilk_cursor_wm_reg_max(dev, level);
1928 max->fbc = ilk_fbc_wm_reg_max(dev);
1929}
1930
d9395655 1931static bool ilk_validate_wm_level(int level,
820c1980 1932 const struct ilk_wm_maximums *max,
d9395655 1933 struct intel_wm_level *result)
a9786a11
VS		 1934{
1935 bool ret;
1936
1937 /* already determined to be invalid? */
1938 if (!result->enable)
1939 return false;
1940
1941 result->enable = result->pri_val <= max->pri &&
1942 result->spr_val <= max->spr &&
1943 result->cur_val <= max->cur;
1944
1945 ret = result->enable;
1946
1947 /*
1948 * HACK until we can pre-compute everything,
1949 * and thus fail gracefully if LP0 watermarks
1950 * are exceeded...
1951 */
1952 if (level == 0 && !result->enable) {
1953 if (result->pri_val > max->pri)
1954 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1955 level, result->pri_val, max->pri);
1956 if (result->spr_val > max->spr)
1957 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1958 level, result->spr_val, max->spr);
1959 if (result->cur_val > max->cur)
1960 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1961 level, result->cur_val, max->cur);
1962
1963 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1964 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1965 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1966 result->enable = true;
1967 }
1968
a9786a11
VS		 1969 return ret;
1970}
1971
d34ff9c6 1972static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1973 const struct intel_crtc *intel_crtc,
6f5ddd17 1974 int level,
7221fc33 1975 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1976 struct intel_plane_state *pristate,
1977 struct intel_plane_state *sprstate,
1978 struct intel_plane_state *curstate,
1fd527cc 1979 struct intel_wm_level *result)
6f5ddd17
VS		 1980{
1981 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1982 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1983 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1984
1985 /* WM1+ latency values stored in 0.5us units */
1986 if (level > 0) {
1987 pri_latency *= 5;
1988 spr_latency *= 5;
1989 cur_latency *= 5;
1990 }
1991
86c8bbbe
MR		 1992 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
1993 pri_latency, level);
1994 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
1995 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
1996 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 1997 result->enable = true;
1998}
1999
801bcfff
PZ		 2000static uint32_t
2001hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2002{
2003 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 2005 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2006 u32 linetime, ips_linetime;
1f8eeabf 2007
3ef00284 2008 if (!intel_crtc->active)
801bcfff 2009 return 0;
1011d8c4 2010
1f8eeabf
ED		 2011 /* The WM are computed with base on how long it takes to fill a single
2012 * row at the given clock rate, multiplied by 8.
2013 * */
124abe07
VS		 2014 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2015 adjusted_mode->crtc_clock);
2016 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2017 dev_priv->cdclk_freq);
1f8eeabf 2018
801bcfff
PZ		 2019 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2020 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2021}
2022
2af30a5c 2023static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2024{
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026
2af30a5c
PB		 2027 if (IS_GEN9(dev)) {
2028 uint32_t val;
4f947386 2029 int ret, i;
367294be 2030 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2031
2032 /* read the first set of memory latencies[0:3] */
2033 val = 0; /* data0 to be programmed to 0 for first set */
2034 mutex_lock(&dev_priv->rps.hw_lock);
2035 ret = sandybridge_pcode_read(dev_priv,
2036 GEN9_PCODE_READ_MEM_LATENCY,
2037 &val);
2038 mutex_unlock(&dev_priv->rps.hw_lock);
2039
2040 if (ret) {
2041 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2042 return;
2043 }
2044
2045 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2046 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2047 GEN9_MEM_LATENCY_LEVEL_MASK;
2048 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2049 GEN9_MEM_LATENCY_LEVEL_MASK;
2050 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2051 GEN9_MEM_LATENCY_LEVEL_MASK;
2052
2053 /* read the second set of memory latencies[4:7] */
2054 val = 1; /* data0 to be programmed to 1 for second set */
2055 mutex_lock(&dev_priv->rps.hw_lock);
2056 ret = sandybridge_pcode_read(dev_priv,
2057 GEN9_PCODE_READ_MEM_LATENCY,
2058 &val);
2059 mutex_unlock(&dev_priv->rps.hw_lock);
2060 if (ret) {
2061 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2062 return;
2063 }
2064
2065 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2066 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2067 GEN9_MEM_LATENCY_LEVEL_MASK;
2068 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2069 GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072
367294be 2073 /*
6f97235b
DL		 2074 * WaWmMemoryReadLatency:skl
2075 *
367294be
VK		 2076 * punit doesn't take into account the read latency so we need
2077 * to add 2us to the various latency levels we retrieve from
2078 * the punit.
2079 * - W0 is a bit special in that it's the only level that
2080 * can't be disabled if we want to have display working, so
2081 * we always add 2us there.
2082 * - For levels >=1, punit returns 0us latency when they are
2083 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2084 *
2085 * Additionally, if a level n (n > 1) has a 0us latency, all
2086 * levels m (m >= n) need to be disabled. We make sure to
2087 * sanitize the values out of the punit to satisfy this
2088 * requirement.
367294be
VK		 2089 */
2090 wm[0] += 2;
2091 for (level = 1; level <= max_level; level++)
2092 if (wm[level] != 0)
2093 wm[level] += 2;
4f947386
VK		 2094 else {
2095 for (i = level + 1; i <= max_level; i++)
2096 wm[i] = 0;
367294be 2097
4f947386
VK		 2098 break;
2099 }
2af30a5c 2100 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2101 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2102
2103 wm[0] = (sskpd >> 56) & 0xFF;
2104 if (wm[0] == 0)
2105 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2106 wm[1] = (sskpd >> 4) & 0xFF;
2107 wm[2] = (sskpd >> 12) & 0xFF;
2108 wm[3] = (sskpd >> 20) & 0x1FF;
2109 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2110 } else if (INTEL_INFO(dev)->gen >= 6) {
2111 uint32_t sskpd = I915_READ(MCH_SSKPD);
2112
2113 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2114 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2115 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2116 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2117 } else if (INTEL_INFO(dev)->gen >= 5) {
2118 uint32_t mltr = I915_READ(MLTR_ILK);
2119
2120 /* ILK primary LP0 latency is 700 ns */
2121 wm[0] = 7;
2122 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2123 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2124 }
2125}
2126
53615a5e
VS		 2127static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2128{
2129 /* ILK sprite LP0 latency is 1300 ns */
2130 if (INTEL_INFO(dev)->gen == 5)
2131 wm[0] = 13;
2132}
2133
2134static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2135{
2136 /* ILK cursor LP0 latency is 1300 ns */
2137 if (INTEL_INFO(dev)->gen == 5)
2138 wm[0] = 13;
2139
2140 /* WaDoubleCursorLP3Latency:ivb */
2141 if (IS_IVYBRIDGE(dev))
2142 wm[3] *= 2;
2143}
2144
546c81fd 2145int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2146{
26ec971e 2147 /* how many WM levels are we expecting */
b6e742f6 2148 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2149 return 7;
2150 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2151 return 4;
26ec971e 2152 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2153 return 3;
26ec971e 2154 else
ad0d6dc4
VS		 2155 return 2;
2156}
7526ed79 2157
ad0d6dc4
VS		 2158static void intel_print_wm_latency(struct drm_device *dev,
2159 const char *name,
2af30a5c 2160 const uint16_t wm[8])
ad0d6dc4
VS		 2161{
2162 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2163
2164 for (level = 0; level <= max_level; level++) {
2165 unsigned int latency = wm[level];
2166
2167 if (latency == 0) {
2168 DRM_ERROR("%s WM%d latency not provided\n",
2169 name, level);
2170 continue;
2171 }
2172
2af30a5c
PB		 2173 /*
2174 * - latencies are in us on gen9.
2175 * - before then, WM1+ latency values are in 0.5us units
2176 */
2177 if (IS_GEN9(dev))
2178 latency *= 10;
2179 else if (level > 0)
26ec971e
VS		 2180 latency *= 5;
2181
2182 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2183 name, level, wm[level],
2184 latency / 10, latency % 10);
2185 }
2186}
2187
e95a2f75
VS		 2188static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2189 uint16_t wm[5], uint16_t min)
2190{
2191 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2192
2193 if (wm[0] >= min)
2194 return false;
2195
2196 wm[0] = max(wm[0], min);
2197 for (level = 1; level <= max_level; level++)
2198 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2199
2200 return true;
2201}
2202
2203static void snb_wm_latency_quirk(struct drm_device *dev)
2204{
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 bool changed;
2207
2208 /*
2209 * The BIOS provided WM memory latency values are often
2210 * inadequate for high resolution displays. Adjust them.
2211 */
2212 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2213 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2214 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2215
2216 if (!changed)
2217 return;
2218
2219 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2220 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2221 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2222 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2223}
2224
fa50ad61 2225static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2226{
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2230
2231 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2232 sizeof(dev_priv->wm.pri_latency));
2233 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2234 sizeof(dev_priv->wm.pri_latency));
2235
2236 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2237 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2238
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2242
2243 if (IS_GEN6(dev))
2244 snb_wm_latency_quirk(dev);
53615a5e
VS		 2245}
2246
2af30a5c
PB		 2247static void skl_setup_wm_latency(struct drm_device *dev)
2248{
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250
2251 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2252 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2253}
2254
0b2ae6d7 2255/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2256static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2257 struct drm_atomic_state *state)
0b2ae6d7 2258{
86c8bbbe
MR		 2259 struct intel_pipe_wm *pipe_wm;
2260 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2261 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2262 struct intel_crtc_state *cstate = NULL;
43d59eda 2263 struct intel_plane *intel_plane;
86c8bbbe
MR		 2264 struct drm_plane_state *ps;
2265 struct intel_plane_state *pristate = NULL;
43d59eda 2266 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2267 struct intel_plane_state *curstate = NULL;
0b2ae6d7
VS		 2268 int level, max_level = ilk_wm_max_level(dev);
2269 /* LP0 watermark maximums depend on this pipe alone */
2270 struct intel_wm_config config = {
2271 .num_pipes_active = 1,
0b2ae6d7 2272 };
820c1980 2273 struct ilk_wm_maximums max;
0b2ae6d7 2274
86c8bbbe
MR		 2275 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2276 if (IS_ERR(cstate))
2277 return PTR_ERR(cstate);
2278
2279 pipe_wm = &cstate->wm.optimal.ilk;
2280
43d59eda 2281 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2282 ps = drm_atomic_get_plane_state(state,
2283 &intel_plane->base);
2284 if (IS_ERR(ps))
2285 return PTR_ERR(ps);
2286
2287 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2288 pristate = to_intel_plane_state(ps);
2289 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2290 sprstate = to_intel_plane_state(ps);
2291 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2292 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2293 }
2294
2295 config.sprites_enabled = sprstate->visible;
2296 config.sprites_scaled = sprstate->visible &&
2297 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2298 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2299
7221fc33 2300 pipe_wm->pipe_enabled = cstate->base.active;
86c8bbbe 2301 pipe_wm->sprites_enabled = config.sprites_enabled;
43d59eda 2302 pipe_wm->sprites_scaled = config.sprites_scaled;
2a44b76b 2303
7b39a0b7 2304 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2305 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2306 max_level = 1;
2307
2308 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
43d59eda 2309 if (config.sprites_scaled)
7b39a0b7
VS		 2310 max_level = 0;
2311
86c8bbbe
MR		 2312 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2313 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2314
a42a5719 2315 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
86c8bbbe
MR		 2316 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2317 &intel_crtc->base);
0b2ae6d7 2318
a3cb4048
VS		 2319 /* LP0 watermarks always use 1/2 DDB partitioning */
2320 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2321
0b2ae6d7 2322 /* At least LP0 must be valid */
a3cb4048 2323 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
86c8bbbe 2324 return -EINVAL;
a3cb4048
VS		 2325
2326 ilk_compute_wm_reg_maximums(dev, 1, &max);
2327
2328 for (level = 1; level <= max_level; level++) {
2329 struct intel_wm_level wm = {};
2330
86c8bbbe
MR		 2331 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2332 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2333
2334 /*
2335 * Disable any watermark level that exceeds the
2336 * register maximums since such watermarks are
2337 * always invalid.
2338 */
2339 if (!ilk_validate_wm_level(level, &max, &wm))
2340 break;
2341
2342 pipe_wm->wm[level] = wm;
2343 }
2344
86c8bbbe 2345 return 0;
0b2ae6d7
VS		 2346}
2347
2348/*
2349 * Merge the watermarks from all active pipes for a specific level.
2350 */
2351static void ilk_merge_wm_level(struct drm_device *dev,
2352 int level,
2353 struct intel_wm_level *ret_wm)
2354{
2355 const struct intel_crtc *intel_crtc;
2356
d52fea5b
VS		 2357 ret_wm->enable = true;
2358
d3fcc808 2359 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2360 const struct intel_crtc_state *cstate =
2361 to_intel_crtc_state(intel_crtc->base.state);
2362 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2363 const struct intel_wm_level *wm = &active->wm[level];
2364
2365 if (!active->pipe_enabled)
2366 continue;
0b2ae6d7 2367
d52fea5b
VS		 2368 /*
2369 * The watermark values may have been used in the past,
2370 * so we must maintain them in the registers for some
2371 * time even if the level is now disabled.
2372 */
0b2ae6d7 2373 if (!wm->enable)
d52fea5b 2374 ret_wm->enable = false;
0b2ae6d7
VS		 2375
2376 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2377 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2378 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2379 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2380 }
0b2ae6d7
VS		 2381}
2382
2383/*
2384 * Merge all low power watermarks for all active pipes.
2385 */
2386static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2387 const struct intel_wm_config *config,
820c1980 2388 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2389 struct intel_pipe_wm *merged)
2390{
7733b49b 2391 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2392 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2393 int last_enabled_level = max_level;
0b2ae6d7 2394
0ba22e26
VS		 2395 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2396 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2397 config->num_pipes_active > 1)
2398 return;
2399
6c8b6c28
VS		 2400 /* ILK: FBC WM must be disabled always */
2401 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2402
2403 /* merge each WM1+ level */
2404 for (level = 1; level <= max_level; level++) {
2405 struct intel_wm_level *wm = &merged->wm[level];
2406
2407 ilk_merge_wm_level(dev, level, wm);
2408
d52fea5b
VS		 2409 if (level > last_enabled_level)
2410 wm->enable = false;
2411 else if (!ilk_validate_wm_level(level, max, wm))
2412 /* make sure all following levels get disabled */
2413 last_enabled_level = level - 1;
0b2ae6d7
VS		 2414
2415 /*
2416 * The spec says it is preferred to disable
2417 * FBC WMs instead of disabling a WM level.
2418 */
2419 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2420 if (wm->enable)
2421 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2422 wm->fbc_val = 0;
2423 }
2424 }
6c8b6c28
VS		 2425
2426 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2427 /*
2428 * FIXME this is racy. FBC might get enabled later.
2429 * What we should check here is whether FBC can be
2430 * enabled sometime later.
2431 */
7733b49b 2432 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2433 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2434 for (level = 2; level <= max_level; level++) {
2435 struct intel_wm_level *wm = &merged->wm[level];
2436
2437 wm->enable = false;
2438 }
2439 }
0b2ae6d7
VS		 2440}
2441
b380ca3c
VS		 2442static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2443{
2444 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2445 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2446}
2447
a68d68ee
VS		 2448/* The value we need to program into the WM_LPx latency field */
2449static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2450{
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452
a42a5719 2453 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2454 return 2 * level;
2455 else
2456 return dev_priv->wm.pri_latency[level];
2457}
2458
820c1980 2459static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2460 const struct intel_pipe_wm *merged,
609cedef 2461 enum intel_ddb_partitioning partitioning,
820c1980 2462 struct ilk_wm_values *results)
801bcfff 2463{
0b2ae6d7
VS		 2464 struct intel_crtc *intel_crtc;
2465 int level, wm_lp;
cca32e9a 2466
0362c781 2467 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2468 results->partitioning = partitioning;
cca32e9a 2469
0b2ae6d7 2470 /* LP1+ register values */
cca32e9a 2471 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2472 const struct intel_wm_level *r;
801bcfff 2473
b380ca3c 2474 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2475
0362c781 2476 r = &merged->wm[level];
cca32e9a 2477
d52fea5b
VS		 2478 /*
2479 * Maintain the watermark values even if the level is
2480 * disabled. Doing otherwise could cause underruns.
2481 */
2482 results->wm_lp[wm_lp - 1] =
a68d68ee 2483 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2484 (r->pri_val << WM1_LP_SR_SHIFT) |
2485 r->cur_val;
2486
d52fea5b
VS		 2487 if (r->enable)
2488 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2489
416f4727
VS		 2490 if (INTEL_INFO(dev)->gen >= 8)
2491 results->wm_lp[wm_lp - 1] |=
2492 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2493 else
2494 results->wm_lp[wm_lp - 1] |=
2495 r->fbc_val << WM1_LP_FBC_SHIFT;
2496
d52fea5b
VS		 2497 /*
2498 * Always set WM1S_LP_EN when spr_val != 0, even if the
2499 * level is disabled. Doing otherwise could cause underruns.
2500 */
6cef2b8a
VS		 2501 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2502 WARN_ON(wm_lp != 1);
2503 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2504 } else
2505 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2506 }
801bcfff 2507
0b2ae6d7 2508 /* LP0 register values */
d3fcc808 2509 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2510 const struct intel_crtc_state *cstate =
2511 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2512 enum pipe pipe = intel_crtc->pipe;
4e0963c7 2513 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2514
2515 if (WARN_ON(!r->enable))
2516 continue;
2517
4e0963c7 2518 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2519
0b2ae6d7
VS		 2520 results->wm_pipe[pipe] =
2521 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2522 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2523 r->cur_val;
801bcfff
PZ		 2524 }
2525}
2526
861f3389
PZ		 2527/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2528 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2529static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2530 struct intel_pipe_wm *r1,
2531 struct intel_pipe_wm *r2)
861f3389 2532{
198a1e9b
VS		 2533 int level, max_level = ilk_wm_max_level(dev);
2534 int level1 = 0, level2 = 0;
861f3389 2535
198a1e9b
VS		 2536 for (level = 1; level <= max_level; level++) {
2537 if (r1->wm[level].enable)
2538 level1 = level;
2539 if (r2->wm[level].enable)
2540 level2 = level;
861f3389
PZ		 2541 }
2542
198a1e9b
VS		 2543 if (level1 == level2) {
2544 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2545 return r2;
2546 else
2547 return r1;
198a1e9b 2548 } else if (level1 > level2) {
861f3389
PZ		 2549 return r1;
2550 } else {
2551 return r2;
2552 }
2553}
2554
49a687c4
VS		 2555/* dirty bits used to track which watermarks need changes */
2556#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2557#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2558#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2559#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2560#define WM_DIRTY_FBC (1 << 24)
2561#define WM_DIRTY_DDB (1 << 25)
2562
055e393f 2563static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2564 const struct ilk_wm_values *old,
2565 const struct ilk_wm_values *new)
49a687c4
VS		 2566{
2567 unsigned int dirty = 0;
2568 enum pipe pipe;
2569 int wm_lp;
2570
055e393f 2571 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2572 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2573 dirty |= WM_DIRTY_LINETIME(pipe);
2574 /* Must disable LP1+ watermarks too */
2575 dirty |= WM_DIRTY_LP_ALL;
2576 }
2577
2578 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2579 dirty |= WM_DIRTY_PIPE(pipe);
2580 /* Must disable LP1+ watermarks too */
2581 dirty |= WM_DIRTY_LP_ALL;
2582 }
2583 }
2584
2585 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2586 dirty |= WM_DIRTY_FBC;
2587 /* Must disable LP1+ watermarks too */
2588 dirty |= WM_DIRTY_LP_ALL;
2589 }
2590
2591 if (old->partitioning != new->partitioning) {
2592 dirty |= WM_DIRTY_DDB;
2593 /* Must disable LP1+ watermarks too */
2594 dirty |= WM_DIRTY_LP_ALL;
2595 }
2596
2597 /* LP1+ watermarks already deemed dirty, no need to continue */
2598 if (dirty & WM_DIRTY_LP_ALL)
2599 return dirty;
2600
2601 /* Find the lowest numbered LP1+ watermark in need of an update... */
2602 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2603 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2604 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2605 break;
2606 }
2607
2608 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2609 for (; wm_lp <= 3; wm_lp++)
2610 dirty |= WM_DIRTY_LP(wm_lp);
2611
2612 return dirty;
2613}
2614
8553c18e
VS		 2615static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2616 unsigned int dirty)
801bcfff 2617{
820c1980 2618 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2619 bool changed = false;
801bcfff 2620
facd619b
VS		 2621 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2622 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2623 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2624 changed = true;
facd619b
VS		 2625 }
2626 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2627 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2628 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2629 changed = true;
facd619b
VS		 2630 }
2631 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2632 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2633 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2634 changed = true;
facd619b 2635 }
801bcfff 2636
facd619b
VS		 2637 /*
2638 * Don't touch WM1S_LP_EN here.
2639 * Doing so could cause underruns.
2640 */
6cef2b8a 2641
8553c18e
VS		 2642 return changed;
2643}
2644
2645/*
2646 * The spec says we shouldn't write when we don't need, because every write
2647 * causes WMs to be re-evaluated, expending some power.
2648 */
820c1980
ID		 2649static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2650 struct ilk_wm_values *results)
8553c18e
VS		 2651{
2652 struct drm_device *dev = dev_priv->dev;
820c1980 2653 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2654 unsigned int dirty;
2655 uint32_t val;
2656
055e393f 2657 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2658 if (!dirty)
2659 return;
2660
2661 _ilk_disable_lp_wm(dev_priv, dirty);
2662
49a687c4 2663 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2664 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2665 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2666 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2667 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2668 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2669
49a687c4 2670 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2671 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2672 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2673 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2674 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2675 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2676
49a687c4 2677 if (dirty & WM_DIRTY_DDB) {
a42a5719 2678 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2679 val = I915_READ(WM_MISC);
2680 if (results->partitioning == INTEL_DDB_PART_1_2)
2681 val &= ~WM_MISC_DATA_PARTITION_5_6;
2682 else
2683 val |= WM_MISC_DATA_PARTITION_5_6;
2684 I915_WRITE(WM_MISC, val);
2685 } else {
2686 val = I915_READ(DISP_ARB_CTL2);
2687 if (results->partitioning == INTEL_DDB_PART_1_2)
2688 val &= ~DISP_DATA_PARTITION_5_6;
2689 else
2690 val |= DISP_DATA_PARTITION_5_6;
2691 I915_WRITE(DISP_ARB_CTL2, val);
2692 }
1011d8c4
PZ		 2693 }
2694
49a687c4 2695 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2696 val = I915_READ(DISP_ARB_CTL);
2697 if (results->enable_fbc_wm)
2698 val &= ~DISP_FBC_WM_DIS;
2699 else
2700 val |= DISP_FBC_WM_DIS;
2701 I915_WRITE(DISP_ARB_CTL, val);
2702 }
2703
954911eb
ID		 2704 if (dirty & WM_DIRTY_LP(1) &&
2705 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2706 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2707
2708 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2709 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2710 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2711 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2712 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2713 }
801bcfff 2714
facd619b 2715 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2716 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2717 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2718 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2719 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2720 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2721
2722 dev_priv->wm.hw = *results;
801bcfff
PZ		 2723}
2724
8553c18e
VS		 2725static bool ilk_disable_lp_wm(struct drm_device *dev)
2726{
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728
2729 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2730}
2731
b9cec075
DL		 2732/*
2733 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2734 * different active planes.
2735 */
2736
2737#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2738#define BXT_DDB_SIZE 512
b9cec075 2739
024c9045
MR		 2740/*
2741 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2742 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2743 * other universal planes are in indices 1..n. Note that this may leave unused
2744 * indices between the top "sprite" plane and the cursor.
2745 */
2746static int
2747skl_wm_plane_id(const struct intel_plane *plane)
2748{
2749 switch (plane->base.type) {
2750 case DRM_PLANE_TYPE_PRIMARY:
2751 return 0;
2752 case DRM_PLANE_TYPE_CURSOR:
2753 return PLANE_CURSOR;
2754 case DRM_PLANE_TYPE_OVERLAY:
2755 return plane->plane + 1;
2756 default:
2757 MISSING_CASE(plane->base.type);
2758 return plane->plane;
2759 }
2760}
2761
b9cec075
DL		 2762static void
2763skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2764 const struct intel_crtc_state *cstate,
b9cec075 2765 const struct intel_wm_config *config,
b9cec075
DL		 2766 struct skl_ddb_entry *alloc /* out */)
2767{
024c9045 2768 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2769 struct drm_crtc *crtc;
2770 unsigned int pipe_size, ddb_size;
2771 int nth_active_pipe;
2772
024c9045 2773 if (!cstate->base.active) {
b9cec075
DL		 2774 alloc->start = 0;
2775 alloc->end = 0;
2776 return;
2777 }
2778
43d735a6
DL		 2779 if (IS_BROXTON(dev))
2780 ddb_size = BXT_DDB_SIZE;
2781 else
2782 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2783
2784 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2785
2786 nth_active_pipe = 0;
2787 for_each_crtc(dev, crtc) {
3ef00284 2788 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2789 continue;
2790
2791 if (crtc == for_crtc)
2792 break;
2793
2794 nth_active_pipe++;
2795 }
2796
2797 pipe_size = ddb_size / config->num_pipes_active;
2798 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2799 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2800}
2801
2802static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2803{
2804 if (config->num_pipes_active == 1)
2805 return 32;
2806
2807 return 8;
2808}
2809
a269c583
DL		 2810static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2811{
2812 entry->start = reg & 0x3ff;
2813 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2814 if (entry->end)
2815 entry->end += 1;
a269c583
DL		 2816}
2817
08db6652
DL		 2818void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2819 struct skl_ddb_allocation *ddb /* out */)
a269c583 2820{
a269c583
DL		 2821 enum pipe pipe;
2822 int plane;
2823 u32 val;
2824
b10f1b20
ML		 2825 memset(ddb, 0, sizeof(*ddb));
2826
a269c583 2827 for_each_pipe(dev_priv, pipe) {
b10f1b20
ML		 2828 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2829 continue;
2830
dd740780 2831 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2832 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2833 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2834 val);
2835 }
2836
2837 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2838 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2839 val);
a269c583
DL		 2840 }
2841}
2842
b9cec075 2843static unsigned int
024c9045
MR		 2844skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2845 const struct drm_plane_state *pstate,
2846 int y)
b9cec075 2847{
024c9045
MR		 2848 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2849 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2850
2851 /* for planar format */
024c9045 2852 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2853 if (y) /* y-plane data rate */
024c9045
MR		 2854 return intel_crtc->config->pipe_src_w *
2855 intel_crtc->config->pipe_src_h *
2856 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2857 else /* uv-plane data rate */
024c9045
MR		 2858 return (intel_crtc->config->pipe_src_w/2) *
2859 (intel_crtc->config->pipe_src_h/2) *
2860 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2861 }
2862
2863 /* for packed formats */
024c9045
MR		 2864 return intel_crtc->config->pipe_src_w *
2865 intel_crtc->config->pipe_src_h *
2866 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2867}
2868
2869/*
2870 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2871 * a 8192x4096@32bpp framebuffer:
2872 * 3 * 4096 * 8192 * 4 < 2^32
2873 */
2874static unsigned int
024c9045 2875skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2876{
024c9045
MR		 2877 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2878 struct drm_device *dev = intel_crtc->base.dev;
2879 const struct intel_plane *intel_plane;
b9cec075 2880 unsigned int total_data_rate = 0;
b9cec075 2881
024c9045
MR		 2882 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2883 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2884
024c9045 2885 if (pstate->fb == NULL)
b9cec075
DL		 2886 continue;
2887
024c9045
MR		 2888 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2889 continue;
2890
2891 /* packed/uv */
2892 total_data_rate += skl_plane_relative_data_rate(cstate,
2893 pstate,
2894 0);
2895
2896 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2897 /* y-plane */
2898 total_data_rate += skl_plane_relative_data_rate(cstate,
2899 pstate,
2900 1);
b9cec075
DL		 2901 }
2902
2903 return total_data_rate;
2904}
2905
2906static void
024c9045 2907skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2908 struct skl_ddb_allocation *ddb /* out */)
2909{
024c9045 2910 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2911 struct drm_device *dev = crtc->dev;
aa363136
MR		 2912 struct drm_i915_private *dev_priv = to_i915(dev);
2913 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2915 struct intel_plane *intel_plane;
b9cec075 2916 enum pipe pipe = intel_crtc->pipe;
34bb56af 2917 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2918 uint16_t alloc_size, start, cursor_blocks;
80958155 2919 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2920 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2921 unsigned int total_data_rate;
b9cec075 2922
024c9045 2923 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2924 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2925 if (alloc_size == 0) {
2926 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2927 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2928 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2929 return;
2930 }
2931
2932 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2933 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2934 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2935
2936 alloc_size -= cursor_blocks;
34bb56af 2937 alloc->end -= cursor_blocks;
b9cec075 2938
80958155 2939 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2940 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2941 struct drm_plane *plane = &intel_plane->base;
2942 struct drm_framebuffer *fb = plane->state->fb;
2943 int id = skl_wm_plane_id(intel_plane);
80958155 2944
024c9045
MR		 2945 if (fb == NULL)
2946 continue;
2947 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2948 continue;
2949
024c9045
MR		 2950 minimum[id] = 8;
2951 alloc_size -= minimum[id];
2952 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2953 alloc_size -= y_minimum[id];
80958155
DL		 2954 }
2955
b9cec075 2956 /*
80958155
DL		 2957 * 2. Distribute the remaining space in proportion to the amount of
2958 * data each plane needs to fetch from memory.
b9cec075
DL		 2959 *
2960 * FIXME: we may not allocate every single block here.
2961 */
024c9045 2962 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2963
34bb56af 2964 start = alloc->start;
024c9045
MR		 2965 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2966 struct drm_plane *plane = &intel_plane->base;
2967 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2968 unsigned int data_rate, y_data_rate;
2969 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2970 int id = skl_wm_plane_id(intel_plane);
b9cec075 2971
024c9045
MR		 2972 if (pstate->fb == NULL)
2973 continue;
2974 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 2975 continue;
2976
024c9045 2977 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 2978
2979 /*
2cd601c6 2980 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 2981 * promote the expression to 64 bits to avoid overflowing, the
2982 * result is < available as data_rate / total_data_rate < 1
2983 */
024c9045 2984 plane_blocks = minimum[id];
80958155
DL		 2985 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2986 total_data_rate);
b9cec075 2987
024c9045
MR		 2988 ddb->plane[pipe][id].start = start;
2989 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 2990
2991 start += plane_blocks;
2cd601c6
CK		 2992
2993 /*
2994 * allocation for y_plane part of planar format:
2995 */
024c9045
MR		 2996 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
2997 y_data_rate = skl_plane_relative_data_rate(cstate,
2998 pstate,
2999 1);
3000 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3001 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3002 total_data_rate);
3003
024c9045
MR		 3004 ddb->y_plane[pipe][id].start = start;
3005 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3006
3007 start += y_plane_blocks;
3008 }
3009
b9cec075
DL		 3010 }
3011
3012}
3013
5cec258b 3014static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3015{
3016 /* TODO: Take into account the scalers once we support them */
2d112de7 3017 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3018}
3019
3020/*
3021 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3022 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3023 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3024 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3025*/
3026static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3027 uint32_t latency)
3028{
3029 uint32_t wm_intermediate_val, ret;
3030
3031 if (latency == 0)
3032 return UINT_MAX;
3033
d4c2aa60 3034 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3035 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3036
3037 return ret;
3038}
3039
3040static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3041 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3042 uint64_t tiling, uint32_t latency)
2d41c0b5 3043{
d4c2aa60
TU		 3044 uint32_t ret;
3045 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3046 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3047
3048 if (latency == 0)
3049 return UINT_MAX;
3050
3051 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3052
3053 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3054 tiling == I915_FORMAT_MOD_Yf_TILED) {
3055 plane_bytes_per_line *= 4;
3056 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3057 plane_blocks_per_line /= 4;
3058 } else {
3059 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3060 }
3061
2d41c0b5
PB		 3062 wm_intermediate_val = latency * pixel_rate;
3063 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3064 plane_blocks_per_line;
2d41c0b5
PB		 3065
3066 return ret;
3067}
3068
2d41c0b5
PB		 3069static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3070 const struct intel_crtc *intel_crtc)
3071{
3072 struct drm_device *dev = intel_crtc->base.dev;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3075
e6d90023
KM		 3076 /*
3077 * If ddb allocation of pipes changed, it may require recalculation of
3078 * watermarks
3079 */
3080 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3081 return true;
3082
3083 return false;
3084}
3085
d4c2aa60 3086static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3087 struct intel_crtc_state *cstate,
3088 struct intel_plane *intel_plane,
afb024aa 3089 uint16_t ddb_allocation,
d4c2aa60 3090 int level,
afb024aa
DL		 3091 uint16_t *out_blocks, /* out */
3092 uint8_t *out_lines /* out */)
2d41c0b5 3093{
024c9045
MR		 3094 struct drm_plane *plane = &intel_plane->base;
3095 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3096 uint32_t latency = dev_priv->wm.skl_latency[level];
3097 uint32_t method1, method2;
3098 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3099 uint32_t res_blocks, res_lines;
3100 uint32_t selected_result;
2cd601c6 3101 uint8_t bytes_per_pixel;
2d41c0b5 3102
024c9045 3103 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3104 return false;
3105
024c9045
MR		 3106 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3107 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3108 bytes_per_pixel,
d4c2aa60 3109 latency);
024c9045
MR		 3110 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3111 cstate->base.adjusted_mode.crtc_htotal,
3112 cstate->pipe_src_w,
2cd601c6 3113 bytes_per_pixel,
024c9045 3114 fb->modifier[0],
d4c2aa60 3115 latency);
2d41c0b5 3116
024c9045 3117 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3118 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3119
024c9045
MR		 3120 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3121 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3122 uint32_t min_scanlines = 4;
3123 uint32_t y_tile_minimum;
024c9045
MR		 3124 if (intel_rotation_90_or_270(plane->state->rotation)) {
3125 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3126 drm_format_plane_cpp(fb->pixel_format, 1) :
3127 drm_format_plane_cpp(fb->pixel_format, 0);
3128
3129 switch (bpp) {
1fc0a8f7
TU		 3130 case 1:
3131 min_scanlines = 16;
3132 break;
3133 case 2:
3134 min_scanlines = 8;
3135 break;
3136 case 8:
3137 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3138 }
1fc0a8f7
TU		 3139 }
3140 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3141 selected_result = max(method2, y_tile_minimum);
3142 } else {
3143 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3144 selected_result = min(method1, method2);
3145 else
3146 selected_result = method1;
3147 }
2d41c0b5 3148
d4c2aa60
TU		 3149 res_blocks = selected_result + 1;
3150 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3151
0fda6568 3152 if (level >= 1 && level <= 7) {
024c9045
MR		 3153 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3154 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3155 res_lines += 4;
3156 else
3157 res_blocks++;
3158 }
e6d66171 3159
d4c2aa60 3160 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3161 return false;
3162
3163 *out_blocks = res_blocks;
3164 *out_lines = res_lines;
2d41c0b5
PB		 3165
3166 return true;
3167}
3168
3169static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3170 struct skl_ddb_allocation *ddb,
024c9045 3171 struct intel_crtc_state *cstate,
2d41c0b5 3172 int level,
2d41c0b5
PB		 3173 struct skl_wm_level *result)
3174{
024c9045
MR		 3175 struct drm_device *dev = dev_priv->dev;
3176 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3177 struct intel_plane *intel_plane;
2d41c0b5 3178 uint16_t ddb_blocks;
024c9045
MR		 3179 enum pipe pipe = intel_crtc->pipe;
3180
3181 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3182 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3183
2d41c0b5
PB		 3184 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3185
d4c2aa60 3186 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3187 cstate,
3188 intel_plane,
2d41c0b5 3189 ddb_blocks,
d4c2aa60 3190 level,
2d41c0b5
PB		 3191 &result->plane_res_b[i],
3192 &result->plane_res_l[i]);
3193 }
2d41c0b5
PB		 3194}
3195
407b50f3 3196static uint32_t
024c9045 3197skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3198{
024c9045 3199 if (!cstate->base.active)
407b50f3
DL		 3200 return 0;
3201
024c9045 3202 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3203 return 0;
407b50f3 3204
024c9045
MR		 3205 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3206 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3207}
3208
024c9045 3209static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3210 struct skl_wm_level *trans_wm /* out */)
407b50f3 3211{
024c9045 3212 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3214 struct intel_plane *intel_plane;
9414f563 3215
024c9045 3216 if (!cstate->base.active)
407b50f3 3217 return;
9414f563
DL		 3218
3219 /* Until we know more, just disable transition WMs */
024c9045
MR		 3220 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3221 int i = skl_wm_plane_id(intel_plane);
3222
9414f563 3223 trans_wm->plane_en[i] = false;
024c9045 3224 }
407b50f3
DL		 3225}
3226
024c9045 3227static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3228 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3229 struct skl_pipe_wm *pipe_wm)
3230{
024c9045 3231 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3232 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3233 int level, max_level = ilk_wm_max_level(dev);
3234
3235 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3236 skl_compute_wm_level(dev_priv, ddb, cstate,
3237 level, &pipe_wm->wm[level]);
2d41c0b5 3238 }
024c9045 3239 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3240
024c9045 3241 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3242}
3243
3244static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3245 struct skl_pipe_wm *p_wm,
3246 struct skl_wm_values *r,
3247 struct intel_crtc *intel_crtc)
3248{
3249 int level, max_level = ilk_wm_max_level(dev);
3250 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3251 uint32_t temp;
3252 int i;
2d41c0b5
PB		 3253
3254 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3255 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3256 temp = 0;
2d41c0b5
PB		 3257
3258 temp |= p_wm->wm[level].plane_res_l[i] <<
3259 PLANE_WM_LINES_SHIFT;
3260 temp |= p_wm->wm[level].plane_res_b[i];
3261 if (p_wm->wm[level].plane_en[i])
3262 temp |= PLANE_WM_EN;
3263
3264 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3265 }
3266
3267 temp = 0;
2d41c0b5 3268
4969d33e
MR		 3269 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3270 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3271
4969d33e 3272 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3273 temp |= PLANE_WM_EN;
3274
4969d33e 3275 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3276
3277 }
3278
9414f563
DL		 3279 /* transition WMs */
3280 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3281 temp = 0;
3282 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3283 temp |= p_wm->trans_wm.plane_res_b[i];
3284 if (p_wm->trans_wm.plane_en[i])
3285 temp |= PLANE_WM_EN;
3286
3287 r->plane_trans[pipe][i] = temp;
3288 }
3289
3290 temp = 0;
4969d33e
MR		 3291 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3292 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3293 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3294 temp |= PLANE_WM_EN;
3295
4969d33e 3296 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3297
2d41c0b5
PB		 3298 r->wm_linetime[pipe] = p_wm->linetime;
3299}
3300
f0f59a00
VS		 3301static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3302 i915_reg_t reg,
16160e3d
DL		 3303 const struct skl_ddb_entry *entry)
3304{
3305 if (entry->end)
3306 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3307 else
3308 I915_WRITE(reg, 0);
3309}
3310
2d41c0b5
PB		 3311static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3312 const struct skl_wm_values *new)
3313{
3314 struct drm_device *dev = dev_priv->dev;
3315 struct intel_crtc *crtc;
3316
3317 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3318 int i, level, max_level = ilk_wm_max_level(dev);
3319 enum pipe pipe = crtc->pipe;
3320
5d374d96
DL		 3321 if (!new->dirty[pipe])
3322 continue;
8211bd5b 3323
5d374d96 3324 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3325
5d374d96
DL		 3326 for (level = 0; level <= max_level; level++) {
3327 for (i = 0; i < intel_num_planes(crtc); i++)
3328 I915_WRITE(PLANE_WM(pipe, i, level),
3329 new->plane[pipe][i][level]);
3330 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3331 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3332 }
5d374d96
DL		 3333 for (i = 0; i < intel_num_planes(crtc); i++)
3334 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3335 new->plane_trans[pipe][i]);
4969d33e
MR		 3336 I915_WRITE(CUR_WM_TRANS(pipe),
3337 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3338
2cd601c6 3339 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3340 skl_ddb_entry_write(dev_priv,
3341 PLANE_BUF_CFG(pipe, i),
3342 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3343 skl_ddb_entry_write(dev_priv,
3344 PLANE_NV12_BUF_CFG(pipe, i),
3345 &new->ddb.y_plane[pipe][i]);
3346 }
5d374d96
DL		 3347
3348 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3349 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3350 }
2d41c0b5
PB		 3351}
3352
0e8fb7ba
DL		 3353/*
3354 * When setting up a new DDB allocation arrangement, we need to correctly
3355 * sequence the times at which the new allocations for the pipes are taken into
3356 * account or we'll have pipes fetching from space previously allocated to
3357 * another pipe.
3358 *
3359 * Roughly the sequence looks like:
3360 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3361 * overlapping with a previous light-up pipe (another way to put it is:
3362 * pipes with their new allocation strickly included into their old ones).
3363 * 2. re-allocate the other pipes that get their allocation reduced
3364 * 3. allocate the pipes having their allocation increased
3365 *
3366 * Steps 1. and 2. are here to take care of the following case:
3367 * - Initially DDB looks like this:
3368 * | B | C |
3369 * - enable pipe A.
3370 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3371 * allocation
3372 * | A | B | C |
3373 *
3374 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3375 */
3376
d21b795c
DL		 3377static void
3378skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3379{
0e8fb7ba
DL		 3380 int plane;
3381
d21b795c
DL		 3382 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3383
dd740780 3384 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3385 I915_WRITE(PLANE_SURF(pipe, plane),
3386 I915_READ(PLANE_SURF(pipe, plane)));
3387 }
3388 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3389}
3390
3391static bool
3392skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3393 const struct skl_ddb_allocation *new,
3394 enum pipe pipe)
3395{
3396 uint16_t old_size, new_size;
3397
3398 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3399 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3400
3401 return old_size != new_size &&
3402 new->pipe[pipe].start >= old->pipe[pipe].start &&
3403 new->pipe[pipe].end <= old->pipe[pipe].end;
3404}
3405
3406static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3407 struct skl_wm_values *new_values)
3408{
3409 struct drm_device *dev = dev_priv->dev;
3410 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3411 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3412 struct intel_crtc *crtc;
3413 enum pipe pipe;
3414
3415 new_ddb = &new_values->ddb;
3416 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3417
3418 /*
3419 * First pass: flush the pipes with the new allocation contained into
3420 * the old space.
3421 *
3422 * We'll wait for the vblank on those pipes to ensure we can safely
3423 * re-allocate the freed space without this pipe fetching from it.
3424 */
3425 for_each_intel_crtc(dev, crtc) {
3426 if (!crtc->active)
3427 continue;
3428
3429 pipe = crtc->pipe;
3430
3431 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3432 continue;
3433
d21b795c 3434 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3435 intel_wait_for_vblank(dev, pipe);
3436
3437 reallocated[pipe] = true;
3438 }
3439
3440
3441 /*
3442 * Second pass: flush the pipes that are having their allocation
3443 * reduced, but overlapping with a previous allocation.
3444 *
3445 * Here as well we need to wait for the vblank to make sure the freed
3446 * space is not used anymore.
3447 */
3448 for_each_intel_crtc(dev, crtc) {
3449 if (!crtc->active)
3450 continue;
3451
3452 pipe = crtc->pipe;
3453
3454 if (reallocated[pipe])
3455 continue;
3456
3457 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3458 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3459 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3460 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3461 reallocated[pipe] = true;
0e8fb7ba 3462 }
0e8fb7ba
DL		 3463 }
3464
3465 /*
3466 * Third pass: flush the pipes that got more space allocated.
3467 *
3468 * We don't need to actively wait for the update here, next vblank
3469 * will just get more DDB space with the correct WM values.
3470 */
3471 for_each_intel_crtc(dev, crtc) {
3472 if (!crtc->active)
3473 continue;
3474
3475 pipe = crtc->pipe;
3476
3477 /*
3478 * At this point, only the pipes more space than before are
3479 * left to re-allocate.
3480 */
3481 if (reallocated[pipe])
3482 continue;
3483
d21b795c 3484 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3485 }
3486}
3487
2d41c0b5 3488static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3489 struct skl_ddb_allocation *ddb, /* out */
3490 struct skl_pipe_wm *pipe_wm /* out */)
3491{
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3493 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3494
aa363136 3495 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3496 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3497
4e0963c7 3498 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3499 return false;
3500
4e0963c7 3501 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3502
2d41c0b5
PB		 3503 return true;
3504}
3505
3506static void skl_update_other_pipe_wm(struct drm_device *dev,
3507 struct drm_crtc *crtc,
2d41c0b5
PB		 3508 struct skl_wm_values *r)
3509{
3510 struct intel_crtc *intel_crtc;
3511 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3512
3513 /*
3514 * If the WM update hasn't changed the allocation for this_crtc (the
3515 * crtc we are currently computing the new WM values for), other
3516 * enabled crtcs will keep the same allocation and we don't need to
3517 * recompute anything for them.
3518 */
3519 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3520 return;
3521
3522 /*
3523 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3524 * other active pipes need new DDB allocation and WM values.
3525 */
3526 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3527 base.head) {
2d41c0b5
PB		 3528 struct skl_pipe_wm pipe_wm = {};
3529 bool wm_changed;
3530
3531 if (this_crtc->pipe == intel_crtc->pipe)
3532 continue;
3533
3534 if (!intel_crtc->active)
3535 continue;
3536
aa363136 3537 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3538 &r->ddb, &pipe_wm);
3539
3540 /*
3541 * If we end up re-computing the other pipe WM values, it's
3542 * because it was really needed, so we expect the WM values to
3543 * be different.
3544 */
3545 WARN_ON(!wm_changed);
3546
024c9045 3547 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3548 r->dirty[intel_crtc->pipe] = true;
3549 }
3550}
3551
adda50b8
BP		 3552static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3553{
3554 watermarks->wm_linetime[pipe] = 0;
3555 memset(watermarks->plane[pipe], 0,
3556 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3557 memset(watermarks->plane_trans[pipe],
3558 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3559 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3560
3561 /* Clear ddb entries for pipe */
3562 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3563 memset(&watermarks->ddb.plane[pipe], 0,
3564 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3565 memset(&watermarks->ddb.y_plane[pipe], 0,
3566 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3567 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3568 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3569
3570}
3571
2d41c0b5
PB		 3572static void skl_update_wm(struct drm_crtc *crtc)
3573{
3574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575 struct drm_device *dev = crtc->dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3577 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3578 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3579 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3580
adda50b8
BP		 3581
3582 /* Clear all dirty flags */
3583 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3584
3585 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3586
aa363136 3587 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3588 return;
3589
4e0963c7 3590 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3591 results->dirty[intel_crtc->pipe] = true;
3592
aa363136 3593 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3594 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3595 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3596
3597 /* store the new configuration */
3598 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3599}
3600
b9d5c839 3601static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3602{
b9d5c839
VS		 3603 struct drm_device *dev = dev_priv->dev;
3604 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3605 struct ilk_wm_maximums max;
aa363136 3606 struct intel_wm_config *config = &dev_priv->wm.config;
820c1980 3607 struct ilk_wm_values results = {};
77c122bc 3608 enum intel_ddb_partitioning partitioning;
261a27d1 3609
aa363136
MR		 3610 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3611 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
a485bfb8
VS		 3612
3613 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3614 if (INTEL_INFO(dev)->gen >= 7 &&
aa363136
MR		 3615 config->num_pipes_active == 1 && config->sprites_enabled) {
3616 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3617 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
0362c781 3618
820c1980 3619 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3620 } else {
198a1e9b 3621 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3622 }
3623
198a1e9b 3624 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3625 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3626
820c1980 3627 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3628
820c1980 3629 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3630}
3631
b9d5c839
VS		 3632static void ilk_update_wm(struct drm_crtc *crtc)
3633{
3634 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3636 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
b9d5c839
VS		 3637
3638 WARN_ON(cstate->base.active != intel_crtc->active);
3639
3640 /*
3641 * IVB workaround: must disable low power watermarks for at least
3642 * one frame before enabling scaling. LP watermarks can be re-enabled
3643 * when scaling is disabled.
3644 *
3645 * WaCxSRDisabledForSpriteScaling:ivb
3646 */
3647 if (cstate->disable_lp_wm) {
3648 ilk_disable_lp_wm(crtc->dev);
3649 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3650 }
3651
4e0963c7 3652 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
b9d5c839
VS		 3653
3654 ilk_program_watermarks(dev_priv);
3655}
3656
3078999f
PB		 3657static void skl_pipe_wm_active_state(uint32_t val,
3658 struct skl_pipe_wm *active,
3659 bool is_transwm,
3660 bool is_cursor,
3661 int i,
3662 int level)
3663{
3664 bool is_enabled = (val & PLANE_WM_EN) != 0;
3665
3666 if (!is_transwm) {
3667 if (!is_cursor) {
3668 active->wm[level].plane_en[i] = is_enabled;
3669 active->wm[level].plane_res_b[i] =
3670 val & PLANE_WM_BLOCKS_MASK;
3671 active->wm[level].plane_res_l[i] =
3672 (val >> PLANE_WM_LINES_SHIFT) &
3673 PLANE_WM_LINES_MASK;
3674 } else {
4969d33e
MR		 3675 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3676 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3677 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3678 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3679 (val >> PLANE_WM_LINES_SHIFT) &
3680 PLANE_WM_LINES_MASK;
3681 }
3682 } else {
3683 if (!is_cursor) {
3684 active->trans_wm.plane_en[i] = is_enabled;
3685 active->trans_wm.plane_res_b[i] =
3686 val & PLANE_WM_BLOCKS_MASK;
3687 active->trans_wm.plane_res_l[i] =
3688 (val >> PLANE_WM_LINES_SHIFT) &
3689 PLANE_WM_LINES_MASK;
3690 } else {
4969d33e
MR		 3691 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3692 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3693 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3694 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3695 (val >> PLANE_WM_LINES_SHIFT) &
3696 PLANE_WM_LINES_MASK;
3697 }
3698 }
3699}
3700
3701static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3702{
3703 struct drm_device *dev = crtc->dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3707 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3708 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3709 enum pipe pipe = intel_crtc->pipe;
3710 int level, i, max_level;
3711 uint32_t temp;
3712
3713 max_level = ilk_wm_max_level(dev);
3714
3715 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3716
3717 for (level = 0; level <= max_level; level++) {
3718 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3719 hw->plane[pipe][i][level] =
3720 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3721 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3722 }
3723
3724 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3725 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3726 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3727
3ef00284 3728 if (!intel_crtc->active)
3078999f
PB		 3729 return;
3730
3731 hw->dirty[pipe] = true;
3732
3733 active->linetime = hw->wm_linetime[pipe];
3734
3735 for (level = 0; level <= max_level; level++) {
3736 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3737 temp = hw->plane[pipe][i][level];
3738 skl_pipe_wm_active_state(temp, active, false,
3739 false, i, level);
3740 }
4969d33e 3741 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3742 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3743 }
3744
3745 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3746 temp = hw->plane_trans[pipe][i];
3747 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3748 }
3749
4969d33e 3750 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3751 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3752
3753 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3754}
3755
3756void skl_wm_get_hw_state(struct drm_device *dev)
3757{
a269c583
DL		 3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3760 struct drm_crtc *crtc;
3761
a269c583 3762 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3763 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3764 skl_pipe_wm_get_hw_state(crtc);
3765}
3766
243e6a44
VS		 3767static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3768{
3769 struct drm_device *dev = crtc->dev;
3770 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3771 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3773 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3774 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3775 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3776 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3777 [PIPE_A] = WM0_PIPEA_ILK,
3778 [PIPE_B] = WM0_PIPEB_ILK,
3779 [PIPE_C] = WM0_PIPEC_IVB,
3780 };
3781
3782 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3783 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3784 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3785
3ef00284 3786 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3787
3788 if (active->pipe_enabled) {
243e6a44
VS		 3789 u32 tmp = hw->wm_pipe[pipe];
3790
3791 /*
3792 * For active pipes LP0 watermark is marked as
3793 * enabled, and LP1+ watermaks as disabled since
3794 * we can't really reverse compute them in case
3795 * multiple pipes are active.
3796 */
3797 active->wm[0].enable = true;
3798 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3799 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3800 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3801 active->linetime = hw->wm_linetime[pipe];
3802 } else {
3803 int level, max_level = ilk_wm_max_level(dev);
3804
3805 /*
3806 * For inactive pipes, all watermark levels
3807 * should be marked as enabled but zeroed,
3808 * which is what we'd compute them to.
3809 */
3810 for (level = 0; level <= max_level; level++)
3811 active->wm[level].enable = true;
3812 }
4e0963c7
MR		 3813
3814 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3815}
3816
6eb1a681
VS		 3817#define _FW_WM(value, plane) \
3818 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3819#define _FW_WM_VLV(value, plane) \
3820 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3821
3822static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3823 struct vlv_wm_values *wm)
3824{
3825 enum pipe pipe;
3826 uint32_t tmp;
3827
3828 for_each_pipe(dev_priv, pipe) {
3829 tmp = I915_READ(VLV_DDL(pipe));
3830
3831 wm->ddl[pipe].primary =
3832 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3833 wm->ddl[pipe].cursor =
3834 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3835 wm->ddl[pipe].sprite[0] =
3836 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3837 wm->ddl[pipe].sprite[1] =
3838 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3839 }
3840
3841 tmp = I915_READ(DSPFW1);
3842 wm->sr.plane = _FW_WM(tmp, SR);
3843 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3844 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3845 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3846
3847 tmp = I915_READ(DSPFW2);
3848 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3849 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3850 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3851
3852 tmp = I915_READ(DSPFW3);
3853 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3854
3855 if (IS_CHERRYVIEW(dev_priv)) {
3856 tmp = I915_READ(DSPFW7_CHV);
3857 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3858 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3859
3860 tmp = I915_READ(DSPFW8_CHV);
3861 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3862 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3863
3864 tmp = I915_READ(DSPFW9_CHV);
3865 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3866 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3867
3868 tmp = I915_READ(DSPHOWM);
3869 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3870 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3871 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3872 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3873 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3874 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3875 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3876 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3877 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3878 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3879 } else {
3880 tmp = I915_READ(DSPFW7);
3881 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3882 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3883
3884 tmp = I915_READ(DSPHOWM);
3885 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3886 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3887 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3888 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3889 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3890 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3891 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3892 }
3893}
3894
3895#undef _FW_WM
3896#undef _FW_WM_VLV
3897
3898void vlv_wm_get_hw_state(struct drm_device *dev)
3899{
3900 struct drm_i915_private *dev_priv = to_i915(dev);
3901 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3902 struct intel_plane *plane;
3903 enum pipe pipe;
3904 u32 val;
3905
3906 vlv_read_wm_values(dev_priv, wm);
3907
3908 for_each_intel_plane(dev, plane) {
3909 switch (plane->base.type) {
3910 int sprite;
3911 case DRM_PLANE_TYPE_CURSOR:
3912 plane->wm.fifo_size = 63;
3913 break;
3914 case DRM_PLANE_TYPE_PRIMARY:
3915 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3916 break;
3917 case DRM_PLANE_TYPE_OVERLAY:
3918 sprite = plane->plane;
3919 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3920 break;
3921 }
3922 }
3923
3924 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3925 wm->level = VLV_WM_LEVEL_PM2;
3926
3927 if (IS_CHERRYVIEW(dev_priv)) {
3928 mutex_lock(&dev_priv->rps.hw_lock);
3929
3930 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3931 if (val & DSP_MAXFIFO_PM5_ENABLE)
3932 wm->level = VLV_WM_LEVEL_PM5;
3933
58590c14
VS		 3934 /*
3935 * If DDR DVFS is disabled in the BIOS, Punit
3936 * will never ack the request. So if that happens
3937 * assume we don't have to enable/disable DDR DVFS
3938 * dynamically. To test that just set the REQ_ACK
3939 * bit to poke the Punit, but don't change the
3940 * HIGH/LOW bits so that we don't actually change
3941 * the current state.
3942 */
6eb1a681 3943 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3944 val |= FORCE_DDR_FREQ_REQ_ACK;
3945 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3946
3947 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3948 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3949 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3950 "assuming DDR DVFS is disabled\n");
3951 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3952 } else {
3953 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3954 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3955 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3956 }
6eb1a681
VS		 3957
3958 mutex_unlock(&dev_priv->rps.hw_lock);
3959 }
3960
3961 for_each_pipe(dev_priv, pipe)
3962 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3963 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3964 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3965
3966 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3967 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3968}
3969
243e6a44
VS		 3970void ilk_wm_get_hw_state(struct drm_device *dev)
3971{
3972 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3973 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3974 struct drm_crtc *crtc;
3975
70e1e0ec 3976 for_each_crtc(dev, crtc)
243e6a44
VS		 3977 ilk_pipe_wm_get_hw_state(crtc);
3978
3979 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3980 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3981 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3982
3983 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3984 if (INTEL_INFO(dev)->gen >= 7) {
3985 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3986 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3987 }
243e6a44 3988
a42a5719 3989 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3990 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3991 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3992 else if (IS_IVYBRIDGE(dev))
3993 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3994 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3995
3996 hw->enable_fbc_wm =
3997 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3998}
3999
b445e3b0
ED		 4000/**
4001 * intel_update_watermarks - update FIFO watermark values based on current modes
4002 *
4003 * Calculate watermark values for the various WM regs based on current mode
4004 * and plane configuration.
4005 *
4006 * There are several cases to deal with here:
4007 * - normal (i.e. non-self-refresh)
4008 * - self-refresh (SR) mode
4009 * - lines are large relative to FIFO size (buffer can hold up to 2)
4010 * - lines are small relative to FIFO size (buffer can hold more than 2
4011 * lines), so need to account for TLB latency
4012 *
4013 * The normal calculation is:
4014 * watermark = dotclock * bytes per pixel * latency
4015 * where latency is platform & configuration dependent (we assume pessimal
4016 * values here).
4017 *
4018 * The SR calculation is:
4019 * watermark = (trunc(latency/line time)+1) * surface width *
4020 * bytes per pixel
4021 * where
4022 * line time = htotal / dotclock
4023 * surface width = hdisplay for normal plane and 64 for cursor
4024 * and latency is assumed to be high, as above.
4025 *
4026 * The final value programmed to the register should always be rounded up,
4027 * and include an extra 2 entries to account for clock crossings.
4028 *
4029 * We don't use the sprite, so we can ignore that. And on Crestline we have
4030 * to set the non-SR watermarks to 8.
4031 */
46ba614c 4032void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4033{
46ba614c 4034 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4035
4036 if (dev_priv->display.update_wm)
46ba614c 4037 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4038}
4039
9270388e
DV		 4040/**
4041 * Lock protecting IPS related data structures
9270388e
DV		 4042 */
4043DEFINE_SPINLOCK(mchdev_lock);
4044
4045/* Global for IPS driver to get at the current i915 device. Protected by
4046 * mchdev_lock. */
4047static struct drm_i915_private *i915_mch_dev;
4048
2b4e57bd
ED		 4049bool ironlake_set_drps(struct drm_device *dev, u8 val)
4050{
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052 u16 rgvswctl;
4053
9270388e
DV		 4054 assert_spin_locked(&mchdev_lock);
4055
2b4e57bd
ED		 4056 rgvswctl = I915_READ16(MEMSWCTL);
4057 if (rgvswctl & MEMCTL_CMD_STS) {
4058 DRM_DEBUG("gpu busy, RCS change rejected\n");
4059 return false; /* still busy with another command */
4060 }
4061
4062 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4063 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4064 I915_WRITE16(MEMSWCTL, rgvswctl);
4065 POSTING_READ16(MEMSWCTL);
4066
4067 rgvswctl |= MEMCTL_CMD_STS;
4068 I915_WRITE16(MEMSWCTL, rgvswctl);
4069
4070 return true;
4071}
4072
8090c6b9 4073static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 u32 rgvmodectl = I915_READ(MEMMODECTL);
4077 u8 fmax, fmin, fstart, vstart;
4078
9270388e
DV		 4079 spin_lock_irq(&mchdev_lock);
4080
2b4e57bd
ED		 4081 /* Enable temp reporting */
4082 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4083 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4084
4085 /* 100ms RC evaluation intervals */
4086 I915_WRITE(RCUPEI, 100000);
4087 I915_WRITE(RCDNEI, 100000);
4088
4089 /* Set max/min thresholds to 90ms and 80ms respectively */
4090 I915_WRITE(RCBMAXAVG, 90000);
4091 I915_WRITE(RCBMINAVG, 80000);
4092
4093 I915_WRITE(MEMIHYST, 1);
4094
4095 /* Set up min, max, and cur for interrupt handling */
4096 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4097 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4098 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4099 MEMMODE_FSTART_SHIFT;
4100
616847e7 4101 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4102 PXVFREQ_PX_SHIFT;
4103
20e4d407
DV		 4104 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4105 dev_priv->ips.fstart = fstart;
2b4e57bd 4106
20e4d407
DV		 4107 dev_priv->ips.max_delay = fstart;
4108 dev_priv->ips.min_delay = fmin;
4109 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4110
4111 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4112 fmax, fmin, fstart);
4113
4114 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4115
4116 /*
4117 * Interrupts will be enabled in ironlake_irq_postinstall
4118 */
4119
4120 I915_WRITE(VIDSTART, vstart);
4121 POSTING_READ(VIDSTART);
4122
4123 rgvmodectl |= MEMMODE_SWMODE_EN;
4124 I915_WRITE(MEMMODECTL, rgvmodectl);
4125
9270388e 4126 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4127 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4128 mdelay(1);
2b4e57bd
ED		 4129
4130 ironlake_set_drps(dev, fstart);
4131
7d81c3e0
VS		 4132 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4133 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4134 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4135 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4136 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4137
4138 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4139}
4140
8090c6b9 4141static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4142{
4143 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4144 u16 rgvswctl;
4145
4146 spin_lock_irq(&mchdev_lock);
4147
4148 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4149
4150 /* Ack interrupts, disable EFC interrupt */
4151 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4152 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4153 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4154 I915_WRITE(DEIIR, DE_PCU_EVENT);
4155 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4156
4157 /* Go back to the starting frequency */
20e4d407 4158 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4159 mdelay(1);
2b4e57bd
ED		 4160 rgvswctl |= MEMCTL_CMD_STS;
4161 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4162 mdelay(1);
2b4e57bd 4163
9270388e 4164 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4165}
4166
acbe9475
DV		 4167/* There's a funny hw issue where the hw returns all 0 when reading from
4168 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4169 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4170 * all limits and the gpu stuck at whatever frequency it is at atm).
4171 */
74ef1173 4172static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4173{
7b9e0ae6 4174 u32 limits;
2b4e57bd 4175
20b46e59
DV		 4176 /* Only set the down limit when we've reached the lowest level to avoid
4177 * getting more interrupts, otherwise leave this clear. This prevents a
4178 * race in the hw when coming out of rc6: There's a tiny window where
4179 * the hw runs at the minimal clock before selecting the desired
4180 * frequency, if the down threshold expires in that window we will not
4181 * receive a down interrupt. */
74ef1173
AG		 4182 if (IS_GEN9(dev_priv->dev)) {
4183 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4184 if (val <= dev_priv->rps.min_freq_softlimit)
4185 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4186 } else {
4187 limits = dev_priv->rps.max_freq_softlimit << 24;
4188 if (val <= dev_priv->rps.min_freq_softlimit)
4189 limits |= dev_priv->rps.min_freq_softlimit << 16;
4190 }
20b46e59
DV		 4191
4192 return limits;
4193}
4194
dd75fdc8
CW		 4195static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4196{
4197 int new_power;
8a586437
AG		 4198 u32 threshold_up = 0, threshold_down = 0; /* in % */
4199 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4200
4201 new_power = dev_priv->rps.power;
4202 switch (dev_priv->rps.power) {
4203 case LOW_POWER:
b39fb297 4204 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4205 new_power = BETWEEN;
4206 break;
4207
4208 case BETWEEN:
b39fb297 4209 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4210 new_power = LOW_POWER;
b39fb297 4211 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4212 new_power = HIGH_POWER;
4213 break;
4214
4215 case HIGH_POWER:
b39fb297 4216 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4217 new_power = BETWEEN;
4218 break;
4219 }
4220 /* Max/min bins are special */
aed242ff 4221 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4222 new_power = LOW_POWER;
aed242ff 4223 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4224 new_power = HIGH_POWER;
4225 if (new_power == dev_priv->rps.power)
4226 return;
4227
4228 /* Note the units here are not exactly 1us, but 1280ns. */
4229 switch (new_power) {
4230 case LOW_POWER:
4231 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4232 ei_up = 16000;
4233 threshold_up = 95;
dd75fdc8
CW		 4234
4235 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4236 ei_down = 32000;
4237 threshold_down = 85;
dd75fdc8
CW		 4238 break;
4239
4240 case BETWEEN:
4241 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4242 ei_up = 13000;
4243 threshold_up = 90;
dd75fdc8
CW		 4244
4245 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4246 ei_down = 32000;
4247 threshold_down = 75;
dd75fdc8
CW		 4248 break;
4249
4250 case HIGH_POWER:
4251 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4252 ei_up = 10000;
4253 threshold_up = 85;
dd75fdc8
CW		 4254
4255 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4256 ei_down = 32000;
4257 threshold_down = 60;
dd75fdc8
CW		 4258 break;
4259 }
4260
8a586437
AG		 4261 I915_WRITE(GEN6_RP_UP_EI,
4262 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4263 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4264 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4265
4266 I915_WRITE(GEN6_RP_DOWN_EI,
4267 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4268 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4269 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4270
4271 I915_WRITE(GEN6_RP_CONTROL,
4272 GEN6_RP_MEDIA_TURBO |
4273 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4274 GEN6_RP_MEDIA_IS_GFX |
4275 GEN6_RP_ENABLE |
4276 GEN6_RP_UP_BUSY_AVG |
4277 GEN6_RP_DOWN_IDLE_AVG);
4278
dd75fdc8 4279 dev_priv->rps.power = new_power;
8fb55197
CW		 4280 dev_priv->rps.up_threshold = threshold_up;
4281 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4282 dev_priv->rps.last_adj = 0;
4283}
4284
2876ce73
CW		 4285static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4286{
4287 u32 mask = 0;
4288
4289 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4290 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4291 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4292 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4293
7b3c29f6
CW		 4294 mask &= dev_priv->pm_rps_events;
4295
59d02a1f 4296 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4297}
4298
b8a5ff8d
JM		 4299/* gen6_set_rps is called to update the frequency request, but should also be
4300 * called when the range (min_delay and max_delay) is modified so that we can
4301 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4302static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4303{
4304 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4305
23eafea6 4306 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4307 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4308 return;
4309
4fc688ce 4310 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4311 WARN_ON(val > dev_priv->rps.max_freq);
4312 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4313
eb64cad1
CW		 4314 /* min/max delay may still have been modified so be sure to
4315 * write the limits value.
4316 */
4317 if (val != dev_priv->rps.cur_freq) {
4318 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4319
5704195c
AG		 4320 if (IS_GEN9(dev))
4321 I915_WRITE(GEN6_RPNSWREQ,
4322 GEN9_FREQUENCY(val));
4323 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4324 I915_WRITE(GEN6_RPNSWREQ,
4325 HSW_FREQUENCY(val));
4326 else
4327 I915_WRITE(GEN6_RPNSWREQ,
4328 GEN6_FREQUENCY(val) |
4329 GEN6_OFFSET(0) |
4330 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4331 }
7b9e0ae6 4332
7b9e0ae6
CW		 4333 /* Make sure we continue to get interrupts
4334 * until we hit the minimum or maximum frequencies.
4335 */
74ef1173 4336 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4337 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4338
d5570a72
BW		 4339 POSTING_READ(GEN6_RPNSWREQ);
4340
b39fb297 4341 dev_priv->rps.cur_freq = val;
0f94592e 4342 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4343}
4344
ffe02b40
VS		 4345static void valleyview_set_rps(struct drm_device *dev, u8 val)
4346{
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348
4349 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4350 WARN_ON(val > dev_priv->rps.max_freq);
4351 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4352
4353 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4354 "Odd GPU freq value\n"))
4355 val &= ~1;
4356
cd25dd5b
D		 4357 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4358
8fb55197 4359 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4360 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4361 if (!IS_CHERRYVIEW(dev_priv))
4362 gen6_set_rps_thresholds(dev_priv, val);
4363 }
ffe02b40 4364
ffe02b40
VS		 4365 dev_priv->rps.cur_freq = val;
4366 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4367}
4368
a7f6e231 4369/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4370 *
4371 * * If Gfx is Idle, then
a7f6e231
D		 4372 * 1. Forcewake Media well.
4373 * 2. Request idle freq.
4374 * 3. Release Forcewake of Media well.
76c3552f
D		 4375*/
4376static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4377{
aed242ff 4378 u32 val = dev_priv->rps.idle_freq;
5549d25f 4379
aed242ff 4380 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4381 return;
4382
a7f6e231
D		 4383 /* Wake up the media well, as that takes a lot less
4384 * power than the Render well. */
4385 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4386 valleyview_set_rps(dev_priv->dev, val);
4387 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4388}
4389
43cf3bf0
CW		 4390void gen6_rps_busy(struct drm_i915_private *dev_priv)
4391{
4392 mutex_lock(&dev_priv->rps.hw_lock);
4393 if (dev_priv->rps.enabled) {
4394 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4395 gen6_rps_reset_ei(dev_priv);
4396 I915_WRITE(GEN6_PMINTRMSK,
4397 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4398 }
4399 mutex_unlock(&dev_priv->rps.hw_lock);
4400}
4401
b29c19b6
CW		 4402void gen6_rps_idle(struct drm_i915_private *dev_priv)
4403{
691bb717
DL		 4404 struct drm_device *dev = dev_priv->dev;
4405
b29c19b6 4406 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4407 if (dev_priv->rps.enabled) {
21a11fff 4408 if (IS_VALLEYVIEW(dev))
76c3552f 4409 vlv_set_rps_idle(dev_priv);
7526ed79 4410 else
aed242ff 4411 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4412 dev_priv->rps.last_adj = 0;
43cf3bf0 4413 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4414 }
8d3afd7d 4415 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4416
8d3afd7d 4417 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4418 while (!list_empty(&dev_priv->rps.clients))
4419 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4420 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4421}
4422
1854d5ca 4423void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4424 struct intel_rps_client *rps,
4425 unsigned long submitted)
b29c19b6 4426{
8d3afd7d
CW		 4427 /* This is intentionally racy! We peek at the state here, then
4428 * validate inside the RPS worker.
4429 */
4430 if (!(dev_priv->mm.busy &&
4431 dev_priv->rps.enabled &&
4432 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4433 return;
43cf3bf0 4434
e61b9958
CW		 4435 /* Force a RPS boost (and don't count it against the client) if
4436 * the GPU is severely congested.
4437 */
d0bc54f2 4438 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4439 rps = NULL;
4440
8d3afd7d
CW		 4441 spin_lock(&dev_priv->rps.client_lock);
4442 if (rps == NULL || list_empty(&rps->link)) {
4443 spin_lock_irq(&dev_priv->irq_lock);
4444 if (dev_priv->rps.interrupts_enabled) {
4445 dev_priv->rps.client_boost = true;
4446 queue_work(dev_priv->wq, &dev_priv->rps.work);
4447 }
4448 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4449
2e1b8730
CW		 4450 if (rps != NULL) {
4451 list_add(&rps->link, &dev_priv->rps.clients);
4452 rps->boosts++;
1854d5ca
CW		 4453 } else
4454 dev_priv->rps.boosts++;
c0951f0c 4455 }
8d3afd7d 4456 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4457}
4458
ffe02b40 4459void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4460{
ffe02b40
VS		 4461 if (IS_VALLEYVIEW(dev))
4462 valleyview_set_rps(dev, val);
4463 else
4464 gen6_set_rps(dev, val);
0a073b84
JB		 4465}
4466
20e49366
ZW		 4467static void gen9_disable_rps(struct drm_device *dev)
4468{
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4470
4471 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4472 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4473}
4474
44fc7d5c 4475static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4476{
4477 struct drm_i915_private *dev_priv = dev->dev_private;
4478
4479 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4480 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4481}
4482
38807746
D		 4483static void cherryview_disable_rps(struct drm_device *dev)
4484{
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486
4487 I915_WRITE(GEN6_RC_CONTROL, 0);
4488}
4489
44fc7d5c
DV		 4490static void valleyview_disable_rps(struct drm_device *dev)
4491{
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493
98a2e5f9
D		 4494 /* we're doing forcewake before Disabling RC6,
4495 * This what the BIOS expects when going into suspend */
59bad947 4496 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4497
44fc7d5c 4498 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4499
59bad947 4500 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4501}
4502
dc39fff7
BW		 4503static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4504{
91ca689a
ID		 4505 if (IS_VALLEYVIEW(dev)) {
4506 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4507 mode = GEN6_RC_CTL_RC6_ENABLE;
4508 else
4509 mode = 0;
4510 }
58abf1da
RV		 4511 if (HAS_RC6p(dev))
4512 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4513 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4514 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4515 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4516
4517 else
4518 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4519 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4520}
4521
e6069ca8 4522static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4523{
e7d66d89
DV		 4524 /* No RC6 before Ironlake and code is gone for ilk. */
4525 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4526 return 0;
4527
456470eb 4528 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4529 if (enable_rc6 >= 0) {
4530 int mask;
4531
58abf1da 4532 if (HAS_RC6p(dev))
e6069ca8
ID		 4533 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4534 INTEL_RC6pp_ENABLE;
4535 else
4536 mask = INTEL_RC6_ENABLE;
4537
4538 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4539 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4540 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4541
4542 return enable_rc6 & mask;
4543 }
2b4e57bd 4544
8bade1ad 4545 if (IS_IVYBRIDGE(dev))
cca84a1f 4546 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4547
4548 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4549}
4550
e6069ca8
ID		 4551int intel_enable_rc6(const struct drm_device *dev)
4552{
4553 return i915.enable_rc6;
4554}
4555
93ee2920 4556static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4557{
93ee2920
TR		 4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 uint32_t rp_state_cap;
4560 u32 ddcc_status = 0;
4561 int ret;
4562
3280e8b0
BW		 4563 /* All of these values are in units of 50MHz */
4564 dev_priv->rps.cur_freq = 0;
93ee2920 4565 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4566 if (IS_BROXTON(dev)) {
4567 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4568 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4569 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4570 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4571 } else {
4572 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4573 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4574 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4575 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4576 }
4577
3280e8b0
BW		 4578 /* hw_max = RP0 until we check for overclocking */
4579 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4580
93ee2920 4581 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4582 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4583 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4584 ret = sandybridge_pcode_read(dev_priv,
4585 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4586 &ddcc_status);
4587 if (0 == ret)
4588 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4589 clamp_t(u8,
4590 ((ddcc_status >> 8) & 0xff),
4591 dev_priv->rps.min_freq,
4592 dev_priv->rps.max_freq);
93ee2920
TR		 4593 }
4594
ef11bdb3 4595 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4596 /* Store the frequency values in 16.66 MHZ units, which is
4597 the natural hardware unit for SKL */
4598 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4599 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4600 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4601 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4602 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4603 }
4604
aed242ff
CW		 4605 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4606
3280e8b0
BW		 4607 /* Preserve min/max settings in case of re-init */
4608 if (dev_priv->rps.max_freq_softlimit == 0)
4609 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4610
93ee2920
TR		 4611 if (dev_priv->rps.min_freq_softlimit == 0) {
4612 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4613 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4614 max_t(int, dev_priv->rps.efficient_freq,
4615 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4616 else
4617 dev_priv->rps.min_freq_softlimit =
4618 dev_priv->rps.min_freq;
4619 }
3280e8b0
BW		 4620}
4621
b6fef0ef 4622/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4623static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4624{
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626
4627 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4628
ba1c554c
DL		 4629 gen6_init_rps_frequencies(dev);
4630
23eafea6 4631 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4632 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4633 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4634 return;
4635 }
4636
0beb059a
AG		 4637 /* Program defaults and thresholds for RPS*/
4638 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4639 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4640
4641 /* 1 second timeout*/
4642 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4643 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4644
b6fef0ef 4645 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4646
0beb059a
AG		 4647 /* Leaning on the below call to gen6_set_rps to program/setup the
4648 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4649 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4650 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4651 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4652
4653 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4654}
4655
4656static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4657{
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659 struct intel_engine_cs *ring;
4660 uint32_t rc6_mask = 0;
4661 int unused;
4662
4663 /* 1a: Software RC state - RC0 */
4664 I915_WRITE(GEN6_RC_STATE, 0);
4665
4666 /* 1b: Get forcewake during program sequence. Although the driver
4667 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4668 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4669
4670 /* 2a: Disable RC states. */
4671 I915_WRITE(GEN6_RC_CONTROL, 0);
4672
4673 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4674
4675 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4676 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4677 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4678 else
4679 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4680 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4681 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4682 for_each_ring(ring, dev_priv, unused)
4683 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4684
4685 if (HAS_GUC_UCODE(dev))
4686 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4687
20e49366 4688 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4689
38c23527
ZW		 4690 /* 2c: Program Coarse Power Gating Policies. */
4691 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4692 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4693
20e49366
ZW		 4694 /* 3a: Enable RC6 */
4695 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4696 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4697 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4698 "on" : "off");
3e7732a0 4699 /* WaRsUseTimeoutMode */
e87a005d 4700 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4701 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4702 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4703 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4704 GEN7_RC_CTL_TO_MODE |
4705 rc6_mask);
3e7732a0
SAK		 4706 } else {
4707 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4708 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4709 GEN6_RC_CTL_EI_MODE(1) |
4710 rc6_mask);
3e7732a0 4711 }
20e49366 4712
cb07bae0
SK		 4713 /*
4714 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4715 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4716 */
e87a005d
JN		 4717 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
4718 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
6686ece1 4719 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
f2d2fe95
SAK		 4720 I915_WRITE(GEN9_PG_ENABLE, 0);
4721 else
4722 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4723 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4724
59bad947 4725 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4726
4727}
4728
6edee7f3
BW		 4729static void gen8_enable_rps(struct drm_device *dev)
4730{
4731 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4732 struct intel_engine_cs *ring;
93ee2920 4733 uint32_t rc6_mask = 0;
6edee7f3
BW		 4734 int unused;
4735
4736 /* 1a: Software RC state - RC0 */
4737 I915_WRITE(GEN6_RC_STATE, 0);
4738
4739 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4740 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4741 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4742
4743 /* 2a: Disable RC states. */
4744 I915_WRITE(GEN6_RC_CONTROL, 0);
4745
93ee2920
TR		 4746 /* Initialize rps frequencies */
4747 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4748
4749 /* 2b: Program RC6 thresholds.*/
4750 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4751 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4752 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4753 for_each_ring(ring, dev_priv, unused)
4754 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4755 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4756 if (IS_BROADWELL(dev))
4757 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4758 else
4759 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4760
4761 /* 3: Enable RC6 */
4762 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4763 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4764 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4765 if (IS_BROADWELL(dev))
4766 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4767 GEN7_RC_CTL_TO_MODE |
4768 rc6_mask);
4769 else
4770 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4771 GEN6_RC_CTL_EI_MODE(1) |
4772 rc6_mask);
6edee7f3
BW		 4773
4774 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4775 I915_WRITE(GEN6_RPNSWREQ,
4776 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4777 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4778 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4779 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4780 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4781
4782 /* Docs recommend 900MHz, and 300 MHz respectively */
4783 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4784 dev_priv->rps.max_freq_softlimit << 24 |
4785 dev_priv->rps.min_freq_softlimit << 16);
4786
4787 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4788 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4789 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4790 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4791
4792 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4793
4794 /* 5: Enable RPS */
7526ed79
DV		 4795 I915_WRITE(GEN6_RP_CONTROL,
4796 GEN6_RP_MEDIA_TURBO |
4797 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4798 GEN6_RP_MEDIA_IS_GFX |
4799 GEN6_RP_ENABLE |
4800 GEN6_RP_UP_BUSY_AVG |
4801 GEN6_RP_DOWN_IDLE_AVG);
4802
4803 /* 6: Ring frequency + overclocking (our driver does this later */
4804
c7f3153a 4805 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4806 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4807
59bad947 4808 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4809}
4810
79f5b2c7 4811static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4812{
79f5b2c7 4813 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4814 struct intel_engine_cs *ring;
d060c169 4815 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4816 u32 gtfifodbg;
2b4e57bd 4817 int rc6_mode;
42c0526c 4818 int i, ret;
2b4e57bd 4819
4fc688ce 4820 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4821
2b4e57bd
ED		 4822 /* Here begins a magic sequence of register writes to enable
4823 * auto-downclocking.
4824 *
4825 * Perhaps there might be some value in exposing these to
4826 * userspace...
4827 */
4828 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4829
4830 /* Clear the DBG now so we don't confuse earlier errors */
4831 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4832 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4833 I915_WRITE(GTFIFODBG, gtfifodbg);
4834 }
4835
59bad947 4836 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4837
93ee2920
TR		 4838 /* Initialize rps frequencies */
4839 gen6_init_rps_frequencies(dev);
dd0a1aa1 4840
2b4e57bd
ED		 4841 /* disable the counters and set deterministic thresholds */
4842 I915_WRITE(GEN6_RC_CONTROL, 0);
4843
4844 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4845 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4846 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4847 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4848 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4849
b4519513
CW		 4850 for_each_ring(ring, dev_priv, i)
4851 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4852
4853 I915_WRITE(GEN6_RC_SLEEP, 0);
4854 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4855 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4856 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4857 else
4858 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4859 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4860 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4861
5a7dc92a 4862 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4863 rc6_mode = intel_enable_rc6(dev_priv->dev);
4864 if (rc6_mode & INTEL_RC6_ENABLE)
4865 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4866
5a7dc92a
ED		 4867 /* We don't use those on Haswell */
4868 if (!IS_HASWELL(dev)) {
4869 if (rc6_mode & INTEL_RC6p_ENABLE)
4870 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4871
5a7dc92a
ED		 4872 if (rc6_mode & INTEL_RC6pp_ENABLE)
4873 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4874 }
2b4e57bd 4875
dc39fff7 4876 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4877
4878 I915_WRITE(GEN6_RC_CONTROL,
4879 rc6_mask |
4880 GEN6_RC_CTL_EI_MODE(1) |
4881 GEN6_RC_CTL_HW_ENABLE);
4882
dd75fdc8
CW		 4883 /* Power down if completely idle for over 50ms */
4884 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4885 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4886
42c0526c 4887 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4888 if (ret)
42c0526c 4889 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4890
4891 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4892 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4893 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4894 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4895 (pcu_mbox & 0xff) * 50);
b39fb297 4896 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4897 }
4898
dd75fdc8 4899 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4900 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4901
31643d54
BW		 4902 rc6vids = 0;
4903 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4904 if (IS_GEN6(dev) && ret) {
4905 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4906 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4907 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4908 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4909 rc6vids &= 0xffff00;
4910 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4911 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4912 if (ret)
4913 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4914 }
4915
59bad947 4916 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4917}
4918
c2bc2fc5 4919static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4920{
79f5b2c7 4921 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4922 int min_freq = 15;
3ebecd07
CW		 4923 unsigned int gpu_freq;
4924 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4925 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4926 int scaling_factor = 180;
eda79642 4927 struct cpufreq_policy *policy;
2b4e57bd 4928
4fc688ce 4929 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4930
eda79642
BW		 4931 policy = cpufreq_cpu_get(0);
4932 if (policy) {
4933 max_ia_freq = policy->cpuinfo.max_freq;
4934 cpufreq_cpu_put(policy);
4935 } else {
4936 /*
4937 * Default to measured freq if none found, PCU will ensure we
4938 * don't go over
4939 */
2b4e57bd 4940 max_ia_freq = tsc_khz;
eda79642 4941 }
2b4e57bd
ED		 4942
4943 /* Convert from kHz to MHz */
4944 max_ia_freq /= 1000;
4945
153b4b95 4946 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4947 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4948 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4949
ef11bdb3 4950 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4951 /* Convert GT frequency to 50 HZ units */
4952 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4953 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4954 } else {
4955 min_gpu_freq = dev_priv->rps.min_freq;
4956 max_gpu_freq = dev_priv->rps.max_freq;
4957 }
4958
2b4e57bd
ED		 4959 /*
4960 * For each potential GPU frequency, load a ring frequency we'd like
4961 * to use for memory access. We do this by specifying the IA frequency
4962 * the PCU should use as a reference to determine the ring frequency.
4963 */
4c8c7743
AG		 4964 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4965 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 4966 unsigned int ia_freq = 0, ring_freq = 0;
4967
ef11bdb3 4968 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4969 /*
4970 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4971 * No floor required for ring frequency on SKL.
4972 */
4973 ring_freq = gpu_freq;
4974 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 4975 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4976 ring_freq = max(min_ring_freq, gpu_freq);
4977 } else if (IS_HASWELL(dev)) {
f6aca45c 4978 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4979 ring_freq = max(min_ring_freq, ring_freq);
4980 /* leave ia_freq as the default, chosen by cpufreq */
4981 } else {
4982 /* On older processors, there is no separate ring
4983 * clock domain, so in order to boost the bandwidth
4984 * of the ring, we need to upclock the CPU (ia_freq).
4985 *
4986 * For GPU frequencies less than 750MHz,
4987 * just use the lowest ring freq.
4988 */
4989 if (gpu_freq < min_freq)
4990 ia_freq = 800;
4991 else
4992 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4993 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4994 }
2b4e57bd 4995
42c0526c
BW		 4996 sandybridge_pcode_write(dev_priv,
4997 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4998 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4999 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5000 gpu_freq);
2b4e57bd 5001 }
2b4e57bd
ED		 5002}
5003
c2bc2fc5
ID		 5004void gen6_update_ring_freq(struct drm_device *dev)
5005{
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007
97d3308a 5008 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5009 return;
5010
5011 mutex_lock(&dev_priv->rps.hw_lock);
5012 __gen6_update_ring_freq(dev);
5013 mutex_unlock(&dev_priv->rps.hw_lock);
5014}
5015
03af2045 5016static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5017{
095acd5f 5018 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5019 u32 val, rp0;
5020
5b5929cb 5021 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5022
5b5929cb
JN		 5023 switch (INTEL_INFO(dev)->eu_total) {
5024 case 8:
5025 /* (2 * 4) config */
5026 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5027 break;
5028 case 12:
5029 /* (2 * 6) config */
5030 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5031 break;
5032 case 16:
5033 /* (2 * 8) config */
5034 default:
5035 /* Setting (2 * 8) Min RP0 for any other combination */
5036 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5037 break;
095acd5f 5038 }
5b5929cb
JN		 5039
5040 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5041
2b6b3a09
D		 5042 return rp0;
5043}
5044
5045static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5046{
5047 u32 val, rpe;
5048
5049 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5050 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5051
5052 return rpe;
5053}
5054
7707df4a
D		 5055static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5056{
5057 u32 val, rp1;
5058
5b5929cb
JN		 5059 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5060 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5061
7707df4a
D		 5062 return rp1;
5063}
5064
f8f2b001
D		 5065static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5066{
5067 u32 val, rp1;
5068
5069 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5070
5071 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5072
5073 return rp1;
5074}
5075
03af2045 5076static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5077{
5078 u32 val, rp0;
5079
64936258 5080 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5081
5082 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5083 /* Clamp to max */
5084 rp0 = min_t(u32, rp0, 0xea);
5085
5086 return rp0;
5087}
5088
5089static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5090{
5091 u32 val, rpe;
5092
64936258 5093 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5094 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5095 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5096 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5097
5098 return rpe;
5099}
5100
03af2045 5101static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5102{
64936258 5103 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5104}
5105
ae48434c
ID		 5106/* Check that the pctx buffer wasn't move under us. */
5107static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5108{
5109 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5110
5111 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5112 dev_priv->vlv_pctx->stolen->start);
5113}
5114
38807746
D		 5115
5116/* Check that the pcbr address is not empty. */
5117static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5118{
5119 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5120
5121 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5122}
5123
5124static void cherryview_setup_pctx(struct drm_device *dev)
5125{
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 unsigned long pctx_paddr, paddr;
5128 struct i915_gtt *gtt = &dev_priv->gtt;
5129 u32 pcbr;
5130 int pctx_size = 32*1024;
5131
5132 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5133
5134 pcbr = I915_READ(VLV_PCBR);
5135 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5136 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5137 paddr = (dev_priv->mm.stolen_base +
5138 (gtt->stolen_size - pctx_size));
5139
5140 pctx_paddr = (paddr & (~4095));
5141 I915_WRITE(VLV_PCBR, pctx_paddr);
5142 }
ce611ef8
VS		 5143
5144 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5145}
5146
c9cddffc
JB		 5147static void valleyview_setup_pctx(struct drm_device *dev)
5148{
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5150 struct drm_i915_gem_object *pctx;
5151 unsigned long pctx_paddr;
5152 u32 pcbr;
5153 int pctx_size = 24*1024;
5154
17b0c1f7
ID		 5155 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5156
c9cddffc
JB		 5157 pcbr = I915_READ(VLV_PCBR);
5158 if (pcbr) {
5159 /* BIOS set it up already, grab the pre-alloc'd space */
5160 int pcbr_offset;
5161
5162 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5163 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5164 pcbr_offset,
190d6cd5 5165 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5166 pctx_size);
5167 goto out;
5168 }
5169
ce611ef8
VS		 5170 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5171
c9cddffc
JB		 5172 /*
5173 * From the Gunit register HAS:
5174 * The Gfx driver is expected to program this register and ensure
5175 * proper allocation within Gfx stolen memory. For example, this
5176 * register should be programmed such than the PCBR range does not
5177 * overlap with other ranges, such as the frame buffer, protected
5178 * memory, or any other relevant ranges.
5179 */
5180 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5181 if (!pctx) {
5182 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5183 return;
5184 }
5185
5186 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5187 I915_WRITE(VLV_PCBR, pctx_paddr);
5188
5189out:
ce611ef8 5190 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5191 dev_priv->vlv_pctx = pctx;
5192}
5193
ae48434c
ID		 5194static void valleyview_cleanup_pctx(struct drm_device *dev)
5195{
5196 struct drm_i915_private *dev_priv = dev->dev_private;
5197
5198 if (WARN_ON(!dev_priv->vlv_pctx))
5199 return;
5200
5201 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5202 dev_priv->vlv_pctx = NULL;
5203}
5204
4e80519e
ID		 5205static void valleyview_init_gt_powersave(struct drm_device *dev)
5206{
5207 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5208 u32 val;
4e80519e
ID		 5209
5210 valleyview_setup_pctx(dev);
5211
5212 mutex_lock(&dev_priv->rps.hw_lock);
5213
2bb25c17
VS		 5214 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5215 switch ((val >> 6) & 3) {
5216 case 0:
5217 case 1:
5218 dev_priv->mem_freq = 800;
5219 break;
5220 case 2:
5221 dev_priv->mem_freq = 1066;
5222 break;
5223 case 3:
5224 dev_priv->mem_freq = 1333;
5225 break;
5226 }
80b83b62 5227 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5228
4e80519e
ID		 5229 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5230 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5231 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5232 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5233 dev_priv->rps.max_freq);
5234
5235 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5236 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5237 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5238 dev_priv->rps.efficient_freq);
5239
f8f2b001
D		 5240 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5241 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5242 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5243 dev_priv->rps.rp1_freq);
5244
4e80519e
ID		 5245 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5246 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5247 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5248 dev_priv->rps.min_freq);
5249
aed242ff
CW		 5250 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5251
4e80519e
ID		 5252 /* Preserve min/max settings in case of re-init */
5253 if (dev_priv->rps.max_freq_softlimit == 0)
5254 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5255
5256 if (dev_priv->rps.min_freq_softlimit == 0)
5257 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5258
5259 mutex_unlock(&dev_priv->rps.hw_lock);
5260}
5261
38807746
D		 5262static void cherryview_init_gt_powersave(struct drm_device *dev)
5263{
2b6b3a09 5264 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5265 u32 val;
2b6b3a09 5266
38807746 5267 cherryview_setup_pctx(dev);
2b6b3a09
D		 5268
5269 mutex_lock(&dev_priv->rps.hw_lock);
5270
a580516d 5271 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5272 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5273 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5274
2bb25c17 5275 switch ((val >> 2) & 0x7) {
2bb25c17 5276 case 3:
2bb25c17
VS		 5277 dev_priv->mem_freq = 2000;
5278 break;
bfa7df01 5279 default:
2bb25c17
VS		 5280 dev_priv->mem_freq = 1600;
5281 break;
5282 }
80b83b62 5283 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5284
2b6b3a09
D		 5285 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5286 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5287 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5288 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5289 dev_priv->rps.max_freq);
5290
5291 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5292 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5293 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5294 dev_priv->rps.efficient_freq);
5295
7707df4a
D		 5296 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5297 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5298 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5299 dev_priv->rps.rp1_freq);
5300
5b7c91b7
D		 5301 /* PUnit validated range is only [RPe, RP0] */
5302 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5303 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5304 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5305 dev_priv->rps.min_freq);
5306
1c14762d
VS		 5307 WARN_ONCE((dev_priv->rps.max_freq |
5308 dev_priv->rps.efficient_freq |
5309 dev_priv->rps.rp1_freq |
5310 dev_priv->rps.min_freq) & 1,
5311 "Odd GPU freq values\n");
5312
aed242ff
CW		 5313 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5314
2b6b3a09
D		 5315 /* Preserve min/max settings in case of re-init */
5316 if (dev_priv->rps.max_freq_softlimit == 0)
5317 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5318
5319 if (dev_priv->rps.min_freq_softlimit == 0)
5320 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5321
5322 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5323}
5324
4e80519e
ID		 5325static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5326{
5327 valleyview_cleanup_pctx(dev);
5328}
5329
38807746
D		 5330static void cherryview_enable_rps(struct drm_device *dev)
5331{
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 struct intel_engine_cs *ring;
2b6b3a09 5334 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5335 int i;
5336
5337 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5338
5339 gtfifodbg = I915_READ(GTFIFODBG);
5340 if (gtfifodbg) {
5341 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5342 gtfifodbg);
5343 I915_WRITE(GTFIFODBG, gtfifodbg);
5344 }
5345
5346 cherryview_check_pctx(dev_priv);
5347
5348 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5349 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5350 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5351
160614a2
VS		 5352 /* Disable RC states. */
5353 I915_WRITE(GEN6_RC_CONTROL, 0);
5354
38807746
D		 5355 /* 2a: Program RC6 thresholds.*/
5356 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5357 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5358 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5359
5360 for_each_ring(ring, dev_priv, i)
5361 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5362 I915_WRITE(GEN6_RC_SLEEP, 0);
5363
f4f71c7d
D		 5364 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5365 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5366
5367 /* allows RC6 residency counter to work */
5368 I915_WRITE(VLV_COUNTER_CONTROL,
5369 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5370 VLV_MEDIA_RC6_COUNT_EN |
5371 VLV_RENDER_RC6_COUNT_EN));
5372
5373 /* For now we assume BIOS is allocating and populating the PCBR */
5374 pcbr = I915_READ(VLV_PCBR);
5375
38807746
D		 5376 /* 3: Enable RC6 */
5377 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5378 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5379 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5380
5381 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5382
2b6b3a09 5383 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5384 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5385 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5386 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5387 I915_WRITE(GEN6_RP_UP_EI, 66000);
5388 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5389
5390 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5391
5392 /* 5: Enable RPS */
5393 I915_WRITE(GEN6_RP_CONTROL,
5394 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5395 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5396 GEN6_RP_ENABLE |
5397 GEN6_RP_UP_BUSY_AVG |
5398 GEN6_RP_DOWN_IDLE_AVG);
5399
3ef62342
D		 5400 /* Setting Fixed Bias */
5401 val = VLV_OVERRIDE_EN |
5402 VLV_SOC_TDP_EN |
5403 CHV_BIAS_CPU_50_SOC_50;
5404 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5405
2b6b3a09
D		 5406 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5407
8d40c3ae
VS		 5408 /* RPS code assumes GPLL is used */
5409 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5410
742f491d 5411 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5412 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5413
5414 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5415 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5416 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5417 dev_priv->rps.cur_freq);
5418
5419 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5420 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5421 dev_priv->rps.efficient_freq);
5422
5423 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5424
59bad947 5425 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5426}
5427
0a073b84
JB		 5428static void valleyview_enable_rps(struct drm_device *dev)
5429{
5430 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5431 struct intel_engine_cs *ring;
2a5913a8 5432 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5433 int i;
5434
5435 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5436
ae48434c
ID		 5437 valleyview_check_pctx(dev_priv);
5438
0a073b84 5439 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5440 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5441 gtfifodbg);
0a073b84
JB		 5442 I915_WRITE(GTFIFODBG, gtfifodbg);
5443 }
5444
c8d9a590 5445 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5446 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5447
160614a2
VS		 5448 /* Disable RC states. */
5449 I915_WRITE(GEN6_RC_CONTROL, 0);
5450
cad725fe 5451 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5452 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5453 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5454 I915_WRITE(GEN6_RP_UP_EI, 66000);
5455 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5456
5457 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5458
5459 I915_WRITE(GEN6_RP_CONTROL,
5460 GEN6_RP_MEDIA_TURBO |
5461 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5462 GEN6_RP_MEDIA_IS_GFX |
5463 GEN6_RP_ENABLE |
5464 GEN6_RP_UP_BUSY_AVG |
5465 GEN6_RP_DOWN_IDLE_CONT);
5466
5467 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5468 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5469 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5470
5471 for_each_ring(ring, dev_priv, i)
5472 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5473
2f0aa304 5474 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5475
5476 /* allows RC6 residency counter to work */
49798eb2 5477 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5478 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5479 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5480 VLV_MEDIA_RC6_COUNT_EN |
5481 VLV_RENDER_RC6_COUNT_EN));
31685c25 5482
a2b23fe0 5483 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5484 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5485
5486 intel_print_rc6_info(dev, rc6_mode);
5487
a2b23fe0 5488 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5489
3ef62342
D		 5490 /* Setting Fixed Bias */
5491 val = VLV_OVERRIDE_EN |
5492 VLV_SOC_TDP_EN |
5493 VLV_BIAS_CPU_125_SOC_875;
5494 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5495
64936258 5496 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5497
8d40c3ae
VS		 5498 /* RPS code assumes GPLL is used */
5499 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5500
742f491d 5501 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5502 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5503
b39fb297 5504 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5505 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5506 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5507 dev_priv->rps.cur_freq);
0a073b84 5508
73008b98 5509 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5510 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5511 dev_priv->rps.efficient_freq);
0a073b84 5512
b39fb297 5513 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5514
59bad947 5515 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5516}
5517
dde18883
ED		 5518static unsigned long intel_pxfreq(u32 vidfreq)
5519{
5520 unsigned long freq;
5521 int div = (vidfreq & 0x3f0000) >> 16;
5522 int post = (vidfreq & 0x3000) >> 12;
5523 int pre = (vidfreq & 0x7);
5524
5525 if (!pre)
5526 return 0;
5527
5528 freq = ((div * 133333) / ((1<<post) * pre));
5529
5530 return freq;
5531}
5532
eb48eb00
DV		 5533static const struct cparams {
5534 u16 i;
5535 u16 t;
5536 u16 m;
5537 u16 c;
5538} cparams[] = {
5539 { 1, 1333, 301, 28664 },
5540 { 1, 1066, 294, 24460 },
5541 { 1, 800, 294, 25192 },
5542 { 0, 1333, 276, 27605 },
5543 { 0, 1066, 276, 27605 },
5544 { 0, 800, 231, 23784 },
5545};
5546
f531dcb2 5547static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5548{
5549 u64 total_count, diff, ret;
5550 u32 count1, count2, count3, m = 0, c = 0;
5551 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5552 int i;
5553
02d71956
DV		 5554 assert_spin_locked(&mchdev_lock);
5555
20e4d407 5556 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5557
5558 /* Prevent division-by-zero if we are asking too fast.
5559 * Also, we don't get interesting results if we are polling
5560 * faster than once in 10ms, so just return the saved value
5561 * in such cases.
5562 */
5563 if (diff1 <= 10)
20e4d407 5564 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5565
5566 count1 = I915_READ(DMIEC);
5567 count2 = I915_READ(DDREC);
5568 count3 = I915_READ(CSIEC);
5569
5570 total_count = count1 + count2 + count3;
5571
5572 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5573 if (total_count < dev_priv->ips.last_count1) {
5574 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5575 diff += total_count;
5576 } else {
20e4d407 5577 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5578 }
5579
5580 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5581 if (cparams[i].i == dev_priv->ips.c_m &&
5582 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5583 m = cparams[i].m;
5584 c = cparams[i].c;
5585 break;
5586 }
5587 }
5588
5589 diff = div_u64(diff, diff1);
5590 ret = ((m * diff) + c);
5591 ret = div_u64(ret, 10);
5592
20e4d407
DV		 5593 dev_priv->ips.last_count1 = total_count;
5594 dev_priv->ips.last_time1 = now;
eb48eb00 5595
20e4d407 5596 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5597
5598 return ret;
5599}
5600
f531dcb2
CW		 5601unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5602{
3d13ef2e 5603 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5604 unsigned long val;
5605
3d13ef2e 5606 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5607 return 0;
5608
5609 spin_lock_irq(&mchdev_lock);
5610
5611 val = __i915_chipset_val(dev_priv);
5612
5613 spin_unlock_irq(&mchdev_lock);
5614
5615 return val;
5616}
5617
eb48eb00
DV		 5618unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5619{
5620 unsigned long m, x, b;
5621 u32 tsfs;
5622
5623 tsfs = I915_READ(TSFS);
5624
5625 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5626 x = I915_READ8(TR1);
5627
5628 b = tsfs & TSFS_INTR_MASK;
5629
5630 return ((m * x) / 127) - b;
5631}
5632
d972d6ee
MK		 5633static int _pxvid_to_vd(u8 pxvid)
5634{
5635 if (pxvid == 0)
5636 return 0;
5637
5638 if (pxvid >= 8 && pxvid < 31)
5639 pxvid = 31;
5640
5641 return (pxvid + 2) * 125;
5642}
5643
5644static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5645{
3d13ef2e 5646 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5647 const int vd = _pxvid_to_vd(pxvid);
5648 const int vm = vd - 1125;
5649
3d13ef2e 5650 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5651 return vm > 0 ? vm : 0;
5652
5653 return vd;
eb48eb00
DV		 5654}
5655
02d71956 5656static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5657{
5ed0bdf2 5658 u64 now, diff, diffms;
eb48eb00
DV		 5659 u32 count;
5660
02d71956 5661 assert_spin_locked(&mchdev_lock);
eb48eb00 5662
5ed0bdf2
TG		 5663 now = ktime_get_raw_ns();
5664 diffms = now - dev_priv->ips.last_time2;
5665 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5666
5667 /* Don't divide by 0 */
eb48eb00
DV		 5668 if (!diffms)
5669 return;
5670
5671 count = I915_READ(GFXEC);
5672
20e4d407
DV		 5673 if (count < dev_priv->ips.last_count2) {
5674 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5675 diff += count;
5676 } else {
20e4d407 5677 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5678 }
5679
20e4d407
DV		 5680 dev_priv->ips.last_count2 = count;
5681 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5682
5683 /* More magic constants... */
5684 diff = diff * 1181;
5685 diff = div_u64(diff, diffms * 10);
20e4d407 5686 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5687}
5688
02d71956
DV		 5689void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5690{
3d13ef2e
DL		 5691 struct drm_device *dev = dev_priv->dev;
5692
5693 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5694 return;
5695
9270388e 5696 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5697
5698 __i915_update_gfx_val(dev_priv);
5699
9270388e 5700 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5701}
5702
f531dcb2 5703static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5704{
5705 unsigned long t, corr, state1, corr2, state2;
5706 u32 pxvid, ext_v;
5707
02d71956
DV		 5708 assert_spin_locked(&mchdev_lock);
5709
616847e7 5710 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5711 pxvid = (pxvid >> 24) & 0x7f;
5712 ext_v = pvid_to_extvid(dev_priv, pxvid);
5713
5714 state1 = ext_v;
5715
5716 t = i915_mch_val(dev_priv);
5717
5718 /* Revel in the empirically derived constants */
5719
5720 /* Correction factor in 1/100000 units */
5721 if (t > 80)
5722 corr = ((t * 2349) + 135940);
5723 else if (t >= 50)
5724 corr = ((t * 964) + 29317);
5725 else /* < 50 */
5726 corr = ((t * 301) + 1004);
5727
5728 corr = corr * ((150142 * state1) / 10000 - 78642);
5729 corr /= 100000;
20e4d407 5730 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5731
5732 state2 = (corr2 * state1) / 10000;
5733 state2 /= 100; /* convert to mW */
5734
02d71956 5735 __i915_update_gfx_val(dev_priv);
eb48eb00 5736
20e4d407 5737 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5738}
5739
f531dcb2
CW		 5740unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5741{
3d13ef2e 5742 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5743 unsigned long val;
5744
3d13ef2e 5745 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5746 return 0;
5747
5748 spin_lock_irq(&mchdev_lock);
5749
5750 val = __i915_gfx_val(dev_priv);
5751
5752 spin_unlock_irq(&mchdev_lock);
5753
5754 return val;
5755}
5756
eb48eb00
DV		 5757/**
5758 * i915_read_mch_val - return value for IPS use
5759 *
5760 * Calculate and return a value for the IPS driver to use when deciding whether
5761 * we have thermal and power headroom to increase CPU or GPU power budget.
5762 */
5763unsigned long i915_read_mch_val(void)
5764{
5765 struct drm_i915_private *dev_priv;
5766 unsigned long chipset_val, graphics_val, ret = 0;
5767
9270388e 5768 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5769 if (!i915_mch_dev)
5770 goto out_unlock;
5771 dev_priv = i915_mch_dev;
5772
f531dcb2
CW		 5773 chipset_val = __i915_chipset_val(dev_priv);
5774 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5775
5776 ret = chipset_val + graphics_val;
5777
5778out_unlock:
9270388e 5779 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5780
5781 return ret;
5782}
5783EXPORT_SYMBOL_GPL(i915_read_mch_val);
5784
5785/**
5786 * i915_gpu_raise - raise GPU frequency limit
5787 *
5788 * Raise the limit; IPS indicates we have thermal headroom.
5789 */
5790bool i915_gpu_raise(void)
5791{
5792 struct drm_i915_private *dev_priv;
5793 bool ret = true;
5794
9270388e 5795 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5796 if (!i915_mch_dev) {
5797 ret = false;
5798 goto out_unlock;
5799 }
5800 dev_priv = i915_mch_dev;
5801
20e4d407
DV		 5802 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5803 dev_priv->ips.max_delay--;
eb48eb00
DV		 5804
5805out_unlock:
9270388e 5806 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5807
5808 return ret;
5809}
5810EXPORT_SYMBOL_GPL(i915_gpu_raise);
5811
5812/**
5813 * i915_gpu_lower - lower GPU frequency limit
5814 *
5815 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5816 * frequency maximum.
5817 */
5818bool i915_gpu_lower(void)
5819{
5820 struct drm_i915_private *dev_priv;
5821 bool ret = true;
5822
9270388e 5823 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5824 if (!i915_mch_dev) {
5825 ret = false;
5826 goto out_unlock;
5827 }
5828 dev_priv = i915_mch_dev;
5829
20e4d407
DV		 5830 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5831 dev_priv->ips.max_delay++;
eb48eb00
DV		 5832
5833out_unlock:
9270388e 5834 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5835
5836 return ret;
5837}
5838EXPORT_SYMBOL_GPL(i915_gpu_lower);
5839
5840/**
5841 * i915_gpu_busy - indicate GPU business to IPS
5842 *
5843 * Tell the IPS driver whether or not the GPU is busy.
5844 */
5845bool i915_gpu_busy(void)
5846{
5847 struct drm_i915_private *dev_priv;
a4872ba6 5848 struct intel_engine_cs *ring;
eb48eb00 5849 bool ret = false;
f047e395 5850 int i;
eb48eb00 5851
9270388e 5852 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5853 if (!i915_mch_dev)
5854 goto out_unlock;
5855 dev_priv = i915_mch_dev;
5856
f047e395
CW		 5857 for_each_ring(ring, dev_priv, i)
5858 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5859
5860out_unlock:
9270388e 5861 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5862
5863 return ret;
5864}
5865EXPORT_SYMBOL_GPL(i915_gpu_busy);
5866
5867/**
5868 * i915_gpu_turbo_disable - disable graphics turbo
5869 *
5870 * Disable graphics turbo by resetting the max frequency and setting the
5871 * current frequency to the default.
5872 */
5873bool i915_gpu_turbo_disable(void)
5874{
5875 struct drm_i915_private *dev_priv;
5876 bool ret = true;
5877
9270388e 5878 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5879 if (!i915_mch_dev) {
5880 ret = false;
5881 goto out_unlock;
5882 }
5883 dev_priv = i915_mch_dev;
5884
20e4d407 5885 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5886
20e4d407 5887 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5888 ret = false;
5889
5890out_unlock:
9270388e 5891 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5892
5893 return ret;
5894}
5895EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5896
5897/**
5898 * Tells the intel_ips driver that the i915 driver is now loaded, if
5899 * IPS got loaded first.
5900 *
5901 * This awkward dance is so that neither module has to depend on the
5902 * other in order for IPS to do the appropriate communication of
5903 * GPU turbo limits to i915.
5904 */
5905static void
5906ips_ping_for_i915_load(void)
5907{
5908 void (*link)(void);
5909
5910 link = symbol_get(ips_link_to_i915_driver);
5911 if (link) {
5912 link();
5913 symbol_put(ips_link_to_i915_driver);
5914 }
5915}
5916
5917void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5918{
02d71956
DV		 5919 /* We only register the i915 ips part with intel-ips once everything is
5920 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5921 spin_lock_irq(&mchdev_lock);
eb48eb00 5922 i915_mch_dev = dev_priv;
9270388e 5923 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5924
5925 ips_ping_for_i915_load();
5926}
5927
5928void intel_gpu_ips_teardown(void)
5929{
9270388e 5930 spin_lock_irq(&mchdev_lock);
eb48eb00 5931 i915_mch_dev = NULL;
9270388e 5932 spin_unlock_irq(&mchdev_lock);
eb48eb00 5933}
76c3552f 5934
8090c6b9 5935static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5936{
5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 u32 lcfuse;
5939 u8 pxw[16];
5940 int i;
5941
5942 /* Disable to program */
5943 I915_WRITE(ECR, 0);
5944 POSTING_READ(ECR);
5945
5946 /* Program energy weights for various events */
5947 I915_WRITE(SDEW, 0x15040d00);
5948 I915_WRITE(CSIEW0, 0x007f0000);
5949 I915_WRITE(CSIEW1, 0x1e220004);
5950 I915_WRITE(CSIEW2, 0x04000004);
5951
5952 for (i = 0; i < 5; i++)
616847e7 5953 I915_WRITE(PEW(i), 0);
dde18883 5954 for (i = 0; i < 3; i++)
616847e7 5955 I915_WRITE(DEW(i), 0);
dde18883
ED		 5956
5957 /* Program P-state weights to account for frequency power adjustment */
5958 for (i = 0; i < 16; i++) {
616847e7 5959 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 5960 unsigned long freq = intel_pxfreq(pxvidfreq);
5961 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5962 PXVFREQ_PX_SHIFT;
5963 unsigned long val;
5964
5965 val = vid * vid;
5966 val *= (freq / 1000);
5967 val *= 255;
5968 val /= (127*127*900);
5969 if (val > 0xff)
5970 DRM_ERROR("bad pxval: %ld\n", val);
5971 pxw[i] = val;
5972 }
5973 /* Render standby states get 0 weight */
5974 pxw[14] = 0;
5975 pxw[15] = 0;
5976
5977 for (i = 0; i < 4; i++) {
5978 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5979 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 5980 I915_WRITE(PXW(i), val);
dde18883
ED		 5981 }
5982
5983 /* Adjust magic regs to magic values (more experimental results) */
5984 I915_WRITE(OGW0, 0);
5985 I915_WRITE(OGW1, 0);
5986 I915_WRITE(EG0, 0x00007f00);
5987 I915_WRITE(EG1, 0x0000000e);
5988 I915_WRITE(EG2, 0x000e0000);
5989 I915_WRITE(EG3, 0x68000300);
5990 I915_WRITE(EG4, 0x42000000);
5991 I915_WRITE(EG5, 0x00140031);
5992 I915_WRITE(EG6, 0);
5993 I915_WRITE(EG7, 0);
5994
5995 for (i = 0; i < 8; i++)
616847e7 5996 I915_WRITE(PXWL(i), 0);
dde18883
ED		 5997
5998 /* Enable PMON + select events */
5999 I915_WRITE(ECR, 0x80000019);
6000
6001 lcfuse = I915_READ(LCFUSE02);
6002
20e4d407 6003 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6004}
6005
ae48434c
ID		 6006void intel_init_gt_powersave(struct drm_device *dev)
6007{
e6069ca8
ID		 6008 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6009
38807746
D		 6010 if (IS_CHERRYVIEW(dev))
6011 cherryview_init_gt_powersave(dev);
6012 else if (IS_VALLEYVIEW(dev))
4e80519e 6013 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6014}
6015
6016void intel_cleanup_gt_powersave(struct drm_device *dev)
6017{
38807746
D		 6018 if (IS_CHERRYVIEW(dev))
6019 return;
6020 else if (IS_VALLEYVIEW(dev))
4e80519e 6021 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6022}
6023
dbea3cea
ID		 6024static void gen6_suspend_rps(struct drm_device *dev)
6025{
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6027
6028 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6029
4c2a8897 6030 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6031}
6032
156c7ca0
JB		 6033/**
6034 * intel_suspend_gt_powersave - suspend PM work and helper threads
6035 * @dev: drm device
6036 *
6037 * We don't want to disable RC6 or other features here, we just want
6038 * to make sure any work we've queued has finished and won't bother
6039 * us while we're suspended.
6040 */
6041void intel_suspend_gt_powersave(struct drm_device *dev)
6042{
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044
d4d70aa5
ID		 6045 if (INTEL_INFO(dev)->gen < 6)
6046 return;
6047
dbea3cea 6048 gen6_suspend_rps(dev);
b47adc17
D		 6049
6050 /* Force GPU to min freq during suspend */
6051 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6052}
6053
8090c6b9
DV		 6054void intel_disable_gt_powersave(struct drm_device *dev)
6055{
1a01ab3b
JB		 6056 struct drm_i915_private *dev_priv = dev->dev_private;
6057
930ebb46 6058 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6059 ironlake_disable_drps(dev);
38807746 6060 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6061 intel_suspend_gt_powersave(dev);
e494837a 6062
4fc688ce 6063 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6064 if (INTEL_INFO(dev)->gen >= 9)
6065 gen9_disable_rps(dev);
6066 else if (IS_CHERRYVIEW(dev))
38807746
D		 6067 cherryview_disable_rps(dev);
6068 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6069 valleyview_disable_rps(dev);
6070 else
6071 gen6_disable_rps(dev);
e534770a 6072
c0951f0c 6073 dev_priv->rps.enabled = false;
4fc688ce 6074 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6075 }
8090c6b9
DV		 6076}
6077
1a01ab3b
JB		 6078static void intel_gen6_powersave_work(struct work_struct *work)
6079{
6080 struct drm_i915_private *dev_priv =
6081 container_of(work, struct drm_i915_private,
6082 rps.delayed_resume_work.work);
6083 struct drm_device *dev = dev_priv->dev;
6084
4fc688ce 6085 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6086
4c2a8897 6087 gen6_reset_rps_interrupts(dev);
3cc134e3 6088
38807746
D		 6089 if (IS_CHERRYVIEW(dev)) {
6090 cherryview_enable_rps(dev);
6091 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6092 valleyview_enable_rps(dev);
20e49366 6093 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6094 gen9_enable_rc6(dev);
20e49366 6095 gen9_enable_rps(dev);
ef11bdb3 6096 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6097 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6098 } else if (IS_BROADWELL(dev)) {
6099 gen8_enable_rps(dev);
c2bc2fc5 6100 __gen6_update_ring_freq(dev);
0a073b84
JB		 6101 } else {
6102 gen6_enable_rps(dev);
c2bc2fc5 6103 __gen6_update_ring_freq(dev);
0a073b84 6104 }
aed242ff
CW		 6105
6106 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6107 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6108
6109 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6110 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6111
c0951f0c 6112 dev_priv->rps.enabled = true;
3cc134e3 6113
4c2a8897 6114 gen6_enable_rps_interrupts(dev);
3cc134e3 6115
4fc688ce 6116 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6117
6118 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6119}
6120
8090c6b9
DV		 6121void intel_enable_gt_powersave(struct drm_device *dev)
6122{
1a01ab3b
JB		 6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124
f61018b1
YZ		 6125 /* Powersaving is controlled by the host when inside a VM */
6126 if (intel_vgpu_active(dev))
6127 return;
6128
8090c6b9 6129 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6130 mutex_lock(&dev->struct_mutex);
8090c6b9 6131 ironlake_enable_drps(dev);
8090c6b9 6132 intel_init_emon(dev);
dc1d0136 6133 mutex_unlock(&dev->struct_mutex);
38807746 6134 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6135 /*
6136 * PCU communication is slow and this doesn't need to be
6137 * done at any specific time, so do this out of our fast path
6138 * to make resume and init faster.
c6df39b5
ID		 6139 *
6140 * We depend on the HW RC6 power context save/restore
6141 * mechanism when entering D3 through runtime PM suspend. So
6142 * disable RPM until RPS/RC6 is properly setup. We can only
6143 * get here via the driver load/system resume/runtime resume
6144 * paths, so the _noresume version is enough (and in case of
6145 * runtime resume it's necessary).
1a01ab3b 6146 */
c6df39b5
ID		 6147 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6148 round_jiffies_up_relative(HZ)))
6149 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6150 }
6151}
6152
c6df39b5
ID		 6153void intel_reset_gt_powersave(struct drm_device *dev)
6154{
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6156
dbea3cea
ID		 6157 if (INTEL_INFO(dev)->gen < 6)
6158 return;
6159
6160 gen6_suspend_rps(dev);
c6df39b5 6161 dev_priv->rps.enabled = false;
c6df39b5
ID		 6162}
6163
3107bd48
DV		 6164static void ibx_init_clock_gating(struct drm_device *dev)
6165{
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167
6168 /*
6169 * On Ibex Peak and Cougar Point, we need to disable clock
6170 * gating for the panel power sequencer or it will fail to
6171 * start up when no ports are active.
6172 */
6173 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6174}
6175
0e088b8f
VS		 6176static void g4x_disable_trickle_feed(struct drm_device *dev)
6177{
6178 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6179 enum pipe pipe;
0e088b8f 6180
055e393f 6181 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6182 I915_WRITE(DSPCNTR(pipe),
6183 I915_READ(DSPCNTR(pipe)) |
6184 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6185
6186 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6187 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6188 }
6189}
6190
017636cc
VS		 6191static void ilk_init_lp_watermarks(struct drm_device *dev)
6192{
6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194
6195 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6196 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6197 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6198
6199 /*
6200 * Don't touch WM1S_LP_EN here.
6201 * Doing so could cause underruns.
6202 */
6203}
6204
1fa61106 6205static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6206{
6207 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6208 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6209
f1e8fa56
DL		 6210 /*
6211 * Required for FBC
6212 * WaFbcDisableDpfcClockGating:ilk
6213 */
4d47e4f5
DL		 6214 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6215 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6216 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6217
6218 I915_WRITE(PCH_3DCGDIS0,
6219 MARIUNIT_CLOCK_GATE_DISABLE |
6220 SVSMUNIT_CLOCK_GATE_DISABLE);
6221 I915_WRITE(PCH_3DCGDIS1,
6222 VFMUNIT_CLOCK_GATE_DISABLE);
6223
6f1d69b0
ED		 6224 /*
6225 * According to the spec the following bits should be set in
6226 * order to enable memory self-refresh
6227 * The bit 22/21 of 0x42004
6228 * The bit 5 of 0x42020
6229 * The bit 15 of 0x45000
6230 */
6231 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6232 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6233 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6234 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6235 I915_WRITE(DISP_ARB_CTL,
6236 (I915_READ(DISP_ARB_CTL) |
6237 DISP_FBC_WM_DIS));
017636cc
VS		 6238
6239 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6240
6241 /*
6242 * Based on the document from hardware guys the following bits
6243 * should be set unconditionally in order to enable FBC.
6244 * The bit 22 of 0x42000
6245 * The bit 22 of 0x42004
6246 * The bit 7,8,9 of 0x42020.
6247 */
6248 if (IS_IRONLAKE_M(dev)) {
4bb35334 6249 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6250 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6251 I915_READ(ILK_DISPLAY_CHICKEN1) |
6252 ILK_FBCQ_DIS);
6253 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6254 I915_READ(ILK_DISPLAY_CHICKEN2) |
6255 ILK_DPARB_GATE);
6f1d69b0
ED		 6256 }
6257
4d47e4f5
DL		 6258 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6259
6f1d69b0
ED		 6260 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6261 I915_READ(ILK_DISPLAY_CHICKEN2) |
6262 ILK_ELPIN_409_SELECT);
6263 I915_WRITE(_3D_CHICKEN2,
6264 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6265 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6266
ecdb4eb7 6267 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6268 I915_WRITE(CACHE_MODE_0,
6269 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6270
4e04632e
AG		 6271 /* WaDisable_RenderCache_OperationalFlush:ilk */
6272 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6273
0e088b8f 6274 g4x_disable_trickle_feed(dev);
bdad2b2f 6275
3107bd48
DV		 6276 ibx_init_clock_gating(dev);
6277}
6278
6279static void cpt_init_clock_gating(struct drm_device *dev)
6280{
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6282 int pipe;
3f704fa2 6283 uint32_t val;
3107bd48
DV		 6284
6285 /*
6286 * On Ibex Peak and Cougar Point, we need to disable clock
6287 * gating for the panel power sequencer or it will fail to
6288 * start up when no ports are active.
6289 */
cd664078
JB		 6290 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6291 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6292 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6293 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6294 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6295 /* The below fixes the weird display corruption, a few pixels shifted
6296 * downward, on (only) LVDS of some HP laptops with IVY.
6297 */
055e393f 6298 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6299 val = I915_READ(TRANS_CHICKEN2(pipe));
6300 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6301 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6302 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6303 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6304 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6305 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6306 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6307 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6308 }
3107bd48 6309 /* WADP0ClockGatingDisable */
055e393f 6310 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6311 I915_WRITE(TRANS_CHICKEN1(pipe),
6312 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6313 }
6f1d69b0
ED		 6314}
6315
1d7aaa0c
DV		 6316static void gen6_check_mch_setup(struct drm_device *dev)
6317{
6318 struct drm_i915_private *dev_priv = dev->dev_private;
6319 uint32_t tmp;
6320
6321 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6322 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6323 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6324 tmp);
1d7aaa0c
DV		 6325}
6326
1fa61106 6327static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6328{
6329 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6330 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6331
231e54f6 6332 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6333
6334 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6335 I915_READ(ILK_DISPLAY_CHICKEN2) |
6336 ILK_ELPIN_409_SELECT);
6337
ecdb4eb7 6338 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6339 I915_WRITE(_3D_CHICKEN,
6340 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6341
4e04632e
AG		 6342 /* WaDisable_RenderCache_OperationalFlush:snb */
6343 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6344
8d85d272
VS		 6345 /*
6346 * BSpec recoomends 8x4 when MSAA is used,
6347 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6348 *
6349 * Note that PS/WM thread counts depend on the WIZ hashing
6350 * disable bit, which we don't touch here, but it's good
6351 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6352 */
6353 I915_WRITE(GEN6_GT_MODE,
98533251 6354 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6355
017636cc 6356 ilk_init_lp_watermarks(dev);
6f1d69b0 6357
6f1d69b0 6358 I915_WRITE(CACHE_MODE_0,
50743298 6359 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6360
6361 I915_WRITE(GEN6_UCGCTL1,
6362 I915_READ(GEN6_UCGCTL1) |
6363 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6364 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6365
6366 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6367 * gating disable must be set. Failure to set it results in
6368 * flickering pixels due to Z write ordering failures after
6369 * some amount of runtime in the Mesa "fire" demo, and Unigine
6370 * Sanctuary and Tropics, and apparently anything else with
6371 * alpha test or pixel discard.
6372 *
6373 * According to the spec, bit 11 (RCCUNIT) must also be set,
6374 * but we didn't debug actual testcases to find it out.
0f846f81 6375 *
ef59318c
VS		 6376 * WaDisableRCCUnitClockGating:snb
6377 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6378 */
6379 I915_WRITE(GEN6_UCGCTL2,
6380 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6381 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6382
5eb146dd 6383 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6384 I915_WRITE(_3D_CHICKEN3,
6385 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6386
e927ecde
VS		 6387 /*
6388 * Bspec says:
6389 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6390 * 3DSTATE_SF number of SF output attributes is more than 16."
6391 */
6392 I915_WRITE(_3D_CHICKEN3,
6393 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6394
6f1d69b0
ED		 6395 /*
6396 * According to the spec the following bits should be
6397 * set in order to enable memory self-refresh and fbc:
6398 * The bit21 and bit22 of 0x42000
6399 * The bit21 and bit22 of 0x42004
6400 * The bit5 and bit7 of 0x42020
6401 * The bit14 of 0x70180
6402 * The bit14 of 0x71180
4bb35334
DL		 6403 *
6404 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6405 */
6406 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6407 I915_READ(ILK_DISPLAY_CHICKEN1) |
6408 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6409 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6410 I915_READ(ILK_DISPLAY_CHICKEN2) |
6411 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6412 I915_WRITE(ILK_DSPCLK_GATE_D,
6413 I915_READ(ILK_DSPCLK_GATE_D) |
6414 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6415 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6416
0e088b8f 6417 g4x_disable_trickle_feed(dev);
f8f2ac9a 6418
3107bd48 6419 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6420
6421 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6422}
6423
6424static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6425{
6426 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6427
3aad9059 6428 /*
46680e0a 6429 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6430 *
6431 * This actually overrides the dispatch
6432 * mode for all thread types.
6433 */
6f1d69b0
ED		 6434 reg &= ~GEN7_FF_SCHED_MASK;
6435 reg |= GEN7_FF_TS_SCHED_HW;
6436 reg |= GEN7_FF_VS_SCHED_HW;
6437 reg |= GEN7_FF_DS_SCHED_HW;
6438
6439 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6440}
6441
17a303ec
PZ		 6442static void lpt_init_clock_gating(struct drm_device *dev)
6443{
6444 struct drm_i915_private *dev_priv = dev->dev_private;
6445
6446 /*
6447 * TODO: this bit should only be enabled when really needed, then
6448 * disabled when not needed anymore in order to save power.
6449 */
c2699524 6450 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6451 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6452 I915_READ(SOUTH_DSPCLK_GATE_D) |
6453 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6454
6455 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6456 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6457 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6458 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6459}
6460
7d708ee4
ID		 6461static void lpt_suspend_hw(struct drm_device *dev)
6462{
6463 struct drm_i915_private *dev_priv = dev->dev_private;
6464
c2699524 6465 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6466 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6467
6468 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6469 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6470 }
6471}
6472
47c2bd97 6473static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6474{
6475 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6476 enum pipe pipe;
4d487cff 6477 uint32_t misccpctl;
1020a5c2 6478
7ad0dbab 6479 ilk_init_lp_watermarks(dev);
50ed5fbd 6480
ab57fff1 6481 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6482 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6483
ab57fff1 6484 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6485 I915_WRITE(CHICKEN_PAR1_1,
6486 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6487
ab57fff1 6488 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6489 for_each_pipe(dev_priv, pipe) {
07d27e20 6490 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6491 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6492 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6493 }
63801f21 6494
ab57fff1
BW		 6495 /* WaVSRefCountFullforceMissDisable:bdw */
6496 /* WaDSRefCountFullforceMissDisable:bdw */
6497 I915_WRITE(GEN7_FF_THREAD_MODE,
6498 I915_READ(GEN7_FF_THREAD_MODE) &
6499 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6500
295e8bb7
VS		 6501 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6502 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6503
6504 /* WaDisableSDEUnitClockGating:bdw */
6505 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6506 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6507
4d487cff
VS		 6508 /*
6509 * WaProgramL3SqcReg1Default:bdw
6510 * WaTempDisableDOPClkGating:bdw
6511 */
6512 misccpctl = I915_READ(GEN7_MISCCPCTL);
6513 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6514 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6515 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6516
6d50b065
VS		 6517 /*
6518 * WaGttCachingOffByDefault:bdw
6519 * GTT cache may not work with big pages, so if those
6520 * are ever enabled GTT cache may need to be disabled.
6521 */
6522 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6523
89d6b2b8 6524 lpt_init_clock_gating(dev);
1020a5c2
BW		 6525}
6526
cad2a2d7
ED		 6527static void haswell_init_clock_gating(struct drm_device *dev)
6528{
6529 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6530
017636cc 6531 ilk_init_lp_watermarks(dev);
cad2a2d7 6532
f3fc4884
FJ		 6533 /* L3 caching of data atomics doesn't work -- disable it. */
6534 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6535 I915_WRITE(HSW_ROW_CHICKEN3,
6536 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6537
ecdb4eb7 6538 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6539 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6540 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6541 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6542
e36ea7ff
VS		 6543 /* WaVSRefCountFullforceMissDisable:hsw */
6544 I915_WRITE(GEN7_FF_THREAD_MODE,
6545 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6546
4e04632e
AG		 6547 /* WaDisable_RenderCache_OperationalFlush:hsw */
6548 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6549
fe27c606
CW		 6550 /* enable HiZ Raw Stall Optimization */
6551 I915_WRITE(CACHE_MODE_0_GEN7,
6552 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6553
ecdb4eb7 6554 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6555 I915_WRITE(CACHE_MODE_1,
6556 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6557
a12c4967
VS		 6558 /*
6559 * BSpec recommends 8x4 when MSAA is used,
6560 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6561 *
6562 * Note that PS/WM thread counts depend on the WIZ hashing
6563 * disable bit, which we don't touch here, but it's good
6564 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6565 */
6566 I915_WRITE(GEN7_GT_MODE,
98533251 6567 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6568
94411593
KG		 6569 /* WaSampleCChickenBitEnable:hsw */
6570 I915_WRITE(HALF_SLICE_CHICKEN3,
6571 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6572
ecdb4eb7 6573 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6574 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6575
90a88643
PZ		 6576 /* WaRsPkgCStateDisplayPMReq:hsw */
6577 I915_WRITE(CHICKEN_PAR1_1,
6578 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6579
17a303ec 6580 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6581}
6582
1fa61106 6583static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6584{
6585 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6586 uint32_t snpcr;
6f1d69b0 6587
017636cc 6588 ilk_init_lp_watermarks(dev);
6f1d69b0 6589
231e54f6 6590 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6591
ecdb4eb7 6592 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6593 I915_WRITE(_3D_CHICKEN3,
6594 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6595
ecdb4eb7 6596 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6597 I915_WRITE(IVB_CHICKEN3,
6598 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6599 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6600
ecdb4eb7 6601 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6602 if (IS_IVB_GT1(dev))
6603 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6604 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6605
4e04632e
AG		 6606 /* WaDisable_RenderCache_OperationalFlush:ivb */
6607 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6608
ecdb4eb7 6609 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6610 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6611 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6612
ecdb4eb7 6613 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6614 I915_WRITE(GEN7_L3CNTLREG1,
6615 GEN7_WA_FOR_GEN7_L3_CONTROL);
6616 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6617 GEN7_WA_L3_CHICKEN_MODE);
6618 if (IS_IVB_GT1(dev))
6619 I915_WRITE(GEN7_ROW_CHICKEN2,
6620 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6621 else {
6622 /* must write both registers */
6623 I915_WRITE(GEN7_ROW_CHICKEN2,
6624 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6625 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6626 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6627 }
6f1d69b0 6628
ecdb4eb7 6629 /* WaForceL3Serialization:ivb */
61939d97
JB		 6630 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6631 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6632
1b80a19a 6633 /*
0f846f81 6634 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6635 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6636 */
6637 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6638 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6639
ecdb4eb7 6640 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6641 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6642 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6643 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6644
0e088b8f 6645 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6646
6647 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6648
22721343
CW		 6649 if (0) { /* causes HiZ corruption on ivb:gt1 */
6650 /* enable HiZ Raw Stall Optimization */
6651 I915_WRITE(CACHE_MODE_0_GEN7,
6652 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6653 }
116f2b6d 6654
ecdb4eb7 6655 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6656 I915_WRITE(CACHE_MODE_1,
6657 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6658
a607c1a4
VS		 6659 /*
6660 * BSpec recommends 8x4 when MSAA is used,
6661 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6662 *
6663 * Note that PS/WM thread counts depend on the WIZ hashing
6664 * disable bit, which we don't touch here, but it's good
6665 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6666 */
6667 I915_WRITE(GEN7_GT_MODE,
98533251 6668 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6669
20848223
BW		 6670 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6671 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6672 snpcr |= GEN6_MBC_SNPCR_MED;
6673 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6674
ab5c608b
BW		 6675 if (!HAS_PCH_NOP(dev))
6676 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6677
6678 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6679}
6680
c6beb13e
VS		 6681static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6682{
6683 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6684
6685 /*
6686 * Disable trickle feed and enable pnd deadline calculation
6687 */
6688 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6689 I915_WRITE(CBR1_VLV, 0);
6690}
6691
1fa61106 6692static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6693{
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6695
c6beb13e 6696 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6697
ecdb4eb7 6698 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6699 I915_WRITE(_3D_CHICKEN3,
6700 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6701
ecdb4eb7 6702 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6703 I915_WRITE(IVB_CHICKEN3,
6704 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6705 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6706
fad7d36e 6707 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6708 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6709 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6710 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6711 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6712
4e04632e
AG		 6713 /* WaDisable_RenderCache_OperationalFlush:vlv */
6714 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6715
ecdb4eb7 6716 /* WaForceL3Serialization:vlv */
61939d97
JB		 6717 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6718 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6719
ecdb4eb7 6720 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6721 I915_WRITE(GEN7_ROW_CHICKEN2,
6722 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6723
ecdb4eb7 6724 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6725 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6726 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6727 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6728
46680e0a
VS		 6729 gen7_setup_fixed_func_scheduler(dev_priv);
6730
3c0edaeb 6731 /*
0f846f81 6732 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6733 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6734 */
6735 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6736 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6737
c98f5062
AG		 6738 /* WaDisableL3Bank2xClockGate:vlv
6739 * Disabling L3 clock gating- MMIO 940c[25] = 1
6740 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6741 I915_WRITE(GEN7_UCGCTL4,
6742 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6743
afd58e79
VS		 6744 /*
6745 * BSpec says this must be set, even though
6746 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6747 */
6b26c86d
DV		 6748 I915_WRITE(CACHE_MODE_1,
6749 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6750
da2518f9
VS		 6751 /*
6752 * BSpec recommends 8x4 when MSAA is used,
6753 * however in practice 16x4 seems fastest.
6754 *
6755 * Note that PS/WM thread counts depend on the WIZ hashing
6756 * disable bit, which we don't touch here, but it's good
6757 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6758 */
6759 I915_WRITE(GEN7_GT_MODE,
6760 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6761
031994ee
VS		 6762 /*
6763 * WaIncreaseL3CreditsForVLVB0:vlv
6764 * This is the hardware default actually.
6765 */
6766 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6767
2d809570 6768 /*
ecdb4eb7 6769 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6770 * Disable clock gating on th GCFG unit to prevent a delay
6771 * in the reporting of vblank events.
6772 */
7a0d1eed 6773 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6774}
6775
a4565da8
VS		 6776static void cherryview_init_clock_gating(struct drm_device *dev)
6777{
6778 struct drm_i915_private *dev_priv = dev->dev_private;
6779
c6beb13e 6780 vlv_init_display_clock_gating(dev_priv);
dd811e70 6781
232ce337
VS		 6782 /* WaVSRefCountFullforceMissDisable:chv */
6783 /* WaDSRefCountFullforceMissDisable:chv */
6784 I915_WRITE(GEN7_FF_THREAD_MODE,
6785 I915_READ(GEN7_FF_THREAD_MODE) &
6786 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6787
6788 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6789 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6790 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6791
6792 /* WaDisableCSUnitClockGating:chv */
6793 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6794 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6795
6796 /* WaDisableSDEUnitClockGating:chv */
6797 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6798 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6799
6800 /*
6801 * GTT cache may not work with big pages, so if those
6802 * are ever enabled GTT cache may need to be disabled.
6803 */
6804 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6805}
6806
1fa61106 6807static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6808{
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 uint32_t dspclk_gate;
6811
6812 I915_WRITE(RENCLK_GATE_D1, 0);
6813 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6814 GS_UNIT_CLOCK_GATE_DISABLE |
6815 CL_UNIT_CLOCK_GATE_DISABLE);
6816 I915_WRITE(RAMCLK_GATE_D, 0);
6817 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6818 OVRUNIT_CLOCK_GATE_DISABLE |
6819 OVCUNIT_CLOCK_GATE_DISABLE;
6820 if (IS_GM45(dev))
6821 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6822 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6823
6824 /* WaDisableRenderCachePipelinedFlush */
6825 I915_WRITE(CACHE_MODE_0,
6826 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6827
4e04632e
AG		 6828 /* WaDisable_RenderCache_OperationalFlush:g4x */
6829 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6830
0e088b8f 6831 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6832}
6833
1fa61106 6834static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6835{
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837
6838 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6839 I915_WRITE(RENCLK_GATE_D2, 0);
6840 I915_WRITE(DSPCLK_GATE_D, 0);
6841 I915_WRITE(RAMCLK_GATE_D, 0);
6842 I915_WRITE16(DEUC, 0);
20f94967
VS		 6843 I915_WRITE(MI_ARB_STATE,
6844 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6845
6846 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6847 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6848}
6849
1fa61106 6850static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6851{
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853
6854 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6855 I965_RCC_CLOCK_GATE_DISABLE |
6856 I965_RCPB_CLOCK_GATE_DISABLE |
6857 I965_ISC_CLOCK_GATE_DISABLE |
6858 I965_FBC_CLOCK_GATE_DISABLE);
6859 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6860 I915_WRITE(MI_ARB_STATE,
6861 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6862
6863 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6864 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6865}
6866
1fa61106 6867static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6868{
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 u32 dstate = I915_READ(D_STATE);
6871
6872 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6873 DSTATE_DOT_CLOCK_GATING;
6874 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6875
6876 if (IS_PINEVIEW(dev))
6877 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6878
6879 /* IIR "flip pending" means done if this bit is set */
6880 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6881
6882 /* interrupts should cause a wake up from C3 */
3299254f 6883 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6884
6885 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6886 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6887
6888 I915_WRITE(MI_ARB_STATE,
6889 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6890}
6891
1fa61106 6892static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6893{
6894 struct drm_i915_private *dev_priv = dev->dev_private;
6895
6896 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6897
6898 /* interrupts should cause a wake up from C3 */
6899 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6900 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6901
6902 I915_WRITE(MEM_MODE,
6903 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6904}
6905
1fa61106 6906static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6907{
6908 struct drm_i915_private *dev_priv = dev->dev_private;
6909
6910 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6911
6912 I915_WRITE(MEM_MODE,
6913 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6914 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6915}
6916
6f1d69b0
ED		 6917void intel_init_clock_gating(struct drm_device *dev)
6918{
6919 struct drm_i915_private *dev_priv = dev->dev_private;
6920
c57e3551
DL		 6921 if (dev_priv->display.init_clock_gating)
6922 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6923}
6924
7d708ee4
ID		 6925void intel_suspend_hw(struct drm_device *dev)
6926{
6927 if (HAS_PCH_LPT(dev))
6928 lpt_suspend_hw(dev);
6929}
6930
1fa61106
ED		 6931/* Set up chip specific power management-related functions */
6932void intel_init_pm(struct drm_device *dev)
6933{
6934 struct drm_i915_private *dev_priv = dev->dev_private;
6935
7ff0ebcc 6936 intel_fbc_init(dev_priv);
1fa61106 6937
c921aba8
DV		 6938 /* For cxsr */
6939 if (IS_PINEVIEW(dev))
6940 i915_pineview_get_mem_freq(dev);
6941 else if (IS_GEN5(dev))
6942 i915_ironlake_get_mem_freq(dev);
6943
1fa61106 6944 /* For FIFO watermark updates */
f5ed50cb 6945 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6946 skl_setup_wm_latency(dev);
6947
a82abe43
ID		 6948 if (IS_BROXTON(dev))
6949 dev_priv->display.init_clock_gating =
6950 bxt_init_clock_gating;
2d41c0b5 6951 dev_priv->display.update_wm = skl_update_wm;
c83155a6 6952 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6953 ilk_setup_wm_latency(dev);
53615a5e 6954
bd602544
VS		 6955 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6956 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6957 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6958 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6959 dev_priv->display.update_wm = ilk_update_wm;
86c8bbbe 6960 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
bd602544
VS		 6961 } else {
6962 DRM_DEBUG_KMS("Failed to read display plane latency. "
6963 "Disable CxSR\n");
6964 }
6965
6966 if (IS_GEN5(dev))
1fa61106 6967 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6968 else if (IS_GEN6(dev))
1fa61106 6969 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6970 else if (IS_IVYBRIDGE(dev))
1fa61106 6971 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6972 else if (IS_HASWELL(dev))
cad2a2d7 6973 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6974 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6975 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6976 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 6977 vlv_setup_wm_latency(dev);
6978
6979 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 6980 dev_priv->display.init_clock_gating =
6981 cherryview_init_clock_gating;
1fa61106 6982 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 6983 vlv_setup_wm_latency(dev);
6984
6985 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 6986 dev_priv->display.init_clock_gating =
6987 valleyview_init_clock_gating;
1fa61106
ED		 6988 } else if (IS_PINEVIEW(dev)) {
6989 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6990 dev_priv->is_ddr3,
6991 dev_priv->fsb_freq,
6992 dev_priv->mem_freq)) {
6993 DRM_INFO("failed to find known CxSR latency "
6994 "(found ddr%s fsb freq %d, mem freq %d), "
6995 "disabling CxSR\n",
6996 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6997 dev_priv->fsb_freq, dev_priv->mem_freq);
6998 /* Disable CxSR and never update its watermark again */
5209b1f4 6999 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7000 dev_priv->display.update_wm = NULL;
7001 } else
7002 dev_priv->display.update_wm = pineview_update_wm;
7003 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7004 } else if (IS_G4X(dev)) {
7005 dev_priv->display.update_wm = g4x_update_wm;
7006 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7007 } else if (IS_GEN4(dev)) {
7008 dev_priv->display.update_wm = i965_update_wm;
7009 if (IS_CRESTLINE(dev))
7010 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7011 else if (IS_BROADWATER(dev))
7012 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7013 } else if (IS_GEN3(dev)) {
7014 dev_priv->display.update_wm = i9xx_update_wm;
7015 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7016 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7017 } else if (IS_GEN2(dev)) {
7018 if (INTEL_INFO(dev)->num_pipes == 1) {
7019 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7020 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7021 } else {
7022 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7023 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7024 }
7025
7026 if (IS_I85X(dev) || IS_I865G(dev))
7027 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7028 else
7029 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7030 } else {
7031 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7032 }
7033}
7034
151a49d0 7035int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7036{
4fc688ce 7037 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7038
7039 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7040 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7041 return -EAGAIN;
7042 }
7043
7044 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7045 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7046 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7047
7048 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7049 500)) {
7050 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7051 return -ETIMEDOUT;
7052 }
7053
7054 *val = I915_READ(GEN6_PCODE_DATA);
7055 I915_WRITE(GEN6_PCODE_DATA, 0);
7056
7057 return 0;
7058}
7059
151a49d0 7060int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7061{
4fc688ce 7062 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7063
7064 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7065 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7066 return -EAGAIN;
7067 }
7068
7069 I915_WRITE(GEN6_PCODE_DATA, val);
7070 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7071
7072 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7073 500)) {
7074 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7075 return -ETIMEDOUT;
7076 }
7077
7078 I915_WRITE(GEN6_PCODE_DATA, 0);
7079
7080 return 0;
7081}
a0e4e199 7082
dd06f88c 7083static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7084{
dd06f88c
VS		 7085 switch (czclk_freq) {
7086 case 200:
7087 return 10;
7088 case 267:
7089 return 12;
7090 case 320:
7091 case 333:
dd06f88c 7092 return 16;
ab3fb157
VS		 7093 case 400:
7094 return 20;
855ba3be
JB		 7095 default:
7096 return -1;
7097 }
dd06f88c 7098}
855ba3be 7099
dd06f88c
VS		 7100static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7101{
bfa7df01 7102 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7103
7104 div = vlv_gpu_freq_div(czclk_freq);
7105 if (div < 0)
7106 return div;
7107
7108 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7109}
7110
b55dd647 7111static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7112{
bfa7df01 7113 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7114
dd06f88c
VS		 7115 mul = vlv_gpu_freq_div(czclk_freq);
7116 if (mul < 0)
7117 return mul;
855ba3be 7118
dd06f88c 7119 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7120}
7121
b55dd647 7122static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7123{
bfa7df01 7124 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7125
dd06f88c
VS		 7126 div = vlv_gpu_freq_div(czclk_freq) / 2;
7127 if (div < 0)
7128 return div;
22b1b2f8 7129
dd06f88c 7130 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7131}
7132
b55dd647 7133static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7134{
bfa7df01 7135 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7136
dd06f88c
VS		 7137 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7138 if (mul < 0)
7139 return mul;
22b1b2f8 7140
1c14762d 7141 /* CHV needs even values */
dd06f88c 7142 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7143}
7144
616bc820 7145int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7146{
80b6dda4 7147 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7148 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7149 GEN9_FREQ_SCALER);
80b6dda4 7150 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7151 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7152 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7153 return byt_gpu_freq(dev_priv, val);
7154 else
7155 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7156}
7157
616bc820
VS		 7158int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7159{
80b6dda4 7160 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7161 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7162 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7163 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7164 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7165 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7166 return byt_freq_opcode(dev_priv, val);
7167 else
500a3d2e 7168 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7169}
22b1b2f8 7170
6ad790c0
CW		 7171struct request_boost {
7172 struct work_struct work;
eed29a5b 7173 struct drm_i915_gem_request *req;
6ad790c0
CW		 7174};
7175
7176static void __intel_rps_boost_work(struct work_struct *work)
7177{
7178 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7179 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7180
e61b9958
CW		 7181 if (!i915_gem_request_completed(req, true))
7182 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7183 req->emitted_jiffies);
6ad790c0 7184
e61b9958 7185 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7186 kfree(boost);
7187}
7188
7189void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7190 struct drm_i915_gem_request *req)
6ad790c0
CW		 7191{
7192 struct request_boost *boost;
7193
eed29a5b 7194 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7195 return;
7196
e61b9958
CW		 7197 if (i915_gem_request_completed(req, true))
7198 return;
7199
6ad790c0
CW		 7200 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7201 if (boost == NULL)
7202 return;
7203
eed29a5b
DV		 7204 i915_gem_request_reference(req);
7205 boost->req = req;
6ad790c0
CW		 7206
7207 INIT_WORK(&boost->work, __intel_rps_boost_work);
7208 queue_work(to_i915(dev)->wq, &boost->work);
7209}
7210
f742a552 7211void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7212{
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214
f742a552 7215 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7216 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7217
907b28c5
CW		 7218 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7219 intel_gen6_powersave_work);
1854d5ca 7220 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7221 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7222 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7223
33688d95 7224 dev_priv->pm.suspended = false;
907b28c5 7225}
Linux kernel - Deliverables
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