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drm/i915: Extract CFB threshold calculation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 152 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 224 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 280 struct drm_framebuffer *fb = crtc->primary->fb;
abe959c7
RV		 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
28554164 300 } else {
2adb6db8 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
891348b2 305 }
b74ea102 306
abe959c7
RV		 307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
310
311 sandybridge_blit_fbc_update(dev);
312
b19870ee 313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 314}
315
85208be0
ED		 316bool intel_fbc_enabled(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (!dev_priv->display.fbc_enabled)
321 return false;
322
323 return dev_priv->display.fbc_enabled(dev);
324}
325
326static void intel_fbc_work_fn(struct work_struct *__work)
327{
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333
334 mutex_lock(&dev->struct_mutex);
5c3fe8b0 335 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 336 /* Double check that we haven't switched fb without cancelling
337 * the prior work.
338 */
f4510a27 339 if (work->crtc->primary->fb == work->fb) {
993495ae 340 dev_priv->display.enable_fbc(work->crtc);
85208be0 341
5c3fe8b0 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 344 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 345 }
346
5c3fe8b0 347 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 348 }
349 mutex_unlock(&dev->struct_mutex);
350
351 kfree(work);
352}
353
354static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
355{
5c3fe8b0 356 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 357 return;
358
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
360
361 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 363 * entirely asynchronously.
364 */
5c3fe8b0 365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 366 /* tasklet was killed before being run, clean up */
5c3fe8b0 367 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 368
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
372 * necessary to run.
373 */
5c3fe8b0 374 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 375}
376
993495ae 377static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 378{
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382
383 if (!dev_priv->display.enable_fbc)
384 return;
385
386 intel_cancel_fbc_work(dev_priv);
387
b14c5679 388 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 389 if (work == NULL) {
6cdcb5e7 390 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 391 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 392 return;
393 }
394
395 work->crtc = crtc;
f4510a27 396 work->fb = crtc->primary->fb;
85208be0
ED		 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
398
5c3fe8b0 399 dev_priv->fbc.fbc_work = work;
85208be0 400
85208be0
ED		 401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
406 *
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
7457d617
DL		 411 *
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 413 */
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
415}
416
417void intel_disable_fbc(struct drm_device *dev)
418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420
421 intel_cancel_fbc_work(dev_priv);
422
423 if (!dev_priv->display.disable_fbc)
424 return;
425
426 dev_priv->display.disable_fbc(dev);
5c3fe8b0 427 dev_priv->fbc.plane = -1;
85208be0
ED		 428}
429
29ebf90f
CW		 430static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
432{
433 if (dev_priv->fbc.no_fbc_reason == reason)
434 return false;
435
436 dev_priv->fbc.no_fbc_reason = reason;
437 return true;
438}
439
85208be0
ED		 440/**
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
443 *
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
449 * - no dual wide
f85da868 450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 451 *
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
455 * stolen memory.
456 *
457 * We need to enable/disable FBC on a global basis.
458 */
459void intel_update_fbc(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
ef644fda 467 const struct drm_display_mode *adjusted_mode;
37327abd 468 unsigned int max_width, max_height;
85208be0 469
3a77c4c4 470 if (!HAS_FBC(dev)) {
29ebf90f 471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 472 return;
29ebf90f 473 }
85208be0 474
d330a953 475 if (!i915.powersave) {
29ebf90f
CW		 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 478 return;
29ebf90f 479 }
85208be0
ED		 480
481 /*
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
489 */
70e1e0ec 490 for_each_crtc(dev, tmp_crtc) {
3490ea5d 491 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 492 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 493 if (crtc) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 496 goto out_disable;
497 }
498 crtc = tmp_crtc;
499 }
500 }
501
f4510a27 502 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 505 goto out_disable;
506 }
507
508 intel_crtc = to_intel_crtc(crtc);
f4510a27 509 fb = crtc->primary->fb;
85208be0
ED		 510 intel_fb = to_intel_framebuffer(fb);
511 obj = intel_fb->obj;
ef644fda 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 513
d330a953 514 if (i915.enable_fbc < 0 &&
8a5729a3 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 518 goto out_disable;
85208be0 519 }
d330a953 520 if (!i915.enable_fbc) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 523 goto out_disable;
524 }
ef644fda
VS		 525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
529 "disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
f85da868 532
032843a5
DS		 533 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
534 max_width = 4096;
535 max_height = 4096;
536 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 537 max_width = 4096;
538 max_height = 2048;
f85da868 539 } else {
37327abd
VS		 540 max_width = 2048;
541 max_height = 1536;
f85da868 542 }
37327abd
VS		 543 if (intel_crtc->config.pipe_src_w > max_width ||
544 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 545 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
546 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 547 goto out_disable;
548 }
8f94d24b 549 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 550 intel_crtc->plane != PLANE_A) {
29ebf90f 551 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 552 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 553 goto out_disable;
554 }
555
556 /* The use of a CPU fence is mandatory in order to detect writes
557 * by the CPU to the scanout and trigger updates to the FBC.
558 */
559 if (obj->tiling_mode != I915_TILING_X ||
560 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 561 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
562 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 563 goto out_disable;
564 }
565
566 /* If the kernel debugger is active, always disable compression */
567 if (in_dbg_master())
568 goto out_disable;
569
11be49eb 570 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 571 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
572 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 573 goto out_disable;
574 }
575
85208be0
ED		 576 /* If the scanout has not changed, don't modify the FBC settings.
577 * Note that we make the fundamental assumption that the fb->obj
578 * cannot be unpinned (and have its GTT offset and fence revoked)
579 * without first being decoupled from the scanout and FBC disabled.
580 */
5c3fe8b0
BW		 581 if (dev_priv->fbc.plane == intel_crtc->plane &&
582 dev_priv->fbc.fb_id == fb->base.id &&
583 dev_priv->fbc.y == crtc->y)
85208be0
ED		 584 return;
585
586 if (intel_fbc_enabled(dev)) {
587 /* We update FBC along two paths, after changing fb/crtc
588 * configuration (modeswitching) and after page-flipping
589 * finishes. For the latter, we know that not only did
590 * we disable the FBC at the start of the page-flip
591 * sequence, but also more than one vblank has passed.
592 *
593 * For the former case of modeswitching, it is possible
594 * to switch between two FBC valid configurations
595 * instantaneously so we do need to disable the FBC
596 * before we can modify its control registers. We also
597 * have to wait for the next vblank for that to take
598 * effect. However, since we delay enabling FBC we can
599 * assume that a vblank has passed since disabling and
600 * that we can safely alter the registers in the deferred
601 * callback.
602 *
603 * In the scenario that we go from a valid to invalid
604 * and then back to valid FBC configuration we have
605 * no strict enforcement that a vblank occurred since
606 * disabling the FBC. However, along all current pipe
607 * disabling paths we do need to wait for a vblank at
608 * some point. And we wait before enabling FBC anyway.
609 */
610 DRM_DEBUG_KMS("disabling active FBC for update\n");
611 intel_disable_fbc(dev);
612 }
613
993495ae 614 intel_enable_fbc(crtc);
29ebf90f 615 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 616 return;
617
618out_disable:
619 /* Multiple disables should be harmless */
620 if (intel_fbc_enabled(dev)) {
621 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
622 intel_disable_fbc(dev);
623 }
11be49eb 624 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 625}
626
c921aba8
DV		 627static void i915_pineview_get_mem_freq(struct drm_device *dev)
628{
50227e1c 629 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 630 u32 tmp;
631
632 tmp = I915_READ(CLKCFG);
633
634 switch (tmp & CLKCFG_FSB_MASK) {
635 case CLKCFG_FSB_533:
636 dev_priv->fsb_freq = 533; /* 133*4 */
637 break;
638 case CLKCFG_FSB_800:
639 dev_priv->fsb_freq = 800; /* 200*4 */
640 break;
641 case CLKCFG_FSB_667:
642 dev_priv->fsb_freq = 667; /* 167*4 */
643 break;
644 case CLKCFG_FSB_400:
645 dev_priv->fsb_freq = 400; /* 100*4 */
646 break;
647 }
648
649 switch (tmp & CLKCFG_MEM_MASK) {
650 case CLKCFG_MEM_533:
651 dev_priv->mem_freq = 533;
652 break;
653 case CLKCFG_MEM_667:
654 dev_priv->mem_freq = 667;
655 break;
656 case CLKCFG_MEM_800:
657 dev_priv->mem_freq = 800;
658 break;
659 }
660
661 /* detect pineview DDR3 setting */
662 tmp = I915_READ(CSHRDDR3CTL);
663 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
664}
665
666static void i915_ironlake_get_mem_freq(struct drm_device *dev)
667{
50227e1c 668 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 669 u16 ddrpll, csipll;
670
671 ddrpll = I915_READ16(DDRMPLL1);
672 csipll = I915_READ16(CSIPLL0);
673
674 switch (ddrpll & 0xff) {
675 case 0xc:
676 dev_priv->mem_freq = 800;
677 break;
678 case 0x10:
679 dev_priv->mem_freq = 1066;
680 break;
681 case 0x14:
682 dev_priv->mem_freq = 1333;
683 break;
684 case 0x18:
685 dev_priv->mem_freq = 1600;
686 break;
687 default:
688 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
689 ddrpll & 0xff);
690 dev_priv->mem_freq = 0;
691 break;
692 }
693
20e4d407 694 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 695
696 switch (csipll & 0x3ff) {
697 case 0x00c:
698 dev_priv->fsb_freq = 3200;
699 break;
700 case 0x00e:
701 dev_priv->fsb_freq = 3733;
702 break;
703 case 0x010:
704 dev_priv->fsb_freq = 4266;
705 break;
706 case 0x012:
707 dev_priv->fsb_freq = 4800;
708 break;
709 case 0x014:
710 dev_priv->fsb_freq = 5333;
711 break;
712 case 0x016:
713 dev_priv->fsb_freq = 5866;
714 break;
715 case 0x018:
716 dev_priv->fsb_freq = 6400;
717 break;
718 default:
719 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
720 csipll & 0x3ff);
721 dev_priv->fsb_freq = 0;
722 break;
723 }
724
725 if (dev_priv->fsb_freq == 3200) {
20e4d407 726 dev_priv->ips.c_m = 0;
c921aba8 727 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 728 dev_priv->ips.c_m = 1;
c921aba8 729 } else {
20e4d407 730 dev_priv->ips.c_m = 2;
c921aba8
DV		 731 }
732}
733
b445e3b0
ED		 734static const struct cxsr_latency cxsr_latency_table[] = {
735 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
736 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
737 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
738 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
739 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
740
741 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
742 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
743 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
744 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
745 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
746
747 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
748 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
749 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
750 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
751 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
752
753 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
754 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
755 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
756 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
757 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
758
759 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
760 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
761 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
762 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
763 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
764
765 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
766 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
767 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
768 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
769 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
770};
771
63c62275 772static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 773 int is_ddr3,
774 int fsb,
775 int mem)
776{
777 const struct cxsr_latency *latency;
778 int i;
779
780 if (fsb == 0 || mem == 0)
781 return NULL;
782
783 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
784 latency = &cxsr_latency_table[i];
785 if (is_desktop == latency->is_desktop &&
786 is_ddr3 == latency->is_ddr3 &&
787 fsb == latency->fsb_freq && mem == latency->mem_freq)
788 return latency;
789 }
790
791 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
792
793 return NULL;
794}
795
1fa61106 796static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 797{
798 struct drm_i915_private *dev_priv = dev->dev_private;
799
800 /* deactivate cxsr */
801 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
802}
803
804/*
805 * Latency for FIFO fetches is dependent on several factors:
806 * - memory configuration (speed, channels)
807 * - chipset
808 * - current MCH state
809 * It can be fairly high in some situations, so here we assume a fairly
810 * pessimal value. It's a tradeoff between extra memory fetches (if we
811 * set this value too high, the FIFO will fetch frequently to stay full)
812 * and power consumption (set it too low to save power and we might see
813 * FIFO underruns and display "flicker").
814 *
815 * A value of 5us seems to be a good balance; safe for very low end
816 * platforms but not overly aggressive on lower latency configs.
817 */
818static const int latency_ns = 5000;
819
1fa61106 820static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 821{
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t dsparb = I915_READ(DSPARB);
824 int size;
825
826 size = dsparb & 0x7f;
827 if (plane)
828 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
829
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
832
833 return size;
834}
835
feb56b93 836static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 837{
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
840 int size;
841
842 size = dsparb & 0x1ff;
843 if (plane)
844 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
845 size >>= 1; /* Convert to cachelines */
846
847 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
848 plane ? "B" : "A", size);
849
850 return size;
851}
852
1fa61106 853static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 uint32_t dsparb = I915_READ(DSPARB);
857 int size;
858
859 size = dsparb & 0x7f;
860 size >>= 2; /* Convert to cachelines */
861
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
863 plane ? "B" : "A",
864 size);
865
866 return size;
867}
868
b445e3b0
ED		 869/* Pineview has different values for various configs */
870static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 871 .fifo_size = PINEVIEW_DISPLAY_FIFO,
872 .max_wm = PINEVIEW_MAX_WM,
873 .default_wm = PINEVIEW_DFT_WM,
874 .guard_size = PINEVIEW_GUARD_WM,
875 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 876};
877static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 878 .fifo_size = PINEVIEW_DISPLAY_FIFO,
879 .max_wm = PINEVIEW_MAX_WM,
880 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
881 .guard_size = PINEVIEW_GUARD_WM,
882 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 883};
884static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 885 .fifo_size = PINEVIEW_CURSOR_FIFO,
886 .max_wm = PINEVIEW_CURSOR_MAX_WM,
887 .default_wm = PINEVIEW_CURSOR_DFT_WM,
888 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
889 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 890};
891static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 892 .fifo_size = PINEVIEW_CURSOR_FIFO,
893 .max_wm = PINEVIEW_CURSOR_MAX_WM,
894 .default_wm = PINEVIEW_CURSOR_DFT_WM,
895 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
896 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 897};
898static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 899 .fifo_size = G4X_FIFO_SIZE,
900 .max_wm = G4X_MAX_WM,
901 .default_wm = G4X_MAX_WM,
902 .guard_size = 2,
903 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 904};
905static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 906 .fifo_size = I965_CURSOR_FIFO,
907 .max_wm = I965_CURSOR_MAX_WM,
908 .default_wm = I965_CURSOR_DFT_WM,
909 .guard_size = 2,
910 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 911};
912static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 913 .fifo_size = VALLEYVIEW_FIFO_SIZE,
914 .max_wm = VALLEYVIEW_MAX_WM,
915 .default_wm = VALLEYVIEW_MAX_WM,
916 .guard_size = 2,
917 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 918};
919static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 920 .fifo_size = I965_CURSOR_FIFO,
921 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
922 .default_wm = I965_CURSOR_DFT_WM,
923 .guard_size = 2,
924 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 925};
926static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 927 .fifo_size = I965_CURSOR_FIFO,
928 .max_wm = I965_CURSOR_MAX_WM,
929 .default_wm = I965_CURSOR_DFT_WM,
930 .guard_size = 2,
931 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 932};
933static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 934 .fifo_size = I945_FIFO_SIZE,
935 .max_wm = I915_MAX_WM,
936 .default_wm = 1,
937 .guard_size = 2,
938 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 939};
940static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 941 .fifo_size = I915_FIFO_SIZE,
942 .max_wm = I915_MAX_WM,
943 .default_wm = 1,
944 .guard_size = 2,
945 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 946};
feb56b93 947static const struct intel_watermark_params i830_wm_info = {
e0f0273e
VS		 948 .fifo_size = I855GM_FIFO_SIZE,
949 .max_wm = I915_MAX_WM,
950 .default_wm = 1,
951 .guard_size = 2,
952 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 953};
feb56b93 954static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 955 .fifo_size = I830_FIFO_SIZE,
956 .max_wm = I915_MAX_WM,
957 .default_wm = 1,
958 .guard_size = 2,
959 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 960};
961
b445e3b0
ED		 962/**
963 * intel_calculate_wm - calculate watermark level
964 * @clock_in_khz: pixel clock
965 * @wm: chip FIFO params
966 * @pixel_size: display pixel size
967 * @latency_ns: memory latency for the platform
968 *
969 * Calculate the watermark level (the level at which the display plane will
970 * start fetching from memory again). Each chip has a different display
971 * FIFO size and allocation, so the caller needs to figure that out and pass
972 * in the correct intel_watermark_params structure.
973 *
974 * As the pixel clock runs, the FIFO will be drained at a rate that depends
975 * on the pixel size. When it reaches the watermark level, it'll start
976 * fetching FIFO line sized based chunks from memory until the FIFO fills
977 * past the watermark point. If the FIFO drains completely, a FIFO underrun
978 * will occur, and a display engine hang could result.
979 */
980static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
981 const struct intel_watermark_params *wm,
982 int fifo_size,
983 int pixel_size,
984 unsigned long latency_ns)
985{
986 long entries_required, wm_size;
987
988 /*
989 * Note: we need to make sure we don't overflow for various clock &
990 * latency values.
991 * clocks go from a few thousand to several hundred thousand.
992 * latency is usually a few thousand
993 */
994 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
995 1000;
996 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
997
998 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
999
1000 wm_size = fifo_size - (entries_required + wm->guard_size);
1001
1002 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1003
1004 /* Don't promote wm_size to unsigned... */
1005 if (wm_size > (long)wm->max_wm)
1006 wm_size = wm->max_wm;
1007 if (wm_size <= 0)
1008 wm_size = wm->default_wm;
1009 return wm_size;
1010}
1011
1012static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1013{
1014 struct drm_crtc *crtc, *enabled = NULL;
1015
70e1e0ec 1016 for_each_crtc(dev, crtc) {
3490ea5d 1017 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1018 if (enabled)
1019 return NULL;
1020 enabled = crtc;
1021 }
1022 }
1023
1024 return enabled;
1025}
1026
46ba614c 1027static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1028{
46ba614c 1029 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct drm_crtc *crtc;
1032 const struct cxsr_latency *latency;
1033 u32 reg;
1034 unsigned long wm;
1035
1036 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1037 dev_priv->fsb_freq, dev_priv->mem_freq);
1038 if (!latency) {
1039 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1040 pineview_disable_cxsr(dev);
1041 return;
1042 }
1043
1044 crtc = single_enabled_crtc(dev);
1045 if (crtc) {
241bfc38 1046 const struct drm_display_mode *adjusted_mode;
f4510a27 1047 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1048 int clock;
1049
1050 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1051 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1052
1053 /* Display SR */
1054 wm = intel_calculate_wm(clock, &pineview_display_wm,
1055 pineview_display_wm.fifo_size,
1056 pixel_size, latency->display_sr);
1057 reg = I915_READ(DSPFW1);
1058 reg &= ~DSPFW_SR_MASK;
1059 reg |= wm << DSPFW_SR_SHIFT;
1060 I915_WRITE(DSPFW1, reg);
1061 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1062
1063 /* cursor SR */
1064 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1065 pineview_display_wm.fifo_size,
1066 pixel_size, latency->cursor_sr);
1067 reg = I915_READ(DSPFW3);
1068 reg &= ~DSPFW_CURSOR_SR_MASK;
1069 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1070 I915_WRITE(DSPFW3, reg);
1071
1072 /* Display HPLL off SR */
1073 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1074 pineview_display_hplloff_wm.fifo_size,
1075 pixel_size, latency->display_hpll_disable);
1076 reg = I915_READ(DSPFW3);
1077 reg &= ~DSPFW_HPLL_SR_MASK;
1078 reg |= wm & DSPFW_HPLL_SR_MASK;
1079 I915_WRITE(DSPFW3, reg);
1080
1081 /* cursor HPLL off SR */
1082 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1083 pineview_display_hplloff_wm.fifo_size,
1084 pixel_size, latency->cursor_hpll_disable);
1085 reg = I915_READ(DSPFW3);
1086 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1087 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1088 I915_WRITE(DSPFW3, reg);
1089 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1090
1091 /* activate cxsr */
1092 I915_WRITE(DSPFW3,
1093 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1094 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1095 } else {
1096 pineview_disable_cxsr(dev);
1097 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1098 }
1099}
1100
1101static bool g4x_compute_wm0(struct drm_device *dev,
1102 int plane,
1103 const struct intel_watermark_params *display,
1104 int display_latency_ns,
1105 const struct intel_watermark_params *cursor,
1106 int cursor_latency_ns,
1107 int *plane_wm,
1108 int *cursor_wm)
1109{
1110 struct drm_crtc *crtc;
4fe8590a 1111 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1112 int htotal, hdisplay, clock, pixel_size;
1113 int line_time_us, line_count;
1114 int entries, tlb_miss;
1115
1116 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1117 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1118 *cursor_wm = cursor->guard_size;
1119 *plane_wm = display->guard_size;
1120 return false;
1121 }
1122
4fe8590a 1123 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1124 clock = adjusted_mode->crtc_clock;
fec8cba3 1125 htotal = adjusted_mode->crtc_htotal;
37327abd 1126 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1127 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1128
1129 /* Use the small buffer method to calculate plane watermark */
1130 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1131 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1132 if (tlb_miss > 0)
1133 entries += tlb_miss;
1134 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1135 *plane_wm = entries + display->guard_size;
1136 if (*plane_wm > (int)display->max_wm)
1137 *plane_wm = display->max_wm;
1138
1139 /* Use the large buffer method to calculate cursor watermark */
922044c9 1140 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1141 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1142 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1143 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1144 if (tlb_miss > 0)
1145 entries += tlb_miss;
1146 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1147 *cursor_wm = entries + cursor->guard_size;
1148 if (*cursor_wm > (int)cursor->max_wm)
1149 *cursor_wm = (int)cursor->max_wm;
1150
1151 return true;
1152}
1153
1154/*
1155 * Check the wm result.
1156 *
1157 * If any calculated watermark values is larger than the maximum value that
1158 * can be programmed into the associated watermark register, that watermark
1159 * must be disabled.
1160 */
1161static bool g4x_check_srwm(struct drm_device *dev,
1162 int display_wm, int cursor_wm,
1163 const struct intel_watermark_params *display,
1164 const struct intel_watermark_params *cursor)
1165{
1166 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1167 display_wm, cursor_wm);
1168
1169 if (display_wm > display->max_wm) {
1170 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1171 display_wm, display->max_wm);
1172 return false;
1173 }
1174
1175 if (cursor_wm > cursor->max_wm) {
1176 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1177 cursor_wm, cursor->max_wm);
1178 return false;
1179 }
1180
1181 if (!(display_wm || cursor_wm)) {
1182 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1183 return false;
1184 }
1185
1186 return true;
1187}
1188
1189static bool g4x_compute_srwm(struct drm_device *dev,
1190 int plane,
1191 int latency_ns,
1192 const struct intel_watermark_params *display,
1193 const struct intel_watermark_params *cursor,
1194 int *display_wm, int *cursor_wm)
1195{
1196 struct drm_crtc *crtc;
4fe8590a 1197 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1198 int hdisplay, htotal, pixel_size, clock;
1199 unsigned long line_time_us;
1200 int line_count, line_size;
1201 int small, large;
1202 int entries;
1203
1204 if (!latency_ns) {
1205 *display_wm = *cursor_wm = 0;
1206 return false;
1207 }
1208
1209 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1210 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1211 clock = adjusted_mode->crtc_clock;
fec8cba3 1212 htotal = adjusted_mode->crtc_htotal;
37327abd 1213 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1214 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1215
922044c9 1216 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1217 line_count = (latency_ns / line_time_us + 1000) / 1000;
1218 line_size = hdisplay * pixel_size;
1219
1220 /* Use the minimum of the small and large buffer method for primary */
1221 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1222 large = line_count * line_size;
1223
1224 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1225 *display_wm = entries + display->guard_size;
1226
1227 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1228 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1229 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1230 *cursor_wm = entries + cursor->guard_size;
1231
1232 return g4x_check_srwm(dev,
1233 *display_wm, *cursor_wm,
1234 display, cursor);
1235}
1236
1237static bool vlv_compute_drain_latency(struct drm_device *dev,
1238 int plane,
1239 int *plane_prec_mult,
1240 int *plane_dl,
1241 int *cursor_prec_mult,
1242 int *cursor_dl)
1243{
1244 struct drm_crtc *crtc;
1245 int clock, pixel_size;
1246 int entries;
1247
1248 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1249 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1250 return false;
1251
241bfc38 1252 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1253 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1254
1255 entries = (clock / 1000) * pixel_size;
1256 *plane_prec_mult = (entries > 256) ?
1257 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1258 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1259 pixel_size);
1260
1261 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1262 *cursor_prec_mult = (entries > 256) ?
1263 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1264 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1265
1266 return true;
1267}
1268
1269/*
1270 * Update drain latency registers of memory arbiter
1271 *
1272 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1273 * to be programmed. Each plane has a drain latency multiplier and a drain
1274 * latency value.
1275 */
1276
1277static void vlv_update_drain_latency(struct drm_device *dev)
1278{
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1281 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1282 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1283 either 16 or 32 */
1284
1285 /* For plane A, Cursor A */
1286 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1287 &cursor_prec_mult, &cursora_dl)) {
1288 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1289 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1290 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1291 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1292
1293 I915_WRITE(VLV_DDL1, cursora_prec |
1294 (cursora_dl << DDL_CURSORA_SHIFT) |
1295 planea_prec | planea_dl);
1296 }
1297
1298 /* For plane B, Cursor B */
1299 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1300 &cursor_prec_mult, &cursorb_dl)) {
1301 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1302 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1303 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1304 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1305
1306 I915_WRITE(VLV_DDL2, cursorb_prec |
1307 (cursorb_dl << DDL_CURSORB_SHIFT) |
1308 planeb_prec | planeb_dl);
1309 }
1310}
1311
1312#define single_plane_enabled(mask) is_power_of_2(mask)
1313
46ba614c 1314static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1315{
46ba614c 1316 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1317 static const int sr_latency_ns = 12000;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1320 int plane_sr, cursor_sr;
af6c4575 1321 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1322 unsigned int enabled = 0;
1323
1324 vlv_update_drain_latency(dev);
1325
51cea1f4 1326 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1327 &valleyview_wm_info, latency_ns,
1328 &valleyview_cursor_wm_info, latency_ns,
1329 &planea_wm, &cursora_wm))
51cea1f4 1330 enabled |= 1 << PIPE_A;
b445e3b0 1331
51cea1f4 1332 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1333 &valleyview_wm_info, latency_ns,
1334 &valleyview_cursor_wm_info, latency_ns,
1335 &planeb_wm, &cursorb_wm))
51cea1f4 1336 enabled |= 1 << PIPE_B;
b445e3b0 1337
b445e3b0
ED		 1338 if (single_plane_enabled(enabled) &&
1339 g4x_compute_srwm(dev, ffs(enabled) - 1,
1340 sr_latency_ns,
1341 &valleyview_wm_info,
1342 &valleyview_cursor_wm_info,
af6c4575
CW		 1343 &plane_sr, &ignore_cursor_sr) &&
1344 g4x_compute_srwm(dev, ffs(enabled) - 1,
1345 2*sr_latency_ns,
1346 &valleyview_wm_info,
1347 &valleyview_cursor_wm_info,
52bd02d8 1348 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1349 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1350 } else {
b445e3b0
ED		 1351 I915_WRITE(FW_BLC_SELF_VLV,
1352 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1353 plane_sr = cursor_sr = 0;
1354 }
b445e3b0
ED		 1355
1356 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1357 planea_wm, cursora_wm,
1358 planeb_wm, cursorb_wm,
1359 plane_sr, cursor_sr);
1360
1361 I915_WRITE(DSPFW1,
1362 (plane_sr << DSPFW_SR_SHIFT) |
1363 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1364 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1365 planea_wm);
1366 I915_WRITE(DSPFW2,
8c919b28 1367 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1368 (cursora_wm << DSPFW_CURSORA_SHIFT));
1369 I915_WRITE(DSPFW3,
8c919b28
CW		 1370 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1371 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1372}
1373
46ba614c 1374static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1375{
46ba614c 1376 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1377 static const int sr_latency_ns = 12000;
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1380 int plane_sr, cursor_sr;
1381 unsigned int enabled = 0;
1382
51cea1f4 1383 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1384 &g4x_wm_info, latency_ns,
1385 &g4x_cursor_wm_info, latency_ns,
1386 &planea_wm, &cursora_wm))
51cea1f4 1387 enabled |= 1 << PIPE_A;
b445e3b0 1388
51cea1f4 1389 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1390 &g4x_wm_info, latency_ns,
1391 &g4x_cursor_wm_info, latency_ns,
1392 &planeb_wm, &cursorb_wm))
51cea1f4 1393 enabled |= 1 << PIPE_B;
b445e3b0 1394
b445e3b0
ED		 1395 if (single_plane_enabled(enabled) &&
1396 g4x_compute_srwm(dev, ffs(enabled) - 1,
1397 sr_latency_ns,
1398 &g4x_wm_info,
1399 &g4x_cursor_wm_info,
52bd02d8 1400 &plane_sr, &cursor_sr)) {
b445e3b0 1401 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1402 } else {
b445e3b0
ED		 1403 I915_WRITE(FW_BLC_SELF,
1404 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1405 plane_sr = cursor_sr = 0;
1406 }
b445e3b0
ED		 1407
1408 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1409 planea_wm, cursora_wm,
1410 planeb_wm, cursorb_wm,
1411 plane_sr, cursor_sr);
1412
1413 I915_WRITE(DSPFW1,
1414 (plane_sr << DSPFW_SR_SHIFT) |
1415 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1416 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1417 planea_wm);
1418 I915_WRITE(DSPFW2,
8c919b28 1419 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1420 (cursora_wm << DSPFW_CURSORA_SHIFT));
1421 /* HPLL off in SR has some issues on G4x... disable it */
1422 I915_WRITE(DSPFW3,
8c919b28 1423 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1425}
1426
46ba614c 1427static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1428{
46ba614c 1429 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 struct drm_crtc *crtc;
1432 int srwm = 1;
1433 int cursor_sr = 16;
1434
1435 /* Calc sr entries for one plane configs */
1436 crtc = single_enabled_crtc(dev);
1437 if (crtc) {
1438 /* self-refresh has much higher latency */
1439 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1440 const struct drm_display_mode *adjusted_mode =
1441 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1442 int clock = adjusted_mode->crtc_clock;
fec8cba3 1443 int htotal = adjusted_mode->crtc_htotal;
37327abd 1444 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1445 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1446 unsigned long line_time_us;
1447 int entries;
1448
922044c9 1449 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1450
1451 /* Use ns/us then divide to preserve precision */
1452 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1453 pixel_size * hdisplay;
1454 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1455 srwm = I965_FIFO_SIZE - entries;
1456 if (srwm < 0)
1457 srwm = 1;
1458 srwm &= 0x1ff;
1459 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1460 entries, srwm);
1461
1462 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1463 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1464 entries = DIV_ROUND_UP(entries,
1465 i965_cursor_wm_info.cacheline_size);
1466 cursor_sr = i965_cursor_wm_info.fifo_size -
1467 (entries + i965_cursor_wm_info.guard_size);
1468
1469 if (cursor_sr > i965_cursor_wm_info.max_wm)
1470 cursor_sr = i965_cursor_wm_info.max_wm;
1471
1472 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1473 "cursor %d\n", srwm, cursor_sr);
1474
1475 if (IS_CRESTLINE(dev))
1476 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1477 } else {
1478 /* Turn off self refresh if both pipes are enabled */
1479 if (IS_CRESTLINE(dev))
1480 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1481 & ~FW_BLC_SELF_EN);
1482 }
1483
1484 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1485 srwm);
1486
1487 /* 965 has limitations... */
1488 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1489 (8 << 16) | (8 << 8) | (8 << 0));
1490 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1491 /* update cursor SR watermark */
1492 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1493}
1494
46ba614c 1495static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1496{
46ba614c 1497 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 const struct intel_watermark_params *wm_info;
1500 uint32_t fwater_lo;
1501 uint32_t fwater_hi;
1502 int cwm, srwm = 1;
1503 int fifo_size;
1504 int planea_wm, planeb_wm;
1505 struct drm_crtc *crtc, *enabled = NULL;
1506
1507 if (IS_I945GM(dev))
1508 wm_info = &i945_wm_info;
1509 else if (!IS_GEN2(dev))
1510 wm_info = &i915_wm_info;
1511 else
feb56b93 1512 wm_info = &i830_wm_info;
b445e3b0
ED		 1513
1514 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1515 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1516 if (intel_crtc_active(crtc)) {
241bfc38 1517 const struct drm_display_mode *adjusted_mode;
f4510a27 1518 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1519 if (IS_GEN2(dev))
1520 cpp = 4;
1521
241bfc38
DL		 1522 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1523 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1524 wm_info, fifo_size, cpp,
b445e3b0
ED		 1525 latency_ns);
1526 enabled = crtc;
1527 } else
1528 planea_wm = fifo_size - wm_info->guard_size;
1529
1530 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1531 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1532 if (intel_crtc_active(crtc)) {
241bfc38 1533 const struct drm_display_mode *adjusted_mode;
f4510a27 1534 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1535 if (IS_GEN2(dev))
1536 cpp = 4;
1537
241bfc38
DL		 1538 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1539 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1540 wm_info, fifo_size, cpp,
b445e3b0
ED		 1541 latency_ns);
1542 if (enabled == NULL)
1543 enabled = crtc;
1544 else
1545 enabled = NULL;
1546 } else
1547 planeb_wm = fifo_size - wm_info->guard_size;
1548
1549 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1550
2ab1bc9d
DV		 1551 if (IS_I915GM(dev) && enabled) {
1552 struct intel_framebuffer *fb;
1553
1554 fb = to_intel_framebuffer(enabled->primary->fb);
1555
1556 /* self-refresh seems busted with untiled */
1557 if (fb->obj->tiling_mode == I915_TILING_NONE)
1558 enabled = NULL;
1559 }
1560
b445e3b0
ED		 1561 /*
1562 * Overlay gets an aggressive default since video jitter is bad.
1563 */
1564 cwm = 2;
1565
1566 /* Play safe and disable self-refresh before adjusting watermarks. */
1567 if (IS_I945G(dev) || IS_I945GM(dev))
1568 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1569 else if (IS_I915GM(dev))
3f2dc5ac 1570 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1571
1572 /* Calc sr entries for one plane configs */
1573 if (HAS_FW_BLC(dev) && enabled) {
1574 /* self-refresh has much higher latency */
1575 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1576 const struct drm_display_mode *adjusted_mode =
1577 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1578 int clock = adjusted_mode->crtc_clock;
fec8cba3 1579 int htotal = adjusted_mode->crtc_htotal;
f727b490 1580 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1581 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1582 unsigned long line_time_us;
1583 int entries;
1584
922044c9 1585 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1586
1587 /* Use ns/us then divide to preserve precision */
1588 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1589 pixel_size * hdisplay;
1590 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1591 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1592 srwm = wm_info->fifo_size - entries;
1593 if (srwm < 0)
1594 srwm = 1;
1595
1596 if (IS_I945G(dev) || IS_I945GM(dev))
1597 I915_WRITE(FW_BLC_SELF,
1598 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1599 else if (IS_I915GM(dev))
1600 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1601 }
1602
1603 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1604 planea_wm, planeb_wm, cwm, srwm);
1605
1606 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1607 fwater_hi = (cwm & 0x1f);
1608
1609 /* Set request length to 8 cachelines per fetch */
1610 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1611 fwater_hi = fwater_hi | (1 << 8);
1612
1613 I915_WRITE(FW_BLC, fwater_lo);
1614 I915_WRITE(FW_BLC2, fwater_hi);
1615
1616 if (HAS_FW_BLC(dev)) {
1617 if (enabled) {
1618 if (IS_I945G(dev) || IS_I945GM(dev))
1619 I915_WRITE(FW_BLC_SELF,
1620 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1621 else if (IS_I915GM(dev))
3f2dc5ac 1622 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1623 DRM_DEBUG_KMS("memory self refresh enabled\n");
1624 } else
1625 DRM_DEBUG_KMS("memory self refresh disabled\n");
1626 }
1627}
1628
feb56b93 1629static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1630{
46ba614c 1631 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633 struct drm_crtc *crtc;
241bfc38 1634 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1635 uint32_t fwater_lo;
1636 int planea_wm;
1637
1638 crtc = single_enabled_crtc(dev);
1639 if (crtc == NULL)
1640 return;
1641
241bfc38
DL		 1642 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1643 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1644 &i845_wm_info,
b445e3b0 1645 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1646 4, latency_ns);
b445e3b0
ED		 1647 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1648 fwater_lo |= (3<<8) | planea_wm;
1649
1650 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1651
1652 I915_WRITE(FW_BLC, fwater_lo);
1653}
1654
3658729a
VS		 1655static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1656 struct drm_crtc *crtc)
801bcfff
PZ		 1657{
1658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1659 uint32_t pixel_rate;
801bcfff 1660
241bfc38 1661 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1662
1663 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1664 * adjust the pixel_rate here. */
1665
fd4daa9c 1666 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1667 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1668 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1669
37327abd
VS		 1670 pipe_w = intel_crtc->config.pipe_src_w;
1671 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1672 pfit_w = (pfit_size >> 16) & 0xFFFF;
1673 pfit_h = pfit_size & 0xFFFF;
1674 if (pipe_w < pfit_w)
1675 pipe_w = pfit_w;
1676 if (pipe_h < pfit_h)
1677 pipe_h = pfit_h;
1678
1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680 pfit_w * pfit_h);
1681 }
1682
1683 return pixel_rate;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
23297044 1687static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1688 uint32_t latency)
1689{
1690 uint64_t ret;
1691
3312ba65
VS		 1692 if (WARN(latency == 0, "Latency value missing\n"))
1693 return UINT_MAX;
1694
801bcfff
PZ		 1695 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1696 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1697
1698 return ret;
1699}
1700
37126462 1701/* latency must be in 0.1us units. */
23297044 1702static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1703 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1704 uint32_t latency)
1705{
1706 uint32_t ret;
1707
3312ba65
VS		 1708 if (WARN(latency == 0, "Latency value missing\n"))
1709 return UINT_MAX;
1710
801bcfff
PZ		 1711 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1712 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1713 ret = DIV_ROUND_UP(ret, 64) + 2;
1714 return ret;
1715}
1716
23297044 1717static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1718 uint8_t bytes_per_pixel)
1719{
1720 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1721}
1722
820c1980 1723struct ilk_pipe_wm_parameters {
801bcfff 1724 bool active;
801bcfff
PZ		 1725 uint32_t pipe_htotal;
1726 uint32_t pixel_rate;
c35426d2
VS		 1727 struct intel_plane_wm_parameters pri;
1728 struct intel_plane_wm_parameters spr;
1729 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1730};
1731
820c1980 1732struct ilk_wm_maximums {
cca32e9a
PZ		 1733 uint16_t pri;
1734 uint16_t spr;
1735 uint16_t cur;
1736 uint16_t fbc;
1737};
1738
240264f4
VS		 1739/* used in computing the new watermarks state */
1740struct intel_wm_config {
1741 unsigned int num_pipes_active;
1742 bool sprites_enabled;
1743 bool sprites_scaled;
240264f4
VS		 1744};
1745
37126462
VS		 1746/*
1747 * For both WM_PIPE and WM_LP.
1748 * mem_value must be in 0.1us units.
1749 */
820c1980 1750static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1751 uint32_t mem_value,
1752 bool is_lp)
801bcfff 1753{
cca32e9a
PZ		 1754 uint32_t method1, method2;
1755
c35426d2 1756 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1757 return 0;
1758
23297044 1759 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1760 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1761 mem_value);
1762
1763 if (!is_lp)
1764 return method1;
1765
23297044 1766 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1767 params->pipe_htotal,
c35426d2
VS		 1768 params->pri.horiz_pixels,
1769 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1770 mem_value);
1771
1772 return min(method1, method2);
801bcfff
PZ		 1773}
1774
37126462
VS		 1775/*
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1778 */
820c1980 1779static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1780 uint32_t mem_value)
1781{
1782 uint32_t method1, method2;
1783
c35426d2 1784 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1785 return 0;
1786
23297044 1787 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1788 params->spr.bytes_per_pixel,
801bcfff 1789 mem_value);
23297044 1790 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1791 params->pipe_htotal,
c35426d2
VS		 1792 params->spr.horiz_pixels,
1793 params->spr.bytes_per_pixel,
801bcfff
PZ		 1794 mem_value);
1795 return min(method1, method2);
1796}
1797
37126462
VS		 1798/*
1799 * For both WM_PIPE and WM_LP.
1800 * mem_value must be in 0.1us units.
1801 */
820c1980 1802static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1803 uint32_t mem_value)
1804{
c35426d2 1805 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1806 return 0;
1807
23297044 1808 return ilk_wm_method2(params->pixel_rate,
801bcfff 1809 params->pipe_htotal,
c35426d2
VS		 1810 params->cur.horiz_pixels,
1811 params->cur.bytes_per_pixel,
801bcfff
PZ		 1812 mem_value);
1813}
1814
cca32e9a 1815/* Only for WM_LP. */
820c1980 1816static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1817 uint32_t pri_val)
cca32e9a 1818{
c35426d2 1819 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1820 return 0;
1821
23297044 1822 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1823 params->pri.horiz_pixels,
1824 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1825}
1826
158ae64f
VS		 1827static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1828{
416f4727
VS		 1829 if (INTEL_INFO(dev)->gen >= 8)
1830 return 3072;
1831 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1832 return 768;
1833 else
1834 return 512;
1835}
1836
4e975081
VS		 1837static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1838 int level, bool is_sprite)
1839{
1840 if (INTEL_INFO(dev)->gen >= 8)
1841 /* BDW primary/sprite plane watermarks */
1842 return level == 0 ? 255 : 2047;
1843 else if (INTEL_INFO(dev)->gen >= 7)
1844 /* IVB/HSW primary/sprite plane watermarks */
1845 return level == 0 ? 127 : 1023;
1846 else if (!is_sprite)
1847 /* ILK/SNB primary plane watermarks */
1848 return level == 0 ? 127 : 511;
1849 else
1850 /* ILK/SNB sprite plane watermarks */
1851 return level == 0 ? 63 : 255;
1852}
1853
1854static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1855 int level)
1856{
1857 if (INTEL_INFO(dev)->gen >= 7)
1858 return level == 0 ? 63 : 255;
1859 else
1860 return level == 0 ? 31 : 63;
1861}
1862
1863static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1864{
1865 if (INTEL_INFO(dev)->gen >= 8)
1866 return 31;
1867 else
1868 return 15;
1869}
1870
158ae64f
VS		 1871/* Calculate the maximum primary/sprite plane watermark */
1872static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1873 int level,
240264f4 1874 const struct intel_wm_config *config,
158ae64f
VS		 1875 enum intel_ddb_partitioning ddb_partitioning,
1876 bool is_sprite)
1877{
1878 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1879
1880 /* if sprites aren't enabled, sprites get nothing */
240264f4 1881 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1882 return 0;
1883
1884 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1885 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1886 fifo_size /= INTEL_INFO(dev)->num_pipes;
1887
1888 /*
1889 * For some reason the non self refresh
1890 * FIFO size is only half of the self
1891 * refresh FIFO size on ILK/SNB.
1892 */
1893 if (INTEL_INFO(dev)->gen <= 6)
1894 fifo_size /= 2;
1895 }
1896
240264f4 1897 if (config->sprites_enabled) {
158ae64f
VS		 1898 /* level 0 is always calculated with 1:1 split */
1899 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1900 if (is_sprite)
1901 fifo_size *= 5;
1902 fifo_size /= 6;
1903 } else {
1904 fifo_size /= 2;
1905 }
1906 }
1907
1908 /* clamp to max that the registers can hold */
4e975081 1909 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1910}
1911
1912/* Calculate the maximum cursor plane watermark */
1913static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1914 int level,
1915 const struct intel_wm_config *config)
158ae64f
VS		 1916{
1917 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1918 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1919 return 64;
1920
1921 /* otherwise just report max that registers can hold */
4e975081 1922 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1923}
1924
d34ff9c6 1925static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1926 int level,
1927 const struct intel_wm_config *config,
1928 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1929 struct ilk_wm_maximums *max)
158ae64f 1930{
240264f4
VS		 1931 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1932 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1933 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1934 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1935}
1936
a3cb4048
VS		 1937static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1938 int level,
1939 struct ilk_wm_maximums *max)
1940{
1941 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1942 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1943 max->cur = ilk_cursor_wm_reg_max(dev, level);
1944 max->fbc = ilk_fbc_wm_reg_max(dev);
1945}
1946
d9395655 1947static bool ilk_validate_wm_level(int level,
820c1980 1948 const struct ilk_wm_maximums *max,
d9395655 1949 struct intel_wm_level *result)
a9786a11
VS		 1950{
1951 bool ret;
1952
1953 /* already determined to be invalid? */
1954 if (!result->enable)
1955 return false;
1956
1957 result->enable = result->pri_val <= max->pri &&
1958 result->spr_val <= max->spr &&
1959 result->cur_val <= max->cur;
1960
1961 ret = result->enable;
1962
1963 /*
1964 * HACK until we can pre-compute everything,
1965 * and thus fail gracefully if LP0 watermarks
1966 * are exceeded...
1967 */
1968 if (level == 0 && !result->enable) {
1969 if (result->pri_val > max->pri)
1970 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1971 level, result->pri_val, max->pri);
1972 if (result->spr_val > max->spr)
1973 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1974 level, result->spr_val, max->spr);
1975 if (result->cur_val > max->cur)
1976 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1977 level, result->cur_val, max->cur);
1978
1979 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1980 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1981 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1982 result->enable = true;
1983 }
1984
a9786a11
VS		 1985 return ret;
1986}
1987
d34ff9c6 1988static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1989 int level,
820c1980 1990 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1991 struct intel_wm_level *result)
6f5ddd17
VS		 1992{
1993 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1994 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1995 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1996
1997 /* WM1+ latency values stored in 0.5us units */
1998 if (level > 0) {
1999 pri_latency *= 5;
2000 spr_latency *= 5;
2001 cur_latency *= 5;
2002 }
2003
2004 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2005 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2006 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2007 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2008 result->enable = true;
2009}
2010
801bcfff
PZ		 2011static uint32_t
2012hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2013{
2014 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2016 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2017 u32 linetime, ips_linetime;
1f8eeabf 2018
801bcfff
PZ		 2019 if (!intel_crtc_active(crtc))
2020 return 0;
1011d8c4 2021
1f8eeabf
ED		 2022 /* The WM are computed with base on how long it takes to fill a single
2023 * row at the given clock rate, multiplied by 8.
2024 * */
fec8cba3
JB		 2025 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2026 mode->crtc_clock);
2027 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2028 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2029
801bcfff
PZ		 2030 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2031 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2032}
2033
12b134df
VS		 2034static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2035{
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037
a42a5719 2038 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2039 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2040
2041 wm[0] = (sskpd >> 56) & 0xFF;
2042 if (wm[0] == 0)
2043 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2044 wm[1] = (sskpd >> 4) & 0xFF;
2045 wm[2] = (sskpd >> 12) & 0xFF;
2046 wm[3] = (sskpd >> 20) & 0x1FF;
2047 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2048 } else if (INTEL_INFO(dev)->gen >= 6) {
2049 uint32_t sskpd = I915_READ(MCH_SSKPD);
2050
2051 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2052 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2053 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2054 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2055 } else if (INTEL_INFO(dev)->gen >= 5) {
2056 uint32_t mltr = I915_READ(MLTR_ILK);
2057
2058 /* ILK primary LP0 latency is 700 ns */
2059 wm[0] = 7;
2060 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2061 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2062 }
2063}
2064
53615a5e
VS		 2065static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2066{
2067 /* ILK sprite LP0 latency is 1300 ns */
2068 if (INTEL_INFO(dev)->gen == 5)
2069 wm[0] = 13;
2070}
2071
2072static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2073{
2074 /* ILK cursor LP0 latency is 1300 ns */
2075 if (INTEL_INFO(dev)->gen == 5)
2076 wm[0] = 13;
2077
2078 /* WaDoubleCursorLP3Latency:ivb */
2079 if (IS_IVYBRIDGE(dev))
2080 wm[3] *= 2;
2081}
2082
546c81fd 2083int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2084{
26ec971e 2085 /* how many WM levels are we expecting */
a42a5719 2086 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2087 return 4;
26ec971e 2088 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2089 return 3;
26ec971e 2090 else
ad0d6dc4
VS		 2091 return 2;
2092}
2093
2094static void intel_print_wm_latency(struct drm_device *dev,
2095 const char *name,
2096 const uint16_t wm[5])
2097{
2098 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2099
2100 for (level = 0; level <= max_level; level++) {
2101 unsigned int latency = wm[level];
2102
2103 if (latency == 0) {
2104 DRM_ERROR("%s WM%d latency not provided\n",
2105 name, level);
2106 continue;
2107 }
2108
2109 /* WM1+ latency values in 0.5us units */
2110 if (level > 0)
2111 latency *= 5;
2112
2113 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2114 name, level, wm[level],
2115 latency / 10, latency % 10);
2116 }
2117}
2118
e95a2f75
VS		 2119static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2120 uint16_t wm[5], uint16_t min)
2121{
2122 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2123
2124 if (wm[0] >= min)
2125 return false;
2126
2127 wm[0] = max(wm[0], min);
2128 for (level = 1; level <= max_level; level++)
2129 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2130
2131 return true;
2132}
2133
2134static void snb_wm_latency_quirk(struct drm_device *dev)
2135{
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2137 bool changed;
2138
2139 /*
2140 * The BIOS provided WM memory latency values are often
2141 * inadequate for high resolution displays. Adjust them.
2142 */
2143 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2144 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2145 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2146
2147 if (!changed)
2148 return;
2149
2150 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2151 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2152 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2153 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2154}
2155
fa50ad61 2156static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2157{
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159
2160 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2161
2162 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2163 sizeof(dev_priv->wm.pri_latency));
2164 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2165 sizeof(dev_priv->wm.pri_latency));
2166
2167 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2168 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2169
2170 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2171 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2172 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2173
2174 if (IS_GEN6(dev))
2175 snb_wm_latency_quirk(dev);
53615a5e
VS		 2176}
2177
820c1980 2178static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2179 struct ilk_pipe_wm_parameters *p)
1011d8c4 2180{
7c4a395f
VS		 2181 struct drm_device *dev = crtc->dev;
2182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2184 struct drm_plane *plane;
1011d8c4 2185
2a44b76b
VS		 2186 if (!intel_crtc_active(crtc))
2187 return;
801bcfff 2188
2a44b76b
VS		 2189 p->active = true;
2190 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2191 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2192 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2193 p->cur.bytes_per_pixel = 4;
2194 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2195 p->cur.horiz_pixels = intel_crtc->cursor_width;
2196 /* TODO: for now, assume primary and cursor planes are always enabled. */
2197 p->pri.enabled = true;
2198 p->cur.enabled = true;
7c4a395f 2199
af2b653b 2200 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2201 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2202
2a44b76b 2203 if (intel_plane->pipe == pipe) {
7c4a395f 2204 p->spr = intel_plane->wm;
2a44b76b
VS		 2205 break;
2206 }
2207 }
2208}
2209
2210static void ilk_compute_wm_config(struct drm_device *dev,
2211 struct intel_wm_config *config)
2212{
2213 struct intel_crtc *intel_crtc;
2214
2215 /* Compute the currently _active_ config */
d3fcc808 2216 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2217 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2218
2a44b76b
VS		 2219 if (!wm->pipe_enabled)
2220 continue;
cca32e9a 2221
2a44b76b
VS		 2222 config->sprites_enabled |= wm->sprites_enabled;
2223 config->sprites_scaled |= wm->sprites_scaled;
2224 config->num_pipes_active++;
cca32e9a 2225 }
801bcfff
PZ		 2226}
2227
0b2ae6d7
VS		 2228/* Compute new watermarks for the pipe */
2229static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2230 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2231 struct intel_pipe_wm *pipe_wm)
2232{
2233 struct drm_device *dev = crtc->dev;
d34ff9c6 2234 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2235 int level, max_level = ilk_wm_max_level(dev);
2236 /* LP0 watermark maximums depend on this pipe alone */
2237 struct intel_wm_config config = {
2238 .num_pipes_active = 1,
2239 .sprites_enabled = params->spr.enabled,
2240 .sprites_scaled = params->spr.scaled,
2241 };
820c1980 2242 struct ilk_wm_maximums max;
0b2ae6d7 2243
2a44b76b
VS		 2244 pipe_wm->pipe_enabled = params->active;
2245 pipe_wm->sprites_enabled = params->spr.enabled;
2246 pipe_wm->sprites_scaled = params->spr.scaled;
2247
7b39a0b7
VS		 2248 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2249 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2250 max_level = 1;
2251
2252 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2253 if (params->spr.scaled)
2254 max_level = 0;
2255
a3cb4048 2256 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2257
a42a5719 2258 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2259 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2260
a3cb4048
VS		 2261 /* LP0 watermarks always use 1/2 DDB partitioning */
2262 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2263
0b2ae6d7 2264 /* At least LP0 must be valid */
a3cb4048
VS		 2265 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2266 return false;
2267
2268 ilk_compute_wm_reg_maximums(dev, 1, &max);
2269
2270 for (level = 1; level <= max_level; level++) {
2271 struct intel_wm_level wm = {};
2272
2273 ilk_compute_wm_level(dev_priv, level, params, &wm);
2274
2275 /*
2276 * Disable any watermark level that exceeds the
2277 * register maximums since such watermarks are
2278 * always invalid.
2279 */
2280 if (!ilk_validate_wm_level(level, &max, &wm))
2281 break;
2282
2283 pipe_wm->wm[level] = wm;
2284 }
2285
2286 return true;
0b2ae6d7
VS		 2287}
2288
2289/*
2290 * Merge the watermarks from all active pipes for a specific level.
2291 */
2292static void ilk_merge_wm_level(struct drm_device *dev,
2293 int level,
2294 struct intel_wm_level *ret_wm)
2295{
2296 const struct intel_crtc *intel_crtc;
2297
d52fea5b
VS		 2298 ret_wm->enable = true;
2299
d3fcc808 2300 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2301 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2302 const struct intel_wm_level *wm = &active->wm[level];
2303
2304 if (!active->pipe_enabled)
2305 continue;
0b2ae6d7 2306
d52fea5b
VS		 2307 /*
2308 * The watermark values may have been used in the past,
2309 * so we must maintain them in the registers for some
2310 * time even if the level is now disabled.
2311 */
0b2ae6d7 2312 if (!wm->enable)
d52fea5b 2313 ret_wm->enable = false;
0b2ae6d7
VS		 2314
2315 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2316 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2317 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2318 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2319 }
0b2ae6d7
VS		 2320}
2321
2322/*
2323 * Merge all low power watermarks for all active pipes.
2324 */
2325static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2326 const struct intel_wm_config *config,
820c1980 2327 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2328 struct intel_pipe_wm *merged)
2329{
2330 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2331 int last_enabled_level = max_level;
0b2ae6d7 2332
0ba22e26
VS		 2333 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2334 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2335 config->num_pipes_active > 1)
2336 return;
2337
6c8b6c28
VS		 2338 /* ILK: FBC WM must be disabled always */
2339 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2340
2341 /* merge each WM1+ level */
2342 for (level = 1; level <= max_level; level++) {
2343 struct intel_wm_level *wm = &merged->wm[level];
2344
2345 ilk_merge_wm_level(dev, level, wm);
2346
d52fea5b
VS		 2347 if (level > last_enabled_level)
2348 wm->enable = false;
2349 else if (!ilk_validate_wm_level(level, max, wm))
2350 /* make sure all following levels get disabled */
2351 last_enabled_level = level - 1;
0b2ae6d7
VS		 2352
2353 /*
2354 * The spec says it is preferred to disable
2355 * FBC WMs instead of disabling a WM level.
2356 */
2357 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2358 if (wm->enable)
2359 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2360 wm->fbc_val = 0;
2361 }
2362 }
6c8b6c28
VS		 2363
2364 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2365 /*
2366 * FIXME this is racy. FBC might get enabled later.
2367 * What we should check here is whether FBC can be
2368 * enabled sometime later.
2369 */
2370 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2371 for (level = 2; level <= max_level; level++) {
2372 struct intel_wm_level *wm = &merged->wm[level];
2373
2374 wm->enable = false;
2375 }
2376 }
0b2ae6d7
VS		 2377}
2378
b380ca3c
VS		 2379static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2380{
2381 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2382 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2383}
2384
a68d68ee
VS		 2385/* The value we need to program into the WM_LPx latency field */
2386static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2387{
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389
a42a5719 2390 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2391 return 2 * level;
2392 else
2393 return dev_priv->wm.pri_latency[level];
2394}
2395
820c1980 2396static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2397 const struct intel_pipe_wm *merged,
609cedef 2398 enum intel_ddb_partitioning partitioning,
820c1980 2399 struct ilk_wm_values *results)
801bcfff 2400{
0b2ae6d7
VS		 2401 struct intel_crtc *intel_crtc;
2402 int level, wm_lp;
cca32e9a 2403
0362c781 2404 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2405 results->partitioning = partitioning;
cca32e9a 2406
0b2ae6d7 2407 /* LP1+ register values */
cca32e9a 2408 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2409 const struct intel_wm_level *r;
801bcfff 2410
b380ca3c 2411 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2412
0362c781 2413 r = &merged->wm[level];
cca32e9a 2414
d52fea5b
VS		 2415 /*
2416 * Maintain the watermark values even if the level is
2417 * disabled. Doing otherwise could cause underruns.
2418 */
2419 results->wm_lp[wm_lp - 1] =
a68d68ee 2420 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2421 (r->pri_val << WM1_LP_SR_SHIFT) |
2422 r->cur_val;
2423
d52fea5b
VS		 2424 if (r->enable)
2425 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2426
416f4727
VS		 2427 if (INTEL_INFO(dev)->gen >= 8)
2428 results->wm_lp[wm_lp - 1] |=
2429 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2430 else
2431 results->wm_lp[wm_lp - 1] |=
2432 r->fbc_val << WM1_LP_FBC_SHIFT;
2433
d52fea5b
VS		 2434 /*
2435 * Always set WM1S_LP_EN when spr_val != 0, even if the
2436 * level is disabled. Doing otherwise could cause underruns.
2437 */
6cef2b8a
VS		 2438 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2439 WARN_ON(wm_lp != 1);
2440 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2441 } else
2442 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2443 }
801bcfff 2444
0b2ae6d7 2445 /* LP0 register values */
d3fcc808 2446 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2447 enum pipe pipe = intel_crtc->pipe;
2448 const struct intel_wm_level *r =
2449 &intel_crtc->wm.active.wm[0];
2450
2451 if (WARN_ON(!r->enable))
2452 continue;
2453
2454 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2455
0b2ae6d7
VS		 2456 results->wm_pipe[pipe] =
2457 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2458 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2459 r->cur_val;
801bcfff
PZ		 2460 }
2461}
2462
861f3389
PZ		 2463/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2464 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2465static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2466 struct intel_pipe_wm *r1,
2467 struct intel_pipe_wm *r2)
861f3389 2468{
198a1e9b
VS		 2469 int level, max_level = ilk_wm_max_level(dev);
2470 int level1 = 0, level2 = 0;
861f3389 2471
198a1e9b
VS		 2472 for (level = 1; level <= max_level; level++) {
2473 if (r1->wm[level].enable)
2474 level1 = level;
2475 if (r2->wm[level].enable)
2476 level2 = level;
861f3389
PZ		 2477 }
2478
198a1e9b
VS		 2479 if (level1 == level2) {
2480 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2481 return r2;
2482 else
2483 return r1;
198a1e9b 2484 } else if (level1 > level2) {
861f3389
PZ		 2485 return r1;
2486 } else {
2487 return r2;
2488 }
2489}
2490
49a687c4
VS		 2491/* dirty bits used to track which watermarks need changes */
2492#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2493#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2494#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2495#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2496#define WM_DIRTY_FBC (1 << 24)
2497#define WM_DIRTY_DDB (1 << 25)
2498
2499static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2500 const struct ilk_wm_values *old,
2501 const struct ilk_wm_values *new)
49a687c4
VS		 2502{
2503 unsigned int dirty = 0;
2504 enum pipe pipe;
2505 int wm_lp;
2506
2507 for_each_pipe(pipe) {
2508 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2509 dirty |= WM_DIRTY_LINETIME(pipe);
2510 /* Must disable LP1+ watermarks too */
2511 dirty |= WM_DIRTY_LP_ALL;
2512 }
2513
2514 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2515 dirty |= WM_DIRTY_PIPE(pipe);
2516 /* Must disable LP1+ watermarks too */
2517 dirty |= WM_DIRTY_LP_ALL;
2518 }
2519 }
2520
2521 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2522 dirty |= WM_DIRTY_FBC;
2523 /* Must disable LP1+ watermarks too */
2524 dirty |= WM_DIRTY_LP_ALL;
2525 }
2526
2527 if (old->partitioning != new->partitioning) {
2528 dirty |= WM_DIRTY_DDB;
2529 /* Must disable LP1+ watermarks too */
2530 dirty |= WM_DIRTY_LP_ALL;
2531 }
2532
2533 /* LP1+ watermarks already deemed dirty, no need to continue */
2534 if (dirty & WM_DIRTY_LP_ALL)
2535 return dirty;
2536
2537 /* Find the lowest numbered LP1+ watermark in need of an update... */
2538 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2539 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2540 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2541 break;
2542 }
2543
2544 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2545 for (; wm_lp <= 3; wm_lp++)
2546 dirty |= WM_DIRTY_LP(wm_lp);
2547
2548 return dirty;
2549}
2550
8553c18e
VS		 2551static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2552 unsigned int dirty)
801bcfff 2553{
820c1980 2554 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2555 bool changed = false;
801bcfff 2556
facd619b
VS		 2557 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2558 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2559 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2560 changed = true;
facd619b
VS		 2561 }
2562 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2563 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2564 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2565 changed = true;
facd619b
VS		 2566 }
2567 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2568 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2569 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2570 changed = true;
facd619b 2571 }
801bcfff 2572
facd619b
VS		 2573 /*
2574 * Don't touch WM1S_LP_EN here.
2575 * Doing so could cause underruns.
2576 */
6cef2b8a 2577
8553c18e
VS		 2578 return changed;
2579}
2580
2581/*
2582 * The spec says we shouldn't write when we don't need, because every write
2583 * causes WMs to be re-evaluated, expending some power.
2584 */
820c1980
ID		 2585static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2586 struct ilk_wm_values *results)
8553c18e
VS		 2587{
2588 struct drm_device *dev = dev_priv->dev;
820c1980 2589 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2590 unsigned int dirty;
2591 uint32_t val;
2592
2593 dirty = ilk_compute_wm_dirty(dev, previous, results);
2594 if (!dirty)
2595 return;
2596
2597 _ilk_disable_lp_wm(dev_priv, dirty);
2598
49a687c4 2599 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2600 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2601 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2602 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2603 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2604 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2605
49a687c4 2606 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2607 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2608 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2609 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2610 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2611 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2612
49a687c4 2613 if (dirty & WM_DIRTY_DDB) {
a42a5719 2614 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2615 val = I915_READ(WM_MISC);
2616 if (results->partitioning == INTEL_DDB_PART_1_2)
2617 val &= ~WM_MISC_DATA_PARTITION_5_6;
2618 else
2619 val |= WM_MISC_DATA_PARTITION_5_6;
2620 I915_WRITE(WM_MISC, val);
2621 } else {
2622 val = I915_READ(DISP_ARB_CTL2);
2623 if (results->partitioning == INTEL_DDB_PART_1_2)
2624 val &= ~DISP_DATA_PARTITION_5_6;
2625 else
2626 val |= DISP_DATA_PARTITION_5_6;
2627 I915_WRITE(DISP_ARB_CTL2, val);
2628 }
1011d8c4
PZ		 2629 }
2630
49a687c4 2631 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2632 val = I915_READ(DISP_ARB_CTL);
2633 if (results->enable_fbc_wm)
2634 val &= ~DISP_FBC_WM_DIS;
2635 else
2636 val |= DISP_FBC_WM_DIS;
2637 I915_WRITE(DISP_ARB_CTL, val);
2638 }
2639
954911eb
ID		 2640 if (dirty & WM_DIRTY_LP(1) &&
2641 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2642 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2643
2644 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2645 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2646 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2647 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2648 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2649 }
801bcfff 2650
facd619b 2651 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2652 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2653 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2654 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2655 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2656 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2657
2658 dev_priv->wm.hw = *results;
801bcfff
PZ		 2659}
2660
8553c18e
VS		 2661static bool ilk_disable_lp_wm(struct drm_device *dev)
2662{
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664
2665 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2666}
2667
820c1980 2668static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2669{
7c4a395f 2670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2671 struct drm_device *dev = crtc->dev;
801bcfff 2672 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2673 struct ilk_wm_maximums max;
2674 struct ilk_pipe_wm_parameters params = {};
2675 struct ilk_wm_values results = {};
77c122bc 2676 enum intel_ddb_partitioning partitioning;
7c4a395f 2677 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2678 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2679 struct intel_wm_config config = {};
7c4a395f 2680
2a44b76b 2681 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2682
2683 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2684
2685 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2686 return;
861f3389 2687
7c4a395f 2688 intel_crtc->wm.active = pipe_wm;
861f3389 2689
2a44b76b
VS		 2690 ilk_compute_wm_config(dev, &config);
2691
34982fe1 2692 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2693 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2694
2695 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2696 if (INTEL_INFO(dev)->gen >= 7 &&
2697 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2698 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2699 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2700
820c1980 2701 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2702 } else {
198a1e9b 2703 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2704 }
2705
198a1e9b 2706 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2707 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2708
820c1980 2709 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2710
820c1980 2711 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2712}
2713
820c1980 2714static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2715 struct drm_crtc *crtc,
526682e9 2716 uint32_t sprite_width, int pixel_size,
bdd57d03 2717 bool enabled, bool scaled)
526682e9 2718{
8553c18e 2719 struct drm_device *dev = plane->dev;
adf3d35e 2720 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2721
adf3d35e
VS		 2722 intel_plane->wm.enabled = enabled;
2723 intel_plane->wm.scaled = scaled;
2724 intel_plane->wm.horiz_pixels = sprite_width;
2725 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2726
8553c18e
VS		 2727 /*
2728 * IVB workaround: must disable low power watermarks for at least
2729 * one frame before enabling scaling. LP watermarks can be re-enabled
2730 * when scaling is disabled.
2731 *
2732 * WaCxSRDisabledForSpriteScaling:ivb
2733 */
2734 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2735 intel_wait_for_vblank(dev, intel_plane->pipe);
2736
820c1980 2737 ilk_update_wm(crtc);
526682e9
PZ		 2738}
2739
243e6a44
VS		 2740static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2741{
2742 struct drm_device *dev = crtc->dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2744 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2746 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2747 enum pipe pipe = intel_crtc->pipe;
2748 static const unsigned int wm0_pipe_reg[] = {
2749 [PIPE_A] = WM0_PIPEA_ILK,
2750 [PIPE_B] = WM0_PIPEB_ILK,
2751 [PIPE_C] = WM0_PIPEC_IVB,
2752 };
2753
2754 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2755 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2756 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2757
2a44b76b
VS		 2758 active->pipe_enabled = intel_crtc_active(crtc);
2759
2760 if (active->pipe_enabled) {
243e6a44
VS		 2761 u32 tmp = hw->wm_pipe[pipe];
2762
2763 /*
2764 * For active pipes LP0 watermark is marked as
2765 * enabled, and LP1+ watermaks as disabled since
2766 * we can't really reverse compute them in case
2767 * multiple pipes are active.
2768 */
2769 active->wm[0].enable = true;
2770 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2771 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2772 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2773 active->linetime = hw->wm_linetime[pipe];
2774 } else {
2775 int level, max_level = ilk_wm_max_level(dev);
2776
2777 /*
2778 * For inactive pipes, all watermark levels
2779 * should be marked as enabled but zeroed,
2780 * which is what we'd compute them to.
2781 */
2782 for (level = 0; level <= max_level; level++)
2783 active->wm[level].enable = true;
2784 }
2785}
2786
2787void ilk_wm_get_hw_state(struct drm_device *dev)
2788{
2789 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2790 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2791 struct drm_crtc *crtc;
2792
70e1e0ec 2793 for_each_crtc(dev, crtc)
243e6a44
VS		 2794 ilk_pipe_wm_get_hw_state(crtc);
2795
2796 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2797 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2798 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2799
2800 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2801 if (INTEL_INFO(dev)->gen >= 7) {
2802 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2803 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2804 }
243e6a44 2805
a42a5719 2806 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2807 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2808 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2809 else if (IS_IVYBRIDGE(dev))
2810 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2811 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2812
2813 hw->enable_fbc_wm =
2814 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2815}
2816
b445e3b0
ED		 2817/**
2818 * intel_update_watermarks - update FIFO watermark values based on current modes
2819 *
2820 * Calculate watermark values for the various WM regs based on current mode
2821 * and plane configuration.
2822 *
2823 * There are several cases to deal with here:
2824 * - normal (i.e. non-self-refresh)
2825 * - self-refresh (SR) mode
2826 * - lines are large relative to FIFO size (buffer can hold up to 2)
2827 * - lines are small relative to FIFO size (buffer can hold more than 2
2828 * lines), so need to account for TLB latency
2829 *
2830 * The normal calculation is:
2831 * watermark = dotclock * bytes per pixel * latency
2832 * where latency is platform & configuration dependent (we assume pessimal
2833 * values here).
2834 *
2835 * The SR calculation is:
2836 * watermark = (trunc(latency/line time)+1) * surface width *
2837 * bytes per pixel
2838 * where
2839 * line time = htotal / dotclock
2840 * surface width = hdisplay for normal plane and 64 for cursor
2841 * and latency is assumed to be high, as above.
2842 *
2843 * The final value programmed to the register should always be rounded up,
2844 * and include an extra 2 entries to account for clock crossings.
2845 *
2846 * We don't use the sprite, so we can ignore that. And on Crestline we have
2847 * to set the non-SR watermarks to 8.
2848 */
46ba614c 2849void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2850{
46ba614c 2851 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2852
2853 if (dev_priv->display.update_wm)
46ba614c 2854 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2855}
2856
adf3d35e
VS		 2857void intel_update_sprite_watermarks(struct drm_plane *plane,
2858 struct drm_crtc *crtc,
4c4ff43a 2859 uint32_t sprite_width, int pixel_size,
39db4a4d 2860 bool enabled, bool scaled)
b445e3b0 2861{
adf3d35e 2862 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2863
2864 if (dev_priv->display.update_sprite_wm)
adf3d35e 2865 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2866 pixel_size, enabled, scaled);
b445e3b0
ED		 2867}
2868
2b4e57bd
ED		 2869static struct drm_i915_gem_object *
2870intel_alloc_context_page(struct drm_device *dev)
2871{
2872 struct drm_i915_gem_object *ctx;
2873 int ret;
2874
2875 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2876
2877 ctx = i915_gem_alloc_object(dev, 4096);
2878 if (!ctx) {
2879 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2880 return NULL;
2881 }
2882
c69766f2 2883 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2884 if (ret) {
2885 DRM_ERROR("failed to pin power context: %d\n", ret);
2886 goto err_unref;
2887 }
2888
2889 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2890 if (ret) {
2891 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2892 goto err_unpin;
2893 }
2894
2895 return ctx;
2896
2897err_unpin:
d7f46fc4 2898 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2899err_unref:
2900 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2901 return NULL;
2902}
2903
9270388e
DV		 2904/**
2905 * Lock protecting IPS related data structures
9270388e
DV		 2906 */
2907DEFINE_SPINLOCK(mchdev_lock);
2908
2909/* Global for IPS driver to get at the current i915 device. Protected by
2910 * mchdev_lock. */
2911static struct drm_i915_private *i915_mch_dev;
2912
2b4e57bd
ED		 2913bool ironlake_set_drps(struct drm_device *dev, u8 val)
2914{
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 u16 rgvswctl;
2917
9270388e
DV		 2918 assert_spin_locked(&mchdev_lock);
2919
2b4e57bd
ED		 2920 rgvswctl = I915_READ16(MEMSWCTL);
2921 if (rgvswctl & MEMCTL_CMD_STS) {
2922 DRM_DEBUG("gpu busy, RCS change rejected\n");
2923 return false; /* still busy with another command */
2924 }
2925
2926 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2927 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2928 I915_WRITE16(MEMSWCTL, rgvswctl);
2929 POSTING_READ16(MEMSWCTL);
2930
2931 rgvswctl |= MEMCTL_CMD_STS;
2932 I915_WRITE16(MEMSWCTL, rgvswctl);
2933
2934 return true;
2935}
2936
8090c6b9 2937static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2938{
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 u32 rgvmodectl = I915_READ(MEMMODECTL);
2941 u8 fmax, fmin, fstart, vstart;
2942
9270388e
DV		 2943 spin_lock_irq(&mchdev_lock);
2944
2b4e57bd
ED		 2945 /* Enable temp reporting */
2946 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2947 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2948
2949 /* 100ms RC evaluation intervals */
2950 I915_WRITE(RCUPEI, 100000);
2951 I915_WRITE(RCDNEI, 100000);
2952
2953 /* Set max/min thresholds to 90ms and 80ms respectively */
2954 I915_WRITE(RCBMAXAVG, 90000);
2955 I915_WRITE(RCBMINAVG, 80000);
2956
2957 I915_WRITE(MEMIHYST, 1);
2958
2959 /* Set up min, max, and cur for interrupt handling */
2960 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2961 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2962 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2963 MEMMODE_FSTART_SHIFT;
2964
2965 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2966 PXVFREQ_PX_SHIFT;
2967
20e4d407
DV		 2968 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2969 dev_priv->ips.fstart = fstart;
2b4e57bd 2970
20e4d407
DV		 2971 dev_priv->ips.max_delay = fstart;
2972 dev_priv->ips.min_delay = fmin;
2973 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2974
2975 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2976 fmax, fmin, fstart);
2977
2978 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2979
2980 /*
2981 * Interrupts will be enabled in ironlake_irq_postinstall
2982 */
2983
2984 I915_WRITE(VIDSTART, vstart);
2985 POSTING_READ(VIDSTART);
2986
2987 rgvmodectl |= MEMMODE_SWMODE_EN;
2988 I915_WRITE(MEMMODECTL, rgvmodectl);
2989
9270388e 2990 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2991 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2992 mdelay(1);
2b4e57bd
ED		 2993
2994 ironlake_set_drps(dev, fstart);
2995
20e4d407 2996 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2997 I915_READ(0x112e0);
20e4d407
DV		 2998 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2999 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3000 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3001
3002 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3003}
3004
8090c6b9 3005static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3006{
3007 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3008 u16 rgvswctl;
3009
3010 spin_lock_irq(&mchdev_lock);
3011
3012 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3013
3014 /* Ack interrupts, disable EFC interrupt */
3015 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3016 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3017 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3018 I915_WRITE(DEIIR, DE_PCU_EVENT);
3019 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3020
3021 /* Go back to the starting frequency */
20e4d407 3022 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3023 mdelay(1);
2b4e57bd
ED		 3024 rgvswctl |= MEMCTL_CMD_STS;
3025 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3026 mdelay(1);
2b4e57bd 3027
9270388e 3028 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3029}
3030
acbe9475
DV		 3031/* There's a funny hw issue where the hw returns all 0 when reading from
3032 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3033 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3034 * all limits and the gpu stuck at whatever frequency it is at atm).
3035 */
6917c7b9 3036static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3037{
7b9e0ae6 3038 u32 limits;
2b4e57bd 3039
20b46e59
DV		 3040 /* Only set the down limit when we've reached the lowest level to avoid
3041 * getting more interrupts, otherwise leave this clear. This prevents a
3042 * race in the hw when coming out of rc6: There's a tiny window where
3043 * the hw runs at the minimal clock before selecting the desired
3044 * frequency, if the down threshold expires in that window we will not
3045 * receive a down interrupt. */
b39fb297
BW		 3046 limits = dev_priv->rps.max_freq_softlimit << 24;
3047 if (val <= dev_priv->rps.min_freq_softlimit)
3048 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3049
3050 return limits;
3051}
3052
dd75fdc8
CW		 3053static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3054{
3055 int new_power;
3056
3057 new_power = dev_priv->rps.power;
3058 switch (dev_priv->rps.power) {
3059 case LOW_POWER:
b39fb297 3060 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3061 new_power = BETWEEN;
3062 break;
3063
3064 case BETWEEN:
b39fb297 3065 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3066 new_power = LOW_POWER;
b39fb297 3067 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3068 new_power = HIGH_POWER;
3069 break;
3070
3071 case HIGH_POWER:
b39fb297 3072 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3073 new_power = BETWEEN;
3074 break;
3075 }
3076 /* Max/min bins are special */
b39fb297 3077 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3078 new_power = LOW_POWER;
b39fb297 3079 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3080 new_power = HIGH_POWER;
3081 if (new_power == dev_priv->rps.power)
3082 return;
3083
3084 /* Note the units here are not exactly 1us, but 1280ns. */
3085 switch (new_power) {
3086 case LOW_POWER:
3087 /* Upclock if more than 95% busy over 16ms */
3088 I915_WRITE(GEN6_RP_UP_EI, 12500);
3089 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3090
3091 /* Downclock if less than 85% busy over 32ms */
3092 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3093 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3094
3095 I915_WRITE(GEN6_RP_CONTROL,
3096 GEN6_RP_MEDIA_TURBO |
3097 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3098 GEN6_RP_MEDIA_IS_GFX |
3099 GEN6_RP_ENABLE |
3100 GEN6_RP_UP_BUSY_AVG |
3101 GEN6_RP_DOWN_IDLE_AVG);
3102 break;
3103
3104 case BETWEEN:
3105 /* Upclock if more than 90% busy over 13ms */
3106 I915_WRITE(GEN6_RP_UP_EI, 10250);
3107 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3108
3109 /* Downclock if less than 75% busy over 32ms */
3110 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3111 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3112
3113 I915_WRITE(GEN6_RP_CONTROL,
3114 GEN6_RP_MEDIA_TURBO |
3115 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3116 GEN6_RP_MEDIA_IS_GFX |
3117 GEN6_RP_ENABLE |
3118 GEN6_RP_UP_BUSY_AVG |
3119 GEN6_RP_DOWN_IDLE_AVG);
3120 break;
3121
3122 case HIGH_POWER:
3123 /* Upclock if more than 85% busy over 10ms */
3124 I915_WRITE(GEN6_RP_UP_EI, 8000);
3125 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3126
3127 /* Downclock if less than 60% busy over 32ms */
3128 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3129 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3130
3131 I915_WRITE(GEN6_RP_CONTROL,
3132 GEN6_RP_MEDIA_TURBO |
3133 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3134 GEN6_RP_MEDIA_IS_GFX |
3135 GEN6_RP_ENABLE |
3136 GEN6_RP_UP_BUSY_AVG |
3137 GEN6_RP_DOWN_IDLE_AVG);
3138 break;
3139 }
3140
3141 dev_priv->rps.power = new_power;
3142 dev_priv->rps.last_adj = 0;
3143}
3144
2876ce73
CW		 3145static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3146{
3147 u32 mask = 0;
3148
3149 if (val > dev_priv->rps.min_freq_softlimit)
3150 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3151 if (val < dev_priv->rps.max_freq_softlimit)
3152 mask |= GEN6_PM_RP_UP_THRESHOLD;
3153
3154 /* IVB and SNB hard hangs on looping batchbuffer
3155 * if GEN6_PM_UP_EI_EXPIRED is masked.
3156 */
3157 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3158 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3159
baccd458
D		 3160 if (IS_GEN8(dev_priv->dev))
3161 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3162
2876ce73
CW		 3163 return ~mask;
3164}
3165
b8a5ff8d
JM		 3166/* gen6_set_rps is called to update the frequency request, but should also be
3167 * called when the range (min_delay and max_delay) is modified so that we can
3168 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3169void gen6_set_rps(struct drm_device *dev, u8 val)
3170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3172
4fc688ce 3173 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3174 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3175 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3176
eb64cad1
CW		 3177 /* min/max delay may still have been modified so be sure to
3178 * write the limits value.
3179 */
3180 if (val != dev_priv->rps.cur_freq) {
3181 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3182
50e6a2a7 3183 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3184 I915_WRITE(GEN6_RPNSWREQ,
3185 HSW_FREQUENCY(val));
3186 else
3187 I915_WRITE(GEN6_RPNSWREQ,
3188 GEN6_FREQUENCY(val) |
3189 GEN6_OFFSET(0) |
3190 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3191 }
7b9e0ae6 3192
7b9e0ae6
CW		 3193 /* Make sure we continue to get interrupts
3194 * until we hit the minimum or maximum frequencies.
3195 */
eb64cad1 3196 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3197 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3198
d5570a72
BW		 3199 POSTING_READ(GEN6_RPNSWREQ);
3200
b39fb297 3201 dev_priv->rps.cur_freq = val;
be2cde9a 3202 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3203}
3204
76c3552f
D		 3205/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3206 *
3207 * * If Gfx is Idle, then
3208 * 1. Mask Turbo interrupts
3209 * 2. Bring up Gfx clock
3210 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3211 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3212 * 5. Unmask Turbo interrupts
3213*/
3214static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3215{
3216 /*
3217 * When we are idle. Drop to min voltage state.
3218 */
3219
b39fb297 3220 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3221 return;
3222
3223 /* Mask turbo interrupt so that they will not come in between */
3224 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3225
650ad970 3226 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3227
b39fb297 3228 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3229
3230 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3231 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3232
3233 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3234 & GENFREQSTATUS) == 0, 5))
3235 DRM_ERROR("timed out waiting for Punit\n");
3236
650ad970 3237 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3238
2876ce73
CW		 3239 I915_WRITE(GEN6_PMINTRMSK,
3240 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3241}
3242
b29c19b6
CW		 3243void gen6_rps_idle(struct drm_i915_private *dev_priv)
3244{
691bb717
DL		 3245 struct drm_device *dev = dev_priv->dev;
3246
b29c19b6 3247 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3248 if (dev_priv->rps.enabled) {
691bb717 3249 if (IS_VALLEYVIEW(dev))
76c3552f 3250 vlv_set_rps_idle(dev_priv);
c0951f0c 3251 else
b39fb297 3252 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3253 dev_priv->rps.last_adj = 0;
3254 }
b29c19b6
CW		 3255 mutex_unlock(&dev_priv->rps.hw_lock);
3256}
3257
3258void gen6_rps_boost(struct drm_i915_private *dev_priv)
3259{
691bb717
DL		 3260 struct drm_device *dev = dev_priv->dev;
3261
b29c19b6 3262 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3263 if (dev_priv->rps.enabled) {
691bb717 3264 if (IS_VALLEYVIEW(dev))
b39fb297 3265 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3266 else
b39fb297 3267 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3268 dev_priv->rps.last_adj = 0;
3269 }
b29c19b6
CW		 3270 mutex_unlock(&dev_priv->rps.hw_lock);
3271}
3272
0a073b84
JB		 3273void valleyview_set_rps(struct drm_device *dev, u8 val)
3274{
3275 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3276
0a073b84 3277 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3278 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3279 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3280
73008b98 3281 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3282 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3283 dev_priv->rps.cur_freq,
2ec3815f 3284 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3285
2876ce73
CW		 3286 if (val != dev_priv->rps.cur_freq)
3287 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3288
09c87db8 3289 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3290
b39fb297 3291 dev_priv->rps.cur_freq = val;
2ec3815f 3292 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3293}
3294
0961021a
BW		 3295static void gen8_disable_rps_interrupts(struct drm_device *dev)
3296{
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298
992f191f 3299 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3300 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3301 ~dev_priv->pm_rps_events);
3302 /* Complete PM interrupt masking here doesn't race with the rps work
3303 * item again unmasking PM interrupts because that is using a different
3304 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3305 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3306 * gen8_enable_rps will clean up. */
3307
3308 spin_lock_irq(&dev_priv->irq_lock);
3309 dev_priv->rps.pm_iir = 0;
3310 spin_unlock_irq(&dev_priv->irq_lock);
3311
3312 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3313}
3314
44fc7d5c 3315static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3316{
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318
2b4e57bd 3319 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3320 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3321 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3322 /* Complete PM interrupt masking here doesn't race with the rps work
3323 * item again unmasking PM interrupts because that is using a different
3324 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3325 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3326
59cdb63d 3327 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3328 dev_priv->rps.pm_iir = 0;
59cdb63d 3329 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3330
a6706b45 3331 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3332}
3333
44fc7d5c 3334static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3335{
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337
3338 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3339 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3340
0961021a
BW		 3341 if (IS_BROADWELL(dev))
3342 gen8_disable_rps_interrupts(dev);
3343 else
3344 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3345}
3346
38807746
D		 3347static void cherryview_disable_rps(struct drm_device *dev)
3348{
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350
3351 I915_WRITE(GEN6_RC_CONTROL, 0);
3352}
3353
44fc7d5c
DV		 3354static void valleyview_disable_rps(struct drm_device *dev)
3355{
3356 struct drm_i915_private *dev_priv = dev->dev_private;
3357
3358 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3359
44fc7d5c 3360 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3361}
3362
dc39fff7
BW		 3363static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3364{
91ca689a
ID		 3365 if (IS_VALLEYVIEW(dev)) {
3366 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3367 mode = GEN6_RC_CTL_RC6_ENABLE;
3368 else
3369 mode = 0;
3370 }
dc39fff7 3371 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3372 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3373 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3374 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3375}
3376
e6069ca8 3377static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3378{
eb4926e4
DL		 3379 /* No RC6 before Ironlake */
3380 if (INTEL_INFO(dev)->gen < 5)
3381 return 0;
3382
e6069ca8
ID		 3383 /* RC6 is only on Ironlake mobile not on desktop */
3384 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3385 return 0;
3386
456470eb 3387 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3388 if (enable_rc6 >= 0) {
3389 int mask;
3390
3391 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3392 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3393 INTEL_RC6pp_ENABLE;
3394 else
3395 mask = INTEL_RC6_ENABLE;
3396
3397 if ((enable_rc6 & mask) != enable_rc6)
3398 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
8fd9c1a9 3399 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3400
3401 return enable_rc6 & mask;
3402 }
2b4e57bd 3403
6567d748
CW		 3404 /* Disable RC6 on Ironlake */
3405 if (INTEL_INFO(dev)->gen == 5)
3406 return 0;
2b4e57bd 3407
8bade1ad 3408 if (IS_IVYBRIDGE(dev))
cca84a1f 3409 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3410
3411 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3412}
3413
e6069ca8
ID		 3414int intel_enable_rc6(const struct drm_device *dev)
3415{
3416 return i915.enable_rc6;
3417}
3418
0961021a
BW		 3419static void gen8_enable_rps_interrupts(struct drm_device *dev)
3420{
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423 spin_lock_irq(&dev_priv->irq_lock);
3424 WARN_ON(dev_priv->rps.pm_iir);
3425 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3426 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3427 spin_unlock_irq(&dev_priv->irq_lock);
3428}
3429
44fc7d5c
DV		 3430static void gen6_enable_rps_interrupts(struct drm_device *dev)
3431{
3432 struct drm_i915_private *dev_priv = dev->dev_private;
3433
3434 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3435 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3436 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3437 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3438 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3439}
3440
3280e8b0
BW		 3441static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3442{
3443 /* All of these values are in units of 50MHz */
3444 dev_priv->rps.cur_freq = 0;
3445 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3446 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3447 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3448 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3449 /* XXX: only BYT has a special efficient freq */
3450 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3451 /* hw_max = RP0 until we check for overclocking */
3452 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3453
3454 /* Preserve min/max settings in case of re-init */
3455 if (dev_priv->rps.max_freq_softlimit == 0)
3456 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3457
3458 if (dev_priv->rps.min_freq_softlimit == 0)
3459 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3460}
3461
6edee7f3
BW		 3462static void gen8_enable_rps(struct drm_device *dev)
3463{
3464 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3465 struct intel_engine_cs *ring;
6edee7f3
BW		 3466 uint32_t rc6_mask = 0, rp_state_cap;
3467 int unused;
3468
3469 /* 1a: Software RC state - RC0 */
3470 I915_WRITE(GEN6_RC_STATE, 0);
3471
3472 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3473 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3474 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3475
3476 /* 2a: Disable RC states. */
3477 I915_WRITE(GEN6_RC_CONTROL, 0);
3478
3479 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3480 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3481
3482 /* 2b: Program RC6 thresholds.*/
3483 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3484 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3485 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3486 for_each_ring(ring, dev_priv, unused)
3487 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3488 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3489 if (IS_BROADWELL(dev))
3490 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3491 else
3492 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3493
3494 /* 3: Enable RC6 */
3495 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3496 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3497 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3498 if (IS_BROADWELL(dev))
3499 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3500 GEN7_RC_CTL_TO_MODE |
3501 rc6_mask);
3502 else
3503 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3504 GEN6_RC_CTL_EI_MODE(1) |
3505 rc6_mask);
6edee7f3
BW		 3506
3507 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3508 I915_WRITE(GEN6_RPNSWREQ,
3509 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3510 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3511 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3512 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3513 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3514
3515 /* Docs recommend 900MHz, and 300 MHz respectively */
3516 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3517 dev_priv->rps.max_freq_softlimit << 24 |
3518 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3519
3520 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3521 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3522 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3523 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3524
3525 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3526
3527 /* 5: Enable RPS */
3528 I915_WRITE(GEN6_RP_CONTROL,
3529 GEN6_RP_MEDIA_TURBO |
3530 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 3531 GEN6_RP_MEDIA_IS_GFX |
6edee7f3
BW		 3532 GEN6_RP_ENABLE |
3533 GEN6_RP_UP_BUSY_AVG |
3534 GEN6_RP_DOWN_IDLE_AVG);
3535
3536 /* 6: Ring frequency + overclocking (our driver does this later */
3537
3538 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3539
0961021a 3540 gen8_enable_rps_interrupts(dev);
6edee7f3 3541
c8d9a590 3542 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3543}
3544
79f5b2c7 3545static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3546{
79f5b2c7 3547 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3548 struct intel_engine_cs *ring;
2a5913a8 3549 u32 rp_state_cap;
7b9e0ae6 3550 u32 gt_perf_status;
d060c169 3551 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3552 u32 gtfifodbg;
2b4e57bd 3553 int rc6_mode;
42c0526c 3554 int i, ret;
2b4e57bd 3555
4fc688ce 3556 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3557
2b4e57bd
ED		 3558 /* Here begins a magic sequence of register writes to enable
3559 * auto-downclocking.
3560 *
3561 * Perhaps there might be some value in exposing these to
3562 * userspace...
3563 */
3564 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3565
3566 /* Clear the DBG now so we don't confuse earlier errors */
3567 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3568 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3569 I915_WRITE(GTFIFODBG, gtfifodbg);
3570 }
3571
c8d9a590 3572 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3573
7b9e0ae6
CW		 3574 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3575 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3576
3280e8b0 3577 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3578
2b4e57bd
ED		 3579 /* disable the counters and set deterministic thresholds */
3580 I915_WRITE(GEN6_RC_CONTROL, 0);
3581
3582 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3583 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3584 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3585 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3586 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3587
b4519513
CW		 3588 for_each_ring(ring, dev_priv, i)
3589 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3590
3591 I915_WRITE(GEN6_RC_SLEEP, 0);
3592 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3593 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3594 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3595 else
3596 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3597 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3598 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3599
5a7dc92a 3600 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3601 rc6_mode = intel_enable_rc6(dev_priv->dev);
3602 if (rc6_mode & INTEL_RC6_ENABLE)
3603 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3604
5a7dc92a
ED		 3605 /* We don't use those on Haswell */
3606 if (!IS_HASWELL(dev)) {
3607 if (rc6_mode & INTEL_RC6p_ENABLE)
3608 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3609
5a7dc92a
ED		 3610 if (rc6_mode & INTEL_RC6pp_ENABLE)
3611 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3612 }
2b4e57bd 3613
dc39fff7 3614 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3615
3616 I915_WRITE(GEN6_RC_CONTROL,
3617 rc6_mask |
3618 GEN6_RC_CTL_EI_MODE(1) |
3619 GEN6_RC_CTL_HW_ENABLE);
3620
dd75fdc8
CW		 3621 /* Power down if completely idle for over 50ms */
3622 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3623 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3624
42c0526c 3625 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3626 if (ret)
42c0526c 3627 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3628
3629 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3630 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3631 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3632 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3633 (pcu_mbox & 0xff) * 50);
b39fb297 3634 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3635 }
3636
dd75fdc8 3637 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3638 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3639
44fc7d5c 3640 gen6_enable_rps_interrupts(dev);
2b4e57bd 3641
31643d54
BW		 3642 rc6vids = 0;
3643 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3644 if (IS_GEN6(dev) && ret) {
3645 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3646 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3647 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3648 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3649 rc6vids &= 0xffff00;
3650 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3651 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3652 if (ret)
3653 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3654 }
3655
c8d9a590 3656 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3657}
3658
c2bc2fc5 3659static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3660{
79f5b2c7 3661 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3662 int min_freq = 15;
3ebecd07
CW		 3663 unsigned int gpu_freq;
3664 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3665 int scaling_factor = 180;
eda79642 3666 struct cpufreq_policy *policy;
2b4e57bd 3667
4fc688ce 3668 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3669
eda79642
BW		 3670 policy = cpufreq_cpu_get(0);
3671 if (policy) {
3672 max_ia_freq = policy->cpuinfo.max_freq;
3673 cpufreq_cpu_put(policy);
3674 } else {
3675 /*
3676 * Default to measured freq if none found, PCU will ensure we
3677 * don't go over
3678 */
2b4e57bd 3679 max_ia_freq = tsc_khz;
eda79642 3680 }
2b4e57bd
ED		 3681
3682 /* Convert from kHz to MHz */
3683 max_ia_freq /= 1000;
3684
153b4b95 3685 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3686 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3687 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3688
2b4e57bd
ED		 3689 /*
3690 * For each potential GPU frequency, load a ring frequency we'd like
3691 * to use for memory access. We do this by specifying the IA frequency
3692 * the PCU should use as a reference to determine the ring frequency.
3693 */
b39fb297 3694 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3695 gpu_freq--) {
b39fb297 3696 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3697 unsigned int ia_freq = 0, ring_freq = 0;
3698
46c764d4
BW		 3699 if (INTEL_INFO(dev)->gen >= 8) {
3700 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3701 ring_freq = max(min_ring_freq, gpu_freq);
3702 } else if (IS_HASWELL(dev)) {
f6aca45c 3703 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3704 ring_freq = max(min_ring_freq, ring_freq);
3705 /* leave ia_freq as the default, chosen by cpufreq */
3706 } else {
3707 /* On older processors, there is no separate ring
3708 * clock domain, so in order to boost the bandwidth
3709 * of the ring, we need to upclock the CPU (ia_freq).
3710 *
3711 * For GPU frequencies less than 750MHz,
3712 * just use the lowest ring freq.
3713 */
3714 if (gpu_freq < min_freq)
3715 ia_freq = 800;
3716 else
3717 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3718 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3719 }
2b4e57bd 3720
42c0526c
BW		 3721 sandybridge_pcode_write(dev_priv,
3722 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3723 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3724 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3725 gpu_freq);
2b4e57bd 3726 }
2b4e57bd
ED		 3727}
3728
c2bc2fc5
ID		 3729void gen6_update_ring_freq(struct drm_device *dev)
3730{
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732
3733 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3734 return;
3735
3736 mutex_lock(&dev_priv->rps.hw_lock);
3737 __gen6_update_ring_freq(dev);
3738 mutex_unlock(&dev_priv->rps.hw_lock);
3739}
3740
2b6b3a09
D		 3741int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3742{
3743 u32 val, rp0;
3744
3745 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3746 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3747
3748 return rp0;
3749}
3750
3751static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3752{
3753 u32 val, rpe;
3754
3755 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3756 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3757
3758 return rpe;
3759}
3760
3761int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3762{
3763 u32 val, rpn;
3764
3765 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3766 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3767 return rpn;
3768}
3769
0a073b84
JB		 3770int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3771{
3772 u32 val, rp0;
3773
64936258 3774 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3775
3776 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3777 /* Clamp to max */
3778 rp0 = min_t(u32, rp0, 0xea);
3779
3780 return rp0;
3781}
3782
3783static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3784{
3785 u32 val, rpe;
3786
64936258 3787 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3788 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3789 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3790 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3791
3792 return rpe;
3793}
3794
3795int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3796{
64936258 3797 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3798}
3799
ae48434c
ID		 3800/* Check that the pctx buffer wasn't move under us. */
3801static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3802{
3803 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3804
3805 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3806 dev_priv->vlv_pctx->stolen->start);
3807}
3808
38807746
D		 3809
3810/* Check that the pcbr address is not empty. */
3811static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3812{
3813 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3814
3815 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3816}
3817
3818static void cherryview_setup_pctx(struct drm_device *dev)
3819{
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821 unsigned long pctx_paddr, paddr;
3822 struct i915_gtt *gtt = &dev_priv->gtt;
3823 u32 pcbr;
3824 int pctx_size = 32*1024;
3825
3826 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3827
3828 pcbr = I915_READ(VLV_PCBR);
3829 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3830 paddr = (dev_priv->mm.stolen_base +
3831 (gtt->stolen_size - pctx_size));
3832
3833 pctx_paddr = (paddr & (~4095));
3834 I915_WRITE(VLV_PCBR, pctx_paddr);
3835 }
3836}
3837
c9cddffc
JB		 3838static void valleyview_setup_pctx(struct drm_device *dev)
3839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 struct drm_i915_gem_object *pctx;
3842 unsigned long pctx_paddr;
3843 u32 pcbr;
3844 int pctx_size = 24*1024;
3845
17b0c1f7
ID		 3846 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3847
c9cddffc
JB		 3848 pcbr = I915_READ(VLV_PCBR);
3849 if (pcbr) {
3850 /* BIOS set it up already, grab the pre-alloc'd space */
3851 int pcbr_offset;
3852
3853 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3854 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3855 pcbr_offset,
190d6cd5 3856 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3857 pctx_size);
3858 goto out;
3859 }
3860
3861 /*
3862 * From the Gunit register HAS:
3863 * The Gfx driver is expected to program this register and ensure
3864 * proper allocation within Gfx stolen memory. For example, this
3865 * register should be programmed such than the PCBR range does not
3866 * overlap with other ranges, such as the frame buffer, protected
3867 * memory, or any other relevant ranges.
3868 */
3869 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3870 if (!pctx) {
3871 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3872 return;
3873 }
3874
3875 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3876 I915_WRITE(VLV_PCBR, pctx_paddr);
3877
3878out:
3879 dev_priv->vlv_pctx = pctx;
3880}
3881
ae48434c
ID		 3882static void valleyview_cleanup_pctx(struct drm_device *dev)
3883{
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885
3886 if (WARN_ON(!dev_priv->vlv_pctx))
3887 return;
3888
3889 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3890 dev_priv->vlv_pctx = NULL;
3891}
3892
4e80519e
ID		 3893static void valleyview_init_gt_powersave(struct drm_device *dev)
3894{
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896
3897 valleyview_setup_pctx(dev);
3898
3899 mutex_lock(&dev_priv->rps.hw_lock);
3900
3901 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3902 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3903 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3904 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3905 dev_priv->rps.max_freq);
3906
3907 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3908 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3909 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3910 dev_priv->rps.efficient_freq);
3911
3912 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3913 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3914 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3915 dev_priv->rps.min_freq);
3916
3917 /* Preserve min/max settings in case of re-init */
3918 if (dev_priv->rps.max_freq_softlimit == 0)
3919 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3920
3921 if (dev_priv->rps.min_freq_softlimit == 0)
3922 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3923
3924 mutex_unlock(&dev_priv->rps.hw_lock);
3925}
3926
38807746
D		 3927static void cherryview_init_gt_powersave(struct drm_device *dev)
3928{
2b6b3a09
D		 3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930
38807746 3931 cherryview_setup_pctx(dev);
2b6b3a09
D		 3932
3933 mutex_lock(&dev_priv->rps.hw_lock);
3934
3935 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
3936 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3937 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3938 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3939 dev_priv->rps.max_freq);
3940
3941 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
3942 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3943 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3944 dev_priv->rps.efficient_freq);
3945
3946 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
3947 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3948 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3949 dev_priv->rps.min_freq);
3950
3951 /* Preserve min/max settings in case of re-init */
3952 if (dev_priv->rps.max_freq_softlimit == 0)
3953 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3954
3955 if (dev_priv->rps.min_freq_softlimit == 0)
3956 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3957
3958 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 3959}
3960
4e80519e
ID		 3961static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3962{
3963 valleyview_cleanup_pctx(dev);
3964}
3965
38807746
D		 3966static void cherryview_enable_rps(struct drm_device *dev)
3967{
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 struct intel_engine_cs *ring;
2b6b3a09 3970 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 3971 int i;
3972
3973 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3974
3975 gtfifodbg = I915_READ(GTFIFODBG);
3976 if (gtfifodbg) {
3977 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3978 gtfifodbg);
3979 I915_WRITE(GTFIFODBG, gtfifodbg);
3980 }
3981
3982 cherryview_check_pctx(dev_priv);
3983
3984 /* 1a & 1b: Get forcewake during program sequence. Although the driver
3985 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3986 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3987
3988 /* 2a: Program RC6 thresholds.*/
3989 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3990 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3991 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3992
3993 for_each_ring(ring, dev_priv, i)
3994 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3995 I915_WRITE(GEN6_RC_SLEEP, 0);
3996
3997 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3998
3999 /* allows RC6 residency counter to work */
4000 I915_WRITE(VLV_COUNTER_CONTROL,
4001 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4002 VLV_MEDIA_RC6_COUNT_EN |
4003 VLV_RENDER_RC6_COUNT_EN));
4004
4005 /* For now we assume BIOS is allocating and populating the PCBR */
4006 pcbr = I915_READ(VLV_PCBR);
4007
4008 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4009
4010 /* 3: Enable RC6 */
4011 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4012 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4013 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4014
4015 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4016
2b6b3a09
D		 4017 /* 4 Program defaults and thresholds for RPS*/
4018 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4019 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4020 I915_WRITE(GEN6_RP_UP_EI, 66000);
4021 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4022
4023 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4024
7405f42c
TR		 4025 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4026 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4027 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4028
2b6b3a09
D		 4029 /* 5: Enable RPS */
4030 I915_WRITE(GEN6_RP_CONTROL,
4031 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4032 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4033 GEN6_RP_ENABLE |
4034 GEN6_RP_UP_BUSY_AVG |
4035 GEN6_RP_DOWN_IDLE_AVG);
4036
4037 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4038
4039 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4040 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4041
4042 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4043 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4044 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4045 dev_priv->rps.cur_freq);
4046
4047 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4048 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4049 dev_priv->rps.efficient_freq);
4050
4051 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4052
38807746
D		 4053 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4054}
4055
0a073b84
JB		 4056static void valleyview_enable_rps(struct drm_device *dev)
4057{
4058 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4059 struct intel_engine_cs *ring;
2a5913a8 4060 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4061 int i;
4062
4063 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4064
ae48434c
ID		 4065 valleyview_check_pctx(dev_priv);
4066
0a073b84 4067 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4068 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4069 gtfifodbg);
0a073b84
JB		 4070 I915_WRITE(GTFIFODBG, gtfifodbg);
4071 }
4072
c8d9a590
D		 4073 /* If VLV, Forcewake all wells, else re-direct to regular path */
4074 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4075
4076 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4077 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4078 I915_WRITE(GEN6_RP_UP_EI, 66000);
4079 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4080
4081 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4082
4083 I915_WRITE(GEN6_RP_CONTROL,
4084 GEN6_RP_MEDIA_TURBO |
4085 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4086 GEN6_RP_MEDIA_IS_GFX |
4087 GEN6_RP_ENABLE |
4088 GEN6_RP_UP_BUSY_AVG |
4089 GEN6_RP_DOWN_IDLE_CONT);
4090
4091 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4092 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4093 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4094
4095 for_each_ring(ring, dev_priv, i)
4096 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4097
2f0aa304 4098 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4099
4100 /* allows RC6 residency counter to work */
49798eb2
JB		 4101 I915_WRITE(VLV_COUNTER_CONTROL,
4102 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4103 VLV_MEDIA_RC6_COUNT_EN |
4104 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 4105 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4106 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4107
4108 intel_print_rc6_info(dev, rc6_mode);
4109
a2b23fe0 4110 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4111
64936258 4112 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4113
4114 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4115 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4116
b39fb297 4117 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4118 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4119 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4120 dev_priv->rps.cur_freq);
0a073b84 4121
73008b98 4122 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4123 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4124 dev_priv->rps.efficient_freq);
0a073b84 4125
b39fb297 4126 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4127
44fc7d5c 4128 gen6_enable_rps_interrupts(dev);
0a073b84 4129
c8d9a590 4130 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4131}
4132
930ebb46 4133void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4134{
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136
3e373948 4137 if (dev_priv->ips.renderctx) {
d7f46fc4 4138 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4139 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4140 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4141 }
4142
3e373948 4143 if (dev_priv->ips.pwrctx) {
d7f46fc4 4144 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4145 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4146 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4147 }
4148}
4149
930ebb46 4150static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4151{
4152 struct drm_i915_private *dev_priv = dev->dev_private;
4153
4154 if (I915_READ(PWRCTXA)) {
4155 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4156 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4157 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4158 50);
4159
4160 I915_WRITE(PWRCTXA, 0);
4161 POSTING_READ(PWRCTXA);
4162
4163 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4164 POSTING_READ(RSTDBYCTL);
4165 }
2b4e57bd
ED		 4166}
4167
4168static int ironlake_setup_rc6(struct drm_device *dev)
4169{
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171
3e373948
DV		 4172 if (dev_priv->ips.renderctx == NULL)
4173 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4174 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4175 return -ENOMEM;
4176
3e373948
DV		 4177 if (dev_priv->ips.pwrctx == NULL)
4178 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4179 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4180 ironlake_teardown_rc6(dev);
4181 return -ENOMEM;
4182 }
4183
4184 return 0;
4185}
4186
930ebb46 4187static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4188{
4189 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4190 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4191 bool was_interruptible;
2b4e57bd
ED		 4192 int ret;
4193
4194 /* rc6 disabled by default due to repeated reports of hanging during
4195 * boot and resume.
4196 */
4197 if (!intel_enable_rc6(dev))
4198 return;
4199
79f5b2c7
DV		 4200 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4201
2b4e57bd 4202 ret = ironlake_setup_rc6(dev);
79f5b2c7 4203 if (ret)
2b4e57bd 4204 return;
2b4e57bd 4205
3e960501
CW		 4206 was_interruptible = dev_priv->mm.interruptible;
4207 dev_priv->mm.interruptible = false;
4208
2b4e57bd
ED		 4209 /*
4210 * GPU can automatically power down the render unit if given a page
4211 * to save state.
4212 */
6d90c952 4213 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4214 if (ret) {
4215 ironlake_teardown_rc6(dev);
3e960501 4216 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4217 return;
4218 }
4219
6d90c952
DV		 4220 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4221 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4222 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4223 MI_MM_SPACE_GTT |
4224 MI_SAVE_EXT_STATE_EN |
4225 MI_RESTORE_EXT_STATE_EN |
4226 MI_RESTORE_INHIBIT);
4227 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4228 intel_ring_emit(ring, MI_NOOP);
4229 intel_ring_emit(ring, MI_FLUSH);
4230 intel_ring_advance(ring);
2b4e57bd
ED		 4231
4232 /*
4233 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4234 * does an implicit flush, combined with MI_FLUSH above, it should be
4235 * safe to assume that renderctx is valid
4236 */
3e960501
CW		 4237 ret = intel_ring_idle(ring);
4238 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4239 if (ret) {
def27a58 4240 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4241 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4242 return;
4243 }
4244
f343c5f6 4245 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4246 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4247
91ca689a 4248 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4249}
4250
dde18883
ED		 4251static unsigned long intel_pxfreq(u32 vidfreq)
4252{
4253 unsigned long freq;
4254 int div = (vidfreq & 0x3f0000) >> 16;
4255 int post = (vidfreq & 0x3000) >> 12;
4256 int pre = (vidfreq & 0x7);
4257
4258 if (!pre)
4259 return 0;
4260
4261 freq = ((div * 133333) / ((1<<post) * pre));
4262
4263 return freq;
4264}
4265
eb48eb00
DV		 4266static const struct cparams {
4267 u16 i;
4268 u16 t;
4269 u16 m;
4270 u16 c;
4271} cparams[] = {
4272 { 1, 1333, 301, 28664 },
4273 { 1, 1066, 294, 24460 },
4274 { 1, 800, 294, 25192 },
4275 { 0, 1333, 276, 27605 },
4276 { 0, 1066, 276, 27605 },
4277 { 0, 800, 231, 23784 },
4278};
4279
f531dcb2 4280static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4281{
4282 u64 total_count, diff, ret;
4283 u32 count1, count2, count3, m = 0, c = 0;
4284 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4285 int i;
4286
02d71956
DV		 4287 assert_spin_locked(&mchdev_lock);
4288
20e4d407 4289 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4290
4291 /* Prevent division-by-zero if we are asking too fast.
4292 * Also, we don't get interesting results if we are polling
4293 * faster than once in 10ms, so just return the saved value
4294 * in such cases.
4295 */
4296 if (diff1 <= 10)
20e4d407 4297 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4298
4299 count1 = I915_READ(DMIEC);
4300 count2 = I915_READ(DDREC);
4301 count3 = I915_READ(CSIEC);
4302
4303 total_count = count1 + count2 + count3;
4304
4305 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4306 if (total_count < dev_priv->ips.last_count1) {
4307 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4308 diff += total_count;
4309 } else {
20e4d407 4310 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4311 }
4312
4313 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4314 if (cparams[i].i == dev_priv->ips.c_m &&
4315 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4316 m = cparams[i].m;
4317 c = cparams[i].c;
4318 break;
4319 }
4320 }
4321
4322 diff = div_u64(diff, diff1);
4323 ret = ((m * diff) + c);
4324 ret = div_u64(ret, 10);
4325
20e4d407
DV		 4326 dev_priv->ips.last_count1 = total_count;
4327 dev_priv->ips.last_time1 = now;
eb48eb00 4328
20e4d407 4329 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4330
4331 return ret;
4332}
4333
f531dcb2
CW		 4334unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4335{
3d13ef2e 4336 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4337 unsigned long val;
4338
3d13ef2e 4339 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4340 return 0;
4341
4342 spin_lock_irq(&mchdev_lock);
4343
4344 val = __i915_chipset_val(dev_priv);
4345
4346 spin_unlock_irq(&mchdev_lock);
4347
4348 return val;
4349}
4350
eb48eb00
DV		 4351unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4352{
4353 unsigned long m, x, b;
4354 u32 tsfs;
4355
4356 tsfs = I915_READ(TSFS);
4357
4358 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4359 x = I915_READ8(TR1);
4360
4361 b = tsfs & TSFS_INTR_MASK;
4362
4363 return ((m * x) / 127) - b;
4364}
4365
4366static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4367{
3d13ef2e 4368 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4369 static const struct v_table {
4370 u16 vd; /* in .1 mil */
4371 u16 vm; /* in .1 mil */
4372 } v_table[] = {
4373 { 0, 0, },
4374 { 375, 0, },
4375 { 500, 0, },
4376 { 625, 0, },
4377 { 750, 0, },
4378 { 875, 0, },
4379 { 1000, 0, },
4380 { 1125, 0, },
4381 { 4125, 3000, },
4382 { 4125, 3000, },
4383 { 4125, 3000, },
4384 { 4125, 3000, },
4385 { 4125, 3000, },
4386 { 4125, 3000, },
4387 { 4125, 3000, },
4388 { 4125, 3000, },
4389 { 4125, 3000, },
4390 { 4125, 3000, },
4391 { 4125, 3000, },
4392 { 4125, 3000, },
4393 { 4125, 3000, },
4394 { 4125, 3000, },
4395 { 4125, 3000, },
4396 { 4125, 3000, },
4397 { 4125, 3000, },
4398 { 4125, 3000, },
4399 { 4125, 3000, },
4400 { 4125, 3000, },
4401 { 4125, 3000, },
4402 { 4125, 3000, },
4403 { 4125, 3000, },
4404 { 4125, 3000, },
4405 { 4250, 3125, },
4406 { 4375, 3250, },
4407 { 4500, 3375, },
4408 { 4625, 3500, },
4409 { 4750, 3625, },
4410 { 4875, 3750, },
4411 { 5000, 3875, },
4412 { 5125, 4000, },
4413 { 5250, 4125, },
4414 { 5375, 4250, },
4415 { 5500, 4375, },
4416 { 5625, 4500, },
4417 { 5750, 4625, },
4418 { 5875, 4750, },
4419 { 6000, 4875, },
4420 { 6125, 5000, },
4421 { 6250, 5125, },
4422 { 6375, 5250, },
4423 { 6500, 5375, },
4424 { 6625, 5500, },
4425 { 6750, 5625, },
4426 { 6875, 5750, },
4427 { 7000, 5875, },
4428 { 7125, 6000, },
4429 { 7250, 6125, },
4430 { 7375, 6250, },
4431 { 7500, 6375, },
4432 { 7625, 6500, },
4433 { 7750, 6625, },
4434 { 7875, 6750, },
4435 { 8000, 6875, },
4436 { 8125, 7000, },
4437 { 8250, 7125, },
4438 { 8375, 7250, },
4439 { 8500, 7375, },
4440 { 8625, 7500, },
4441 { 8750, 7625, },
4442 { 8875, 7750, },
4443 { 9000, 7875, },
4444 { 9125, 8000, },
4445 { 9250, 8125, },
4446 { 9375, 8250, },
4447 { 9500, 8375, },
4448 { 9625, 8500, },
4449 { 9750, 8625, },
4450 { 9875, 8750, },
4451 { 10000, 8875, },
4452 { 10125, 9000, },
4453 { 10250, 9125, },
4454 { 10375, 9250, },
4455 { 10500, 9375, },
4456 { 10625, 9500, },
4457 { 10750, 9625, },
4458 { 10875, 9750, },
4459 { 11000, 9875, },
4460 { 11125, 10000, },
4461 { 11250, 10125, },
4462 { 11375, 10250, },
4463 { 11500, 10375, },
4464 { 11625, 10500, },
4465 { 11750, 10625, },
4466 { 11875, 10750, },
4467 { 12000, 10875, },
4468 { 12125, 11000, },
4469 { 12250, 11125, },
4470 { 12375, 11250, },
4471 { 12500, 11375, },
4472 { 12625, 11500, },
4473 { 12750, 11625, },
4474 { 12875, 11750, },
4475 { 13000, 11875, },
4476 { 13125, 12000, },
4477 { 13250, 12125, },
4478 { 13375, 12250, },
4479 { 13500, 12375, },
4480 { 13625, 12500, },
4481 { 13750, 12625, },
4482 { 13875, 12750, },
4483 { 14000, 12875, },
4484 { 14125, 13000, },
4485 { 14250, 13125, },
4486 { 14375, 13250, },
4487 { 14500, 13375, },
4488 { 14625, 13500, },
4489 { 14750, 13625, },
4490 { 14875, 13750, },
4491 { 15000, 13875, },
4492 { 15125, 14000, },
4493 { 15250, 14125, },
4494 { 15375, 14250, },
4495 { 15500, 14375, },
4496 { 15625, 14500, },
4497 { 15750, 14625, },
4498 { 15875, 14750, },
4499 { 16000, 14875, },
4500 { 16125, 15000, },
4501 };
3d13ef2e 4502 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4503 return v_table[pxvid].vm;
4504 else
4505 return v_table[pxvid].vd;
4506}
4507
02d71956 4508static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4509{
4510 struct timespec now, diff1;
4511 u64 diff;
4512 unsigned long diffms;
4513 u32 count;
4514
02d71956 4515 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4516
4517 getrawmonotonic(&now);
20e4d407 4518 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4519
4520 /* Don't divide by 0 */
4521 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4522 if (!diffms)
4523 return;
4524
4525 count = I915_READ(GFXEC);
4526
20e4d407
DV		 4527 if (count < dev_priv->ips.last_count2) {
4528 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4529 diff += count;
4530 } else {
20e4d407 4531 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4532 }
4533
20e4d407
DV		 4534 dev_priv->ips.last_count2 = count;
4535 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4536
4537 /* More magic constants... */
4538 diff = diff * 1181;
4539 diff = div_u64(diff, diffms * 10);
20e4d407 4540 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4541}
4542
02d71956
DV		 4543void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4544{
3d13ef2e
DL		 4545 struct drm_device *dev = dev_priv->dev;
4546
4547 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4548 return;
4549
9270388e 4550 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4551
4552 __i915_update_gfx_val(dev_priv);
4553
9270388e 4554 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4555}
4556
f531dcb2 4557static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4558{
4559 unsigned long t, corr, state1, corr2, state2;
4560 u32 pxvid, ext_v;
4561
02d71956
DV		 4562 assert_spin_locked(&mchdev_lock);
4563
b39fb297 4564 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4565 pxvid = (pxvid >> 24) & 0x7f;
4566 ext_v = pvid_to_extvid(dev_priv, pxvid);
4567
4568 state1 = ext_v;
4569
4570 t = i915_mch_val(dev_priv);
4571
4572 /* Revel in the empirically derived constants */
4573
4574 /* Correction factor in 1/100000 units */
4575 if (t > 80)
4576 corr = ((t * 2349) + 135940);
4577 else if (t >= 50)
4578 corr = ((t * 964) + 29317);
4579 else /* < 50 */
4580 corr = ((t * 301) + 1004);
4581
4582 corr = corr * ((150142 * state1) / 10000 - 78642);
4583 corr /= 100000;
20e4d407 4584 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4585
4586 state2 = (corr2 * state1) / 10000;
4587 state2 /= 100; /* convert to mW */
4588
02d71956 4589 __i915_update_gfx_val(dev_priv);
eb48eb00 4590
20e4d407 4591 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4592}
4593
f531dcb2
CW		 4594unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4595{
3d13ef2e 4596 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4597 unsigned long val;
4598
3d13ef2e 4599 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4600 return 0;
4601
4602 spin_lock_irq(&mchdev_lock);
4603
4604 val = __i915_gfx_val(dev_priv);
4605
4606 spin_unlock_irq(&mchdev_lock);
4607
4608 return val;
4609}
4610
eb48eb00
DV		 4611/**
4612 * i915_read_mch_val - return value for IPS use
4613 *
4614 * Calculate and return a value for the IPS driver to use when deciding whether
4615 * we have thermal and power headroom to increase CPU or GPU power budget.
4616 */
4617unsigned long i915_read_mch_val(void)
4618{
4619 struct drm_i915_private *dev_priv;
4620 unsigned long chipset_val, graphics_val, ret = 0;
4621
9270388e 4622 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4623 if (!i915_mch_dev)
4624 goto out_unlock;
4625 dev_priv = i915_mch_dev;
4626
f531dcb2
CW		 4627 chipset_val = __i915_chipset_val(dev_priv);
4628 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4629
4630 ret = chipset_val + graphics_val;
4631
4632out_unlock:
9270388e 4633 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4634
4635 return ret;
4636}
4637EXPORT_SYMBOL_GPL(i915_read_mch_val);
4638
4639/**
4640 * i915_gpu_raise - raise GPU frequency limit
4641 *
4642 * Raise the limit; IPS indicates we have thermal headroom.
4643 */
4644bool i915_gpu_raise(void)
4645{
4646 struct drm_i915_private *dev_priv;
4647 bool ret = true;
4648
9270388e 4649 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4650 if (!i915_mch_dev) {
4651 ret = false;
4652 goto out_unlock;
4653 }
4654 dev_priv = i915_mch_dev;
4655
20e4d407
DV		 4656 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4657 dev_priv->ips.max_delay--;
eb48eb00
DV		 4658
4659out_unlock:
9270388e 4660 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4661
4662 return ret;
4663}
4664EXPORT_SYMBOL_GPL(i915_gpu_raise);
4665
4666/**
4667 * i915_gpu_lower - lower GPU frequency limit
4668 *
4669 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4670 * frequency maximum.
4671 */
4672bool i915_gpu_lower(void)
4673{
4674 struct drm_i915_private *dev_priv;
4675 bool ret = true;
4676
9270388e 4677 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4678 if (!i915_mch_dev) {
4679 ret = false;
4680 goto out_unlock;
4681 }
4682 dev_priv = i915_mch_dev;
4683
20e4d407
DV		 4684 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4685 dev_priv->ips.max_delay++;
eb48eb00
DV		 4686
4687out_unlock:
9270388e 4688 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4689
4690 return ret;
4691}
4692EXPORT_SYMBOL_GPL(i915_gpu_lower);
4693
4694/**
4695 * i915_gpu_busy - indicate GPU business to IPS
4696 *
4697 * Tell the IPS driver whether or not the GPU is busy.
4698 */
4699bool i915_gpu_busy(void)
4700{
4701 struct drm_i915_private *dev_priv;
a4872ba6 4702 struct intel_engine_cs *ring;
eb48eb00 4703 bool ret = false;
f047e395 4704 int i;
eb48eb00 4705
9270388e 4706 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4707 if (!i915_mch_dev)
4708 goto out_unlock;
4709 dev_priv = i915_mch_dev;
4710
f047e395
CW		 4711 for_each_ring(ring, dev_priv, i)
4712 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4713
4714out_unlock:
9270388e 4715 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4716
4717 return ret;
4718}
4719EXPORT_SYMBOL_GPL(i915_gpu_busy);
4720
4721/**
4722 * i915_gpu_turbo_disable - disable graphics turbo
4723 *
4724 * Disable graphics turbo by resetting the max frequency and setting the
4725 * current frequency to the default.
4726 */
4727bool i915_gpu_turbo_disable(void)
4728{
4729 struct drm_i915_private *dev_priv;
4730 bool ret = true;
4731
9270388e 4732 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4733 if (!i915_mch_dev) {
4734 ret = false;
4735 goto out_unlock;
4736 }
4737 dev_priv = i915_mch_dev;
4738
20e4d407 4739 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4740
20e4d407 4741 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4742 ret = false;
4743
4744out_unlock:
9270388e 4745 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4746
4747 return ret;
4748}
4749EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4750
4751/**
4752 * Tells the intel_ips driver that the i915 driver is now loaded, if
4753 * IPS got loaded first.
4754 *
4755 * This awkward dance is so that neither module has to depend on the
4756 * other in order for IPS to do the appropriate communication of
4757 * GPU turbo limits to i915.
4758 */
4759static void
4760ips_ping_for_i915_load(void)
4761{
4762 void (*link)(void);
4763
4764 link = symbol_get(ips_link_to_i915_driver);
4765 if (link) {
4766 link();
4767 symbol_put(ips_link_to_i915_driver);
4768 }
4769}
4770
4771void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4772{
02d71956
DV		 4773 /* We only register the i915 ips part with intel-ips once everything is
4774 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4775 spin_lock_irq(&mchdev_lock);
eb48eb00 4776 i915_mch_dev = dev_priv;
9270388e 4777 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4778
4779 ips_ping_for_i915_load();
4780}
4781
4782void intel_gpu_ips_teardown(void)
4783{
9270388e 4784 spin_lock_irq(&mchdev_lock);
eb48eb00 4785 i915_mch_dev = NULL;
9270388e 4786 spin_unlock_irq(&mchdev_lock);
eb48eb00 4787}
76c3552f 4788
8090c6b9 4789static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4790{
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 u32 lcfuse;
4793 u8 pxw[16];
4794 int i;
4795
4796 /* Disable to program */
4797 I915_WRITE(ECR, 0);
4798 POSTING_READ(ECR);
4799
4800 /* Program energy weights for various events */
4801 I915_WRITE(SDEW, 0x15040d00);
4802 I915_WRITE(CSIEW0, 0x007f0000);
4803 I915_WRITE(CSIEW1, 0x1e220004);
4804 I915_WRITE(CSIEW2, 0x04000004);
4805
4806 for (i = 0; i < 5; i++)
4807 I915_WRITE(PEW + (i * 4), 0);
4808 for (i = 0; i < 3; i++)
4809 I915_WRITE(DEW + (i * 4), 0);
4810
4811 /* Program P-state weights to account for frequency power adjustment */
4812 for (i = 0; i < 16; i++) {
4813 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4814 unsigned long freq = intel_pxfreq(pxvidfreq);
4815 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4816 PXVFREQ_PX_SHIFT;
4817 unsigned long val;
4818
4819 val = vid * vid;
4820 val *= (freq / 1000);
4821 val *= 255;
4822 val /= (127*127*900);
4823 if (val > 0xff)
4824 DRM_ERROR("bad pxval: %ld\n", val);
4825 pxw[i] = val;
4826 }
4827 /* Render standby states get 0 weight */
4828 pxw[14] = 0;
4829 pxw[15] = 0;
4830
4831 for (i = 0; i < 4; i++) {
4832 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4833 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4834 I915_WRITE(PXW + (i * 4), val);
4835 }
4836
4837 /* Adjust magic regs to magic values (more experimental results) */
4838 I915_WRITE(OGW0, 0);
4839 I915_WRITE(OGW1, 0);
4840 I915_WRITE(EG0, 0x00007f00);
4841 I915_WRITE(EG1, 0x0000000e);
4842 I915_WRITE(EG2, 0x000e0000);
4843 I915_WRITE(EG3, 0x68000300);
4844 I915_WRITE(EG4, 0x42000000);
4845 I915_WRITE(EG5, 0x00140031);
4846 I915_WRITE(EG6, 0);
4847 I915_WRITE(EG7, 0);
4848
4849 for (i = 0; i < 8; i++)
4850 I915_WRITE(PXWL + (i * 4), 0);
4851
4852 /* Enable PMON + select events */
4853 I915_WRITE(ECR, 0x80000019);
4854
4855 lcfuse = I915_READ(LCFUSE02);
4856
20e4d407 4857 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4858}
4859
ae48434c
ID		 4860void intel_init_gt_powersave(struct drm_device *dev)
4861{
e6069ca8
ID		 4862 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4863
38807746
D		 4864 if (IS_CHERRYVIEW(dev))
4865 cherryview_init_gt_powersave(dev);
4866 else if (IS_VALLEYVIEW(dev))
4e80519e 4867 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4868}
4869
4870void intel_cleanup_gt_powersave(struct drm_device *dev)
4871{
38807746
D		 4872 if (IS_CHERRYVIEW(dev))
4873 return;
4874 else if (IS_VALLEYVIEW(dev))
4e80519e 4875 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4876}
4877
156c7ca0
JB		 4878/**
4879 * intel_suspend_gt_powersave - suspend PM work and helper threads
4880 * @dev: drm device
4881 *
4882 * We don't want to disable RC6 or other features here, we just want
4883 * to make sure any work we've queued has finished and won't bother
4884 * us while we're suspended.
4885 */
4886void intel_suspend_gt_powersave(struct drm_device *dev)
4887{
4888 struct drm_i915_private *dev_priv = dev->dev_private;
4889
4890 /* Interrupts should be disabled already to avoid re-arming. */
e11aa362 4891 WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled);
156c7ca0
JB		 4892
4893 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4894
4895 cancel_work_sync(&dev_priv->rps.work);
4896}
4897
8090c6b9
DV		 4898void intel_disable_gt_powersave(struct drm_device *dev)
4899{
1a01ab3b
JB		 4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901
fd0c0642 4902 /* Interrupts should be disabled already to avoid re-arming. */
e11aa362 4903 WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled);
fd0c0642 4904
930ebb46 4905 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4906 ironlake_disable_drps(dev);
930ebb46 4907 ironlake_disable_rc6(dev);
38807746 4908 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 4909 intel_suspend_gt_powersave(dev);
e494837a 4910
4fc688ce 4911 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 4912 if (IS_CHERRYVIEW(dev))
4913 cherryview_disable_rps(dev);
4914 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 4915 valleyview_disable_rps(dev);
4916 else
4917 gen6_disable_rps(dev);
c0951f0c 4918 dev_priv->rps.enabled = false;
4fc688ce 4919 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4920 }
8090c6b9
DV		 4921}
4922
1a01ab3b
JB		 4923static void intel_gen6_powersave_work(struct work_struct *work)
4924{
4925 struct drm_i915_private *dev_priv =
4926 container_of(work, struct drm_i915_private,
4927 rps.delayed_resume_work.work);
4928 struct drm_device *dev = dev_priv->dev;
4929
4fc688ce 4930 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 4931
38807746
D		 4932 if (IS_CHERRYVIEW(dev)) {
4933 cherryview_enable_rps(dev);
4934 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 4935 valleyview_enable_rps(dev);
6edee7f3
BW		 4936 } else if (IS_BROADWELL(dev)) {
4937 gen8_enable_rps(dev);
c2bc2fc5 4938 __gen6_update_ring_freq(dev);
0a073b84
JB		 4939 } else {
4940 gen6_enable_rps(dev);
c2bc2fc5 4941 __gen6_update_ring_freq(dev);
0a073b84 4942 }
c0951f0c 4943 dev_priv->rps.enabled = true;
4fc688ce 4944 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 4945
4946 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 4947}
4948
8090c6b9
DV		 4949void intel_enable_gt_powersave(struct drm_device *dev)
4950{
1a01ab3b
JB		 4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952
8090c6b9 4953 if (IS_IRONLAKE_M(dev)) {
dc1d0136 4954 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 4955 ironlake_enable_drps(dev);
4956 ironlake_enable_rc6(dev);
4957 intel_init_emon(dev);
dc1d0136 4958 mutex_unlock(&dev->struct_mutex);
38807746 4959 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 4960 /*
4961 * PCU communication is slow and this doesn't need to be
4962 * done at any specific time, so do this out of our fast path
4963 * to make resume and init faster.
c6df39b5
ID		 4964 *
4965 * We depend on the HW RC6 power context save/restore
4966 * mechanism when entering D3 through runtime PM suspend. So
4967 * disable RPM until RPS/RC6 is properly setup. We can only
4968 * get here via the driver load/system resume/runtime resume
4969 * paths, so the _noresume version is enough (and in case of
4970 * runtime resume it's necessary).
1a01ab3b 4971 */
c6df39b5
ID		 4972 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4973 round_jiffies_up_relative(HZ)))
4974 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 4975 }
4976}
4977
c6df39b5
ID		 4978void intel_reset_gt_powersave(struct drm_device *dev)
4979{
4980 struct drm_i915_private *dev_priv = dev->dev_private;
4981
4982 dev_priv->rps.enabled = false;
4983 intel_enable_gt_powersave(dev);
4984}
4985
3107bd48
DV		 4986static void ibx_init_clock_gating(struct drm_device *dev)
4987{
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989
4990 /*
4991 * On Ibex Peak and Cougar Point, we need to disable clock
4992 * gating for the panel power sequencer or it will fail to
4993 * start up when no ports are active.
4994 */
4995 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4996}
4997
0e088b8f
VS		 4998static void g4x_disable_trickle_feed(struct drm_device *dev)
4999{
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 int pipe;
5002
5003 for_each_pipe(pipe) {
5004 I915_WRITE(DSPCNTR(pipe),
5005 I915_READ(DSPCNTR(pipe)) |
5006 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5007 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5008 }
5009}
5010
017636cc
VS		 5011static void ilk_init_lp_watermarks(struct drm_device *dev)
5012{
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014
5015 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5016 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5017 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5018
5019 /*
5020 * Don't touch WM1S_LP_EN here.
5021 * Doing so could cause underruns.
5022 */
5023}
5024
1fa61106 5025static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5026{
5027 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5028 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5029
f1e8fa56
DL		 5030 /*
5031 * Required for FBC
5032 * WaFbcDisableDpfcClockGating:ilk
5033 */
4d47e4f5
DL		 5034 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5035 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5036 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5037
5038 I915_WRITE(PCH_3DCGDIS0,
5039 MARIUNIT_CLOCK_GATE_DISABLE |
5040 SVSMUNIT_CLOCK_GATE_DISABLE);
5041 I915_WRITE(PCH_3DCGDIS1,
5042 VFMUNIT_CLOCK_GATE_DISABLE);
5043
6f1d69b0
ED		 5044 /*
5045 * According to the spec the following bits should be set in
5046 * order to enable memory self-refresh
5047 * The bit 22/21 of 0x42004
5048 * The bit 5 of 0x42020
5049 * The bit 15 of 0x45000
5050 */
5051 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5052 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5053 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5054 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5055 I915_WRITE(DISP_ARB_CTL,
5056 (I915_READ(DISP_ARB_CTL) |
5057 DISP_FBC_WM_DIS));
017636cc
VS		 5058
5059 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5060
5061 /*
5062 * Based on the document from hardware guys the following bits
5063 * should be set unconditionally in order to enable FBC.
5064 * The bit 22 of 0x42000
5065 * The bit 22 of 0x42004
5066 * The bit 7,8,9 of 0x42020.
5067 */
5068 if (IS_IRONLAKE_M(dev)) {
4bb35334 5069 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5070 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5071 I915_READ(ILK_DISPLAY_CHICKEN1) |
5072 ILK_FBCQ_DIS);
5073 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5074 I915_READ(ILK_DISPLAY_CHICKEN2) |
5075 ILK_DPARB_GATE);
6f1d69b0
ED		 5076 }
5077
4d47e4f5
DL		 5078 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5079
6f1d69b0
ED		 5080 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5081 I915_READ(ILK_DISPLAY_CHICKEN2) |
5082 ILK_ELPIN_409_SELECT);
5083 I915_WRITE(_3D_CHICKEN2,
5084 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5085 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5086
ecdb4eb7 5087 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5088 I915_WRITE(CACHE_MODE_0,
5089 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5090
4e04632e
AG		 5091 /* WaDisable_RenderCache_OperationalFlush:ilk */
5092 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5093
0e088b8f 5094 g4x_disable_trickle_feed(dev);
bdad2b2f 5095
3107bd48
DV		 5096 ibx_init_clock_gating(dev);
5097}
5098
5099static void cpt_init_clock_gating(struct drm_device *dev)
5100{
5101 struct drm_i915_private *dev_priv = dev->dev_private;
5102 int pipe;
3f704fa2 5103 uint32_t val;
3107bd48
DV		 5104
5105 /*
5106 * On Ibex Peak and Cougar Point, we need to disable clock
5107 * gating for the panel power sequencer or it will fail to
5108 * start up when no ports are active.
5109 */
cd664078
JB		 5110 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5111 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5112 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5113 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5114 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5115 /* The below fixes the weird display corruption, a few pixels shifted
5116 * downward, on (only) LVDS of some HP laptops with IVY.
5117 */
3f704fa2 5118 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5119 val = I915_READ(TRANS_CHICKEN2(pipe));
5120 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5121 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5122 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5123 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5124 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5125 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5126 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5127 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5128 }
3107bd48
DV		 5129 /* WADP0ClockGatingDisable */
5130 for_each_pipe(pipe) {
5131 I915_WRITE(TRANS_CHICKEN1(pipe),
5132 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5133 }
6f1d69b0
ED		 5134}
5135
1d7aaa0c
DV		 5136static void gen6_check_mch_setup(struct drm_device *dev)
5137{
5138 struct drm_i915_private *dev_priv = dev->dev_private;
5139 uint32_t tmp;
5140
5141 tmp = I915_READ(MCH_SSKPD);
5142 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5143 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5144 DRM_INFO("This can cause pipe underruns and display issues.\n");
5145 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5146 }
5147}
5148
1fa61106 5149static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5150{
5151 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5152 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5153
231e54f6 5154 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5155
5156 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5157 I915_READ(ILK_DISPLAY_CHICKEN2) |
5158 ILK_ELPIN_409_SELECT);
5159
ecdb4eb7 5160 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5161 I915_WRITE(_3D_CHICKEN,
5162 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5163
ecdb4eb7 5164 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5165 if (IS_SNB_GT1(dev))
5166 I915_WRITE(GEN6_GT_MODE,
5167 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5168
4e04632e
AG		 5169 /* WaDisable_RenderCache_OperationalFlush:snb */
5170 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5171
8d85d272
VS		 5172 /*
5173 * BSpec recoomends 8x4 when MSAA is used,
5174 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5175 *
5176 * Note that PS/WM thread counts depend on the WIZ hashing
5177 * disable bit, which we don't touch here, but it's good
5178 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5179 */
5180 I915_WRITE(GEN6_GT_MODE,
5181 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5182
017636cc 5183 ilk_init_lp_watermarks(dev);
6f1d69b0 5184
6f1d69b0 5185 I915_WRITE(CACHE_MODE_0,
50743298 5186 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5187
5188 I915_WRITE(GEN6_UCGCTL1,
5189 I915_READ(GEN6_UCGCTL1) |
5190 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5191 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5192
5193 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5194 * gating disable must be set. Failure to set it results in
5195 * flickering pixels due to Z write ordering failures after
5196 * some amount of runtime in the Mesa "fire" demo, and Unigine
5197 * Sanctuary and Tropics, and apparently anything else with
5198 * alpha test or pixel discard.
5199 *
5200 * According to the spec, bit 11 (RCCUNIT) must also be set,
5201 * but we didn't debug actual testcases to find it out.
0f846f81 5202 *
ef59318c
VS		 5203 * WaDisableRCCUnitClockGating:snb
5204 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5205 */
5206 I915_WRITE(GEN6_UCGCTL2,
5207 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5208 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5209
5eb146dd 5210 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5211 I915_WRITE(_3D_CHICKEN3,
5212 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5213
e927ecde
VS		 5214 /*
5215 * Bspec says:
5216 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5217 * 3DSTATE_SF number of SF output attributes is more than 16."
5218 */
5219 I915_WRITE(_3D_CHICKEN3,
5220 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5221
6f1d69b0
ED		 5222 /*
5223 * According to the spec the following bits should be
5224 * set in order to enable memory self-refresh and fbc:
5225 * The bit21 and bit22 of 0x42000
5226 * The bit21 and bit22 of 0x42004
5227 * The bit5 and bit7 of 0x42020
5228 * The bit14 of 0x70180
5229 * The bit14 of 0x71180
4bb35334
DL		 5230 *
5231 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5232 */
5233 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5234 I915_READ(ILK_DISPLAY_CHICKEN1) |
5235 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5236 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5237 I915_READ(ILK_DISPLAY_CHICKEN2) |
5238 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5239 I915_WRITE(ILK_DSPCLK_GATE_D,
5240 I915_READ(ILK_DSPCLK_GATE_D) |
5241 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5242 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5243
0e088b8f 5244 g4x_disable_trickle_feed(dev);
f8f2ac9a 5245
3107bd48 5246 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5247
5248 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5249}
5250
5251static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5252{
5253 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5254
3aad9059 5255 /*
46680e0a 5256 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5257 *
5258 * This actually overrides the dispatch
5259 * mode for all thread types.
5260 */
6f1d69b0
ED		 5261 reg &= ~GEN7_FF_SCHED_MASK;
5262 reg |= GEN7_FF_TS_SCHED_HW;
5263 reg |= GEN7_FF_VS_SCHED_HW;
5264 reg |= GEN7_FF_DS_SCHED_HW;
5265
5266 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5267}
5268
17a303ec
PZ		 5269static void lpt_init_clock_gating(struct drm_device *dev)
5270{
5271 struct drm_i915_private *dev_priv = dev->dev_private;
5272
5273 /*
5274 * TODO: this bit should only be enabled when really needed, then
5275 * disabled when not needed anymore in order to save power.
5276 */
5277 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5278 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5279 I915_READ(SOUTH_DSPCLK_GATE_D) |
5280 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5281
5282 /* WADPOClockGatingDisable:hsw */
5283 I915_WRITE(_TRANSA_CHICKEN1,
5284 I915_READ(_TRANSA_CHICKEN1) |
5285 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5286}
5287
7d708ee4
ID		 5288static void lpt_suspend_hw(struct drm_device *dev)
5289{
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291
5292 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5293 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5294
5295 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5296 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5297 }
5298}
5299
1020a5c2
BW		 5300static void gen8_init_clock_gating(struct drm_device *dev)
5301{
5302 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5303 enum pipe pipe;
1020a5c2
BW		 5304
5305 I915_WRITE(WM3_LP_ILK, 0);
5306 I915_WRITE(WM2_LP_ILK, 0);
5307 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5308
5309 /* FIXME(BDW): Check all the w/a, some might only apply to
5310 * pre-production hw. */
5311
c8966e10
KG		 5312 /* WaDisablePartialInstShootdown:bdw */
5313 I915_WRITE(GEN8_ROW_CHICKEN,
5314 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5315
1411e6a5
KG		 5316 /* WaDisableThreadStallDopClockGating:bdw */
5317 /* FIXME: Unclear whether we really need this on production bdw. */
5318 I915_WRITE(GEN8_ROW_CHICKEN,
5319 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5320
4167e32c
DL		 5321 /*
5322 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5323 * pre-production hardware
5324 */
fd392b60
BW		 5325 I915_WRITE(HALF_SLICE_CHICKEN3,
5326 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5327 I915_WRITE(HALF_SLICE_CHICKEN3,
5328 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5329 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5330
7f88da0c
BW		 5331 I915_WRITE(_3D_CHICKEN3,
5332 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5333
a75f3628
BW		 5334 I915_WRITE(COMMON_SLICE_CHICKEN2,
5335 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5336
4c2e7a5f
BW		 5337 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5338 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5339
242a4018
BW		 5340 /* WaDisableDopClockGating:bdw May not be needed for production */
5341 I915_WRITE(GEN7_ROW_CHICKEN2,
5342 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5343
ab57fff1 5344 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5345 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5346
ab57fff1 5347 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5348 I915_WRITE(CHICKEN_PAR1_1,
5349 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5350
ab57fff1 5351 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5352 for_each_pipe(pipe) {
5353 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5354 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5355 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5356 }
63801f21
BW		 5357
5358 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5359 * workaround for for a possible hang in the unlikely event a TLB
5360 * invalidation occurs during a PSD flush.
5361 */
5362 I915_WRITE(HDC_CHICKEN0,
5363 I915_READ(HDC_CHICKEN0) |
5364 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5365
5366 /* WaVSRefCountFullforceMissDisable:bdw */
5367 /* WaDSRefCountFullforceMissDisable:bdw */
5368 I915_WRITE(GEN7_FF_THREAD_MODE,
5369 I915_READ(GEN7_FF_THREAD_MODE) &
5370 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5371
5372 /*
5373 * BSpec recommends 8x4 when MSAA is used,
5374 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5375 *
5376 * Note that PS/WM thread counts depend on the WIZ hashing
5377 * disable bit, which we don't touch here, but it's good
5378 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5379 */
5380 I915_WRITE(GEN7_GT_MODE,
5381 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5382
5383 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5384 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5385
5386 /* WaDisableSDEUnitClockGating:bdw */
5387 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5388 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5389
5390 /* Wa4x4STCOptimizationDisable:bdw */
5391 I915_WRITE(CACHE_MODE_1,
5392 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5393}
5394
cad2a2d7
ED		 5395static void haswell_init_clock_gating(struct drm_device *dev)
5396{
5397 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5398
017636cc 5399 ilk_init_lp_watermarks(dev);
cad2a2d7 5400
f3fc4884
FJ		 5401 /* L3 caching of data atomics doesn't work -- disable it. */
5402 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5403 I915_WRITE(HSW_ROW_CHICKEN3,
5404 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5405
ecdb4eb7 5406 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5407 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5408 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5409 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5410
e36ea7ff
VS		 5411 /* WaVSRefCountFullforceMissDisable:hsw */
5412 I915_WRITE(GEN7_FF_THREAD_MODE,
5413 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5414
4e04632e
AG		 5415 /* WaDisable_RenderCache_OperationalFlush:hsw */
5416 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5417
fe27c606
CW		 5418 /* enable HiZ Raw Stall Optimization */
5419 I915_WRITE(CACHE_MODE_0_GEN7,
5420 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5421
ecdb4eb7 5422 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5423 I915_WRITE(CACHE_MODE_1,
5424 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5425
a12c4967
VS		 5426 /*
5427 * BSpec recommends 8x4 when MSAA is used,
5428 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5429 *
5430 * Note that PS/WM thread counts depend on the WIZ hashing
5431 * disable bit, which we don't touch here, but it's good
5432 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5433 */
5434 I915_WRITE(GEN7_GT_MODE,
5435 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5436
ecdb4eb7 5437 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5438 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5439
90a88643
PZ		 5440 /* WaRsPkgCStateDisplayPMReq:hsw */
5441 I915_WRITE(CHICKEN_PAR1_1,
5442 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5443
17a303ec 5444 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5445}
5446
1fa61106 5447static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5448{
5449 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5450 uint32_t snpcr;
6f1d69b0 5451
017636cc 5452 ilk_init_lp_watermarks(dev);
6f1d69b0 5453
231e54f6 5454 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5455
ecdb4eb7 5456 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5457 I915_WRITE(_3D_CHICKEN3,
5458 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5459
ecdb4eb7 5460 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5461 I915_WRITE(IVB_CHICKEN3,
5462 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5463 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5464
ecdb4eb7 5465 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5466 if (IS_IVB_GT1(dev))
5467 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5468 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5469
4e04632e
AG		 5470 /* WaDisable_RenderCache_OperationalFlush:ivb */
5471 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5472
ecdb4eb7 5473 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5474 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5475 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5476
ecdb4eb7 5477 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5478 I915_WRITE(GEN7_L3CNTLREG1,
5479 GEN7_WA_FOR_GEN7_L3_CONTROL);
5480 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5481 GEN7_WA_L3_CHICKEN_MODE);
5482 if (IS_IVB_GT1(dev))
5483 I915_WRITE(GEN7_ROW_CHICKEN2,
5484 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5485 else {
5486 /* must write both registers */
5487 I915_WRITE(GEN7_ROW_CHICKEN2,
5488 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5489 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5490 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5491 }
6f1d69b0 5492
ecdb4eb7 5493 /* WaForceL3Serialization:ivb */
61939d97
JB		 5494 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5495 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5496
1b80a19a 5497 /*
0f846f81 5498 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5499 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5500 */
5501 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5502 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5503
ecdb4eb7 5504 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5505 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5506 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5507 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5508
0e088b8f 5509 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5510
5511 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5512
22721343
CW		 5513 if (0) { /* causes HiZ corruption on ivb:gt1 */
5514 /* enable HiZ Raw Stall Optimization */
5515 I915_WRITE(CACHE_MODE_0_GEN7,
5516 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5517 }
116f2b6d 5518
ecdb4eb7 5519 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5520 I915_WRITE(CACHE_MODE_1,
5521 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5522
a607c1a4
VS		 5523 /*
5524 * BSpec recommends 8x4 when MSAA is used,
5525 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5526 *
5527 * Note that PS/WM thread counts depend on the WIZ hashing
5528 * disable bit, which we don't touch here, but it's good
5529 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5530 */
5531 I915_WRITE(GEN7_GT_MODE,
5532 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5533
20848223
BW		 5534 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5535 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5536 snpcr |= GEN6_MBC_SNPCR_MED;
5537 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5538
ab5c608b
BW		 5539 if (!HAS_PCH_NOP(dev))
5540 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5541
5542 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5543}
5544
1fa61106 5545static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5546{
5547 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5548 u32 val;
5549
5550 mutex_lock(&dev_priv->rps.hw_lock);
5551 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5552 mutex_unlock(&dev_priv->rps.hw_lock);
5553 switch ((val >> 6) & 3) {
5554 case 0:
f64a28a7 5555 case 1:
f6d51948 5556 dev_priv->mem_freq = 800;
85b1d7b3 5557 break;
f64a28a7 5558 case 2:
f6d51948 5559 dev_priv->mem_freq = 1066;
85b1d7b3 5560 break;
f64a28a7 5561 case 3:
2325991e 5562 dev_priv->mem_freq = 1333;
f64a28a7 5563 break;
85b1d7b3
JB		 5564 }
5565 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5566
d60c4473
ID		 5567 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5568 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5569 dev_priv->vlv_cdclk_freq);
5570
d7fe0cc0 5571 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5572
ecdb4eb7 5573 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5574 I915_WRITE(_3D_CHICKEN3,
5575 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5576
ecdb4eb7 5577 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5578 I915_WRITE(IVB_CHICKEN3,
5579 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5580 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5581
fad7d36e 5582 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5583 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5584 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5585 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5586 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5587
4e04632e
AG		 5588 /* WaDisable_RenderCache_OperationalFlush:vlv */
5589 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5590
ecdb4eb7 5591 /* WaForceL3Serialization:vlv */
61939d97
JB		 5592 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5593 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5594
ecdb4eb7 5595 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5596 I915_WRITE(GEN7_ROW_CHICKEN2,
5597 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5598
ecdb4eb7 5599 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5600 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5601 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5602 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5603
46680e0a
VS		 5604 gen7_setup_fixed_func_scheduler(dev_priv);
5605
3c0edaeb 5606 /*
0f846f81 5607 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5608 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5609 */
5610 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5611 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5612
c98f5062
AG		 5613 /* WaDisableL3Bank2xClockGate:vlv
5614 * Disabling L3 clock gating- MMIO 940c[25] = 1
5615 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5616 I915_WRITE(GEN7_UCGCTL4,
5617 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5618
e0d8d59b 5619 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5620
afd58e79
VS		 5621 /*
5622 * BSpec says this must be set, even though
5623 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5624 */
6b26c86d
DV		 5625 I915_WRITE(CACHE_MODE_1,
5626 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5627
031994ee
VS		 5628 /*
5629 * WaIncreaseL3CreditsForVLVB0:vlv
5630 * This is the hardware default actually.
5631 */
5632 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5633
2d809570 5634 /*
ecdb4eb7 5635 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5636 * Disable clock gating on th GCFG unit to prevent a delay
5637 * in the reporting of vblank events.
5638 */
7a0d1eed 5639 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5640}
5641
a4565da8
VS		 5642static void cherryview_init_clock_gating(struct drm_device *dev)
5643{
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645
5646 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5647
5648 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5649
5650 /* WaDisablePartialInstShootdown:chv */
5651 I915_WRITE(GEN8_ROW_CHICKEN,
5652 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5653
5654 /* WaDisableThreadStallDopClockGating:chv */
5655 I915_WRITE(GEN8_ROW_CHICKEN,
5656 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
232ce337
VS		 5657
5658 /* WaVSRefCountFullforceMissDisable:chv */
5659 /* WaDSRefCountFullforceMissDisable:chv */
5660 I915_WRITE(GEN7_FF_THREAD_MODE,
5661 I915_READ(GEN7_FF_THREAD_MODE) &
5662 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5663
5664 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5665 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5666 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5667
5668 /* WaDisableCSUnitClockGating:chv */
5669 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5670 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5671
5672 /* WaDisableSDEUnitClockGating:chv */
5673 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5674 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7
RB		 5675
5676 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5677 I915_WRITE(HALF_SLICE_CHICKEN3,
5678 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
e4443e45
VS		 5679
5680 /* WaDisableGunitClockGating:chv (pre-production hw) */
5681 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5682 GINT_DIS);
5683
5684 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5685 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5686 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5687
5688 /* WaDisableDopClockGating:chv (pre-production hw) */
5689 I915_WRITE(GEN7_ROW_CHICKEN2,
5690 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5691 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5692 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5693}
5694
1fa61106 5695static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5696{
5697 struct drm_i915_private *dev_priv = dev->dev_private;
5698 uint32_t dspclk_gate;
5699
5700 I915_WRITE(RENCLK_GATE_D1, 0);
5701 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5702 GS_UNIT_CLOCK_GATE_DISABLE |
5703 CL_UNIT_CLOCK_GATE_DISABLE);
5704 I915_WRITE(RAMCLK_GATE_D, 0);
5705 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5706 OVRUNIT_CLOCK_GATE_DISABLE |
5707 OVCUNIT_CLOCK_GATE_DISABLE;
5708 if (IS_GM45(dev))
5709 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5710 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5711
5712 /* WaDisableRenderCachePipelinedFlush */
5713 I915_WRITE(CACHE_MODE_0,
5714 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5715
4e04632e
AG		 5716 /* WaDisable_RenderCache_OperationalFlush:g4x */
5717 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5718
0e088b8f 5719 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5720}
5721
1fa61106 5722static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5723{
5724 struct drm_i915_private *dev_priv = dev->dev_private;
5725
5726 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5727 I915_WRITE(RENCLK_GATE_D2, 0);
5728 I915_WRITE(DSPCLK_GATE_D, 0);
5729 I915_WRITE(RAMCLK_GATE_D, 0);
5730 I915_WRITE16(DEUC, 0);
20f94967
VS		 5731 I915_WRITE(MI_ARB_STATE,
5732 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5733
5734 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5735 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5736}
5737
1fa61106 5738static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5739{
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741
5742 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5743 I965_RCC_CLOCK_GATE_DISABLE |
5744 I965_RCPB_CLOCK_GATE_DISABLE |
5745 I965_ISC_CLOCK_GATE_DISABLE |
5746 I965_FBC_CLOCK_GATE_DISABLE);
5747 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5748 I915_WRITE(MI_ARB_STATE,
5749 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5750
5751 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5752 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5753}
5754
1fa61106 5755static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5756{
5757 struct drm_i915_private *dev_priv = dev->dev_private;
5758 u32 dstate = I915_READ(D_STATE);
5759
5760 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5761 DSTATE_DOT_CLOCK_GATING;
5762 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5763
5764 if (IS_PINEVIEW(dev))
5765 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5766
5767 /* IIR "flip pending" means done if this bit is set */
5768 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 5769
5770 /* interrupts should cause a wake up from C3 */
3299254f 5771 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 5772
5773 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5774 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6f1d69b0
ED		 5775}
5776
1fa61106 5777static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5778{
5779 struct drm_i915_private *dev_priv = dev->dev_private;
5780
5781 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 5782
5783 /* interrupts should cause a wake up from C3 */
5784 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5785 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6f1d69b0
ED		 5786}
5787
1fa61106 5788static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5789{
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791
5792 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5793}
5794
6f1d69b0
ED		 5795void intel_init_clock_gating(struct drm_device *dev)
5796{
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798
5799 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5800}
5801
7d708ee4
ID		 5802void intel_suspend_hw(struct drm_device *dev)
5803{
5804 if (HAS_PCH_LPT(dev))
5805 lpt_suspend_hw(dev);
5806}
5807
c1ca727f
ID		 5808#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5809 for (i = 0; \
5810 i < (power_domains)->power_well_count && \
5811 ((power_well) = &(power_domains)->power_wells[i]); \
5812 i++) \
5813 if ((power_well)->domains & (domain_mask))
5814
5815#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5816 for (i = (power_domains)->power_well_count - 1; \
5817 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5818 i--) \
5819 if ((power_well)->domains & (domain_mask))
5820
15d199ea
PZ		 5821/**
5822 * We should only use the power well if we explicitly asked the hardware to
5823 * enable it, so check if it's enabled and also check if we've requested it to
5824 * be enabled.
5825 */
da7e29bd 5826static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5827 struct i915_power_well *power_well)
5828{
c1ca727f
ID		 5829 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5830 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5831}
5832
da7e29bd 5833bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536
ID		 5834 enum intel_display_power_domain domain)
5835{
ddf9c536 5836 struct i915_power_domains *power_domains;
b8c000d9
ID		 5837 struct i915_power_well *power_well;
5838 bool is_enabled;
5839 int i;
5840
5841 if (dev_priv->pm.suspended)
5842 return false;
ddf9c536
ID		 5843
5844 power_domains = &dev_priv->power_domains;
b8c000d9
ID		 5845 is_enabled = true;
5846 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5847 if (power_well->always_on)
5848 continue;
ddf9c536 5849
b8c000d9
ID		 5850 if (!power_well->count) {
5851 is_enabled = false;
5852 break;
5853 }
5854 }
5855 return is_enabled;
ddf9c536
ID		 5856}
5857
da7e29bd 5858bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5859 enum intel_display_power_domain domain)
15d199ea 5860{
c1ca727f
ID		 5861 struct i915_power_domains *power_domains;
5862 struct i915_power_well *power_well;
5863 bool is_enabled;
5864 int i;
15d199ea 5865
882244a3
PZ		 5866 if (dev_priv->pm.suspended)
5867 return false;
5868
c1ca727f
ID		 5869 power_domains = &dev_priv->power_domains;
5870
5871 is_enabled = true;
5872
5873 mutex_lock(&power_domains->lock);
5874 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5875 if (power_well->always_on)
5876 continue;
5877
c6cb582e 5878 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
c1ca727f
ID		 5879 is_enabled = false;
5880 break;
5881 }
5882 }
5883 mutex_unlock(&power_domains->lock);
5884
5885 return is_enabled;
15d199ea
PZ		 5886}
5887
93c73e8c
ID		 5888/*
5889 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5890 * when not needed anymore. We have 4 registers that can request the power well
5891 * to be enabled, and it will only be disabled if none of the registers is
5892 * requesting it to be enabled.
5893 */
d5e8fdc8
PZ		 5894static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5895{
5896 struct drm_device *dev = dev_priv->dev;
5897 unsigned long irqflags;
5898
f9dcb0df
PZ		 5899 /*
5900 * After we re-enable the power well, if we touch VGA register 0x3d5
5901 * we'll get unclaimed register interrupts. This stops after we write
5902 * anything to the VGA MSR register. The vgacon module uses this
5903 * register all the time, so if we unbind our driver and, as a
5904 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5905 * console_unlock(). So make here we touch the VGA MSR register, making
5906 * sure vgacon can keep working normally without triggering interrupts
5907 * and error messages.
5908 */
5909 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5910 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5911 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5912
d5e8fdc8
PZ		 5913 if (IS_BROADWELL(dev)) {
5914 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5915 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5916 dev_priv->de_irq_mask[PIPE_B]);
5917 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5918 ~dev_priv->de_irq_mask[PIPE_B] |
5919 GEN8_PIPE_VBLANK);
5920 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5921 dev_priv->de_irq_mask[PIPE_C]);
5922 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5923 ~dev_priv->de_irq_mask[PIPE_C] |
5924 GEN8_PIPE_VBLANK);
5925 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5926 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5927 }
5928}
5929
da7e29bd 5930static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5931 struct i915_power_well *power_well, bool enable)
d0d3e513 5932{
fa42e23c
PZ		 5933 bool is_enabled, enable_requested;
5934 uint32_t tmp;
d0d3e513 5935
fa42e23c 5936 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5937 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5938 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5939
fa42e23c
PZ		 5940 if (enable) {
5941 if (!enable_requested)
6aedd1f5
PZ		 5942 I915_WRITE(HSW_PWR_WELL_DRIVER,
5943 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5944
fa42e23c
PZ		 5945 if (!is_enabled) {
5946 DRM_DEBUG_KMS("Enabling power well\n");
5947 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5948 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5949 DRM_ERROR("Timeout enabling power well\n");
5950 }
596cc11e 5951
d5e8fdc8 5952 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5953 } else {
5954 if (enable_requested) {
5955 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5956 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5957 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5958 }
5959 }
fa42e23c 5960}
d0d3e513 5961
c6cb582e
ID		 5962static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5963 struct i915_power_well *power_well)
5964{
5965 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5966
5967 /*
5968 * We're taking over the BIOS, so clear any requests made by it since
5969 * the driver is in charge now.
5970 */
5971 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5972 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5973}
5974
5975static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5976 struct i915_power_well *power_well)
5977{
c6cb582e
ID		 5978 hsw_set_power_well(dev_priv, power_well, true);
5979}
5980
5981static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5982 struct i915_power_well *power_well)
5983{
5984 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 5985}
5986
a45f4466
ID		 5987static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5988 struct i915_power_well *power_well)
5989{
5990}
5991
5992static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5993 struct i915_power_well *power_well)
5994{
5995 return true;
5996}
5997
57021059
JB		 5998void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5999 enum punit_power_well power_well_id, bool enable)
77961eb9 6000{
4dfbd12c 6001 struct drm_device *dev = dev_priv->dev;
77961eb9
ID		 6002 u32 mask;
6003 u32 state;
6004 u32 ctrl;
4dfbd12c 6005 enum pipe pipe;
77961eb9 6006
f618e38d
JB		 6007 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6008 if (enable) {
6009 /*
6010 * Enable the CRI clock source so we can get at the
6011 * display and the reference clock for VGA
6012 * hotplug / manual detection.
6013 */
6014 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6015 DPLL_REFA_CLK_ENABLE_VLV |
6016 DPLL_INTEGRATED_CRI_CLK_VLV);
6017 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6018 } else {
4dfbd12c
JB		 6019 for_each_pipe(pipe)
6020 assert_pll_disabled(dev_priv, pipe);
f618e38d
JB		 6021 /* Assert common reset */
6022 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
6023 ~DPIO_CMNRST);
6024 }
b00f025c 6025 }
77961eb9
ID		 6026
6027 mask = PUNIT_PWRGT_MASK(power_well_id);
6028 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6029 PUNIT_PWRGT_PWR_GATE(power_well_id);
6030
6031 mutex_lock(&dev_priv->rps.hw_lock);
6032
6033#define COND \
6034 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6035
6036 if (COND)
6037 goto out;
6038
6039 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6040 ctrl &= ~mask;
6041 ctrl |= state;
6042 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6043
6044 if (wait_for(COND, 100))
6045 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6046 state,
6047 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6048
6049#undef COND
6050
6051out:
6052 mutex_unlock(&dev_priv->rps.hw_lock);
f618e38d
JB		 6053
6054 /*
6055 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6056 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6057 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6058 * b. The other bits such as sfr settings / modesel may all
6059 * be set to 0.
6060 *
6061 * This should only be done on init and resume from S3 with
6062 * both PLLs disabled, or we risk losing DPIO and PLL
6063 * synchronization.
6064 */
6065 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
6066 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
77961eb9
ID		 6067}
6068
57021059
JB		 6069static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6070 struct i915_power_well *power_well, bool enable)
6071{
6072 enum punit_power_well power_well_id = power_well->data;
6073
6074 __vlv_set_power_well(dev_priv, power_well_id, enable);
77961eb9
ID		 6075}
6076
6077static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6078 struct i915_power_well *power_well)
6079{
6080 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6081}
6082
6083static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6084 struct i915_power_well *power_well)
6085{
6086 vlv_set_power_well(dev_priv, power_well, true);
6087}
6088
6089static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6090 struct i915_power_well *power_well)
6091{
6092 vlv_set_power_well(dev_priv, power_well, false);
6093}
6094
6095static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6096 struct i915_power_well *power_well)
6097{
6098 int power_well_id = power_well->data;
6099 bool enabled = false;
6100 u32 mask;
6101 u32 state;
6102 u32 ctrl;
6103
6104 mask = PUNIT_PWRGT_MASK(power_well_id);
6105 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6106
6107 mutex_lock(&dev_priv->rps.hw_lock);
6108
6109 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6110 /*
6111 * We only ever set the power-on and power-gate states, anything
6112 * else is unexpected.
6113 */
6114 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6115 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6116 if (state == ctrl)
6117 enabled = true;
6118
6119 /*
6120 * A transient state at this point would mean some unexpected party
6121 * is poking at the power controls too.
6122 */
6123 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6124 WARN_ON(ctrl != state);
6125
6126 mutex_unlock(&dev_priv->rps.hw_lock);
6127
6128 return enabled;
6129}
6130
6131static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6132 struct i915_power_well *power_well)
6133{
6134 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6135
6136 vlv_set_power_well(dev_priv, power_well, true);
6137
6138 spin_lock_irq(&dev_priv->irq_lock);
6139 valleyview_enable_display_irqs(dev_priv);
6140 spin_unlock_irq(&dev_priv->irq_lock);
6141
6142 /*
0d116a29
ID		 6143 * During driver initialization/resume we can avoid restoring the
6144 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6145 */
0d116a29
ID		 6146 if (dev_priv->power_domains.initializing)
6147 return;
6148
6149 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6150
6151 i915_redisable_vga_power_on(dev_priv->dev);
6152}
6153
6154static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6155 struct i915_power_well *power_well)
6156{
77961eb9
ID		 6157 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6158
6159 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6160 valleyview_disable_display_irqs(dev_priv);
6161 spin_unlock_irq(&dev_priv->irq_lock);
6162
77961eb9
ID		 6163 vlv_set_power_well(dev_priv, power_well, false);
6164}
6165
25eaa003
ID		 6166static void check_power_well_state(struct drm_i915_private *dev_priv,
6167 struct i915_power_well *power_well)
6168{
6169 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6170
6171 if (power_well->always_on || !i915.disable_power_well) {
6172 if (!enabled)
6173 goto mismatch;
6174
6175 return;
6176 }
6177
6178 if (enabled != (power_well->count > 0))
6179 goto mismatch;
6180
6181 return;
6182
6183mismatch:
6184 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6185 power_well->name, power_well->always_on, enabled,
6186 power_well->count, i915.disable_power_well);
6187}
6188
da7e29bd 6189void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6190 enum intel_display_power_domain domain)
6191{
83c00f55 6192 struct i915_power_domains *power_domains;
c1ca727f
ID		 6193 struct i915_power_well *power_well;
6194 int i;
6765625e 6195
9e6ea71a
PZ		 6196 intel_runtime_pm_get(dev_priv);
6197
83c00f55
ID		 6198 power_domains = &dev_priv->power_domains;
6199
6200 mutex_lock(&power_domains->lock);
1da51581 6201
25eaa003
ID		 6202 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6203 if (!power_well->count++) {
6204 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6205 power_well->ops->enable(dev_priv, power_well);
25eaa003
ID		 6206 }
6207
6208 check_power_well_state(dev_priv, power_well);
6209 }
1da51581 6210
ddf9c536
ID		 6211 power_domains->domain_use_count[domain]++;
6212
83c00f55 6213 mutex_unlock(&power_domains->lock);
6765625e
VS		 6214}
6215
da7e29bd 6216void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6217 enum intel_display_power_domain domain)
6218{
83c00f55 6219 struct i915_power_domains *power_domains;
c1ca727f
ID		 6220 struct i915_power_well *power_well;
6221 int i;
6765625e 6222
83c00f55
ID		 6223 power_domains = &dev_priv->power_domains;
6224
6225 mutex_lock(&power_domains->lock);
1da51581 6226
1da51581
ID		 6227 WARN_ON(!power_domains->domain_use_count[domain]);
6228 power_domains->domain_use_count[domain]--;
ddf9c536 6229
70bf407c
ID		 6230 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6231 WARN_ON(!power_well->count);
6232
25eaa003
ID		 6233 if (!--power_well->count && i915.disable_power_well) {
6234 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
c6cb582e 6235 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6236 }
6237
6238 check_power_well_state(dev_priv, power_well);
70bf407c 6239 }
1da51581 6240
83c00f55 6241 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6242
6243 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6244}
6245
83c00f55 6246static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6247
6248/* Display audio driver power well request */
6249void i915_request_power_well(void)
6250{
b4ed4484
ID		 6251 struct drm_i915_private *dev_priv;
6252
a38911a3
WX		 6253 if (WARN_ON(!hsw_pwr))
6254 return;
6255
b4ed4484
ID		 6256 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6257 power_domains);
da7e29bd 6258 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 6259}
6260EXPORT_SYMBOL_GPL(i915_request_power_well);
6261
6262/* Display audio driver power well release */
6263void i915_release_power_well(void)
6264{
b4ed4484
ID		 6265 struct drm_i915_private *dev_priv;
6266
a38911a3
WX		 6267 if (WARN_ON(!hsw_pwr))
6268 return;
6269
b4ed4484
ID		 6270 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6271 power_domains);
da7e29bd 6272 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 6273}
6274EXPORT_SYMBOL_GPL(i915_release_power_well);
6275
efcad917
ID		 6276#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6277
6278#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6279 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6280 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6281 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6282 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6283 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6284 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6285 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6286 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6287 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6288 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6289 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 6290 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6291#define HSW_DISPLAY_POWER_DOMAINS ( \
6292 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6293 BIT(POWER_DOMAIN_INIT))
6294
6295#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6296 HSW_ALWAYS_ON_POWER_DOMAINS | \
6297 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6298#define BDW_DISPLAY_POWER_DOMAINS ( \
6299 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6300 BIT(POWER_DOMAIN_INIT))
6301
77961eb9
ID		 6302#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6303#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6304
6305#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6306 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6307 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6308 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6309 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6310 BIT(POWER_DOMAIN_PORT_CRT) | \
6311 BIT(POWER_DOMAIN_INIT))
6312
6313#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6314 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6315 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6316 BIT(POWER_DOMAIN_INIT))
6317
6318#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6319 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6320 BIT(POWER_DOMAIN_INIT))
6321
6322#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6323 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6324 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6325 BIT(POWER_DOMAIN_INIT))
6326
6327#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6328 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6329 BIT(POWER_DOMAIN_INIT))
6330
a45f4466
ID		 6331static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6332 .sync_hw = i9xx_always_on_power_well_noop,
6333 .enable = i9xx_always_on_power_well_noop,
6334 .disable = i9xx_always_on_power_well_noop,
6335 .is_enabled = i9xx_always_on_power_well_enabled,
6336};
c6cb582e 6337
1c2256df
ID		 6338static struct i915_power_well i9xx_always_on_power_well[] = {
6339 {
6340 .name = "always-on",
6341 .always_on = 1,
6342 .domains = POWER_DOMAIN_MASK,
c6cb582e 6343 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6344 },
6345};
6346
c6cb582e
ID		 6347static const struct i915_power_well_ops hsw_power_well_ops = {
6348 .sync_hw = hsw_power_well_sync_hw,
6349 .enable = hsw_power_well_enable,
6350 .disable = hsw_power_well_disable,
6351 .is_enabled = hsw_power_well_enabled,
6352};
6353
c1ca727f 6354static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6355 {
6356 .name = "always-on",
6357 .always_on = 1,
6358 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6359 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6360 },
c1ca727f
ID		 6361 {
6362 .name = "display",
efcad917 6363 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6364 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6365 },
6366};
6367
6368static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6369 {
6370 .name = "always-on",
6371 .always_on = 1,
6372 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6373 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6374 },
c1ca727f
ID		 6375 {
6376 .name = "display",
efcad917 6377 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6378 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6379 },
6380};
6381
77961eb9
ID		 6382static const struct i915_power_well_ops vlv_display_power_well_ops = {
6383 .sync_hw = vlv_power_well_sync_hw,
6384 .enable = vlv_display_power_well_enable,
6385 .disable = vlv_display_power_well_disable,
6386 .is_enabled = vlv_power_well_enabled,
6387};
6388
6389static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6390 .sync_hw = vlv_power_well_sync_hw,
6391 .enable = vlv_power_well_enable,
6392 .disable = vlv_power_well_disable,
6393 .is_enabled = vlv_power_well_enabled,
6394};
6395
6396static struct i915_power_well vlv_power_wells[] = {
6397 {
6398 .name = "always-on",
6399 .always_on = 1,
6400 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6401 .ops = &i9xx_always_on_power_well_ops,
6402 },
6403 {
6404 .name = "display",
6405 .domains = VLV_DISPLAY_POWER_DOMAINS,
6406 .data = PUNIT_POWER_WELL_DISP2D,
6407 .ops = &vlv_display_power_well_ops,
6408 },
77961eb9
ID		 6409 {
6410 .name = "dpio-tx-b-01",
6411 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6412 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6413 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6414 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6415 .ops = &vlv_dpio_power_well_ops,
6416 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6417 },
6418 {
6419 .name = "dpio-tx-b-23",
6420 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6421 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6422 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6423 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6424 .ops = &vlv_dpio_power_well_ops,
6425 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6426 },
6427 {
6428 .name = "dpio-tx-c-01",
6429 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6430 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6431 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6432 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6433 .ops = &vlv_dpio_power_well_ops,
6434 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6435 },
6436 {
6437 .name = "dpio-tx-c-23",
6438 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6439 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6440 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6441 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6442 .ops = &vlv_dpio_power_well_ops,
6443 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6444 },
f099a3c6
JB		 6445 {
6446 .name = "dpio-common",
6447 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6448 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6449 .ops = &vlv_dpio_power_well_ops,
6450 },
77961eb9
ID		 6451};
6452
c1ca727f
ID		 6453#define set_power_wells(power_domains, __power_wells) ({ \
6454 (power_domains)->power_wells = (__power_wells); \
6455 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6456})
6457
da7e29bd 6458int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6459{
83c00f55 6460 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6461
83c00f55 6462 mutex_init(&power_domains->lock);
a38911a3 6463
c1ca727f
ID		 6464 /*
6465 * The enabling order will be from lower to higher indexed wells,
6466 * the disabling order is reversed.
6467 */
da7e29bd 6468 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6469 set_power_wells(power_domains, hsw_power_wells);
6470 hsw_pwr = power_domains;
da7e29bd 6471 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6472 set_power_wells(power_domains, bdw_power_wells);
6473 hsw_pwr = power_domains;
77961eb9
ID		 6474 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6475 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6476 } else {
1c2256df 6477 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6478 }
a38911a3
WX		 6479
6480 return 0;
6481}
6482
da7e29bd 6483void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6484{
6485 hsw_pwr = NULL;
6486}
6487
da7e29bd 6488static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6489{
83c00f55
ID		 6490 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6491 struct i915_power_well *power_well;
c1ca727f 6492 int i;
9cdb826c 6493
83c00f55 6494 mutex_lock(&power_domains->lock);
a45f4466
ID		 6495 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6496 power_well->ops->sync_hw(dev_priv, power_well);
83c00f55 6497 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6498}
6499
da7e29bd 6500void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6501{
0d116a29
ID		 6502 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6503
6504 power_domains->initializing = true;
fa42e23c 6505 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6506 intel_display_set_init_power(dev_priv, true);
6507 intel_power_domains_resume(dev_priv);
0d116a29 6508 power_domains->initializing = false;
d0d3e513
ED		 6509}
6510
c67a470b
PZ		 6511void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6512{
d361ae26 6513 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6514}
6515
6516void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6517{
d361ae26 6518 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6519}
6520
8a187455
PZ		 6521void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6522{
6523 struct drm_device *dev = dev_priv->dev;
6524 struct device *device = &dev->pdev->dev;
6525
6526 if (!HAS_RUNTIME_PM(dev))
6527 return;
6528
6529 pm_runtime_get_sync(device);
6530 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6531}
6532
c6df39b5
ID		 6533void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6534{
6535 struct drm_device *dev = dev_priv->dev;
6536 struct device *device = &dev->pdev->dev;
6537
6538 if (!HAS_RUNTIME_PM(dev))
6539 return;
6540
6541 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6542 pm_runtime_get_noresume(device);
6543}
6544
8a187455
PZ		 6545void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6546{
6547 struct drm_device *dev = dev_priv->dev;
6548 struct device *device = &dev->pdev->dev;
6549
6550 if (!HAS_RUNTIME_PM(dev))
6551 return;
6552
6553 pm_runtime_mark_last_busy(device);
6554 pm_runtime_put_autosuspend(device);
6555}
6556
6557void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6558{
6559 struct drm_device *dev = dev_priv->dev;
6560 struct device *device = &dev->pdev->dev;
6561
8a187455
PZ		 6562 if (!HAS_RUNTIME_PM(dev))
6563 return;
6564
6565 pm_runtime_set_active(device);
6566
aeab0b5a
ID		 6567 /*
6568 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6569 * requirement.
6570 */
6571 if (!intel_enable_rc6(dev)) {
6572 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6573 return;
6574 }
6575
8a187455
PZ		 6576 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6577 pm_runtime_mark_last_busy(device);
6578 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 6579
6580 pm_runtime_put_autosuspend(device);
8a187455
PZ		 6581}
6582
6583void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6584{
6585 struct drm_device *dev = dev_priv->dev;
6586 struct device *device = &dev->pdev->dev;
6587
6588 if (!HAS_RUNTIME_PM(dev))
6589 return;
6590
aeab0b5a
ID		 6591 if (!intel_enable_rc6(dev))
6592 return;
6593
8a187455
PZ		 6594 /* Make sure we're not suspended first. */
6595 pm_runtime_get_sync(device);
6596 pm_runtime_disable(device);
6597}
6598
1fa61106
ED		 6599/* Set up chip specific power management-related functions */
6600void intel_init_pm(struct drm_device *dev)
6601{
6602 struct drm_i915_private *dev_priv = dev->dev_private;
6603
3a77c4c4 6604 if (HAS_FBC(dev)) {
40045465 6605 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6606 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6607 dev_priv->display.enable_fbc = gen7_enable_fbc;
6608 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6609 } else if (INTEL_INFO(dev)->gen >= 5) {
6610 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6611 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6612 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6613 } else if (IS_GM45(dev)) {
6614 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6615 dev_priv->display.enable_fbc = g4x_enable_fbc;
6616 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6617 } else {
1fa61106
ED		 6618 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6619 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6620 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6621
6622 /* This value was pulled out of someone's hat */
6623 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6624 }
1fa61106
ED		 6625 }
6626
c921aba8
DV		 6627 /* For cxsr */
6628 if (IS_PINEVIEW(dev))
6629 i915_pineview_get_mem_freq(dev);
6630 else if (IS_GEN5(dev))
6631 i915_ironlake_get_mem_freq(dev);
6632
1fa61106
ED		 6633 /* For FIFO watermark updates */
6634 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6635 ilk_setup_wm_latency(dev);
53615a5e 6636
bd602544
VS		 6637 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6638 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6639 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6640 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6641 dev_priv->display.update_wm = ilk_update_wm;
6642 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6643 } else {
6644 DRM_DEBUG_KMS("Failed to read display plane latency. "
6645 "Disable CxSR\n");
6646 }
6647
6648 if (IS_GEN5(dev))
1fa61106 6649 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6650 else if (IS_GEN6(dev))
1fa61106 6651 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6652 else if (IS_IVYBRIDGE(dev))
1fa61106 6653 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6654 else if (IS_HASWELL(dev))
cad2a2d7 6655 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6656 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6657 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8
VS		 6658 } else if (IS_CHERRYVIEW(dev)) {
6659 dev_priv->display.update_wm = valleyview_update_wm;
6660 dev_priv->display.init_clock_gating =
6661 cherryview_init_clock_gating;
1fa61106
ED		 6662 } else if (IS_VALLEYVIEW(dev)) {
6663 dev_priv->display.update_wm = valleyview_update_wm;
6664 dev_priv->display.init_clock_gating =
6665 valleyview_init_clock_gating;
1fa61106
ED		 6666 } else if (IS_PINEVIEW(dev)) {
6667 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6668 dev_priv->is_ddr3,
6669 dev_priv->fsb_freq,
6670 dev_priv->mem_freq)) {
6671 DRM_INFO("failed to find known CxSR latency "
6672 "(found ddr%s fsb freq %d, mem freq %d), "
6673 "disabling CxSR\n",
6674 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6675 dev_priv->fsb_freq, dev_priv->mem_freq);
6676 /* Disable CxSR and never update its watermark again */
6677 pineview_disable_cxsr(dev);
6678 dev_priv->display.update_wm = NULL;
6679 } else
6680 dev_priv->display.update_wm = pineview_update_wm;
6681 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6682 } else if (IS_G4X(dev)) {
6683 dev_priv->display.update_wm = g4x_update_wm;
6684 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6685 } else if (IS_GEN4(dev)) {
6686 dev_priv->display.update_wm = i965_update_wm;
6687 if (IS_CRESTLINE(dev))
6688 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6689 else if (IS_BROADWATER(dev))
6690 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6691 } else if (IS_GEN3(dev)) {
6692 dev_priv->display.update_wm = i9xx_update_wm;
6693 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6694 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6695 } else if (IS_GEN2(dev)) {
6696 if (INTEL_INFO(dev)->num_pipes == 1) {
6697 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6698 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6699 } else {
6700 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6701 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6702 }
6703
6704 if (IS_I85X(dev) || IS_I865G(dev))
6705 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6706 else
6707 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6708 } else {
6709 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6710 }
6711}
6712
42c0526c
BW		 6713int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6714{
4fc688ce 6715 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6716
6717 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6718 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6719 return -EAGAIN;
6720 }
6721
6722 I915_WRITE(GEN6_PCODE_DATA, *val);
6723 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6724
6725 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6726 500)) {
6727 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6728 return -ETIMEDOUT;
6729 }
6730
6731 *val = I915_READ(GEN6_PCODE_DATA);
6732 I915_WRITE(GEN6_PCODE_DATA, 0);
6733
6734 return 0;
6735}
6736
6737int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6738{
4fc688ce 6739 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6740
6741 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6742 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6743 return -EAGAIN;
6744 }
6745
6746 I915_WRITE(GEN6_PCODE_DATA, val);
6747 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6748
6749 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6750 500)) {
6751 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6752 return -ETIMEDOUT;
6753 }
6754
6755 I915_WRITE(GEN6_PCODE_DATA, 0);
6756
6757 return 0;
6758}
a0e4e199 6759
2ec3815f 6760int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6761{
07ab118b 6762 int div;
855ba3be 6763
07ab118b 6764 /* 4 x czclk */
2ec3815f 6765 switch (dev_priv->mem_freq) {
855ba3be 6766 case 800:
07ab118b 6767 div = 10;
855ba3be
JB		 6768 break;
6769 case 1066:
07ab118b 6770 div = 12;
855ba3be
JB		 6771 break;
6772 case 1333:
07ab118b 6773 div = 16;
855ba3be
JB		 6774 break;
6775 default:
6776 return -1;
6777 }
6778
2ec3815f 6779 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6780}
6781
2ec3815f 6782int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6783{
07ab118b 6784 int mul;
855ba3be 6785
07ab118b 6786 /* 4 x czclk */
2ec3815f 6787 switch (dev_priv->mem_freq) {
855ba3be 6788 case 800:
07ab118b 6789 mul = 10;
855ba3be
JB		 6790 break;
6791 case 1066:
07ab118b 6792 mul = 12;
855ba3be
JB		 6793 break;
6794 case 1333:
07ab118b 6795 mul = 16;
855ba3be
JB		 6796 break;
6797 default:
6798 return -1;
6799 }
6800
2ec3815f 6801 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6802}
6803
f742a552 6804void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6805{
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807
f742a552
DV		 6808 mutex_init(&dev_priv->rps.hw_lock);
6809
907b28c5
CW		 6810 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6811 intel_gen6_powersave_work);
5d584b2e 6812
33688d95 6813 dev_priv->pm.suspended = false;
5d584b2e 6814 dev_priv->pm.irqs_disabled = false;
907b28c5 6815}
Linux kernel - Deliverables
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