Commit | Line | Data |
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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
59 | static bool is_edp_psr(struct intel_dp *intel_dp) | |
60 | { | |
61 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; | |
62 | } | |
63 | ||
e2bbc343 RV |
64 | static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) |
65 | { | |
fac5e23e | 66 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
67 | uint32_t val; |
68 | ||
69 | val = I915_READ(VLV_PSRSTAT(pipe)) & | |
70 | VLV_EDP_PSR_CURR_STATE_MASK; | |
71 | return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
72 | (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); | |
73 | } | |
74 | ||
0bc12bcb | 75 | static void intel_psr_write_vsc(struct intel_dp *intel_dp, |
436c6d4a | 76 | const struct edp_vsc_psr *vsc_psr) |
0bc12bcb RV |
77 | { |
78 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
79 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 80 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 81 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
436c6d4a | 82 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 83 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
0bc12bcb RV |
84 | uint32_t *data = (uint32_t *) vsc_psr; |
85 | unsigned int i; | |
86 | ||
87 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
88 | the video DIP being updated before program video DIP data buffer | |
89 | registers for DIP being updated. */ | |
90 | I915_WRITE(ctl_reg, 0); | |
91 | POSTING_READ(ctl_reg); | |
92 | ||
436c6d4a VS |
93 | for (i = 0; i < sizeof(*vsc_psr); i += 4) { |
94 | I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, | |
95 | i >> 2), *data); | |
96 | data++; | |
0bc12bcb | 97 | } |
436c6d4a VS |
98 | for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) |
99 | I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, | |
100 | i >> 2), 0); | |
0bc12bcb RV |
101 | |
102 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
103 | POSTING_READ(ctl_reg); | |
104 | } | |
105 | ||
e2bbc343 RV |
106 | static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) |
107 | { | |
108 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
109 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 110 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
111 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
112 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
113 | uint32_t val; | |
114 | ||
115 | /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ | |
116 | val = I915_READ(VLV_VSCSDP(pipe)); | |
117 | val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; | |
118 | val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; | |
119 | I915_WRITE(VLV_VSCSDP(pipe), val); | |
120 | } | |
121 | ||
474d1ec4 SJ |
122 | static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) |
123 | { | |
124 | struct edp_vsc_psr psr_vsc; | |
125 | ||
126 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ | |
127 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
128 | psr_vsc.sdp_header.HB0 = 0; | |
129 | psr_vsc.sdp_header.HB1 = 0x7; | |
130 | psr_vsc.sdp_header.HB2 = 0x3; | |
131 | psr_vsc.sdp_header.HB3 = 0xb; | |
132 | intel_psr_write_vsc(intel_dp, &psr_vsc); | |
133 | } | |
134 | ||
e2bbc343 | 135 | static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) |
0bc12bcb RV |
136 | { |
137 | struct edp_vsc_psr psr_vsc; | |
138 | ||
139 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
140 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
141 | psr_vsc.sdp_header.HB0 = 0; | |
142 | psr_vsc.sdp_header.HB1 = 0x7; | |
143 | psr_vsc.sdp_header.HB2 = 0x2; | |
144 | psr_vsc.sdp_header.HB3 = 0x8; | |
145 | intel_psr_write_vsc(intel_dp, &psr_vsc); | |
146 | } | |
147 | ||
e2bbc343 RV |
148 | static void vlv_psr_enable_sink(struct intel_dp *intel_dp) |
149 | { | |
150 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
670b90d2 | 151 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
e2bbc343 RV |
152 | } |
153 | ||
f0f59a00 VS |
154 | static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, |
155 | enum port port) | |
1f38089c VS |
156 | { |
157 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
158 | return DP_AUX_CH_CTL(port); | |
159 | else | |
160 | return EDP_PSR_AUX_CTL; | |
161 | } | |
162 | ||
f0f59a00 VS |
163 | static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, |
164 | enum port port, int index) | |
1f38089c VS |
165 | { |
166 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
167 | return DP_AUX_CH_DATA(port, index); | |
168 | else | |
169 | return EDP_PSR_AUX_DATA(index); | |
170 | } | |
171 | ||
e2bbc343 | 172 | static void hsw_psr_enable_sink(struct intel_dp *intel_dp) |
0bc12bcb RV |
173 | { |
174 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
175 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 176 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 177 | uint32_t aux_clock_divider; |
f0f59a00 | 178 | i915_reg_t aux_ctl_reg; |
0bc12bcb RV |
179 | static const uint8_t aux_msg[] = { |
180 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
181 | [1] = DP_SET_POWER >> 8, | |
182 | [2] = DP_SET_POWER & 0xff, | |
183 | [3] = 1 - 1, | |
184 | [4] = DP_SET_POWER_D0, | |
185 | }; | |
750a951f | 186 | enum port port = dig_port->port; |
d4dcbdce | 187 | u32 aux_ctl; |
0bc12bcb RV |
188 | int i; |
189 | ||
190 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
191 | ||
192 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); | |
193 | ||
474d1ec4 SJ |
194 | /* Enable AUX frame sync at sink */ |
195 | if (dev_priv->psr.aux_frame_sync) | |
196 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
197 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
198 | DP_AUX_FRAME_SYNC_ENABLE); | |
199 | ||
6f32ea7e DV |
200 | if (dev_priv->psr.link_standby) |
201 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
202 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); | |
203 | else | |
204 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
205 | DP_PSR_ENABLE); | |
206 | ||
1f38089c | 207 | aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port); |
e3d99845 | 208 | |
0bc12bcb RV |
209 | /* Setup AUX registers */ |
210 | for (i = 0; i < sizeof(aux_msg); i += 4) | |
1f38089c | 211 | I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2), |
0bc12bcb RV |
212 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
213 | ||
d4dcbdce DV |
214 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg), |
215 | aux_clock_divider); | |
216 | I915_WRITE(aux_ctl_reg, aux_ctl); | |
0bc12bcb RV |
217 | } |
218 | ||
e2bbc343 RV |
219 | static void vlv_psr_enable_source(struct intel_dp *intel_dp) |
220 | { | |
221 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
222 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 223 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
224 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
225 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
226 | ||
227 | /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ | |
228 | I915_WRITE(VLV_PSRCTL(pipe), | |
229 | VLV_EDP_PSR_MODE_SW_TIMER | | |
230 | VLV_EDP_PSR_SRC_TRANSMITTER_STATE | | |
231 | VLV_EDP_PSR_ENABLE); | |
232 | } | |
233 | ||
995d3047 RV |
234 | static void vlv_psr_activate(struct intel_dp *intel_dp) |
235 | { | |
236 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
237 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 238 | struct drm_i915_private *dev_priv = to_i915(dev); |
995d3047 RV |
239 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
240 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
241 | ||
242 | /* Let's do the transition from PSR_state 1 to PSR_state 2 | |
243 | * that is PSR transition to active - static frame transmission. | |
244 | * Then Hardware is responsible for the transition to PSR_state 3 | |
245 | * that is PSR active - no Remote Frame Buffer (RFB) update. | |
246 | */ | |
247 | I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | | |
248 | VLV_EDP_PSR_ACTIVE_ENTRY); | |
249 | } | |
250 | ||
e2bbc343 | 251 | static void hsw_psr_enable_source(struct intel_dp *intel_dp) |
0bc12bcb RV |
252 | { |
253 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
254 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 255 | struct drm_i915_private *dev_priv = to_i915(dev); |
474d1ec4 | 256 | |
0bc12bcb | 257 | uint32_t max_sleep_time = 0x1f; |
1c80c25f DV |
258 | /* Lately it was identified that depending on panel idle frame count |
259 | * calculated at HW can be off by 1. So let's use what came | |
260 | * from VBT + 1. | |
261 | * There are also other cases where panel demands at least 4 | |
262 | * but VBT is not being set. To cover these 2 cases lets use | |
263 | * at least 5 when VBT isn't set to be on the safest side. | |
d44b4dcb | 264 | */ |
1c80c25f | 265 | uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1; |
50db1390 DV |
266 | uint32_t val = EDP_PSR_ENABLE; |
267 | ||
268 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
269 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
7370c68d RV |
270 | |
271 | if (IS_HASWELL(dev)) | |
272 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
0bc12bcb | 273 | |
60e5ffe3 RV |
274 | if (dev_priv->psr.link_standby) |
275 | val |= EDP_PSR_LINK_STANDBY; | |
276 | ||
50db1390 DV |
277 | if (dev_priv->vbt.psr.tp1_wakeup_time > 5) |
278 | val |= EDP_PSR_TP1_TIME_2500us; | |
279 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) | |
280 | val |= EDP_PSR_TP1_TIME_500us; | |
281 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) | |
282 | val |= EDP_PSR_TP1_TIME_100us; | |
283 | else | |
284 | val |= EDP_PSR_TP1_TIME_0us; | |
285 | ||
286 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) | |
287 | val |= EDP_PSR_TP2_TP3_TIME_2500us; | |
288 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) | |
289 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
290 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) | |
291 | val |= EDP_PSR_TP2_TP3_TIME_100us; | |
292 | else | |
293 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
294 | ||
295 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
296 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
297 | val |= EDP_PSR_TP1_TP3_SEL; | |
298 | else | |
299 | val |= EDP_PSR_TP1_TP2_SEL; | |
300 | ||
301 | I915_WRITE(EDP_PSR_CTL, val); | |
302 | ||
303 | if (!dev_priv->psr.psr2_support) | |
304 | return; | |
305 | ||
306 | /* FIXME: selective update is probably totally broken because it doesn't | |
307 | * mesh at all with our frontbuffer tracking. And the hw alone isn't | |
308 | * good enough. */ | |
309 | val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; | |
310 | ||
311 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) | |
312 | val |= EDP_PSR2_TP2_TIME_2500; | |
313 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) | |
314 | val |= EDP_PSR2_TP2_TIME_500; | |
315 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) | |
316 | val |= EDP_PSR2_TP2_TIME_100; | |
317 | else | |
318 | val |= EDP_PSR2_TP2_TIME_50; | |
474d1ec4 | 319 | |
50db1390 | 320 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
321 | } |
322 | ||
323 | static bool intel_psr_match_conditions(struct intel_dp *intel_dp) | |
324 | { | |
325 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
326 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 327 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
328 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dfd2e9ab VS |
330 | const struct drm_display_mode *adjusted_mode = |
331 | &intel_crtc->config->base.adjusted_mode; | |
332 | int psr_setup_time; | |
0bc12bcb RV |
333 | |
334 | lockdep_assert_held(&dev_priv->psr.lock); | |
335 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
336 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); | |
337 | ||
338 | dev_priv->psr.source_ok = false; | |
339 | ||
dc9b5a0c RV |
340 | /* |
341 | * HSW spec explicitly says PSR is tied to port A. | |
342 | * BDW+ platforms with DDI implementation of PSR have different | |
343 | * PSR registers per transcoder and we only implement transcoder EDP | |
344 | * ones. Since by Display design transcoder EDP is tied to port A | |
345 | * we can safely escape based on the port A. | |
346 | */ | |
347 | if (HAS_DDI(dev) && dig_port->port != PORT_A) { | |
348 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); | |
0bc12bcb RV |
349 | return false; |
350 | } | |
351 | ||
352 | if (!i915.enable_psr) { | |
353 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
354 | return false; | |
355 | } | |
356 | ||
65f61b42 RV |
357 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
358 | !dev_priv->psr.link_standby) { | |
359 | DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n"); | |
360 | return false; | |
361 | } | |
362 | ||
c8e68b7e | 363 | if (IS_HASWELL(dev) && |
6e3c9717 | 364 | I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & |
c8e68b7e | 365 | S3D_ENABLE) { |
0bc12bcb RV |
366 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
367 | return false; | |
368 | } | |
369 | ||
c8e68b7e | 370 | if (IS_HASWELL(dev) && |
dfd2e9ab | 371 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb RV |
372 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
373 | return false; | |
374 | } | |
375 | ||
dfd2e9ab VS |
376 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
377 | if (psr_setup_time < 0) { | |
378 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
379 | intel_dp->psr_dpcd[1]); | |
380 | return false; | |
381 | } | |
382 | ||
383 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
384 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
385 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
386 | psr_setup_time); | |
387 | return false; | |
388 | } | |
389 | ||
0bc12bcb RV |
390 | dev_priv->psr.source_ok = true; |
391 | return true; | |
392 | } | |
393 | ||
e2bbc343 | 394 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb RV |
395 | { |
396 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
397 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 398 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 399 | |
443a389f | 400 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); |
0bc12bcb RV |
401 | WARN_ON(dev_priv->psr.active); |
402 | lockdep_assert_held(&dev_priv->psr.lock); | |
403 | ||
995d3047 RV |
404 | /* Enable/Re-enable PSR on the host */ |
405 | if (HAS_DDI(dev)) | |
406 | /* On HSW+ after we enable PSR on source it will activate it | |
407 | * as soon as it match configure idle_frame count. So | |
408 | * we just actually enable it here on activation time. | |
409 | */ | |
410 | hsw_psr_enable_source(intel_dp); | |
411 | else | |
412 | vlv_psr_activate(intel_dp); | |
413 | ||
0bc12bcb RV |
414 | dev_priv->psr.active = true; |
415 | } | |
416 | ||
b2b89f55 RV |
417 | /** |
418 | * intel_psr_enable - Enable PSR | |
419 | * @intel_dp: Intel DP | |
420 | * | |
421 | * This function can only be called after the pipe is fully trained and enabled. | |
422 | */ | |
0bc12bcb RV |
423 | void intel_psr_enable(struct intel_dp *intel_dp) |
424 | { | |
425 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
426 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 427 | struct drm_i915_private *dev_priv = to_i915(dev); |
474d1ec4 | 428 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
0bc12bcb RV |
429 | |
430 | if (!HAS_PSR(dev)) { | |
431 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); | |
432 | return; | |
433 | } | |
434 | ||
435 | if (!is_edp_psr(intel_dp)) { | |
436 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); | |
437 | return; | |
438 | } | |
439 | ||
440 | mutex_lock(&dev_priv->psr.lock); | |
441 | if (dev_priv->psr.enabled) { | |
442 | DRM_DEBUG_KMS("PSR already in use\n"); | |
443 | goto unlock; | |
444 | } | |
445 | ||
446 | if (!intel_psr_match_conditions(intel_dp)) | |
447 | goto unlock; | |
448 | ||
449 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
450 | ||
e2bbc343 RV |
451 | if (HAS_DDI(dev)) { |
452 | hsw_psr_setup_vsc(intel_dp); | |
0bc12bcb | 453 | |
474d1ec4 SJ |
454 | if (dev_priv->psr.psr2_support) { |
455 | /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */ | |
456 | if (crtc->config->pipe_src_w > 3200 || | |
457 | crtc->config->pipe_src_h > 2000) | |
458 | dev_priv->psr.psr2_support = false; | |
459 | else | |
460 | skl_psr_setup_su_vsc(intel_dp); | |
461 | } | |
462 | ||
bb929cbc RV |
463 | /* |
464 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD. | |
465 | * Also mask LPSP to avoid dependency on other drivers that | |
466 | * might block runtime_pm besides preventing other hw tracking | |
467 | * issues now we can rely on frontbuffer tracking. | |
468 | */ | |
443a389f | 469 | I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP | |
bb929cbc | 470 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
0bc12bcb | 471 | |
e2bbc343 RV |
472 | /* Enable PSR on the panel */ |
473 | hsw_psr_enable_sink(intel_dp); | |
e3d99845 SJ |
474 | |
475 | if (INTEL_INFO(dev)->gen >= 9) | |
476 | intel_psr_activate(intel_dp); | |
e2bbc343 RV |
477 | } else { |
478 | vlv_psr_setup_vsc(intel_dp); | |
479 | ||
480 | /* Enable PSR on the panel */ | |
481 | vlv_psr_enable_sink(intel_dp); | |
482 | ||
483 | /* On HSW+ enable_source also means go to PSR entry/active | |
484 | * state as soon as idle_frame achieved and here would be | |
485 | * to soon. However on VLV enable_source just enable PSR | |
486 | * but let it on inactive state. So we might do this prior | |
487 | * to active transition, i.e. here. | |
488 | */ | |
489 | vlv_psr_enable_source(intel_dp); | |
490 | } | |
0bc12bcb | 491 | |
d0ac896a RV |
492 | /* |
493 | * FIXME: Activation should happen immediately since this function | |
494 | * is just called after pipe is fully trained and enabled. | |
495 | * However on every platform we face issues when first activation | |
496 | * follows a modeset so quickly. | |
497 | * - On VLV/CHV we get bank screen on first activation | |
498 | * - On HSW/BDW we get a recoverable frozen screen until next | |
499 | * exit-activate sequence. | |
500 | */ | |
501 | if (INTEL_INFO(dev)->gen < 9) | |
502 | schedule_delayed_work(&dev_priv->psr.work, | |
503 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
504 | ||
0bc12bcb RV |
505 | dev_priv->psr.enabled = intel_dp; |
506 | unlock: | |
507 | mutex_unlock(&dev_priv->psr.lock); | |
508 | } | |
509 | ||
e2bbc343 | 510 | static void vlv_psr_disable(struct intel_dp *intel_dp) |
0bc12bcb RV |
511 | { |
512 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
513 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 514 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
515 | struct intel_crtc *intel_crtc = |
516 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
517 | uint32_t val; | |
0bc12bcb | 518 | |
e2bbc343 RV |
519 | if (dev_priv->psr.active) { |
520 | /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ | |
eb0241c1 CW |
521 | if (intel_wait_for_register(dev_priv, |
522 | VLV_PSRSTAT(intel_crtc->pipe), | |
523 | VLV_EDP_PSR_IN_TRANS, | |
524 | 0, | |
525 | 1)) | |
e2bbc343 RV |
526 | WARN(1, "PSR transition took longer than expected\n"); |
527 | ||
528 | val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); | |
529 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
530 | val &= ~VLV_EDP_PSR_ENABLE; | |
531 | val &= ~VLV_EDP_PSR_MODE_MASK; | |
532 | I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); | |
533 | ||
534 | dev_priv->psr.active = false; | |
535 | } else { | |
536 | WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); | |
0bc12bcb | 537 | } |
e2bbc343 RV |
538 | } |
539 | ||
540 | static void hsw_psr_disable(struct intel_dp *intel_dp) | |
541 | { | |
542 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
543 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 544 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
545 | |
546 | if (dev_priv->psr.active) { | |
443a389f VS |
547 | I915_WRITE(EDP_PSR_CTL, |
548 | I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); | |
0bc12bcb RV |
549 | |
550 | /* Wait till PSR is idle */ | |
a5b2fd8c CW |
551 | if (intel_wait_for_register(dev_priv, |
552 | EDP_PSR_STATUS_CTL, | |
553 | EDP_PSR_STATUS_STATE_MASK, | |
554 | 0, | |
555 | 2000)) | |
0bc12bcb RV |
556 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
557 | ||
558 | dev_priv->psr.active = false; | |
559 | } else { | |
443a389f | 560 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); |
0bc12bcb | 561 | } |
e2bbc343 RV |
562 | } |
563 | ||
564 | /** | |
565 | * intel_psr_disable - Disable PSR | |
566 | * @intel_dp: Intel DP | |
567 | * | |
568 | * This function needs to be called before disabling pipe. | |
569 | */ | |
570 | void intel_psr_disable(struct intel_dp *intel_dp) | |
571 | { | |
572 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
573 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 574 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
575 | |
576 | mutex_lock(&dev_priv->psr.lock); | |
577 | if (!dev_priv->psr.enabled) { | |
578 | mutex_unlock(&dev_priv->psr.lock); | |
579 | return; | |
580 | } | |
581 | ||
b6e4d534 | 582 | /* Disable PSR on Source */ |
e2bbc343 RV |
583 | if (HAS_DDI(dev)) |
584 | hsw_psr_disable(intel_dp); | |
585 | else | |
586 | vlv_psr_disable(intel_dp); | |
0bc12bcb | 587 | |
b6e4d534 RV |
588 | /* Disable PSR on Sink */ |
589 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
590 | ||
0bc12bcb RV |
591 | dev_priv->psr.enabled = NULL; |
592 | mutex_unlock(&dev_priv->psr.lock); | |
593 | ||
594 | cancel_delayed_work_sync(&dev_priv->psr.work); | |
595 | } | |
596 | ||
597 | static void intel_psr_work(struct work_struct *work) | |
598 | { | |
599 | struct drm_i915_private *dev_priv = | |
600 | container_of(work, typeof(*dev_priv), psr.work.work); | |
601 | struct intel_dp *intel_dp = dev_priv->psr.enabled; | |
995d3047 RV |
602 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
603 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
0bc12bcb RV |
604 | |
605 | /* We have to make sure PSR is ready for re-enable | |
606 | * otherwise it keeps disabled until next full enable/disable cycle. | |
607 | * PSR might take some time to get fully disabled | |
608 | * and be ready for re-enable. | |
609 | */ | |
2d1fe073 | 610 | if (HAS_DDI(dev_priv)) { |
12bb6319 CW |
611 | if (intel_wait_for_register(dev_priv, |
612 | EDP_PSR_STATUS_CTL, | |
613 | EDP_PSR_STATUS_STATE_MASK, | |
614 | 0, | |
615 | 50)) { | |
995d3047 RV |
616 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); |
617 | return; | |
618 | } | |
619 | } else { | |
12bb6319 CW |
620 | if (intel_wait_for_register(dev_priv, |
621 | VLV_PSRSTAT(pipe), | |
622 | VLV_EDP_PSR_IN_TRANS, | |
623 | 0, | |
624 | 1)) { | |
995d3047 RV |
625 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); |
626 | return; | |
627 | } | |
0bc12bcb | 628 | } |
0bc12bcb RV |
629 | mutex_lock(&dev_priv->psr.lock); |
630 | intel_dp = dev_priv->psr.enabled; | |
631 | ||
632 | if (!intel_dp) | |
633 | goto unlock; | |
634 | ||
635 | /* | |
636 | * The delayed work can race with an invalidate hence we need to | |
637 | * recheck. Since psr_flush first clears this and then reschedules we | |
638 | * won't ever miss a flush when bailing out here. | |
639 | */ | |
640 | if (dev_priv->psr.busy_frontbuffer_bits) | |
641 | goto unlock; | |
642 | ||
e2bbc343 | 643 | intel_psr_activate(intel_dp); |
0bc12bcb RV |
644 | unlock: |
645 | mutex_unlock(&dev_priv->psr.lock); | |
646 | } | |
647 | ||
5748b6a1 | 648 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
0bc12bcb | 649 | { |
995d3047 RV |
650 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
651 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
652 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
653 | u32 val; | |
0bc12bcb | 654 | |
995d3047 RV |
655 | if (!dev_priv->psr.active) |
656 | return; | |
657 | ||
5748b6a1 | 658 | if (HAS_DDI(dev_priv)) { |
443a389f | 659 | val = I915_READ(EDP_PSR_CTL); |
0bc12bcb RV |
660 | |
661 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
662 | ||
443a389f | 663 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); |
995d3047 RV |
664 | } else { |
665 | val = I915_READ(VLV_PSRCTL(pipe)); | |
666 | ||
667 | /* Here we do the transition from PSR_state 3 to PSR_state 5 | |
668 | * directly once PSR State 4 that is active with single frame | |
669 | * update can be skipped. PSR_state 5 that is PSR exit then | |
670 | * Hardware is responsible to transition back to PSR_state 1 | |
671 | * that is PSR inactive. Same state after | |
672 | * vlv_edp_psr_enable_source. | |
673 | */ | |
674 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
675 | I915_WRITE(VLV_PSRCTL(pipe), val); | |
676 | ||
677 | /* Send AUX wake up - Spec says after transitioning to PSR | |
678 | * active we have to send AUX wake up by writing 01h in DPCD | |
679 | * 600h of sink device. | |
680 | * XXX: This might slow down the transition, but without this | |
681 | * HW doesn't complete the transition to PSR_state 1 and we | |
682 | * never get the screen updated. | |
683 | */ | |
684 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, | |
685 | DP_SET_POWER_D0); | |
0bc12bcb RV |
686 | } |
687 | ||
995d3047 | 688 | dev_priv->psr.active = false; |
0bc12bcb RV |
689 | } |
690 | ||
c7240c3b RV |
691 | /** |
692 | * intel_psr_single_frame_update - Single Frame Update | |
5748b6a1 | 693 | * @dev_priv: i915 device |
20c8838b | 694 | * @frontbuffer_bits: frontbuffer plane tracking bits |
c7240c3b RV |
695 | * |
696 | * Some platforms support a single frame update feature that is used to | |
697 | * send and update only one frame on Remote Frame Buffer. | |
698 | * So far it is only implemented for Valleyview and Cherryview because | |
699 | * hardware requires this to be done before a page flip. | |
700 | */ | |
5748b6a1 | 701 | void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, |
20c8838b | 702 | unsigned frontbuffer_bits) |
c7240c3b | 703 | { |
c7240c3b RV |
704 | struct drm_crtc *crtc; |
705 | enum pipe pipe; | |
706 | u32 val; | |
707 | ||
708 | /* | |
709 | * Single frame update is already supported on BDW+ but it requires | |
710 | * many W/A and it isn't really needed. | |
711 | */ | |
5748b6a1 | 712 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
c7240c3b RV |
713 | return; |
714 | ||
715 | mutex_lock(&dev_priv->psr.lock); | |
716 | if (!dev_priv->psr.enabled) { | |
717 | mutex_unlock(&dev_priv->psr.lock); | |
718 | return; | |
719 | } | |
720 | ||
721 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
722 | pipe = to_intel_crtc(crtc)->pipe; | |
c7240c3b | 723 | |
20c8838b DV |
724 | if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) { |
725 | val = I915_READ(VLV_PSRCTL(pipe)); | |
c7240c3b | 726 | |
20c8838b DV |
727 | /* |
728 | * We need to set this bit before writing registers for a flip. | |
729 | * This bit will be self-clear when it gets to the PSR active state. | |
730 | */ | |
731 | I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); | |
732 | } | |
c7240c3b RV |
733 | mutex_unlock(&dev_priv->psr.lock); |
734 | } | |
735 | ||
b2b89f55 RV |
736 | /** |
737 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 738 | * @dev_priv: i915 device |
b2b89f55 RV |
739 | * @frontbuffer_bits: frontbuffer plane tracking bits |
740 | * | |
741 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
742 | * with the software frontbuffer tracking. This function gets called every | |
743 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
744 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
745 | * | |
746 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
747 | */ | |
5748b6a1 | 748 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
20c8838b | 749 | unsigned frontbuffer_bits) |
0bc12bcb | 750 | { |
0bc12bcb RV |
751 | struct drm_crtc *crtc; |
752 | enum pipe pipe; | |
753 | ||
754 | mutex_lock(&dev_priv->psr.lock); | |
755 | if (!dev_priv->psr.enabled) { | |
756 | mutex_unlock(&dev_priv->psr.lock); | |
757 | return; | |
758 | } | |
759 | ||
760 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
761 | pipe = to_intel_crtc(crtc)->pipe; | |
762 | ||
0bc12bcb | 763 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
0bc12bcb | 764 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
765 | |
766 | if (frontbuffer_bits) | |
5748b6a1 | 767 | intel_psr_exit(dev_priv); |
ec76d629 | 768 | |
0bc12bcb RV |
769 | mutex_unlock(&dev_priv->psr.lock); |
770 | } | |
771 | ||
b2b89f55 RV |
772 | /** |
773 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 774 | * @dev_priv: i915 device |
b2b89f55 | 775 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 776 | * @origin: which operation caused the flush |
b2b89f55 RV |
777 | * |
778 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
779 | * with the software frontbuffer tracking. This function gets called every | |
780 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
781 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
782 | * | |
783 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
784 | */ | |
5748b6a1 | 785 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 786 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 787 | { |
0bc12bcb RV |
788 | struct drm_crtc *crtc; |
789 | enum pipe pipe; | |
790 | ||
791 | mutex_lock(&dev_priv->psr.lock); | |
792 | if (!dev_priv->psr.enabled) { | |
793 | mutex_unlock(&dev_priv->psr.lock); | |
794 | return; | |
795 | } | |
796 | ||
797 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
798 | pipe = to_intel_crtc(crtc)->pipe; | |
ec76d629 DV |
799 | |
800 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
0bc12bcb RV |
801 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
802 | ||
921ec285 RV |
803 | /* By definition flush = invalidate + flush */ |
804 | if (frontbuffer_bits) | |
5748b6a1 | 805 | intel_psr_exit(dev_priv); |
995d3047 | 806 | |
0bc12bcb | 807 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
d0ac896a RV |
808 | if (!work_busy(&dev_priv->psr.work.work)) |
809 | schedule_delayed_work(&dev_priv->psr.work, | |
20bb97fe | 810 | msecs_to_jiffies(100)); |
0bc12bcb RV |
811 | mutex_unlock(&dev_priv->psr.lock); |
812 | } | |
813 | ||
b2b89f55 RV |
814 | /** |
815 | * intel_psr_init - Init basic PSR work and mutex. | |
816 | * @dev: DRM device | |
817 | * | |
818 | * This function is called only once at driver load to initialize basic | |
819 | * PSR stuff. | |
820 | */ | |
0bc12bcb RV |
821 | void intel_psr_init(struct drm_device *dev) |
822 | { | |
fac5e23e | 823 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 824 | |
443a389f VS |
825 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
826 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
827 | ||
d94d6e87 RV |
828 | /* Per platform default */ |
829 | if (i915.enable_psr == -1) { | |
dcb2e993 | 830 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a38c274f RV |
831 | i915.enable_psr = 1; |
832 | else | |
833 | i915.enable_psr = 0; | |
d94d6e87 RV |
834 | } |
835 | ||
65f61b42 | 836 | /* Set link_standby x link_off defaults */ |
60e5ffe3 RV |
837 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
838 | /* HSW and BDW require workarounds that we don't implement. */ | |
839 | dev_priv->psr.link_standby = false; | |
840 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
841 | /* On VLV and CHV only standby mode is supported. */ | |
842 | dev_priv->psr.link_standby = true; | |
843 | else | |
844 | /* For new platforms let's respect VBT back again */ | |
845 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
846 | ||
65f61b42 RV |
847 | /* Override link_standby x link_off defaults */ |
848 | if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) { | |
849 | DRM_DEBUG_KMS("PSR: Forcing link standby\n"); | |
850 | dev_priv->psr.link_standby = true; | |
851 | } | |
852 | if (i915.enable_psr == 3 && dev_priv->psr.link_standby) { | |
853 | DRM_DEBUG_KMS("PSR: Forcing main link off\n"); | |
854 | dev_priv->psr.link_standby = false; | |
855 | } | |
856 | ||
0bc12bcb RV |
857 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); |
858 | mutex_init(&dev_priv->psr.lock); | |
859 | } |