Commit | Line | Data |
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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
59 | static bool is_edp_psr(struct intel_dp *intel_dp) | |
60 | { | |
61 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; | |
62 | } | |
63 | ||
e2bbc343 RV |
64 | static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) |
65 | { | |
66 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67 | uint32_t val; | |
68 | ||
69 | val = I915_READ(VLV_PSRSTAT(pipe)) & | |
70 | VLV_EDP_PSR_CURR_STATE_MASK; | |
71 | return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
72 | (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); | |
73 | } | |
74 | ||
0bc12bcb RV |
75 | static void intel_psr_write_vsc(struct intel_dp *intel_dp, |
76 | struct edp_vsc_psr *vsc_psr) | |
77 | { | |
78 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
79 | struct drm_device *dev = dig_port->base.base.dev; | |
80 | struct drm_i915_private *dev_priv = dev->dev_private; | |
81 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
6e3c9717 ACO |
82 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); |
83 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder); | |
0bc12bcb RV |
84 | uint32_t *data = (uint32_t *) vsc_psr; |
85 | unsigned int i; | |
86 | ||
87 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
88 | the video DIP being updated before program video DIP data buffer | |
89 | registers for DIP being updated. */ | |
90 | I915_WRITE(ctl_reg, 0); | |
91 | POSTING_READ(ctl_reg); | |
92 | ||
93 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
94 | if (i < sizeof(struct edp_vsc_psr)) | |
95 | I915_WRITE(data_reg + i, *data++); | |
96 | else | |
97 | I915_WRITE(data_reg + i, 0); | |
98 | } | |
99 | ||
100 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
101 | POSTING_READ(ctl_reg); | |
102 | } | |
103 | ||
e2bbc343 RV |
104 | static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) |
105 | { | |
106 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
107 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
109 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
110 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
111 | uint32_t val; | |
112 | ||
113 | /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ | |
114 | val = I915_READ(VLV_VSCSDP(pipe)); | |
115 | val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; | |
116 | val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; | |
117 | I915_WRITE(VLV_VSCSDP(pipe), val); | |
118 | } | |
119 | ||
120 | static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) | |
0bc12bcb RV |
121 | { |
122 | struct edp_vsc_psr psr_vsc; | |
123 | ||
124 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
125 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
126 | psr_vsc.sdp_header.HB0 = 0; | |
127 | psr_vsc.sdp_header.HB1 = 0x7; | |
128 | psr_vsc.sdp_header.HB2 = 0x2; | |
129 | psr_vsc.sdp_header.HB3 = 0x8; | |
130 | intel_psr_write_vsc(intel_dp, &psr_vsc); | |
131 | } | |
132 | ||
e2bbc343 RV |
133 | static void vlv_psr_enable_sink(struct intel_dp *intel_dp) |
134 | { | |
135 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
136 | DP_PSR_ENABLE); | |
137 | } | |
138 | ||
139 | static void hsw_psr_enable_sink(struct intel_dp *intel_dp) | |
0bc12bcb RV |
140 | { |
141 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
142 | struct drm_device *dev = dig_port->base.base.dev; | |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | uint32_t aux_clock_divider; | |
145 | int precharge = 0x3; | |
0bc12bcb RV |
146 | static const uint8_t aux_msg[] = { |
147 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
148 | [1] = DP_SET_POWER >> 8, | |
149 | [2] = DP_SET_POWER & 0xff, | |
150 | [3] = 1 - 1, | |
151 | [4] = DP_SET_POWER_D0, | |
152 | }; | |
153 | int i; | |
154 | ||
155 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
156 | ||
157 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); | |
158 | ||
0bc12bcb | 159 | /* Enable PSR in sink */ |
0243f7ba | 160 | if (dev_priv->psr.link_standby) |
0bc12bcb | 161 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
6caf36a4 | 162 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
0bc12bcb RV |
163 | else |
164 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
6caf36a4 | 165 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
0bc12bcb RV |
166 | |
167 | /* Setup AUX registers */ | |
168 | for (i = 0; i < sizeof(aux_msg); i += 4) | |
169 | I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i, | |
170 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); | |
171 | ||
172 | I915_WRITE(EDP_PSR_AUX_CTL(dev), | |
173 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
174 | (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
175 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
176 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
177 | } | |
178 | ||
e2bbc343 RV |
179 | static void vlv_psr_enable_source(struct intel_dp *intel_dp) |
180 | { | |
181 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
182 | struct drm_device *dev = dig_port->base.base.dev; | |
183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
184 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
185 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
186 | ||
187 | /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ | |
188 | I915_WRITE(VLV_PSRCTL(pipe), | |
189 | VLV_EDP_PSR_MODE_SW_TIMER | | |
190 | VLV_EDP_PSR_SRC_TRANSMITTER_STATE | | |
191 | VLV_EDP_PSR_ENABLE); | |
192 | } | |
193 | ||
995d3047 RV |
194 | static void vlv_psr_activate(struct intel_dp *intel_dp) |
195 | { | |
196 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
197 | struct drm_device *dev = dig_port->base.base.dev; | |
198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
199 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
200 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
201 | ||
202 | /* Let's do the transition from PSR_state 1 to PSR_state 2 | |
203 | * that is PSR transition to active - static frame transmission. | |
204 | * Then Hardware is responsible for the transition to PSR_state 3 | |
205 | * that is PSR active - no Remote Frame Buffer (RFB) update. | |
206 | */ | |
207 | I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | | |
208 | VLV_EDP_PSR_ACTIVE_ENTRY); | |
209 | } | |
210 | ||
e2bbc343 | 211 | static void hsw_psr_enable_source(struct intel_dp *intel_dp) |
0bc12bcb RV |
212 | { |
213 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
214 | struct drm_device *dev = dig_port->base.base.dev; | |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
216 | uint32_t max_sleep_time = 0x1f; | |
d44b4dcb RV |
217 | /* Lately it was identified that depending on panel idle frame count |
218 | * calculated at HW can be off by 1. So let's use what came | |
219 | * from VBT + 1 and at minimum 2 to be on the safe side. | |
220 | */ | |
221 | uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ? | |
222 | dev_priv->vbt.psr.idle_frames + 1 : 2; | |
0bc12bcb RV |
223 | uint32_t val = 0x0; |
224 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
0bc12bcb | 225 | |
0243f7ba | 226 | if (dev_priv->psr.link_standby) { |
0bc12bcb RV |
227 | val |= EDP_PSR_LINK_STANDBY; |
228 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
229 | val |= EDP_PSR_TP1_TIME_0us; | |
230 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
0bc12bcb RV |
231 | } else |
232 | val |= EDP_PSR_LINK_DISABLE; | |
233 | ||
234 | I915_WRITE(EDP_PSR_CTL(dev), val | | |
235 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | | |
236 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | | |
237 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
238 | EDP_PSR_ENABLE); | |
239 | } | |
240 | ||
241 | static bool intel_psr_match_conditions(struct intel_dp *intel_dp) | |
242 | { | |
243 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
244 | struct drm_device *dev = dig_port->base.base.dev; | |
245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
246 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
248 | ||
249 | lockdep_assert_held(&dev_priv->psr.lock); | |
250 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
251 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); | |
252 | ||
253 | dev_priv->psr.source_ok = false; | |
254 | ||
255 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { | |
256 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); | |
257 | return false; | |
258 | } | |
259 | ||
260 | if (!i915.enable_psr) { | |
261 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
262 | return false; | |
263 | } | |
264 | ||
c8e68b7e | 265 | if (IS_HASWELL(dev) && |
6e3c9717 | 266 | I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & |
c8e68b7e | 267 | S3D_ENABLE) { |
0bc12bcb RV |
268 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
269 | return false; | |
270 | } | |
271 | ||
c8e68b7e | 272 | if (IS_HASWELL(dev) && |
6e3c9717 | 273 | intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb RV |
274 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
275 | return false; | |
276 | } | |
277 | ||
0bc12bcb RV |
278 | dev_priv->psr.source_ok = true; |
279 | return true; | |
280 | } | |
281 | ||
e2bbc343 | 282 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb RV |
283 | { |
284 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
285 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
287 | ||
288 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); | |
289 | WARN_ON(dev_priv->psr.active); | |
290 | lockdep_assert_held(&dev_priv->psr.lock); | |
291 | ||
995d3047 RV |
292 | /* Enable/Re-enable PSR on the host */ |
293 | if (HAS_DDI(dev)) | |
294 | /* On HSW+ after we enable PSR on source it will activate it | |
295 | * as soon as it match configure idle_frame count. So | |
296 | * we just actually enable it here on activation time. | |
297 | */ | |
298 | hsw_psr_enable_source(intel_dp); | |
299 | else | |
300 | vlv_psr_activate(intel_dp); | |
301 | ||
0bc12bcb RV |
302 | dev_priv->psr.active = true; |
303 | } | |
304 | ||
b2b89f55 RV |
305 | /** |
306 | * intel_psr_enable - Enable PSR | |
307 | * @intel_dp: Intel DP | |
308 | * | |
309 | * This function can only be called after the pipe is fully trained and enabled. | |
310 | */ | |
0bc12bcb RV |
311 | void intel_psr_enable(struct intel_dp *intel_dp) |
312 | { | |
313 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
314 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
316 | ||
317 | if (!HAS_PSR(dev)) { | |
318 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); | |
319 | return; | |
320 | } | |
321 | ||
322 | if (!is_edp_psr(intel_dp)) { | |
323 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); | |
324 | return; | |
325 | } | |
326 | ||
327 | mutex_lock(&dev_priv->psr.lock); | |
328 | if (dev_priv->psr.enabled) { | |
329 | DRM_DEBUG_KMS("PSR already in use\n"); | |
330 | goto unlock; | |
331 | } | |
332 | ||
333 | if (!intel_psr_match_conditions(intel_dp)) | |
334 | goto unlock; | |
335 | ||
0243f7ba RV |
336 | /* First we check VBT, but we must respect sink and source |
337 | * known restrictions */ | |
338 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
339 | if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) || | |
340 | (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)) | |
341 | dev_priv->psr.link_standby = true; | |
342 | ||
0bc12bcb RV |
343 | dev_priv->psr.busy_frontbuffer_bits = 0; |
344 | ||
e2bbc343 RV |
345 | if (HAS_DDI(dev)) { |
346 | hsw_psr_setup_vsc(intel_dp); | |
0bc12bcb | 347 | |
e2bbc343 RV |
348 | /* Avoid continuous PSR exit by masking memup and hpd */ |
349 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | | |
350 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); | |
0bc12bcb | 351 | |
e2bbc343 RV |
352 | /* Enable PSR on the panel */ |
353 | hsw_psr_enable_sink(intel_dp); | |
354 | } else { | |
355 | vlv_psr_setup_vsc(intel_dp); | |
356 | ||
357 | /* Enable PSR on the panel */ | |
358 | vlv_psr_enable_sink(intel_dp); | |
359 | ||
360 | /* On HSW+ enable_source also means go to PSR entry/active | |
361 | * state as soon as idle_frame achieved and here would be | |
362 | * to soon. However on VLV enable_source just enable PSR | |
363 | * but let it on inactive state. So we might do this prior | |
364 | * to active transition, i.e. here. | |
365 | */ | |
366 | vlv_psr_enable_source(intel_dp); | |
367 | } | |
0bc12bcb RV |
368 | |
369 | dev_priv->psr.enabled = intel_dp; | |
370 | unlock: | |
371 | mutex_unlock(&dev_priv->psr.lock); | |
372 | } | |
373 | ||
e2bbc343 | 374 | static void vlv_psr_disable(struct intel_dp *intel_dp) |
0bc12bcb RV |
375 | { |
376 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
377 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2bbc343 RV |
379 | struct intel_crtc *intel_crtc = |
380 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
381 | uint32_t val; | |
0bc12bcb | 382 | |
e2bbc343 RV |
383 | if (dev_priv->psr.active) { |
384 | /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ | |
385 | if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & | |
386 | VLV_EDP_PSR_IN_TRANS) == 0, 1)) | |
387 | WARN(1, "PSR transition took longer than expected\n"); | |
388 | ||
389 | val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); | |
390 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
391 | val &= ~VLV_EDP_PSR_ENABLE; | |
392 | val &= ~VLV_EDP_PSR_MODE_MASK; | |
393 | I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); | |
394 | ||
395 | dev_priv->psr.active = false; | |
396 | } else { | |
397 | WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); | |
0bc12bcb | 398 | } |
e2bbc343 RV |
399 | } |
400 | ||
401 | static void hsw_psr_disable(struct intel_dp *intel_dp) | |
402 | { | |
403 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
404 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0bc12bcb RV |
406 | |
407 | if (dev_priv->psr.active) { | |
408 | I915_WRITE(EDP_PSR_CTL(dev), | |
409 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
410 | ||
411 | /* Wait till PSR is idle */ | |
412 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & | |
413 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) | |
414 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
415 | ||
416 | dev_priv->psr.active = false; | |
417 | } else { | |
418 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); | |
419 | } | |
e2bbc343 RV |
420 | } |
421 | ||
422 | /** | |
423 | * intel_psr_disable - Disable PSR | |
424 | * @intel_dp: Intel DP | |
425 | * | |
426 | * This function needs to be called before disabling pipe. | |
427 | */ | |
428 | void intel_psr_disable(struct intel_dp *intel_dp) | |
429 | { | |
430 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
431 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
433 | ||
434 | mutex_lock(&dev_priv->psr.lock); | |
435 | if (!dev_priv->psr.enabled) { | |
436 | mutex_unlock(&dev_priv->psr.lock); | |
437 | return; | |
438 | } | |
439 | ||
440 | if (HAS_DDI(dev)) | |
441 | hsw_psr_disable(intel_dp); | |
442 | else | |
443 | vlv_psr_disable(intel_dp); | |
0bc12bcb RV |
444 | |
445 | dev_priv->psr.enabled = NULL; | |
446 | mutex_unlock(&dev_priv->psr.lock); | |
447 | ||
448 | cancel_delayed_work_sync(&dev_priv->psr.work); | |
449 | } | |
450 | ||
451 | static void intel_psr_work(struct work_struct *work) | |
452 | { | |
453 | struct drm_i915_private *dev_priv = | |
454 | container_of(work, typeof(*dev_priv), psr.work.work); | |
455 | struct intel_dp *intel_dp = dev_priv->psr.enabled; | |
995d3047 RV |
456 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
457 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
0bc12bcb RV |
458 | |
459 | /* We have to make sure PSR is ready for re-enable | |
460 | * otherwise it keeps disabled until next full enable/disable cycle. | |
461 | * PSR might take some time to get fully disabled | |
462 | * and be ready for re-enable. | |
463 | */ | |
995d3047 RV |
464 | if (HAS_DDI(dev_priv->dev)) { |
465 | if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & | |
466 | EDP_PSR_STATUS_STATE_MASK) == 0, 50)) { | |
467 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
468 | return; | |
469 | } | |
470 | } else { | |
471 | if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) & | |
472 | VLV_EDP_PSR_IN_TRANS) == 0, 1)) { | |
473 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
474 | return; | |
475 | } | |
0bc12bcb | 476 | } |
0bc12bcb RV |
477 | mutex_lock(&dev_priv->psr.lock); |
478 | intel_dp = dev_priv->psr.enabled; | |
479 | ||
480 | if (!intel_dp) | |
481 | goto unlock; | |
482 | ||
483 | /* | |
484 | * The delayed work can race with an invalidate hence we need to | |
485 | * recheck. Since psr_flush first clears this and then reschedules we | |
486 | * won't ever miss a flush when bailing out here. | |
487 | */ | |
488 | if (dev_priv->psr.busy_frontbuffer_bits) | |
489 | goto unlock; | |
490 | ||
e2bbc343 | 491 | intel_psr_activate(intel_dp); |
0bc12bcb RV |
492 | unlock: |
493 | mutex_unlock(&dev_priv->psr.lock); | |
494 | } | |
495 | ||
496 | static void intel_psr_exit(struct drm_device *dev) | |
497 | { | |
498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
995d3047 RV |
499 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
500 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
501 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
502 | u32 val; | |
0bc12bcb | 503 | |
995d3047 RV |
504 | if (!dev_priv->psr.active) |
505 | return; | |
506 | ||
507 | if (HAS_DDI(dev)) { | |
508 | val = I915_READ(EDP_PSR_CTL(dev)); | |
0bc12bcb RV |
509 | |
510 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
511 | ||
512 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); | |
513 | ||
514 | dev_priv->psr.active = false; | |
995d3047 RV |
515 | } else { |
516 | val = I915_READ(VLV_PSRCTL(pipe)); | |
517 | ||
518 | /* Here we do the transition from PSR_state 3 to PSR_state 5 | |
519 | * directly once PSR State 4 that is active with single frame | |
520 | * update can be skipped. PSR_state 5 that is PSR exit then | |
521 | * Hardware is responsible to transition back to PSR_state 1 | |
522 | * that is PSR inactive. Same state after | |
523 | * vlv_edp_psr_enable_source. | |
524 | */ | |
525 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
526 | I915_WRITE(VLV_PSRCTL(pipe), val); | |
527 | ||
528 | /* Send AUX wake up - Spec says after transitioning to PSR | |
529 | * active we have to send AUX wake up by writing 01h in DPCD | |
530 | * 600h of sink device. | |
531 | * XXX: This might slow down the transition, but without this | |
532 | * HW doesn't complete the transition to PSR_state 1 and we | |
533 | * never get the screen updated. | |
534 | */ | |
535 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, | |
536 | DP_SET_POWER_D0); | |
0bc12bcb RV |
537 | } |
538 | ||
995d3047 | 539 | dev_priv->psr.active = false; |
0bc12bcb RV |
540 | } |
541 | ||
b2b89f55 RV |
542 | /** |
543 | * intel_psr_invalidate - Invalidade PSR | |
544 | * @dev: DRM device | |
545 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
546 | * | |
547 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
548 | * with the software frontbuffer tracking. This function gets called every | |
549 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
550 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
551 | * | |
552 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
553 | */ | |
0bc12bcb RV |
554 | void intel_psr_invalidate(struct drm_device *dev, |
555 | unsigned frontbuffer_bits) | |
556 | { | |
557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
558 | struct drm_crtc *crtc; | |
559 | enum pipe pipe; | |
560 | ||
561 | mutex_lock(&dev_priv->psr.lock); | |
562 | if (!dev_priv->psr.enabled) { | |
563 | mutex_unlock(&dev_priv->psr.lock); | |
564 | return; | |
565 | } | |
566 | ||
567 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
568 | pipe = to_intel_crtc(crtc)->pipe; | |
569 | ||
570 | intel_psr_exit(dev); | |
571 | ||
572 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
573 | ||
574 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; | |
575 | mutex_unlock(&dev_priv->psr.lock); | |
576 | } | |
577 | ||
b2b89f55 RV |
578 | /** |
579 | * intel_psr_flush - Flush PSR | |
580 | * @dev: DRM device | |
581 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
582 | * | |
583 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
584 | * with the software frontbuffer tracking. This function gets called every | |
585 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
586 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
587 | * | |
588 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
589 | */ | |
0bc12bcb RV |
590 | void intel_psr_flush(struct drm_device *dev, |
591 | unsigned frontbuffer_bits) | |
592 | { | |
593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
594 | struct drm_crtc *crtc; | |
595 | enum pipe pipe; | |
596 | ||
597 | mutex_lock(&dev_priv->psr.lock); | |
598 | if (!dev_priv->psr.enabled) { | |
599 | mutex_unlock(&dev_priv->psr.lock); | |
600 | return; | |
601 | } | |
602 | ||
603 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
604 | pipe = to_intel_crtc(crtc)->pipe; | |
605 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; | |
606 | ||
607 | /* | |
608 | * On Haswell sprite plane updates don't result in a psr invalidating | |
609 | * signal in the hardware. Which means we need to manually fake this in | |
610 | * software for all flushes, not just when we've seen a preceding | |
611 | * invalidation through frontbuffer rendering. | |
612 | */ | |
613 | if (IS_HASWELL(dev) && | |
614 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) | |
615 | intel_psr_exit(dev); | |
616 | ||
995d3047 RV |
617 | /* |
618 | * On Valleyview and Cherryview we don't use hardware tracking so | |
46c3fce6 | 619 | * any plane updates or cursor moves don't result in a PSR |
995d3047 RV |
620 | * invalidating. Which means we need to manually fake this in |
621 | * software for all flushes, not just when we've seen a preceding | |
622 | * invalidation through frontbuffer rendering. */ | |
46c3fce6 | 623 | if (!HAS_DDI(dev)) |
995d3047 RV |
624 | intel_psr_exit(dev); |
625 | ||
0bc12bcb RV |
626 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
627 | schedule_delayed_work(&dev_priv->psr.work, | |
628 | msecs_to_jiffies(100)); | |
629 | mutex_unlock(&dev_priv->psr.lock); | |
630 | } | |
631 | ||
b2b89f55 RV |
632 | /** |
633 | * intel_psr_init - Init basic PSR work and mutex. | |
634 | * @dev: DRM device | |
635 | * | |
636 | * This function is called only once at driver load to initialize basic | |
637 | * PSR stuff. | |
638 | */ | |
0bc12bcb RV |
639 | void intel_psr_init(struct drm_device *dev) |
640 | { | |
641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
642 | ||
643 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); | |
644 | mutex_init(&dev_priv->psr.lock); | |
645 | } |