[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_psr.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

/**
 * DOC: Panel Self Refresh (PSR/SRD)
 *
 * Since Haswell Display controller supports Panel Self-Refresh on display
 * panels witch have a remote frame buffer (RFB) implemented according to PSR
 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
 * when system is idle but display is on as it eliminates display refresh
 * request to DDR memory completely as long as the frame buffer for that
 * display is unchanged.
 *
 * Panel Self Refresh must be supported by both Hardware (source) and
 * Panel (sink).
 *
 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
 * to power down the link and memory controller. For DSI panels the same idea
 * is called "manual mode".
 *
 * The implementation uses the hardware-based PSR support which automatically
 * enters/exits self-refresh mode. The hardware takes care of sending the
 * required DP aux message and could even retrain the link (that part isn't
 * enabled yet though). The hardware also keeps track of any frontbuffer
 * changes to know when to exit self-refresh mode again. Unfortunately that
 * part doesn't work too well, hence why the i915 PSR support uses the
 * software frontbuffer tracking to make sure it doesn't miss a screen
 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
 * get called by the frontbuffer tracking code. Note that because of locking
 * issues the self-refresh re-enable code is done from a work queue, which
 * must be correctly synchronized/cancelled when shutting down the pipe."
 */

#include <drm/drmP.h>

#include "intel_drv.h"
#include "i915_drv.h"

static bool is_edp_psr(struct intel_dp *intel_dp)
{
	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
}

static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t val;

	val = I915_READ(VLV_PSRSTAT(pipe)) &
	      VLV_EDP_PSR_CURR_STATE_MASK;
	return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
	       (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
}

static void intel_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	uint32_t val;

	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
	val  = I915_READ(VLV_VSCSDP(pipe));
	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
	val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
	I915_WRITE(VLV_VSCSDP(pipe), val);
}

static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
{
	struct edp_vsc_psr psr_vsc;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_psr_write_vsc(intel_dp, &psr_vsc);
}

static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
{
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
			   DP_PSR_ENABLE);
}

static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t aux_clock_divider;
	int precharge = 0x3;
	bool only_standby = dev_priv->vbt.psr.full_link;
	static const uint8_t aux_msg[] = {
		[0] = DP_AUX_NATIVE_WRITE << 4,
		[1] = DP_SET_POWER >> 8,
		[2] = DP_SET_POWER & 0xff,
		[3] = 1 - 1,
		[4] = DP_SET_POWER_D0,
	};
	int i;

	BUILD_BUG_ON(sizeof(aux_msg) > 20);

	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;

	/* Enable PSR in sink */
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
	else
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);

	/* Setup AUX registers */
	for (i = 0; i < sizeof(aux_msg); i += 4)
		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));

	I915_WRITE(EDP_PSR_AUX_CTL(dev),
		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void vlv_psr_enable_source(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	enum pipe pipe = to_intel_crtc(crtc)->pipe;

	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
	I915_WRITE(VLV_PSRCTL(pipe),
		   VLV_EDP_PSR_MODE_SW_TIMER |
		   VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
		   VLV_EDP_PSR_ENABLE);
}

static void hsw_psr_enable_source(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	/* Lately it was identified that depending on panel idle frame count
	 * calculated at HW can be off by 1. So let's use what came
	 * from VBT + 1 and at minimum 2 to be on the safe side.
	 */
	uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
			       dev_priv->vbt.psr.idle_frames + 1 : 2;
	uint32_t val = 0x0;
	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
	bool only_standby = false;

	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;

	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
	} else
		val |= EDP_PSR_LINK_DISABLE;

	I915_WRITE(EDP_PSR_CTL(dev), val |
		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	lockdep_assert_held(&dev_priv->psr.lock);
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));

	dev_priv->psr.source_ok = false;

	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

	if (!i915.enable_psr) {
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

	/* Below limitations aren't valid for Broadwell */
	if (IS_BROADWELL(dev))
		goto out;

	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

 out:
	dev_priv->psr.source_ok = true;
	return true;
}

static void intel_psr_activate(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	WARN_ON(dev_priv->psr.active);
	lockdep_assert_held(&dev_priv->psr.lock);

	/* Enable/Re-enable PSR on the host
	 * On HSW+ after we enable PSR on source it will activate it
	 * as soon as it match configure idle_frame count. So
	 * we just actually enable it here on activation time.
	 */
	hsw_psr_enable_source(intel_dp);
	dev_priv->psr.active = true;
}

/**
 * intel_psr_enable - Enable PSR
 * @intel_dp: Intel DP
 *
 * This function can only be called after the pipe is fully trained and enabled.
 */
void intel_psr_enable(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!HAS_PSR(dev)) {
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return;
	}

	if (!is_edp_psr(intel_dp)) {
		DRM_DEBUG_KMS("PSR not supported by this panel\n");
		return;
	}

	mutex_lock(&dev_priv->psr.lock);
	if (dev_priv->psr.enabled) {
		DRM_DEBUG_KMS("PSR already in use\n");
		goto unlock;
	}

	if (!intel_psr_match_conditions(intel_dp))
		goto unlock;

	dev_priv->psr.busy_frontbuffer_bits = 0;

	if (HAS_DDI(dev)) {
		hsw_psr_setup_vsc(intel_dp);

		/* Avoid continuous PSR exit by masking memup and hpd */
		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);

		/* Enable PSR on the panel */
		hsw_psr_enable_sink(intel_dp);
	} else {
		vlv_psr_setup_vsc(intel_dp);

		/* Enable PSR on the panel */
		vlv_psr_enable_sink(intel_dp);

		/* On HSW+ enable_source also means go to PSR entry/active
		 * state as soon as idle_frame achieved and here would be
		 * to soon. However on VLV enable_source just enable PSR
		 * but let it on inactive state. So we might do this prior
		 * to active transition, i.e. here.
		 */
		vlv_psr_enable_source(intel_dp);
	}

	dev_priv->psr.enabled = intel_dp;
unlock:
	mutex_unlock(&dev_priv->psr.lock);
}

static void vlv_psr_disable(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
	uint32_t val;

	if (dev_priv->psr.active) {
		/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
		if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
			      VLV_EDP_PSR_IN_TRANS) == 0, 1))
			WARN(1, "PSR transition took longer than expected\n");

		val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
		val &= ~VLV_EDP_PSR_ENABLE;
		val &= ~VLV_EDP_PSR_MODE_MASK;
		I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);

		dev_priv->psr.active = false;
	} else {
		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
	}
}

static void hsw_psr_disable(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->psr.active) {
		I915_WRITE(EDP_PSR_CTL(dev),
			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);

		/* Wait till PSR is idle */
		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
			DRM_ERROR("Timed out waiting for PSR Idle State\n");

		dev_priv->psr.active = false;
	} else {
		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	}
}

/**
 * intel_psr_disable - Disable PSR
 * @intel_dp: Intel DP
 *
 * This function needs to be called before disabling pipe.
 */
void intel_psr_disable(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	if (HAS_DDI(dev))
		hsw_psr_disable(intel_dp);
	else
		vlv_psr_disable(intel_dp);

	dev_priv->psr.enabled = NULL;
	mutex_unlock(&dev_priv->psr.lock);

	cancel_delayed_work_sync(&dev_priv->psr.work);
}

static void intel_psr_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), psr.work.work);
	struct intel_dp *intel_dp = dev_priv->psr.enabled;

	/* We have to make sure PSR is ready for re-enable
	 * otherwise it keeps disabled until next full enable/disable cycle.
	 * PSR might take some time to get fully disabled
	 * and be ready for re-enable.
	 */
	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
		return;
	}

	mutex_lock(&dev_priv->psr.lock);
	intel_dp = dev_priv->psr.enabled;

	if (!intel_dp)
		goto unlock;

	/*
	 * The delayed work can race with an invalidate hence we need to
	 * recheck. Since psr_flush first clears this and then reschedules we
	 * won't ever miss a flush when bailing out here.
	 */
	if (dev_priv->psr.busy_frontbuffer_bits)
		goto unlock;

	intel_psr_activate(intel_dp);
unlock:
	mutex_unlock(&dev_priv->psr.lock);
}

static void intel_psr_exit(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->psr.active) {
		u32 val = I915_READ(EDP_PSR_CTL(dev));

		WARN_ON(!(val & EDP_PSR_ENABLE));

		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);

		dev_priv->psr.active = false;
	}

}

/**
 * intel_psr_invalidate - Invalidade PSR
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
 * Since the hardware frontbuffer tracking has gaps we need to integrate
 * with the software frontbuffer tracking. This function gets called every
 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 *
 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 */
void intel_psr_invalidate(struct drm_device *dev,
			      unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

	intel_psr_exit(dev);

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
	mutex_unlock(&dev_priv->psr.lock);
}

/**
 * intel_psr_flush - Flush PSR
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
 * Since the hardware frontbuffer tracking has gaps we need to integrate
 * with the software frontbuffer tracking. This function gets called every
 * time frontbuffer rendering has completed and flushed out to memory. PSR
 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 *
 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 */
void intel_psr_flush(struct drm_device *dev,
			 unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;

	/*
	 * On Haswell sprite plane updates don't result in a psr invalidating
	 * signal in the hardware. Which means we need to manually fake this in
	 * software for all flushes, not just when we've seen a preceding
	 * invalidation through frontbuffer rendering.
	 */
	if (IS_HASWELL(dev) &&
	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
		intel_psr_exit(dev);

	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
		schedule_delayed_work(&dev_priv->psr.work,
				      msecs_to_jiffies(100));
	mutex_unlock(&dev_priv->psr.lock);
}

/**
 * intel_psr_init - Init basic PSR work and mutex.
 * @dev: DRM device
 *
 * This function is  called only once at driver load to initialize basic
 * PSR stuff.
 */
void intel_psr_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
	mutex_init(&dev_priv->psr.lock);
}
Commit	Line	Data
0bc12bcb RV	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
b2b89f55 RV	24	/**
	25	* DOC: Panel Self Refresh (PSR/SRD)
	26	*
	27	* Since Haswell Display controller supports Panel Self-Refresh on display
	28	* panels witch have a remote frame buffer (RFB) implemented according to PSR
	29	* spec in eDP1.3. PSR feature allows the display to go to lower standby states
	30	* when system is idle but display is on as it eliminates display refresh
	31	* request to DDR memory completely as long as the frame buffer for that
	32	* display is unchanged.
	33	*
	34	* Panel Self Refresh must be supported by both Hardware (source) and
	35	* Panel (sink).
	36	*
	37	* PSR saves power by caching the framebuffer in the panel RFB, which allows us
	38	* to power down the link and memory controller. For DSI panels the same idea
	39	* is called "manual mode".
	40	*
	41	* The implementation uses the hardware-based PSR support which automatically
	42	* enters/exits self-refresh mode. The hardware takes care of sending the
	43	* required DP aux message and could even retrain the link (that part isn't
	44	* enabled yet though). The hardware also keeps track of any frontbuffer
	45	* changes to know when to exit self-refresh mode again. Unfortunately that
	46	* part doesn't work too well, hence why the i915 PSR support uses the
	47	* software frontbuffer tracking to make sure it doesn't miss a screen
	48	* update. For this integration intel_psr_invalidate() and intel_psr_flush()
	49	* get called by the frontbuffer tracking code. Note that because of locking
	50	* issues the self-refresh re-enable code is done from a work queue, which
	51	* must be correctly synchronized/cancelled when shutting down the pipe."
	52	*/
	53
0bc12bcb RV	54	#include <drm/drmP.h>
	55
	56	#include "intel_drv.h"
	57	#include "i915_drv.h"
	58
	59	static bool is_edp_psr(struct intel_dp *intel_dp)
	60	{
	61	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
	62	}
	63
e2bbc343 RV	64	static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
	65	{
	66	struct drm_i915_private *dev_priv = dev->dev_private;
	67	uint32_t val;
	68
	69	val = I915_READ(VLV_PSRSTAT(pipe)) &
	70	VLV_EDP_PSR_CURR_STATE_MASK;
	71	return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) \|\|
	72	(val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
	73	}
	74
0bc12bcb RV	75	static void intel_psr_write_vsc(struct intel_dp *intel_dp,
	76	struct edp_vsc_psr *vsc_psr)
	77	{
	78	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	79	struct drm_device *dev = dig_port->base.base.dev;
	80	struct drm_i915_private *dev_priv = dev->dev_private;
	81	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	82	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	83	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	84	uint32_t data = (uint32_t ) vsc_psr;
	85	unsigned int i;
	86
	87	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	88	the video DIP being updated before program video DIP data buffer
	89	registers for DIP being updated. */
	90	I915_WRITE(ctl_reg, 0);
	91	POSTING_READ(ctl_reg);
	92
	93	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
	94	if (i < sizeof(struct edp_vsc_psr))
	95	I915_WRITE(data_reg + i, *data++);
	96	else
	97	I915_WRITE(data_reg + i, 0);
	98	}
	99
	100	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	101	POSTING_READ(ctl_reg);
	102	}
	103
e2bbc343 RV	104	static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
	105	{
	106	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	107	struct drm_device *dev = intel_dig_port->base.base.dev;
	108	struct drm_i915_private *dev_priv = dev->dev_private;
	109	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	110	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	111	uint32_t val;
	112
	113	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
	114	val = I915_READ(VLV_VSCSDP(pipe));
	115	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
	116	val \|= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
	117	I915_WRITE(VLV_VSCSDP(pipe), val);
	118	}
	119
	120	static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
0bc12bcb RV	121	{
	122	struct edp_vsc_psr psr_vsc;
	123
	124	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	125	memset(&psr_vsc, 0, sizeof(psr_vsc));
	126	psr_vsc.sdp_header.HB0 = 0;
	127	psr_vsc.sdp_header.HB1 = 0x7;
	128	psr_vsc.sdp_header.HB2 = 0x2;
	129	psr_vsc.sdp_header.HB3 = 0x8;
	130	intel_psr_write_vsc(intel_dp, &psr_vsc);
	131	}
	132
e2bbc343 RV	133	static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
	134	{
	135	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
	136	DP_PSR_ENABLE);
	137	}
	138
	139	static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
0bc12bcb RV	140	{
	141	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	142	struct drm_device *dev = dig_port->base.base.dev;
	143	struct drm_i915_private *dev_priv = dev->dev_private;
	144	uint32_t aux_clock_divider;
	145	int precharge = 0x3;
8cc726c9	146	bool only_standby = dev_priv->vbt.psr.full_link;
0bc12bcb RV	147	static const uint8_t aux_msg[] = {
	148	[0] = DP_AUX_NATIVE_WRITE << 4,
	149	[1] = DP_SET_POWER >> 8,
	150	[2] = DP_SET_POWER & 0xff,
	151	[3] = 1 - 1,
	152	[4] = DP_SET_POWER_D0,
	153	};
	154	int i;
	155
	156	BUILD_BUG_ON(sizeof(aux_msg) > 20);
	157
	158	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
	159
	160	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
	161	only_standby = true;
	162
	163	/* Enable PSR in sink */
	164	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT \|\| only_standby)
	165	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
	166	DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
	167	else
	168	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
	169	DP_PSR_ENABLE \| DP_PSR_MAIN_LINK_ACTIVE);
	170
	171	/* Setup AUX registers */
	172	for (i = 0; i < sizeof(aux_msg); i += 4)
	173	I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
	174	intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
	175
	176	I915_WRITE(EDP_PSR_AUX_CTL(dev),
	177	DP_AUX_CH_CTL_TIME_OUT_400us \|
	178	(sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) \|
	179	(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) \|
	180	(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
	181	}
	182
e2bbc343 RV	183	static void vlv_psr_enable_source(struct intel_dp *intel_dp)
	184	{
	185	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	186	struct drm_device *dev = dig_port->base.base.dev;
	187	struct drm_i915_private *dev_priv = dev->dev_private;
	188	struct drm_crtc *crtc = dig_port->base.base.crtc;
	189	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	190
	191	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
	192	I915_WRITE(VLV_PSRCTL(pipe),
	193	VLV_EDP_PSR_MODE_SW_TIMER \|
	194	VLV_EDP_PSR_SRC_TRANSMITTER_STATE \|
	195	VLV_EDP_PSR_ENABLE);
	196	}
	197
	198	static void hsw_psr_enable_source(struct intel_dp *intel_dp)
0bc12bcb RV	199	{
	200	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	201	struct drm_device *dev = dig_port->base.base.dev;
	202	struct drm_i915_private *dev_priv = dev->dev_private;
	203	uint32_t max_sleep_time = 0x1f;
d44b4dcb RV	204	/* Lately it was identified that depending on panel idle frame count
	205	* calculated at HW can be off by 1. So let's use what came
	206	* from VBT + 1 and at minimum 2 to be on the safe side.
	207	*/
	208	uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
	209	dev_priv->vbt.psr.idle_frames + 1 : 2;
0bc12bcb RV	210	uint32_t val = 0x0;
	211	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
	212	bool only_standby = false;
	213
	214	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
	215	only_standby = true;
	216
	217	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT \|\| only_standby) {
	218	val \|= EDP_PSR_LINK_STANDBY;
	219	val \|= EDP_PSR_TP2_TP3_TIME_0us;
	220	val \|= EDP_PSR_TP1_TIME_0us;
	221	val \|= EDP_PSR_SKIP_AUX_EXIT;
0bc12bcb RV	222	} else
	223	val \|= EDP_PSR_LINK_DISABLE;
	224
	225	I915_WRITE(EDP_PSR_CTL(dev), val \|
	226	(IS_BROADWELL(dev) ? 0 : link_entry_time) \|
	227	max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT \|
	228	idle_frames << EDP_PSR_IDLE_FRAME_SHIFT \|
	229	EDP_PSR_ENABLE);
	230	}
	231
	232	static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
	233	{
	234	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	235	struct drm_device *dev = dig_port->base.base.dev;
	236	struct drm_i915_private *dev_priv = dev->dev_private;
	237	struct drm_crtc *crtc = dig_port->base.base.crtc;
	238	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	239
	240	lockdep_assert_held(&dev_priv->psr.lock);
	241	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
	242	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
	243
	244	dev_priv->psr.source_ok = false;
	245
	246	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
	247	DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
	248	return false;
	249	}
	250
	251	if (!i915.enable_psr) {
	252	DRM_DEBUG_KMS("PSR disable by flag\n");
	253	return false;
	254	}
	255
	256	/* Below limitations aren't valid for Broadwell */
	257	if (IS_BROADWELL(dev))
	258	goto out;
	259
	260	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	261	S3D_ENABLE) {
	262	DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
	263	return false;
	264	}
	265
	266	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
	267	DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
	268	return false;
	269	}
	270
	271	out:
	272	dev_priv->psr.source_ok = true;
	273	return true;
	274	}
	275
e2bbc343	276	static void intel_psr_activate(struct intel_dp *intel_dp)
0bc12bcb RV	277	{
	278	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	279	struct drm_device *dev = intel_dig_port->base.base.dev;
	280	struct drm_i915_private *dev_priv = dev->dev_private;
	281
	282	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	283	WARN_ON(dev_priv->psr.active);
	284	lockdep_assert_held(&dev_priv->psr.lock);
	285
e2bbc343 RV	286	/* Enable/Re-enable PSR on the host
	287	* On HSW+ after we enable PSR on source it will activate it
	288	* as soon as it match configure idle_frame count. So
	289	* we just actually enable it here on activation time.
	290	*/
	291	hsw_psr_enable_source(intel_dp);
0bc12bcb RV	292	dev_priv->psr.active = true;
	293	}
	294
b2b89f55 RV	295	/**
	296	* intel_psr_enable - Enable PSR
	297	* @intel_dp: Intel DP
	298	*
	299	* This function can only be called after the pipe is fully trained and enabled.
	300	*/
0bc12bcb RV	301	void intel_psr_enable(struct intel_dp *intel_dp)
	302	{
	303	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	304	struct drm_device *dev = intel_dig_port->base.base.dev;
	305	struct drm_i915_private *dev_priv = dev->dev_private;
	306
	307	if (!HAS_PSR(dev)) {
	308	DRM_DEBUG_KMS("PSR not supported on this platform\n");
	309	return;
	310	}
	311
	312	if (!is_edp_psr(intel_dp)) {
	313	DRM_DEBUG_KMS("PSR not supported by this panel\n");
	314	return;
	315	}
	316
	317	mutex_lock(&dev_priv->psr.lock);
	318	if (dev_priv->psr.enabled) {
	319	DRM_DEBUG_KMS("PSR already in use\n");
	320	goto unlock;
	321	}
	322
	323	if (!intel_psr_match_conditions(intel_dp))
	324	goto unlock;
	325
	326	dev_priv->psr.busy_frontbuffer_bits = 0;
	327
e2bbc343 RV	328	if (HAS_DDI(dev)) {
e2bbc343 RV	329	hsw_psr_setup_vsc(intel_dp);
0bc12bcb	330
e2bbc343 RV	331	/* Avoid continuous PSR exit by masking memup and hpd */
	332	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP \|
	333	EDP_PSR_DEBUG_MASK_HPD \| EDP_PSR_DEBUG_MASK_LPSP);
0bc12bcb	334
e2bbc343 RV	335	/* Enable PSR on the panel */
	336	hsw_psr_enable_sink(intel_dp);
	337	} else {
	338	vlv_psr_setup_vsc(intel_dp);
	339
	340	/* Enable PSR on the panel */
	341	vlv_psr_enable_sink(intel_dp);
	342
	343	/* On HSW+ enable_source also means go to PSR entry/active
	344	* state as soon as idle_frame achieved and here would be
	345	* to soon. However on VLV enable_source just enable PSR
	346	* but let it on inactive state. So we might do this prior
	347	* to active transition, i.e. here.
	348	*/
	349	vlv_psr_enable_source(intel_dp);
	350	}
0bc12bcb RV	351
	352	dev_priv->psr.enabled = intel_dp;
	353	unlock:
	354	mutex_unlock(&dev_priv->psr.lock);
	355	}
	356
e2bbc343	357	static void vlv_psr_disable(struct intel_dp *intel_dp)
0bc12bcb RV	358	{
	359	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	360	struct drm_device *dev = intel_dig_port->base.base.dev;
	361	struct drm_i915_private *dev_priv = dev->dev_private;
e2bbc343 RV	362	struct intel_crtc *intel_crtc =
	363	to_intel_crtc(intel_dig_port->base.base.crtc);
	364	uint32_t val;
0bc12bcb	365
e2bbc343 RV	366	if (dev_priv->psr.active) {
	367	/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
	368	if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
	369	VLV_EDP_PSR_IN_TRANS) == 0, 1))
	370	WARN(1, "PSR transition took longer than expected\n");
	371
	372	val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
	373	val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
	374	val &= ~VLV_EDP_PSR_ENABLE;
	375	val &= ~VLV_EDP_PSR_MODE_MASK;
	376	I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
	377
	378	dev_priv->psr.active = false;
	379	} else {
	380	WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
0bc12bcb	381	}
e2bbc343 RV	382	}
	383
	384	static void hsw_psr_disable(struct intel_dp *intel_dp)
	385	{
	386	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	387	struct drm_device *dev = intel_dig_port->base.base.dev;
	388	struct drm_i915_private *dev_priv = dev->dev_private;
0bc12bcb RV	389
	390	if (dev_priv->psr.active) {
	391	I915_WRITE(EDP_PSR_CTL(dev),
	392	I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
	393
	394	/* Wait till PSR is idle */
	395	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
	396	EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
	397	DRM_ERROR("Timed out waiting for PSR Idle State\n");
	398
	399	dev_priv->psr.active = false;
	400	} else {
	401	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	402	}
e2bbc343 RV	403	}
	404
	405	/**
	406	* intel_psr_disable - Disable PSR
	407	* @intel_dp: Intel DP
	408	*
	409	* This function needs to be called before disabling pipe.
	410	*/
	411	void intel_psr_disable(struct intel_dp *intel_dp)
	412	{
	413	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	414	struct drm_device *dev = intel_dig_port->base.base.dev;
	415	struct drm_i915_private *dev_priv = dev->dev_private;
	416
	417	mutex_lock(&dev_priv->psr.lock);
	418	if (!dev_priv->psr.enabled) {
	419	mutex_unlock(&dev_priv->psr.lock);
	420	return;
	421	}
	422
	423	if (HAS_DDI(dev))
	424	hsw_psr_disable(intel_dp);
	425	else
	426	vlv_psr_disable(intel_dp);
0bc12bcb RV	427
	428	dev_priv->psr.enabled = NULL;
	429	mutex_unlock(&dev_priv->psr.lock);
	430
	431	cancel_delayed_work_sync(&dev_priv->psr.work);
	432	}
	433
	434	static void intel_psr_work(struct work_struct *work)
	435	{
	436	struct drm_i915_private *dev_priv =
	437	container_of(work, typeof(*dev_priv), psr.work.work);
	438	struct intel_dp *intel_dp = dev_priv->psr.enabled;
	439
	440	/* We have to make sure PSR is ready for re-enable
	441	* otherwise it keeps disabled until next full enable/disable cycle.
	442	* PSR might take some time to get fully disabled
	443	* and be ready for re-enable.
	444	*/
	445	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
	446	EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
	447	DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
	448	return;
	449	}
	450
	451	mutex_lock(&dev_priv->psr.lock);
	452	intel_dp = dev_priv->psr.enabled;
	453
	454	if (!intel_dp)
	455	goto unlock;
	456
	457	/*
	458	* The delayed work can race with an invalidate hence we need to
	459	* recheck. Since psr_flush first clears this and then reschedules we
	460	* won't ever miss a flush when bailing out here.
	461	*/
	462	if (dev_priv->psr.busy_frontbuffer_bits)
	463	goto unlock;
	464
e2bbc343	465	intel_psr_activate(intel_dp);
0bc12bcb RV	466	unlock:
	467	mutex_unlock(&dev_priv->psr.lock);
	468	}
	469
	470	static void intel_psr_exit(struct drm_device *dev)
	471	{
	472	struct drm_i915_private *dev_priv = dev->dev_private;
	473
	474	if (dev_priv->psr.active) {
	475	u32 val = I915_READ(EDP_PSR_CTL(dev));
	476
	477	WARN_ON(!(val & EDP_PSR_ENABLE));
	478
	479	I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
	480
	481	dev_priv->psr.active = false;
	482	}
	483
	484	}
	485
b2b89f55 RV	486	/**
	487	* intel_psr_invalidate - Invalidade PSR
	488	* @dev: DRM device
	489	* @frontbuffer_bits: frontbuffer plane tracking bits
	490	*
	491	* Since the hardware frontbuffer tracking has gaps we need to integrate
	492	* with the software frontbuffer tracking. This function gets called every
	493	* time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
	494	* disabled if the frontbuffer mask contains a buffer relevant to PSR.
	495	*
	496	* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
	497	*/
0bc12bcb RV	498	void intel_psr_invalidate(struct drm_device *dev,
	499	unsigned frontbuffer_bits)
	500	{
	501	struct drm_i915_private *dev_priv = dev->dev_private;
	502	struct drm_crtc *crtc;
	503	enum pipe pipe;
	504
	505	mutex_lock(&dev_priv->psr.lock);
	506	if (!dev_priv->psr.enabled) {
	507	mutex_unlock(&dev_priv->psr.lock);
	508	return;
	509	}
	510
	511	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	512	pipe = to_intel_crtc(crtc)->pipe;
	513
	514	intel_psr_exit(dev);
	515
	516	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	517
	518	dev_priv->psr.busy_frontbuffer_bits \|= frontbuffer_bits;
	519	mutex_unlock(&dev_priv->psr.lock);
	520	}
	521
b2b89f55 RV	522	/**
	523	* intel_psr_flush - Flush PSR
	524	* @dev: DRM device
	525	* @frontbuffer_bits: frontbuffer plane tracking bits
	526	*
	527	* Since the hardware frontbuffer tracking has gaps we need to integrate
	528	* with the software frontbuffer tracking. This function gets called every
	529	* time frontbuffer rendering has completed and flushed out to memory. PSR
	530	* can be enabled again if no other frontbuffer relevant to PSR is dirty.
	531	*
	532	* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
	533	*/
0bc12bcb RV	534	void intel_psr_flush(struct drm_device *dev,
	535	unsigned frontbuffer_bits)
	536	{
	537	struct drm_i915_private *dev_priv = dev->dev_private;
	538	struct drm_crtc *crtc;
	539	enum pipe pipe;
	540
	541	mutex_lock(&dev_priv->psr.lock);
	542	if (!dev_priv->psr.enabled) {
	543	mutex_unlock(&dev_priv->psr.lock);
	544	return;
	545	}
	546
	547	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	548	pipe = to_intel_crtc(crtc)->pipe;
	549	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
	550
	551	/*
	552	* On Haswell sprite plane updates don't result in a psr invalidating
	553	* signal in the hardware. Which means we need to manually fake this in
	554	* software for all flushes, not just when we've seen a preceding
	555	* invalidation through frontbuffer rendering.
	556	*/
	557	if (IS_HASWELL(dev) &&
	558	(frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
	559	intel_psr_exit(dev);
	560
	561	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
	562	schedule_delayed_work(&dev_priv->psr.work,
	563	msecs_to_jiffies(100));
	564	mutex_unlock(&dev_priv->psr.lock);
	565	}
	566
b2b89f55 RV	567	/**
	568	* intel_psr_init - Init basic PSR work and mutex.
	569	* @dev: DRM device
	570	*
	571	* This function is called only once at driver load to initialize basic
	572	* PSR stuff.
	573	*/
0bc12bcb RV	574	void intel_psr_init(struct drm_device *dev)
	575	{
	576	struct drm_i915_private *dev_priv = dev->dev_private;
	577
	578	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
	579	mutex_init(&dev_priv->psr.lock);
	580	}