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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
82e104cc | 37 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 38 | { |
4f54741e DG |
39 | int space = head - tail; |
40 | if (space <= 0) | |
1cf0ba14 | 41 | space += size; |
4f54741e | 42 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
43 | } |
44 | ||
ebd0fd4b DG |
45 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
46 | { | |
47 | if (ringbuf->last_retired_head != -1) { | |
48 | ringbuf->head = ringbuf->last_retired_head; | |
49 | ringbuf->last_retired_head = -1; | |
50 | } | |
51 | ||
52 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
53 | ringbuf->tail, ringbuf->size); | |
54 | } | |
55 | ||
117897f4 | 56 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 57 | { |
0bc40be8 | 58 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
666796da | 59 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 60 | } |
09246732 | 61 | |
0bc40be8 | 62 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 63 | { |
0bc40be8 | 64 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 65 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 66 | if (intel_engine_stopped(engine)) |
09246732 | 67 | return; |
0bc40be8 | 68 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
69 | } |
70 | ||
b72f3acb | 71 | static int |
a84c3ae1 | 72 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
73 | u32 invalidate_domains, |
74 | u32 flush_domains) | |
75 | { | |
4a570db5 | 76 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
77 | u32 cmd; |
78 | int ret; | |
79 | ||
80 | cmd = MI_FLUSH; | |
31b14c9f | 81 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
82 | cmd |= MI_NO_WRITE_FLUSH; |
83 | ||
84 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
85 | cmd |= MI_READ_FLUSH; | |
86 | ||
5fb9de1a | 87 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
88 | if (ret) |
89 | return ret; | |
90 | ||
e2f80391 TU |
91 | intel_ring_emit(engine, cmd); |
92 | intel_ring_emit(engine, MI_NOOP); | |
93 | intel_ring_advance(engine); | |
46f0f8d1 CW |
94 | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static int | |
a84c3ae1 | 99 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
100 | u32 invalidate_domains, |
101 | u32 flush_domains) | |
62fdfeaf | 102 | { |
4a570db5 | 103 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 104 | struct drm_device *dev = engine->dev; |
6f392d54 | 105 | u32 cmd; |
b72f3acb | 106 | int ret; |
6f392d54 | 107 | |
36d527de CW |
108 | /* |
109 | * read/write caches: | |
110 | * | |
111 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
112 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
113 | * also flushed at 2d versus 3d pipeline switches. | |
114 | * | |
115 | * read-only caches: | |
116 | * | |
117 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
118 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
119 | * | |
120 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
121 | * | |
122 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
123 | * invalidated when MI_EXE_FLUSH is set. | |
124 | * | |
125 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
126 | * invalidated with every MI_FLUSH. | |
127 | * | |
128 | * TLBs: | |
129 | * | |
130 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
131 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
132 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
133 | * are flushed at any MI_FLUSH. | |
134 | */ | |
135 | ||
136 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 137 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 138 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
139 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
140 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 141 | |
36d527de CW |
142 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
143 | (IS_G4X(dev) || IS_GEN5(dev))) | |
144 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 145 | |
5fb9de1a | 146 | ret = intel_ring_begin(req, 2); |
36d527de CW |
147 | if (ret) |
148 | return ret; | |
b72f3acb | 149 | |
e2f80391 TU |
150 | intel_ring_emit(engine, cmd); |
151 | intel_ring_emit(engine, MI_NOOP); | |
152 | intel_ring_advance(engine); | |
b72f3acb CW |
153 | |
154 | return 0; | |
8187a2b7 ZN |
155 | } |
156 | ||
8d315287 JB |
157 | /** |
158 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
159 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
160 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
161 | * | |
162 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
163 | * produced by non-pipelined state commands), software needs to first | |
164 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
165 | * 0. | |
166 | * | |
167 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
168 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
169 | * | |
170 | * And the workaround for these two requires this workaround first: | |
171 | * | |
172 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
173 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
174 | * flushes. | |
175 | * | |
176 | * And this last workaround is tricky because of the requirements on | |
177 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
178 | * volume 2 part 1: | |
179 | * | |
180 | * "1 of the following must also be set: | |
181 | * - Render Target Cache Flush Enable ([12] of DW1) | |
182 | * - Depth Cache Flush Enable ([0] of DW1) | |
183 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
184 | * - Depth Stall ([13] of DW1) | |
185 | * - Post-Sync Operation ([13] of DW1) | |
186 | * - Notify Enable ([8] of DW1)" | |
187 | * | |
188 | * The cache flushes require the workaround flush that triggered this | |
189 | * one, so we can't use it. Depth stall would trigger the same. | |
190 | * Post-sync nonzero is what triggered this second workaround, so we | |
191 | * can't use that one either. Notify enable is IRQs, which aren't | |
192 | * really our business. That leaves only stall at scoreboard. | |
193 | */ | |
194 | static int | |
f2cf1fcc | 195 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 196 | { |
4a570db5 | 197 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 198 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
199 | int ret; |
200 | ||
5fb9de1a | 201 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
202 | if (ret) |
203 | return ret; | |
204 | ||
e2f80391 TU |
205 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
206 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 207 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
208 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
209 | intel_ring_emit(engine, 0); /* low dword */ | |
210 | intel_ring_emit(engine, 0); /* high dword */ | |
211 | intel_ring_emit(engine, MI_NOOP); | |
212 | intel_ring_advance(engine); | |
8d315287 | 213 | |
5fb9de1a | 214 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
215 | if (ret) |
216 | return ret; | |
217 | ||
e2f80391 TU |
218 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
219 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
220 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
221 | intel_ring_emit(engine, 0); | |
222 | intel_ring_emit(engine, 0); | |
223 | intel_ring_emit(engine, MI_NOOP); | |
224 | intel_ring_advance(engine); | |
8d315287 JB |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int | |
a84c3ae1 JH |
230 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
231 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 232 | { |
4a570db5 | 233 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 234 | u32 flags = 0; |
e2f80391 | 235 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
236 | int ret; |
237 | ||
b3111509 | 238 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 239 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
240 | if (ret) |
241 | return ret; | |
242 | ||
8d315287 JB |
243 | /* Just flush everything. Experiments have shown that reducing the |
244 | * number of bits based on the write domains has little performance | |
245 | * impact. | |
246 | */ | |
7d54a904 CW |
247 | if (flush_domains) { |
248 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
249 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
250 | /* | |
251 | * Ensure that any following seqno writes only happen | |
252 | * when the render cache is indeed flushed. | |
253 | */ | |
97f209bc | 254 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
255 | } |
256 | if (invalidate_domains) { | |
257 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
258 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
259 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
260 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
261 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
262 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
263 | /* | |
264 | * TLB invalidate requires a post-sync write. | |
265 | */ | |
3ac78313 | 266 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 267 | } |
8d315287 | 268 | |
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
270 | if (ret) |
271 | return ret; | |
272 | ||
e2f80391 TU |
273 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(engine, flags); | |
275 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
276 | intel_ring_emit(engine, 0); | |
277 | intel_ring_advance(engine); | |
8d315287 JB |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
f3987631 | 282 | static int |
f2cf1fcc | 283 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 284 | { |
4a570db5 | 285 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
286 | int ret; |
287 | ||
5fb9de1a | 288 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
289 | if (ret) |
290 | return ret; | |
291 | ||
e2f80391 TU |
292 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
293 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 294 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
295 | intel_ring_emit(engine, 0); |
296 | intel_ring_emit(engine, 0); | |
297 | intel_ring_advance(engine); | |
f3987631 PZ |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
4772eaeb | 302 | static int |
a84c3ae1 | 303 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
304 | u32 invalidate_domains, u32 flush_domains) |
305 | { | |
4a570db5 | 306 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 307 | u32 flags = 0; |
e2f80391 | 308 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
309 | int ret; |
310 | ||
f3987631 PZ |
311 | /* |
312 | * Ensure that any following seqno writes only happen when the render | |
313 | * cache is indeed flushed. | |
314 | * | |
315 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
316 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
317 | * don't try to be clever and just set it unconditionally. | |
318 | */ | |
319 | flags |= PIPE_CONTROL_CS_STALL; | |
320 | ||
4772eaeb PZ |
321 | /* Just flush everything. Experiments have shown that reducing the |
322 | * number of bits based on the write domains has little performance | |
323 | * impact. | |
324 | */ | |
325 | if (flush_domains) { | |
326 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
327 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 328 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 329 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
330 | } |
331 | if (invalidate_domains) { | |
332 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
335 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
336 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
337 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 338 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
339 | /* |
340 | * TLB invalidate requires a post-sync write. | |
341 | */ | |
342 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 343 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 344 | |
add284a3 CW |
345 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
346 | ||
f3987631 PZ |
347 | /* Workaround: we must issue a pipe_control with CS-stall bit |
348 | * set before a pipe_control command that has the state cache | |
349 | * invalidate bit set. */ | |
f2cf1fcc | 350 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
351 | } |
352 | ||
5fb9de1a | 353 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
354 | if (ret) |
355 | return ret; | |
356 | ||
e2f80391 TU |
357 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
358 | intel_ring_emit(engine, flags); | |
359 | intel_ring_emit(engine, scratch_addr); | |
360 | intel_ring_emit(engine, 0); | |
361 | intel_ring_advance(engine); | |
4772eaeb PZ |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
884ceace | 366 | static int |
f2cf1fcc | 367 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
368 | u32 flags, u32 scratch_addr) |
369 | { | |
4a570db5 | 370 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
371 | int ret; |
372 | ||
5fb9de1a | 373 | ret = intel_ring_begin(req, 6); |
884ceace KG |
374 | if (ret) |
375 | return ret; | |
376 | ||
e2f80391 TU |
377 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
378 | intel_ring_emit(engine, flags); | |
379 | intel_ring_emit(engine, scratch_addr); | |
380 | intel_ring_emit(engine, 0); | |
381 | intel_ring_emit(engine, 0); | |
382 | intel_ring_emit(engine, 0); | |
383 | intel_ring_advance(engine); | |
884ceace KG |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
a5f3d68e | 388 | static int |
a84c3ae1 | 389 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
390 | u32 invalidate_domains, u32 flush_domains) |
391 | { | |
392 | u32 flags = 0; | |
4a570db5 | 393 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 394 | int ret; |
a5f3d68e BW |
395 | |
396 | flags |= PIPE_CONTROL_CS_STALL; | |
397 | ||
398 | if (flush_domains) { | |
399 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
400 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 401 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 402 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
403 | } |
404 | if (invalidate_domains) { | |
405 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
406 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
407 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
408 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
409 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
410 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
411 | flags |= PIPE_CONTROL_QW_WRITE; | |
412 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
413 | |
414 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 415 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
416 | PIPE_CONTROL_CS_STALL | |
417 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
418 | 0); | |
419 | if (ret) | |
420 | return ret; | |
a5f3d68e BW |
421 | } |
422 | ||
f2cf1fcc | 423 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
424 | } |
425 | ||
0bc40be8 | 426 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 427 | u32 value) |
d46eefa2 | 428 | { |
0bc40be8 TU |
429 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
430 | I915_WRITE_TAIL(engine, value); | |
d46eefa2 XH |
431 | } |
432 | ||
0bc40be8 | 433 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 434 | { |
0bc40be8 | 435 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
50877445 | 436 | u64 acthd; |
8187a2b7 | 437 | |
0bc40be8 TU |
438 | if (INTEL_INFO(engine->dev)->gen >= 8) |
439 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
440 | RING_ACTHD_UDW(engine->mmio_base)); | |
441 | else if (INTEL_INFO(engine->dev)->gen >= 4) | |
442 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
50877445 CW |
443 | else |
444 | acthd = I915_READ(ACTHD); | |
445 | ||
446 | return acthd; | |
8187a2b7 ZN |
447 | } |
448 | ||
0bc40be8 | 449 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 450 | { |
0bc40be8 | 451 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
035dc1e0 DV |
452 | u32 addr; |
453 | ||
454 | addr = dev_priv->status_page_dmah->busaddr; | |
0bc40be8 | 455 | if (INTEL_INFO(engine->dev)->gen >= 4) |
035dc1e0 DV |
456 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
457 | I915_WRITE(HWS_PGA, addr); | |
458 | } | |
459 | ||
0bc40be8 | 460 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 461 | { |
0bc40be8 TU |
462 | struct drm_device *dev = engine->dev; |
463 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
f0f59a00 | 464 | i915_reg_t mmio; |
af75f269 DL |
465 | |
466 | /* The ring status page addresses are no longer next to the rest of | |
467 | * the ring registers as of gen7. | |
468 | */ | |
469 | if (IS_GEN7(dev)) { | |
0bc40be8 | 470 | switch (engine->id) { |
af75f269 DL |
471 | case RCS: |
472 | mmio = RENDER_HWS_PGA_GEN7; | |
473 | break; | |
474 | case BCS: | |
475 | mmio = BLT_HWS_PGA_GEN7; | |
476 | break; | |
477 | /* | |
478 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
479 | * gcc switch check warning | |
480 | */ | |
481 | case VCS2: | |
482 | case VCS: | |
483 | mmio = BSD_HWS_PGA_GEN7; | |
484 | break; | |
485 | case VECS: | |
486 | mmio = VEBOX_HWS_PGA_GEN7; | |
487 | break; | |
488 | } | |
0bc40be8 TU |
489 | } else if (IS_GEN6(engine->dev)) { |
490 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); | |
af75f269 DL |
491 | } else { |
492 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 493 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
494 | } |
495 | ||
0bc40be8 | 496 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
497 | POSTING_READ(mmio); |
498 | ||
499 | /* | |
500 | * Flush the TLB for this page | |
501 | * | |
502 | * FIXME: These two bits have disappeared on gen8, so a question | |
503 | * arises: do we still need this and if so how should we go about | |
504 | * invalidating the TLB? | |
505 | */ | |
506 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
0bc40be8 | 507 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
508 | |
509 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 510 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
511 | |
512 | I915_WRITE(reg, | |
513 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
514 | INSTPM_SYNC_FLUSH)); | |
515 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
516 | 1000)) | |
517 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
0bc40be8 | 518 | engine->name); |
af75f269 DL |
519 | } |
520 | } | |
521 | ||
0bc40be8 | 522 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 523 | { |
0bc40be8 | 524 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
8187a2b7 | 525 | |
0bc40be8 TU |
526 | if (!IS_GEN2(engine->dev)) { |
527 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); | |
528 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
529 | DRM_ERROR("%s : timed out trying to stop ring\n", | |
530 | engine->name); | |
9bec9b13 CW |
531 | /* Sometimes we observe that the idle flag is not |
532 | * set even though the ring is empty. So double | |
533 | * check before giving up. | |
534 | */ | |
0bc40be8 | 535 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 536 | return false; |
9991ae78 CW |
537 | } |
538 | } | |
b7884eb4 | 539 | |
0bc40be8 TU |
540 | I915_WRITE_CTL(engine, 0); |
541 | I915_WRITE_HEAD(engine, 0); | |
542 | engine->write_tail(engine, 0); | |
8187a2b7 | 543 | |
0bc40be8 TU |
544 | if (!IS_GEN2(engine->dev)) { |
545 | (void)I915_READ_CTL(engine); | |
546 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 547 | } |
a51435a3 | 548 | |
0bc40be8 | 549 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 550 | } |
8187a2b7 | 551 | |
fc0768ce TE |
552 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
553 | { | |
554 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
555 | } | |
556 | ||
0bc40be8 | 557 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 558 | { |
0bc40be8 | 559 | struct drm_device *dev = engine->dev; |
9991ae78 | 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 561 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 562 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
563 | int ret = 0; |
564 | ||
59bad947 | 565 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 566 | |
0bc40be8 | 567 | if (!stop_ring(engine)) { |
9991ae78 | 568 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
569 | DRM_DEBUG_KMS("%s head not reset to zero " |
570 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
571 | engine->name, |
572 | I915_READ_CTL(engine), | |
573 | I915_READ_HEAD(engine), | |
574 | I915_READ_TAIL(engine), | |
575 | I915_READ_START(engine)); | |
8187a2b7 | 576 | |
0bc40be8 | 577 | if (!stop_ring(engine)) { |
6fd0d56e CW |
578 | DRM_ERROR("failed to set %s head to zero " |
579 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
580 | engine->name, |
581 | I915_READ_CTL(engine), | |
582 | I915_READ_HEAD(engine), | |
583 | I915_READ_TAIL(engine), | |
584 | I915_READ_START(engine)); | |
9991ae78 CW |
585 | ret = -EIO; |
586 | goto out; | |
6fd0d56e | 587 | } |
8187a2b7 ZN |
588 | } |
589 | ||
9991ae78 | 590 | if (I915_NEED_GFX_HWS(dev)) |
0bc40be8 | 591 | intel_ring_setup_status_page(engine); |
9991ae78 | 592 | else |
0bc40be8 | 593 | ring_setup_phys_status_page(engine); |
9991ae78 | 594 | |
ece4a17d | 595 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 596 | I915_READ_HEAD(engine); |
ece4a17d | 597 | |
0d8957c8 DV |
598 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
599 | * registers with the above sequence (the readback of the HEAD registers | |
600 | * also enforces ordering), otherwise the hw might lose the new ring | |
601 | * register values. */ | |
0bc40be8 | 602 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
603 | |
604 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 605 | if (I915_READ_HEAD(engine)) |
95468892 | 606 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
607 | engine->name, I915_READ_HEAD(engine)); |
608 | I915_WRITE_HEAD(engine, 0); | |
609 | (void)I915_READ_HEAD(engine); | |
95468892 | 610 | |
0bc40be8 | 611 | I915_WRITE_CTL(engine, |
93b0a4e0 | 612 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 613 | | RING_VALID); |
8187a2b7 | 614 | |
8187a2b7 | 615 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
616 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
617 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
618 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 619 | DRM_ERROR("%s initialization failed " |
48e48a0b | 620 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
621 | engine->name, |
622 | I915_READ_CTL(engine), | |
623 | I915_READ_CTL(engine) & RING_VALID, | |
624 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
625 | I915_READ_START(engine), | |
626 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
627 | ret = -EIO; |
628 | goto out; | |
8187a2b7 ZN |
629 | } |
630 | ||
ebd0fd4b | 631 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
632 | ringbuf->head = I915_READ_HEAD(engine); |
633 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 634 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 635 | |
fc0768ce | 636 | intel_engine_init_hangcheck(engine); |
50f018df | 637 | |
b7884eb4 | 638 | out: |
59bad947 | 639 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
640 | |
641 | return ret; | |
8187a2b7 ZN |
642 | } |
643 | ||
9b1136d5 | 644 | void |
0bc40be8 | 645 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 646 | { |
0bc40be8 | 647 | struct drm_device *dev = engine->dev; |
9b1136d5 | 648 | |
0bc40be8 | 649 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
650 | return; |
651 | ||
652 | if (INTEL_INFO(dev)->gen >= 5) { | |
0bc40be8 TU |
653 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
654 | i915_gem_object_ggtt_unpin(engine->scratch.obj); | |
9b1136d5 OM |
655 | } |
656 | ||
0bc40be8 TU |
657 | drm_gem_object_unreference(&engine->scratch.obj->base); |
658 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
659 | } |
660 | ||
661 | int | |
0bc40be8 | 662 | intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 663 | { |
c6df541c CW |
664 | int ret; |
665 | ||
0bc40be8 | 666 | WARN_ON(engine->scratch.obj); |
c6df541c | 667 | |
0bc40be8 TU |
668 | engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096); |
669 | if (engine->scratch.obj == NULL) { | |
c6df541c CW |
670 | DRM_ERROR("Failed to allocate seqno page\n"); |
671 | ret = -ENOMEM; | |
672 | goto err; | |
673 | } | |
e4ffd173 | 674 | |
0bc40be8 TU |
675 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
676 | I915_CACHE_LLC); | |
a9cc726c DV |
677 | if (ret) |
678 | goto err_unref; | |
c6df541c | 679 | |
0bc40be8 | 680 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
c6df541c CW |
681 | if (ret) |
682 | goto err_unref; | |
683 | ||
0bc40be8 TU |
684 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
685 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); | |
686 | if (engine->scratch.cpu_page == NULL) { | |
56b085a0 | 687 | ret = -ENOMEM; |
c6df541c | 688 | goto err_unpin; |
56b085a0 | 689 | } |
c6df541c | 690 | |
2b1086cc | 691 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 692 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
693 | return 0; |
694 | ||
695 | err_unpin: | |
0bc40be8 | 696 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
c6df541c | 697 | err_unref: |
0bc40be8 | 698 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 699 | err: |
c6df541c CW |
700 | return ret; |
701 | } | |
702 | ||
e2be4faf | 703 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 704 | { |
7225342a | 705 | int ret, i; |
4a570db5 | 706 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 707 | struct drm_device *dev = engine->dev; |
888b5995 | 708 | struct drm_i915_private *dev_priv = dev->dev_private; |
7225342a | 709 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 710 | |
02235808 | 711 | if (w->count == 0) |
7225342a | 712 | return 0; |
888b5995 | 713 | |
e2f80391 | 714 | engine->gpu_caches_dirty = true; |
4866d729 | 715 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
716 | if (ret) |
717 | return ret; | |
888b5995 | 718 | |
5fb9de1a | 719 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
720 | if (ret) |
721 | return ret; | |
722 | ||
e2f80391 | 723 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 724 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
725 | intel_ring_emit_reg(engine, w->reg[i].addr); |
726 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 727 | } |
e2f80391 | 728 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 729 | |
e2f80391 | 730 | intel_ring_advance(engine); |
7225342a | 731 | |
e2f80391 | 732 | engine->gpu_caches_dirty = true; |
4866d729 | 733 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
734 | if (ret) |
735 | return ret; | |
888b5995 | 736 | |
7225342a | 737 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 738 | |
7225342a | 739 | return 0; |
86d7f238 AS |
740 | } |
741 | ||
8753181e | 742 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
743 | { |
744 | int ret; | |
745 | ||
e2be4faf | 746 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
747 | if (ret != 0) |
748 | return ret; | |
749 | ||
be01363f | 750 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 751 | if (ret) |
e26e1b97 | 752 | return ret; |
8f0e2b9d | 753 | |
e26e1b97 | 754 | return 0; |
8f0e2b9d DV |
755 | } |
756 | ||
7225342a | 757 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
758 | i915_reg_t addr, |
759 | const u32 mask, const u32 val) | |
7225342a MK |
760 | { |
761 | const u32 idx = dev_priv->workarounds.count; | |
762 | ||
763 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
764 | return -ENOSPC; | |
765 | ||
766 | dev_priv->workarounds.reg[idx].addr = addr; | |
767 | dev_priv->workarounds.reg[idx].value = val; | |
768 | dev_priv->workarounds.reg[idx].mask = mask; | |
769 | ||
770 | dev_priv->workarounds.count++; | |
771 | ||
772 | return 0; | |
86d7f238 AS |
773 | } |
774 | ||
ca5a0fbd | 775 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 776 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
777 | if (r) \ |
778 | return r; \ | |
ca5a0fbd | 779 | } while (0) |
7225342a MK |
780 | |
781 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 782 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
783 | |
784 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 785 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 786 | |
98533251 | 787 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 788 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 789 | |
cf4b0de6 DL |
790 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
791 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 792 | |
cf4b0de6 | 793 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 794 | |
0bc40be8 TU |
795 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
796 | i915_reg_t reg) | |
33136b06 | 797 | { |
0bc40be8 | 798 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
33136b06 | 799 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 800 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
801 | |
802 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
803 | return -EINVAL; | |
804 | ||
0bc40be8 | 805 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 806 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 807 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
0bc40be8 | 812 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 813 | { |
0bc40be8 | 814 | struct drm_device *dev = engine->dev; |
68c6198b AS |
815 | struct drm_i915_private *dev_priv = dev->dev_private; |
816 | ||
817 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 818 | |
717d84d6 AS |
819 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
820 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
821 | ||
d0581194 AS |
822 | /* WaDisablePartialInstShootdown:bdw,chv */ |
823 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
824 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
825 | ||
a340af58 AS |
826 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
827 | * workaround for for a possible hang in the unlikely event a TLB | |
828 | * invalidation occurs during a PSD flush. | |
829 | */ | |
830 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 831 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 832 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 833 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
834 | HDC_FORCE_NON_COHERENT); |
835 | ||
6def8fdd AS |
836 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
837 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
838 | * polygons in the same 8x4 pixel/sample area to be processed without | |
839 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
840 | * buffer." | |
841 | * | |
842 | * This optimization is off by default for BDW and CHV; turn it on. | |
843 | */ | |
844 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
845 | ||
48404636 AS |
846 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
847 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
848 | ||
7eebcde6 AS |
849 | /* |
850 | * BSpec recommends 8x4 when MSAA is used, | |
851 | * however in practice 16x4 seems fastest. | |
852 | * | |
853 | * Note that PS/WM thread counts depend on the WIZ hashing | |
854 | * disable bit, which we don't touch here, but it's good | |
855 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
856 | */ | |
857 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
858 | GEN6_WIZ_HASHING_MASK, | |
859 | GEN6_WIZ_HASHING_16x4); | |
860 | ||
e9a64ada AS |
861 | return 0; |
862 | } | |
863 | ||
0bc40be8 | 864 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 865 | { |
e9a64ada | 866 | int ret; |
0bc40be8 | 867 | struct drm_device *dev = engine->dev; |
888b5995 | 868 | struct drm_i915_private *dev_priv = dev->dev_private; |
86d7f238 | 869 | |
0bc40be8 | 870 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
871 | if (ret) |
872 | return ret; | |
873 | ||
101b376d | 874 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 875 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 876 | |
101b376d | 877 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
878 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
879 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 880 | |
7225342a MK |
881 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
882 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 883 | |
7225342a | 884 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
885 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
886 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 887 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 888 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 889 | |
86d7f238 AS |
890 | return 0; |
891 | } | |
892 | ||
0bc40be8 | 893 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 894 | { |
e9a64ada | 895 | int ret; |
0bc40be8 | 896 | struct drm_device *dev = engine->dev; |
00e1e623 VS |
897 | struct drm_i915_private *dev_priv = dev->dev_private; |
898 | ||
0bc40be8 | 899 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
900 | if (ret) |
901 | return ret; | |
902 | ||
00e1e623 | 903 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 904 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 905 | |
d60de81d KG |
906 | /* Improve HiZ throughput on CHV. */ |
907 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
908 | ||
7225342a MK |
909 | return 0; |
910 | } | |
911 | ||
0bc40be8 | 912 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 913 | { |
0bc40be8 | 914 | struct drm_device *dev = engine->dev; |
ab0dfafe | 915 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ea6f892 | 916 | uint32_t tmp; |
e0f3fa09 | 917 | int ret; |
ab0dfafe | 918 | |
9c4cbf82 MK |
919 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
920 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
921 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
922 | ||
923 | /* WaDisableKillLogic:bxt,skl */ | |
924 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
925 | ECOCHK_DIS_TLB); | |
926 | ||
950b2aae | 927 | /* WaClearFlowControlGpgpuContextSave:skl,bxt */ |
b0e6f6d4 | 928 | /* WaDisablePartialInstShootdown:skl,bxt */ |
ab0dfafe | 929 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 930 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
931 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
932 | ||
a119a6e6 | 933 | /* Syncing dependencies between camera and graphics:skl,bxt */ |
8424171e NH |
934 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
935 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
936 | ||
e87a005d JN |
937 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
938 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
939 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
a86eb582 DL |
940 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
941 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 942 | |
e87a005d JN |
943 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
944 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
945 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { | |
183c6dac DL |
946 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
947 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
948 | /* |
949 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
950 | * but we do that in per ctx batchbuffer as there is an issue | |
951 | * with this register not getting restored on ctx restore | |
952 | */ | |
183c6dac DL |
953 | } |
954 | ||
e87a005d | 955 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ |
bfd8ad4e TG |
956 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */ |
957 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, | |
958 | GEN9_ENABLE_YV12_BUGFIX | | |
959 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 960 | |
5068368c | 961 | /* Wa4x4STCOptimizationDisable:skl,bxt */ |
27160c96 | 962 | /* WaDisablePartialResolveInVc:skl,bxt */ |
60294683 AS |
963 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
964 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 965 | |
16be17af | 966 | /* WaCcsTlbPrefetchDisable:skl,bxt */ |
e2db7071 DL |
967 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
968 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
969 | ||
5a2ae95e | 970 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
e87a005d JN |
971 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
972 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
38a39a7b BW |
973 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
974 | PIXEL_MASK_CAMMING_DISABLE); | |
975 | ||
8ea6f892 ID |
976 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ |
977 | tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; | |
97ea6be1 | 978 | if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) || |
e87a005d | 979 | IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) |
8ea6f892 ID |
980 | tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; |
981 | WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); | |
982 | ||
8c761609 | 983 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */ |
e87a005d | 984 | if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0)) |
8c761609 AS |
985 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
986 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 987 | |
6b6d5626 RB |
988 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
989 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); | |
990 | ||
6ecf56ae AS |
991 | /* WaOCLCoherentLineFlush:skl,bxt */ |
992 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | | |
993 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
994 | ||
e0f3fa09 | 995 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ |
0bc40be8 | 996 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
997 | if (ret) |
998 | return ret; | |
999 | ||
3669ab61 | 1000 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt */ |
0bc40be8 | 1001 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1002 | if (ret) |
1003 | return ret; | |
1004 | ||
3b106531 HN |
1005 | return 0; |
1006 | } | |
1007 | ||
0bc40be8 | 1008 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1009 | { |
0bc40be8 | 1010 | struct drm_device *dev = engine->dev; |
b7668791 DL |
1011 | struct drm_i915_private *dev_priv = dev->dev_private; |
1012 | u8 vals[3] = { 0, 0, 0 }; | |
1013 | unsigned int i; | |
1014 | ||
1015 | for (i = 0; i < 3; i++) { | |
1016 | u8 ss; | |
1017 | ||
1018 | /* | |
1019 | * Only consider slices where one, and only one, subslice has 7 | |
1020 | * EUs | |
1021 | */ | |
a4d8a0fe | 1022 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1023 | continue; |
1024 | ||
1025 | /* | |
1026 | * subslice_7eu[i] != 0 (because of the check above) and | |
1027 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1028 | * | |
1029 | * -> 0 <= ss <= 3; | |
1030 | */ | |
1031 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1032 | vals[i] = 3 - ss; | |
1033 | } | |
1034 | ||
1035 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1036 | return 0; | |
1037 | ||
1038 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1039 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1040 | GEN9_IZ_HASHING_MASK(2) | | |
1041 | GEN9_IZ_HASHING_MASK(1) | | |
1042 | GEN9_IZ_HASHING_MASK(0), | |
1043 | GEN9_IZ_HASHING(2, vals[2]) | | |
1044 | GEN9_IZ_HASHING(1, vals[1]) | | |
1045 | GEN9_IZ_HASHING(0, vals[0])); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
0bc40be8 | 1050 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1051 | { |
aa0011a8 | 1052 | int ret; |
0bc40be8 | 1053 | struct drm_device *dev = engine->dev; |
d0bbbc4f DL |
1054 | struct drm_i915_private *dev_priv = dev->dev_private; |
1055 | ||
0bc40be8 | 1056 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1057 | if (ret) |
1058 | return ret; | |
8d205494 | 1059 | |
a78536e7 AS |
1060 | /* |
1061 | * Actual WA is to disable percontext preemption granularity control | |
1062 | * until D0 which is the default case so this is equivalent to | |
1063 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1064 | */ | |
1065 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { | |
1066 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1067 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1068 | } | |
1069 | ||
e87a005d | 1070 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
9c4cbf82 MK |
1071 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1072 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1073 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1074 | } | |
1075 | ||
1076 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1077 | * involving this register should also be added to WA batch as required. | |
1078 | */ | |
e87a005d | 1079 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1080 | /* WaDisableLSQCROPERFforOCL:skl */ |
1081 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1082 | GEN8_LQSC_RO_PERF_DIS); | |
1083 | ||
1084 | /* WaEnableGapsTsvCreditFix:skl */ | |
e87a005d | 1085 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1086 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1087 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1088 | } | |
1089 | ||
d0bbbc4f | 1090 | /* WaDisablePowerCompilerClockGating:skl */ |
e87a005d | 1091 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1092 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1093 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1094 | ||
97ea6be1 MK |
1095 | /* This is tied to WaForceContextSaveRestoreNonCoherent */ |
1096 | if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) { | |
b62adbd1 NH |
1097 | /* |
1098 | *Use Force Non-Coherent whenever executing a 3D context. This | |
1099 | * is a workaround for a possible hang in the unlikely event | |
1100 | * a TLB invalidation occurs during a PSD flush. | |
1101 | */ | |
1102 | /* WaForceEnableNonCoherent:skl */ | |
1103 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1104 | HDC_FORCE_NON_COHERENT); | |
e238659d MK |
1105 | |
1106 | /* WaDisableHDCInvalidation:skl */ | |
1107 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1108 | BDW_DISABLE_HDC_INVALIDATION); | |
b62adbd1 NH |
1109 | } |
1110 | ||
e87a005d JN |
1111 | /* WaBarrierPerformanceFixDisable:skl */ |
1112 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) | |
5b6fd12a VS |
1113 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1114 | HDC_FENCE_DEST_SLM_DISABLE | | |
1115 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1116 | ||
9bd9dfb4 | 1117 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
e87a005d | 1118 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1119 | WA_SET_BIT_MASKED( |
1120 | GEN7_HALF_SLICE_CHICKEN1, | |
1121 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1122 | |
6107497e | 1123 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1124 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1125 | if (ret) |
1126 | return ret; | |
1127 | ||
0bc40be8 | 1128 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1129 | } |
1130 | ||
0bc40be8 | 1131 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1132 | { |
aa0011a8 | 1133 | int ret; |
0bc40be8 | 1134 | struct drm_device *dev = engine->dev; |
dfb601e6 NH |
1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
1136 | ||
0bc40be8 | 1137 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1138 | if (ret) |
1139 | return ret; | |
cae0437f | 1140 | |
9c4cbf82 MK |
1141 | /* WaStoreMultiplePTEenable:bxt */ |
1142 | /* This is a requirement according to Hardware specification */ | |
cbdc12a9 | 1143 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1144 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1145 | ||
1146 | /* WaSetClckGatingDisableMedia:bxt */ | |
cbdc12a9 | 1147 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1148 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1149 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1150 | } | |
1151 | ||
dfb601e6 NH |
1152 | /* WaDisableThreadStallDopClockGating:bxt */ |
1153 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1154 | STALL_DOP_GATING_DISABLE); | |
1155 | ||
983b4b9d | 1156 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
e87a005d | 1157 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1158 | WA_SET_BIT_MASKED( |
1159 | GEN7_HALF_SLICE_CHICKEN1, | |
1160 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1161 | } | |
1162 | ||
2c8580e4 AS |
1163 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1164 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1165 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1166 | /* WaDisableLSQCROPERFforOCL:bxt */ |
2c8580e4 | 1167 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
0bc40be8 | 1168 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1169 | if (ret) |
1170 | return ret; | |
a786d53a | 1171 | |
0bc40be8 | 1172 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1173 | if (ret) |
1174 | return ret; | |
2c8580e4 AS |
1175 | } |
1176 | ||
cae0437f NH |
1177 | return 0; |
1178 | } | |
1179 | ||
0bc40be8 | 1180 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1181 | { |
0bc40be8 | 1182 | struct drm_device *dev = engine->dev; |
7225342a MK |
1183 | struct drm_i915_private *dev_priv = dev->dev_private; |
1184 | ||
0bc40be8 | 1185 | WARN_ON(engine->id != RCS); |
7225342a MK |
1186 | |
1187 | dev_priv->workarounds.count = 0; | |
33136b06 | 1188 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a MK |
1189 | |
1190 | if (IS_BROADWELL(dev)) | |
0bc40be8 | 1191 | return bdw_init_workarounds(engine); |
7225342a MK |
1192 | |
1193 | if (IS_CHERRYVIEW(dev)) | |
0bc40be8 | 1194 | return chv_init_workarounds(engine); |
00e1e623 | 1195 | |
8d205494 | 1196 | if (IS_SKYLAKE(dev)) |
0bc40be8 | 1197 | return skl_init_workarounds(engine); |
cae0437f NH |
1198 | |
1199 | if (IS_BROXTON(dev)) | |
0bc40be8 | 1200 | return bxt_init_workarounds(engine); |
3b106531 | 1201 | |
00e1e623 VS |
1202 | return 0; |
1203 | } | |
1204 | ||
0bc40be8 | 1205 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1206 | { |
0bc40be8 | 1207 | struct drm_device *dev = engine->dev; |
1ec14ad3 | 1208 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 1209 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1210 | if (ret) |
1211 | return ret; | |
a69ffdbf | 1212 | |
61a563a2 AG |
1213 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1214 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1215 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1216 | |
1217 | /* We need to disable the AsyncFlip performance optimisations in order | |
1218 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1219 | * programmed to '1' on all products. | |
8693a824 | 1220 | * |
2441f877 | 1221 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1222 | */ |
2441f877 | 1223 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
1c8c38c5 CW |
1224 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1225 | ||
f05bb0c7 | 1226 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1227 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1228 | if (INTEL_INFO(dev)->gen == 6) |
1229 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1230 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1231 | |
01fa0302 | 1232 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1233 | if (IS_GEN7(dev)) |
1234 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1235 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1236 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1237 | |
5e13a0c5 | 1238 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1239 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1240 | * "If this bit is set, STCunit will have LRA as replacement | |
1241 | * policy. [...] This bit must be reset. LRA replacement | |
1242 | * policy is not supported." | |
1243 | */ | |
1244 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1245 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1246 | } |
1247 | ||
9cc83020 | 1248 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
6b26c86d | 1249 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1250 | |
040d2baa | 1251 | if (HAS_L3_DPF(dev)) |
0bc40be8 | 1252 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1253 | |
0bc40be8 | 1254 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1255 | } |
1256 | ||
0bc40be8 | 1257 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1258 | { |
0bc40be8 | 1259 | struct drm_device *dev = engine->dev; |
3e78998a BW |
1260 | struct drm_i915_private *dev_priv = dev->dev_private; |
1261 | ||
1262 | if (dev_priv->semaphore_obj) { | |
1263 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1264 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1265 | dev_priv->semaphore_obj = NULL; | |
1266 | } | |
b45305fc | 1267 | |
0bc40be8 | 1268 | intel_fini_pipe_control(engine); |
c6df541c CW |
1269 | } |
1270 | ||
f7169687 | 1271 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1272 | unsigned int num_dwords) |
1273 | { | |
1274 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1275 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1276 | struct drm_device *dev = signaller->dev; |
1277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1278 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1279 | enum intel_engine_id id; |
1280 | int ret, num_rings; | |
3e78998a BW |
1281 | |
1282 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1283 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1284 | #undef MBOX_UPDATE_DWORDS | |
1285 | ||
5fb9de1a | 1286 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1287 | if (ret) |
1288 | return ret; | |
1289 | ||
c3232b18 | 1290 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1291 | u32 seqno; |
c3232b18 | 1292 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1293 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1294 | continue; | |
1295 | ||
f7169687 | 1296 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1297 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1298 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1299 | PIPE_CONTROL_QW_WRITE | | |
1300 | PIPE_CONTROL_FLUSH_ENABLE); | |
1301 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1302 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1303 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1304 | intel_ring_emit(signaller, 0); |
1305 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
83e53802 | 1306 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1307 | intel_ring_emit(signaller, 0); |
1308 | } | |
1309 | ||
1310 | return 0; | |
1311 | } | |
1312 | ||
f7169687 | 1313 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1314 | unsigned int num_dwords) |
1315 | { | |
1316 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1317 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1318 | struct drm_device *dev = signaller->dev; |
1319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1320 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1321 | enum intel_engine_id id; |
1322 | int ret, num_rings; | |
3e78998a BW |
1323 | |
1324 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1325 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1326 | #undef MBOX_UPDATE_DWORDS | |
1327 | ||
5fb9de1a | 1328 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1329 | if (ret) |
1330 | return ret; | |
1331 | ||
c3232b18 | 1332 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1333 | u32 seqno; |
c3232b18 | 1334 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1335 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1336 | continue; | |
1337 | ||
f7169687 | 1338 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1339 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1340 | MI_FLUSH_DW_OP_STOREDW); | |
1341 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1342 | MI_FLUSH_DW_USE_GTT); | |
1343 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1344 | intel_ring_emit(signaller, seqno); |
3e78998a | 1345 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
83e53802 | 1346 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1347 | intel_ring_emit(signaller, 0); |
1348 | } | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
f7169687 | 1353 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1354 | unsigned int num_dwords) |
1ec14ad3 | 1355 | { |
4a570db5 | 1356 | struct intel_engine_cs *signaller = signaller_req->engine; |
024a43e1 BW |
1357 | struct drm_device *dev = signaller->dev; |
1358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1359 | struct intel_engine_cs *useless; |
c3232b18 DG |
1360 | enum intel_engine_id id; |
1361 | int ret, num_rings; | |
78325f2d | 1362 | |
a1444b79 BW |
1363 | #define MBOX_UPDATE_DWORDS 3 |
1364 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1365 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1366 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1367 | |
5fb9de1a | 1368 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1369 | if (ret) |
1370 | return ret; | |
024a43e1 | 1371 | |
c3232b18 DG |
1372 | for_each_engine_id(useless, dev_priv, id) { |
1373 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1374 | |
1375 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1376 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1377 | |
78325f2d | 1378 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1379 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1380 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1381 | } |
1382 | } | |
024a43e1 | 1383 | |
a1444b79 BW |
1384 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1385 | if (num_rings % 2 == 0) | |
1386 | intel_ring_emit(signaller, MI_NOOP); | |
1387 | ||
024a43e1 | 1388 | return 0; |
1ec14ad3 CW |
1389 | } |
1390 | ||
c8c99b0f BW |
1391 | /** |
1392 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1393 | * |
1394 | * @request - request to write to the ring | |
c8c99b0f BW |
1395 | * |
1396 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1397 | * This acts like a signal in the canonical semaphore. | |
1398 | */ | |
1ec14ad3 | 1399 | static int |
ee044a88 | 1400 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1401 | { |
4a570db5 | 1402 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1403 | int ret; |
52ed2325 | 1404 | |
e2f80391 TU |
1405 | if (engine->semaphore.signal) |
1406 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1407 | else |
5fb9de1a | 1408 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1409 | |
1ec14ad3 CW |
1410 | if (ret) |
1411 | return ret; | |
1412 | ||
e2f80391 TU |
1413 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1414 | intel_ring_emit(engine, | |
1415 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1416 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1417 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1418 | __intel_ring_advance(engine); | |
1ec14ad3 | 1419 | |
1ec14ad3 CW |
1420 | return 0; |
1421 | } | |
1422 | ||
f72b3435 MK |
1423 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1424 | u32 seqno) | |
1425 | { | |
1426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1427 | return dev_priv->last_seqno < seqno; | |
1428 | } | |
1429 | ||
c8c99b0f BW |
1430 | /** |
1431 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1432 | * | |
1433 | * @waiter - ring that is waiting | |
1434 | * @signaller - ring which has, or will signal | |
1435 | * @seqno - seqno which the waiter will block on | |
1436 | */ | |
5ee426ca BW |
1437 | |
1438 | static int | |
599d924c | 1439 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1440 | struct intel_engine_cs *signaller, |
1441 | u32 seqno) | |
1442 | { | |
4a570db5 | 1443 | struct intel_engine_cs *waiter = waiter_req->engine; |
5ee426ca BW |
1444 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
1445 | int ret; | |
1446 | ||
5fb9de1a | 1447 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1448 | if (ret) |
1449 | return ret; | |
1450 | ||
1451 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1452 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1453 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1454 | MI_SEMAPHORE_SAD_GTE_SDD); |
1455 | intel_ring_emit(waiter, seqno); | |
1456 | intel_ring_emit(waiter, | |
1457 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1458 | intel_ring_emit(waiter, | |
1459 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1460 | intel_ring_advance(waiter); | |
1461 | return 0; | |
1462 | } | |
1463 | ||
c8c99b0f | 1464 | static int |
599d924c | 1465 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1466 | struct intel_engine_cs *signaller, |
686cb5f9 | 1467 | u32 seqno) |
1ec14ad3 | 1468 | { |
4a570db5 | 1469 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1470 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1471 | MI_SEMAPHORE_COMPARE | | |
1472 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1473 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1474 | int ret; | |
1ec14ad3 | 1475 | |
1500f7ea BW |
1476 | /* Throughout all of the GEM code, seqno passed implies our current |
1477 | * seqno is >= the last seqno executed. However for hardware the | |
1478 | * comparison is strictly greater than. | |
1479 | */ | |
1480 | seqno -= 1; | |
1481 | ||
ebc348b2 | 1482 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1483 | |
5fb9de1a | 1484 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1485 | if (ret) |
1486 | return ret; | |
1487 | ||
f72b3435 MK |
1488 | /* If seqno wrap happened, omit the wait with no-ops */ |
1489 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1490 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1491 | intel_ring_emit(waiter, seqno); |
1492 | intel_ring_emit(waiter, 0); | |
1493 | intel_ring_emit(waiter, MI_NOOP); | |
1494 | } else { | |
1495 | intel_ring_emit(waiter, MI_NOOP); | |
1496 | intel_ring_emit(waiter, MI_NOOP); | |
1497 | intel_ring_emit(waiter, MI_NOOP); | |
1498 | intel_ring_emit(waiter, MI_NOOP); | |
1499 | } | |
c8c99b0f | 1500 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1501 | |
1502 | return 0; | |
1503 | } | |
1504 | ||
c6df541c CW |
1505 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1506 | do { \ | |
fcbc34e4 KG |
1507 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1508 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1509 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1510 | intel_ring_emit(ring__, 0); \ | |
1511 | intel_ring_emit(ring__, 0); \ | |
1512 | } while (0) | |
1513 | ||
1514 | static int | |
ee044a88 | 1515 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1516 | { |
4a570db5 | 1517 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1518 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1519 | int ret; |
1520 | ||
1521 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1522 | * incoherent with writes to memory, i.e. completely fubar, | |
1523 | * so we need to use PIPE_NOTIFY instead. | |
1524 | * | |
1525 | * However, we also need to workaround the qword write | |
1526 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1527 | * memory before requesting an interrupt. | |
1528 | */ | |
5fb9de1a | 1529 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1530 | if (ret) |
1531 | return ret; | |
1532 | ||
e2f80391 TU |
1533 | intel_ring_emit(engine, |
1534 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1535 | PIPE_CONTROL_WRITE_FLUSH | |
1536 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
e2f80391 TU |
1537 | intel_ring_emit(engine, |
1538 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1539 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1540 | intel_ring_emit(engine, 0); | |
1541 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1542 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1543 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1544 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1545 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1546 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1547 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1548 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1549 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1550 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1551 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1552 | |
e2f80391 TU |
1553 | intel_ring_emit(engine, |
1554 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1555 | PIPE_CONTROL_WRITE_FLUSH | |
1556 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1557 | PIPE_CONTROL_NOTIFY); |
e2f80391 TU |
1558 | intel_ring_emit(engine, |
1559 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1560 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1561 | intel_ring_emit(engine, 0); | |
1562 | __intel_ring_advance(engine); | |
c6df541c | 1563 | |
c6df541c CW |
1564 | return 0; |
1565 | } | |
1566 | ||
c04e0f3b CW |
1567 | static void |
1568 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1569 | { |
e32da7ad CW |
1570 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
1571 | ||
4cd53c0c DV |
1572 | /* Workaround to force correct ordering between irq and seqno writes on |
1573 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1574 | * ACTHD) before reading the status page. |
1575 | * | |
1576 | * Note that this effectively stalls the read by the time it takes to | |
1577 | * do a memory transaction, which more or less ensures that the write | |
1578 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1579 | * Alternatively we could delay the interrupt from the CS ring to give | |
1580 | * the write time to land, but that would incur a delay after every | |
1581 | * batch i.e. much more frequent than a delay when waiting for the | |
1582 | * interrupt (with the same net latency). | |
e32da7ad CW |
1583 | * |
1584 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1585 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1586 | */ |
e32da7ad | 1587 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1588 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
e32da7ad | 1589 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1590 | } |
1591 | ||
8187a2b7 | 1592 | static u32 |
c04e0f3b | 1593 | ring_get_seqno(struct intel_engine_cs *engine) |
8187a2b7 | 1594 | { |
0bc40be8 | 1595 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
1ec14ad3 CW |
1596 | } |
1597 | ||
b70ec5bf | 1598 | static void |
0bc40be8 | 1599 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1600 | { |
0bc40be8 | 1601 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
b70ec5bf MK |
1602 | } |
1603 | ||
c6df541c | 1604 | static u32 |
c04e0f3b | 1605 | pc_render_get_seqno(struct intel_engine_cs *engine) |
c6df541c | 1606 | { |
0bc40be8 | 1607 | return engine->scratch.cpu_page[0]; |
c6df541c CW |
1608 | } |
1609 | ||
b70ec5bf | 1610 | static void |
0bc40be8 | 1611 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1612 | { |
0bc40be8 | 1613 | engine->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1614 | } |
1615 | ||
e48d8634 | 1616 | static bool |
0bc40be8 | 1617 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1618 | { |
0bc40be8 | 1619 | struct drm_device *dev = engine->dev; |
4640c4ff | 1620 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1621 | unsigned long flags; |
e48d8634 | 1622 | |
7cd512f1 | 1623 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1624 | return false; |
1625 | ||
7338aefa | 1626 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1627 | if (engine->irq_refcount++ == 0) |
1628 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1629 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1630 | |
1631 | return true; | |
1632 | } | |
1633 | ||
1634 | static void | |
0bc40be8 | 1635 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1636 | { |
0bc40be8 | 1637 | struct drm_device *dev = engine->dev; |
4640c4ff | 1638 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1639 | unsigned long flags; |
e48d8634 | 1640 | |
7338aefa | 1641 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1642 | if (--engine->irq_refcount == 0) |
1643 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1644 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1645 | } |
1646 | ||
b13c2b96 | 1647 | static bool |
0bc40be8 | 1648 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1649 | { |
0bc40be8 | 1650 | struct drm_device *dev = engine->dev; |
4640c4ff | 1651 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1652 | unsigned long flags; |
62fdfeaf | 1653 | |
7cd512f1 | 1654 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1655 | return false; |
1656 | ||
7338aefa | 1657 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1658 | if (engine->irq_refcount++ == 0) { |
1659 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1660 | I915_WRITE(IMR, dev_priv->irq_mask); |
1661 | POSTING_READ(IMR); | |
1662 | } | |
7338aefa | 1663 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1664 | |
1665 | return true; | |
62fdfeaf EA |
1666 | } |
1667 | ||
8187a2b7 | 1668 | static void |
0bc40be8 | 1669 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1670 | { |
0bc40be8 | 1671 | struct drm_device *dev = engine->dev; |
4640c4ff | 1672 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1673 | unsigned long flags; |
62fdfeaf | 1674 | |
7338aefa | 1675 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1676 | if (--engine->irq_refcount == 0) { |
1677 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1678 | I915_WRITE(IMR, dev_priv->irq_mask); |
1679 | POSTING_READ(IMR); | |
1680 | } | |
7338aefa | 1681 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1682 | } |
1683 | ||
c2798b19 | 1684 | static bool |
0bc40be8 | 1685 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1686 | { |
0bc40be8 | 1687 | struct drm_device *dev = engine->dev; |
4640c4ff | 1688 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1689 | unsigned long flags; |
c2798b19 | 1690 | |
7cd512f1 | 1691 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1692 | return false; |
1693 | ||
7338aefa | 1694 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1695 | if (engine->irq_refcount++ == 0) { |
1696 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1697 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1698 | POSTING_READ16(IMR); | |
1699 | } | |
7338aefa | 1700 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1701 | |
1702 | return true; | |
1703 | } | |
1704 | ||
1705 | static void | |
0bc40be8 | 1706 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1707 | { |
0bc40be8 | 1708 | struct drm_device *dev = engine->dev; |
4640c4ff | 1709 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1710 | unsigned long flags; |
c2798b19 | 1711 | |
7338aefa | 1712 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1713 | if (--engine->irq_refcount == 0) { |
1714 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1715 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1716 | POSTING_READ16(IMR); | |
1717 | } | |
7338aefa | 1718 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1719 | } |
1720 | ||
b72f3acb | 1721 | static int |
a84c3ae1 | 1722 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1723 | u32 invalidate_domains, |
1724 | u32 flush_domains) | |
d1b851fc | 1725 | { |
4a570db5 | 1726 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1727 | int ret; |
1728 | ||
5fb9de1a | 1729 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1730 | if (ret) |
1731 | return ret; | |
1732 | ||
e2f80391 TU |
1733 | intel_ring_emit(engine, MI_FLUSH); |
1734 | intel_ring_emit(engine, MI_NOOP); | |
1735 | intel_ring_advance(engine); | |
b72f3acb | 1736 | return 0; |
d1b851fc ZN |
1737 | } |
1738 | ||
3cce469c | 1739 | static int |
ee044a88 | 1740 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1741 | { |
4a570db5 | 1742 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1743 | int ret; |
1744 | ||
5fb9de1a | 1745 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1746 | if (ret) |
1747 | return ret; | |
6f392d54 | 1748 | |
e2f80391 TU |
1749 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1750 | intel_ring_emit(engine, | |
1751 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1752 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1753 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1754 | __intel_ring_advance(engine); | |
d1b851fc | 1755 | |
3cce469c | 1756 | return 0; |
d1b851fc ZN |
1757 | } |
1758 | ||
0f46832f | 1759 | static bool |
0bc40be8 | 1760 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1761 | { |
0bc40be8 | 1762 | struct drm_device *dev = engine->dev; |
4640c4ff | 1763 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1764 | unsigned long flags; |
0f46832f | 1765 | |
7cd512f1 DV |
1766 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1767 | return false; | |
0f46832f | 1768 | |
7338aefa | 1769 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1770 | if (engine->irq_refcount++ == 0) { |
1771 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1772 | I915_WRITE_IMR(engine, | |
1773 | ~(engine->irq_enable_mask | | |
35a85ac6 | 1774 | GT_PARITY_ERROR(dev))); |
15b9f80e | 1775 | else |
0bc40be8 TU |
1776 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1777 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1778 | } |
7338aefa | 1779 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1780 | |
1781 | return true; | |
1782 | } | |
1783 | ||
1784 | static void | |
0bc40be8 | 1785 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1786 | { |
0bc40be8 | 1787 | struct drm_device *dev = engine->dev; |
4640c4ff | 1788 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1789 | unsigned long flags; |
0f46832f | 1790 | |
7338aefa | 1791 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1792 | if (--engine->irq_refcount == 0) { |
1793 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1794 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); | |
15b9f80e | 1795 | else |
0bc40be8 TU |
1796 | I915_WRITE_IMR(engine, ~0); |
1797 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1798 | } |
7338aefa | 1799 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1800 | } |
1801 | ||
a19d2933 | 1802 | static bool |
0bc40be8 | 1803 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1804 | { |
0bc40be8 | 1805 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; |
1807 | unsigned long flags; | |
1808 | ||
7cd512f1 | 1809 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1810 | return false; |
1811 | ||
59cdb63d | 1812 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1813 | if (engine->irq_refcount++ == 0) { |
1814 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1815 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1816 | } |
59cdb63d | 1817 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1818 | |
1819 | return true; | |
1820 | } | |
1821 | ||
1822 | static void | |
0bc40be8 | 1823 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1824 | { |
0bc40be8 | 1825 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1826 | struct drm_i915_private *dev_priv = dev->dev_private; |
1827 | unsigned long flags; | |
1828 | ||
59cdb63d | 1829 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1830 | if (--engine->irq_refcount == 0) { |
1831 | I915_WRITE_IMR(engine, ~0); | |
1832 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1833 | } |
59cdb63d | 1834 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1835 | } |
1836 | ||
abd58f01 | 1837 | static bool |
0bc40be8 | 1838 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1839 | { |
0bc40be8 | 1840 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1841 | struct drm_i915_private *dev_priv = dev->dev_private; |
1842 | unsigned long flags; | |
1843 | ||
7cd512f1 | 1844 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1845 | return false; |
1846 | ||
1847 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1848 | if (engine->irq_refcount++ == 0) { |
1849 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1850 | I915_WRITE_IMR(engine, | |
1851 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1852 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1853 | } else { | |
0bc40be8 | 1854 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1855 | } |
0bc40be8 | 1856 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1857 | } |
1858 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1859 | ||
1860 | return true; | |
1861 | } | |
1862 | ||
1863 | static void | |
0bc40be8 | 1864 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1865 | { |
0bc40be8 | 1866 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
1868 | unsigned long flags; | |
1869 | ||
1870 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1871 | if (--engine->irq_refcount == 0) { |
1872 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1873 | I915_WRITE_IMR(engine, | |
abd58f01 BW |
1874 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1875 | } else { | |
0bc40be8 | 1876 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1877 | } |
0bc40be8 | 1878 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1879 | } |
1880 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1881 | } | |
1882 | ||
d1b851fc | 1883 | static int |
53fddaf7 | 1884 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1885 | u64 offset, u32 length, |
8e004efc | 1886 | unsigned dispatch_flags) |
d1b851fc | 1887 | { |
4a570db5 | 1888 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1889 | int ret; |
78501eac | 1890 | |
5fb9de1a | 1891 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1892 | if (ret) |
1893 | return ret; | |
1894 | ||
e2f80391 | 1895 | intel_ring_emit(engine, |
65f56876 CW |
1896 | MI_BATCH_BUFFER_START | |
1897 | MI_BATCH_GTT | | |
8e004efc JH |
1898 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1899 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1900 | intel_ring_emit(engine, offset); |
1901 | intel_ring_advance(engine); | |
78501eac | 1902 | |
d1b851fc ZN |
1903 | return 0; |
1904 | } | |
1905 | ||
b45305fc DV |
1906 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1907 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1908 | #define I830_TLB_ENTRIES (2) |
1909 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1910 | static int |
53fddaf7 | 1911 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1912 | u64 offset, u32 len, |
1913 | unsigned dispatch_flags) | |
62fdfeaf | 1914 | { |
4a570db5 | 1915 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1916 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1917 | int ret; |
62fdfeaf | 1918 | |
5fb9de1a | 1919 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1920 | if (ret) |
1921 | return ret; | |
62fdfeaf | 1922 | |
c4d69da1 | 1923 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1924 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1925 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1926 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1927 | intel_ring_emit(engine, cs_offset); | |
1928 | intel_ring_emit(engine, 0xdeadbeef); | |
1929 | intel_ring_emit(engine, MI_NOOP); | |
1930 | intel_ring_advance(engine); | |
b45305fc | 1931 | |
8e004efc | 1932 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1933 | if (len > I830_BATCH_LIMIT) |
1934 | return -ENOSPC; | |
1935 | ||
5fb9de1a | 1936 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1937 | if (ret) |
1938 | return ret; | |
c4d69da1 CW |
1939 | |
1940 | /* Blit the batch (which has now all relocs applied) to the | |
1941 | * stable batch scratch bo area (so that the CS never | |
1942 | * stumbles over its tlb invalidation bug) ... | |
1943 | */ | |
e2f80391 TU |
1944 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1945 | intel_ring_emit(engine, | |
1946 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
1947 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
1948 | intel_ring_emit(engine, cs_offset); | |
1949 | intel_ring_emit(engine, 4096); | |
1950 | intel_ring_emit(engine, offset); | |
1951 | ||
1952 | intel_ring_emit(engine, MI_FLUSH); | |
1953 | intel_ring_emit(engine, MI_NOOP); | |
1954 | intel_ring_advance(engine); | |
b45305fc DV |
1955 | |
1956 | /* ... and execute it. */ | |
c4d69da1 | 1957 | offset = cs_offset; |
b45305fc | 1958 | } |
e1f99ce6 | 1959 | |
9d611c03 | 1960 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1961 | if (ret) |
1962 | return ret; | |
1963 | ||
e2f80391 TU |
1964 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1965 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1966 | 0 : MI_BATCH_NON_SECURE)); | |
1967 | intel_ring_advance(engine); | |
c4d69da1 | 1968 | |
fb3256da DV |
1969 | return 0; |
1970 | } | |
1971 | ||
1972 | static int | |
53fddaf7 | 1973 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1974 | u64 offset, u32 len, |
8e004efc | 1975 | unsigned dispatch_flags) |
fb3256da | 1976 | { |
4a570db5 | 1977 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
1978 | int ret; |
1979 | ||
5fb9de1a | 1980 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1981 | if (ret) |
1982 | return ret; | |
1983 | ||
e2f80391 TU |
1984 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1985 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1986 | 0 : MI_BATCH_NON_SECURE)); | |
1987 | intel_ring_advance(engine); | |
62fdfeaf | 1988 | |
62fdfeaf EA |
1989 | return 0; |
1990 | } | |
1991 | ||
0bc40be8 | 1992 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1993 | { |
0bc40be8 | 1994 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
7d3fdfff VS |
1995 | |
1996 | if (!dev_priv->status_page_dmah) | |
1997 | return; | |
1998 | ||
0bc40be8 TU |
1999 | drm_pci_free(engine->dev, dev_priv->status_page_dmah); |
2000 | engine->status_page.page_addr = NULL; | |
7d3fdfff VS |
2001 | } |
2002 | ||
0bc40be8 | 2003 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2004 | { |
05394f39 | 2005 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2006 | |
0bc40be8 | 2007 | obj = engine->status_page.obj; |
8187a2b7 | 2008 | if (obj == NULL) |
62fdfeaf | 2009 | return; |
62fdfeaf | 2010 | |
9da3da66 | 2011 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2012 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2013 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2014 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2015 | } |
2016 | ||
0bc40be8 | 2017 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2018 | { |
0bc40be8 | 2019 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2020 | |
7d3fdfff | 2021 | if (obj == NULL) { |
1f767e02 | 2022 | unsigned flags; |
e3efda49 | 2023 | int ret; |
e4ffd173 | 2024 | |
0bc40be8 | 2025 | obj = i915_gem_alloc_object(engine->dev, 4096); |
e3efda49 CW |
2026 | if (obj == NULL) { |
2027 | DRM_ERROR("Failed to allocate status page\n"); | |
2028 | return -ENOMEM; | |
2029 | } | |
62fdfeaf | 2030 | |
e3efda49 CW |
2031 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2032 | if (ret) | |
2033 | goto err_unref; | |
2034 | ||
1f767e02 | 2035 | flags = 0; |
0bc40be8 | 2036 | if (!HAS_LLC(engine->dev)) |
1f767e02 CW |
2037 | /* On g33, we cannot place HWS above 256MiB, so |
2038 | * restrict its pinning to the low mappable arena. | |
2039 | * Though this restriction is not documented for | |
2040 | * gen4, gen5, or byt, they also behave similarly | |
2041 | * and hang if the HWS is placed at the top of the | |
2042 | * GTT. To generalise, it appears that all !llc | |
2043 | * platforms have issues with us placing the HWS | |
2044 | * above the mappable region (even though we never | |
2045 | * actualy map it). | |
2046 | */ | |
2047 | flags |= PIN_MAPPABLE; | |
2048 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2049 | if (ret) { |
2050 | err_unref: | |
2051 | drm_gem_object_unreference(&obj->base); | |
2052 | return ret; | |
2053 | } | |
2054 | ||
0bc40be8 | 2055 | engine->status_page.obj = obj; |
e3efda49 | 2056 | } |
62fdfeaf | 2057 | |
0bc40be8 TU |
2058 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2059 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2060 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2061 | |
8187a2b7 | 2062 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2063 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2064 | |
2065 | return 0; | |
62fdfeaf EA |
2066 | } |
2067 | ||
0bc40be8 | 2068 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2069 | { |
0bc40be8 | 2070 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
6b8294a4 CW |
2071 | |
2072 | if (!dev_priv->status_page_dmah) { | |
2073 | dev_priv->status_page_dmah = | |
0bc40be8 | 2074 | drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2075 | if (!dev_priv->status_page_dmah) |
2076 | return -ENOMEM; | |
2077 | } | |
2078 | ||
0bc40be8 TU |
2079 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2080 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2081 | |
2082 | return 0; | |
2083 | } | |
2084 | ||
7ba717cf | 2085 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2086 | { |
def0c5f6 | 2087 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2088 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 CW |
2089 | else |
2090 | iounmap(ringbuf->virtual_start); | |
8305216f | 2091 | ringbuf->virtual_start = NULL; |
0eb973d3 | 2092 | ringbuf->vma = NULL; |
2919d291 | 2093 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
2094 | } |
2095 | ||
2096 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
2097 | struct intel_ringbuffer *ringbuf) | |
2098 | { | |
2099 | struct drm_i915_private *dev_priv = to_i915(dev); | |
72e96d64 | 2100 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7ba717cf | 2101 | struct drm_i915_gem_object *obj = ringbuf->obj; |
a687a43a CW |
2102 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2103 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2104 | void *addr; |
7ba717cf TD |
2105 | int ret; |
2106 | ||
def0c5f6 | 2107 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2108 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2109 | if (ret) |
2110 | return ret; | |
7ba717cf | 2111 | |
def0c5f6 | 2112 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2113 | if (ret) |
2114 | goto err_unpin; | |
def0c5f6 | 2115 | |
8305216f DG |
2116 | addr = i915_gem_object_pin_map(obj); |
2117 | if (IS_ERR(addr)) { | |
2118 | ret = PTR_ERR(addr); | |
d2cad535 | 2119 | goto err_unpin; |
def0c5f6 CW |
2120 | } |
2121 | } else { | |
a687a43a CW |
2122 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2123 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2124 | if (ret) |
2125 | return ret; | |
7ba717cf | 2126 | |
def0c5f6 | 2127 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2128 | if (ret) |
2129 | goto err_unpin; | |
def0c5f6 | 2130 | |
ff3dc087 DCS |
2131 | /* Access through the GTT requires the device to be awake. */ |
2132 | assert_rpm_wakelock_held(dev_priv); | |
2133 | ||
8305216f DG |
2134 | addr = ioremap_wc(ggtt->mappable_base + |
2135 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
2136 | if (addr == NULL) { | |
d2cad535 CW |
2137 | ret = -ENOMEM; |
2138 | goto err_unpin; | |
def0c5f6 | 2139 | } |
7ba717cf TD |
2140 | } |
2141 | ||
8305216f | 2142 | ringbuf->virtual_start = addr; |
0eb973d3 | 2143 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2144 | return 0; |
d2cad535 CW |
2145 | |
2146 | err_unpin: | |
2147 | i915_gem_object_ggtt_unpin(obj); | |
2148 | return ret; | |
7ba717cf TD |
2149 | } |
2150 | ||
01101fa7 | 2151 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2152 | { |
2919d291 OM |
2153 | drm_gem_object_unreference(&ringbuf->obj->base); |
2154 | ringbuf->obj = NULL; | |
2155 | } | |
2156 | ||
01101fa7 CW |
2157 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2158 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2159 | { |
05394f39 | 2160 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2161 | |
ebc052e0 CW |
2162 | obj = NULL; |
2163 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2164 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2165 | if (obj == NULL) |
93b0a4e0 | 2166 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
2167 | if (obj == NULL) |
2168 | return -ENOMEM; | |
8187a2b7 | 2169 | |
24f3a8cf AG |
2170 | /* mark ring buffers as read-only from GPU side by default */ |
2171 | obj->gt_ro = 1; | |
2172 | ||
93b0a4e0 | 2173 | ringbuf->obj = obj; |
e3efda49 | 2174 | |
7ba717cf | 2175 | return 0; |
e3efda49 CW |
2176 | } |
2177 | ||
01101fa7 CW |
2178 | struct intel_ringbuffer * |
2179 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2180 | { | |
2181 | struct intel_ringbuffer *ring; | |
2182 | int ret; | |
2183 | ||
2184 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2185 | if (ring == NULL) { |
2186 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2187 | engine->name); | |
01101fa7 | 2188 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2189 | } |
01101fa7 | 2190 | |
4a570db5 | 2191 | ring->engine = engine; |
608c1a52 | 2192 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2193 | |
2194 | ring->size = size; | |
2195 | /* Workaround an erratum on the i830 which causes a hang if | |
2196 | * the TAIL pointer points to within the last 2 cachelines | |
2197 | * of the buffer. | |
2198 | */ | |
2199 | ring->effective_size = size; | |
2200 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) | |
2201 | ring->effective_size -= 2 * CACHELINE_BYTES; | |
2202 | ||
2203 | ring->last_retired_head = -1; | |
2204 | intel_ring_update_space(ring); | |
2205 | ||
2206 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); | |
2207 | if (ret) { | |
608c1a52 CW |
2208 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2209 | engine->name, ret); | |
2210 | list_del(&ring->link); | |
01101fa7 CW |
2211 | kfree(ring); |
2212 | return ERR_PTR(ret); | |
2213 | } | |
2214 | ||
2215 | return ring; | |
2216 | } | |
2217 | ||
2218 | void | |
2219 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2220 | { | |
2221 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2222 | list_del(&ring->link); |
01101fa7 CW |
2223 | kfree(ring); |
2224 | } | |
2225 | ||
e3efda49 | 2226 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2227 | struct intel_engine_cs *engine) |
e3efda49 | 2228 | { |
bfc882b4 | 2229 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2230 | int ret; |
2231 | ||
0bc40be8 | 2232 | WARN_ON(engine->buffer); |
bfc882b4 | 2233 | |
0bc40be8 TU |
2234 | engine->dev = dev; |
2235 | INIT_LIST_HEAD(&engine->active_list); | |
2236 | INIT_LIST_HEAD(&engine->request_list); | |
2237 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2238 | INIT_LIST_HEAD(&engine->buffers); | |
2239 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2240 | memset(engine->semaphore.sync_seqno, 0, | |
2241 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2242 | |
0bc40be8 | 2243 | init_waitqueue_head(&engine->irq_queue); |
e3efda49 | 2244 | |
0bc40be8 | 2245 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2246 | if (IS_ERR(ringbuf)) { |
2247 | ret = PTR_ERR(ringbuf); | |
2248 | goto error; | |
2249 | } | |
0bc40be8 | 2250 | engine->buffer = ringbuf; |
01101fa7 | 2251 | |
e3efda49 | 2252 | if (I915_NEED_GFX_HWS(dev)) { |
0bc40be8 | 2253 | ret = init_status_page(engine); |
e3efda49 | 2254 | if (ret) |
8ee14975 | 2255 | goto error; |
e3efda49 | 2256 | } else { |
0bc40be8 TU |
2257 | WARN_ON(engine->id != RCS); |
2258 | ret = init_phys_status_page(engine); | |
e3efda49 | 2259 | if (ret) |
8ee14975 | 2260 | goto error; |
e3efda49 CW |
2261 | } |
2262 | ||
bfc882b4 DV |
2263 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
2264 | if (ret) { | |
2265 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2266 | engine->name, ret); |
bfc882b4 DV |
2267 | intel_destroy_ringbuffer_obj(ringbuf); |
2268 | goto error; | |
e3efda49 | 2269 | } |
62fdfeaf | 2270 | |
0bc40be8 | 2271 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2272 | if (ret) |
8ee14975 OM |
2273 | goto error; |
2274 | ||
8ee14975 | 2275 | return 0; |
351e3db2 | 2276 | |
8ee14975 | 2277 | error: |
117897f4 | 2278 | intel_cleanup_engine(engine); |
8ee14975 | 2279 | return ret; |
62fdfeaf EA |
2280 | } |
2281 | ||
117897f4 | 2282 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2283 | { |
6402c330 | 2284 | struct drm_i915_private *dev_priv; |
33626e6a | 2285 | |
117897f4 | 2286 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2287 | return; |
2288 | ||
0bc40be8 | 2289 | dev_priv = to_i915(engine->dev); |
6402c330 | 2290 | |
0bc40be8 | 2291 | if (engine->buffer) { |
117897f4 | 2292 | intel_stop_engine(engine); |
0bc40be8 | 2293 | WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2294 | |
0bc40be8 TU |
2295 | intel_unpin_ringbuffer_obj(engine->buffer); |
2296 | intel_ringbuffer_free(engine->buffer); | |
2297 | engine->buffer = NULL; | |
b0366a54 | 2298 | } |
78501eac | 2299 | |
0bc40be8 TU |
2300 | if (engine->cleanup) |
2301 | engine->cleanup(engine); | |
8d19215b | 2302 | |
0bc40be8 TU |
2303 | if (I915_NEED_GFX_HWS(engine->dev)) { |
2304 | cleanup_status_page(engine); | |
7d3fdfff | 2305 | } else { |
0bc40be8 TU |
2306 | WARN_ON(engine->id != RCS); |
2307 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2308 | } |
44e895a8 | 2309 | |
0bc40be8 TU |
2310 | i915_cmd_parser_fini_ring(engine); |
2311 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
2312 | engine->dev = NULL; | |
62fdfeaf EA |
2313 | } |
2314 | ||
666796da | 2315 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2316 | { |
a4b3a571 | 2317 | struct drm_i915_gem_request *req; |
3e960501 | 2318 | |
3e960501 | 2319 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2320 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2321 | return 0; |
2322 | ||
0bc40be8 TU |
2323 | req = list_entry(engine->request_list.prev, |
2324 | struct drm_i915_gem_request, | |
2325 | list); | |
b4716185 CW |
2326 | |
2327 | /* Make sure we do not trigger any retires */ | |
2328 | return __i915_wait_request(req, | |
c19ae989 | 2329 | req->i915->mm.interruptible, |
b4716185 | 2330 | NULL, NULL); |
3e960501 CW |
2331 | } |
2332 | ||
6689cb2b | 2333 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2334 | { |
4a570db5 | 2335 | request->ringbuf = request->engine->buffer; |
9eba5d4a | 2336 | return 0; |
9d773091 CW |
2337 | } |
2338 | ||
ccd98fe4 JH |
2339 | int intel_ring_reserve_space(struct drm_i915_gem_request *request) |
2340 | { | |
2341 | /* | |
2342 | * The first call merely notes the reserve request and is common for | |
2343 | * all back ends. The subsequent localised _begin() call actually | |
2344 | * ensures that the reservation is available. Without the begin, if | |
2345 | * the request creator immediately submitted the request without | |
2346 | * adding any commands to it then there might not actually be | |
2347 | * sufficient room for the submission commands. | |
2348 | */ | |
2349 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
2350 | ||
2351 | return intel_ring_begin(request, 0); | |
2352 | } | |
2353 | ||
29b1b415 JH |
2354 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size) |
2355 | { | |
92dcc67c | 2356 | GEM_BUG_ON(ringbuf->reserved_size); |
29b1b415 | 2357 | ringbuf->reserved_size = size; |
29b1b415 JH |
2358 | } |
2359 | ||
2360 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf) | |
2361 | { | |
92dcc67c | 2362 | GEM_BUG_ON(!ringbuf->reserved_size); |
29b1b415 | 2363 | ringbuf->reserved_size = 0; |
29b1b415 JH |
2364 | } |
2365 | ||
2366 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf) | |
2367 | { | |
92dcc67c CW |
2368 | GEM_BUG_ON(!ringbuf->reserved_size); |
2369 | ringbuf->reserved_size = 0; | |
29b1b415 JH |
2370 | } |
2371 | ||
2372 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf) | |
2373 | { | |
92dcc67c CW |
2374 | GEM_BUG_ON(ringbuf->reserved_size); |
2375 | } | |
2376 | ||
2377 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) | |
2378 | { | |
2379 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2380 | struct intel_engine_cs *engine = req->engine; | |
2381 | struct drm_i915_gem_request *target; | |
2382 | ||
2383 | intel_ring_update_space(ringbuf); | |
2384 | if (ringbuf->space >= bytes) | |
2385 | return 0; | |
2386 | ||
2387 | /* | |
2388 | * Space is reserved in the ringbuffer for finalising the request, | |
2389 | * as that cannot be allowed to fail. During request finalisation, | |
2390 | * reserved_space is set to 0 to stop the overallocation and the | |
2391 | * assumption is that then we never need to wait (which has the | |
2392 | * risk of failing with EINTR). | |
2393 | * | |
2394 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2395 | */ | |
2396 | GEM_BUG_ON(!ringbuf->reserved_size); | |
2397 | ||
2398 | list_for_each_entry(target, &engine->request_list, list) { | |
2399 | unsigned space; | |
2400 | ||
79bbcc29 | 2401 | /* |
92dcc67c CW |
2402 | * The request queue is per-engine, so can contain requests |
2403 | * from multiple ringbuffers. Here, we must ignore any that | |
2404 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2405 | */ |
92dcc67c CW |
2406 | if (target->ringbuf != ringbuf) |
2407 | continue; | |
2408 | ||
2409 | /* Would completion of this request free enough space? */ | |
2410 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2411 | ringbuf->size); | |
2412 | if (space >= bytes) | |
2413 | break; | |
79bbcc29 | 2414 | } |
29b1b415 | 2415 | |
92dcc67c CW |
2416 | if (WARN_ON(&target->list == &engine->request_list)) |
2417 | return -ENOSPC; | |
2418 | ||
2419 | return i915_wait_request(target); | |
29b1b415 JH |
2420 | } |
2421 | ||
92dcc67c | 2422 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2423 | { |
92dcc67c | 2424 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2425 | int remain_actual = ringbuf->size - ringbuf->tail; |
92dcc67c CW |
2426 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2427 | int bytes = num_dwords * sizeof(u32); | |
2428 | int total_bytes, wait_bytes; | |
79bbcc29 | 2429 | bool need_wrap = false; |
29b1b415 | 2430 | |
92dcc67c | 2431 | total_bytes = bytes + ringbuf->reserved_size; |
29b1b415 | 2432 | |
79bbcc29 JH |
2433 | if (unlikely(bytes > remain_usable)) { |
2434 | /* | |
2435 | * Not enough space for the basic request. So need to flush | |
2436 | * out the remainder and then wait for base + reserved. | |
2437 | */ | |
2438 | wait_bytes = remain_actual + total_bytes; | |
2439 | need_wrap = true; | |
92dcc67c CW |
2440 | } else if (unlikely(total_bytes > remain_usable)) { |
2441 | /* | |
2442 | * The base request will fit but the reserved space | |
2443 | * falls off the end. So we don't need an immediate wrap | |
2444 | * and only need to effectively wait for the reserved | |
2445 | * size space from the start of ringbuffer. | |
2446 | */ | |
2447 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
79bbcc29 | 2448 | } else { |
92dcc67c CW |
2449 | /* No wrapping required, just waiting. */ |
2450 | wait_bytes = total_bytes; | |
cbcc80df MK |
2451 | } |
2452 | ||
92dcc67c CW |
2453 | if (wait_bytes > ringbuf->space) { |
2454 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2455 | if (unlikely(ret)) |
2456 | return ret; | |
79bbcc29 | 2457 | |
92dcc67c | 2458 | intel_ring_update_space(ringbuf); |
157d2c7f CW |
2459 | if (unlikely(ringbuf->space < wait_bytes)) |
2460 | return -EAGAIN; | |
cbcc80df MK |
2461 | } |
2462 | ||
92dcc67c CW |
2463 | if (unlikely(need_wrap)) { |
2464 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2465 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2466 | |
92dcc67c CW |
2467 | /* Fill the tail with MI_NOOP */ |
2468 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2469 | 0, remain_actual); | |
2470 | ringbuf->tail = 0; | |
2471 | ringbuf->space -= remain_actual; | |
2472 | } | |
304d695c | 2473 | |
92dcc67c CW |
2474 | ringbuf->space -= bytes; |
2475 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2476 | return 0; |
8187a2b7 | 2477 | } |
78501eac | 2478 | |
753b1ad4 | 2479 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2480 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2481 | { |
4a570db5 | 2482 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2483 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2484 | int ret; |
2485 | ||
2486 | if (num_dwords == 0) | |
2487 | return 0; | |
2488 | ||
18393f63 | 2489 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2490 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2491 | if (ret) |
2492 | return ret; | |
2493 | ||
2494 | while (num_dwords--) | |
e2f80391 | 2495 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2496 | |
e2f80391 | 2497 | intel_ring_advance(engine); |
753b1ad4 VS |
2498 | |
2499 | return 0; | |
2500 | } | |
2501 | ||
0bc40be8 | 2502 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2503 | { |
d04bce48 | 2504 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
498d2ac1 | 2505 | |
29dcb570 CW |
2506 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2507 | * so long as the semaphore value in the register/page is greater | |
2508 | * than the sync value), so whenever we reset the seqno, | |
2509 | * so long as we reset the tracking semaphore value to 0, it will | |
2510 | * always be before the next request's seqno. If we don't reset | |
2511 | * the semaphore value, then when the seqno moves backwards all | |
2512 | * future waits will complete instantly (causing rendering corruption). | |
2513 | */ | |
d04bce48 | 2514 | if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { |
0bc40be8 TU |
2515 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2516 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2517 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2518 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2519 | } |
a058d934 CW |
2520 | if (dev_priv->semaphore_obj) { |
2521 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2522 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2523 | void *semaphores = kmap(page); | |
2524 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2525 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2526 | kunmap(page); | |
2527 | } | |
29dcb570 CW |
2528 | memset(engine->semaphore.sync_seqno, 0, |
2529 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2530 | |
0bc40be8 | 2531 | engine->set_seqno(engine, seqno); |
01347126 | 2532 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2533 | |
0bc40be8 | 2534 | engine->hangcheck.seqno = seqno; |
8187a2b7 | 2535 | } |
62fdfeaf | 2536 | |
0bc40be8 | 2537 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2538 | u32 value) |
881f47b6 | 2539 | { |
0bc40be8 | 2540 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
881f47b6 XH |
2541 | |
2542 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2543 | |
2544 | /* Disable notification that the ring is IDLE. The GT | |
2545 | * will then assume that it is busy and bring it out of rc6. | |
2546 | */ | |
0206e353 | 2547 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2548 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2549 | ||
2550 | /* Clear the context id. Here be magic! */ | |
2551 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2552 | |
12f55818 | 2553 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2554 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2555 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2556 | 50)) | |
2557 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2558 | |
12f55818 | 2559 | /* Now that the ring is fully powered up, update the tail */ |
0bc40be8 TU |
2560 | I915_WRITE_TAIL(engine, value); |
2561 | POSTING_READ(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2562 | |
2563 | /* Let the ring send IDLE messages to the GT again, | |
2564 | * and so let it sleep to conserve power when idle. | |
2565 | */ | |
0206e353 | 2566 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2567 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2568 | } |
2569 | ||
a84c3ae1 | 2570 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2571 | u32 invalidate, u32 flush) |
881f47b6 | 2572 | { |
4a570db5 | 2573 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2574 | uint32_t cmd; |
b72f3acb CW |
2575 | int ret; |
2576 | ||
5fb9de1a | 2577 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2578 | if (ret) |
2579 | return ret; | |
2580 | ||
71a77e07 | 2581 | cmd = MI_FLUSH_DW; |
e2f80391 | 2582 | if (INTEL_INFO(engine->dev)->gen >= 8) |
075b3bba | 2583 | cmd += 1; |
f0a1fb10 CW |
2584 | |
2585 | /* We always require a command barrier so that subsequent | |
2586 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2587 | * wrt the contents of the write cache being flushed to memory | |
2588 | * (and thus being coherent from the CPU). | |
2589 | */ | |
2590 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2591 | ||
9a289771 JB |
2592 | /* |
2593 | * Bspec vol 1c.5 - video engine command streamer: | |
2594 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2595 | * operation is complete. This bit is only valid when the | |
2596 | * Post-Sync Operation field is a value of 1h or 3h." | |
2597 | */ | |
71a77e07 | 2598 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2599 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2600 | ||
e2f80391 TU |
2601 | intel_ring_emit(engine, cmd); |
2602 | intel_ring_emit(engine, | |
2603 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
2604 | if (INTEL_INFO(engine->dev)->gen >= 8) { | |
2605 | intel_ring_emit(engine, 0); /* upper addr */ | |
2606 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2607 | } else { |
e2f80391 TU |
2608 | intel_ring_emit(engine, 0); |
2609 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2610 | } |
e2f80391 | 2611 | intel_ring_advance(engine); |
b72f3acb | 2612 | return 0; |
881f47b6 XH |
2613 | } |
2614 | ||
1c7a0623 | 2615 | static int |
53fddaf7 | 2616 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2617 | u64 offset, u32 len, |
8e004efc | 2618 | unsigned dispatch_flags) |
1c7a0623 | 2619 | { |
4a570db5 | 2620 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2621 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2622 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2623 | int ret; |
2624 | ||
5fb9de1a | 2625 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2626 | if (ret) |
2627 | return ret; | |
2628 | ||
2629 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2630 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2631 | (dispatch_flags & I915_DISPATCH_RS ? |
2632 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2633 | intel_ring_emit(engine, lower_32_bits(offset)); |
2634 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2635 | intel_ring_emit(engine, MI_NOOP); | |
2636 | intel_ring_advance(engine); | |
1c7a0623 BW |
2637 | |
2638 | return 0; | |
2639 | } | |
2640 | ||
d7d4eedd | 2641 | static int |
53fddaf7 | 2642 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2643 | u64 offset, u32 len, |
2644 | unsigned dispatch_flags) | |
d7d4eedd | 2645 | { |
4a570db5 | 2646 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2647 | int ret; |
2648 | ||
5fb9de1a | 2649 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2650 | if (ret) |
2651 | return ret; | |
2652 | ||
e2f80391 | 2653 | intel_ring_emit(engine, |
77072258 | 2654 | MI_BATCH_BUFFER_START | |
8e004efc | 2655 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2656 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2657 | (dispatch_flags & I915_DISPATCH_RS ? | |
2658 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2659 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2660 | intel_ring_emit(engine, offset); |
2661 | intel_ring_advance(engine); | |
d7d4eedd CW |
2662 | |
2663 | return 0; | |
2664 | } | |
2665 | ||
881f47b6 | 2666 | static int |
53fddaf7 | 2667 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2668 | u64 offset, u32 len, |
8e004efc | 2669 | unsigned dispatch_flags) |
881f47b6 | 2670 | { |
4a570db5 | 2671 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2672 | int ret; |
ab6f8e32 | 2673 | |
5fb9de1a | 2674 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2675 | if (ret) |
2676 | return ret; | |
e1f99ce6 | 2677 | |
e2f80391 | 2678 | intel_ring_emit(engine, |
d7d4eedd | 2679 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2680 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2681 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2682 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2683 | intel_ring_emit(engine, offset); |
2684 | intel_ring_advance(engine); | |
ab6f8e32 | 2685 | |
0206e353 | 2686 | return 0; |
881f47b6 XH |
2687 | } |
2688 | ||
549f7365 CW |
2689 | /* Blitter support (SandyBridge+) */ |
2690 | ||
a84c3ae1 | 2691 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2692 | u32 invalidate, u32 flush) |
8d19215b | 2693 | { |
4a570db5 | 2694 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2695 | struct drm_device *dev = engine->dev; |
71a77e07 | 2696 | uint32_t cmd; |
b72f3acb CW |
2697 | int ret; |
2698 | ||
5fb9de1a | 2699 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2700 | if (ret) |
2701 | return ret; | |
2702 | ||
71a77e07 | 2703 | cmd = MI_FLUSH_DW; |
dbef0f15 | 2704 | if (INTEL_INFO(dev)->gen >= 8) |
075b3bba | 2705 | cmd += 1; |
f0a1fb10 CW |
2706 | |
2707 | /* We always require a command barrier so that subsequent | |
2708 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2709 | * wrt the contents of the write cache being flushed to memory | |
2710 | * (and thus being coherent from the CPU). | |
2711 | */ | |
2712 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2713 | ||
9a289771 JB |
2714 | /* |
2715 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2716 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2717 | * operation is complete. This bit is only valid when the | |
2718 | * Post-Sync Operation field is a value of 1h or 3h." | |
2719 | */ | |
71a77e07 | 2720 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2721 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2722 | intel_ring_emit(engine, cmd); |
2723 | intel_ring_emit(engine, | |
2724 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
dbef0f15 | 2725 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 TU |
2726 | intel_ring_emit(engine, 0); /* upper addr */ |
2727 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2728 | } else { |
e2f80391 TU |
2729 | intel_ring_emit(engine, 0); |
2730 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2731 | } |
e2f80391 | 2732 | intel_ring_advance(engine); |
fd3da6c9 | 2733 | |
b72f3acb | 2734 | return 0; |
8d19215b ZN |
2735 | } |
2736 | ||
5c1143bb XH |
2737 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2738 | { | |
4640c4ff | 2739 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2740 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
2741 | struct drm_i915_gem_object *obj; |
2742 | int ret; | |
5c1143bb | 2743 | |
e2f80391 TU |
2744 | engine->name = "render ring"; |
2745 | engine->id = RCS; | |
2746 | engine->exec_id = I915_EXEC_RENDER; | |
83e53802 | 2747 | engine->hw_id = 0; |
e2f80391 | 2748 | engine->mmio_base = RENDER_RING_BASE; |
59465b5f | 2749 | |
707d9cf9 | 2750 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2751 | if (i915_semaphore_is_enabled(dev)) { |
2752 | obj = i915_gem_alloc_object(dev, 4096); | |
2753 | if (obj == NULL) { | |
2754 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2755 | i915.semaphores = 0; | |
2756 | } else { | |
2757 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2758 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2759 | if (ret != 0) { | |
2760 | drm_gem_object_unreference(&obj->base); | |
2761 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2762 | i915.semaphores = 0; | |
2763 | } else | |
2764 | dev_priv->semaphore_obj = obj; | |
2765 | } | |
2766 | } | |
7225342a | 2767 | |
e2f80391 TU |
2768 | engine->init_context = intel_rcs_ctx_init; |
2769 | engine->add_request = gen6_add_request; | |
2770 | engine->flush = gen8_render_ring_flush; | |
2771 | engine->irq_get = gen8_ring_get_irq; | |
2772 | engine->irq_put = gen8_ring_put_irq; | |
2773 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2774 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2775 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2776 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2777 | if (i915_semaphore_is_enabled(dev)) { |
3e78998a | 2778 | WARN_ON(!dev_priv->semaphore_obj); |
e2f80391 TU |
2779 | engine->semaphore.sync_to = gen8_ring_sync; |
2780 | engine->semaphore.signal = gen8_rcs_signal; | |
2781 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 BW |
2782 | } |
2783 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
e2f80391 TU |
2784 | engine->init_context = intel_rcs_ctx_init; |
2785 | engine->add_request = gen6_add_request; | |
2786 | engine->flush = gen7_render_ring_flush; | |
6c6cf5aa | 2787 | if (INTEL_INFO(dev)->gen == 6) |
e2f80391 TU |
2788 | engine->flush = gen6_render_ring_flush; |
2789 | engine->irq_get = gen6_ring_get_irq; | |
2790 | engine->irq_put = gen6_ring_put_irq; | |
2791 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2792 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2793 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2794 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2795 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2796 | engine->semaphore.sync_to = gen6_ring_sync; |
2797 | engine->semaphore.signal = gen6_signal; | |
707d9cf9 BW |
2798 | /* |
2799 | * The current semaphore is only applied on pre-gen8 | |
2800 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2801 | * platform. So the semaphore between RCS and VCS2 is | |
2802 | * initialized as INVALID. Gen8 will initialize the | |
2803 | * sema between VCS2 and RCS later. | |
2804 | */ | |
e2f80391 TU |
2805 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
2806 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2807 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2808 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2809 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2810 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2811 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2812 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2813 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2814 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2815 | } |
c6df541c | 2816 | } else if (IS_GEN5(dev)) { |
e2f80391 TU |
2817 | engine->add_request = pc_render_add_request; |
2818 | engine->flush = gen4_render_ring_flush; | |
2819 | engine->get_seqno = pc_render_get_seqno; | |
2820 | engine->set_seqno = pc_render_set_seqno; | |
2821 | engine->irq_get = gen5_ring_get_irq; | |
2822 | engine->irq_put = gen5_ring_put_irq; | |
2823 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | | |
cc609d5d | 2824 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 2825 | } else { |
e2f80391 | 2826 | engine->add_request = i9xx_add_request; |
46f0f8d1 | 2827 | if (INTEL_INFO(dev)->gen < 4) |
e2f80391 | 2828 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2829 | else |
e2f80391 TU |
2830 | engine->flush = gen4_render_ring_flush; |
2831 | engine->get_seqno = ring_get_seqno; | |
2832 | engine->set_seqno = ring_set_seqno; | |
c2798b19 | 2833 | if (IS_GEN2(dev)) { |
e2f80391 TU |
2834 | engine->irq_get = i8xx_ring_get_irq; |
2835 | engine->irq_put = i8xx_ring_put_irq; | |
c2798b19 | 2836 | } else { |
e2f80391 TU |
2837 | engine->irq_get = i9xx_ring_get_irq; |
2838 | engine->irq_put = i9xx_ring_put_irq; | |
c2798b19 | 2839 | } |
e2f80391 | 2840 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2841 | } |
e2f80391 | 2842 | engine->write_tail = ring_write_tail; |
707d9cf9 | 2843 | |
d7d4eedd | 2844 | if (IS_HASWELL(dev)) |
e2f80391 | 2845 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
1c7a0623 | 2846 | else if (IS_GEN8(dev)) |
e2f80391 | 2847 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
d7d4eedd | 2848 | else if (INTEL_INFO(dev)->gen >= 6) |
e2f80391 | 2849 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
fb3256da | 2850 | else if (INTEL_INFO(dev)->gen >= 4) |
e2f80391 | 2851 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
fb3256da | 2852 | else if (IS_I830(dev) || IS_845G(dev)) |
e2f80391 | 2853 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
fb3256da | 2854 | else |
e2f80391 TU |
2855 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
2856 | engine->init_hw = init_render_ring; | |
2857 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2858 | |
b45305fc DV |
2859 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2860 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2861 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2862 | if (obj == NULL) { |
2863 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2864 | return -ENOMEM; | |
2865 | } | |
2866 | ||
be1fa129 | 2867 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2868 | if (ret != 0) { |
2869 | drm_gem_object_unreference(&obj->base); | |
2870 | DRM_ERROR("Failed to ping batch bo\n"); | |
2871 | return ret; | |
2872 | } | |
2873 | ||
e2f80391 TU |
2874 | engine->scratch.obj = obj; |
2875 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2876 | } |
2877 | ||
e2f80391 | 2878 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
2879 | if (ret) |
2880 | return ret; | |
2881 | ||
2882 | if (INTEL_INFO(dev)->gen >= 5) { | |
e2f80391 | 2883 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2884 | if (ret) |
2885 | return ret; | |
2886 | } | |
2887 | ||
2888 | return 0; | |
5c1143bb XH |
2889 | } |
2890 | ||
2891 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2892 | { | |
4640c4ff | 2893 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2894 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 2895 | |
e2f80391 TU |
2896 | engine->name = "bsd ring"; |
2897 | engine->id = VCS; | |
2898 | engine->exec_id = I915_EXEC_BSD; | |
83e53802 | 2899 | engine->hw_id = 1; |
58fa3835 | 2900 | |
e2f80391 | 2901 | engine->write_tail = ring_write_tail; |
780f18c8 | 2902 | if (INTEL_INFO(dev)->gen >= 6) { |
e2f80391 | 2903 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2904 | /* gen6 bsd needs a special wa for tail updates */ |
2905 | if (IS_GEN6(dev)) | |
e2f80391 TU |
2906 | engine->write_tail = gen6_bsd_ring_write_tail; |
2907 | engine->flush = gen6_bsd_ring_flush; | |
2908 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2909 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2910 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2911 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 2912 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 2913 | engine->irq_enable_mask = |
abd58f01 | 2914 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
e2f80391 TU |
2915 | engine->irq_get = gen8_ring_get_irq; |
2916 | engine->irq_put = gen8_ring_put_irq; | |
2917 | engine->dispatch_execbuffer = | |
1c7a0623 | 2918 | gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2919 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2920 | engine->semaphore.sync_to = gen8_ring_sync; |
2921 | engine->semaphore.signal = gen8_xcs_signal; | |
2922 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 2923 | } |
abd58f01 | 2924 | } else { |
e2f80391 TU |
2925 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
2926 | engine->irq_get = gen6_ring_get_irq; | |
2927 | engine->irq_put = gen6_ring_put_irq; | |
2928 | engine->dispatch_execbuffer = | |
1c7a0623 | 2929 | gen6_ring_dispatch_execbuffer; |
707d9cf9 | 2930 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2931 | engine->semaphore.sync_to = gen6_ring_sync; |
2932 | engine->semaphore.signal = gen6_signal; | |
2933 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2934 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2935 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2936 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2937 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2938 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2939 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2940 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2941 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2942 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2943 | } |
abd58f01 | 2944 | } |
58fa3835 | 2945 | } else { |
e2f80391 TU |
2946 | engine->mmio_base = BSD_RING_BASE; |
2947 | engine->flush = bsd_ring_flush; | |
2948 | engine->add_request = i9xx_add_request; | |
2949 | engine->get_seqno = ring_get_seqno; | |
2950 | engine->set_seqno = ring_set_seqno; | |
e48d8634 | 2951 | if (IS_GEN5(dev)) { |
e2f80391 TU |
2952 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
2953 | engine->irq_get = gen5_ring_get_irq; | |
2954 | engine->irq_put = gen5_ring_put_irq; | |
e48d8634 | 2955 | } else { |
e2f80391 TU |
2956 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
2957 | engine->irq_get = i9xx_ring_get_irq; | |
2958 | engine->irq_put = i9xx_ring_put_irq; | |
e48d8634 | 2959 | } |
e2f80391 | 2960 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2961 | } |
e2f80391 | 2962 | engine->init_hw = init_ring_common; |
58fa3835 | 2963 | |
e2f80391 | 2964 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 2965 | } |
549f7365 | 2966 | |
845f74a7 | 2967 | /** |
62659920 | 2968 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
2969 | */ |
2970 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2971 | { | |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2973 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
2974 | |
2975 | engine->name = "bsd2 ring"; | |
2976 | engine->id = VCS2; | |
2977 | engine->exec_id = I915_EXEC_BSD; | |
83e53802 | 2978 | engine->hw_id = 4; |
e2f80391 TU |
2979 | |
2980 | engine->write_tail = ring_write_tail; | |
2981 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
2982 | engine->flush = gen6_bsd_ring_flush; | |
2983 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2984 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2985 | engine->get_seqno = ring_get_seqno; | |
e2f80391 TU |
2986 | engine->set_seqno = ring_set_seqno; |
2987 | engine->irq_enable_mask = | |
845f74a7 | 2988 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
e2f80391 TU |
2989 | engine->irq_get = gen8_ring_get_irq; |
2990 | engine->irq_put = gen8_ring_put_irq; | |
2991 | engine->dispatch_execbuffer = | |
845f74a7 | 2992 | gen8_ring_dispatch_execbuffer; |
3e78998a | 2993 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2994 | engine->semaphore.sync_to = gen8_ring_sync; |
2995 | engine->semaphore.signal = gen8_xcs_signal; | |
2996 | GEN8_RING_SEMAPHORE_INIT(engine); | |
3e78998a | 2997 | } |
e2f80391 | 2998 | engine->init_hw = init_ring_common; |
845f74a7 | 2999 | |
e2f80391 | 3000 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
3001 | } |
3002 | ||
549f7365 CW |
3003 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
3004 | { | |
4640c4ff | 3005 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3006 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
3007 | |
3008 | engine->name = "blitter ring"; | |
3009 | engine->id = BCS; | |
3010 | engine->exec_id = I915_EXEC_BLT; | |
83e53802 | 3011 | engine->hw_id = 2; |
e2f80391 TU |
3012 | |
3013 | engine->mmio_base = BLT_RING_BASE; | |
3014 | engine->write_tail = ring_write_tail; | |
3015 | engine->flush = gen6_ring_flush; | |
3016 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3017 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3018 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3019 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 3020 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 3021 | engine->irq_enable_mask = |
abd58f01 | 3022 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
e2f80391 TU |
3023 | engine->irq_get = gen8_ring_get_irq; |
3024 | engine->irq_put = gen8_ring_put_irq; | |
3025 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3026 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3027 | engine->semaphore.sync_to = gen8_ring_sync; |
3028 | engine->semaphore.signal = gen8_xcs_signal; | |
3029 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3030 | } |
abd58f01 | 3031 | } else { |
e2f80391 TU |
3032 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3033 | engine->irq_get = gen6_ring_get_irq; | |
3034 | engine->irq_put = gen6_ring_put_irq; | |
3035 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3036 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3037 | engine->semaphore.signal = gen6_signal; |
3038 | engine->semaphore.sync_to = gen6_ring_sync; | |
707d9cf9 BW |
3039 | /* |
3040 | * The current semaphore is only applied on pre-gen8 | |
3041 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3042 | * platform. So the semaphore between BCS and VCS2 is | |
3043 | * initialized as INVALID. Gen8 will initialize the | |
3044 | * sema between BCS and VCS2 later. | |
3045 | */ | |
e2f80391 TU |
3046 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
3047 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
3048 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3049 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
3050 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3051 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
3052 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
3053 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
3054 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
3055 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3056 | } |
abd58f01 | 3057 | } |
e2f80391 | 3058 | engine->init_hw = init_ring_common; |
549f7365 | 3059 | |
e2f80391 | 3060 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3061 | } |
a7b9761d | 3062 | |
9a8a2213 BW |
3063 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3064 | { | |
4640c4ff | 3065 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3066 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3067 | |
e2f80391 TU |
3068 | engine->name = "video enhancement ring"; |
3069 | engine->id = VECS; | |
3070 | engine->exec_id = I915_EXEC_VEBOX; | |
83e53802 | 3071 | engine->hw_id = 3; |
9a8a2213 | 3072 | |
e2f80391 TU |
3073 | engine->mmio_base = VEBOX_RING_BASE; |
3074 | engine->write_tail = ring_write_tail; | |
3075 | engine->flush = gen6_ring_flush; | |
3076 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3077 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3078 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3079 | engine->set_seqno = ring_set_seqno; |
abd58f01 BW |
3080 | |
3081 | if (INTEL_INFO(dev)->gen >= 8) { | |
e2f80391 | 3082 | engine->irq_enable_mask = |
40c499f9 | 3083 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
e2f80391 TU |
3084 | engine->irq_get = gen8_ring_get_irq; |
3085 | engine->irq_put = gen8_ring_put_irq; | |
3086 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3087 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3088 | engine->semaphore.sync_to = gen8_ring_sync; |
3089 | engine->semaphore.signal = gen8_xcs_signal; | |
3090 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3091 | } |
abd58f01 | 3092 | } else { |
e2f80391 TU |
3093 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3094 | engine->irq_get = hsw_vebox_get_irq; | |
3095 | engine->irq_put = hsw_vebox_put_irq; | |
3096 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3097 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3098 | engine->semaphore.sync_to = gen6_ring_sync; |
3099 | engine->semaphore.signal = gen6_signal; | |
3100 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
3101 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3102 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3103 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3104 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3105 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3106 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3107 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3108 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3109 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3110 | } |
abd58f01 | 3111 | } |
e2f80391 | 3112 | engine->init_hw = init_ring_common; |
9a8a2213 | 3113 | |
e2f80391 | 3114 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3115 | } |
3116 | ||
a7b9761d | 3117 | int |
4866d729 | 3118 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3119 | { |
4a570db5 | 3120 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3121 | int ret; |
3122 | ||
e2f80391 | 3123 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3124 | return 0; |
3125 | ||
e2f80391 | 3126 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3127 | if (ret) |
3128 | return ret; | |
3129 | ||
a84c3ae1 | 3130 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3131 | |
e2f80391 | 3132 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3133 | return 0; |
3134 | } | |
3135 | ||
3136 | int | |
2f20055d | 3137 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3138 | { |
4a570db5 | 3139 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3140 | uint32_t flush_domains; |
3141 | int ret; | |
3142 | ||
3143 | flush_domains = 0; | |
e2f80391 | 3144 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3145 | flush_domains = I915_GEM_GPU_DOMAINS; |
3146 | ||
e2f80391 | 3147 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3148 | if (ret) |
3149 | return ret; | |
3150 | ||
a84c3ae1 | 3151 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3152 | |
e2f80391 | 3153 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3154 | return 0; |
3155 | } | |
e3efda49 CW |
3156 | |
3157 | void | |
117897f4 | 3158 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3159 | { |
3160 | int ret; | |
3161 | ||
117897f4 | 3162 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3163 | return; |
3164 | ||
666796da | 3165 | ret = intel_engine_idle(engine); |
f4457ae7 | 3166 | if (ret) |
e3efda49 | 3167 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3168 | engine->name, ret); |
e3efda49 | 3169 | |
0bc40be8 | 3170 | stop_ring(engine); |
e3efda49 | 3171 | } |