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drm/i915: Enable querying offset of UV plane with intel_plane_obj_offset
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
6258fbe2 84static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a84c3ae1 94gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
a84c3ae1 98 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
31b14c9f 103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
5fb9de1a 109 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118}
119
120static int
a84c3ae1 121gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 122 u32 invalidate_domains,
123 u32 flush_domains)
62fdfeaf 124{
a84c3ae1 125 struct intel_engine_cs *ring = req->ring;
78501eac 126 struct drm_device *dev = ring->dev;
6f392d54 127 u32 cmd;
b72f3acb 128 int ret;
6f392d54 129
36d527de
CW		 130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 160 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
62fdfeaf 163
36d527de
CW		 164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
70eac33e 167
5fb9de1a 168 ret = intel_ring_begin(req, 2);
36d527de
CW		 169 if (ret)
170 return ret;
b72f3acb 171
36d527de
CW		 172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
b72f3acb
CW		 175
176 return 0;
8187a2b7
ZN		 177}
178
8d315287
JB		 179/**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216static int
f2cf1fcc 217intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 218{
f2cf1fcc 219 struct intel_engine_cs *ring = req->ring;
18393f63 220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 221 int ret;
222
5fb9de1a 223 ret = intel_ring_begin(req, 6);
8d315287
JB		 224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
5fb9de1a 236 ret = intel_ring_begin(req, 6);
8d315287
JB		 237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
251static int
a84c3ae1
JH		 252gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
8d315287 254{
a84c3ae1 255 struct intel_engine_cs *ring = req->ring;
8d315287 256 u32 flags = 0;
18393f63 257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 258 int ret;
259
b3111509 260 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 261 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 262 if (ret)
263 return ret;
264
8d315287
JB		 265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
7d54a904
CW		 269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
97f209bc 276 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
3ac78313 288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 289 }
8d315287 290
5fb9de1a 291 ret = intel_ring_begin(req, 4);
8d315287
JB		 292 if (ret)
293 return ret;
294
6c6cf5aa 295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 298 intel_ring_emit(ring, 0);
8d315287
JB		 299 intel_ring_advance(ring);
300
301 return 0;
302}
303
f3987631 304static int
f2cf1fcc 305gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 306{
f2cf1fcc 307 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 308 int ret;
309
5fb9de1a 310 ret = intel_ring_begin(req, 4);
f3987631
PZ		 311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322}
323
4772eaeb 324static int
a84c3ae1 325gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 326 u32 invalidate_domains, u32 flush_domains)
327{
a84c3ae1 328 struct intel_engine_cs *ring = req->ring;
4772eaeb 329 u32 flags = 0;
18393f63 330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 331 int ret;
332
f3987631
PZ		 333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
4772eaeb
PZ		 343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 364
add284a3
CW		 365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
f3987631
PZ		 367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
f2cf1fcc 370 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 371 }
372
5fb9de1a 373 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
b9e1faa7 379 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384}
385
884ceace 386static int
f2cf1fcc 387gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 388 u32 flags, u32 scratch_addr)
389{
f2cf1fcc 390 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 391 int ret;
392
5fb9de1a 393 ret = intel_ring_begin(req, 6);
884ceace
KG		 394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406}
407
a5f3d68e 408static int
a84c3ae1 409gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 410 u32 invalidate_domains, u32 flush_domains)
411{
412 u32 flags = 0;
f2cf1fcc 413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 414 int ret;
a5f3d68e
BW		 415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 433 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
a5f3d68e
BW		 439 }
440
f2cf1fcc 441 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 442}
443
a4872ba6 444static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 445 u32 value)
d46eefa2 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 448 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 449}
450
a4872ba6 451u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 452{
4640c4ff 453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 454 u64 acthd;
8187a2b7 455
50877445
CW		 456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
8187a2b7
ZN		 465}
466
a4872ba6 467static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 468{
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476}
477
af75f269
DL		 478static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479{
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538}
539
a4872ba6 540static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 541{
9991ae78 542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 543
9991ae78
CW		 544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
9991ae78
CW		 554 }
555 }
b7884eb4 556
7f2ab699 557 I915_WRITE_CTL(ring, 0);
570ef608 558 I915_WRITE_HEAD(ring, 0);
78501eac 559 ring->write_tail(ring, 0);
8187a2b7 560
9991ae78
CW		 561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
a51435a3 565
9991ae78
CW		 566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567}
8187a2b7 568
a4872ba6 569static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 570{
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 575 int ret = 0;
576
59bad947 577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
8187a2b7 588
9991ae78 589 if (!stop_ring(ring)) {
6fd0d56e
CW		 590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
9991ae78
CW		 597 ret = -EIO;
598 goto out;
6fd0d56e 599 }
8187a2b7
ZN		 600 }
601
9991ae78
CW		 602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
ece4a17d
JK		 607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
0d8957c8
DV		 610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
f343c5f6 614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
7f2ab699 623 I915_WRITE_CTL(ring,
93b0a4e0 624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 625 | RING_VALID);
8187a2b7 626
8187a2b7 627 /* If the head is still not zero, the ring is dead */
f01db988 628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 631 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 637 ret = -EIO;
638 goto out;
8187a2b7
ZN		 639 }
640
ebd0fd4b 641 ringbuf->last_retired_head = -1;
5c6c6003
CW		 642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 644 intel_ring_update_space(ringbuf);
1ec14ad3 645
50f018df
CW		 646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
b7884eb4 648out:
59bad947 649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 650
651 return ret;
8187a2b7
ZN		 652}
653
9b1136d5
OM		 654void
655intel_fini_pipe_control(struct intel_engine_cs *ring)
656{
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669}
670
671int
672intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 673{
c6df541c
CW		 674 int ret;
675
bfc882b4 676 WARN_ON(ring->scratch.obj);
c6df541c 677
0d1aacac
CW		 678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
c6df541c
CW		 680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
e4ffd173 684
a9cc726c
DV		 685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
c6df541c 688
1ec9e26d 689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 690 if (ret)
691 goto err_unref;
692
0d1aacac
CW		 693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
56b085a0 696 ret = -ENOMEM;
c6df541c 697 goto err_unpin;
56b085a0 698 }
c6df541c 699
2b1086cc 700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 701 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 702 return 0;
703
704err_unpin:
d7f46fc4 705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 706err_unref:
0d1aacac 707 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 708err:
c6df541c
CW		 709 return ret;
710}
711
e2be4faf 712static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 713{
7225342a 714 int ret, i;
e2be4faf 715 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 718 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 719
e6c1abb7 720 if (WARN_ON_ONCE(w->count == 0))
7225342a 721 return 0;
888b5995 722
7225342a 723 ring->gpu_caches_dirty = true;
4866d729 724 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 725 if (ret)
726 return ret;
888b5995 727
5fb9de1a 728 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 729 if (ret)
730 return ret;
731
22a916aa 732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 733 for (i = 0; i < w->count; i++) {
7225342a
MK		 734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
22a916aa 737 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
4866d729 742 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 743 if (ret)
744 return ret;
888b5995 745
7225342a 746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 747
7225342a 748 return 0;
86d7f238
AS		 749}
750
8753181e 751static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 752{
753 int ret;
754
e2be4faf 755 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 756 if (ret != 0)
757 return ret;
758
be01363f 759 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764}
765
7225342a 766static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 767 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 768{
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
86d7f238
AS		 781}
782
ca5a0fbd 783#define WA_REG(addr, mask, val) do { \
cf4b0de6 784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 785 if (r) \
786 return r; \
ca5a0fbd 787 } while (0)
7225342a
MK		 788
789#define WA_SET_BIT_MASKED(addr, mask) \
26459343 790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 791
792#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 794
98533251 795#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 797
cf4b0de6
DL		 798#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 800
cf4b0de6 801#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 802
00e1e623 803static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 804{
888b5995
AS		 805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 807
9cc83020
VS		 808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
809
2441f877
VS		 810 /* WaDisableAsyncFlipPerfMode:bdw */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
86d7f238 813 /* WaDisablePartialInstShootdown:bdw */
101b376d 814 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
817 STALL_DOP_GATING_DISABLE);
86d7f238 818
101b376d 819 /* WaDisableDopClockGating:bdw */
7225342a
MK		 820 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
821 DOP_CLOCK_GATING_DISABLE);
86d7f238 822
7225342a
MK		 823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
824 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 825
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
829 */
7225342a 830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 831 /* WaForceEnableNonCoherent:bdw */
7225342a 832 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
835 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 836 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 837 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 838 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 839
2701fc43
KG		 840 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
841 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
842 * polygons in the same 8x4 pixel/sample area to be processed without
843 * stalling waiting for the earlier ones to write to Hierarchical Z
844 * buffer."
845 *
846 * This optimization is off by default for Broadwell; turn it on.
847 */
848 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
849
86d7f238 850 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 851 WA_SET_BIT_MASKED(CACHE_MODE_1,
852 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 853
854 /*
855 * BSpec recommends 8x4 when MSAA is used,
856 * however in practice 16x4 seems fastest.
857 *
858 * Note that PS/WM thread counts depend on the WIZ hashing
859 * disable bit, which we don't touch here, but it's good
860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
861 */
98533251
DL		 862 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
863 GEN6_WIZ_HASHING_MASK,
864 GEN6_WIZ_HASHING_16x4);
888b5995 865
86d7f238
AS		 866 return 0;
867}
868
00e1e623
VS		 869static int chv_init_workarounds(struct intel_engine_cs *ring)
870{
00e1e623
VS		 871 struct drm_device *dev = ring->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873
9cc83020
VS		 874 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
875
2441f877
VS		 876 /* WaDisableAsyncFlipPerfMode:chv */
877 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
878
00e1e623 879 /* WaDisablePartialInstShootdown:chv */
00e1e623 880 /* WaDisableThreadStallDopClockGating:chv */
7225342a 881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 882 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
883 STALL_DOP_GATING_DISABLE);
00e1e623 884
95289009
AS		 885 /* Use Force Non-Coherent whenever executing a 3D context. This is a
886 * workaround for a possible hang in the unlikely event a TLB
887 * invalidation occurs during a PSD flush.
888 */
889 /* WaForceEnableNonCoherent:chv */
890 /* WaHdcDisableFetchWhenMasked:chv */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0,
892 HDC_FORCE_NON_COHERENT |
893 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
894
973a5b06
KG		 895 /* According to the CACHE_MODE_0 default value documentation, some
896 * CHV platforms disable this optimization by default. Turn it on.
897 */
898 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
899
14bc16e3
VS		 900 /* Wa4x4STCOptimizationDisable:chv */
901 WA_SET_BIT_MASKED(CACHE_MODE_1,
902 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
903
d60de81d
KG		 904 /* Improve HiZ throughput on CHV. */
905 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
906
e7fc2436
VS		 907 /*
908 * BSpec recommends 8x4 when MSAA is used,
909 * however in practice 16x4 seems fastest.
910 *
911 * Note that PS/WM thread counts depend on the WIZ hashing
912 * disable bit, which we don't touch here, but it's good
913 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
914 */
915 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
916 GEN6_WIZ_HASHING_MASK,
917 GEN6_WIZ_HASHING_16x4);
918
7225342a
MK		 919 return 0;
920}
921
3b106531
HN		 922static int gen9_init_workarounds(struct intel_engine_cs *ring)
923{
ab0dfafe
HN		 924 struct drm_device *dev = ring->dev;
925 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 926 uint32_t tmp;
ab0dfafe 927
b0e6f6d4 928 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
931
a119a6e6 932 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
935
d2a31dbd
NH		 936 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
937 INTEL_REVID(dev) == SKL_REVID_B0)) ||
938 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 940 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
941 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 942 }
943
a13d215f
NH		 944 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
945 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
946 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
948 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 949 /*
950 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
951 * but we do that in per ctx batchbuffer as there is an issue
952 * with this register not getting restored on ctx restore
953 */
183c6dac
DL		 954 }
955
27a1b688
NH		 956 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
957 IS_BROXTON(dev)) {
958 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 959 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
960 GEN9_ENABLE_YV12_BUGFIX);
961 }
962
5068368c 963 /* Wa4x4STCOptimizationDisable:skl,bxt */
1840481f
HN		 964 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
965
27160c96 966 /* WaDisablePartialResolveInVc:skl,bxt */
9370cd98
DL		 967 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
968
16be17af 969 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 970 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
971 GEN9_CCS_TLB_PREFETCH_ENABLE);
972
5a2ae95e
ID		 973 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
974 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
975 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 976 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
977 PIXEL_MASK_CAMMING_DISABLE);
978
8ea6f892
ID		 979 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
980 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
981 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
982 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
983 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
984 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
985
8c761609
AS		 986 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
987 if (IS_SKYLAKE(dev) ||
988 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
989 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
990 GEN8_SAMPLER_POWER_BYPASS_DIS);
991 }
992
6b6d5626
RB		 993 /* WaDisableSTUnitPowerOptimization:skl,bxt */
994 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
995
3b106531
HN		 996 return 0;
997}
998
b7668791
DL		 999static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1000{
1001 struct drm_device *dev = ring->dev;
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 u8 vals[3] = { 0, 0, 0 };
1004 unsigned int i;
1005
1006 for (i = 0; i < 3; i++) {
1007 u8 ss;
1008
1009 /*
1010 * Only consider slices where one, and only one, subslice has 7
1011 * EUs
1012 */
1013 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1014 continue;
1015
1016 /*
1017 * subslice_7eu[i] != 0 (because of the check above) and
1018 * ss_max == 4 (maximum number of subslices possible per slice)
1019 *
1020 * -> 0 <= ss <= 3;
1021 */
1022 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1023 vals[i] = 3 - ss;
1024 }
1025
1026 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1027 return 0;
1028
1029 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1030 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1031 GEN9_IZ_HASHING_MASK(2) |
1032 GEN9_IZ_HASHING_MASK(1) |
1033 GEN9_IZ_HASHING_MASK(0),
1034 GEN9_IZ_HASHING(2, vals[2]) |
1035 GEN9_IZ_HASHING(1, vals[1]) |
1036 GEN9_IZ_HASHING(0, vals[0]));
1037
1038 return 0;
1039}
1040
1041
8d205494
DL		 1042static int skl_init_workarounds(struct intel_engine_cs *ring)
1043{
d0bbbc4f
DL		 1044 struct drm_device *dev = ring->dev;
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046
8d205494
DL		 1047 gen9_init_workarounds(ring);
1048
d0bbbc4f
DL		 1049 /* WaDisablePowerCompilerClockGating:skl */
1050 if (INTEL_REVID(dev) == SKL_REVID_B0)
1051 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1052 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1053
b62adbd1
NH		 1054 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1055 /*
1056 *Use Force Non-Coherent whenever executing a 3D context. This
1057 * is a workaround for a possible hang in the unlikely event
1058 * a TLB invalidation occurs during a PSD flush.
1059 */
1060 /* WaForceEnableNonCoherent:skl */
1061 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1062 HDC_FORCE_NON_COHERENT);
1063 }
1064
5b6fd12a
VS		 1065 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1066 INTEL_REVID(dev) == SKL_REVID_D0)
1067 /* WaBarrierPerformanceFixDisable:skl */
1068 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1069 HDC_FENCE_DEST_SLM_DISABLE |
1070 HDC_BARRIER_PERFORMANCE_DISABLE);
1071
9bd9dfb4
MK		 1072 /* WaDisableSbeCacheDispatchPortSharing:skl */
1073 if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1074 WA_SET_BIT_MASKED(
1075 GEN7_HALF_SLICE_CHICKEN1,
1076 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1077 }
1078
b7668791 1079 return skl_tune_iz_hashing(ring);
7225342a
MK		 1080}
1081
cae0437f
NH		 1082static int bxt_init_workarounds(struct intel_engine_cs *ring)
1083{
dfb601e6
NH		 1084 struct drm_device *dev = ring->dev;
1085 struct drm_i915_private *dev_priv = dev->dev_private;
1086
cae0437f
NH		 1087 gen9_init_workarounds(ring);
1088
dfb601e6
NH		 1089 /* WaDisableThreadStallDopClockGating:bxt */
1090 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1091 STALL_DOP_GATING_DISABLE);
1092
983b4b9d
NH		 1093 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1094 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1095 WA_SET_BIT_MASKED(
1096 GEN7_HALF_SLICE_CHICKEN1,
1097 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1098 }
1099
cae0437f
NH		 1100 return 0;
1101}
1102
771b9a53 1103int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1104{
1105 struct drm_device *dev = ring->dev;
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107
1108 WARN_ON(ring->id != RCS);
1109
1110 dev_priv->workarounds.count = 0;
1111
1112 if (IS_BROADWELL(dev))
1113 return bdw_init_workarounds(ring);
1114
1115 if (IS_CHERRYVIEW(dev))
1116 return chv_init_workarounds(ring);
00e1e623 1117
8d205494
DL		 1118 if (IS_SKYLAKE(dev))
1119 return skl_init_workarounds(ring);
cae0437f
NH		 1120
1121 if (IS_BROXTON(dev))
1122 return bxt_init_workarounds(ring);
3b106531 1123
00e1e623
VS		 1124 return 0;
1125}
1126
a4872ba6 1127static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1128{
78501eac 1129 struct drm_device *dev = ring->dev;
1ec14ad3 1130 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1131 int ret = init_ring_common(ring);
9c33baa6
KZ		 1132 if (ret)
1133 return ret;
a69ffdbf 1134
61a563a2
AG		 1135 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1136 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1137 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1138
1139 /* We need to disable the AsyncFlip performance optimisations in order
1140 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1141 * programmed to '1' on all products.
8693a824 1142 *
2441f877 1143 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1144 */
2441f877 1145 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1146 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1147
f05bb0c7 1148 /* Required for the hardware to program scanline values for waiting */
01fa0302 1149 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1150 if (INTEL_INFO(dev)->gen == 6)
1151 I915_WRITE(GFX_MODE,
aa83e30d 1152 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1153
01fa0302 1154 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1155 if (IS_GEN7(dev))
1156 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1157 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1158 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1159
5e13a0c5 1160 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1161 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1162 * "If this bit is set, STCunit will have LRA as replacement
1163 * policy. [...] This bit must be reset. LRA replacement
1164 * policy is not supported."
1165 */
1166 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1167 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1168 }
1169
9cc83020 1170 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1171 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1172
040d2baa 1173 if (HAS_L3_DPF(dev))
35a85ac6 1174 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1175
7225342a 1176 return init_workarounds_ring(ring);
8187a2b7
ZN		 1177}
1178
a4872ba6 1179static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1180{
b45305fc 1181 struct drm_device *dev = ring->dev;
3e78998a
BW		 1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183
1184 if (dev_priv->semaphore_obj) {
1185 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1186 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1187 dev_priv->semaphore_obj = NULL;
1188 }
b45305fc 1189
9b1136d5 1190 intel_fini_pipe_control(ring);
c6df541c
CW		 1191}
1192
f7169687 1193static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1194 unsigned int num_dwords)
1195{
1196#define MBOX_UPDATE_DWORDS 8
f7169687 1197 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1198 struct drm_device *dev = signaller->dev;
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 struct intel_engine_cs *waiter;
1201 int i, ret, num_rings;
1202
1203 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1204 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1205#undef MBOX_UPDATE_DWORDS
1206
5fb9de1a 1207 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1208 if (ret)
1209 return ret;
1210
1211 for_each_ring(waiter, dev_priv, i) {
6259cead 1212 u32 seqno;
3e78998a
BW		 1213 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1214 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1215 continue;
1216
f7169687 1217 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1218 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1219 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1220 PIPE_CONTROL_QW_WRITE |
1221 PIPE_CONTROL_FLUSH_ENABLE);
1222 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1223 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1224 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1225 intel_ring_emit(signaller, 0);
1226 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1227 MI_SEMAPHORE_TARGET(waiter->id));
1228 intel_ring_emit(signaller, 0);
1229 }
1230
1231 return 0;
1232}
1233
f7169687 1234static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1235 unsigned int num_dwords)
1236{
1237#define MBOX_UPDATE_DWORDS 6
f7169687 1238 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1239 struct drm_device *dev = signaller->dev;
1240 struct drm_i915_private *dev_priv = dev->dev_private;
1241 struct intel_engine_cs *waiter;
1242 int i, ret, num_rings;
1243
1244 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1245 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1246#undef MBOX_UPDATE_DWORDS
1247
5fb9de1a 1248 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1249 if (ret)
1250 return ret;
1251
1252 for_each_ring(waiter, dev_priv, i) {
6259cead 1253 u32 seqno;
3e78998a
BW		 1254 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1255 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1256 continue;
1257
f7169687 1258 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1259 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1260 MI_FLUSH_DW_OP_STOREDW);
1261 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1262 MI_FLUSH_DW_USE_GTT);
1263 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1264 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1265 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1266 MI_SEMAPHORE_TARGET(waiter->id));
1267 intel_ring_emit(signaller, 0);
1268 }
1269
1270 return 0;
1271}
1272
f7169687 1273static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1274 unsigned int num_dwords)
1ec14ad3 1275{
f7169687 1276 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1277 struct drm_device *dev = signaller->dev;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1279 struct intel_engine_cs *useless;
a1444b79 1280 int i, ret, num_rings;
78325f2d 1281
a1444b79
BW		 1282#define MBOX_UPDATE_DWORDS 3
1283 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1284 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1285#undef MBOX_UPDATE_DWORDS
024a43e1 1286
5fb9de1a 1287 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1288 if (ret)
1289 return ret;
024a43e1 1290
78325f2d
BW		 1291 for_each_ring(useless, dev_priv, i) {
1292 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1293 if (mbox_reg != GEN6_NOSYNC) {
f7169687 1294 u32 seqno = i915_gem_request_get_seqno(signaller_req);
78325f2d
BW		 1295 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1296 intel_ring_emit(signaller, mbox_reg);
6259cead 1297 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1298 }
1299 }
024a43e1 1300
a1444b79
BW		 1301 /* If num_dwords was rounded, make sure the tail pointer is correct */
1302 if (num_rings % 2 == 0)
1303 intel_ring_emit(signaller, MI_NOOP);
1304
024a43e1 1305 return 0;
1ec14ad3
CW		 1306}
1307
c8c99b0f
BW		 1308/**
1309 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1310 *
1311 * @request - request to write to the ring
c8c99b0f
BW		 1312 *
1313 * Update the mailbox registers in the *other* rings with the current seqno.
1314 * This acts like a signal in the canonical semaphore.
1315 */
1ec14ad3 1316static int
ee044a88 1317gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1318{
ee044a88 1319 struct intel_engine_cs *ring = req->ring;
024a43e1 1320 int ret;
52ed2325 1321
707d9cf9 1322 if (ring->semaphore.signal)
f7169687 1323 ret = ring->semaphore.signal(req, 4);
707d9cf9 1324 else
5fb9de1a 1325 ret = intel_ring_begin(req, 4);
707d9cf9 1326
1ec14ad3
CW		 1327 if (ret)
1328 return ret;
1329
1ec14ad3
CW		 1330 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1331 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1332 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1333 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1334 __intel_ring_advance(ring);
1ec14ad3 1335
1ec14ad3
CW		 1336 return 0;
1337}
1338
f72b3435
MK		 1339static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1340 u32 seqno)
1341{
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 return dev_priv->last_seqno < seqno;
1344}
1345
c8c99b0f
BW		 1346/**
1347 * intel_ring_sync - sync the waiter to the signaller on seqno
1348 *
1349 * @waiter - ring that is waiting
1350 * @signaller - ring which has, or will signal
1351 * @seqno - seqno which the waiter will block on
1352 */
5ee426ca
BW		 1353
1354static int
599d924c 1355gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1356 struct intel_engine_cs *signaller,
1357 u32 seqno)
1358{
599d924c 1359 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1360 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1361 int ret;
1362
5fb9de1a 1363 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1364 if (ret)
1365 return ret;
1366
1367 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1368 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1369 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1370 MI_SEMAPHORE_SAD_GTE_SDD);
1371 intel_ring_emit(waiter, seqno);
1372 intel_ring_emit(waiter,
1373 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1374 intel_ring_emit(waiter,
1375 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1376 intel_ring_advance(waiter);
1377 return 0;
1378}
1379
c8c99b0f 1380static int
599d924c 1381gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1382 struct intel_engine_cs *signaller,
686cb5f9 1383 u32 seqno)
1ec14ad3 1384{
599d924c 1385 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1386 u32 dw1 = MI_SEMAPHORE_MBOX |
1387 MI_SEMAPHORE_COMPARE |
1388 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1389 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1390 int ret;
1ec14ad3 1391
1500f7ea
BW		 1392 /* Throughout all of the GEM code, seqno passed implies our current
1393 * seqno is >= the last seqno executed. However for hardware the
1394 * comparison is strictly greater than.
1395 */
1396 seqno -= 1;
1397
ebc348b2 1398 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1399
5fb9de1a 1400 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1401 if (ret)
1402 return ret;
1403
f72b3435
MK		 1404 /* If seqno wrap happened, omit the wait with no-ops */
1405 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1406 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1407 intel_ring_emit(waiter, seqno);
1408 intel_ring_emit(waiter, 0);
1409 intel_ring_emit(waiter, MI_NOOP);
1410 } else {
1411 intel_ring_emit(waiter, MI_NOOP);
1412 intel_ring_emit(waiter, MI_NOOP);
1413 intel_ring_emit(waiter, MI_NOOP);
1414 intel_ring_emit(waiter, MI_NOOP);
1415 }
c8c99b0f 1416 intel_ring_advance(waiter);
1ec14ad3
CW		 1417
1418 return 0;
1419}
1420
c6df541c
CW		 1421#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1422do { \
fcbc34e4
KG		 1423 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1424 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1425 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1426 intel_ring_emit(ring__, 0); \
1427 intel_ring_emit(ring__, 0); \
1428} while (0)
1429
1430static int
ee044a88 1431pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1432{
ee044a88 1433 struct intel_engine_cs *ring = req->ring;
18393f63 1434 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1435 int ret;
1436
1437 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1438 * incoherent with writes to memory, i.e. completely fubar,
1439 * so we need to use PIPE_NOTIFY instead.
1440 *
1441 * However, we also need to workaround the qword write
1442 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1443 * memory before requesting an interrupt.
1444 */
5fb9de1a 1445 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1446 if (ret)
1447 return ret;
1448
fcbc34e4 1449 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1450 PIPE_CONTROL_WRITE_FLUSH |
1451 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1452 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1453 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1454 intel_ring_emit(ring, 0);
1455 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1456 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1457 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1458 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1459 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1460 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1461 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1462 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1463 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1464 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1465 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1466
fcbc34e4 1467 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1468 PIPE_CONTROL_WRITE_FLUSH |
1469 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1470 PIPE_CONTROL_NOTIFY);
0d1aacac 1471 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1472 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1473 intel_ring_emit(ring, 0);
09246732 1474 __intel_ring_advance(ring);
c6df541c 1475
c6df541c
CW		 1476 return 0;
1477}
1478
4cd53c0c 1479static u32
a4872ba6 1480gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1481{
4cd53c0c
DV		 1482 /* Workaround to force correct ordering between irq and seqno writes on
1483 * ivb (and maybe also on snb) by reading from a CS register (like
1484 * ACTHD) before reading the status page. */
50877445
CW		 1485 if (!lazy_coherency) {
1486 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1487 POSTING_READ(RING_ACTHD(ring->mmio_base));
1488 }
1489
4cd53c0c
DV		 1490 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1491}
1492
8187a2b7 1493static u32
a4872ba6 1494ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1495{
1ec14ad3
CW		 1496 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1497}
1498
b70ec5bf 1499static void
a4872ba6 1500ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1501{
1502 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1503}
1504
c6df541c 1505static u32
a4872ba6 1506pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1507{
0d1aacac 1508 return ring->scratch.cpu_page[0];
c6df541c
CW		 1509}
1510
b70ec5bf 1511static void
a4872ba6 1512pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1513{
0d1aacac 1514 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1515}
1516
e48d8634 1517static bool
a4872ba6 1518gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1519{
1520 struct drm_device *dev = ring->dev;
4640c4ff 1521 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1522 unsigned long flags;
e48d8634 1523
7cd512f1 1524 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1525 return false;
1526
7338aefa 1527 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1528 if (ring->irq_refcount++ == 0)
480c8033 1529 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1530 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1531
1532 return true;
1533}
1534
1535static void
a4872ba6 1536gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1537{
1538 struct drm_device *dev = ring->dev;
4640c4ff 1539 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1540 unsigned long flags;
e48d8634 1541
7338aefa 1542 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1543 if (--ring->irq_refcount == 0)
480c8033 1544 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1545 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1546}
1547
b13c2b96 1548static bool
a4872ba6 1549i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1550{
78501eac 1551 struct drm_device *dev = ring->dev;
4640c4ff 1552 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1553 unsigned long flags;
62fdfeaf 1554
7cd512f1 1555 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1556 return false;
1557
7338aefa 1558 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1559 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1560 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1561 I915_WRITE(IMR, dev_priv->irq_mask);
1562 POSTING_READ(IMR);
1563 }
7338aefa 1564 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1565
1566 return true;
62fdfeaf
EA		 1567}
1568
8187a2b7 1569static void
a4872ba6 1570i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1571{
78501eac 1572 struct drm_device *dev = ring->dev;
4640c4ff 1573 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1574 unsigned long flags;
62fdfeaf 1575
7338aefa 1576 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1577 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1578 dev_priv->irq_mask |= ring->irq_enable_mask;
1579 I915_WRITE(IMR, dev_priv->irq_mask);
1580 POSTING_READ(IMR);
1581 }
7338aefa 1582 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1583}
1584
c2798b19 1585static bool
a4872ba6 1586i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1587{
1588 struct drm_device *dev = ring->dev;
4640c4ff 1589 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1590 unsigned long flags;
c2798b19 1591
7cd512f1 1592 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1593 return false;
1594
7338aefa 1595 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1596 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1597 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1598 I915_WRITE16(IMR, dev_priv->irq_mask);
1599 POSTING_READ16(IMR);
1600 }
7338aefa 1601 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1602
1603 return true;
1604}
1605
1606static void
a4872ba6 1607i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1608{
1609 struct drm_device *dev = ring->dev;
4640c4ff 1610 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1611 unsigned long flags;
c2798b19 1612
7338aefa 1613 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1614 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1615 dev_priv->irq_mask |= ring->irq_enable_mask;
1616 I915_WRITE16(IMR, dev_priv->irq_mask);
1617 POSTING_READ16(IMR);
1618 }
7338aefa 1619 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1620}
1621
b72f3acb 1622static int
a84c3ae1 1623bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1624 u32 invalidate_domains,
1625 u32 flush_domains)
d1b851fc 1626{
a84c3ae1 1627 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1628 int ret;
1629
5fb9de1a 1630 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1631 if (ret)
1632 return ret;
1633
1634 intel_ring_emit(ring, MI_FLUSH);
1635 intel_ring_emit(ring, MI_NOOP);
1636 intel_ring_advance(ring);
1637 return 0;
d1b851fc
ZN		 1638}
1639
3cce469c 1640static int
ee044a88 1641i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1642{
ee044a88 1643 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1644 int ret;
1645
5fb9de1a 1646 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1647 if (ret)
1648 return ret;
6f392d54 1649
3cce469c
CW		 1650 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1651 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1652 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1653 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1654 __intel_ring_advance(ring);
d1b851fc 1655
3cce469c 1656 return 0;
d1b851fc
ZN		 1657}
1658
0f46832f 1659static bool
a4872ba6 1660gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1661{
1662 struct drm_device *dev = ring->dev;
4640c4ff 1663 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1664 unsigned long flags;
0f46832f 1665
7cd512f1
DV		 1666 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1667 return false;
0f46832f 1668
7338aefa 1669 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1670 if (ring->irq_refcount++ == 0) {
040d2baa 1671 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1672 I915_WRITE_IMR(ring,
1673 ~(ring->irq_enable_mask |
35a85ac6 1674 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1675 else
1676 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1677 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1678 }
7338aefa 1679 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1680
1681 return true;
1682}
1683
1684static void
a4872ba6 1685gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1686{
1687 struct drm_device *dev = ring->dev;
4640c4ff 1688 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1689 unsigned long flags;
0f46832f 1690
7338aefa 1691 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1692 if (--ring->irq_refcount == 0) {
040d2baa 1693 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1694 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1695 else
1696 I915_WRITE_IMR(ring, ~0);
480c8033 1697 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1698 }
7338aefa 1699 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1700}
1701
a19d2933 1702static bool
a4872ba6 1703hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1704{
1705 struct drm_device *dev = ring->dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 unsigned long flags;
1708
7cd512f1 1709 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1710 return false;
1711
59cdb63d 1712 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1713 if (ring->irq_refcount++ == 0) {
a19d2933 1714 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1715 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1716 }
59cdb63d 1717 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1718
1719 return true;
1720}
1721
1722static void
a4872ba6 1723hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1724{
1725 struct drm_device *dev = ring->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727 unsigned long flags;
1728
59cdb63d 1729 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1730 if (--ring->irq_refcount == 0) {
a19d2933 1731 I915_WRITE_IMR(ring, ~0);
480c8033 1732 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1733 }
59cdb63d 1734 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1735}
1736
abd58f01 1737static bool
a4872ba6 1738gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1739{
1740 struct drm_device *dev = ring->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 unsigned long flags;
1743
7cd512f1 1744 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1745 return false;
1746
1747 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1748 if (ring->irq_refcount++ == 0) {
1749 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1750 I915_WRITE_IMR(ring,
1751 ~(ring->irq_enable_mask |
1752 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1753 } else {
1754 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1755 }
1756 POSTING_READ(RING_IMR(ring->mmio_base));
1757 }
1758 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1759
1760 return true;
1761}
1762
1763static void
a4872ba6 1764gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1765{
1766 struct drm_device *dev = ring->dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 unsigned long flags;
1769
1770 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1771 if (--ring->irq_refcount == 0) {
1772 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1773 I915_WRITE_IMR(ring,
1774 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1775 } else {
1776 I915_WRITE_IMR(ring, ~0);
1777 }
1778 POSTING_READ(RING_IMR(ring->mmio_base));
1779 }
1780 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1781}
1782
d1b851fc 1783static int
53fddaf7 1784i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1785 u64 offset, u32 length,
8e004efc 1786 unsigned dispatch_flags)
d1b851fc 1787{
53fddaf7 1788 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1789 int ret;
78501eac 1790
5fb9de1a 1791 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1792 if (ret)
1793 return ret;
1794
78501eac 1795 intel_ring_emit(ring,
65f56876
CW		 1796 MI_BATCH_BUFFER_START |
1797 MI_BATCH_GTT |
8e004efc
JH		 1798 (dispatch_flags & I915_DISPATCH_SECURE ?
1799 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1800 intel_ring_emit(ring, offset);
78501eac
CW		 1801 intel_ring_advance(ring);
1802
d1b851fc
ZN		 1803 return 0;
1804}
1805
b45305fc
DV		 1806/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1807#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1808#define I830_TLB_ENTRIES (2)
1809#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1810static int
53fddaf7 1811i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1812 u64 offset, u32 len,
1813 unsigned dispatch_flags)
62fdfeaf 1814{
53fddaf7 1815 struct intel_engine_cs *ring = req->ring;
c4d69da1 1816 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1817 int ret;
62fdfeaf 1818
5fb9de1a 1819 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1820 if (ret)
1821 return ret;
62fdfeaf 1822
c4d69da1
CW		 1823 /* Evict the invalid PTE TLBs */
1824 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1825 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1826 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1827 intel_ring_emit(ring, cs_offset);
1828 intel_ring_emit(ring, 0xdeadbeef);
1829 intel_ring_emit(ring, MI_NOOP);
1830 intel_ring_advance(ring);
b45305fc 1831
8e004efc 1832 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1833 if (len > I830_BATCH_LIMIT)
1834 return -ENOSPC;
1835
5fb9de1a 1836 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1837 if (ret)
1838 return ret;
c4d69da1
CW		 1839
1840 /* Blit the batch (which has now all relocs applied) to the
1841 * stable batch scratch bo area (so that the CS never
1842 * stumbles over its tlb invalidation bug) ...
1843 */
1844 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1845 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1846 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1847 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1848 intel_ring_emit(ring, 4096);
1849 intel_ring_emit(ring, offset);
c4d69da1 1850
b45305fc 1851 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1852 intel_ring_emit(ring, MI_NOOP);
1853 intel_ring_advance(ring);
b45305fc
DV		 1854
1855 /* ... and execute it. */
c4d69da1 1856 offset = cs_offset;
b45305fc 1857 }
e1f99ce6 1858
5fb9de1a 1859 ret = intel_ring_begin(req, 4);
c4d69da1
CW		 1860 if (ret)
1861 return ret;
1862
1863 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1864 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1865 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1866 intel_ring_emit(ring, offset + len - 8);
1867 intel_ring_emit(ring, MI_NOOP);
1868 intel_ring_advance(ring);
1869
fb3256da
DV		 1870 return 0;
1871}
1872
1873static int
53fddaf7 1874i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1875 u64 offset, u32 len,
8e004efc 1876 unsigned dispatch_flags)
fb3256da 1877{
53fddaf7 1878 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1879 int ret;
1880
5fb9de1a 1881 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1882 if (ret)
1883 return ret;
1884
65f56876 1885 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1886 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1887 0 : MI_BATCH_NON_SECURE));
c4e7a414 1888 intel_ring_advance(ring);
62fdfeaf 1889
62fdfeaf
EA		 1890 return 0;
1891}
1892
a4872ba6 1893static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1894{
05394f39 1895 struct drm_i915_gem_object *obj;
62fdfeaf 1896
8187a2b7
ZN		 1897 obj = ring->status_page.obj;
1898 if (obj == NULL)
62fdfeaf 1899 return;
62fdfeaf 1900
9da3da66 1901 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1902 i915_gem_object_ggtt_unpin(obj);
05394f39 1903 drm_gem_object_unreference(&obj->base);
8187a2b7 1904 ring->status_page.obj = NULL;
62fdfeaf
EA		 1905}
1906
a4872ba6 1907static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1908{
05394f39 1909 struct drm_i915_gem_object *obj;
62fdfeaf 1910
e3efda49 1911 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1912 unsigned flags;
e3efda49 1913 int ret;
e4ffd173 1914
e3efda49
CW		 1915 obj = i915_gem_alloc_object(ring->dev, 4096);
1916 if (obj == NULL) {
1917 DRM_ERROR("Failed to allocate status page\n");
1918 return -ENOMEM;
1919 }
62fdfeaf 1920
e3efda49
CW		 1921 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1922 if (ret)
1923 goto err_unref;
1924
1f767e02
CW		 1925 flags = 0;
1926 if (!HAS_LLC(ring->dev))
1927 /* On g33, we cannot place HWS above 256MiB, so
1928 * restrict its pinning to the low mappable arena.
1929 * Though this restriction is not documented for
1930 * gen4, gen5, or byt, they also behave similarly
1931 * and hang if the HWS is placed at the top of the
1932 * GTT. To generalise, it appears that all !llc
1933 * platforms have issues with us placing the HWS
1934 * above the mappable region (even though we never
1935 * actualy map it).
1936 */
1937 flags |= PIN_MAPPABLE;
1938 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1939 if (ret) {
1940err_unref:
1941 drm_gem_object_unreference(&obj->base);
1942 return ret;
1943 }
1944
1945 ring->status_page.obj = obj;
1946 }
62fdfeaf 1947
f343c5f6 1948 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1949 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1950 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1951
8187a2b7
ZN		 1952 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1953 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1954
1955 return 0;
62fdfeaf
EA		 1956}
1957
a4872ba6 1958static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1959{
1960 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1961
1962 if (!dev_priv->status_page_dmah) {
1963 dev_priv->status_page_dmah =
1964 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1965 if (!dev_priv->status_page_dmah)
1966 return -ENOMEM;
1967 }
1968
6b8294a4
CW		 1969 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1970 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1971
1972 return 0;
1973}
1974
7ba717cf 1975void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1976{
2919d291 1977 iounmap(ringbuf->virtual_start);
7ba717cf 1978 ringbuf->virtual_start = NULL;
2919d291 1979 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1980}
1981
1982int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1983 struct intel_ringbuffer *ringbuf)
1984{
1985 struct drm_i915_private *dev_priv = to_i915(dev);
1986 struct drm_i915_gem_object *obj = ringbuf->obj;
1987 int ret;
1988
1989 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1990 if (ret)
1991 return ret;
1992
1993 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1994 if (ret) {
1995 i915_gem_object_ggtt_unpin(obj);
1996 return ret;
1997 }
1998
1999 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2000 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2001 if (ringbuf->virtual_start == NULL) {
2002 i915_gem_object_ggtt_unpin(obj);
2003 return -EINVAL;
2004 }
2005
2006 return 0;
2007}
2008
01101fa7 2009static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2010{
2919d291
OM		 2011 drm_gem_object_unreference(&ringbuf->obj->base);
2012 ringbuf->obj = NULL;
2013}
2014
01101fa7
CW		 2015static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2016 struct intel_ringbuffer *ringbuf)
62fdfeaf 2017{
05394f39 2018 struct drm_i915_gem_object *obj;
62fdfeaf 2019
ebc052e0
CW		 2020 obj = NULL;
2021 if (!HAS_LLC(dev))
93b0a4e0 2022 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2023 if (obj == NULL)
93b0a4e0 2024 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2025 if (obj == NULL)
2026 return -ENOMEM;
8187a2b7 2027
24f3a8cf
AG		 2028 /* mark ring buffers as read-only from GPU side by default */
2029 obj->gt_ro = 1;
2030
93b0a4e0 2031 ringbuf->obj = obj;
e3efda49 2032
7ba717cf 2033 return 0;
e3efda49
CW		 2034}
2035
01101fa7
CW		 2036struct intel_ringbuffer *
2037intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2038{
2039 struct intel_ringbuffer *ring;
2040 int ret;
2041
2042 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2043 if (ring == NULL)
2044 return ERR_PTR(-ENOMEM);
2045
2046 ring->ring = engine;
2047
2048 ring->size = size;
2049 /* Workaround an erratum on the i830 which causes a hang if
2050 * the TAIL pointer points to within the last 2 cachelines
2051 * of the buffer.
2052 */
2053 ring->effective_size = size;
2054 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2055 ring->effective_size -= 2 * CACHELINE_BYTES;
2056
2057 ring->last_retired_head = -1;
2058 intel_ring_update_space(ring);
2059
2060 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2061 if (ret) {
2062 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2063 engine->name, ret);
2064 kfree(ring);
2065 return ERR_PTR(ret);
2066 }
2067
2068 return ring;
2069}
2070
2071void
2072intel_ringbuffer_free(struct intel_ringbuffer *ring)
2073{
2074 intel_destroy_ringbuffer_obj(ring);
2075 kfree(ring);
2076}
2077
e3efda49 2078static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2079 struct intel_engine_cs *ring)
e3efda49 2080{
bfc882b4 2081 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2082 int ret;
2083
bfc882b4
DV		 2084 WARN_ON(ring->buffer);
2085
e3efda49
CW		 2086 ring->dev = dev;
2087 INIT_LIST_HEAD(&ring->active_list);
2088 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2089 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2090 i915_gem_batch_pool_init(dev, &ring->batch_pool);
ebc348b2 2091 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2092
2093 init_waitqueue_head(&ring->irq_queue);
2094
01101fa7
CW		 2095 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2096 if (IS_ERR(ringbuf))
2097 return PTR_ERR(ringbuf);
2098 ring->buffer = ringbuf;
2099
e3efda49
CW		 2100 if (I915_NEED_GFX_HWS(dev)) {
2101 ret = init_status_page(ring);
2102 if (ret)
8ee14975 2103 goto error;
e3efda49
CW		 2104 } else {
2105 BUG_ON(ring->id != RCS);
2106 ret = init_phys_status_page(ring);
2107 if (ret)
8ee14975 2108 goto error;
e3efda49
CW		 2109 }
2110
bfc882b4
DV		 2111 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2112 if (ret) {
2113 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2114 ring->name, ret);
2115 intel_destroy_ringbuffer_obj(ringbuf);
2116 goto error;
e3efda49 2117 }
62fdfeaf 2118
44e895a8
BV		 2119 ret = i915_cmd_parser_init_ring(ring);
2120 if (ret)
8ee14975
OM		 2121 goto error;
2122
8ee14975 2123 return 0;
351e3db2 2124
8ee14975 2125error:
01101fa7 2126 intel_ringbuffer_free(ringbuf);
8ee14975
OM		 2127 ring->buffer = NULL;
2128 return ret;
62fdfeaf
EA		 2129}
2130
a4872ba6 2131void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2132{
6402c330 2133 struct drm_i915_private *dev_priv;
33626e6a 2134
93b0a4e0 2135 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2136 return;
2137
6402c330 2138 dev_priv = to_i915(ring->dev);
6402c330 2139
e3efda49 2140 intel_stop_ring_buffer(ring);
de8f0a50 2141 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2142
01101fa7
CW		 2143 intel_unpin_ringbuffer_obj(ring->buffer);
2144 intel_ringbuffer_free(ring->buffer);
2145 ring->buffer = NULL;
78501eac 2146
8d19215b
ZN		 2147 if (ring->cleanup)
2148 ring->cleanup(ring);
2149
78501eac 2150 cleanup_status_page(ring);
44e895a8
BV		 2151
2152 i915_cmd_parser_fini_ring(ring);
06fbca71 2153 i915_gem_batch_pool_fini(&ring->batch_pool);
62fdfeaf
EA		 2154}
2155
595e1eeb 2156static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2157{
93b0a4e0 2158 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2159 struct drm_i915_gem_request *request;
b4716185
CW		 2160 unsigned space;
2161 int ret;
a71d8d94 2162
ebd0fd4b
DG		 2163 if (intel_ring_space(ringbuf) >= n)
2164 return 0;
a71d8d94 2165
79bbcc29
JH		 2166 /* The whole point of reserving space is to not wait! */
2167 WARN_ON(ringbuf->reserved_in_use);
2168
a71d8d94 2169 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2170 space = __intel_ring_space(request->postfix, ringbuf->tail,
2171 ringbuf->size);
2172 if (space >= n)
a71d8d94 2173 break;
a71d8d94
CW		 2174 }
2175
595e1eeb 2176 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2177 return -ENOSPC;
2178
a4b3a571 2179 ret = i915_wait_request(request);
a71d8d94
CW		 2180 if (ret)
2181 return ret;
2182
b4716185 2183 ringbuf->space = space;
a71d8d94
CW		 2184 return 0;
2185}
2186
79bbcc29 2187static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
3e960501
CW		 2188{
2189 uint32_t __iomem *virt;
93b0a4e0 2190 int rem = ringbuf->size - ringbuf->tail;
3e960501 2191
93b0a4e0 2192 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2193 rem /= 4;
2194 while (rem--)
2195 iowrite32(MI_NOOP, virt++);
2196
93b0a4e0 2197 ringbuf->tail = 0;
ebd0fd4b 2198 intel_ring_update_space(ringbuf);
3e960501
CW		 2199}
2200
a4872ba6 2201int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2202{
a4b3a571 2203 struct drm_i915_gem_request *req;
3e960501 2204
3e960501
CW		 2205 /* Wait upon the last request to be completed */
2206 if (list_empty(&ring->request_list))
2207 return 0;
2208
a4b3a571 2209 req = list_entry(ring->request_list.prev,
b4716185
CW		 2210 struct drm_i915_gem_request,
2211 list);
2212
2213 /* Make sure we do not trigger any retires */
2214 return __i915_wait_request(req,
2215 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2216 to_i915(ring->dev)->mm.interruptible,
2217 NULL, NULL);
3e960501
CW		 2218}
2219
6689cb2b 2220int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2221{
6689cb2b 2222 request->ringbuf = request->ring->buffer;
9eba5d4a 2223 return 0;
9d773091
CW		 2224}
2225
ccd98fe4
JH		 2226int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2227{
2228 /*
2229 * The first call merely notes the reserve request and is common for
2230 * all back ends. The subsequent localised _begin() call actually
2231 * ensures that the reservation is available. Without the begin, if
2232 * the request creator immediately submitted the request without
2233 * adding any commands to it then there might not actually be
2234 * sufficient room for the submission commands.
2235 */
2236 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2237
2238 return intel_ring_begin(request, 0);
2239}
2240
29b1b415
JH		 2241void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2242{
ccd98fe4 2243 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2244 WARN_ON(ringbuf->reserved_in_use);
2245
2246 ringbuf->reserved_size = size;
29b1b415
JH		 2247}
2248
2249void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2250{
2251 WARN_ON(ringbuf->reserved_in_use);
2252
2253 ringbuf->reserved_size = 0;
2254 ringbuf->reserved_in_use = false;
2255}
2256
2257void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2258{
2259 WARN_ON(ringbuf->reserved_in_use);
2260
2261 ringbuf->reserved_in_use = true;
2262 ringbuf->reserved_tail = ringbuf->tail;
2263}
2264
2265void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2266{
2267 WARN_ON(!ringbuf->reserved_in_use);
79bbcc29
JH		 2268 if (ringbuf->tail > ringbuf->reserved_tail) {
2269 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2270 "request reserved size too small: %d vs %d!\n",
2271 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2272 } else {
2273 /*
2274 * The ring was wrapped while the reserved space was in use.
2275 * That means that some unknown amount of the ring tail was
2276 * no-op filled and skipped. Thus simply adding the ring size
2277 * to the tail and doing the above space check will not work.
2278 * Rather than attempt to track how much tail was skipped,
2279 * it is much simpler to say that also skipping the sanity
2280 * check every once in a while is not a big issue.
2281 */
2282 }
29b1b415
JH		 2283
2284 ringbuf->reserved_size = 0;
2285 ringbuf->reserved_in_use = false;
2286}
2287
2288static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2289{
93b0a4e0 2290 struct intel_ringbuffer *ringbuf = ring->buffer;
79bbcc29
JH		 2291 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2292 int remain_actual = ringbuf->size - ringbuf->tail;
2293 int ret, total_bytes, wait_bytes = 0;
2294 bool need_wrap = false;
29b1b415 2295
79bbcc29
JH		 2296 if (ringbuf->reserved_in_use)
2297 total_bytes = bytes;
2298 else
2299 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2300
79bbcc29
JH		 2301 if (unlikely(bytes > remain_usable)) {
2302 /*
2303 * Not enough space for the basic request. So need to flush
2304 * out the remainder and then wait for base + reserved.
2305 */
2306 wait_bytes = remain_actual + total_bytes;
2307 need_wrap = true;
2308 } else {
2309 if (unlikely(total_bytes > remain_usable)) {
2310 /*
2311 * The base request will fit but the reserved space
2312 * falls off the end. So only need to to wait for the
2313 * reserved size after flushing out the remainder.
2314 */
2315 wait_bytes = remain_actual + ringbuf->reserved_size;
2316 need_wrap = true;
2317 } else if (total_bytes > ringbuf->space) {
2318 /* No wrapping required, just waiting. */
2319 wait_bytes = total_bytes;
29b1b415 2320 }
cbcc80df
MK		 2321 }
2322
79bbcc29
JH		 2323 if (wait_bytes) {
2324 ret = ring_wait_for_space(ring, wait_bytes);
cbcc80df
MK		 2325 if (unlikely(ret))
2326 return ret;
79bbcc29
JH		 2327
2328 if (need_wrap)
2329 __wrap_ring_buffer(ringbuf);
cbcc80df
MK		 2330 }
2331
cbcc80df
MK		 2332 return 0;
2333}
2334
5fb9de1a 2335int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2336 int num_dwords)
8187a2b7 2337{
5fb9de1a
JH		 2338 struct intel_engine_cs *ring;
2339 struct drm_i915_private *dev_priv;
e1f99ce6 2340 int ret;
78501eac 2341
5fb9de1a
JH		 2342 WARN_ON(req == NULL);
2343 ring = req->ring;
2344 dev_priv = ring->dev->dev_private;
2345
33196ded
DV		 2346 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2347 dev_priv->mm.interruptible);
de2b9985
DV		 2348 if (ret)
2349 return ret;
21dd3734 2350
304d695c
CW		 2351 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2352 if (ret)
2353 return ret;
2354
ee1b1e5e 2355 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2356 return 0;
8187a2b7 2357}
78501eac 2358
753b1ad4 2359/* Align the ring tail to a cacheline boundary */
bba09b12 2360int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2361{
bba09b12 2362 struct intel_engine_cs *ring = req->ring;
ee1b1e5e 2363 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2364 int ret;
2365
2366 if (num_dwords == 0)
2367 return 0;
2368
18393f63 2369 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2370 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2371 if (ret)
2372 return ret;
2373
2374 while (num_dwords--)
2375 intel_ring_emit(ring, MI_NOOP);
2376
2377 intel_ring_advance(ring);
2378
2379 return 0;
2380}
2381
a4872ba6 2382void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2383{
3b2cc8ab
OM		 2384 struct drm_device *dev = ring->dev;
2385 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2386
3b2cc8ab 2387 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2388 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2389 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2390 if (HAS_VEBOX(dev))
5020150b 2391 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2392 }
d97ed339 2393
f7e98ad4 2394 ring->set_seqno(ring, seqno);
92cab734 2395 ring->hangcheck.seqno = seqno;
8187a2b7 2396}
62fdfeaf 2397
a4872ba6 2398static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2399 u32 value)
881f47b6 2400{
4640c4ff 2401 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2402
2403 /* Every tail move must follow the sequence below */
12f55818
CW		 2404
2405 /* Disable notification that the ring is IDLE. The GT
2406 * will then assume that it is busy and bring it out of rc6.
2407 */
0206e353 2408 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2409 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2410
2411 /* Clear the context id. Here be magic! */
2412 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2413
12f55818 2414 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2415 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2416 GEN6_BSD_SLEEP_INDICATOR) == 0,
2417 50))
2418 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2419
12f55818 2420 /* Now that the ring is fully powered up, update the tail */
0206e353 2421 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2422 POSTING_READ(RING_TAIL(ring->mmio_base));
2423
2424 /* Let the ring send IDLE messages to the GT again,
2425 * and so let it sleep to conserve power when idle.
2426 */
0206e353 2427 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2428 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2429}
2430
a84c3ae1 2431static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2432 u32 invalidate, u32 flush)
881f47b6 2433{
a84c3ae1 2434 struct intel_engine_cs *ring = req->ring;
71a77e07 2435 uint32_t cmd;
b72f3acb
CW		 2436 int ret;
2437
5fb9de1a 2438 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2439 if (ret)
2440 return ret;
2441
71a77e07 2442 cmd = MI_FLUSH_DW;
075b3bba
BW		 2443 if (INTEL_INFO(ring->dev)->gen >= 8)
2444 cmd += 1;
f0a1fb10
CW		 2445
2446 /* We always require a command barrier so that subsequent
2447 * commands, such as breadcrumb interrupts, are strictly ordered
2448 * wrt the contents of the write cache being flushed to memory
2449 * (and thus being coherent from the CPU).
2450 */
2451 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2452
9a289771
JB		 2453 /*
2454 * Bspec vol 1c.5 - video engine command streamer:
2455 * "If ENABLED, all TLBs will be invalidated once the flush
2456 * operation is complete. This bit is only valid when the
2457 * Post-Sync Operation field is a value of 1h or 3h."
2458 */
71a77e07 2459 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2460 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2461
71a77e07 2462 intel_ring_emit(ring, cmd);
9a289771 2463 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2464 if (INTEL_INFO(ring->dev)->gen >= 8) {
2465 intel_ring_emit(ring, 0); /* upper addr */
2466 intel_ring_emit(ring, 0); /* value */
2467 } else {
2468 intel_ring_emit(ring, 0);
2469 intel_ring_emit(ring, MI_NOOP);
2470 }
b72f3acb
CW		 2471 intel_ring_advance(ring);
2472 return 0;
881f47b6
XH		 2473}
2474
1c7a0623 2475static int
53fddaf7 2476gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2477 u64 offset, u32 len,
8e004efc 2478 unsigned dispatch_flags)
1c7a0623 2479{
53fddaf7 2480 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2481 bool ppgtt = USES_PPGTT(ring->dev) &&
2482 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2483 int ret;
2484
5fb9de1a 2485 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2486 if (ret)
2487 return ret;
2488
2489 /* FIXME(BDW): Address space and security selectors. */
919032ec
AJ		 2490 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2491 (dispatch_flags & I915_DISPATCH_RS ?
2492 MI_BATCH_RESOURCE_STREAMER : 0));
9bcb144c
BW		 2493 intel_ring_emit(ring, lower_32_bits(offset));
2494 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2495 intel_ring_emit(ring, MI_NOOP);
2496 intel_ring_advance(ring);
2497
2498 return 0;
2499}
2500
d7d4eedd 2501static int
53fddaf7 2502hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2503 u64 offset, u32 len,
2504 unsigned dispatch_flags)
d7d4eedd 2505{
53fddaf7 2506 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2507 int ret;
2508
5fb9de1a 2509 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2510 if (ret)
2511 return ret;
2512
2513 intel_ring_emit(ring,
77072258 2514 MI_BATCH_BUFFER_START |
8e004efc 2515 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2516 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2517 (dispatch_flags & I915_DISPATCH_RS ?
2518 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd
CW		 2519 /* bit0-7 is the length on GEN6+ */
2520 intel_ring_emit(ring, offset);
2521 intel_ring_advance(ring);
2522
2523 return 0;
2524}
2525
881f47b6 2526static int
53fddaf7 2527gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2528 u64 offset, u32 len,
8e004efc 2529 unsigned dispatch_flags)
881f47b6 2530{
53fddaf7 2531 struct intel_engine_cs *ring = req->ring;
0206e353 2532 int ret;
ab6f8e32 2533
5fb9de1a 2534 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2535 if (ret)
2536 return ret;
e1f99ce6 2537
d7d4eedd
CW		 2538 intel_ring_emit(ring,
2539 MI_BATCH_BUFFER_START |
8e004efc
JH		 2540 (dispatch_flags & I915_DISPATCH_SECURE ?
2541 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2542 /* bit0-7 is the length on GEN6+ */
2543 intel_ring_emit(ring, offset);
2544 intel_ring_advance(ring);
ab6f8e32 2545
0206e353 2546 return 0;
881f47b6
XH		 2547}
2548
549f7365
CW		 2549/* Blitter support (SandyBridge+) */
2550
a84c3ae1 2551static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2552 u32 invalidate, u32 flush)
8d19215b 2553{
a84c3ae1 2554 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2555 struct drm_device *dev = ring->dev;
71a77e07 2556 uint32_t cmd;
b72f3acb
CW		 2557 int ret;
2558
5fb9de1a 2559 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2560 if (ret)
2561 return ret;
2562
71a77e07 2563 cmd = MI_FLUSH_DW;
dbef0f15 2564 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2565 cmd += 1;
f0a1fb10
CW		 2566
2567 /* We always require a command barrier so that subsequent
2568 * commands, such as breadcrumb interrupts, are strictly ordered
2569 * wrt the contents of the write cache being flushed to memory
2570 * (and thus being coherent from the CPU).
2571 */
2572 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2573
9a289771
JB		 2574 /*
2575 * Bspec vol 1c.3 - blitter engine command streamer:
2576 * "If ENABLED, all TLBs will be invalidated once the flush
2577 * operation is complete. This bit is only valid when the
2578 * Post-Sync Operation field is a value of 1h or 3h."
2579 */
71a77e07 2580 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2581 cmd |= MI_INVALIDATE_TLB;
71a77e07 2582 intel_ring_emit(ring, cmd);
9a289771 2583 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2584 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2585 intel_ring_emit(ring, 0); /* upper addr */
2586 intel_ring_emit(ring, 0); /* value */
2587 } else {
2588 intel_ring_emit(ring, 0);
2589 intel_ring_emit(ring, MI_NOOP);
2590 }
b72f3acb 2591 intel_ring_advance(ring);
fd3da6c9 2592
b72f3acb 2593 return 0;
8d19215b
ZN		 2594}
2595
5c1143bb
XH		 2596int intel_init_render_ring_buffer(struct drm_device *dev)
2597{
4640c4ff 2598 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2599 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2600 struct drm_i915_gem_object *obj;
2601 int ret;
5c1143bb 2602
59465b5f
DV		 2603 ring->name = "render ring";
2604 ring->id = RCS;
2605 ring->mmio_base = RENDER_RING_BASE;
2606
707d9cf9 2607 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2608 if (i915_semaphore_is_enabled(dev)) {
2609 obj = i915_gem_alloc_object(dev, 4096);
2610 if (obj == NULL) {
2611 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2612 i915.semaphores = 0;
2613 } else {
2614 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2615 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2616 if (ret != 0) {
2617 drm_gem_object_unreference(&obj->base);
2618 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2619 i915.semaphores = 0;
2620 } else
2621 dev_priv->semaphore_obj = obj;
2622 }
2623 }
7225342a 2624
8f0e2b9d 2625 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2626 ring->add_request = gen6_add_request;
2627 ring->flush = gen8_render_ring_flush;
2628 ring->irq_get = gen8_ring_get_irq;
2629 ring->irq_put = gen8_ring_put_irq;
2630 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2631 ring->get_seqno = gen6_ring_get_seqno;
2632 ring->set_seqno = ring_set_seqno;
2633 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2634 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2635 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2636 ring->semaphore.signal = gen8_rcs_signal;
2637 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2638 }
2639 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2640 ring->add_request = gen6_add_request;
4772eaeb 2641 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2642 if (INTEL_INFO(dev)->gen == 6)
b3111509 2643 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2644 ring->irq_get = gen6_ring_get_irq;
2645 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2646 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2647 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2648 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2649 if (i915_semaphore_is_enabled(dev)) {
2650 ring->semaphore.sync_to = gen6_ring_sync;
2651 ring->semaphore.signal = gen6_signal;
2652 /*
2653 * The current semaphore is only applied on pre-gen8
2654 * platform. And there is no VCS2 ring on the pre-gen8
2655 * platform. So the semaphore between RCS and VCS2 is
2656 * initialized as INVALID. Gen8 will initialize the
2657 * sema between VCS2 and RCS later.
2658 */
2659 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2660 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2661 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2662 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2663 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2664 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2665 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2666 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2667 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2668 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2669 }
c6df541c
CW		 2670 } else if (IS_GEN5(dev)) {
2671 ring->add_request = pc_render_add_request;
46f0f8d1 2672 ring->flush = gen4_render_ring_flush;
c6df541c 2673 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2674 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2675 ring->irq_get = gen5_ring_get_irq;
2676 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2677 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2678 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2679 } else {
8620a3a9 2680 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2681 if (INTEL_INFO(dev)->gen < 4)
2682 ring->flush = gen2_render_ring_flush;
2683 else
2684 ring->flush = gen4_render_ring_flush;
59465b5f 2685 ring->get_seqno = ring_get_seqno;
b70ec5bf 2686 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2687 if (IS_GEN2(dev)) {
2688 ring->irq_get = i8xx_ring_get_irq;
2689 ring->irq_put = i8xx_ring_put_irq;
2690 } else {
2691 ring->irq_get = i9xx_ring_get_irq;
2692 ring->irq_put = i9xx_ring_put_irq;
2693 }
e3670319 2694 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2695 }
59465b5f 2696 ring->write_tail = ring_write_tail;
707d9cf9 2697
d7d4eedd
CW		 2698 if (IS_HASWELL(dev))
2699 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2700 else if (IS_GEN8(dev))
2701 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2702 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2703 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2704 else if (INTEL_INFO(dev)->gen >= 4)
2705 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2706 else if (IS_I830(dev) || IS_845G(dev))
2707 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2708 else
2709 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2710 ring->init_hw = init_render_ring;
59465b5f
DV		 2711 ring->cleanup = render_ring_cleanup;
2712
b45305fc
DV		 2713 /* Workaround batchbuffer to combat CS tlb bug. */
2714 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2715 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2716 if (obj == NULL) {
2717 DRM_ERROR("Failed to allocate batch bo\n");
2718 return -ENOMEM;
2719 }
2720
be1fa129 2721 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2722 if (ret != 0) {
2723 drm_gem_object_unreference(&obj->base);
2724 DRM_ERROR("Failed to ping batch bo\n");
2725 return ret;
2726 }
2727
0d1aacac
CW		 2728 ring->scratch.obj = obj;
2729 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2730 }
2731
99be1dfe
DV		 2732 ret = intel_init_ring_buffer(dev, ring);
2733 if (ret)
2734 return ret;
2735
2736 if (INTEL_INFO(dev)->gen >= 5) {
2737 ret = intel_init_pipe_control(ring);
2738 if (ret)
2739 return ret;
2740 }
2741
2742 return 0;
5c1143bb
XH		 2743}
2744
2745int intel_init_bsd_ring_buffer(struct drm_device *dev)
2746{
4640c4ff 2747 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2748 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2749
58fa3835
DV		 2750 ring->name = "bsd ring";
2751 ring->id = VCS;
2752
0fd2c201 2753 ring->write_tail = ring_write_tail;
780f18c8 2754 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2755 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2756 /* gen6 bsd needs a special wa for tail updates */
2757 if (IS_GEN6(dev))
2758 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2759 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2760 ring->add_request = gen6_add_request;
2761 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2762 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2763 if (INTEL_INFO(dev)->gen >= 8) {
2764 ring->irq_enable_mask =
2765 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2766 ring->irq_get = gen8_ring_get_irq;
2767 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2768 ring->dispatch_execbuffer =
2769 gen8_ring_dispatch_execbuffer;
707d9cf9 2770 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2771 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2772 ring->semaphore.signal = gen8_xcs_signal;
2773 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2774 }
abd58f01
BW		 2775 } else {
2776 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2777 ring->irq_get = gen6_ring_get_irq;
2778 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2779 ring->dispatch_execbuffer =
2780 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2781 if (i915_semaphore_is_enabled(dev)) {
2782 ring->semaphore.sync_to = gen6_ring_sync;
2783 ring->semaphore.signal = gen6_signal;
2784 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2785 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2786 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2787 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2788 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2789 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2790 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2791 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2792 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2793 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2794 }
abd58f01 2795 }
58fa3835
DV		 2796 } else {
2797 ring->mmio_base = BSD_RING_BASE;
58fa3835 2798 ring->flush = bsd_ring_flush;
8620a3a9 2799 ring->add_request = i9xx_add_request;
58fa3835 2800 ring->get_seqno = ring_get_seqno;
b70ec5bf 2801 ring->set_seqno = ring_set_seqno;
e48d8634 2802 if (IS_GEN5(dev)) {
cc609d5d 2803 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2804 ring->irq_get = gen5_ring_get_irq;
2805 ring->irq_put = gen5_ring_put_irq;
2806 } else {
e3670319 2807 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2808 ring->irq_get = i9xx_ring_get_irq;
2809 ring->irq_put = i9xx_ring_put_irq;
2810 }
fb3256da 2811 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2812 }
ecfe00d8 2813 ring->init_hw = init_ring_common;
58fa3835 2814
1ec14ad3 2815 return intel_init_ring_buffer(dev, ring);
5c1143bb 2816}
549f7365 2817
845f74a7 2818/**
62659920 2819 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2820 */
2821int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2822{
2823 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2824 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2825
f7b64236 2826 ring->name = "bsd2 ring";
845f74a7
ZY		 2827 ring->id = VCS2;
2828
2829 ring->write_tail = ring_write_tail;
2830 ring->mmio_base = GEN8_BSD2_RING_BASE;
2831 ring->flush = gen6_bsd_ring_flush;
2832 ring->add_request = gen6_add_request;
2833 ring->get_seqno = gen6_ring_get_seqno;
2834 ring->set_seqno = ring_set_seqno;
2835 ring->irq_enable_mask =
2836 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2837 ring->irq_get = gen8_ring_get_irq;
2838 ring->irq_put = gen8_ring_put_irq;
2839 ring->dispatch_execbuffer =
2840 gen8_ring_dispatch_execbuffer;
3e78998a 2841 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2842 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2843 ring->semaphore.signal = gen8_xcs_signal;
2844 GEN8_RING_SEMAPHORE_INIT;
2845 }
ecfe00d8 2846 ring->init_hw = init_ring_common;
845f74a7
ZY		 2847
2848 return intel_init_ring_buffer(dev, ring);
2849}
2850
549f7365
CW		 2851int intel_init_blt_ring_buffer(struct drm_device *dev)
2852{
4640c4ff 2853 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2854 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2855
3535d9dd
DV		 2856 ring->name = "blitter ring";
2857 ring->id = BCS;
2858
2859 ring->mmio_base = BLT_RING_BASE;
2860 ring->write_tail = ring_write_tail;
ea251324 2861 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2862 ring->add_request = gen6_add_request;
2863 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2864 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2865 if (INTEL_INFO(dev)->gen >= 8) {
2866 ring->irq_enable_mask =
2867 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2868 ring->irq_get = gen8_ring_get_irq;
2869 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2870 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2871 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2872 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2873 ring->semaphore.signal = gen8_xcs_signal;
2874 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2875 }
abd58f01
BW		 2876 } else {
2877 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2878 ring->irq_get = gen6_ring_get_irq;
2879 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2880 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2881 if (i915_semaphore_is_enabled(dev)) {
2882 ring->semaphore.signal = gen6_signal;
2883 ring->semaphore.sync_to = gen6_ring_sync;
2884 /*
2885 * The current semaphore is only applied on pre-gen8
2886 * platform. And there is no VCS2 ring on the pre-gen8
2887 * platform. So the semaphore between BCS and VCS2 is
2888 * initialized as INVALID. Gen8 will initialize the
2889 * sema between BCS and VCS2 later.
2890 */
2891 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2892 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2893 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2894 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2895 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2896 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2897 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2898 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2899 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2900 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2901 }
abd58f01 2902 }
ecfe00d8 2903 ring->init_hw = init_ring_common;
549f7365 2904
1ec14ad3 2905 return intel_init_ring_buffer(dev, ring);
549f7365 2906}
a7b9761d 2907
9a8a2213
BW		 2908int intel_init_vebox_ring_buffer(struct drm_device *dev)
2909{
4640c4ff 2910 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2911 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2912
2913 ring->name = "video enhancement ring";
2914 ring->id = VECS;
2915
2916 ring->mmio_base = VEBOX_RING_BASE;
2917 ring->write_tail = ring_write_tail;
2918 ring->flush = gen6_ring_flush;
2919 ring->add_request = gen6_add_request;
2920 ring->get_seqno = gen6_ring_get_seqno;
2921 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2922
2923 if (INTEL_INFO(dev)->gen >= 8) {
2924 ring->irq_enable_mask =
40c499f9 2925 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2926 ring->irq_get = gen8_ring_get_irq;
2927 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2928 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2929 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2930 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2931 ring->semaphore.signal = gen8_xcs_signal;
2932 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2933 }
abd58f01
BW		 2934 } else {
2935 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2936 ring->irq_get = hsw_vebox_get_irq;
2937 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2938 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2939 if (i915_semaphore_is_enabled(dev)) {
2940 ring->semaphore.sync_to = gen6_ring_sync;
2941 ring->semaphore.signal = gen6_signal;
2942 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2943 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2944 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2945 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2946 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2947 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2948 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2949 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2950 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2951 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2952 }
abd58f01 2953 }
ecfe00d8 2954 ring->init_hw = init_ring_common;
9a8a2213
BW		 2955
2956 return intel_init_ring_buffer(dev, ring);
2957}
2958
a7b9761d 2959int
4866d729 2960intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2961{
4866d729 2962 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2963 int ret;
2964
2965 if (!ring->gpu_caches_dirty)
2966 return 0;
2967
a84c3ae1 2968 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2969 if (ret)
2970 return ret;
2971
a84c3ae1 2972 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2973
2974 ring->gpu_caches_dirty = false;
2975 return 0;
2976}
2977
2978int
2f20055d 2979intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2980{
2f20055d 2981 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2982 uint32_t flush_domains;
2983 int ret;
2984
2985 flush_domains = 0;
2986 if (ring->gpu_caches_dirty)
2987 flush_domains = I915_GEM_GPU_DOMAINS;
2988
a84c3ae1 2989 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2990 if (ret)
2991 return ret;
2992
a84c3ae1 2993 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2994
2995 ring->gpu_caches_dirty = false;
2996 return 0;
2997}
e3efda49
CW		 2998
2999void
a4872ba6 3000intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 3001{
3002 int ret;
3003
3004 if (!intel_ring_initialized(ring))
3005 return;
3006
3007 ret = intel_ring_idle(ring);
3008 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3009 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3010 ring->name, ret);
3011
3012 stop_ring(ring);
3013}
Linux kernel - Deliverables
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