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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
82e104cc | 37 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 38 | { |
4f54741e DG |
39 | int space = head - tail; |
40 | if (space <= 0) | |
1cf0ba14 | 41 | space += size; |
4f54741e | 42 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
43 | } |
44 | ||
ebd0fd4b DG |
45 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
46 | { | |
47 | if (ringbuf->last_retired_head != -1) { | |
48 | ringbuf->head = ringbuf->last_retired_head; | |
49 | ringbuf->last_retired_head = -1; | |
50 | } | |
51 | ||
52 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
53 | ringbuf->tail, ringbuf->size); | |
54 | } | |
55 | ||
82e104cc | 56 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 57 | { |
ebd0fd4b DG |
58 | intel_ring_update_space(ringbuf); |
59 | return ringbuf->space; | |
1cf0ba14 CW |
60 | } |
61 | ||
117897f4 | 62 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 63 | { |
0bc40be8 | 64 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
666796da | 65 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 66 | } |
09246732 | 67 | |
0bc40be8 | 68 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 69 | { |
0bc40be8 | 70 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 71 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 72 | if (intel_engine_stopped(engine)) |
09246732 | 73 | return; |
0bc40be8 | 74 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
75 | } |
76 | ||
b72f3acb | 77 | static int |
a84c3ae1 | 78 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
79 | u32 invalidate_domains, |
80 | u32 flush_domains) | |
81 | { | |
4a570db5 | 82 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
83 | u32 cmd; |
84 | int ret; | |
85 | ||
86 | cmd = MI_FLUSH; | |
31b14c9f | 87 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
88 | cmd |= MI_NO_WRITE_FLUSH; |
89 | ||
90 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
91 | cmd |= MI_READ_FLUSH; | |
92 | ||
5fb9de1a | 93 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
94 | if (ret) |
95 | return ret; | |
96 | ||
e2f80391 TU |
97 | intel_ring_emit(engine, cmd); |
98 | intel_ring_emit(engine, MI_NOOP); | |
99 | intel_ring_advance(engine); | |
46f0f8d1 CW |
100 | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static int | |
a84c3ae1 | 105 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
106 | u32 invalidate_domains, |
107 | u32 flush_domains) | |
62fdfeaf | 108 | { |
4a570db5 | 109 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 110 | struct drm_device *dev = engine->dev; |
6f392d54 | 111 | u32 cmd; |
b72f3acb | 112 | int ret; |
6f392d54 | 113 | |
36d527de CW |
114 | /* |
115 | * read/write caches: | |
116 | * | |
117 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
118 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
119 | * also flushed at 2d versus 3d pipeline switches. | |
120 | * | |
121 | * read-only caches: | |
122 | * | |
123 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
124 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
125 | * | |
126 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
127 | * | |
128 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
129 | * invalidated when MI_EXE_FLUSH is set. | |
130 | * | |
131 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
132 | * invalidated with every MI_FLUSH. | |
133 | * | |
134 | * TLBs: | |
135 | * | |
136 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
137 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
138 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
139 | * are flushed at any MI_FLUSH. | |
140 | */ | |
141 | ||
142 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 143 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 144 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
145 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
146 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 147 | |
36d527de CW |
148 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
149 | (IS_G4X(dev) || IS_GEN5(dev))) | |
150 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 151 | |
5fb9de1a | 152 | ret = intel_ring_begin(req, 2); |
36d527de CW |
153 | if (ret) |
154 | return ret; | |
b72f3acb | 155 | |
e2f80391 TU |
156 | intel_ring_emit(engine, cmd); |
157 | intel_ring_emit(engine, MI_NOOP); | |
158 | intel_ring_advance(engine); | |
b72f3acb CW |
159 | |
160 | return 0; | |
8187a2b7 ZN |
161 | } |
162 | ||
8d315287 JB |
163 | /** |
164 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
165 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
166 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
167 | * | |
168 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
169 | * produced by non-pipelined state commands), software needs to first | |
170 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
171 | * 0. | |
172 | * | |
173 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
174 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
175 | * | |
176 | * And the workaround for these two requires this workaround first: | |
177 | * | |
178 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
179 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
180 | * flushes. | |
181 | * | |
182 | * And this last workaround is tricky because of the requirements on | |
183 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
184 | * volume 2 part 1: | |
185 | * | |
186 | * "1 of the following must also be set: | |
187 | * - Render Target Cache Flush Enable ([12] of DW1) | |
188 | * - Depth Cache Flush Enable ([0] of DW1) | |
189 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
190 | * - Depth Stall ([13] of DW1) | |
191 | * - Post-Sync Operation ([13] of DW1) | |
192 | * - Notify Enable ([8] of DW1)" | |
193 | * | |
194 | * The cache flushes require the workaround flush that triggered this | |
195 | * one, so we can't use it. Depth stall would trigger the same. | |
196 | * Post-sync nonzero is what triggered this second workaround, so we | |
197 | * can't use that one either. Notify enable is IRQs, which aren't | |
198 | * really our business. That leaves only stall at scoreboard. | |
199 | */ | |
200 | static int | |
f2cf1fcc | 201 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 202 | { |
4a570db5 | 203 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 204 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
205 | int ret; |
206 | ||
5fb9de1a | 207 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
208 | if (ret) |
209 | return ret; | |
210 | ||
e2f80391 TU |
211 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
212 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 213 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
214 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
215 | intel_ring_emit(engine, 0); /* low dword */ | |
216 | intel_ring_emit(engine, 0); /* high dword */ | |
217 | intel_ring_emit(engine, MI_NOOP); | |
218 | intel_ring_advance(engine); | |
8d315287 | 219 | |
5fb9de1a | 220 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
221 | if (ret) |
222 | return ret; | |
223 | ||
e2f80391 TU |
224 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
225 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
226 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
227 | intel_ring_emit(engine, 0); | |
228 | intel_ring_emit(engine, 0); | |
229 | intel_ring_emit(engine, MI_NOOP); | |
230 | intel_ring_advance(engine); | |
8d315287 JB |
231 | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static int | |
a84c3ae1 JH |
236 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
237 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 238 | { |
4a570db5 | 239 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 240 | u32 flags = 0; |
e2f80391 | 241 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
242 | int ret; |
243 | ||
b3111509 | 244 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 245 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
246 | if (ret) |
247 | return ret; | |
248 | ||
8d315287 JB |
249 | /* Just flush everything. Experiments have shown that reducing the |
250 | * number of bits based on the write domains has little performance | |
251 | * impact. | |
252 | */ | |
7d54a904 CW |
253 | if (flush_domains) { |
254 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
255 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
256 | /* | |
257 | * Ensure that any following seqno writes only happen | |
258 | * when the render cache is indeed flushed. | |
259 | */ | |
97f209bc | 260 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
261 | } |
262 | if (invalidate_domains) { | |
263 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
264 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
265 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
266 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
267 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
268 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
269 | /* | |
270 | * TLB invalidate requires a post-sync write. | |
271 | */ | |
3ac78313 | 272 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 273 | } |
8d315287 | 274 | |
5fb9de1a | 275 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
276 | if (ret) |
277 | return ret; | |
278 | ||
e2f80391 TU |
279 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
280 | intel_ring_emit(engine, flags); | |
281 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
282 | intel_ring_emit(engine, 0); | |
283 | intel_ring_advance(engine); | |
8d315287 JB |
284 | |
285 | return 0; | |
286 | } | |
287 | ||
f3987631 | 288 | static int |
f2cf1fcc | 289 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 290 | { |
4a570db5 | 291 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
292 | int ret; |
293 | ||
5fb9de1a | 294 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
295 | if (ret) |
296 | return ret; | |
297 | ||
e2f80391 TU |
298 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
299 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 300 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
301 | intel_ring_emit(engine, 0); |
302 | intel_ring_emit(engine, 0); | |
303 | intel_ring_advance(engine); | |
f3987631 PZ |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
4772eaeb | 308 | static int |
a84c3ae1 | 309 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
310 | u32 invalidate_domains, u32 flush_domains) |
311 | { | |
4a570db5 | 312 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 313 | u32 flags = 0; |
e2f80391 | 314 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
315 | int ret; |
316 | ||
f3987631 PZ |
317 | /* |
318 | * Ensure that any following seqno writes only happen when the render | |
319 | * cache is indeed flushed. | |
320 | * | |
321 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
322 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
323 | * don't try to be clever and just set it unconditionally. | |
324 | */ | |
325 | flags |= PIPE_CONTROL_CS_STALL; | |
326 | ||
4772eaeb PZ |
327 | /* Just flush everything. Experiments have shown that reducing the |
328 | * number of bits based on the write domains has little performance | |
329 | * impact. | |
330 | */ | |
331 | if (flush_domains) { | |
332 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
333 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 334 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 335 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
336 | } |
337 | if (invalidate_domains) { | |
338 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
339 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
340 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
341 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
342 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
343 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 344 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
345 | /* |
346 | * TLB invalidate requires a post-sync write. | |
347 | */ | |
348 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 349 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 350 | |
add284a3 CW |
351 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
352 | ||
f3987631 PZ |
353 | /* Workaround: we must issue a pipe_control with CS-stall bit |
354 | * set before a pipe_control command that has the state cache | |
355 | * invalidate bit set. */ | |
f2cf1fcc | 356 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
357 | } |
358 | ||
5fb9de1a | 359 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
360 | if (ret) |
361 | return ret; | |
362 | ||
e2f80391 TU |
363 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
364 | intel_ring_emit(engine, flags); | |
365 | intel_ring_emit(engine, scratch_addr); | |
366 | intel_ring_emit(engine, 0); | |
367 | intel_ring_advance(engine); | |
4772eaeb PZ |
368 | |
369 | return 0; | |
370 | } | |
371 | ||
884ceace | 372 | static int |
f2cf1fcc | 373 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
374 | u32 flags, u32 scratch_addr) |
375 | { | |
4a570db5 | 376 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
377 | int ret; |
378 | ||
5fb9de1a | 379 | ret = intel_ring_begin(req, 6); |
884ceace KG |
380 | if (ret) |
381 | return ret; | |
382 | ||
e2f80391 TU |
383 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
384 | intel_ring_emit(engine, flags); | |
385 | intel_ring_emit(engine, scratch_addr); | |
386 | intel_ring_emit(engine, 0); | |
387 | intel_ring_emit(engine, 0); | |
388 | intel_ring_emit(engine, 0); | |
389 | intel_ring_advance(engine); | |
884ceace KG |
390 | |
391 | return 0; | |
392 | } | |
393 | ||
a5f3d68e | 394 | static int |
a84c3ae1 | 395 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
396 | u32 invalidate_domains, u32 flush_domains) |
397 | { | |
398 | u32 flags = 0; | |
4a570db5 | 399 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 400 | int ret; |
a5f3d68e BW |
401 | |
402 | flags |= PIPE_CONTROL_CS_STALL; | |
403 | ||
404 | if (flush_domains) { | |
405 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
406 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 407 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 408 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
409 | } |
410 | if (invalidate_domains) { | |
411 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
412 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
413 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
414 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
415 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
416 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
417 | flags |= PIPE_CONTROL_QW_WRITE; | |
418 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
419 | |
420 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 421 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
422 | PIPE_CONTROL_CS_STALL | |
423 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
424 | 0); | |
425 | if (ret) | |
426 | return ret; | |
a5f3d68e BW |
427 | } |
428 | ||
f2cf1fcc | 429 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
430 | } |
431 | ||
0bc40be8 | 432 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 433 | u32 value) |
d46eefa2 | 434 | { |
0bc40be8 TU |
435 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
436 | I915_WRITE_TAIL(engine, value); | |
d46eefa2 XH |
437 | } |
438 | ||
0bc40be8 | 439 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 440 | { |
0bc40be8 | 441 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
50877445 | 442 | u64 acthd; |
8187a2b7 | 443 | |
0bc40be8 TU |
444 | if (INTEL_INFO(engine->dev)->gen >= 8) |
445 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
446 | RING_ACTHD_UDW(engine->mmio_base)); | |
447 | else if (INTEL_INFO(engine->dev)->gen >= 4) | |
448 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
50877445 CW |
449 | else |
450 | acthd = I915_READ(ACTHD); | |
451 | ||
452 | return acthd; | |
8187a2b7 ZN |
453 | } |
454 | ||
0bc40be8 | 455 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 456 | { |
0bc40be8 | 457 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
035dc1e0 DV |
458 | u32 addr; |
459 | ||
460 | addr = dev_priv->status_page_dmah->busaddr; | |
0bc40be8 | 461 | if (INTEL_INFO(engine->dev)->gen >= 4) |
035dc1e0 DV |
462 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
463 | I915_WRITE(HWS_PGA, addr); | |
464 | } | |
465 | ||
0bc40be8 | 466 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 467 | { |
0bc40be8 TU |
468 | struct drm_device *dev = engine->dev; |
469 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
f0f59a00 | 470 | i915_reg_t mmio; |
af75f269 DL |
471 | |
472 | /* The ring status page addresses are no longer next to the rest of | |
473 | * the ring registers as of gen7. | |
474 | */ | |
475 | if (IS_GEN7(dev)) { | |
0bc40be8 | 476 | switch (engine->id) { |
af75f269 DL |
477 | case RCS: |
478 | mmio = RENDER_HWS_PGA_GEN7; | |
479 | break; | |
480 | case BCS: | |
481 | mmio = BLT_HWS_PGA_GEN7; | |
482 | break; | |
483 | /* | |
484 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
485 | * gcc switch check warning | |
486 | */ | |
487 | case VCS2: | |
488 | case VCS: | |
489 | mmio = BSD_HWS_PGA_GEN7; | |
490 | break; | |
491 | case VECS: | |
492 | mmio = VEBOX_HWS_PGA_GEN7; | |
493 | break; | |
494 | } | |
0bc40be8 TU |
495 | } else if (IS_GEN6(engine->dev)) { |
496 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); | |
af75f269 DL |
497 | } else { |
498 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 499 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
500 | } |
501 | ||
0bc40be8 | 502 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
503 | POSTING_READ(mmio); |
504 | ||
505 | /* | |
506 | * Flush the TLB for this page | |
507 | * | |
508 | * FIXME: These two bits have disappeared on gen8, so a question | |
509 | * arises: do we still need this and if so how should we go about | |
510 | * invalidating the TLB? | |
511 | */ | |
512 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
0bc40be8 | 513 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
514 | |
515 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 516 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
517 | |
518 | I915_WRITE(reg, | |
519 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
520 | INSTPM_SYNC_FLUSH)); | |
521 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
522 | 1000)) | |
523 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
0bc40be8 | 524 | engine->name); |
af75f269 DL |
525 | } |
526 | } | |
527 | ||
0bc40be8 | 528 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 529 | { |
0bc40be8 | 530 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
8187a2b7 | 531 | |
0bc40be8 TU |
532 | if (!IS_GEN2(engine->dev)) { |
533 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); | |
534 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
535 | DRM_ERROR("%s : timed out trying to stop ring\n", | |
536 | engine->name); | |
9bec9b13 CW |
537 | /* Sometimes we observe that the idle flag is not |
538 | * set even though the ring is empty. So double | |
539 | * check before giving up. | |
540 | */ | |
0bc40be8 | 541 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 542 | return false; |
9991ae78 CW |
543 | } |
544 | } | |
b7884eb4 | 545 | |
0bc40be8 TU |
546 | I915_WRITE_CTL(engine, 0); |
547 | I915_WRITE_HEAD(engine, 0); | |
548 | engine->write_tail(engine, 0); | |
8187a2b7 | 549 | |
0bc40be8 TU |
550 | if (!IS_GEN2(engine->dev)) { |
551 | (void)I915_READ_CTL(engine); | |
552 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 553 | } |
a51435a3 | 554 | |
0bc40be8 | 555 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 556 | } |
8187a2b7 | 557 | |
fc0768ce TE |
558 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
559 | { | |
560 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
561 | } | |
562 | ||
0bc40be8 | 563 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 564 | { |
0bc40be8 | 565 | struct drm_device *dev = engine->dev; |
9991ae78 | 566 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 567 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 568 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
569 | int ret = 0; |
570 | ||
59bad947 | 571 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 572 | |
0bc40be8 | 573 | if (!stop_ring(engine)) { |
9991ae78 | 574 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
575 | DRM_DEBUG_KMS("%s head not reset to zero " |
576 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
577 | engine->name, |
578 | I915_READ_CTL(engine), | |
579 | I915_READ_HEAD(engine), | |
580 | I915_READ_TAIL(engine), | |
581 | I915_READ_START(engine)); | |
8187a2b7 | 582 | |
0bc40be8 | 583 | if (!stop_ring(engine)) { |
6fd0d56e CW |
584 | DRM_ERROR("failed to set %s head to zero " |
585 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
586 | engine->name, |
587 | I915_READ_CTL(engine), | |
588 | I915_READ_HEAD(engine), | |
589 | I915_READ_TAIL(engine), | |
590 | I915_READ_START(engine)); | |
9991ae78 CW |
591 | ret = -EIO; |
592 | goto out; | |
6fd0d56e | 593 | } |
8187a2b7 ZN |
594 | } |
595 | ||
9991ae78 | 596 | if (I915_NEED_GFX_HWS(dev)) |
0bc40be8 | 597 | intel_ring_setup_status_page(engine); |
9991ae78 | 598 | else |
0bc40be8 | 599 | ring_setup_phys_status_page(engine); |
9991ae78 | 600 | |
ece4a17d | 601 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 602 | I915_READ_HEAD(engine); |
ece4a17d | 603 | |
0d8957c8 DV |
604 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
605 | * registers with the above sequence (the readback of the HEAD registers | |
606 | * also enforces ordering), otherwise the hw might lose the new ring | |
607 | * register values. */ | |
0bc40be8 | 608 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
609 | |
610 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 611 | if (I915_READ_HEAD(engine)) |
95468892 | 612 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
613 | engine->name, I915_READ_HEAD(engine)); |
614 | I915_WRITE_HEAD(engine, 0); | |
615 | (void)I915_READ_HEAD(engine); | |
95468892 | 616 | |
0bc40be8 | 617 | I915_WRITE_CTL(engine, |
93b0a4e0 | 618 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 619 | | RING_VALID); |
8187a2b7 | 620 | |
8187a2b7 | 621 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
622 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
623 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
624 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 625 | DRM_ERROR("%s initialization failed " |
48e48a0b | 626 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
627 | engine->name, |
628 | I915_READ_CTL(engine), | |
629 | I915_READ_CTL(engine) & RING_VALID, | |
630 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
631 | I915_READ_START(engine), | |
632 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
633 | ret = -EIO; |
634 | goto out; | |
8187a2b7 ZN |
635 | } |
636 | ||
ebd0fd4b | 637 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
638 | ringbuf->head = I915_READ_HEAD(engine); |
639 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 640 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 641 | |
fc0768ce | 642 | intel_engine_init_hangcheck(engine); |
50f018df | 643 | |
b7884eb4 | 644 | out: |
59bad947 | 645 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
646 | |
647 | return ret; | |
8187a2b7 ZN |
648 | } |
649 | ||
9b1136d5 | 650 | void |
0bc40be8 | 651 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 652 | { |
0bc40be8 | 653 | struct drm_device *dev = engine->dev; |
9b1136d5 | 654 | |
0bc40be8 | 655 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
656 | return; |
657 | ||
658 | if (INTEL_INFO(dev)->gen >= 5) { | |
0bc40be8 TU |
659 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
660 | i915_gem_object_ggtt_unpin(engine->scratch.obj); | |
9b1136d5 OM |
661 | } |
662 | ||
0bc40be8 TU |
663 | drm_gem_object_unreference(&engine->scratch.obj->base); |
664 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
665 | } |
666 | ||
667 | int | |
0bc40be8 | 668 | intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 669 | { |
c6df541c CW |
670 | int ret; |
671 | ||
0bc40be8 | 672 | WARN_ON(engine->scratch.obj); |
c6df541c | 673 | |
0bc40be8 TU |
674 | engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096); |
675 | if (engine->scratch.obj == NULL) { | |
c6df541c CW |
676 | DRM_ERROR("Failed to allocate seqno page\n"); |
677 | ret = -ENOMEM; | |
678 | goto err; | |
679 | } | |
e4ffd173 | 680 | |
0bc40be8 TU |
681 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
682 | I915_CACHE_LLC); | |
a9cc726c DV |
683 | if (ret) |
684 | goto err_unref; | |
c6df541c | 685 | |
0bc40be8 | 686 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
c6df541c CW |
687 | if (ret) |
688 | goto err_unref; | |
689 | ||
0bc40be8 TU |
690 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
691 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); | |
692 | if (engine->scratch.cpu_page == NULL) { | |
56b085a0 | 693 | ret = -ENOMEM; |
c6df541c | 694 | goto err_unpin; |
56b085a0 | 695 | } |
c6df541c | 696 | |
2b1086cc | 697 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 698 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
699 | return 0; |
700 | ||
701 | err_unpin: | |
0bc40be8 | 702 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
c6df541c | 703 | err_unref: |
0bc40be8 | 704 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 705 | err: |
c6df541c CW |
706 | return ret; |
707 | } | |
708 | ||
e2be4faf | 709 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 710 | { |
7225342a | 711 | int ret, i; |
4a570db5 | 712 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 713 | struct drm_device *dev = engine->dev; |
888b5995 | 714 | struct drm_i915_private *dev_priv = dev->dev_private; |
7225342a | 715 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 716 | |
02235808 | 717 | if (w->count == 0) |
7225342a | 718 | return 0; |
888b5995 | 719 | |
e2f80391 | 720 | engine->gpu_caches_dirty = true; |
4866d729 | 721 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
722 | if (ret) |
723 | return ret; | |
888b5995 | 724 | |
5fb9de1a | 725 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
726 | if (ret) |
727 | return ret; | |
728 | ||
e2f80391 | 729 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 730 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
731 | intel_ring_emit_reg(engine, w->reg[i].addr); |
732 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 733 | } |
e2f80391 | 734 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 735 | |
e2f80391 | 736 | intel_ring_advance(engine); |
7225342a | 737 | |
e2f80391 | 738 | engine->gpu_caches_dirty = true; |
4866d729 | 739 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
740 | if (ret) |
741 | return ret; | |
888b5995 | 742 | |
7225342a | 743 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 744 | |
7225342a | 745 | return 0; |
86d7f238 AS |
746 | } |
747 | ||
8753181e | 748 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
749 | { |
750 | int ret; | |
751 | ||
e2be4faf | 752 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
753 | if (ret != 0) |
754 | return ret; | |
755 | ||
be01363f | 756 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 757 | if (ret) |
e26e1b97 | 758 | return ret; |
8f0e2b9d | 759 | |
e26e1b97 | 760 | return 0; |
8f0e2b9d DV |
761 | } |
762 | ||
7225342a | 763 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
764 | i915_reg_t addr, |
765 | const u32 mask, const u32 val) | |
7225342a MK |
766 | { |
767 | const u32 idx = dev_priv->workarounds.count; | |
768 | ||
769 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
770 | return -ENOSPC; | |
771 | ||
772 | dev_priv->workarounds.reg[idx].addr = addr; | |
773 | dev_priv->workarounds.reg[idx].value = val; | |
774 | dev_priv->workarounds.reg[idx].mask = mask; | |
775 | ||
776 | dev_priv->workarounds.count++; | |
777 | ||
778 | return 0; | |
86d7f238 AS |
779 | } |
780 | ||
ca5a0fbd | 781 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 782 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
783 | if (r) \ |
784 | return r; \ | |
ca5a0fbd | 785 | } while (0) |
7225342a MK |
786 | |
787 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 788 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
789 | |
790 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 791 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 792 | |
98533251 | 793 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 794 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 795 | |
cf4b0de6 DL |
796 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
797 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 798 | |
cf4b0de6 | 799 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 800 | |
0bc40be8 TU |
801 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
802 | i915_reg_t reg) | |
33136b06 | 803 | { |
0bc40be8 | 804 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
33136b06 | 805 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 806 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
807 | |
808 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
809 | return -EINVAL; | |
810 | ||
0bc40be8 | 811 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 812 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 813 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
814 | |
815 | return 0; | |
816 | } | |
817 | ||
0bc40be8 | 818 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 819 | { |
0bc40be8 | 820 | struct drm_device *dev = engine->dev; |
68c6198b AS |
821 | struct drm_i915_private *dev_priv = dev->dev_private; |
822 | ||
823 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 824 | |
717d84d6 AS |
825 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
826 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
827 | ||
d0581194 AS |
828 | /* WaDisablePartialInstShootdown:bdw,chv */ |
829 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
830 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
831 | ||
a340af58 AS |
832 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
833 | * workaround for for a possible hang in the unlikely event a TLB | |
834 | * invalidation occurs during a PSD flush. | |
835 | */ | |
836 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 837 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 838 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 839 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
840 | HDC_FORCE_NON_COHERENT); |
841 | ||
6def8fdd AS |
842 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
843 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
844 | * polygons in the same 8x4 pixel/sample area to be processed without | |
845 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
846 | * buffer." | |
847 | * | |
848 | * This optimization is off by default for BDW and CHV; turn it on. | |
849 | */ | |
850 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
851 | ||
48404636 AS |
852 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
853 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
854 | ||
7eebcde6 AS |
855 | /* |
856 | * BSpec recommends 8x4 when MSAA is used, | |
857 | * however in practice 16x4 seems fastest. | |
858 | * | |
859 | * Note that PS/WM thread counts depend on the WIZ hashing | |
860 | * disable bit, which we don't touch here, but it's good | |
861 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
862 | */ | |
863 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
864 | GEN6_WIZ_HASHING_MASK, | |
865 | GEN6_WIZ_HASHING_16x4); | |
866 | ||
e9a64ada AS |
867 | return 0; |
868 | } | |
869 | ||
0bc40be8 | 870 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 871 | { |
e9a64ada | 872 | int ret; |
0bc40be8 | 873 | struct drm_device *dev = engine->dev; |
888b5995 | 874 | struct drm_i915_private *dev_priv = dev->dev_private; |
86d7f238 | 875 | |
0bc40be8 | 876 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
877 | if (ret) |
878 | return ret; | |
879 | ||
101b376d | 880 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 881 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 882 | |
101b376d | 883 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
884 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
885 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 886 | |
7225342a MK |
887 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
888 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 889 | |
7225342a | 890 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
891 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
892 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 893 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 894 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 895 | |
86d7f238 AS |
896 | return 0; |
897 | } | |
898 | ||
0bc40be8 | 899 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 900 | { |
e9a64ada | 901 | int ret; |
0bc40be8 | 902 | struct drm_device *dev = engine->dev; |
00e1e623 VS |
903 | struct drm_i915_private *dev_priv = dev->dev_private; |
904 | ||
0bc40be8 | 905 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
906 | if (ret) |
907 | return ret; | |
908 | ||
00e1e623 | 909 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 910 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 911 | |
d60de81d KG |
912 | /* Improve HiZ throughput on CHV. */ |
913 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
914 | ||
7225342a MK |
915 | return 0; |
916 | } | |
917 | ||
0bc40be8 | 918 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 919 | { |
0bc40be8 | 920 | struct drm_device *dev = engine->dev; |
ab0dfafe | 921 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ea6f892 | 922 | uint32_t tmp; |
e0f3fa09 | 923 | int ret; |
ab0dfafe | 924 | |
9c4cbf82 MK |
925 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
926 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
927 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
928 | ||
929 | /* WaDisableKillLogic:bxt,skl */ | |
930 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
931 | ECOCHK_DIS_TLB); | |
932 | ||
950b2aae | 933 | /* WaClearFlowControlGpgpuContextSave:skl,bxt */ |
b0e6f6d4 | 934 | /* WaDisablePartialInstShootdown:skl,bxt */ |
ab0dfafe | 935 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 936 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
937 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
938 | ||
a119a6e6 | 939 | /* Syncing dependencies between camera and graphics:skl,bxt */ |
8424171e NH |
940 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
941 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
942 | ||
e87a005d JN |
943 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
944 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
945 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
a86eb582 DL |
946 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
947 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 948 | |
e87a005d JN |
949 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
950 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
951 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { | |
183c6dac DL |
952 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
953 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
954 | /* |
955 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
956 | * but we do that in per ctx batchbuffer as there is an issue | |
957 | * with this register not getting restored on ctx restore | |
958 | */ | |
183c6dac DL |
959 | } |
960 | ||
e87a005d JN |
961 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ |
962 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev)) | |
cac23df4 NH |
963 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
964 | GEN9_ENABLE_YV12_BUGFIX); | |
cac23df4 | 965 | |
5068368c | 966 | /* Wa4x4STCOptimizationDisable:skl,bxt */ |
27160c96 | 967 | /* WaDisablePartialResolveInVc:skl,bxt */ |
60294683 AS |
968 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
969 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 970 | |
16be17af | 971 | /* WaCcsTlbPrefetchDisable:skl,bxt */ |
e2db7071 DL |
972 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
973 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
974 | ||
5a2ae95e | 975 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
e87a005d JN |
976 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
977 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
38a39a7b BW |
978 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
979 | PIXEL_MASK_CAMMING_DISABLE); | |
980 | ||
8ea6f892 ID |
981 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ |
982 | tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; | |
e87a005d JN |
983 | if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) || |
984 | IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) | |
8ea6f892 ID |
985 | tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; |
986 | WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); | |
987 | ||
8c761609 | 988 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */ |
e87a005d | 989 | if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0)) |
8c761609 AS |
990 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
991 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 992 | |
6b6d5626 RB |
993 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
994 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); | |
995 | ||
6ecf56ae AS |
996 | /* WaOCLCoherentLineFlush:skl,bxt */ |
997 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | | |
998 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
999 | ||
e0f3fa09 | 1000 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ |
0bc40be8 | 1001 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1002 | if (ret) |
1003 | return ret; | |
1004 | ||
3669ab61 | 1005 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt */ |
0bc40be8 | 1006 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1007 | if (ret) |
1008 | return ret; | |
1009 | ||
3b106531 HN |
1010 | return 0; |
1011 | } | |
1012 | ||
0bc40be8 | 1013 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1014 | { |
0bc40be8 | 1015 | struct drm_device *dev = engine->dev; |
b7668791 DL |
1016 | struct drm_i915_private *dev_priv = dev->dev_private; |
1017 | u8 vals[3] = { 0, 0, 0 }; | |
1018 | unsigned int i; | |
1019 | ||
1020 | for (i = 0; i < 3; i++) { | |
1021 | u8 ss; | |
1022 | ||
1023 | /* | |
1024 | * Only consider slices where one, and only one, subslice has 7 | |
1025 | * EUs | |
1026 | */ | |
a4d8a0fe | 1027 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1028 | continue; |
1029 | ||
1030 | /* | |
1031 | * subslice_7eu[i] != 0 (because of the check above) and | |
1032 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1033 | * | |
1034 | * -> 0 <= ss <= 3; | |
1035 | */ | |
1036 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1037 | vals[i] = 3 - ss; | |
1038 | } | |
1039 | ||
1040 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1041 | return 0; | |
1042 | ||
1043 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1044 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1045 | GEN9_IZ_HASHING_MASK(2) | | |
1046 | GEN9_IZ_HASHING_MASK(1) | | |
1047 | GEN9_IZ_HASHING_MASK(0), | |
1048 | GEN9_IZ_HASHING(2, vals[2]) | | |
1049 | GEN9_IZ_HASHING(1, vals[1]) | | |
1050 | GEN9_IZ_HASHING(0, vals[0])); | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
0bc40be8 | 1055 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1056 | { |
aa0011a8 | 1057 | int ret; |
0bc40be8 | 1058 | struct drm_device *dev = engine->dev; |
d0bbbc4f DL |
1059 | struct drm_i915_private *dev_priv = dev->dev_private; |
1060 | ||
0bc40be8 | 1061 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1062 | if (ret) |
1063 | return ret; | |
8d205494 | 1064 | |
a78536e7 AS |
1065 | /* |
1066 | * Actual WA is to disable percontext preemption granularity control | |
1067 | * until D0 which is the default case so this is equivalent to | |
1068 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1069 | */ | |
1070 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { | |
1071 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1072 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1073 | } | |
1074 | ||
e87a005d | 1075 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
9c4cbf82 MK |
1076 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1077 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1078 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1079 | } | |
1080 | ||
1081 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1082 | * involving this register should also be added to WA batch as required. | |
1083 | */ | |
e87a005d | 1084 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1085 | /* WaDisableLSQCROPERFforOCL:skl */ |
1086 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1087 | GEN8_LQSC_RO_PERF_DIS); | |
1088 | ||
1089 | /* WaEnableGapsTsvCreditFix:skl */ | |
e87a005d | 1090 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1091 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1092 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1093 | } | |
1094 | ||
d0bbbc4f | 1095 | /* WaDisablePowerCompilerClockGating:skl */ |
e87a005d | 1096 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1097 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1098 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1099 | ||
e238659d | 1100 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) { |
b62adbd1 NH |
1101 | /* |
1102 | *Use Force Non-Coherent whenever executing a 3D context. This | |
1103 | * is a workaround for a possible hang in the unlikely event | |
1104 | * a TLB invalidation occurs during a PSD flush. | |
1105 | */ | |
1106 | /* WaForceEnableNonCoherent:skl */ | |
1107 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1108 | HDC_FORCE_NON_COHERENT); | |
e238659d MK |
1109 | |
1110 | /* WaDisableHDCInvalidation:skl */ | |
1111 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1112 | BDW_DISABLE_HDC_INVALIDATION); | |
b62adbd1 NH |
1113 | } |
1114 | ||
e87a005d JN |
1115 | /* WaBarrierPerformanceFixDisable:skl */ |
1116 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) | |
5b6fd12a VS |
1117 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1118 | HDC_FENCE_DEST_SLM_DISABLE | | |
1119 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1120 | ||
9bd9dfb4 | 1121 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
e87a005d | 1122 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1123 | WA_SET_BIT_MASKED( |
1124 | GEN7_HALF_SLICE_CHICKEN1, | |
1125 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1126 | |
6107497e | 1127 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1128 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1129 | if (ret) |
1130 | return ret; | |
1131 | ||
0bc40be8 | 1132 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1133 | } |
1134 | ||
0bc40be8 | 1135 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1136 | { |
aa0011a8 | 1137 | int ret; |
0bc40be8 | 1138 | struct drm_device *dev = engine->dev; |
dfb601e6 NH |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
1140 | ||
0bc40be8 | 1141 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1142 | if (ret) |
1143 | return ret; | |
cae0437f | 1144 | |
9c4cbf82 MK |
1145 | /* WaStoreMultiplePTEenable:bxt */ |
1146 | /* This is a requirement according to Hardware specification */ | |
cbdc12a9 | 1147 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1148 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1149 | ||
1150 | /* WaSetClckGatingDisableMedia:bxt */ | |
cbdc12a9 | 1151 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1152 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1153 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1154 | } | |
1155 | ||
dfb601e6 NH |
1156 | /* WaDisableThreadStallDopClockGating:bxt */ |
1157 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1158 | STALL_DOP_GATING_DISABLE); | |
1159 | ||
983b4b9d | 1160 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
e87a005d | 1161 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1162 | WA_SET_BIT_MASKED( |
1163 | GEN7_HALF_SLICE_CHICKEN1, | |
1164 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1165 | } | |
1166 | ||
2c8580e4 AS |
1167 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1168 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1169 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1170 | /* WaDisableLSQCROPERFforOCL:bxt */ |
2c8580e4 | 1171 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
0bc40be8 | 1172 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1173 | if (ret) |
1174 | return ret; | |
a786d53a | 1175 | |
0bc40be8 | 1176 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1177 | if (ret) |
1178 | return ret; | |
2c8580e4 AS |
1179 | } |
1180 | ||
cae0437f NH |
1181 | return 0; |
1182 | } | |
1183 | ||
0bc40be8 | 1184 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1185 | { |
0bc40be8 | 1186 | struct drm_device *dev = engine->dev; |
7225342a MK |
1187 | struct drm_i915_private *dev_priv = dev->dev_private; |
1188 | ||
0bc40be8 | 1189 | WARN_ON(engine->id != RCS); |
7225342a MK |
1190 | |
1191 | dev_priv->workarounds.count = 0; | |
33136b06 | 1192 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a MK |
1193 | |
1194 | if (IS_BROADWELL(dev)) | |
0bc40be8 | 1195 | return bdw_init_workarounds(engine); |
7225342a MK |
1196 | |
1197 | if (IS_CHERRYVIEW(dev)) | |
0bc40be8 | 1198 | return chv_init_workarounds(engine); |
00e1e623 | 1199 | |
8d205494 | 1200 | if (IS_SKYLAKE(dev)) |
0bc40be8 | 1201 | return skl_init_workarounds(engine); |
cae0437f NH |
1202 | |
1203 | if (IS_BROXTON(dev)) | |
0bc40be8 | 1204 | return bxt_init_workarounds(engine); |
3b106531 | 1205 | |
00e1e623 VS |
1206 | return 0; |
1207 | } | |
1208 | ||
0bc40be8 | 1209 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1210 | { |
0bc40be8 | 1211 | struct drm_device *dev = engine->dev; |
1ec14ad3 | 1212 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 1213 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1214 | if (ret) |
1215 | return ret; | |
a69ffdbf | 1216 | |
61a563a2 AG |
1217 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1218 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1219 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1220 | |
1221 | /* We need to disable the AsyncFlip performance optimisations in order | |
1222 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1223 | * programmed to '1' on all products. | |
8693a824 | 1224 | * |
2441f877 | 1225 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1226 | */ |
2441f877 | 1227 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
1c8c38c5 CW |
1228 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1229 | ||
f05bb0c7 | 1230 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1231 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1232 | if (INTEL_INFO(dev)->gen == 6) |
1233 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1234 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1235 | |
01fa0302 | 1236 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1237 | if (IS_GEN7(dev)) |
1238 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1239 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1240 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1241 | |
5e13a0c5 | 1242 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1243 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1244 | * "If this bit is set, STCunit will have LRA as replacement | |
1245 | * policy. [...] This bit must be reset. LRA replacement | |
1246 | * policy is not supported." | |
1247 | */ | |
1248 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1249 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1250 | } |
1251 | ||
9cc83020 | 1252 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
6b26c86d | 1253 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1254 | |
040d2baa | 1255 | if (HAS_L3_DPF(dev)) |
0bc40be8 | 1256 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1257 | |
0bc40be8 | 1258 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1259 | } |
1260 | ||
0bc40be8 | 1261 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1262 | { |
0bc40be8 | 1263 | struct drm_device *dev = engine->dev; |
3e78998a BW |
1264 | struct drm_i915_private *dev_priv = dev->dev_private; |
1265 | ||
1266 | if (dev_priv->semaphore_obj) { | |
1267 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1268 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1269 | dev_priv->semaphore_obj = NULL; | |
1270 | } | |
b45305fc | 1271 | |
0bc40be8 | 1272 | intel_fini_pipe_control(engine); |
c6df541c CW |
1273 | } |
1274 | ||
f7169687 | 1275 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1276 | unsigned int num_dwords) |
1277 | { | |
1278 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1279 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1280 | struct drm_device *dev = signaller->dev; |
1281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1282 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1283 | enum intel_engine_id id; |
1284 | int ret, num_rings; | |
3e78998a BW |
1285 | |
1286 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1287 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1288 | #undef MBOX_UPDATE_DWORDS | |
1289 | ||
5fb9de1a | 1290 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1291 | if (ret) |
1292 | return ret; | |
1293 | ||
c3232b18 | 1294 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1295 | u32 seqno; |
c3232b18 | 1296 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1297 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1298 | continue; | |
1299 | ||
f7169687 | 1300 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1301 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1302 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1303 | PIPE_CONTROL_QW_WRITE | | |
1304 | PIPE_CONTROL_FLUSH_ENABLE); | |
1305 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1306 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1307 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1308 | intel_ring_emit(signaller, 0); |
1309 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
1310 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1311 | intel_ring_emit(signaller, 0); | |
1312 | } | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
f7169687 | 1317 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1318 | unsigned int num_dwords) |
1319 | { | |
1320 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1321 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1322 | struct drm_device *dev = signaller->dev; |
1323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1324 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1325 | enum intel_engine_id id; |
1326 | int ret, num_rings; | |
3e78998a BW |
1327 | |
1328 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1329 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1330 | #undef MBOX_UPDATE_DWORDS | |
1331 | ||
5fb9de1a | 1332 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1333 | if (ret) |
1334 | return ret; | |
1335 | ||
c3232b18 | 1336 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1337 | u32 seqno; |
c3232b18 | 1338 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1339 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1340 | continue; | |
1341 | ||
f7169687 | 1342 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1343 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1344 | MI_FLUSH_DW_OP_STOREDW); | |
1345 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1346 | MI_FLUSH_DW_USE_GTT); | |
1347 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1348 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1349 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
1350 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1351 | intel_ring_emit(signaller, 0); | |
1352 | } | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
f7169687 | 1357 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1358 | unsigned int num_dwords) |
1ec14ad3 | 1359 | { |
4a570db5 | 1360 | struct intel_engine_cs *signaller = signaller_req->engine; |
024a43e1 BW |
1361 | struct drm_device *dev = signaller->dev; |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1363 | struct intel_engine_cs *useless; |
c3232b18 DG |
1364 | enum intel_engine_id id; |
1365 | int ret, num_rings; | |
78325f2d | 1366 | |
a1444b79 BW |
1367 | #define MBOX_UPDATE_DWORDS 3 |
1368 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1369 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1370 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1371 | |
5fb9de1a | 1372 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1373 | if (ret) |
1374 | return ret; | |
024a43e1 | 1375 | |
c3232b18 DG |
1376 | for_each_engine_id(useless, dev_priv, id) { |
1377 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1378 | |
1379 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1380 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1381 | |
78325f2d | 1382 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1383 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1384 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1385 | } |
1386 | } | |
024a43e1 | 1387 | |
a1444b79 BW |
1388 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1389 | if (num_rings % 2 == 0) | |
1390 | intel_ring_emit(signaller, MI_NOOP); | |
1391 | ||
024a43e1 | 1392 | return 0; |
1ec14ad3 CW |
1393 | } |
1394 | ||
c8c99b0f BW |
1395 | /** |
1396 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1397 | * |
1398 | * @request - request to write to the ring | |
c8c99b0f BW |
1399 | * |
1400 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1401 | * This acts like a signal in the canonical semaphore. | |
1402 | */ | |
1ec14ad3 | 1403 | static int |
ee044a88 | 1404 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1405 | { |
4a570db5 | 1406 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1407 | int ret; |
52ed2325 | 1408 | |
e2f80391 TU |
1409 | if (engine->semaphore.signal) |
1410 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1411 | else |
5fb9de1a | 1412 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1413 | |
1ec14ad3 CW |
1414 | if (ret) |
1415 | return ret; | |
1416 | ||
e2f80391 TU |
1417 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1418 | intel_ring_emit(engine, | |
1419 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1420 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1421 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1422 | __intel_ring_advance(engine); | |
1ec14ad3 | 1423 | |
1ec14ad3 CW |
1424 | return 0; |
1425 | } | |
1426 | ||
f72b3435 MK |
1427 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1428 | u32 seqno) | |
1429 | { | |
1430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1431 | return dev_priv->last_seqno < seqno; | |
1432 | } | |
1433 | ||
c8c99b0f BW |
1434 | /** |
1435 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1436 | * | |
1437 | * @waiter - ring that is waiting | |
1438 | * @signaller - ring which has, or will signal | |
1439 | * @seqno - seqno which the waiter will block on | |
1440 | */ | |
5ee426ca BW |
1441 | |
1442 | static int | |
599d924c | 1443 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1444 | struct intel_engine_cs *signaller, |
1445 | u32 seqno) | |
1446 | { | |
4a570db5 | 1447 | struct intel_engine_cs *waiter = waiter_req->engine; |
5ee426ca BW |
1448 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
1449 | int ret; | |
1450 | ||
5fb9de1a | 1451 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1452 | if (ret) |
1453 | return ret; | |
1454 | ||
1455 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1456 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1457 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1458 | MI_SEMAPHORE_SAD_GTE_SDD); |
1459 | intel_ring_emit(waiter, seqno); | |
1460 | intel_ring_emit(waiter, | |
1461 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1462 | intel_ring_emit(waiter, | |
1463 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1464 | intel_ring_advance(waiter); | |
1465 | return 0; | |
1466 | } | |
1467 | ||
c8c99b0f | 1468 | static int |
599d924c | 1469 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1470 | struct intel_engine_cs *signaller, |
686cb5f9 | 1471 | u32 seqno) |
1ec14ad3 | 1472 | { |
4a570db5 | 1473 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1474 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1475 | MI_SEMAPHORE_COMPARE | | |
1476 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1477 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1478 | int ret; | |
1ec14ad3 | 1479 | |
1500f7ea BW |
1480 | /* Throughout all of the GEM code, seqno passed implies our current |
1481 | * seqno is >= the last seqno executed. However for hardware the | |
1482 | * comparison is strictly greater than. | |
1483 | */ | |
1484 | seqno -= 1; | |
1485 | ||
ebc348b2 | 1486 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1487 | |
5fb9de1a | 1488 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1489 | if (ret) |
1490 | return ret; | |
1491 | ||
f72b3435 MK |
1492 | /* If seqno wrap happened, omit the wait with no-ops */ |
1493 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1494 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1495 | intel_ring_emit(waiter, seqno); |
1496 | intel_ring_emit(waiter, 0); | |
1497 | intel_ring_emit(waiter, MI_NOOP); | |
1498 | } else { | |
1499 | intel_ring_emit(waiter, MI_NOOP); | |
1500 | intel_ring_emit(waiter, MI_NOOP); | |
1501 | intel_ring_emit(waiter, MI_NOOP); | |
1502 | intel_ring_emit(waiter, MI_NOOP); | |
1503 | } | |
c8c99b0f | 1504 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1505 | |
1506 | return 0; | |
1507 | } | |
1508 | ||
c6df541c CW |
1509 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1510 | do { \ | |
fcbc34e4 KG |
1511 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1512 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1513 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1514 | intel_ring_emit(ring__, 0); \ | |
1515 | intel_ring_emit(ring__, 0); \ | |
1516 | } while (0) | |
1517 | ||
1518 | static int | |
ee044a88 | 1519 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1520 | { |
4a570db5 | 1521 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1522 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1523 | int ret; |
1524 | ||
1525 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1526 | * incoherent with writes to memory, i.e. completely fubar, | |
1527 | * so we need to use PIPE_NOTIFY instead. | |
1528 | * | |
1529 | * However, we also need to workaround the qword write | |
1530 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1531 | * memory before requesting an interrupt. | |
1532 | */ | |
5fb9de1a | 1533 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1534 | if (ret) |
1535 | return ret; | |
1536 | ||
e2f80391 TU |
1537 | intel_ring_emit(engine, |
1538 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1539 | PIPE_CONTROL_WRITE_FLUSH | |
1540 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
e2f80391 TU |
1541 | intel_ring_emit(engine, |
1542 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1543 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1544 | intel_ring_emit(engine, 0); | |
1545 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1546 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1547 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1548 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1549 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1550 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1551 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1552 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1553 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1554 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1555 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1556 | |
e2f80391 TU |
1557 | intel_ring_emit(engine, |
1558 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1559 | PIPE_CONTROL_WRITE_FLUSH | |
1560 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1561 | PIPE_CONTROL_NOTIFY); |
e2f80391 TU |
1562 | intel_ring_emit(engine, |
1563 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1564 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1565 | intel_ring_emit(engine, 0); | |
1566 | __intel_ring_advance(engine); | |
c6df541c | 1567 | |
c6df541c CW |
1568 | return 0; |
1569 | } | |
1570 | ||
c04e0f3b CW |
1571 | static void |
1572 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1573 | { |
4cd53c0c DV |
1574 | /* Workaround to force correct ordering between irq and seqno writes on |
1575 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1576 | * ACTHD) before reading the status page. |
1577 | * | |
1578 | * Note that this effectively stalls the read by the time it takes to | |
1579 | * do a memory transaction, which more or less ensures that the write | |
1580 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1581 | * Alternatively we could delay the interrupt from the CS ring to give | |
1582 | * the write time to land, but that would incur a delay after every | |
1583 | * batch i.e. much more frequent than a delay when waiting for the | |
1584 | * interrupt (with the same net latency). | |
1585 | */ | |
c04e0f3b CW |
1586 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
1587 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); | |
4cd53c0c DV |
1588 | } |
1589 | ||
8187a2b7 | 1590 | static u32 |
c04e0f3b | 1591 | ring_get_seqno(struct intel_engine_cs *engine) |
8187a2b7 | 1592 | { |
0bc40be8 | 1593 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
1ec14ad3 CW |
1594 | } |
1595 | ||
b70ec5bf | 1596 | static void |
0bc40be8 | 1597 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1598 | { |
0bc40be8 | 1599 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
b70ec5bf MK |
1600 | } |
1601 | ||
c6df541c | 1602 | static u32 |
c04e0f3b | 1603 | pc_render_get_seqno(struct intel_engine_cs *engine) |
c6df541c | 1604 | { |
0bc40be8 | 1605 | return engine->scratch.cpu_page[0]; |
c6df541c CW |
1606 | } |
1607 | ||
b70ec5bf | 1608 | static void |
0bc40be8 | 1609 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1610 | { |
0bc40be8 | 1611 | engine->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1612 | } |
1613 | ||
e48d8634 | 1614 | static bool |
0bc40be8 | 1615 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1616 | { |
0bc40be8 | 1617 | struct drm_device *dev = engine->dev; |
4640c4ff | 1618 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1619 | unsigned long flags; |
e48d8634 | 1620 | |
7cd512f1 | 1621 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1622 | return false; |
1623 | ||
7338aefa | 1624 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1625 | if (engine->irq_refcount++ == 0) |
1626 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1627 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1628 | |
1629 | return true; | |
1630 | } | |
1631 | ||
1632 | static void | |
0bc40be8 | 1633 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1634 | { |
0bc40be8 | 1635 | struct drm_device *dev = engine->dev; |
4640c4ff | 1636 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1637 | unsigned long flags; |
e48d8634 | 1638 | |
7338aefa | 1639 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1640 | if (--engine->irq_refcount == 0) |
1641 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1642 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1643 | } |
1644 | ||
b13c2b96 | 1645 | static bool |
0bc40be8 | 1646 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1647 | { |
0bc40be8 | 1648 | struct drm_device *dev = engine->dev; |
4640c4ff | 1649 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1650 | unsigned long flags; |
62fdfeaf | 1651 | |
7cd512f1 | 1652 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1653 | return false; |
1654 | ||
7338aefa | 1655 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1656 | if (engine->irq_refcount++ == 0) { |
1657 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1658 | I915_WRITE(IMR, dev_priv->irq_mask); |
1659 | POSTING_READ(IMR); | |
1660 | } | |
7338aefa | 1661 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1662 | |
1663 | return true; | |
62fdfeaf EA |
1664 | } |
1665 | ||
8187a2b7 | 1666 | static void |
0bc40be8 | 1667 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1668 | { |
0bc40be8 | 1669 | struct drm_device *dev = engine->dev; |
4640c4ff | 1670 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1671 | unsigned long flags; |
62fdfeaf | 1672 | |
7338aefa | 1673 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1674 | if (--engine->irq_refcount == 0) { |
1675 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1676 | I915_WRITE(IMR, dev_priv->irq_mask); |
1677 | POSTING_READ(IMR); | |
1678 | } | |
7338aefa | 1679 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1680 | } |
1681 | ||
c2798b19 | 1682 | static bool |
0bc40be8 | 1683 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1684 | { |
0bc40be8 | 1685 | struct drm_device *dev = engine->dev; |
4640c4ff | 1686 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1687 | unsigned long flags; |
c2798b19 | 1688 | |
7cd512f1 | 1689 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1690 | return false; |
1691 | ||
7338aefa | 1692 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1693 | if (engine->irq_refcount++ == 0) { |
1694 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1695 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1696 | POSTING_READ16(IMR); | |
1697 | } | |
7338aefa | 1698 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1699 | |
1700 | return true; | |
1701 | } | |
1702 | ||
1703 | static void | |
0bc40be8 | 1704 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1705 | { |
0bc40be8 | 1706 | struct drm_device *dev = engine->dev; |
4640c4ff | 1707 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1708 | unsigned long flags; |
c2798b19 | 1709 | |
7338aefa | 1710 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1711 | if (--engine->irq_refcount == 0) { |
1712 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1713 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1714 | POSTING_READ16(IMR); | |
1715 | } | |
7338aefa | 1716 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1717 | } |
1718 | ||
b72f3acb | 1719 | static int |
a84c3ae1 | 1720 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1721 | u32 invalidate_domains, |
1722 | u32 flush_domains) | |
d1b851fc | 1723 | { |
4a570db5 | 1724 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1725 | int ret; |
1726 | ||
5fb9de1a | 1727 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1728 | if (ret) |
1729 | return ret; | |
1730 | ||
e2f80391 TU |
1731 | intel_ring_emit(engine, MI_FLUSH); |
1732 | intel_ring_emit(engine, MI_NOOP); | |
1733 | intel_ring_advance(engine); | |
b72f3acb | 1734 | return 0; |
d1b851fc ZN |
1735 | } |
1736 | ||
3cce469c | 1737 | static int |
ee044a88 | 1738 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1739 | { |
4a570db5 | 1740 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1741 | int ret; |
1742 | ||
5fb9de1a | 1743 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1744 | if (ret) |
1745 | return ret; | |
6f392d54 | 1746 | |
e2f80391 TU |
1747 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1748 | intel_ring_emit(engine, | |
1749 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1750 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1751 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1752 | __intel_ring_advance(engine); | |
d1b851fc | 1753 | |
3cce469c | 1754 | return 0; |
d1b851fc ZN |
1755 | } |
1756 | ||
0f46832f | 1757 | static bool |
0bc40be8 | 1758 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1759 | { |
0bc40be8 | 1760 | struct drm_device *dev = engine->dev; |
4640c4ff | 1761 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1762 | unsigned long flags; |
0f46832f | 1763 | |
7cd512f1 DV |
1764 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1765 | return false; | |
0f46832f | 1766 | |
7338aefa | 1767 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1768 | if (engine->irq_refcount++ == 0) { |
1769 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1770 | I915_WRITE_IMR(engine, | |
1771 | ~(engine->irq_enable_mask | | |
35a85ac6 | 1772 | GT_PARITY_ERROR(dev))); |
15b9f80e | 1773 | else |
0bc40be8 TU |
1774 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1775 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1776 | } |
7338aefa | 1777 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1778 | |
1779 | return true; | |
1780 | } | |
1781 | ||
1782 | static void | |
0bc40be8 | 1783 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1784 | { |
0bc40be8 | 1785 | struct drm_device *dev = engine->dev; |
4640c4ff | 1786 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1787 | unsigned long flags; |
0f46832f | 1788 | |
7338aefa | 1789 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1790 | if (--engine->irq_refcount == 0) { |
1791 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1792 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); | |
15b9f80e | 1793 | else |
0bc40be8 TU |
1794 | I915_WRITE_IMR(engine, ~0); |
1795 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1796 | } |
7338aefa | 1797 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1798 | } |
1799 | ||
a19d2933 | 1800 | static bool |
0bc40be8 | 1801 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1802 | { |
0bc40be8 | 1803 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1804 | struct drm_i915_private *dev_priv = dev->dev_private; |
1805 | unsigned long flags; | |
1806 | ||
7cd512f1 | 1807 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1808 | return false; |
1809 | ||
59cdb63d | 1810 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1811 | if (engine->irq_refcount++ == 0) { |
1812 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1813 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1814 | } |
59cdb63d | 1815 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1816 | |
1817 | return true; | |
1818 | } | |
1819 | ||
1820 | static void | |
0bc40be8 | 1821 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1822 | { |
0bc40be8 | 1823 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1824 | struct drm_i915_private *dev_priv = dev->dev_private; |
1825 | unsigned long flags; | |
1826 | ||
59cdb63d | 1827 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1828 | if (--engine->irq_refcount == 0) { |
1829 | I915_WRITE_IMR(engine, ~0); | |
1830 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1831 | } |
59cdb63d | 1832 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1833 | } |
1834 | ||
abd58f01 | 1835 | static bool |
0bc40be8 | 1836 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1837 | { |
0bc40be8 | 1838 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1839 | struct drm_i915_private *dev_priv = dev->dev_private; |
1840 | unsigned long flags; | |
1841 | ||
7cd512f1 | 1842 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1843 | return false; |
1844 | ||
1845 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1846 | if (engine->irq_refcount++ == 0) { |
1847 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1848 | I915_WRITE_IMR(engine, | |
1849 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1850 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1851 | } else { | |
0bc40be8 | 1852 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1853 | } |
0bc40be8 | 1854 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1855 | } |
1856 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1857 | ||
1858 | return true; | |
1859 | } | |
1860 | ||
1861 | static void | |
0bc40be8 | 1862 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1863 | { |
0bc40be8 | 1864 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1865 | struct drm_i915_private *dev_priv = dev->dev_private; |
1866 | unsigned long flags; | |
1867 | ||
1868 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1869 | if (--engine->irq_refcount == 0) { |
1870 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1871 | I915_WRITE_IMR(engine, | |
abd58f01 BW |
1872 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1873 | } else { | |
0bc40be8 | 1874 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1875 | } |
0bc40be8 | 1876 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1877 | } |
1878 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1879 | } | |
1880 | ||
d1b851fc | 1881 | static int |
53fddaf7 | 1882 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1883 | u64 offset, u32 length, |
8e004efc | 1884 | unsigned dispatch_flags) |
d1b851fc | 1885 | { |
4a570db5 | 1886 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1887 | int ret; |
78501eac | 1888 | |
5fb9de1a | 1889 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1890 | if (ret) |
1891 | return ret; | |
1892 | ||
e2f80391 | 1893 | intel_ring_emit(engine, |
65f56876 CW |
1894 | MI_BATCH_BUFFER_START | |
1895 | MI_BATCH_GTT | | |
8e004efc JH |
1896 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1897 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1898 | intel_ring_emit(engine, offset); |
1899 | intel_ring_advance(engine); | |
78501eac | 1900 | |
d1b851fc ZN |
1901 | return 0; |
1902 | } | |
1903 | ||
b45305fc DV |
1904 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1905 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1906 | #define I830_TLB_ENTRIES (2) |
1907 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1908 | static int |
53fddaf7 | 1909 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1910 | u64 offset, u32 len, |
1911 | unsigned dispatch_flags) | |
62fdfeaf | 1912 | { |
4a570db5 | 1913 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1914 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1915 | int ret; |
62fdfeaf | 1916 | |
5fb9de1a | 1917 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1918 | if (ret) |
1919 | return ret; | |
62fdfeaf | 1920 | |
c4d69da1 | 1921 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1922 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1923 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1924 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1925 | intel_ring_emit(engine, cs_offset); | |
1926 | intel_ring_emit(engine, 0xdeadbeef); | |
1927 | intel_ring_emit(engine, MI_NOOP); | |
1928 | intel_ring_advance(engine); | |
b45305fc | 1929 | |
8e004efc | 1930 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1931 | if (len > I830_BATCH_LIMIT) |
1932 | return -ENOSPC; | |
1933 | ||
5fb9de1a | 1934 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1935 | if (ret) |
1936 | return ret; | |
c4d69da1 CW |
1937 | |
1938 | /* Blit the batch (which has now all relocs applied) to the | |
1939 | * stable batch scratch bo area (so that the CS never | |
1940 | * stumbles over its tlb invalidation bug) ... | |
1941 | */ | |
e2f80391 TU |
1942 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1943 | intel_ring_emit(engine, | |
1944 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
1945 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
1946 | intel_ring_emit(engine, cs_offset); | |
1947 | intel_ring_emit(engine, 4096); | |
1948 | intel_ring_emit(engine, offset); | |
1949 | ||
1950 | intel_ring_emit(engine, MI_FLUSH); | |
1951 | intel_ring_emit(engine, MI_NOOP); | |
1952 | intel_ring_advance(engine); | |
b45305fc DV |
1953 | |
1954 | /* ... and execute it. */ | |
c4d69da1 | 1955 | offset = cs_offset; |
b45305fc | 1956 | } |
e1f99ce6 | 1957 | |
9d611c03 | 1958 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1959 | if (ret) |
1960 | return ret; | |
1961 | ||
e2f80391 TU |
1962 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1963 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1964 | 0 : MI_BATCH_NON_SECURE)); | |
1965 | intel_ring_advance(engine); | |
c4d69da1 | 1966 | |
fb3256da DV |
1967 | return 0; |
1968 | } | |
1969 | ||
1970 | static int | |
53fddaf7 | 1971 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1972 | u64 offset, u32 len, |
8e004efc | 1973 | unsigned dispatch_flags) |
fb3256da | 1974 | { |
4a570db5 | 1975 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
1976 | int ret; |
1977 | ||
5fb9de1a | 1978 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1979 | if (ret) |
1980 | return ret; | |
1981 | ||
e2f80391 TU |
1982 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1983 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1984 | 0 : MI_BATCH_NON_SECURE)); | |
1985 | intel_ring_advance(engine); | |
62fdfeaf | 1986 | |
62fdfeaf EA |
1987 | return 0; |
1988 | } | |
1989 | ||
0bc40be8 | 1990 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1991 | { |
0bc40be8 | 1992 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
7d3fdfff VS |
1993 | |
1994 | if (!dev_priv->status_page_dmah) | |
1995 | return; | |
1996 | ||
0bc40be8 TU |
1997 | drm_pci_free(engine->dev, dev_priv->status_page_dmah); |
1998 | engine->status_page.page_addr = NULL; | |
7d3fdfff VS |
1999 | } |
2000 | ||
0bc40be8 | 2001 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2002 | { |
05394f39 | 2003 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2004 | |
0bc40be8 | 2005 | obj = engine->status_page.obj; |
8187a2b7 | 2006 | if (obj == NULL) |
62fdfeaf | 2007 | return; |
62fdfeaf | 2008 | |
9da3da66 | 2009 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2010 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2011 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2012 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2013 | } |
2014 | ||
0bc40be8 | 2015 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2016 | { |
0bc40be8 | 2017 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2018 | |
7d3fdfff | 2019 | if (obj == NULL) { |
1f767e02 | 2020 | unsigned flags; |
e3efda49 | 2021 | int ret; |
e4ffd173 | 2022 | |
0bc40be8 | 2023 | obj = i915_gem_alloc_object(engine->dev, 4096); |
e3efda49 CW |
2024 | if (obj == NULL) { |
2025 | DRM_ERROR("Failed to allocate status page\n"); | |
2026 | return -ENOMEM; | |
2027 | } | |
62fdfeaf | 2028 | |
e3efda49 CW |
2029 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2030 | if (ret) | |
2031 | goto err_unref; | |
2032 | ||
1f767e02 | 2033 | flags = 0; |
0bc40be8 | 2034 | if (!HAS_LLC(engine->dev)) |
1f767e02 CW |
2035 | /* On g33, we cannot place HWS above 256MiB, so |
2036 | * restrict its pinning to the low mappable arena. | |
2037 | * Though this restriction is not documented for | |
2038 | * gen4, gen5, or byt, they also behave similarly | |
2039 | * and hang if the HWS is placed at the top of the | |
2040 | * GTT. To generalise, it appears that all !llc | |
2041 | * platforms have issues with us placing the HWS | |
2042 | * above the mappable region (even though we never | |
2043 | * actualy map it). | |
2044 | */ | |
2045 | flags |= PIN_MAPPABLE; | |
2046 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2047 | if (ret) { |
2048 | err_unref: | |
2049 | drm_gem_object_unreference(&obj->base); | |
2050 | return ret; | |
2051 | } | |
2052 | ||
0bc40be8 | 2053 | engine->status_page.obj = obj; |
e3efda49 | 2054 | } |
62fdfeaf | 2055 | |
0bc40be8 TU |
2056 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2057 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2058 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2059 | |
8187a2b7 | 2060 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2061 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2062 | |
2063 | return 0; | |
62fdfeaf EA |
2064 | } |
2065 | ||
0bc40be8 | 2066 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2067 | { |
0bc40be8 | 2068 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
6b8294a4 CW |
2069 | |
2070 | if (!dev_priv->status_page_dmah) { | |
2071 | dev_priv->status_page_dmah = | |
0bc40be8 | 2072 | drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2073 | if (!dev_priv->status_page_dmah) |
2074 | return -ENOMEM; | |
2075 | } | |
2076 | ||
0bc40be8 TU |
2077 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2078 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2079 | |
2080 | return 0; | |
2081 | } | |
2082 | ||
7ba717cf | 2083 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2084 | { |
def0c5f6 | 2085 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2086 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 CW |
2087 | else |
2088 | iounmap(ringbuf->virtual_start); | |
0eb973d3 | 2089 | ringbuf->vma = NULL; |
2919d291 | 2090 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
2091 | } |
2092 | ||
2093 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
2094 | struct intel_ringbuffer *ringbuf) | |
2095 | { | |
2096 | struct drm_i915_private *dev_priv = to_i915(dev); | |
72e96d64 | 2097 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7ba717cf TD |
2098 | struct drm_i915_gem_object *obj = ringbuf->obj; |
2099 | int ret; | |
2100 | ||
def0c5f6 CW |
2101 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
2102 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0); | |
2103 | if (ret) | |
2104 | return ret; | |
7ba717cf | 2105 | |
def0c5f6 | 2106 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2107 | if (ret) |
2108 | goto err_unpin; | |
def0c5f6 | 2109 | |
0a798eb9 | 2110 | ringbuf->virtual_start = i915_gem_object_pin_map(obj); |
def0c5f6 | 2111 | if (ringbuf->virtual_start == NULL) { |
d2cad535 CW |
2112 | ret = -ENOMEM; |
2113 | goto err_unpin; | |
def0c5f6 CW |
2114 | } |
2115 | } else { | |
2116 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); | |
2117 | if (ret) | |
2118 | return ret; | |
7ba717cf | 2119 | |
def0c5f6 | 2120 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2121 | if (ret) |
2122 | goto err_unpin; | |
def0c5f6 | 2123 | |
ff3dc087 DCS |
2124 | /* Access through the GTT requires the device to be awake. */ |
2125 | assert_rpm_wakelock_held(dev_priv); | |
2126 | ||
72e96d64 | 2127 | ringbuf->virtual_start = ioremap_wc(ggtt->mappable_base + |
def0c5f6 CW |
2128 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
2129 | if (ringbuf->virtual_start == NULL) { | |
d2cad535 CW |
2130 | ret = -ENOMEM; |
2131 | goto err_unpin; | |
def0c5f6 | 2132 | } |
7ba717cf TD |
2133 | } |
2134 | ||
0eb973d3 | 2135 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2136 | return 0; |
d2cad535 CW |
2137 | |
2138 | err_unpin: | |
2139 | i915_gem_object_ggtt_unpin(obj); | |
2140 | return ret; | |
7ba717cf TD |
2141 | } |
2142 | ||
01101fa7 | 2143 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2144 | { |
2919d291 OM |
2145 | drm_gem_object_unreference(&ringbuf->obj->base); |
2146 | ringbuf->obj = NULL; | |
2147 | } | |
2148 | ||
01101fa7 CW |
2149 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2150 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2151 | { |
05394f39 | 2152 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2153 | |
ebc052e0 CW |
2154 | obj = NULL; |
2155 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2156 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2157 | if (obj == NULL) |
93b0a4e0 | 2158 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
2159 | if (obj == NULL) |
2160 | return -ENOMEM; | |
8187a2b7 | 2161 | |
24f3a8cf AG |
2162 | /* mark ring buffers as read-only from GPU side by default */ |
2163 | obj->gt_ro = 1; | |
2164 | ||
93b0a4e0 | 2165 | ringbuf->obj = obj; |
e3efda49 | 2166 | |
7ba717cf | 2167 | return 0; |
e3efda49 CW |
2168 | } |
2169 | ||
01101fa7 CW |
2170 | struct intel_ringbuffer * |
2171 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2172 | { | |
2173 | struct intel_ringbuffer *ring; | |
2174 | int ret; | |
2175 | ||
2176 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2177 | if (ring == NULL) { |
2178 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2179 | engine->name); | |
01101fa7 | 2180 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2181 | } |
01101fa7 | 2182 | |
4a570db5 | 2183 | ring->engine = engine; |
608c1a52 | 2184 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2185 | |
2186 | ring->size = size; | |
2187 | /* Workaround an erratum on the i830 which causes a hang if | |
2188 | * the TAIL pointer points to within the last 2 cachelines | |
2189 | * of the buffer. | |
2190 | */ | |
2191 | ring->effective_size = size; | |
2192 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) | |
2193 | ring->effective_size -= 2 * CACHELINE_BYTES; | |
2194 | ||
2195 | ring->last_retired_head = -1; | |
2196 | intel_ring_update_space(ring); | |
2197 | ||
2198 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); | |
2199 | if (ret) { | |
608c1a52 CW |
2200 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2201 | engine->name, ret); | |
2202 | list_del(&ring->link); | |
01101fa7 CW |
2203 | kfree(ring); |
2204 | return ERR_PTR(ret); | |
2205 | } | |
2206 | ||
2207 | return ring; | |
2208 | } | |
2209 | ||
2210 | void | |
2211 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2212 | { | |
2213 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2214 | list_del(&ring->link); |
01101fa7 CW |
2215 | kfree(ring); |
2216 | } | |
2217 | ||
e3efda49 | 2218 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2219 | struct intel_engine_cs *engine) |
e3efda49 | 2220 | { |
bfc882b4 | 2221 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2222 | int ret; |
2223 | ||
0bc40be8 | 2224 | WARN_ON(engine->buffer); |
bfc882b4 | 2225 | |
0bc40be8 TU |
2226 | engine->dev = dev; |
2227 | INIT_LIST_HEAD(&engine->active_list); | |
2228 | INIT_LIST_HEAD(&engine->request_list); | |
2229 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2230 | INIT_LIST_HEAD(&engine->buffers); | |
2231 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2232 | memset(engine->semaphore.sync_seqno, 0, | |
2233 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2234 | |
0bc40be8 | 2235 | init_waitqueue_head(&engine->irq_queue); |
e3efda49 | 2236 | |
0bc40be8 | 2237 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2238 | if (IS_ERR(ringbuf)) { |
2239 | ret = PTR_ERR(ringbuf); | |
2240 | goto error; | |
2241 | } | |
0bc40be8 | 2242 | engine->buffer = ringbuf; |
01101fa7 | 2243 | |
e3efda49 | 2244 | if (I915_NEED_GFX_HWS(dev)) { |
0bc40be8 | 2245 | ret = init_status_page(engine); |
e3efda49 | 2246 | if (ret) |
8ee14975 | 2247 | goto error; |
e3efda49 | 2248 | } else { |
0bc40be8 TU |
2249 | WARN_ON(engine->id != RCS); |
2250 | ret = init_phys_status_page(engine); | |
e3efda49 | 2251 | if (ret) |
8ee14975 | 2252 | goto error; |
e3efda49 CW |
2253 | } |
2254 | ||
bfc882b4 DV |
2255 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
2256 | if (ret) { | |
2257 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2258 | engine->name, ret); |
bfc882b4 DV |
2259 | intel_destroy_ringbuffer_obj(ringbuf); |
2260 | goto error; | |
e3efda49 | 2261 | } |
62fdfeaf | 2262 | |
0bc40be8 | 2263 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2264 | if (ret) |
8ee14975 OM |
2265 | goto error; |
2266 | ||
8ee14975 | 2267 | return 0; |
351e3db2 | 2268 | |
8ee14975 | 2269 | error: |
117897f4 | 2270 | intel_cleanup_engine(engine); |
8ee14975 | 2271 | return ret; |
62fdfeaf EA |
2272 | } |
2273 | ||
117897f4 | 2274 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2275 | { |
6402c330 | 2276 | struct drm_i915_private *dev_priv; |
33626e6a | 2277 | |
117897f4 | 2278 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2279 | return; |
2280 | ||
0bc40be8 | 2281 | dev_priv = to_i915(engine->dev); |
6402c330 | 2282 | |
0bc40be8 | 2283 | if (engine->buffer) { |
117897f4 | 2284 | intel_stop_engine(engine); |
0bc40be8 | 2285 | WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2286 | |
0bc40be8 TU |
2287 | intel_unpin_ringbuffer_obj(engine->buffer); |
2288 | intel_ringbuffer_free(engine->buffer); | |
2289 | engine->buffer = NULL; | |
b0366a54 | 2290 | } |
78501eac | 2291 | |
0bc40be8 TU |
2292 | if (engine->cleanup) |
2293 | engine->cleanup(engine); | |
8d19215b | 2294 | |
0bc40be8 TU |
2295 | if (I915_NEED_GFX_HWS(engine->dev)) { |
2296 | cleanup_status_page(engine); | |
7d3fdfff | 2297 | } else { |
0bc40be8 TU |
2298 | WARN_ON(engine->id != RCS); |
2299 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2300 | } |
44e895a8 | 2301 | |
0bc40be8 TU |
2302 | i915_cmd_parser_fini_ring(engine); |
2303 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
2304 | engine->dev = NULL; | |
62fdfeaf EA |
2305 | } |
2306 | ||
0bc40be8 | 2307 | static int ring_wait_for_space(struct intel_engine_cs *engine, int n) |
a71d8d94 | 2308 | { |
0bc40be8 | 2309 | struct intel_ringbuffer *ringbuf = engine->buffer; |
a71d8d94 | 2310 | struct drm_i915_gem_request *request; |
b4716185 CW |
2311 | unsigned space; |
2312 | int ret; | |
a71d8d94 | 2313 | |
ebd0fd4b DG |
2314 | if (intel_ring_space(ringbuf) >= n) |
2315 | return 0; | |
a71d8d94 | 2316 | |
79bbcc29 JH |
2317 | /* The whole point of reserving space is to not wait! */ |
2318 | WARN_ON(ringbuf->reserved_in_use); | |
2319 | ||
0bc40be8 | 2320 | list_for_each_entry(request, &engine->request_list, list) { |
b4716185 CW |
2321 | space = __intel_ring_space(request->postfix, ringbuf->tail, |
2322 | ringbuf->size); | |
2323 | if (space >= n) | |
a71d8d94 | 2324 | break; |
a71d8d94 CW |
2325 | } |
2326 | ||
0bc40be8 | 2327 | if (WARN_ON(&request->list == &engine->request_list)) |
a71d8d94 CW |
2328 | return -ENOSPC; |
2329 | ||
a4b3a571 | 2330 | ret = i915_wait_request(request); |
a71d8d94 CW |
2331 | if (ret) |
2332 | return ret; | |
2333 | ||
b4716185 | 2334 | ringbuf->space = space; |
a71d8d94 CW |
2335 | return 0; |
2336 | } | |
2337 | ||
79bbcc29 | 2338 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
3e960501 CW |
2339 | { |
2340 | uint32_t __iomem *virt; | |
93b0a4e0 | 2341 | int rem = ringbuf->size - ringbuf->tail; |
3e960501 | 2342 | |
93b0a4e0 | 2343 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
2344 | rem /= 4; |
2345 | while (rem--) | |
2346 | iowrite32(MI_NOOP, virt++); | |
2347 | ||
93b0a4e0 | 2348 | ringbuf->tail = 0; |
ebd0fd4b | 2349 | intel_ring_update_space(ringbuf); |
3e960501 CW |
2350 | } |
2351 | ||
666796da | 2352 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2353 | { |
a4b3a571 | 2354 | struct drm_i915_gem_request *req; |
3e960501 | 2355 | |
3e960501 | 2356 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2357 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2358 | return 0; |
2359 | ||
0bc40be8 TU |
2360 | req = list_entry(engine->request_list.prev, |
2361 | struct drm_i915_gem_request, | |
2362 | list); | |
b4716185 CW |
2363 | |
2364 | /* Make sure we do not trigger any retires */ | |
2365 | return __i915_wait_request(req, | |
0bc40be8 TU |
2366 | atomic_read(&to_i915(engine->dev)->gpu_error.reset_counter), |
2367 | to_i915(engine->dev)->mm.interruptible, | |
b4716185 | 2368 | NULL, NULL); |
3e960501 CW |
2369 | } |
2370 | ||
6689cb2b | 2371 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2372 | { |
4a570db5 | 2373 | request->ringbuf = request->engine->buffer; |
9eba5d4a | 2374 | return 0; |
9d773091 CW |
2375 | } |
2376 | ||
ccd98fe4 JH |
2377 | int intel_ring_reserve_space(struct drm_i915_gem_request *request) |
2378 | { | |
2379 | /* | |
2380 | * The first call merely notes the reserve request and is common for | |
2381 | * all back ends. The subsequent localised _begin() call actually | |
2382 | * ensures that the reservation is available. Without the begin, if | |
2383 | * the request creator immediately submitted the request without | |
2384 | * adding any commands to it then there might not actually be | |
2385 | * sufficient room for the submission commands. | |
2386 | */ | |
2387 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
2388 | ||
2389 | return intel_ring_begin(request, 0); | |
2390 | } | |
2391 | ||
29b1b415 JH |
2392 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size) |
2393 | { | |
ccd98fe4 | 2394 | WARN_ON(ringbuf->reserved_size); |
29b1b415 JH |
2395 | WARN_ON(ringbuf->reserved_in_use); |
2396 | ||
2397 | ringbuf->reserved_size = size; | |
29b1b415 JH |
2398 | } |
2399 | ||
2400 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf) | |
2401 | { | |
2402 | WARN_ON(ringbuf->reserved_in_use); | |
2403 | ||
2404 | ringbuf->reserved_size = 0; | |
2405 | ringbuf->reserved_in_use = false; | |
2406 | } | |
2407 | ||
2408 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf) | |
2409 | { | |
2410 | WARN_ON(ringbuf->reserved_in_use); | |
2411 | ||
2412 | ringbuf->reserved_in_use = true; | |
2413 | ringbuf->reserved_tail = ringbuf->tail; | |
2414 | } | |
2415 | ||
2416 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf) | |
2417 | { | |
2418 | WARN_ON(!ringbuf->reserved_in_use); | |
79bbcc29 JH |
2419 | if (ringbuf->tail > ringbuf->reserved_tail) { |
2420 | WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size, | |
2421 | "request reserved size too small: %d vs %d!\n", | |
2422 | ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size); | |
2423 | } else { | |
2424 | /* | |
2425 | * The ring was wrapped while the reserved space was in use. | |
2426 | * That means that some unknown amount of the ring tail was | |
2427 | * no-op filled and skipped. Thus simply adding the ring size | |
2428 | * to the tail and doing the above space check will not work. | |
2429 | * Rather than attempt to track how much tail was skipped, | |
2430 | * it is much simpler to say that also skipping the sanity | |
2431 | * check every once in a while is not a big issue. | |
2432 | */ | |
2433 | } | |
29b1b415 JH |
2434 | |
2435 | ringbuf->reserved_size = 0; | |
2436 | ringbuf->reserved_in_use = false; | |
2437 | } | |
2438 | ||
0bc40be8 | 2439 | static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes) |
cbcc80df | 2440 | { |
0bc40be8 | 2441 | struct intel_ringbuffer *ringbuf = engine->buffer; |
79bbcc29 JH |
2442 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2443 | int remain_actual = ringbuf->size - ringbuf->tail; | |
2444 | int ret, total_bytes, wait_bytes = 0; | |
2445 | bool need_wrap = false; | |
29b1b415 | 2446 | |
79bbcc29 JH |
2447 | if (ringbuf->reserved_in_use) |
2448 | total_bytes = bytes; | |
2449 | else | |
2450 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 2451 | |
79bbcc29 JH |
2452 | if (unlikely(bytes > remain_usable)) { |
2453 | /* | |
2454 | * Not enough space for the basic request. So need to flush | |
2455 | * out the remainder and then wait for base + reserved. | |
2456 | */ | |
2457 | wait_bytes = remain_actual + total_bytes; | |
2458 | need_wrap = true; | |
2459 | } else { | |
2460 | if (unlikely(total_bytes > remain_usable)) { | |
2461 | /* | |
2462 | * The base request will fit but the reserved space | |
782f6bc0 AG |
2463 | * falls off the end. So don't need an immediate wrap |
2464 | * and only need to effectively wait for the reserved | |
2465 | * size space from the start of ringbuffer. | |
79bbcc29 JH |
2466 | */ |
2467 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
79bbcc29 JH |
2468 | } else if (total_bytes > ringbuf->space) { |
2469 | /* No wrapping required, just waiting. */ | |
2470 | wait_bytes = total_bytes; | |
29b1b415 | 2471 | } |
cbcc80df MK |
2472 | } |
2473 | ||
79bbcc29 | 2474 | if (wait_bytes) { |
0bc40be8 | 2475 | ret = ring_wait_for_space(engine, wait_bytes); |
cbcc80df MK |
2476 | if (unlikely(ret)) |
2477 | return ret; | |
79bbcc29 JH |
2478 | |
2479 | if (need_wrap) | |
2480 | __wrap_ring_buffer(ringbuf); | |
cbcc80df MK |
2481 | } |
2482 | ||
cbcc80df MK |
2483 | return 0; |
2484 | } | |
2485 | ||
5fb9de1a | 2486 | int intel_ring_begin(struct drm_i915_gem_request *req, |
e1f99ce6 | 2487 | int num_dwords) |
8187a2b7 | 2488 | { |
e2f80391 | 2489 | struct intel_engine_cs *engine; |
5fb9de1a | 2490 | struct drm_i915_private *dev_priv; |
e1f99ce6 | 2491 | int ret; |
78501eac | 2492 | |
5fb9de1a | 2493 | WARN_ON(req == NULL); |
4a570db5 | 2494 | engine = req->engine; |
39dabecd | 2495 | dev_priv = req->i915; |
5fb9de1a | 2496 | |
33196ded DV |
2497 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2498 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2499 | if (ret) |
2500 | return ret; | |
21dd3734 | 2501 | |
e2f80391 | 2502 | ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t)); |
304d695c CW |
2503 | if (ret) |
2504 | return ret; | |
2505 | ||
e2f80391 | 2506 | engine->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2507 | return 0; |
8187a2b7 | 2508 | } |
78501eac | 2509 | |
753b1ad4 | 2510 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2511 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2512 | { |
4a570db5 | 2513 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2514 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2515 | int ret; |
2516 | ||
2517 | if (num_dwords == 0) | |
2518 | return 0; | |
2519 | ||
18393f63 | 2520 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2521 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2522 | if (ret) |
2523 | return ret; | |
2524 | ||
2525 | while (num_dwords--) | |
e2f80391 | 2526 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2527 | |
e2f80391 | 2528 | intel_ring_advance(engine); |
753b1ad4 VS |
2529 | |
2530 | return 0; | |
2531 | } | |
2532 | ||
0bc40be8 | 2533 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2534 | { |
d04bce48 | 2535 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
498d2ac1 | 2536 | |
29dcb570 CW |
2537 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2538 | * so long as the semaphore value in the register/page is greater | |
2539 | * than the sync value), so whenever we reset the seqno, | |
2540 | * so long as we reset the tracking semaphore value to 0, it will | |
2541 | * always be before the next request's seqno. If we don't reset | |
2542 | * the semaphore value, then when the seqno moves backwards all | |
2543 | * future waits will complete instantly (causing rendering corruption). | |
2544 | */ | |
d04bce48 | 2545 | if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { |
0bc40be8 TU |
2546 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2547 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2548 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2549 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2550 | } |
a058d934 CW |
2551 | if (dev_priv->semaphore_obj) { |
2552 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2553 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2554 | void *semaphores = kmap(page); | |
2555 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2556 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2557 | kunmap(page); | |
2558 | } | |
29dcb570 CW |
2559 | memset(engine->semaphore.sync_seqno, 0, |
2560 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2561 | |
0bc40be8 | 2562 | engine->set_seqno(engine, seqno); |
01347126 | 2563 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2564 | |
0bc40be8 | 2565 | engine->hangcheck.seqno = seqno; |
8187a2b7 | 2566 | } |
62fdfeaf | 2567 | |
0bc40be8 | 2568 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2569 | u32 value) |
881f47b6 | 2570 | { |
0bc40be8 | 2571 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
881f47b6 XH |
2572 | |
2573 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2574 | |
2575 | /* Disable notification that the ring is IDLE. The GT | |
2576 | * will then assume that it is busy and bring it out of rc6. | |
2577 | */ | |
0206e353 | 2578 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2579 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2580 | ||
2581 | /* Clear the context id. Here be magic! */ | |
2582 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2583 | |
12f55818 | 2584 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2585 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2586 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2587 | 50)) | |
2588 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2589 | |
12f55818 | 2590 | /* Now that the ring is fully powered up, update the tail */ |
0bc40be8 TU |
2591 | I915_WRITE_TAIL(engine, value); |
2592 | POSTING_READ(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2593 | |
2594 | /* Let the ring send IDLE messages to the GT again, | |
2595 | * and so let it sleep to conserve power when idle. | |
2596 | */ | |
0206e353 | 2597 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2598 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2599 | } |
2600 | ||
a84c3ae1 | 2601 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2602 | u32 invalidate, u32 flush) |
881f47b6 | 2603 | { |
4a570db5 | 2604 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2605 | uint32_t cmd; |
b72f3acb CW |
2606 | int ret; |
2607 | ||
5fb9de1a | 2608 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2609 | if (ret) |
2610 | return ret; | |
2611 | ||
71a77e07 | 2612 | cmd = MI_FLUSH_DW; |
e2f80391 | 2613 | if (INTEL_INFO(engine->dev)->gen >= 8) |
075b3bba | 2614 | cmd += 1; |
f0a1fb10 CW |
2615 | |
2616 | /* We always require a command barrier so that subsequent | |
2617 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2618 | * wrt the contents of the write cache being flushed to memory | |
2619 | * (and thus being coherent from the CPU). | |
2620 | */ | |
2621 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2622 | ||
9a289771 JB |
2623 | /* |
2624 | * Bspec vol 1c.5 - video engine command streamer: | |
2625 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2626 | * operation is complete. This bit is only valid when the | |
2627 | * Post-Sync Operation field is a value of 1h or 3h." | |
2628 | */ | |
71a77e07 | 2629 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2630 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2631 | ||
e2f80391 TU |
2632 | intel_ring_emit(engine, cmd); |
2633 | intel_ring_emit(engine, | |
2634 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
2635 | if (INTEL_INFO(engine->dev)->gen >= 8) { | |
2636 | intel_ring_emit(engine, 0); /* upper addr */ | |
2637 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2638 | } else { |
e2f80391 TU |
2639 | intel_ring_emit(engine, 0); |
2640 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2641 | } |
e2f80391 | 2642 | intel_ring_advance(engine); |
b72f3acb | 2643 | return 0; |
881f47b6 XH |
2644 | } |
2645 | ||
1c7a0623 | 2646 | static int |
53fddaf7 | 2647 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2648 | u64 offset, u32 len, |
8e004efc | 2649 | unsigned dispatch_flags) |
1c7a0623 | 2650 | { |
4a570db5 | 2651 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2652 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2653 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2654 | int ret; |
2655 | ||
5fb9de1a | 2656 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2657 | if (ret) |
2658 | return ret; | |
2659 | ||
2660 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2661 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2662 | (dispatch_flags & I915_DISPATCH_RS ? |
2663 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2664 | intel_ring_emit(engine, lower_32_bits(offset)); |
2665 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2666 | intel_ring_emit(engine, MI_NOOP); | |
2667 | intel_ring_advance(engine); | |
1c7a0623 BW |
2668 | |
2669 | return 0; | |
2670 | } | |
2671 | ||
d7d4eedd | 2672 | static int |
53fddaf7 | 2673 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2674 | u64 offset, u32 len, |
2675 | unsigned dispatch_flags) | |
d7d4eedd | 2676 | { |
4a570db5 | 2677 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2678 | int ret; |
2679 | ||
5fb9de1a | 2680 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2681 | if (ret) |
2682 | return ret; | |
2683 | ||
e2f80391 | 2684 | intel_ring_emit(engine, |
77072258 | 2685 | MI_BATCH_BUFFER_START | |
8e004efc | 2686 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2687 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2688 | (dispatch_flags & I915_DISPATCH_RS ? | |
2689 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2690 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2691 | intel_ring_emit(engine, offset); |
2692 | intel_ring_advance(engine); | |
d7d4eedd CW |
2693 | |
2694 | return 0; | |
2695 | } | |
2696 | ||
881f47b6 | 2697 | static int |
53fddaf7 | 2698 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2699 | u64 offset, u32 len, |
8e004efc | 2700 | unsigned dispatch_flags) |
881f47b6 | 2701 | { |
4a570db5 | 2702 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2703 | int ret; |
ab6f8e32 | 2704 | |
5fb9de1a | 2705 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2706 | if (ret) |
2707 | return ret; | |
e1f99ce6 | 2708 | |
e2f80391 | 2709 | intel_ring_emit(engine, |
d7d4eedd | 2710 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2711 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2712 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2713 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2714 | intel_ring_emit(engine, offset); |
2715 | intel_ring_advance(engine); | |
ab6f8e32 | 2716 | |
0206e353 | 2717 | return 0; |
881f47b6 XH |
2718 | } |
2719 | ||
549f7365 CW |
2720 | /* Blitter support (SandyBridge+) */ |
2721 | ||
a84c3ae1 | 2722 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2723 | u32 invalidate, u32 flush) |
8d19215b | 2724 | { |
4a570db5 | 2725 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2726 | struct drm_device *dev = engine->dev; |
71a77e07 | 2727 | uint32_t cmd; |
b72f3acb CW |
2728 | int ret; |
2729 | ||
5fb9de1a | 2730 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2731 | if (ret) |
2732 | return ret; | |
2733 | ||
71a77e07 | 2734 | cmd = MI_FLUSH_DW; |
dbef0f15 | 2735 | if (INTEL_INFO(dev)->gen >= 8) |
075b3bba | 2736 | cmd += 1; |
f0a1fb10 CW |
2737 | |
2738 | /* We always require a command barrier so that subsequent | |
2739 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2740 | * wrt the contents of the write cache being flushed to memory | |
2741 | * (and thus being coherent from the CPU). | |
2742 | */ | |
2743 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2744 | ||
9a289771 JB |
2745 | /* |
2746 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2747 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2748 | * operation is complete. This bit is only valid when the | |
2749 | * Post-Sync Operation field is a value of 1h or 3h." | |
2750 | */ | |
71a77e07 | 2751 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2752 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2753 | intel_ring_emit(engine, cmd); |
2754 | intel_ring_emit(engine, | |
2755 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
dbef0f15 | 2756 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 TU |
2757 | intel_ring_emit(engine, 0); /* upper addr */ |
2758 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2759 | } else { |
e2f80391 TU |
2760 | intel_ring_emit(engine, 0); |
2761 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2762 | } |
e2f80391 | 2763 | intel_ring_advance(engine); |
fd3da6c9 | 2764 | |
b72f3acb | 2765 | return 0; |
8d19215b ZN |
2766 | } |
2767 | ||
5c1143bb XH |
2768 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2769 | { | |
4640c4ff | 2770 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2771 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
2772 | struct drm_i915_gem_object *obj; |
2773 | int ret; | |
5c1143bb | 2774 | |
e2f80391 TU |
2775 | engine->name = "render ring"; |
2776 | engine->id = RCS; | |
2777 | engine->exec_id = I915_EXEC_RENDER; | |
2778 | engine->mmio_base = RENDER_RING_BASE; | |
59465b5f | 2779 | |
707d9cf9 | 2780 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2781 | if (i915_semaphore_is_enabled(dev)) { |
2782 | obj = i915_gem_alloc_object(dev, 4096); | |
2783 | if (obj == NULL) { | |
2784 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2785 | i915.semaphores = 0; | |
2786 | } else { | |
2787 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2788 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2789 | if (ret != 0) { | |
2790 | drm_gem_object_unreference(&obj->base); | |
2791 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2792 | i915.semaphores = 0; | |
2793 | } else | |
2794 | dev_priv->semaphore_obj = obj; | |
2795 | } | |
2796 | } | |
7225342a | 2797 | |
e2f80391 TU |
2798 | engine->init_context = intel_rcs_ctx_init; |
2799 | engine->add_request = gen6_add_request; | |
2800 | engine->flush = gen8_render_ring_flush; | |
2801 | engine->irq_get = gen8_ring_get_irq; | |
2802 | engine->irq_put = gen8_ring_put_irq; | |
2803 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2804 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2805 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2806 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2807 | if (i915_semaphore_is_enabled(dev)) { |
3e78998a | 2808 | WARN_ON(!dev_priv->semaphore_obj); |
e2f80391 TU |
2809 | engine->semaphore.sync_to = gen8_ring_sync; |
2810 | engine->semaphore.signal = gen8_rcs_signal; | |
2811 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 BW |
2812 | } |
2813 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
e2f80391 TU |
2814 | engine->init_context = intel_rcs_ctx_init; |
2815 | engine->add_request = gen6_add_request; | |
2816 | engine->flush = gen7_render_ring_flush; | |
6c6cf5aa | 2817 | if (INTEL_INFO(dev)->gen == 6) |
e2f80391 TU |
2818 | engine->flush = gen6_render_ring_flush; |
2819 | engine->irq_get = gen6_ring_get_irq; | |
2820 | engine->irq_put = gen6_ring_put_irq; | |
2821 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2822 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2823 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2824 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2825 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2826 | engine->semaphore.sync_to = gen6_ring_sync; |
2827 | engine->semaphore.signal = gen6_signal; | |
707d9cf9 BW |
2828 | /* |
2829 | * The current semaphore is only applied on pre-gen8 | |
2830 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2831 | * platform. So the semaphore between RCS and VCS2 is | |
2832 | * initialized as INVALID. Gen8 will initialize the | |
2833 | * sema between VCS2 and RCS later. | |
2834 | */ | |
e2f80391 TU |
2835 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
2836 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2837 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2838 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2839 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2840 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2841 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2842 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2843 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2844 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2845 | } |
c6df541c | 2846 | } else if (IS_GEN5(dev)) { |
e2f80391 TU |
2847 | engine->add_request = pc_render_add_request; |
2848 | engine->flush = gen4_render_ring_flush; | |
2849 | engine->get_seqno = pc_render_get_seqno; | |
2850 | engine->set_seqno = pc_render_set_seqno; | |
2851 | engine->irq_get = gen5_ring_get_irq; | |
2852 | engine->irq_put = gen5_ring_put_irq; | |
2853 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | | |
cc609d5d | 2854 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 2855 | } else { |
e2f80391 | 2856 | engine->add_request = i9xx_add_request; |
46f0f8d1 | 2857 | if (INTEL_INFO(dev)->gen < 4) |
e2f80391 | 2858 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2859 | else |
e2f80391 TU |
2860 | engine->flush = gen4_render_ring_flush; |
2861 | engine->get_seqno = ring_get_seqno; | |
2862 | engine->set_seqno = ring_set_seqno; | |
c2798b19 | 2863 | if (IS_GEN2(dev)) { |
e2f80391 TU |
2864 | engine->irq_get = i8xx_ring_get_irq; |
2865 | engine->irq_put = i8xx_ring_put_irq; | |
c2798b19 | 2866 | } else { |
e2f80391 TU |
2867 | engine->irq_get = i9xx_ring_get_irq; |
2868 | engine->irq_put = i9xx_ring_put_irq; | |
c2798b19 | 2869 | } |
e2f80391 | 2870 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2871 | } |
e2f80391 | 2872 | engine->write_tail = ring_write_tail; |
707d9cf9 | 2873 | |
d7d4eedd | 2874 | if (IS_HASWELL(dev)) |
e2f80391 | 2875 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
1c7a0623 | 2876 | else if (IS_GEN8(dev)) |
e2f80391 | 2877 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
d7d4eedd | 2878 | else if (INTEL_INFO(dev)->gen >= 6) |
e2f80391 | 2879 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
fb3256da | 2880 | else if (INTEL_INFO(dev)->gen >= 4) |
e2f80391 | 2881 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
fb3256da | 2882 | else if (IS_I830(dev) || IS_845G(dev)) |
e2f80391 | 2883 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
fb3256da | 2884 | else |
e2f80391 TU |
2885 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
2886 | engine->init_hw = init_render_ring; | |
2887 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2888 | |
b45305fc DV |
2889 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2890 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2891 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2892 | if (obj == NULL) { |
2893 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2894 | return -ENOMEM; | |
2895 | } | |
2896 | ||
be1fa129 | 2897 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2898 | if (ret != 0) { |
2899 | drm_gem_object_unreference(&obj->base); | |
2900 | DRM_ERROR("Failed to ping batch bo\n"); | |
2901 | return ret; | |
2902 | } | |
2903 | ||
e2f80391 TU |
2904 | engine->scratch.obj = obj; |
2905 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2906 | } |
2907 | ||
e2f80391 | 2908 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
2909 | if (ret) |
2910 | return ret; | |
2911 | ||
2912 | if (INTEL_INFO(dev)->gen >= 5) { | |
e2f80391 | 2913 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2914 | if (ret) |
2915 | return ret; | |
2916 | } | |
2917 | ||
2918 | return 0; | |
5c1143bb XH |
2919 | } |
2920 | ||
2921 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2922 | { | |
4640c4ff | 2923 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2924 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 2925 | |
e2f80391 TU |
2926 | engine->name = "bsd ring"; |
2927 | engine->id = VCS; | |
2928 | engine->exec_id = I915_EXEC_BSD; | |
58fa3835 | 2929 | |
e2f80391 | 2930 | engine->write_tail = ring_write_tail; |
780f18c8 | 2931 | if (INTEL_INFO(dev)->gen >= 6) { |
e2f80391 | 2932 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2933 | /* gen6 bsd needs a special wa for tail updates */ |
2934 | if (IS_GEN6(dev)) | |
e2f80391 TU |
2935 | engine->write_tail = gen6_bsd_ring_write_tail; |
2936 | engine->flush = gen6_bsd_ring_flush; | |
2937 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2938 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2939 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2940 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 2941 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 2942 | engine->irq_enable_mask = |
abd58f01 | 2943 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
e2f80391 TU |
2944 | engine->irq_get = gen8_ring_get_irq; |
2945 | engine->irq_put = gen8_ring_put_irq; | |
2946 | engine->dispatch_execbuffer = | |
1c7a0623 | 2947 | gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2948 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2949 | engine->semaphore.sync_to = gen8_ring_sync; |
2950 | engine->semaphore.signal = gen8_xcs_signal; | |
2951 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 2952 | } |
abd58f01 | 2953 | } else { |
e2f80391 TU |
2954 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
2955 | engine->irq_get = gen6_ring_get_irq; | |
2956 | engine->irq_put = gen6_ring_put_irq; | |
2957 | engine->dispatch_execbuffer = | |
1c7a0623 | 2958 | gen6_ring_dispatch_execbuffer; |
707d9cf9 | 2959 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2960 | engine->semaphore.sync_to = gen6_ring_sync; |
2961 | engine->semaphore.signal = gen6_signal; | |
2962 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2963 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2964 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2965 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2966 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2967 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2968 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2969 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2970 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2971 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2972 | } |
abd58f01 | 2973 | } |
58fa3835 | 2974 | } else { |
e2f80391 TU |
2975 | engine->mmio_base = BSD_RING_BASE; |
2976 | engine->flush = bsd_ring_flush; | |
2977 | engine->add_request = i9xx_add_request; | |
2978 | engine->get_seqno = ring_get_seqno; | |
2979 | engine->set_seqno = ring_set_seqno; | |
e48d8634 | 2980 | if (IS_GEN5(dev)) { |
e2f80391 TU |
2981 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
2982 | engine->irq_get = gen5_ring_get_irq; | |
2983 | engine->irq_put = gen5_ring_put_irq; | |
e48d8634 | 2984 | } else { |
e2f80391 TU |
2985 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
2986 | engine->irq_get = i9xx_ring_get_irq; | |
2987 | engine->irq_put = i9xx_ring_put_irq; | |
e48d8634 | 2988 | } |
e2f80391 | 2989 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2990 | } |
e2f80391 | 2991 | engine->init_hw = init_ring_common; |
58fa3835 | 2992 | |
e2f80391 | 2993 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 2994 | } |
549f7365 | 2995 | |
845f74a7 | 2996 | /** |
62659920 | 2997 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
2998 | */ |
2999 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
3000 | { | |
3001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 3002 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
3003 | |
3004 | engine->name = "bsd2 ring"; | |
3005 | engine->id = VCS2; | |
3006 | engine->exec_id = I915_EXEC_BSD; | |
3007 | ||
3008 | engine->write_tail = ring_write_tail; | |
3009 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
3010 | engine->flush = gen6_bsd_ring_flush; | |
3011 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3012 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3013 | engine->get_seqno = ring_get_seqno; | |
e2f80391 TU |
3014 | engine->set_seqno = ring_set_seqno; |
3015 | engine->irq_enable_mask = | |
845f74a7 | 3016 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
e2f80391 TU |
3017 | engine->irq_get = gen8_ring_get_irq; |
3018 | engine->irq_put = gen8_ring_put_irq; | |
3019 | engine->dispatch_execbuffer = | |
845f74a7 | 3020 | gen8_ring_dispatch_execbuffer; |
3e78998a | 3021 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3022 | engine->semaphore.sync_to = gen8_ring_sync; |
3023 | engine->semaphore.signal = gen8_xcs_signal; | |
3024 | GEN8_RING_SEMAPHORE_INIT(engine); | |
3e78998a | 3025 | } |
e2f80391 | 3026 | engine->init_hw = init_ring_common; |
845f74a7 | 3027 | |
e2f80391 | 3028 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
3029 | } |
3030 | ||
549f7365 CW |
3031 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
3032 | { | |
4640c4ff | 3033 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3034 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
3035 | |
3036 | engine->name = "blitter ring"; | |
3037 | engine->id = BCS; | |
3038 | engine->exec_id = I915_EXEC_BLT; | |
3039 | ||
3040 | engine->mmio_base = BLT_RING_BASE; | |
3041 | engine->write_tail = ring_write_tail; | |
3042 | engine->flush = gen6_ring_flush; | |
3043 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3044 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3045 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3046 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 3047 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 3048 | engine->irq_enable_mask = |
abd58f01 | 3049 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
e2f80391 TU |
3050 | engine->irq_get = gen8_ring_get_irq; |
3051 | engine->irq_put = gen8_ring_put_irq; | |
3052 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3053 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3054 | engine->semaphore.sync_to = gen8_ring_sync; |
3055 | engine->semaphore.signal = gen8_xcs_signal; | |
3056 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3057 | } |
abd58f01 | 3058 | } else { |
e2f80391 TU |
3059 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3060 | engine->irq_get = gen6_ring_get_irq; | |
3061 | engine->irq_put = gen6_ring_put_irq; | |
3062 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3063 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3064 | engine->semaphore.signal = gen6_signal; |
3065 | engine->semaphore.sync_to = gen6_ring_sync; | |
707d9cf9 BW |
3066 | /* |
3067 | * The current semaphore is only applied on pre-gen8 | |
3068 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3069 | * platform. So the semaphore between BCS and VCS2 is | |
3070 | * initialized as INVALID. Gen8 will initialize the | |
3071 | * sema between BCS and VCS2 later. | |
3072 | */ | |
e2f80391 TU |
3073 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
3074 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
3075 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3076 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
3077 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3078 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
3079 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
3080 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
3081 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
3082 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3083 | } |
abd58f01 | 3084 | } |
e2f80391 | 3085 | engine->init_hw = init_ring_common; |
549f7365 | 3086 | |
e2f80391 | 3087 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3088 | } |
a7b9761d | 3089 | |
9a8a2213 BW |
3090 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3091 | { | |
4640c4ff | 3092 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3093 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3094 | |
e2f80391 TU |
3095 | engine->name = "video enhancement ring"; |
3096 | engine->id = VECS; | |
3097 | engine->exec_id = I915_EXEC_VEBOX; | |
9a8a2213 | 3098 | |
e2f80391 TU |
3099 | engine->mmio_base = VEBOX_RING_BASE; |
3100 | engine->write_tail = ring_write_tail; | |
3101 | engine->flush = gen6_ring_flush; | |
3102 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3103 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3104 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3105 | engine->set_seqno = ring_set_seqno; |
abd58f01 BW |
3106 | |
3107 | if (INTEL_INFO(dev)->gen >= 8) { | |
e2f80391 | 3108 | engine->irq_enable_mask = |
40c499f9 | 3109 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
e2f80391 TU |
3110 | engine->irq_get = gen8_ring_get_irq; |
3111 | engine->irq_put = gen8_ring_put_irq; | |
3112 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3113 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3114 | engine->semaphore.sync_to = gen8_ring_sync; |
3115 | engine->semaphore.signal = gen8_xcs_signal; | |
3116 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3117 | } |
abd58f01 | 3118 | } else { |
e2f80391 TU |
3119 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3120 | engine->irq_get = hsw_vebox_get_irq; | |
3121 | engine->irq_put = hsw_vebox_put_irq; | |
3122 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3123 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3124 | engine->semaphore.sync_to = gen6_ring_sync; |
3125 | engine->semaphore.signal = gen6_signal; | |
3126 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
3127 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3128 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3129 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3130 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3131 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3132 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3133 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3134 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3135 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3136 | } |
abd58f01 | 3137 | } |
e2f80391 | 3138 | engine->init_hw = init_ring_common; |
9a8a2213 | 3139 | |
e2f80391 | 3140 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3141 | } |
3142 | ||
a7b9761d | 3143 | int |
4866d729 | 3144 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3145 | { |
4a570db5 | 3146 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3147 | int ret; |
3148 | ||
e2f80391 | 3149 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3150 | return 0; |
3151 | ||
e2f80391 | 3152 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3153 | if (ret) |
3154 | return ret; | |
3155 | ||
a84c3ae1 | 3156 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3157 | |
e2f80391 | 3158 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3159 | return 0; |
3160 | } | |
3161 | ||
3162 | int | |
2f20055d | 3163 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3164 | { |
4a570db5 | 3165 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3166 | uint32_t flush_domains; |
3167 | int ret; | |
3168 | ||
3169 | flush_domains = 0; | |
e2f80391 | 3170 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3171 | flush_domains = I915_GEM_GPU_DOMAINS; |
3172 | ||
e2f80391 | 3173 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3174 | if (ret) |
3175 | return ret; | |
3176 | ||
a84c3ae1 | 3177 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3178 | |
e2f80391 | 3179 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3180 | return 0; |
3181 | } | |
e3efda49 CW |
3182 | |
3183 | void | |
117897f4 | 3184 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3185 | { |
3186 | int ret; | |
3187 | ||
117897f4 | 3188 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3189 | return; |
3190 | ||
666796da | 3191 | ret = intel_engine_idle(engine); |
0bc40be8 | 3192 | if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error)) |
e3efda49 | 3193 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3194 | engine->name, ret); |
e3efda49 | 3195 | |
0bc40be8 | 3196 | stop_ring(engine); |
e3efda49 | 3197 | } |