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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
c7dca47b
CW		 36static inline int ring_space(struct intel_ring_buffer *ring)
37{
633cf8f5 38 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
c7dca47b
CW		 39 if (space < 0)
40 space += ring->size;
41 return space;
42}
43
b72f3acb 44static int
46f0f8d1
CW		 45gen2_render_ring_flush(struct intel_ring_buffer *ring,
46 u32 invalidate_domains,
47 u32 flush_domains)
48{
49 u32 cmd;
50 int ret;
51
52 cmd = MI_FLUSH;
31b14c9f 53 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 54 cmd |= MI_NO_WRITE_FLUSH;
55
56 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
57 cmd |= MI_READ_FLUSH;
58
59 ret = intel_ring_begin(ring, 2);
60 if (ret)
61 return ret;
62
63 intel_ring_emit(ring, cmd);
64 intel_ring_emit(ring, MI_NOOP);
65 intel_ring_advance(ring);
66
67 return 0;
68}
69
70static int
71gen4_render_ring_flush(struct intel_ring_buffer *ring,
72 u32 invalidate_domains,
73 u32 flush_domains)
62fdfeaf 74{
78501eac 75 struct drm_device *dev = ring->dev;
6f392d54 76 u32 cmd;
b72f3acb 77 int ret;
6f392d54 78
36d527de
CW		 79 /*
80 * read/write caches:
81 *
82 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
83 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
84 * also flushed at 2d versus 3d pipeline switches.
85 *
86 * read-only caches:
87 *
88 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
89 * MI_READ_FLUSH is set, and is always flushed on 965.
90 *
91 * I915_GEM_DOMAIN_COMMAND may not exist?
92 *
93 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
94 * invalidated when MI_EXE_FLUSH is set.
95 *
96 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
97 * invalidated with every MI_FLUSH.
98 *
99 * TLBs:
100 *
101 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
102 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
103 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
104 * are flushed at any MI_FLUSH.
105 */
106
107 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 108 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 109 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 110 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
111 cmd |= MI_EXE_FLUSH;
62fdfeaf 112
36d527de
CW		 113 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
114 (IS_G4X(dev) || IS_GEN5(dev)))
115 cmd |= MI_INVALIDATE_ISP;
70eac33e 116
36d527de
CW		 117 ret = intel_ring_begin(ring, 2);
118 if (ret)
119 return ret;
b72f3acb 120
36d527de
CW		 121 intel_ring_emit(ring, cmd);
122 intel_ring_emit(ring, MI_NOOP);
123 intel_ring_advance(ring);
b72f3acb
CW		 124
125 return 0;
8187a2b7
ZN		 126}
127
8d315287
JB		 128/**
129 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
130 * implementing two workarounds on gen6. From section 1.4.7.1
131 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
132 *
133 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
134 * produced by non-pipelined state commands), software needs to first
135 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
136 * 0.
137 *
138 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
139 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
140 *
141 * And the workaround for these two requires this workaround first:
142 *
143 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
144 * BEFORE the pipe-control with a post-sync op and no write-cache
145 * flushes.
146 *
147 * And this last workaround is tricky because of the requirements on
148 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
149 * volume 2 part 1:
150 *
151 * "1 of the following must also be set:
152 * - Render Target Cache Flush Enable ([12] of DW1)
153 * - Depth Cache Flush Enable ([0] of DW1)
154 * - Stall at Pixel Scoreboard ([1] of DW1)
155 * - Depth Stall ([13] of DW1)
156 * - Post-Sync Operation ([13] of DW1)
157 * - Notify Enable ([8] of DW1)"
158 *
159 * The cache flushes require the workaround flush that triggered this
160 * one, so we can't use it. Depth stall would trigger the same.
161 * Post-sync nonzero is what triggered this second workaround, so we
162 * can't use that one either. Notify enable is IRQs, which aren't
163 * really our business. That leaves only stall at scoreboard.
164 */
165static int
166intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
167{
0d1aacac 168 u32 scratch_addr = ring->scratch.gtt_offset + 128;
8d315287
JB		 169 int ret;
170
171
172 ret = intel_ring_begin(ring, 6);
173 if (ret)
174 return ret;
175
176 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
177 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
178 PIPE_CONTROL_STALL_AT_SCOREBOARD);
179 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
180 intel_ring_emit(ring, 0); /* low dword */
181 intel_ring_emit(ring, 0); /* high dword */
182 intel_ring_emit(ring, MI_NOOP);
183 intel_ring_advance(ring);
184
185 ret = intel_ring_begin(ring, 6);
186 if (ret)
187 return ret;
188
189 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
190 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0);
193 intel_ring_emit(ring, 0);
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 return 0;
198}
199
200static int
201gen6_render_ring_flush(struct intel_ring_buffer *ring,
202 u32 invalidate_domains, u32 flush_domains)
203{
204 u32 flags = 0;
0d1aacac 205 u32 scratch_addr = ring->scratch.gtt_offset + 128;
8d315287
JB		 206 int ret;
207
b3111509
PZ		 208 /* Force SNB workarounds for PIPE_CONTROL flushes */
209 ret = intel_emit_post_sync_nonzero_flush(ring);
210 if (ret)
211 return ret;
212
8d315287
JB		 213 /* Just flush everything. Experiments have shown that reducing the
214 * number of bits based on the write domains has little performance
215 * impact.
216 */
7d54a904
CW		 217 if (flush_domains) {
218 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
219 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
220 /*
221 * Ensure that any following seqno writes only happen
222 * when the render cache is indeed flushed.
223 */
97f209bc 224 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 225 }
226 if (invalidate_domains) {
227 flags |= PIPE_CONTROL_TLB_INVALIDATE;
228 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
229 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
232 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
233 /*
234 * TLB invalidate requires a post-sync write.
235 */
3ac78313 236 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 237 }
8d315287 238
6c6cf5aa 239 ret = intel_ring_begin(ring, 4);
8d315287
JB		 240 if (ret)
241 return ret;
242
6c6cf5aa 243 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 244 intel_ring_emit(ring, flags);
245 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 246 intel_ring_emit(ring, 0);
8d315287
JB		 247 intel_ring_advance(ring);
248
249 return 0;
250}
251
f3987631
PZ		 252static int
253gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
254{
255 int ret;
256
257 ret = intel_ring_begin(ring, 4);
258 if (ret)
259 return ret;
260
261 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
262 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
263 PIPE_CONTROL_STALL_AT_SCOREBOARD);
264 intel_ring_emit(ring, 0);
265 intel_ring_emit(ring, 0);
266 intel_ring_advance(ring);
267
268 return 0;
269}
270
fd3da6c9
RV		 271static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
272{
273 int ret;
274
275 if (!ring->fbc_dirty)
276 return 0;
277
278 ret = intel_ring_begin(ring, 4);
279 if (ret)
280 return ret;
281 intel_ring_emit(ring, MI_NOOP);
282 /* WaFbcNukeOn3DBlt:ivb/hsw */
283 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
284 intel_ring_emit(ring, MSG_FBC_REND_STATE);
285 intel_ring_emit(ring, value);
286 intel_ring_advance(ring);
287
288 ring->fbc_dirty = false;
289 return 0;
290}
291
4772eaeb
PZ		 292static int
293gen7_render_ring_flush(struct intel_ring_buffer *ring,
294 u32 invalidate_domains, u32 flush_domains)
295{
296 u32 flags = 0;
0d1aacac 297 u32 scratch_addr = ring->scratch.gtt_offset + 128;
4772eaeb
PZ		 298 int ret;
299
f3987631
PZ		 300 /*
301 * Ensure that any following seqno writes only happen when the render
302 * cache is indeed flushed.
303 *
304 * Workaround: 4th PIPE_CONTROL command (except the ones with only
305 * read-cache invalidate bits set) must have the CS_STALL bit set. We
306 * don't try to be clever and just set it unconditionally.
307 */
308 flags |= PIPE_CONTROL_CS_STALL;
309
4772eaeb
PZ		 310 /* Just flush everything. Experiments have shown that reducing the
311 * number of bits based on the write domains has little performance
312 * impact.
313 */
314 if (flush_domains) {
315 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
316 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 317 }
318 if (invalidate_domains) {
319 flags |= PIPE_CONTROL_TLB_INVALIDATE;
320 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
321 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
322 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
323 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
324 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
325 /*
326 * TLB invalidate requires a post-sync write.
327 */
328 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 329 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631
PZ		 330
331 /* Workaround: we must issue a pipe_control with CS-stall bit
332 * set before a pipe_control command that has the state cache
333 * invalidate bit set. */
334 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 335 }
336
337 ret = intel_ring_begin(ring, 4);
338 if (ret)
339 return ret;
340
341 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
342 intel_ring_emit(ring, flags);
b9e1faa7 343 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 344 intel_ring_emit(ring, 0);
345 intel_ring_advance(ring);
346
fd3da6c9
RV		 347 if (flush_domains)
348 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
349
4772eaeb
PZ		 350 return 0;
351}
352
78501eac 353static void ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 354 u32 value)
d46eefa2 355{
78501eac 356 drm_i915_private_t *dev_priv = ring->dev->dev_private;
297b0c5b 357 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 358}
359
78501eac 360u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
8187a2b7 361{
78501eac
CW		 362 drm_i915_private_t *dev_priv = ring->dev->dev_private;
363 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
3d281d8c 364 RING_ACTHD(ring->mmio_base) : ACTHD;
8187a2b7
ZN		 365
366 return I915_READ(acthd_reg);
367}
368
035dc1e0
DV		 369static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
370{
371 struct drm_i915_private *dev_priv = ring->dev->dev_private;
372 u32 addr;
373
374 addr = dev_priv->status_page_dmah->busaddr;
375 if (INTEL_INFO(ring->dev)->gen >= 4)
376 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
377 I915_WRITE(HWS_PGA, addr);
378}
379
78501eac 380static int init_ring_common(struct intel_ring_buffer *ring)
8187a2b7 381{
b7884eb4
DV		 382 struct drm_device *dev = ring->dev;
383 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 384 struct drm_i915_gem_object *obj = ring->obj;
b7884eb4 385 int ret = 0;
8187a2b7 386 u32 head;
8187a2b7 387
b7884eb4
DV		 388 if (HAS_FORCE_WAKE(dev))
389 gen6_gt_force_wake_get(dev_priv);
390
035dc1e0
DV		 391 if (I915_NEED_GFX_HWS(dev))
392 intel_ring_setup_status_page(ring);
393 else
394 ring_setup_phys_status_page(ring);
395
8187a2b7 396 /* Stop the ring if it's running. */
7f2ab699 397 I915_WRITE_CTL(ring, 0);
570ef608 398 I915_WRITE_HEAD(ring, 0);
78501eac 399 ring->write_tail(ring, 0);
8187a2b7 400
570ef608 401 head = I915_READ_HEAD(ring) & HEAD_ADDR;
8187a2b7
ZN		 402
403 /* G45 ring initialization fails to reset head to zero */
404 if (head != 0) {
6fd0d56e
CW		 405 DRM_DEBUG_KMS("%s head not reset to zero "
406 "ctl %08x head %08x tail %08x start %08x\n",
407 ring->name,
408 I915_READ_CTL(ring),
409 I915_READ_HEAD(ring),
410 I915_READ_TAIL(ring),
411 I915_READ_START(ring));
8187a2b7 412
570ef608 413 I915_WRITE_HEAD(ring, 0);
8187a2b7 414
6fd0d56e
CW		 415 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
416 DRM_ERROR("failed to set %s head to zero "
417 "ctl %08x head %08x tail %08x start %08x\n",
418 ring->name,
419 I915_READ_CTL(ring),
420 I915_READ_HEAD(ring),
421 I915_READ_TAIL(ring),
422 I915_READ_START(ring));
423 }
8187a2b7
ZN		 424 }
425
0d8957c8
DV		 426 /* Initialize the ring. This must happen _after_ we've cleared the ring
427 * registers with the above sequence (the readback of the HEAD registers
428 * also enforces ordering), otherwise the hw might lose the new ring
429 * register values. */
f343c5f6 430 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
7f2ab699 431 I915_WRITE_CTL(ring,
ae69b42a 432 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 433 | RING_VALID);
8187a2b7 434
8187a2b7 435 /* If the head is still not zero, the ring is dead */
f01db988 436 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 437 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 438 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5
CW		 439 DRM_ERROR("%s initialization failed "
440 "ctl %08x head %08x tail %08x start %08x\n",
441 ring->name,
442 I915_READ_CTL(ring),
443 I915_READ_HEAD(ring),
444 I915_READ_TAIL(ring),
445 I915_READ_START(ring));
b7884eb4
DV		 446 ret = -EIO;
447 goto out;
8187a2b7
ZN		 448 }
449
78501eac
CW		 450 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
451 i915_kernel_lost_context(ring->dev);
8187a2b7 452 else {
c7dca47b 453 ring->head = I915_READ_HEAD(ring);
870e86dd 454 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
c7dca47b 455 ring->space = ring_space(ring);
c3b20037 456 ring->last_retired_head = -1;
8187a2b7 457 }
1ec14ad3 458
50f018df
CW		 459 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
460
b7884eb4
DV		 461out:
462 if (HAS_FORCE_WAKE(dev))
463 gen6_gt_force_wake_put(dev_priv);
464
465 return ret;
8187a2b7
ZN		 466}
467
c6df541c
CW		 468static int
469init_pipe_control(struct intel_ring_buffer *ring)
470{
c6df541c
CW		 471 int ret;
472
0d1aacac 473 if (ring->scratch.obj)
c6df541c
CW		 474 return 0;
475
0d1aacac
CW		 476 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
477 if (ring->scratch.obj == NULL) {
c6df541c
CW		 478 DRM_ERROR("Failed to allocate seqno page\n");
479 ret = -ENOMEM;
480 goto err;
481 }
e4ffd173 482
0d1aacac 483 i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
c6df541c 484
0d1aacac 485 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false);
c6df541c
CW		 486 if (ret)
487 goto err_unref;
488
0d1aacac
CW		 489 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
490 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
491 if (ring->scratch.cpu_page == NULL) {
56b085a0 492 ret = -ENOMEM;
c6df541c 493 goto err_unpin;
56b085a0 494 }
c6df541c 495
2b1086cc 496 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 497 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 498 return 0;
499
500err_unpin:
0d1aacac 501 i915_gem_object_unpin(ring->scratch.obj);
c6df541c 502err_unref:
0d1aacac 503 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 504err:
c6df541c
CW		 505 return ret;
506}
507
78501eac 508static int init_render_ring(struct intel_ring_buffer *ring)
8187a2b7 509{
78501eac 510 struct drm_device *dev = ring->dev;
1ec14ad3 511 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 512 int ret = init_ring_common(ring);
a69ffdbf 513
1c8c38c5 514 if (INTEL_INFO(dev)->gen > 3)
6b26c86d 515 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 516
517 /* We need to disable the AsyncFlip performance optimisations in order
518 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
519 * programmed to '1' on all products.
8693a824
DL		 520 *
521 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5
CW		 522 */
523 if (INTEL_INFO(dev)->gen >= 6)
524 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
525
f05bb0c7
CW		 526 /* Required for the hardware to program scanline values for waiting */
527 if (INTEL_INFO(dev)->gen == 6)
528 I915_WRITE(GFX_MODE,
529 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
530
1c8c38c5
CW		 531 if (IS_GEN7(dev))
532 I915_WRITE(GFX_MODE_GEN7,
533 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
534 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 535
8d315287 536 if (INTEL_INFO(dev)->gen >= 5) {
c6df541c
CW		 537 ret = init_pipe_control(ring);
538 if (ret)
539 return ret;
540 }
541
5e13a0c5 542 if (IS_GEN6(dev)) {
3a69ddd6
KG		 543 /* From the Sandybridge PRM, volume 1 part 3, page 24:
544 * "If this bit is set, STCunit will have LRA as replacement
545 * policy. [...] This bit must be reset. LRA replacement
546 * policy is not supported."
547 */
548 I915_WRITE(CACHE_MODE_0,
5e13a0c5 549 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
12b0286f
BW		 550
551 /* This is not explicitly set for GEN6, so read the register.
552 * see intel_ring_mi_set_context() for why we care.
553 * TODO: consider explicitly setting the bit for GEN5
554 */
555 ring->itlb_before_ctx_switch =
556 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
84f9f938
BW		 557 }
558
6b26c86d
DV		 559 if (INTEL_INFO(dev)->gen >= 6)
560 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 561
e1ef7cc2 562 if (HAS_L3_GPU_CACHE(dev))
cc609d5d 563 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
15b9f80e 564
8187a2b7
ZN		 565 return ret;
566}
567
c6df541c
CW		 568static void render_ring_cleanup(struct intel_ring_buffer *ring)
569{
b45305fc
DV		 570 struct drm_device *dev = ring->dev;
571
0d1aacac 572 if (ring->scratch.obj == NULL)
c6df541c
CW		 573 return;
574
0d1aacac
CW		 575 if (INTEL_INFO(dev)->gen >= 5) {
576 kunmap(sg_page(ring->scratch.obj->pages->sgl));
577 i915_gem_object_unpin(ring->scratch.obj);
578 }
aaf8a516 579
0d1aacac
CW		 580 drm_gem_object_unreference(&ring->scratch.obj->base);
581 ring->scratch.obj = NULL;
c6df541c
CW		 582}
583
1ec14ad3 584static void
c8c99b0f 585update_mboxes(struct intel_ring_buffer *ring,
9d773091 586 u32 mmio_offset)
1ec14ad3 587{
ad776f8b
BW		 588/* NB: In order to be able to do semaphore MBOX updates for varying number
589 * of rings, it's easiest if we round up each individual update to a
590 * multiple of 2 (since ring updates must always be a multiple of 2)
591 * even though the actual update only requires 3 dwords.
592 */
593#define MBOX_UPDATE_DWORDS 4
1c8b46fc 594 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
c8c99b0f 595 intel_ring_emit(ring, mmio_offset);
9d773091 596 intel_ring_emit(ring, ring->outstanding_lazy_request);
ad776f8b 597 intel_ring_emit(ring, MI_NOOP);
1ec14ad3
CW		 598}
599
c8c99b0f
BW		 600/**
601 * gen6_add_request - Update the semaphore mailbox registers
602 *
603 * @ring - ring that is adding a request
604 * @seqno - return seqno stuck into the ring
605 *
606 * Update the mailbox registers in the *other* rings with the current seqno.
607 * This acts like a signal in the canonical semaphore.
608 */
1ec14ad3 609static int
9d773091 610gen6_add_request(struct intel_ring_buffer *ring)
1ec14ad3 611{
ad776f8b
BW		 612 struct drm_device *dev = ring->dev;
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 struct intel_ring_buffer *useless;
615 int i, ret;
1ec14ad3 616
ad776f8b
BW		 617 ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
618 MBOX_UPDATE_DWORDS) +
619 4);
1ec14ad3
CW		 620 if (ret)
621 return ret;
ad776f8b 622#undef MBOX_UPDATE_DWORDS
1ec14ad3 623
ad776f8b
BW		 624 for_each_ring(useless, dev_priv, i) {
625 u32 mbox_reg = ring->signal_mbox[i];
626 if (mbox_reg != GEN6_NOSYNC)
627 update_mboxes(ring, mbox_reg);
628 }
1ec14ad3
CW		 629
630 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
631 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
9d773091 632 intel_ring_emit(ring, ring->outstanding_lazy_request);
1ec14ad3
CW		 633 intel_ring_emit(ring, MI_USER_INTERRUPT);
634 intel_ring_advance(ring);
635
1ec14ad3
CW		 636 return 0;
637}
638
f72b3435
MK		 639static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
640 u32 seqno)
641{
642 struct drm_i915_private *dev_priv = dev->dev_private;
643 return dev_priv->last_seqno < seqno;
644}
645
c8c99b0f
BW		 646/**
647 * intel_ring_sync - sync the waiter to the signaller on seqno
648 *
649 * @waiter - ring that is waiting
650 * @signaller - ring which has, or will signal
651 * @seqno - seqno which the waiter will block on
652 */
653static int
686cb5f9
DV		 654gen6_ring_sync(struct intel_ring_buffer *waiter,
655 struct intel_ring_buffer *signaller,
656 u32 seqno)
1ec14ad3
CW		 657{
658 int ret;
c8c99b0f
BW		 659 u32 dw1 = MI_SEMAPHORE_MBOX |
660 MI_SEMAPHORE_COMPARE |
661 MI_SEMAPHORE_REGISTER;
1ec14ad3 662
1500f7ea
BW		 663 /* Throughout all of the GEM code, seqno passed implies our current
664 * seqno is >= the last seqno executed. However for hardware the
665 * comparison is strictly greater than.
666 */
667 seqno -= 1;
668
686cb5f9
DV		 669 WARN_ON(signaller->semaphore_register[waiter->id] ==
670 MI_SEMAPHORE_SYNC_INVALID);
671
c8c99b0f 672 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 673 if (ret)
674 return ret;
675
f72b3435
MK		 676 /* If seqno wrap happened, omit the wait with no-ops */
677 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
678 intel_ring_emit(waiter,
679 dw1 |
680 signaller->semaphore_register[waiter->id]);
681 intel_ring_emit(waiter, seqno);
682 intel_ring_emit(waiter, 0);
683 intel_ring_emit(waiter, MI_NOOP);
684 } else {
685 intel_ring_emit(waiter, MI_NOOP);
686 intel_ring_emit(waiter, MI_NOOP);
687 intel_ring_emit(waiter, MI_NOOP);
688 intel_ring_emit(waiter, MI_NOOP);
689 }
c8c99b0f 690 intel_ring_advance(waiter);
1ec14ad3
CW		 691
692 return 0;
693}
694
c6df541c
CW		 695#define PIPE_CONTROL_FLUSH(ring__, addr__) \
696do { \
fcbc34e4
KG		 697 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
698 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 699 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
700 intel_ring_emit(ring__, 0); \
701 intel_ring_emit(ring__, 0); \
702} while (0)
703
704static int
9d773091 705pc_render_add_request(struct intel_ring_buffer *ring)
c6df541c 706{
0d1aacac 707 u32 scratch_addr = ring->scratch.gtt_offset + 128;
c6df541c
CW		 708 int ret;
709
710 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
711 * incoherent with writes to memory, i.e. completely fubar,
712 * so we need to use PIPE_NOTIFY instead.
713 *
714 * However, we also need to workaround the qword write
715 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
716 * memory before requesting an interrupt.
717 */
718 ret = intel_ring_begin(ring, 32);
719 if (ret)
720 return ret;
721
fcbc34e4 722 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 723 PIPE_CONTROL_WRITE_FLUSH |
724 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 725 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
9d773091 726 intel_ring_emit(ring, ring->outstanding_lazy_request);
c6df541c
CW		 727 intel_ring_emit(ring, 0);
728 PIPE_CONTROL_FLUSH(ring, scratch_addr);
729 scratch_addr += 128; /* write to separate cachelines */
730 PIPE_CONTROL_FLUSH(ring, scratch_addr);
731 scratch_addr += 128;
732 PIPE_CONTROL_FLUSH(ring, scratch_addr);
733 scratch_addr += 128;
734 PIPE_CONTROL_FLUSH(ring, scratch_addr);
735 scratch_addr += 128;
736 PIPE_CONTROL_FLUSH(ring, scratch_addr);
737 scratch_addr += 128;
738 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 739
fcbc34e4 740 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 741 PIPE_CONTROL_WRITE_FLUSH |
742 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 743 PIPE_CONTROL_NOTIFY);
0d1aacac 744 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
9d773091 745 intel_ring_emit(ring, ring->outstanding_lazy_request);
c6df541c
CW		 746 intel_ring_emit(ring, 0);
747 intel_ring_advance(ring);
748
c6df541c
CW		 749 return 0;
750}
751
4cd53c0c 752static u32
b2eadbc8 753gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
4cd53c0c 754{
4cd53c0c
DV		 755 /* Workaround to force correct ordering between irq and seqno writes on
756 * ivb (and maybe also on snb) by reading from a CS register (like
757 * ACTHD) before reading the status page. */
b2eadbc8 758 if (!lazy_coherency)
4cd53c0c
DV		 759 intel_ring_get_active_head(ring);
760 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
761}
762
8187a2b7 763static u32
b2eadbc8 764ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
8187a2b7 765{
1ec14ad3
CW		 766 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
767}
768
b70ec5bf
MK		 769static void
770ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
771{
772 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
773}
774
c6df541c 775static u32
b2eadbc8 776pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
c6df541c 777{
0d1aacac 778 return ring->scratch.cpu_page[0];
c6df541c
CW		 779}
780
b70ec5bf
MK		 781static void
782pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
783{
0d1aacac 784 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 785}
786
e48d8634
DV		 787static bool
788gen5_ring_get_irq(struct intel_ring_buffer *ring)
789{
790 struct drm_device *dev = ring->dev;
791 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 792 unsigned long flags;
e48d8634
DV		 793
794 if (!dev->irq_enabled)
795 return false;
796
7338aefa 797 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13
PZ		 798 if (ring->irq_refcount++ == 0)
799 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 800 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 801
802 return true;
803}
804
805static void
806gen5_ring_put_irq(struct intel_ring_buffer *ring)
807{
808 struct drm_device *dev = ring->dev;
809 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 810 unsigned long flags;
e48d8634 811
7338aefa 812 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13
PZ		 813 if (--ring->irq_refcount == 0)
814 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 815 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 816}
817
b13c2b96 818static bool
e3670319 819i9xx_ring_get_irq(struct intel_ring_buffer *ring)
62fdfeaf 820{
78501eac 821 struct drm_device *dev = ring->dev;
01a03331 822 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 823 unsigned long flags;
62fdfeaf 824
b13c2b96
CW		 825 if (!dev->irq_enabled)
826 return false;
827
7338aefa 828 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 829 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 830 dev_priv->irq_mask &= ~ring->irq_enable_mask;
831 I915_WRITE(IMR, dev_priv->irq_mask);
832 POSTING_READ(IMR);
833 }
7338aefa 834 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 835
836 return true;
62fdfeaf
EA		 837}
838
8187a2b7 839static void
e3670319 840i9xx_ring_put_irq(struct intel_ring_buffer *ring)
62fdfeaf 841{
78501eac 842 struct drm_device *dev = ring->dev;
01a03331 843 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 844 unsigned long flags;
62fdfeaf 845
7338aefa 846 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 847 if (--ring->irq_refcount == 0) {
f637fde4
DV		 848 dev_priv->irq_mask |= ring->irq_enable_mask;
849 I915_WRITE(IMR, dev_priv->irq_mask);
850 POSTING_READ(IMR);
851 }
7338aefa 852 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 853}
854
c2798b19
CW		 855static bool
856i8xx_ring_get_irq(struct intel_ring_buffer *ring)
857{
858 struct drm_device *dev = ring->dev;
859 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 860 unsigned long flags;
c2798b19
CW		 861
862 if (!dev->irq_enabled)
863 return false;
864
7338aefa 865 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 866 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 867 dev_priv->irq_mask &= ~ring->irq_enable_mask;
868 I915_WRITE16(IMR, dev_priv->irq_mask);
869 POSTING_READ16(IMR);
870 }
7338aefa 871 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 872
873 return true;
874}
875
876static void
877i8xx_ring_put_irq(struct intel_ring_buffer *ring)
878{
879 struct drm_device *dev = ring->dev;
880 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 881 unsigned long flags;
c2798b19 882
7338aefa 883 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 884 if (--ring->irq_refcount == 0) {
c2798b19
CW		 885 dev_priv->irq_mask |= ring->irq_enable_mask;
886 I915_WRITE16(IMR, dev_priv->irq_mask);
887 POSTING_READ16(IMR);
888 }
7338aefa 889 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 890}
891
78501eac 892void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
8187a2b7 893{
4593010b 894 struct drm_device *dev = ring->dev;
78501eac 895 drm_i915_private_t *dev_priv = ring->dev->dev_private;
4593010b
EA		 896 u32 mmio = 0;
897
898 /* The ring status page addresses are no longer next to the rest of
899 * the ring registers as of gen7.
900 */
901 if (IS_GEN7(dev)) {
902 switch (ring->id) {
96154f2f 903 case RCS:
4593010b
EA		 904 mmio = RENDER_HWS_PGA_GEN7;
905 break;
96154f2f 906 case BCS:
4593010b
EA		 907 mmio = BLT_HWS_PGA_GEN7;
908 break;
96154f2f 909 case VCS:
4593010b
EA		 910 mmio = BSD_HWS_PGA_GEN7;
911 break;
4a3dd19d 912 case VECS:
9a8a2213
BW		 913 mmio = VEBOX_HWS_PGA_GEN7;
914 break;
4593010b
EA		 915 }
916 } else if (IS_GEN6(ring->dev)) {
917 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
918 } else {
919 mmio = RING_HWS_PGA(ring->mmio_base);
920 }
921
78501eac
CW		 922 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
923 POSTING_READ(mmio);
884020bf
CW		 924
925 /* Flush the TLB for this page */
926 if (INTEL_INFO(dev)->gen >= 6) {
927 u32 reg = RING_INSTPM(ring->mmio_base);
928 I915_WRITE(reg,
929 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
930 INSTPM_SYNC_FLUSH));
931 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
932 1000))
933 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
934 ring->name);
935 }
8187a2b7
ZN		 936}
937
b72f3acb 938static int
78501eac
CW		 939bsd_ring_flush(struct intel_ring_buffer *ring,
940 u32 invalidate_domains,
941 u32 flush_domains)
d1b851fc 942{
b72f3acb
CW		 943 int ret;
944
b72f3acb
CW		 945 ret = intel_ring_begin(ring, 2);
946 if (ret)
947 return ret;
948
949 intel_ring_emit(ring, MI_FLUSH);
950 intel_ring_emit(ring, MI_NOOP);
951 intel_ring_advance(ring);
952 return 0;
d1b851fc
ZN		 953}
954
3cce469c 955static int
9d773091 956i9xx_add_request(struct intel_ring_buffer *ring)
d1b851fc 957{
3cce469c
CW		 958 int ret;
959
960 ret = intel_ring_begin(ring, 4);
961 if (ret)
962 return ret;
6f392d54 963
3cce469c
CW		 964 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
965 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
9d773091 966 intel_ring_emit(ring, ring->outstanding_lazy_request);
3cce469c
CW		 967 intel_ring_emit(ring, MI_USER_INTERRUPT);
968 intel_ring_advance(ring);
d1b851fc 969
3cce469c 970 return 0;
d1b851fc
ZN		 971}
972
0f46832f 973static bool
25c06300 974gen6_ring_get_irq(struct intel_ring_buffer *ring)
0f46832f
CW		 975{
976 struct drm_device *dev = ring->dev;
01a03331 977 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 978 unsigned long flags;
0f46832f
CW		 979
980 if (!dev->irq_enabled)
981 return false;
982
4cd53c0c
DV		 983 /* It looks like we need to prevent the gt from suspending while waiting
984 * for an notifiy irq, otherwise irqs seem to get lost on at least the
985 * blt/bsd rings on ivb. */
99ffa162 986 gen6_gt_force_wake_get(dev_priv);
4cd53c0c 987
7338aefa 988 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 989 if (ring->irq_refcount++ == 0) {
e1ef7cc2 990 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
cc609d5d
BW		 991 I915_WRITE_IMR(ring,
992 ~(ring->irq_enable_mask |
993 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
15b9f80e
BW		 994 else
995 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
43eaea13 996 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 997 }
7338aefa 998 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 999
1000 return true;
1001}
1002
1003static void
25c06300 1004gen6_ring_put_irq(struct intel_ring_buffer *ring)
0f46832f
CW		 1005{
1006 struct drm_device *dev = ring->dev;
01a03331 1007 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 1008 unsigned long flags;
0f46832f 1009
7338aefa 1010 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1011 if (--ring->irq_refcount == 0) {
e1ef7cc2 1012 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
cc609d5d
BW		 1013 I915_WRITE_IMR(ring,
1014 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
15b9f80e
BW		 1015 else
1016 I915_WRITE_IMR(ring, ~0);
43eaea13 1017 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1018 }
7338aefa 1019 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
4cd53c0c 1020
99ffa162 1021 gen6_gt_force_wake_put(dev_priv);
d1b851fc
ZN		 1022}
1023
a19d2933
BW		 1024static bool
1025hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1026{
1027 struct drm_device *dev = ring->dev;
1028 struct drm_i915_private *dev_priv = dev->dev_private;
1029 unsigned long flags;
1030
1031 if (!dev->irq_enabled)
1032 return false;
1033
59cdb63d 1034 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1035 if (ring->irq_refcount++ == 0) {
a19d2933 1036 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
edbfdb45 1037 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1038 }
59cdb63d 1039 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1040
1041 return true;
1042}
1043
1044static void
1045hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1046{
1047 struct drm_device *dev = ring->dev;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 unsigned long flags;
1050
1051 if (!dev->irq_enabled)
1052 return;
1053
59cdb63d 1054 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1055 if (--ring->irq_refcount == 0) {
a19d2933 1056 I915_WRITE_IMR(ring, ~0);
edbfdb45 1057 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1058 }
59cdb63d 1059 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1060}
1061
d1b851fc 1062static int
d7d4eedd
CW		 1063i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1064 u32 offset, u32 length,
1065 unsigned flags)
d1b851fc 1066{
e1f99ce6 1067 int ret;
78501eac 1068
e1f99ce6
CW		 1069 ret = intel_ring_begin(ring, 2);
1070 if (ret)
1071 return ret;
1072
78501eac 1073 intel_ring_emit(ring,
65f56876
CW		 1074 MI_BATCH_BUFFER_START |
1075 MI_BATCH_GTT |
d7d4eedd 1076 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1077 intel_ring_emit(ring, offset);
78501eac
CW		 1078 intel_ring_advance(ring);
1079
d1b851fc
ZN		 1080 return 0;
1081}
1082
b45305fc
DV		 1083/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1084#define I830_BATCH_LIMIT (256*1024)
8187a2b7 1085static int
fb3256da 1086i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
d7d4eedd
CW		 1087 u32 offset, u32 len,
1088 unsigned flags)
62fdfeaf 1089{
c4e7a414 1090 int ret;
62fdfeaf 1091
b45305fc
DV		 1092 if (flags & I915_DISPATCH_PINNED) {
1093 ret = intel_ring_begin(ring, 4);
1094 if (ret)
1095 return ret;
62fdfeaf 1096
b45305fc
DV		 1097 intel_ring_emit(ring, MI_BATCH_BUFFER);
1098 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1099 intel_ring_emit(ring, offset + len - 8);
1100 intel_ring_emit(ring, MI_NOOP);
1101 intel_ring_advance(ring);
1102 } else {
0d1aacac 1103 u32 cs_offset = ring->scratch.gtt_offset;
b45305fc
DV		 1104
1105 if (len > I830_BATCH_LIMIT)
1106 return -ENOSPC;
1107
1108 ret = intel_ring_begin(ring, 9+3);
1109 if (ret)
1110 return ret;
1111 /* Blit the batch (which has now all relocs applied) to the stable batch
1112 * scratch bo area (so that the CS never stumbles over its tlb
1113 * invalidation bug) ... */
1114 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1115 XY_SRC_COPY_BLT_WRITE_ALPHA |
1116 XY_SRC_COPY_BLT_WRITE_RGB);
1117 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1118 intel_ring_emit(ring, 0);
1119 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1120 intel_ring_emit(ring, cs_offset);
1121 intel_ring_emit(ring, 0);
1122 intel_ring_emit(ring, 4096);
1123 intel_ring_emit(ring, offset);
1124 intel_ring_emit(ring, MI_FLUSH);
1125
1126 /* ... and execute it. */
1127 intel_ring_emit(ring, MI_BATCH_BUFFER);
1128 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1129 intel_ring_emit(ring, cs_offset + len - 8);
1130 intel_ring_advance(ring);
1131 }
e1f99ce6 1132
fb3256da
DV		 1133 return 0;
1134}
1135
1136static int
1137i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
d7d4eedd
CW		 1138 u32 offset, u32 len,
1139 unsigned flags)
fb3256da
DV		 1140{
1141 int ret;
1142
1143 ret = intel_ring_begin(ring, 2);
1144 if (ret)
1145 return ret;
1146
65f56876 1147 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1148 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1149 intel_ring_advance(ring);
62fdfeaf 1150
62fdfeaf
EA		 1151 return 0;
1152}
1153
78501eac 1154static void cleanup_status_page(struct intel_ring_buffer *ring)
62fdfeaf 1155{
05394f39 1156 struct drm_i915_gem_object *obj;
62fdfeaf 1157
8187a2b7
ZN		 1158 obj = ring->status_page.obj;
1159 if (obj == NULL)
62fdfeaf 1160 return;
62fdfeaf 1161
9da3da66 1162 kunmap(sg_page(obj->pages->sgl));
62fdfeaf 1163 i915_gem_object_unpin(obj);
05394f39 1164 drm_gem_object_unreference(&obj->base);
8187a2b7 1165 ring->status_page.obj = NULL;
62fdfeaf
EA		 1166}
1167
78501eac 1168static int init_status_page(struct intel_ring_buffer *ring)
62fdfeaf 1169{
78501eac 1170 struct drm_device *dev = ring->dev;
05394f39 1171 struct drm_i915_gem_object *obj;
62fdfeaf
EA		 1172 int ret;
1173
62fdfeaf
EA		 1174 obj = i915_gem_alloc_object(dev, 4096);
1175 if (obj == NULL) {
1176 DRM_ERROR("Failed to allocate status page\n");
1177 ret = -ENOMEM;
1178 goto err;
1179 }
e4ffd173
CW		 1180
1181 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
62fdfeaf 1182
c37e2204 1183 ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
62fdfeaf 1184 if (ret != 0) {
62fdfeaf
EA		 1185 goto err_unref;
1186 }
1187
f343c5f6 1188 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1189 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1190 if (ring->status_page.page_addr == NULL) {
2e6c21ed 1191 ret = -ENOMEM;
62fdfeaf
EA		 1192 goto err_unpin;
1193 }
8187a2b7
ZN		 1194 ring->status_page.obj = obj;
1195 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1196
8187a2b7
ZN		 1197 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1198 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1199
1200 return 0;
1201
1202err_unpin:
1203 i915_gem_object_unpin(obj);
1204err_unref:
05394f39 1205 drm_gem_object_unreference(&obj->base);
62fdfeaf 1206err:
8187a2b7 1207 return ret;
62fdfeaf
EA		 1208}
1209
035dc1e0 1210static int init_phys_status_page(struct intel_ring_buffer *ring)
6b8294a4
CW		 1211{
1212 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1213
1214 if (!dev_priv->status_page_dmah) {
1215 dev_priv->status_page_dmah =
1216 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1217 if (!dev_priv->status_page_dmah)
1218 return -ENOMEM;
1219 }
1220
6b8294a4
CW		 1221 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1222 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1223
1224 return 0;
1225}
1226
c43b5634
BW		 1227static int intel_init_ring_buffer(struct drm_device *dev,
1228 struct intel_ring_buffer *ring)
62fdfeaf 1229{
05394f39 1230 struct drm_i915_gem_object *obj;
dd2757f8 1231 struct drm_i915_private *dev_priv = dev->dev_private;
dd785e35
CW		 1232 int ret;
1233
8187a2b7 1234 ring->dev = dev;
23bc5982
CW		 1235 INIT_LIST_HEAD(&ring->active_list);
1236 INIT_LIST_HEAD(&ring->request_list);
dfc9ef2f 1237 ring->size = 32 * PAGE_SIZE;
9d773091 1238 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
0dc79fb2 1239
b259f673 1240 init_waitqueue_head(&ring->irq_queue);
62fdfeaf 1241
8187a2b7 1242 if (I915_NEED_GFX_HWS(dev)) {
78501eac 1243 ret = init_status_page(ring);
8187a2b7
ZN		 1244 if (ret)
1245 return ret;
6b8294a4
CW		 1246 } else {
1247 BUG_ON(ring->id != RCS);
035dc1e0 1248 ret = init_phys_status_page(ring);
6b8294a4
CW		 1249 if (ret)
1250 return ret;
8187a2b7 1251 }
62fdfeaf 1252
ebc052e0
CW		 1253 obj = NULL;
1254 if (!HAS_LLC(dev))
1255 obj = i915_gem_object_create_stolen(dev, ring->size);
1256 if (obj == NULL)
1257 obj = i915_gem_alloc_object(dev, ring->size);
62fdfeaf
EA		 1258 if (obj == NULL) {
1259 DRM_ERROR("Failed to allocate ringbuffer\n");
8187a2b7 1260 ret = -ENOMEM;
dd785e35 1261 goto err_hws;
62fdfeaf 1262 }
62fdfeaf 1263
05394f39 1264 ring->obj = obj;
8187a2b7 1265
c37e2204 1266 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);
dd785e35
CW		 1267 if (ret)
1268 goto err_unref;
62fdfeaf 1269
3eef8918
CW		 1270 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1271 if (ret)
1272 goto err_unpin;
1273
dd2757f8 1274 ring->virtual_start =
f343c5f6 1275 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
dd2757f8 1276 ring->size);
4225d0f2 1277 if (ring->virtual_start == NULL) {
62fdfeaf 1278 DRM_ERROR("Failed to map ringbuffer.\n");
8187a2b7 1279 ret = -EINVAL;
dd785e35 1280 goto err_unpin;
62fdfeaf
EA		 1281 }
1282
78501eac 1283 ret = ring->init(ring);
dd785e35
CW		 1284 if (ret)
1285 goto err_unmap;
62fdfeaf 1286
55249baa
CW		 1287 /* Workaround an erratum on the i830 which causes a hang if
1288 * the TAIL pointer points to within the last 2 cachelines
1289 * of the buffer.
1290 */
1291 ring->effective_size = ring->size;
27c1cbd0 1292 if (IS_I830(ring->dev) || IS_845G(ring->dev))
55249baa
CW		 1293 ring->effective_size -= 128;
1294
c584fe47 1295 return 0;
dd785e35
CW		 1296
1297err_unmap:
4225d0f2 1298 iounmap(ring->virtual_start);
dd785e35
CW		 1299err_unpin:
1300 i915_gem_object_unpin(obj);
1301err_unref:
05394f39
CW		 1302 drm_gem_object_unreference(&obj->base);
1303 ring->obj = NULL;
dd785e35 1304err_hws:
78501eac 1305 cleanup_status_page(ring);
8187a2b7 1306 return ret;
62fdfeaf
EA		 1307}
1308
78501eac 1309void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 1310{
33626e6a
CW		 1311 struct drm_i915_private *dev_priv;
1312 int ret;
1313
05394f39 1314 if (ring->obj == NULL)
62fdfeaf
EA		 1315 return;
1316
33626e6a
CW		 1317 /* Disable the ring buffer. The ring must be idle at this point */
1318 dev_priv = ring->dev->dev_private;
3e960501 1319 ret = intel_ring_idle(ring);
29ee3991
CW		 1320 if (ret)
1321 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1322 ring->name, ret);
1323
33626e6a
CW		 1324 I915_WRITE_CTL(ring, 0);
1325
4225d0f2 1326 iounmap(ring->virtual_start);
62fdfeaf 1327
05394f39
CW		 1328 i915_gem_object_unpin(ring->obj);
1329 drm_gem_object_unreference(&ring->obj->base);
1330 ring->obj = NULL;
78501eac 1331
8d19215b
ZN		 1332 if (ring->cleanup)
1333 ring->cleanup(ring);
1334
78501eac 1335 cleanup_status_page(ring);
62fdfeaf
EA		 1336}
1337
a71d8d94
CW		 1338static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1339{
a71d8d94
CW		 1340 int ret;
1341
199b2bc2 1342 ret = i915_wait_seqno(ring, seqno);
b2da9fe5
BW		 1343 if (!ret)
1344 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 1345
1346 return ret;
1347}
1348
1349static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1350{
1351 struct drm_i915_gem_request *request;
1352 u32 seqno = 0;
1353 int ret;
1354
1355 i915_gem_retire_requests_ring(ring);
1356
1357 if (ring->last_retired_head != -1) {
1358 ring->head = ring->last_retired_head;
1359 ring->last_retired_head = -1;
1360 ring->space = ring_space(ring);
1361 if (ring->space >= n)
1362 return 0;
1363 }
1364
1365 list_for_each_entry(request, &ring->request_list, list) {
1366 int space;
1367
1368 if (request->tail == -1)
1369 continue;
1370
633cf8f5 1371 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
a71d8d94
CW		 1372 if (space < 0)
1373 space += ring->size;
1374 if (space >= n) {
1375 seqno = request->seqno;
1376 break;
1377 }
1378
1379 /* Consume this request in case we need more space than
1380 * is available and so need to prevent a race between
1381 * updating last_retired_head and direct reads of
1382 * I915_RING_HEAD. It also provides a nice sanity check.
1383 */
1384 request->tail = -1;
1385 }
1386
1387 if (seqno == 0)
1388 return -ENOSPC;
1389
1390 ret = intel_ring_wait_seqno(ring, seqno);
1391 if (ret)
1392 return ret;
1393
1394 if (WARN_ON(ring->last_retired_head == -1))
1395 return -ENOSPC;
1396
1397 ring->head = ring->last_retired_head;
1398 ring->last_retired_head = -1;
1399 ring->space = ring_space(ring);
1400 if (WARN_ON(ring->space < n))
1401 return -ENOSPC;
1402
1403 return 0;
1404}
1405
3e960501 1406static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
62fdfeaf 1407{
78501eac 1408 struct drm_device *dev = ring->dev;
cae5852d 1409 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1410 unsigned long end;
a71d8d94 1411 int ret;
c7dca47b 1412
a71d8d94
CW		 1413 ret = intel_ring_wait_request(ring, n);
1414 if (ret != -ENOSPC)
1415 return ret;
1416
db53a302 1417 trace_i915_ring_wait_begin(ring);
63ed2cb2
DV		 1418 /* With GEM the hangcheck timer should kick us out of the loop,
1419 * leaving it early runs the risk of corrupting GEM state (due
1420 * to running on almost untested codepaths). But on resume
1421 * timers don't work yet, so prevent a complete hang in that
1422 * case by choosing an insanely large timeout. */
1423 end = jiffies + 60 * HZ;
e6bfaf85 1424
8187a2b7 1425 do {
c7dca47b
CW		 1426 ring->head = I915_READ_HEAD(ring);
1427 ring->space = ring_space(ring);
62fdfeaf 1428 if (ring->space >= n) {
db53a302 1429 trace_i915_ring_wait_end(ring);
62fdfeaf
EA		 1430 return 0;
1431 }
1432
1433 if (dev->primary->master) {
1434 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1435 if (master_priv->sarea_priv)
1436 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1437 }
d1b851fc 1438
e60a0b10 1439 msleep(1);
d6b2c790 1440
33196ded
DV		 1441 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1442 dev_priv->mm.interruptible);
d6b2c790
DV		 1443 if (ret)
1444 return ret;
8187a2b7 1445 } while (!time_after(jiffies, end));
db53a302 1446 trace_i915_ring_wait_end(ring);
8187a2b7
ZN		 1447 return -EBUSY;
1448}
62fdfeaf 1449
3e960501
CW		 1450static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1451{
1452 uint32_t __iomem *virt;
1453 int rem = ring->size - ring->tail;
1454
1455 if (ring->space < rem) {
1456 int ret = ring_wait_for_space(ring, rem);
1457 if (ret)
1458 return ret;
1459 }
1460
1461 virt = ring->virtual_start + ring->tail;
1462 rem /= 4;
1463 while (rem--)
1464 iowrite32(MI_NOOP, virt++);
1465
1466 ring->tail = 0;
1467 ring->space = ring_space(ring);
1468
1469 return 0;
1470}
1471
1472int intel_ring_idle(struct intel_ring_buffer *ring)
1473{
1474 u32 seqno;
1475 int ret;
1476
1477 /* We need to add any requests required to flush the objects and ring */
1478 if (ring->outstanding_lazy_request) {
0025c077 1479 ret = i915_add_request(ring, NULL);
3e960501
CW		 1480 if (ret)
1481 return ret;
1482 }
1483
1484 /* Wait upon the last request to be completed */
1485 if (list_empty(&ring->request_list))
1486 return 0;
1487
1488 seqno = list_entry(ring->request_list.prev,
1489 struct drm_i915_gem_request,
1490 list)->seqno;
1491
1492 return i915_wait_seqno(ring, seqno);
1493}
1494
9d773091
CW		 1495static int
1496intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1497{
1498 if (ring->outstanding_lazy_request)
1499 return 0;
1500
1501 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1502}
1503
cbcc80df
MK		 1504static int __intel_ring_begin(struct intel_ring_buffer *ring,
1505 int bytes)
1506{
1507 int ret;
1508
1509 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1510 ret = intel_wrap_ring_buffer(ring);
1511 if (unlikely(ret))
1512 return ret;
1513 }
1514
1515 if (unlikely(ring->space < bytes)) {
1516 ret = ring_wait_for_space(ring, bytes);
1517 if (unlikely(ret))
1518 return ret;
1519 }
1520
1521 ring->space -= bytes;
1522 return 0;
1523}
1524
e1f99ce6
CW		 1525int intel_ring_begin(struct intel_ring_buffer *ring,
1526 int num_dwords)
8187a2b7 1527{
de2b9985 1528 drm_i915_private_t *dev_priv = ring->dev->dev_private;
e1f99ce6 1529 int ret;
78501eac 1530
33196ded
DV		 1531 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1532 dev_priv->mm.interruptible);
de2b9985
DV		 1533 if (ret)
1534 return ret;
21dd3734 1535
9d773091
CW		 1536 /* Preallocate the olr before touching the ring */
1537 ret = intel_ring_alloc_seqno(ring);
1538 if (ret)
1539 return ret;
1540
cbcc80df 1541 return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
8187a2b7 1542}
78501eac 1543
f7e98ad4 1544void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
498d2ac1 1545{
f7e98ad4 1546 struct drm_i915_private *dev_priv = ring->dev->dev_private;
498d2ac1
MK		 1547
1548 BUG_ON(ring->outstanding_lazy_request);
1549
f7e98ad4
MK		 1550 if (INTEL_INFO(ring->dev)->gen >= 6) {
1551 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1552 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
5020150b
BW		 1553 if (HAS_VEBOX(ring->dev))
1554 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 1555 }
d97ed339 1556
f7e98ad4 1557 ring->set_seqno(ring, seqno);
92cab734 1558 ring->hangcheck.seqno = seqno;
8187a2b7 1559}
62fdfeaf 1560
78501eac 1561void intel_ring_advance(struct intel_ring_buffer *ring)
8187a2b7 1562{
e5eb3d63
DV		 1563 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1564
d97ed339 1565 ring->tail &= ring->size - 1;
99584db3 1566 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
e5eb3d63 1567 return;
78501eac 1568 ring->write_tail(ring, ring->tail);
8187a2b7 1569}
62fdfeaf 1570
881f47b6 1571
78501eac 1572static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 1573 u32 value)
881f47b6 1574{
0206e353 1575 drm_i915_private_t *dev_priv = ring->dev->dev_private;
881f47b6
XH		 1576
1577 /* Every tail move must follow the sequence below */
12f55818
CW		 1578
1579 /* Disable notification that the ring is IDLE. The GT
1580 * will then assume that it is busy and bring it out of rc6.
1581 */
0206e353 1582 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 1583 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1584
1585 /* Clear the context id. Here be magic! */
1586 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 1587
12f55818 1588 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 1589 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 1590 GEN6_BSD_SLEEP_INDICATOR) == 0,
1591 50))
1592 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 1593
12f55818 1594 /* Now that the ring is fully powered up, update the tail */
0206e353 1595 I915_WRITE_TAIL(ring, value);
12f55818
CW		 1596 POSTING_READ(RING_TAIL(ring->mmio_base));
1597
1598 /* Let the ring send IDLE messages to the GT again,
1599 * and so let it sleep to conserve power when idle.
1600 */
0206e353 1601 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 1602 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 1603}
1604
ea251324
BW		 1605static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1606 u32 invalidate, u32 flush)
881f47b6 1607{
71a77e07 1608 uint32_t cmd;
b72f3acb
CW		 1609 int ret;
1610
b72f3acb
CW		 1611 ret = intel_ring_begin(ring, 4);
1612 if (ret)
1613 return ret;
1614
71a77e07 1615 cmd = MI_FLUSH_DW;
9a289771
JB		 1616 /*
1617 * Bspec vol 1c.5 - video engine command streamer:
1618 * "If ENABLED, all TLBs will be invalidated once the flush
1619 * operation is complete. This bit is only valid when the
1620 * Post-Sync Operation field is a value of 1h or 3h."
1621 */
71a77e07 1622 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 1623 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1624 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 1625 intel_ring_emit(ring, cmd);
9a289771 1626 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
b72f3acb 1627 intel_ring_emit(ring, 0);
71a77e07 1628 intel_ring_emit(ring, MI_NOOP);
b72f3acb
CW		 1629 intel_ring_advance(ring);
1630 return 0;
881f47b6
XH		 1631}
1632
d7d4eedd
CW		 1633static int
1634hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1635 u32 offset, u32 len,
1636 unsigned flags)
1637{
1638 int ret;
1639
1640 ret = intel_ring_begin(ring, 2);
1641 if (ret)
1642 return ret;
1643
1644 intel_ring_emit(ring,
1645 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1646 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1647 /* bit0-7 is the length on GEN6+ */
1648 intel_ring_emit(ring, offset);
1649 intel_ring_advance(ring);
1650
1651 return 0;
1652}
1653
881f47b6 1654static int
78501eac 1655gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
d7d4eedd
CW		 1656 u32 offset, u32 len,
1657 unsigned flags)
881f47b6 1658{
0206e353 1659 int ret;
ab6f8e32 1660
0206e353
AJ		 1661 ret = intel_ring_begin(ring, 2);
1662 if (ret)
1663 return ret;
e1f99ce6 1664
d7d4eedd
CW		 1665 intel_ring_emit(ring,
1666 MI_BATCH_BUFFER_START |
1667 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 1668 /* bit0-7 is the length on GEN6+ */
1669 intel_ring_emit(ring, offset);
1670 intel_ring_advance(ring);
ab6f8e32 1671
0206e353 1672 return 0;
881f47b6
XH		 1673}
1674
549f7365
CW		 1675/* Blitter support (SandyBridge+) */
1676
ea251324
BW		 1677static int gen6_ring_flush(struct intel_ring_buffer *ring,
1678 u32 invalidate, u32 flush)
8d19215b 1679{
fd3da6c9 1680 struct drm_device *dev = ring->dev;
71a77e07 1681 uint32_t cmd;
b72f3acb
CW		 1682 int ret;
1683
6a233c78 1684 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 1685 if (ret)
1686 return ret;
1687
71a77e07 1688 cmd = MI_FLUSH_DW;
9a289771
JB		 1689 /*
1690 * Bspec vol 1c.3 - blitter engine command streamer:
1691 * "If ENABLED, all TLBs will be invalidated once the flush
1692 * operation is complete. This bit is only valid when the
1693 * Post-Sync Operation field is a value of 1h or 3h."
1694 */
71a77e07 1695 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 1696 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 1697 MI_FLUSH_DW_OP_STOREDW;
71a77e07 1698 intel_ring_emit(ring, cmd);
9a289771 1699 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
b72f3acb 1700 intel_ring_emit(ring, 0);
71a77e07 1701 intel_ring_emit(ring, MI_NOOP);
b72f3acb 1702 intel_ring_advance(ring);
fd3da6c9
RV		 1703
1704 if (IS_GEN7(dev) && flush)
1705 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1706
b72f3acb 1707 return 0;
8d19215b
ZN		 1708}
1709
5c1143bb
XH		 1710int intel_init_render_ring_buffer(struct drm_device *dev)
1711{
1712 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1713 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5c1143bb 1714
59465b5f
DV		 1715 ring->name = "render ring";
1716 ring->id = RCS;
1717 ring->mmio_base = RENDER_RING_BASE;
1718
1ec14ad3
CW		 1719 if (INTEL_INFO(dev)->gen >= 6) {
1720 ring->add_request = gen6_add_request;
4772eaeb 1721 ring->flush = gen7_render_ring_flush;
6c6cf5aa 1722 if (INTEL_INFO(dev)->gen == 6)
b3111509 1723 ring->flush = gen6_render_ring_flush;
25c06300
BW		 1724 ring->irq_get = gen6_ring_get_irq;
1725 ring->irq_put = gen6_ring_put_irq;
cc609d5d 1726 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 1727 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 1728 ring->set_seqno = ring_set_seqno;
686cb5f9 1729 ring->sync_to = gen6_ring_sync;
5586181f
BW		 1730 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1731 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1732 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1950de14 1733 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
ad776f8b
BW		 1734 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1735 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1736 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1950de14 1737 ring->signal_mbox[VECS] = GEN6_VERSYNC;
c6df541c
CW		 1738 } else if (IS_GEN5(dev)) {
1739 ring->add_request = pc_render_add_request;
46f0f8d1 1740 ring->flush = gen4_render_ring_flush;
c6df541c 1741 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 1742 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 1743 ring->irq_get = gen5_ring_get_irq;
1744 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 1745 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1746 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 1747 } else {
8620a3a9 1748 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 1749 if (INTEL_INFO(dev)->gen < 4)
1750 ring->flush = gen2_render_ring_flush;
1751 else
1752 ring->flush = gen4_render_ring_flush;
59465b5f 1753 ring->get_seqno = ring_get_seqno;
b70ec5bf 1754 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 1755 if (IS_GEN2(dev)) {
1756 ring->irq_get = i8xx_ring_get_irq;
1757 ring->irq_put = i8xx_ring_put_irq;
1758 } else {
1759 ring->irq_get = i9xx_ring_get_irq;
1760 ring->irq_put = i9xx_ring_put_irq;
1761 }
e3670319 1762 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 1763 }
59465b5f 1764 ring->write_tail = ring_write_tail;
d7d4eedd
CW		 1765 if (IS_HASWELL(dev))
1766 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1767 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 1768 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1769 else if (INTEL_INFO(dev)->gen >= 4)
1770 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1771 else if (IS_I830(dev) || IS_845G(dev))
1772 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1773 else
1774 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 1775 ring->init = init_render_ring;
1776 ring->cleanup = render_ring_cleanup;
1777
b45305fc
DV		 1778 /* Workaround batchbuffer to combat CS tlb bug. */
1779 if (HAS_BROKEN_CS_TLB(dev)) {
1780 struct drm_i915_gem_object *obj;
1781 int ret;
1782
1783 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1784 if (obj == NULL) {
1785 DRM_ERROR("Failed to allocate batch bo\n");
1786 return -ENOMEM;
1787 }
1788
c37e2204 1789 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
b45305fc
DV		 1790 if (ret != 0) {
1791 drm_gem_object_unreference(&obj->base);
1792 DRM_ERROR("Failed to ping batch bo\n");
1793 return ret;
1794 }
1795
0d1aacac
CW		 1796 ring->scratch.obj = obj;
1797 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 1798 }
1799
1ec14ad3 1800 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 1801}
1802
e8616b6c
CW		 1803int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1804{
1805 drm_i915_private_t *dev_priv = dev->dev_private;
1806 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6b8294a4 1807 int ret;
e8616b6c 1808
59465b5f
DV		 1809 ring->name = "render ring";
1810 ring->id = RCS;
1811 ring->mmio_base = RENDER_RING_BASE;
1812
e8616b6c 1813 if (INTEL_INFO(dev)->gen >= 6) {
b4178f8a
DV		 1814 /* non-kms not supported on gen6+ */
1815 return -ENODEV;
e8616b6c 1816 }
28f0cbf7
DV		 1817
1818 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1819 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1820 * the special gen5 functions. */
1821 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 1822 if (INTEL_INFO(dev)->gen < 4)
1823 ring->flush = gen2_render_ring_flush;
1824 else
1825 ring->flush = gen4_render_ring_flush;
28f0cbf7 1826 ring->get_seqno = ring_get_seqno;
b70ec5bf 1827 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 1828 if (IS_GEN2(dev)) {
1829 ring->irq_get = i8xx_ring_get_irq;
1830 ring->irq_put = i8xx_ring_put_irq;
1831 } else {
1832 ring->irq_get = i9xx_ring_get_irq;
1833 ring->irq_put = i9xx_ring_put_irq;
1834 }
28f0cbf7 1835 ring->irq_enable_mask = I915_USER_INTERRUPT;
59465b5f 1836 ring->write_tail = ring_write_tail;
fb3256da
DV		 1837 if (INTEL_INFO(dev)->gen >= 4)
1838 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1839 else if (IS_I830(dev) || IS_845G(dev))
1840 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1841 else
1842 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 1843 ring->init = init_render_ring;
1844 ring->cleanup = render_ring_cleanup;
e8616b6c
CW		 1845
1846 ring->dev = dev;
1847 INIT_LIST_HEAD(&ring->active_list);
1848 INIT_LIST_HEAD(&ring->request_list);
e8616b6c
CW		 1849
1850 ring->size = size;
1851 ring->effective_size = ring->size;
17f10fdc 1852 if (IS_I830(ring->dev) || IS_845G(ring->dev))
e8616b6c
CW		 1853 ring->effective_size -= 128;
1854
4225d0f2
DV		 1855 ring->virtual_start = ioremap_wc(start, size);
1856 if (ring->virtual_start == NULL) {
e8616b6c
CW		 1857 DRM_ERROR("can not ioremap virtual address for"
1858 " ring buffer\n");
1859 return -ENOMEM;
1860 }
1861
6b8294a4 1862 if (!I915_NEED_GFX_HWS(dev)) {
035dc1e0 1863 ret = init_phys_status_page(ring);
6b8294a4
CW		 1864 if (ret)
1865 return ret;
1866 }
1867
e8616b6c
CW		 1868 return 0;
1869}
1870
5c1143bb
XH		 1871int intel_init_bsd_ring_buffer(struct drm_device *dev)
1872{
1873 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1874 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
5c1143bb 1875
58fa3835
DV		 1876 ring->name = "bsd ring";
1877 ring->id = VCS;
1878
0fd2c201 1879 ring->write_tail = ring_write_tail;
58fa3835
DV		 1880 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1881 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 1882 /* gen6 bsd needs a special wa for tail updates */
1883 if (IS_GEN6(dev))
1884 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 1885 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 1886 ring->add_request = gen6_add_request;
1887 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 1888 ring->set_seqno = ring_set_seqno;
cc609d5d 1889 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
58fa3835
DV		 1890 ring->irq_get = gen6_ring_get_irq;
1891 ring->irq_put = gen6_ring_put_irq;
1892 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
686cb5f9 1893 ring->sync_to = gen6_ring_sync;
5586181f
BW		 1894 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1895 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1896 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1950de14 1897 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
ad776f8b
BW		 1898 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1899 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1900 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1950de14 1901 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
58fa3835
DV		 1902 } else {
1903 ring->mmio_base = BSD_RING_BASE;
58fa3835 1904 ring->flush = bsd_ring_flush;
8620a3a9 1905 ring->add_request = i9xx_add_request;
58fa3835 1906 ring->get_seqno = ring_get_seqno;
b70ec5bf 1907 ring->set_seqno = ring_set_seqno;
e48d8634 1908 if (IS_GEN5(dev)) {
cc609d5d 1909 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 1910 ring->irq_get = gen5_ring_get_irq;
1911 ring->irq_put = gen5_ring_put_irq;
1912 } else {
e3670319 1913 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 1914 ring->irq_get = i9xx_ring_get_irq;
1915 ring->irq_put = i9xx_ring_put_irq;
1916 }
fb3256da 1917 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835
DV		 1918 }
1919 ring->init = init_ring_common;
1920
1ec14ad3 1921 return intel_init_ring_buffer(dev, ring);
5c1143bb 1922}
549f7365
CW		 1923
1924int intel_init_blt_ring_buffer(struct drm_device *dev)
1925{
1926 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1927 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
549f7365 1928
3535d9dd
DV		 1929 ring->name = "blitter ring";
1930 ring->id = BCS;
1931
1932 ring->mmio_base = BLT_RING_BASE;
1933 ring->write_tail = ring_write_tail;
ea251324 1934 ring->flush = gen6_ring_flush;
3535d9dd
DV		 1935 ring->add_request = gen6_add_request;
1936 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 1937 ring->set_seqno = ring_set_seqno;
cc609d5d 1938 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3535d9dd
DV		 1939 ring->irq_get = gen6_ring_get_irq;
1940 ring->irq_put = gen6_ring_put_irq;
1941 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
686cb5f9 1942 ring->sync_to = gen6_ring_sync;
5586181f
BW		 1943 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1944 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1945 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1950de14 1946 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
ad776f8b
BW		 1947 ring->signal_mbox[RCS] = GEN6_RBSYNC;
1948 ring->signal_mbox[VCS] = GEN6_VBSYNC;
1949 ring->signal_mbox[BCS] = GEN6_NOSYNC;
1950de14 1950 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
3535d9dd 1951 ring->init = init_ring_common;
549f7365 1952
1ec14ad3 1953 return intel_init_ring_buffer(dev, ring);
549f7365 1954}
a7b9761d 1955
9a8a2213
BW		 1956int intel_init_vebox_ring_buffer(struct drm_device *dev)
1957{
1958 drm_i915_private_t *dev_priv = dev->dev_private;
1959 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
1960
1961 ring->name = "video enhancement ring";
1962 ring->id = VECS;
1963
1964 ring->mmio_base = VEBOX_RING_BASE;
1965 ring->write_tail = ring_write_tail;
1966 ring->flush = gen6_ring_flush;
1967 ring->add_request = gen6_add_request;
1968 ring->get_seqno = gen6_ring_get_seqno;
1969 ring->set_seqno = ring_set_seqno;
c0d6a3dd 1970 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
a19d2933
BW		 1971 ring->irq_get = hsw_vebox_get_irq;
1972 ring->irq_put = hsw_vebox_put_irq;
9a8a2213
BW		 1973 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1974 ring->sync_to = gen6_ring_sync;
1975 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
1976 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
1977 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
1978 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
1979 ring->signal_mbox[RCS] = GEN6_RVESYNC;
1980 ring->signal_mbox[VCS] = GEN6_VVESYNC;
1981 ring->signal_mbox[BCS] = GEN6_BVESYNC;
1982 ring->signal_mbox[VECS] = GEN6_NOSYNC;
1983 ring->init = init_ring_common;
1984
1985 return intel_init_ring_buffer(dev, ring);
1986}
1987
a7b9761d
CW		 1988int
1989intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1990{
1991 int ret;
1992
1993 if (!ring->gpu_caches_dirty)
1994 return 0;
1995
1996 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1997 if (ret)
1998 return ret;
1999
2000 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2001
2002 ring->gpu_caches_dirty = false;
2003 return 0;
2004}
2005
2006int
2007intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2008{
2009 uint32_t flush_domains;
2010 int ret;
2011
2012 flush_domains = 0;
2013 if (ring->gpu_caches_dirty)
2014 flush_domains = I915_GEM_GPU_DOMAINS;
2015
2016 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2017 if (ret)
2018 return ret;
2019
2020 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2021
2022 ring->gpu_caches_dirty = false;
2023 return 0;
2024}
Linux kernel - Deliverables
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