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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b72f3acb | 61 | static int |
7c9cf4e3 | 62 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 63 | { |
7e37f889 | 64 | struct intel_ring *ring = req->ring; |
46f0f8d1 CW |
65 | u32 cmd; |
66 | int ret; | |
67 | ||
68 | cmd = MI_FLUSH; | |
46f0f8d1 | 69 | |
7c9cf4e3 | 70 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
71 | cmd |= MI_READ_FLUSH; |
72 | ||
5fb9de1a | 73 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
74 | if (ret) |
75 | return ret; | |
76 | ||
b5321f30 CW |
77 | intel_ring_emit(ring, cmd); |
78 | intel_ring_emit(ring, MI_NOOP); | |
79 | intel_ring_advance(ring); | |
46f0f8d1 CW |
80 | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static int | |
7c9cf4e3 | 85 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 86 | { |
7e37f889 | 87 | struct intel_ring *ring = req->ring; |
6f392d54 | 88 | u32 cmd; |
b72f3acb | 89 | int ret; |
6f392d54 | 90 | |
36d527de CW |
91 | /* |
92 | * read/write caches: | |
93 | * | |
94 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
95 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
96 | * also flushed at 2d versus 3d pipeline switches. | |
97 | * | |
98 | * read-only caches: | |
99 | * | |
100 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
101 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
102 | * | |
103 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
104 | * | |
105 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
106 | * invalidated when MI_EXE_FLUSH is set. | |
107 | * | |
108 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
109 | * invalidated with every MI_FLUSH. | |
110 | * | |
111 | * TLBs: | |
112 | * | |
113 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
114 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
115 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
116 | * are flushed at any MI_FLUSH. | |
117 | */ | |
118 | ||
b5321f30 | 119 | cmd = MI_FLUSH; |
7c9cf4e3 | 120 | if (mode & EMIT_INVALIDATE) { |
36d527de | 121 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
122 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
123 | cmd |= MI_INVALIDATE_ISP; | |
124 | } | |
70eac33e | 125 | |
5fb9de1a | 126 | ret = intel_ring_begin(req, 2); |
36d527de CW |
127 | if (ret) |
128 | return ret; | |
b72f3acb | 129 | |
b5321f30 CW |
130 | intel_ring_emit(ring, cmd); |
131 | intel_ring_emit(ring, MI_NOOP); | |
132 | intel_ring_advance(ring); | |
b72f3acb CW |
133 | |
134 | return 0; | |
8187a2b7 ZN |
135 | } |
136 | ||
8d315287 JB |
137 | /** |
138 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
139 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
140 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
141 | * | |
142 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
143 | * produced by non-pipelined state commands), software needs to first | |
144 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
145 | * 0. | |
146 | * | |
147 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
148 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
149 | * | |
150 | * And the workaround for these two requires this workaround first: | |
151 | * | |
152 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
153 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
154 | * flushes. | |
155 | * | |
156 | * And this last workaround is tricky because of the requirements on | |
157 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
158 | * volume 2 part 1: | |
159 | * | |
160 | * "1 of the following must also be set: | |
161 | * - Render Target Cache Flush Enable ([12] of DW1) | |
162 | * - Depth Cache Flush Enable ([0] of DW1) | |
163 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
164 | * - Depth Stall ([13] of DW1) | |
165 | * - Post-Sync Operation ([13] of DW1) | |
166 | * - Notify Enable ([8] of DW1)" | |
167 | * | |
168 | * The cache flushes require the workaround flush that triggered this | |
169 | * one, so we can't use it. Depth stall would trigger the same. | |
170 | * Post-sync nonzero is what triggered this second workaround, so we | |
171 | * can't use that one either. Notify enable is IRQs, which aren't | |
172 | * really our business. That leaves only stall at scoreboard. | |
173 | */ | |
174 | static int | |
f2cf1fcc | 175 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 176 | { |
7e37f889 | 177 | struct intel_ring *ring = req->ring; |
b5321f30 | 178 | u32 scratch_addr = |
bde13ebd | 179 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
8d315287 JB |
180 | int ret; |
181 | ||
5fb9de1a | 182 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
183 | if (ret) |
184 | return ret; | |
185 | ||
b5321f30 CW |
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
8d315287 | 188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
b5321f30 CW |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
8d315287 | 194 | |
5fb9de1a | 195 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
196 | if (ret) |
197 | return ret; | |
198 | ||
b5321f30 CW |
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
8d315287 JB |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
7c9cf4e3 | 211 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 212 | { |
7e37f889 | 213 | struct intel_ring *ring = req->ring; |
b5321f30 | 214 | u32 scratch_addr = |
bde13ebd | 215 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
8d315287 | 216 | u32 flags = 0; |
8d315287 JB |
217 | int ret; |
218 | ||
b3111509 | 219 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 220 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
221 | if (ret) |
222 | return ret; | |
223 | ||
8d315287 JB |
224 | /* Just flush everything. Experiments have shown that reducing the |
225 | * number of bits based on the write domains has little performance | |
226 | * impact. | |
227 | */ | |
7c9cf4e3 | 228 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
229 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
231 | /* | |
232 | * Ensure that any following seqno writes only happen | |
233 | * when the render cache is indeed flushed. | |
234 | */ | |
97f209bc | 235 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 236 | } |
7c9cf4e3 | 237 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
238 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
239 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
244 | /* | |
245 | * TLB invalidate requires a post-sync write. | |
246 | */ | |
3ac78313 | 247 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 248 | } |
8d315287 | 249 | |
5fb9de1a | 250 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
251 | if (ret) |
252 | return ret; | |
253 | ||
b5321f30 CW |
254 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
255 | intel_ring_emit(ring, flags); | |
256 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | intel_ring_emit(ring, 0); | |
258 | intel_ring_advance(ring); | |
8d315287 JB |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
f3987631 | 263 | static int |
f2cf1fcc | 264 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 265 | { |
7e37f889 | 266 | struct intel_ring *ring = req->ring; |
f3987631 PZ |
267 | int ret; |
268 | ||
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
270 | if (ret) |
271 | return ret; | |
272 | ||
b5321f30 CW |
273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(ring, | |
275 | PIPE_CONTROL_CS_STALL | | |
276 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
277 | intel_ring_emit(ring, 0); | |
278 | intel_ring_emit(ring, 0); | |
279 | intel_ring_advance(ring); | |
f3987631 PZ |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
4772eaeb | 284 | static int |
7c9cf4e3 | 285 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 286 | { |
7e37f889 | 287 | struct intel_ring *ring = req->ring; |
b5321f30 | 288 | u32 scratch_addr = |
bde13ebd | 289 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
4772eaeb | 290 | u32 flags = 0; |
4772eaeb PZ |
291 | int ret; |
292 | ||
f3987631 PZ |
293 | /* |
294 | * Ensure that any following seqno writes only happen when the render | |
295 | * cache is indeed flushed. | |
296 | * | |
297 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
298 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
299 | * don't try to be clever and just set it unconditionally. | |
300 | */ | |
301 | flags |= PIPE_CONTROL_CS_STALL; | |
302 | ||
4772eaeb PZ |
303 | /* Just flush everything. Experiments have shown that reducing the |
304 | * number of bits based on the write domains has little performance | |
305 | * impact. | |
306 | */ | |
7c9cf4e3 | 307 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
308 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
309 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 310 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 311 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 312 | } |
7c9cf4e3 | 313 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
314 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
315 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
316 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
317 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
318 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
319 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 320 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
321 | /* |
322 | * TLB invalidate requires a post-sync write. | |
323 | */ | |
324 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 325 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 326 | |
add284a3 CW |
327 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
328 | ||
f3987631 PZ |
329 | /* Workaround: we must issue a pipe_control with CS-stall bit |
330 | * set before a pipe_control command that has the state cache | |
331 | * invalidate bit set. */ | |
f2cf1fcc | 332 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
333 | } |
334 | ||
5fb9de1a | 335 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
336 | if (ret) |
337 | return ret; | |
338 | ||
b5321f30 CW |
339 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
340 | intel_ring_emit(ring, flags); | |
341 | intel_ring_emit(ring, scratch_addr); | |
342 | intel_ring_emit(ring, 0); | |
343 | intel_ring_advance(ring); | |
4772eaeb PZ |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
884ceace | 348 | static int |
f2cf1fcc | 349 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
350 | u32 flags, u32 scratch_addr) |
351 | { | |
7e37f889 | 352 | struct intel_ring *ring = req->ring; |
884ceace KG |
353 | int ret; |
354 | ||
5fb9de1a | 355 | ret = intel_ring_begin(req, 6); |
884ceace KG |
356 | if (ret) |
357 | return ret; | |
358 | ||
b5321f30 CW |
359 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
360 | intel_ring_emit(ring, flags); | |
361 | intel_ring_emit(ring, scratch_addr); | |
362 | intel_ring_emit(ring, 0); | |
363 | intel_ring_emit(ring, 0); | |
364 | intel_ring_emit(ring, 0); | |
365 | intel_ring_advance(ring); | |
884ceace KG |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
a5f3d68e | 370 | static int |
7c9cf4e3 | 371 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
a5f3d68e | 372 | { |
56c0f1a7 | 373 | u32 scratch_addr = |
bde13ebd | 374 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
b5321f30 | 375 | u32 flags = 0; |
02c9f7e3 | 376 | int ret; |
a5f3d68e BW |
377 | |
378 | flags |= PIPE_CONTROL_CS_STALL; | |
379 | ||
7c9cf4e3 | 380 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
381 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
382 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 383 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 384 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 385 | } |
7c9cf4e3 | 386 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
387 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
388 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
389 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
390 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
391 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
392 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
393 | flags |= PIPE_CONTROL_QW_WRITE; | |
394 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
395 | |
396 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 397 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
398 | PIPE_CONTROL_CS_STALL | |
399 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
400 | 0); | |
401 | if (ret) | |
402 | return ret; | |
a5f3d68e BW |
403 | } |
404 | ||
f2cf1fcc | 405 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
406 | } |
407 | ||
7e37f889 | 408 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 409 | { |
c033666a | 410 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 411 | u64 acthd; |
8187a2b7 | 412 | |
c033666a | 413 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
414 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
415 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 416 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 417 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
418 | else |
419 | acthd = I915_READ(ACTHD); | |
420 | ||
421 | return acthd; | |
8187a2b7 ZN |
422 | } |
423 | ||
0bc40be8 | 424 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 425 | { |
c033666a | 426 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
427 | u32 addr; |
428 | ||
429 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 430 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
431 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
432 | I915_WRITE(HWS_PGA, addr); | |
433 | } | |
434 | ||
0bc40be8 | 435 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 436 | { |
c033666a | 437 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 438 | i915_reg_t mmio; |
af75f269 DL |
439 | |
440 | /* The ring status page addresses are no longer next to the rest of | |
441 | * the ring registers as of gen7. | |
442 | */ | |
c033666a | 443 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 444 | switch (engine->id) { |
af75f269 DL |
445 | case RCS: |
446 | mmio = RENDER_HWS_PGA_GEN7; | |
447 | break; | |
448 | case BCS: | |
449 | mmio = BLT_HWS_PGA_GEN7; | |
450 | break; | |
451 | /* | |
452 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
453 | * gcc switch check warning | |
454 | */ | |
455 | case VCS2: | |
456 | case VCS: | |
457 | mmio = BSD_HWS_PGA_GEN7; | |
458 | break; | |
459 | case VECS: | |
460 | mmio = VEBOX_HWS_PGA_GEN7; | |
461 | break; | |
462 | } | |
c033666a | 463 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 464 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
465 | } else { |
466 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 467 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
468 | } |
469 | ||
57e88531 | 470 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
471 | POSTING_READ(mmio); |
472 | ||
473 | /* | |
474 | * Flush the TLB for this page | |
475 | * | |
476 | * FIXME: These two bits have disappeared on gen8, so a question | |
477 | * arises: do we still need this and if so how should we go about | |
478 | * invalidating the TLB? | |
479 | */ | |
ac657f64 | 480 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 481 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
482 | |
483 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 484 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
485 | |
486 | I915_WRITE(reg, | |
487 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
488 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
489 | if (intel_wait_for_register(dev_priv, |
490 | reg, INSTPM_SYNC_FLUSH, 0, | |
491 | 1000)) | |
af75f269 | 492 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 493 | engine->name); |
af75f269 DL |
494 | } |
495 | } | |
496 | ||
0bc40be8 | 497 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 498 | { |
c033666a | 499 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 500 | |
21a2c58a | 501 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 502 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
503 | if (intel_wait_for_register(dev_priv, |
504 | RING_MI_MODE(engine->mmio_base), | |
505 | MODE_IDLE, | |
506 | MODE_IDLE, | |
507 | 1000)) { | |
0bc40be8 TU |
508 | DRM_ERROR("%s : timed out trying to stop ring\n", |
509 | engine->name); | |
9bec9b13 CW |
510 | /* Sometimes we observe that the idle flag is not |
511 | * set even though the ring is empty. So double | |
512 | * check before giving up. | |
513 | */ | |
0bc40be8 | 514 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 515 | return false; |
9991ae78 CW |
516 | } |
517 | } | |
b7884eb4 | 518 | |
0bc40be8 TU |
519 | I915_WRITE_CTL(engine, 0); |
520 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 521 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 522 | |
21a2c58a | 523 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
524 | (void)I915_READ_CTL(engine); |
525 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 526 | } |
a51435a3 | 527 | |
0bc40be8 | 528 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 529 | } |
8187a2b7 | 530 | |
0bc40be8 | 531 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 532 | { |
c033666a | 533 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 534 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
535 | int ret = 0; |
536 | ||
59bad947 | 537 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 538 | |
0bc40be8 | 539 | if (!stop_ring(engine)) { |
9991ae78 | 540 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
541 | DRM_DEBUG_KMS("%s head not reset to zero " |
542 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
543 | engine->name, |
544 | I915_READ_CTL(engine), | |
545 | I915_READ_HEAD(engine), | |
546 | I915_READ_TAIL(engine), | |
547 | I915_READ_START(engine)); | |
8187a2b7 | 548 | |
0bc40be8 | 549 | if (!stop_ring(engine)) { |
6fd0d56e CW |
550 | DRM_ERROR("failed to set %s head to zero " |
551 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
552 | engine->name, |
553 | I915_READ_CTL(engine), | |
554 | I915_READ_HEAD(engine), | |
555 | I915_READ_TAIL(engine), | |
556 | I915_READ_START(engine)); | |
9991ae78 CW |
557 | ret = -EIO; |
558 | goto out; | |
6fd0d56e | 559 | } |
8187a2b7 ZN |
560 | } |
561 | ||
c033666a | 562 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 563 | intel_ring_setup_status_page(engine); |
9991ae78 | 564 | else |
0bc40be8 | 565 | ring_setup_phys_status_page(engine); |
9991ae78 | 566 | |
ece4a17d | 567 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 568 | I915_READ_HEAD(engine); |
ece4a17d | 569 | |
0d8957c8 DV |
570 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
571 | * registers with the above sequence (the readback of the HEAD registers | |
572 | * also enforces ordering), otherwise the hw might lose the new ring | |
573 | * register values. */ | |
bde13ebd | 574 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
575 | |
576 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 577 | if (I915_READ_HEAD(engine)) |
95468892 | 578 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
579 | engine->name, I915_READ_HEAD(engine)); |
580 | I915_WRITE_HEAD(engine, 0); | |
581 | (void)I915_READ_HEAD(engine); | |
95468892 | 582 | |
0bc40be8 | 583 | I915_WRITE_CTL(engine, |
7e37f889 | 584 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 585 | | RING_VALID); |
8187a2b7 | 586 | |
8187a2b7 | 587 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 | 588 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
bde13ebd | 589 | I915_READ_START(engine) == i915_ggtt_offset(ring->vma) && |
0bc40be8 | 590 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 591 | DRM_ERROR("%s initialization failed " |
bde13ebd | 592 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08x]\n", |
0bc40be8 TU |
593 | engine->name, |
594 | I915_READ_CTL(engine), | |
595 | I915_READ_CTL(engine) & RING_VALID, | |
596 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
597 | I915_READ_START(engine), | |
bde13ebd | 598 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
599 | ret = -EIO; |
600 | goto out; | |
8187a2b7 ZN |
601 | } |
602 | ||
7e37f889 CW |
603 | ring->last_retired_head = -1; |
604 | ring->head = I915_READ_HEAD(engine); | |
605 | ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
606 | intel_ring_update_space(ring); | |
1ec14ad3 | 607 | |
fc0768ce | 608 | intel_engine_init_hangcheck(engine); |
50f018df | 609 | |
b7884eb4 | 610 | out: |
59bad947 | 611 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
612 | |
613 | return ret; | |
8187a2b7 ZN |
614 | } |
615 | ||
e2be4faf | 616 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 617 | { |
7e37f889 | 618 | struct intel_ring *ring = req->ring; |
c033666a CW |
619 | struct i915_workarounds *w = &req->i915->workarounds; |
620 | int ret, i; | |
888b5995 | 621 | |
02235808 | 622 | if (w->count == 0) |
7225342a | 623 | return 0; |
888b5995 | 624 | |
7c9cf4e3 | 625 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
626 | if (ret) |
627 | return ret; | |
888b5995 | 628 | |
5fb9de1a | 629 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
630 | if (ret) |
631 | return ret; | |
632 | ||
b5321f30 | 633 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 634 | for (i = 0; i < w->count; i++) { |
b5321f30 CW |
635 | intel_ring_emit_reg(ring, w->reg[i].addr); |
636 | intel_ring_emit(ring, w->reg[i].value); | |
7225342a | 637 | } |
b5321f30 | 638 | intel_ring_emit(ring, MI_NOOP); |
7225342a | 639 | |
b5321f30 | 640 | intel_ring_advance(ring); |
7225342a | 641 | |
7c9cf4e3 | 642 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
643 | if (ret) |
644 | return ret; | |
888b5995 | 645 | |
7225342a | 646 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 647 | |
7225342a | 648 | return 0; |
86d7f238 AS |
649 | } |
650 | ||
8753181e | 651 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
652 | { |
653 | int ret; | |
654 | ||
e2be4faf | 655 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
656 | if (ret != 0) |
657 | return ret; | |
658 | ||
be01363f | 659 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 660 | if (ret) |
e26e1b97 | 661 | return ret; |
8f0e2b9d | 662 | |
e26e1b97 | 663 | return 0; |
8f0e2b9d DV |
664 | } |
665 | ||
7225342a | 666 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
667 | i915_reg_t addr, |
668 | const u32 mask, const u32 val) | |
7225342a MK |
669 | { |
670 | const u32 idx = dev_priv->workarounds.count; | |
671 | ||
672 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
673 | return -ENOSPC; | |
674 | ||
675 | dev_priv->workarounds.reg[idx].addr = addr; | |
676 | dev_priv->workarounds.reg[idx].value = val; | |
677 | dev_priv->workarounds.reg[idx].mask = mask; | |
678 | ||
679 | dev_priv->workarounds.count++; | |
680 | ||
681 | return 0; | |
86d7f238 AS |
682 | } |
683 | ||
ca5a0fbd | 684 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 685 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
686 | if (r) \ |
687 | return r; \ | |
ca5a0fbd | 688 | } while (0) |
7225342a MK |
689 | |
690 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 691 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
692 | |
693 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 694 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 695 | |
98533251 | 696 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 697 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 698 | |
cf4b0de6 DL |
699 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
700 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 701 | |
cf4b0de6 | 702 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 703 | |
0bc40be8 TU |
704 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
705 | i915_reg_t reg) | |
33136b06 | 706 | { |
c033666a | 707 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 708 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 709 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
710 | |
711 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
712 | return -EINVAL; | |
713 | ||
0bc40be8 | 714 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 715 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 716 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
717 | |
718 | return 0; | |
719 | } | |
720 | ||
0bc40be8 | 721 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 722 | { |
c033666a | 723 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
724 | |
725 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 726 | |
717d84d6 AS |
727 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
728 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
729 | ||
d0581194 AS |
730 | /* WaDisablePartialInstShootdown:bdw,chv */ |
731 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
732 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
733 | ||
a340af58 AS |
734 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
735 | * workaround for for a possible hang in the unlikely event a TLB | |
736 | * invalidation occurs during a PSD flush. | |
737 | */ | |
738 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 739 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 740 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 741 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
742 | HDC_FORCE_NON_COHERENT); |
743 | ||
6def8fdd AS |
744 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
745 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
746 | * polygons in the same 8x4 pixel/sample area to be processed without | |
747 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
748 | * buffer." | |
749 | * | |
750 | * This optimization is off by default for BDW and CHV; turn it on. | |
751 | */ | |
752 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
753 | ||
48404636 AS |
754 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
755 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
756 | ||
7eebcde6 AS |
757 | /* |
758 | * BSpec recommends 8x4 when MSAA is used, | |
759 | * however in practice 16x4 seems fastest. | |
760 | * | |
761 | * Note that PS/WM thread counts depend on the WIZ hashing | |
762 | * disable bit, which we don't touch here, but it's good | |
763 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
764 | */ | |
765 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
766 | GEN6_WIZ_HASHING_MASK, | |
767 | GEN6_WIZ_HASHING_16x4); | |
768 | ||
e9a64ada AS |
769 | return 0; |
770 | } | |
771 | ||
0bc40be8 | 772 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 773 | { |
c033666a | 774 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 775 | int ret; |
86d7f238 | 776 | |
0bc40be8 | 777 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
778 | if (ret) |
779 | return ret; | |
780 | ||
101b376d | 781 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 782 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 783 | |
101b376d | 784 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
785 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
786 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 787 | |
7225342a MK |
788 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
789 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 790 | |
7225342a | 791 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
792 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
793 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 794 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 795 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 796 | |
86d7f238 AS |
797 | return 0; |
798 | } | |
799 | ||
0bc40be8 | 800 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 801 | { |
c033666a | 802 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 803 | int ret; |
00e1e623 | 804 | |
0bc40be8 | 805 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
806 | if (ret) |
807 | return ret; | |
808 | ||
00e1e623 | 809 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 810 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 811 | |
d60de81d KG |
812 | /* Improve HiZ throughput on CHV. */ |
813 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
814 | ||
7225342a MK |
815 | return 0; |
816 | } | |
817 | ||
0bc40be8 | 818 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 819 | { |
c033666a | 820 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 821 | int ret; |
ab0dfafe | 822 | |
a8ab5ed5 TG |
823 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
824 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
825 | ||
e5f81d65 | 826 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
827 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
828 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
829 | ||
e5f81d65 | 830 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
831 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
832 | ECOCHK_DIS_TLB); | |
833 | ||
e5f81d65 MK |
834 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
835 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 836 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 837 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
838 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
839 | ||
e5f81d65 | 840 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
841 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
842 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
843 | ||
e87a005d | 844 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
845 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
846 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
847 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
848 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 849 | |
e87a005d | 850 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
851 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
852 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
853 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
854 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
855 | /* |
856 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
857 | * but we do that in per ctx batchbuffer as there is an issue | |
858 | * with this register not getting restored on ctx restore | |
859 | */ | |
183c6dac DL |
860 | } |
861 | ||
e5f81d65 MK |
862 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
863 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
864 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
865 | GEN9_ENABLE_YV12_BUGFIX | | |
866 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 867 | |
e5f81d65 MK |
868 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
869 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
870 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
871 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 872 | |
e5f81d65 | 873 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
874 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
875 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
876 | ||
5a2ae95e | 877 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
878 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
879 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
880 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
881 | PIXEL_MASK_CAMMING_DISABLE); | |
882 | ||
5b0e3659 MK |
883 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
884 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
885 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
886 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 887 | |
bbaefe72 MK |
888 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
889 | * both tied to WaForceContextSaveRestoreNonCoherent | |
890 | * in some hsds for skl. We keep the tie for all gen9. The | |
891 | * documentation is a bit hazy and so we want to get common behaviour, | |
892 | * even though there is no clear evidence we would need both on kbl/bxt. | |
893 | * This area has been source of system hangs so we play it safe | |
894 | * and mimic the skl regardless of what bspec says. | |
895 | * | |
896 | * Use Force Non-Coherent whenever executing a 3D context. This | |
897 | * is a workaround for a possible hang in the unlikely event | |
898 | * a TLB invalidation occurs during a PSD flush. | |
899 | */ | |
900 | ||
901 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
902 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
903 | HDC_FORCE_NON_COHERENT); | |
904 | ||
905 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
906 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
907 | BDW_DISABLE_HDC_INVALIDATION); | |
908 | ||
e5f81d65 MK |
909 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
910 | if (IS_SKYLAKE(dev_priv) || | |
911 | IS_KABYLAKE(dev_priv) || | |
912 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
913 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
914 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 915 | |
e5f81d65 | 916 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
917 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
918 | ||
e5f81d65 | 919 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
920 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
921 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
922 | ||
6bb62855 | 923 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
924 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
925 | if (ret) | |
926 | return ret; | |
927 | ||
e5f81d65 | 928 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 929 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
930 | if (ret) |
931 | return ret; | |
932 | ||
e5f81d65 | 933 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 934 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
935 | if (ret) |
936 | return ret; | |
937 | ||
3b106531 HN |
938 | return 0; |
939 | } | |
940 | ||
0bc40be8 | 941 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 942 | { |
c033666a | 943 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
944 | u8 vals[3] = { 0, 0, 0 }; |
945 | unsigned int i; | |
946 | ||
947 | for (i = 0; i < 3; i++) { | |
948 | u8 ss; | |
949 | ||
950 | /* | |
951 | * Only consider slices where one, and only one, subslice has 7 | |
952 | * EUs | |
953 | */ | |
a4d8a0fe | 954 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
955 | continue; |
956 | ||
957 | /* | |
958 | * subslice_7eu[i] != 0 (because of the check above) and | |
959 | * ss_max == 4 (maximum number of subslices possible per slice) | |
960 | * | |
961 | * -> 0 <= ss <= 3; | |
962 | */ | |
963 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
964 | vals[i] = 3 - ss; | |
965 | } | |
966 | ||
967 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
968 | return 0; | |
969 | ||
970 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
971 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
972 | GEN9_IZ_HASHING_MASK(2) | | |
973 | GEN9_IZ_HASHING_MASK(1) | | |
974 | GEN9_IZ_HASHING_MASK(0), | |
975 | GEN9_IZ_HASHING(2, vals[2]) | | |
976 | GEN9_IZ_HASHING(1, vals[1]) | | |
977 | GEN9_IZ_HASHING(0, vals[0])); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
0bc40be8 | 982 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 983 | { |
c033666a | 984 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 985 | int ret; |
d0bbbc4f | 986 | |
0bc40be8 | 987 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
988 | if (ret) |
989 | return ret; | |
8d205494 | 990 | |
a78536e7 AS |
991 | /* |
992 | * Actual WA is to disable percontext preemption granularity control | |
993 | * until D0 which is the default case so this is equivalent to | |
994 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
995 | */ | |
c033666a | 996 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
997 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
998 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
999 | } | |
1000 | ||
71dce58c | 1001 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1002 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1003 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1004 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1005 | } | |
1006 | ||
1007 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1008 | * involving this register should also be added to WA batch as required. | |
1009 | */ | |
c033666a | 1010 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1011 | /* WaDisableLSQCROPERFforOCL:skl */ |
1012 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1013 | GEN8_LQSC_RO_PERF_DIS); | |
1014 | ||
1015 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1016 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1017 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1018 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1019 | } | |
1020 | ||
d0bbbc4f | 1021 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1022 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1023 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1024 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1025 | ||
e87a005d | 1026 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1027 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1028 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1029 | HDC_FENCE_DEST_SLM_DISABLE | | |
1030 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1031 | ||
9bd9dfb4 | 1032 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1033 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1034 | WA_SET_BIT_MASKED( |
1035 | GEN7_HALF_SLICE_CHICKEN1, | |
1036 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1037 | |
eee8efb0 MK |
1038 | /* WaDisableGafsUnitClkGating:skl */ |
1039 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1040 | ||
4ba9c1f7 MK |
1041 | /* WaInPlaceDecompressionHang:skl */ |
1042 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
1043 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1044 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1045 | ||
6107497e | 1046 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1047 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1048 | if (ret) |
1049 | return ret; | |
1050 | ||
0bc40be8 | 1051 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1052 | } |
1053 | ||
0bc40be8 | 1054 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1055 | { |
c033666a | 1056 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1057 | int ret; |
dfb601e6 | 1058 | |
0bc40be8 | 1059 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1060 | if (ret) |
1061 | return ret; | |
cae0437f | 1062 | |
9c4cbf82 MK |
1063 | /* WaStoreMultiplePTEenable:bxt */ |
1064 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1065 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1066 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1067 | ||
1068 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1069 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1070 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1071 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1072 | } | |
1073 | ||
dfb601e6 NH |
1074 | /* WaDisableThreadStallDopClockGating:bxt */ |
1075 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1076 | STALL_DOP_GATING_DISABLE); | |
1077 | ||
780f0aeb | 1078 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1079 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1080 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1081 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1082 | } | |
1083 | ||
983b4b9d | 1084 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1085 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1086 | WA_SET_BIT_MASKED( |
1087 | GEN7_HALF_SLICE_CHICKEN1, | |
1088 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1089 | } | |
1090 | ||
2c8580e4 AS |
1091 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1092 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1093 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1094 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1095 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1096 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1097 | if (ret) |
1098 | return ret; | |
a786d53a | 1099 | |
0bc40be8 | 1100 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1101 | if (ret) |
1102 | return ret; | |
2c8580e4 AS |
1103 | } |
1104 | ||
050fc465 | 1105 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1106 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1107 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1108 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1109 | |
575e3ccb MA |
1110 | /* WaToEnableHwFixForPushConstHWBug:bxt */ |
1111 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1112 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1113 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1114 | ||
4ba9c1f7 MK |
1115 | /* WaInPlaceDecompressionHang:bxt */ |
1116 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1117 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1118 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1119 | ||
cae0437f NH |
1120 | return 0; |
1121 | } | |
1122 | ||
e5f81d65 MK |
1123 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1124 | { | |
e587f6cb | 1125 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1126 | int ret; |
1127 | ||
1128 | ret = gen9_init_workarounds(engine); | |
1129 | if (ret) | |
1130 | return ret; | |
1131 | ||
e587f6cb MK |
1132 | /* WaEnableGapsTsvCreditFix:kbl */ |
1133 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1134 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1135 | ||
c0b730d5 MK |
1136 | /* WaDisableDynamicCreditSharing:kbl */ |
1137 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1138 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1139 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1140 | ||
8401d42f MK |
1141 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1142 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1143 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1144 | HDC_FENCE_DEST_SLM_DISABLE); | |
1145 | ||
fe905819 MK |
1146 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1147 | * involving this register should also be added to WA batch as required. | |
1148 | */ | |
1149 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1150 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1151 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1152 | GEN8_LQSC_RO_PERF_DIS); | |
1153 | ||
575e3ccb MA |
1154 | /* WaToEnableHwFixForPushConstHWBug:kbl */ |
1155 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1156 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1157 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1158 | ||
4de5d7cc MK |
1159 | /* WaDisableGafsUnitClkGating:kbl */ |
1160 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1161 | ||
954337aa MK |
1162 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1163 | WA_SET_BIT_MASKED( | |
1164 | GEN7_HALF_SLICE_CHICKEN1, | |
1165 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1166 | ||
4ba9c1f7 MK |
1167 | /* WaInPlaceDecompressionHang:kbl */ |
1168 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1169 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1170 | ||
fe905819 MK |
1171 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1172 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1173 | if (ret) | |
1174 | return ret; | |
1175 | ||
e5f81d65 MK |
1176 | return 0; |
1177 | } | |
1178 | ||
0bc40be8 | 1179 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1180 | { |
c033666a | 1181 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1182 | |
0bc40be8 | 1183 | WARN_ON(engine->id != RCS); |
7225342a MK |
1184 | |
1185 | dev_priv->workarounds.count = 0; | |
33136b06 | 1186 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1187 | |
c033666a | 1188 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1189 | return bdw_init_workarounds(engine); |
7225342a | 1190 | |
c033666a | 1191 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1192 | return chv_init_workarounds(engine); |
00e1e623 | 1193 | |
c033666a | 1194 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1195 | return skl_init_workarounds(engine); |
cae0437f | 1196 | |
c033666a | 1197 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1198 | return bxt_init_workarounds(engine); |
3b106531 | 1199 | |
e5f81d65 MK |
1200 | if (IS_KABYLAKE(dev_priv)) |
1201 | return kbl_init_workarounds(engine); | |
1202 | ||
00e1e623 VS |
1203 | return 0; |
1204 | } | |
1205 | ||
0bc40be8 | 1206 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1207 | { |
c033666a | 1208 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1209 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1210 | if (ret) |
1211 | return ret; | |
a69ffdbf | 1212 | |
61a563a2 | 1213 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1214 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1215 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1216 | |
1217 | /* We need to disable the AsyncFlip performance optimisations in order | |
1218 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1219 | * programmed to '1' on all products. | |
8693a824 | 1220 | * |
2441f877 | 1221 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1222 | */ |
ac657f64 | 1223 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1224 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1225 | ||
f05bb0c7 | 1226 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1227 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1228 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1229 | I915_WRITE(GFX_MODE, |
aa83e30d | 1230 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1231 | |
01fa0302 | 1232 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1233 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1234 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1235 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1236 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1237 | |
c033666a | 1238 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1239 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1240 | * "If this bit is set, STCunit will have LRA as replacement | |
1241 | * policy. [...] This bit must be reset. LRA replacement | |
1242 | * policy is not supported." | |
1243 | */ | |
1244 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1245 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1246 | } |
1247 | ||
ac657f64 | 1248 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1249 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1250 | |
035ea405 VS |
1251 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1252 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1253 | |
0bc40be8 | 1254 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1255 | } |
1256 | ||
0bc40be8 | 1257 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1258 | { |
c033666a | 1259 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 1260 | |
19880c4a | 1261 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
1262 | } |
1263 | ||
ad7bdb2b | 1264 | static int gen8_rcs_signal(struct drm_i915_gem_request *req) |
3e78998a | 1265 | { |
ad7bdb2b CW |
1266 | struct intel_ring *ring = req->ring; |
1267 | struct drm_i915_private *dev_priv = req->i915; | |
3e78998a | 1268 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1269 | enum intel_engine_id id; |
1270 | int ret, num_rings; | |
3e78998a | 1271 | |
c1bb1145 | 1272 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1273 | ret = intel_ring_begin(req, (num_rings-1) * 8); |
3e78998a BW |
1274 | if (ret) |
1275 | return ret; | |
1276 | ||
c3232b18 | 1277 | for_each_engine_id(waiter, dev_priv, id) { |
ad7bdb2b | 1278 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1279 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1280 | continue; | |
1281 | ||
ad7bdb2b CW |
1282 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1283 | intel_ring_emit(ring, | |
b5321f30 CW |
1284 | PIPE_CONTROL_GLOBAL_GTT_IVB | |
1285 | PIPE_CONTROL_QW_WRITE | | |
1286 | PIPE_CONTROL_CS_STALL); | |
ad7bdb2b CW |
1287 | intel_ring_emit(ring, lower_32_bits(gtt_offset)); |
1288 | intel_ring_emit(ring, upper_32_bits(gtt_offset)); | |
1289 | intel_ring_emit(ring, req->fence.seqno); | |
1290 | intel_ring_emit(ring, 0); | |
1291 | intel_ring_emit(ring, | |
b5321f30 CW |
1292 | MI_SEMAPHORE_SIGNAL | |
1293 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
ad7bdb2b | 1294 | intel_ring_emit(ring, 0); |
3e78998a | 1295 | } |
ad7bdb2b | 1296 | intel_ring_advance(ring); |
3e78998a BW |
1297 | |
1298 | return 0; | |
1299 | } | |
1300 | ||
ad7bdb2b | 1301 | static int gen8_xcs_signal(struct drm_i915_gem_request *req) |
3e78998a | 1302 | { |
ad7bdb2b CW |
1303 | struct intel_ring *ring = req->ring; |
1304 | struct drm_i915_private *dev_priv = req->i915; | |
3e78998a | 1305 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1306 | enum intel_engine_id id; |
1307 | int ret, num_rings; | |
3e78998a | 1308 | |
c1bb1145 | 1309 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1310 | ret = intel_ring_begin(req, (num_rings-1) * 6); |
3e78998a BW |
1311 | if (ret) |
1312 | return ret; | |
1313 | ||
c3232b18 | 1314 | for_each_engine_id(waiter, dev_priv, id) { |
ad7bdb2b | 1315 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1316 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1317 | continue; | |
1318 | ||
ad7bdb2b | 1319 | intel_ring_emit(ring, |
b5321f30 | 1320 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
ad7bdb2b | 1321 | intel_ring_emit(ring, |
b5321f30 CW |
1322 | lower_32_bits(gtt_offset) | |
1323 | MI_FLUSH_DW_USE_GTT); | |
ad7bdb2b CW |
1324 | intel_ring_emit(ring, upper_32_bits(gtt_offset)); |
1325 | intel_ring_emit(ring, req->fence.seqno); | |
1326 | intel_ring_emit(ring, | |
b5321f30 CW |
1327 | MI_SEMAPHORE_SIGNAL | |
1328 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
ad7bdb2b | 1329 | intel_ring_emit(ring, 0); |
3e78998a | 1330 | } |
ad7bdb2b | 1331 | intel_ring_advance(ring); |
3e78998a BW |
1332 | |
1333 | return 0; | |
1334 | } | |
1335 | ||
ad7bdb2b | 1336 | static int gen6_signal(struct drm_i915_gem_request *req) |
1ec14ad3 | 1337 | { |
ad7bdb2b CW |
1338 | struct intel_ring *ring = req->ring; |
1339 | struct drm_i915_private *dev_priv = req->i915; | |
318f89ca | 1340 | struct intel_engine_cs *engine; |
c3232b18 | 1341 | int ret, num_rings; |
78325f2d | 1342 | |
c1bb1145 | 1343 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1344 | ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2)); |
024a43e1 BW |
1345 | if (ret) |
1346 | return ret; | |
024a43e1 | 1347 | |
318f89ca TU |
1348 | for_each_engine(engine, dev_priv) { |
1349 | i915_reg_t mbox_reg; | |
1350 | ||
1351 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
1352 | continue; | |
f0f59a00 | 1353 | |
318f89ca | 1354 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 1355 | if (i915_mmio_reg_valid(mbox_reg)) { |
ad7bdb2b CW |
1356 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
1357 | intel_ring_emit_reg(ring, mbox_reg); | |
1358 | intel_ring_emit(ring, req->fence.seqno); | |
78325f2d BW |
1359 | } |
1360 | } | |
024a43e1 | 1361 | |
a1444b79 BW |
1362 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1363 | if (num_rings % 2 == 0) | |
ad7bdb2b CW |
1364 | intel_ring_emit(ring, MI_NOOP); |
1365 | intel_ring_advance(ring); | |
a1444b79 | 1366 | |
024a43e1 | 1367 | return 0; |
1ec14ad3 CW |
1368 | } |
1369 | ||
b0411e7d CW |
1370 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
1371 | { | |
1372 | struct drm_i915_private *dev_priv = request->i915; | |
1373 | ||
1374 | I915_WRITE_TAIL(request->engine, | |
1375 | intel_ring_offset(request->ring, request->tail)); | |
1376 | } | |
1377 | ||
1378 | static int i9xx_emit_request(struct drm_i915_gem_request *req) | |
1ec14ad3 | 1379 | { |
7e37f889 | 1380 | struct intel_ring *ring = req->ring; |
024a43e1 | 1381 | int ret; |
52ed2325 | 1382 | |
9242f974 | 1383 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1384 | if (ret) |
1385 | return ret; | |
1386 | ||
b5321f30 CW |
1387 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1388 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1389 | intel_ring_emit(ring, req->fence.seqno); | |
1390 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
c5efa1ad CW |
1391 | intel_ring_advance(ring); |
1392 | ||
1393 | req->tail = ring->tail; | |
1ec14ad3 | 1394 | |
1ec14ad3 CW |
1395 | return 0; |
1396 | } | |
1397 | ||
b0411e7d | 1398 | /** |
618e4ca7 | 1399 | * gen6_sema_emit_request - Update the semaphore mailbox registers |
b0411e7d CW |
1400 | * |
1401 | * @request - request to write to the ring | |
1402 | * | |
1403 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1404 | * This acts like a signal in the canonical semaphore. | |
1405 | */ | |
618e4ca7 | 1406 | static int gen6_sema_emit_request(struct drm_i915_gem_request *req) |
b0411e7d | 1407 | { |
618e4ca7 | 1408 | int ret; |
b0411e7d | 1409 | |
618e4ca7 CW |
1410 | ret = req->engine->semaphore.signal(req); |
1411 | if (ret) | |
1412 | return ret; | |
b0411e7d CW |
1413 | |
1414 | return i9xx_emit_request(req); | |
1415 | } | |
1416 | ||
ddd66c51 | 1417 | static int gen8_render_emit_request(struct drm_i915_gem_request *req) |
a58c01aa CW |
1418 | { |
1419 | struct intel_engine_cs *engine = req->engine; | |
7e37f889 | 1420 | struct intel_ring *ring = req->ring; |
a58c01aa CW |
1421 | int ret; |
1422 | ||
9242f974 CW |
1423 | if (engine->semaphore.signal) { |
1424 | ret = engine->semaphore.signal(req); | |
1425 | if (ret) | |
1426 | return ret; | |
1427 | } | |
1428 | ||
1429 | ret = intel_ring_begin(req, 8); | |
a58c01aa CW |
1430 | if (ret) |
1431 | return ret; | |
1432 | ||
b5321f30 CW |
1433 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1434 | intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1435 | PIPE_CONTROL_CS_STALL | | |
1436 | PIPE_CONTROL_QW_WRITE)); | |
1437 | intel_ring_emit(ring, intel_hws_seqno_address(engine)); | |
1438 | intel_ring_emit(ring, 0); | |
1439 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); | |
a58c01aa | 1440 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1441 | intel_ring_emit(ring, 0); |
1442 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1443 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1444 | intel_ring_advance(ring); |
c5efa1ad CW |
1445 | |
1446 | req->tail = ring->tail; | |
a58c01aa CW |
1447 | |
1448 | return 0; | |
1449 | } | |
1450 | ||
c8c99b0f BW |
1451 | /** |
1452 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1453 | * | |
1454 | * @waiter - ring that is waiting | |
1455 | * @signaller - ring which has, or will signal | |
1456 | * @seqno - seqno which the waiter will block on | |
1457 | */ | |
5ee426ca BW |
1458 | |
1459 | static int | |
ad7bdb2b CW |
1460 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
1461 | struct drm_i915_gem_request *signal) | |
5ee426ca | 1462 | { |
ad7bdb2b CW |
1463 | struct intel_ring *ring = req->ring; |
1464 | struct drm_i915_private *dev_priv = req->i915; | |
1465 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 1466 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1467 | int ret; |
1468 | ||
ad7bdb2b | 1469 | ret = intel_ring_begin(req, 4); |
5ee426ca BW |
1470 | if (ret) |
1471 | return ret; | |
1472 | ||
ad7bdb2b CW |
1473 | intel_ring_emit(ring, |
1474 | MI_SEMAPHORE_WAIT | | |
1475 | MI_SEMAPHORE_GLOBAL_GTT | | |
1476 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1477 | intel_ring_emit(ring, signal->fence.seqno); | |
1478 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1479 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1480 | intel_ring_advance(ring); | |
6ef48d7f CW |
1481 | |
1482 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1483 | * pagetables and we must reload them before executing the batch. | |
1484 | * We do this on the i915_switch_context() following the wait and | |
1485 | * before the dispatch. | |
1486 | */ | |
ad7bdb2b CW |
1487 | ppgtt = req->ctx->ppgtt; |
1488 | if (ppgtt && req->engine->id != RCS) | |
1489 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
1490 | return 0; |
1491 | } | |
1492 | ||
c8c99b0f | 1493 | static int |
ad7bdb2b CW |
1494 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
1495 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 1496 | { |
ad7bdb2b | 1497 | struct intel_ring *ring = req->ring; |
c8c99b0f BW |
1498 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1499 | MI_SEMAPHORE_COMPARE | | |
1500 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 1501 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
ebc348b2 | 1502 | int ret; |
1ec14ad3 | 1503 | |
ebc348b2 | 1504 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1505 | |
ad7bdb2b | 1506 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1507 | if (ret) |
1508 | return ret; | |
1509 | ||
ad7bdb2b | 1510 | intel_ring_emit(ring, dw1 | wait_mbox); |
ddf07be7 CW |
1511 | /* Throughout all of the GEM code, seqno passed implies our current |
1512 | * seqno is >= the last seqno executed. However for hardware the | |
1513 | * comparison is strictly greater than. | |
1514 | */ | |
ad7bdb2b CW |
1515 | intel_ring_emit(ring, signal->fence.seqno - 1); |
1516 | intel_ring_emit(ring, 0); | |
1517 | intel_ring_emit(ring, MI_NOOP); | |
1518 | intel_ring_advance(ring); | |
1ec14ad3 CW |
1519 | |
1520 | return 0; | |
1521 | } | |
1522 | ||
f8973c21 | 1523 | static void |
38a0f2db | 1524 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 1525 | { |
f8973c21 CW |
1526 | /* MI_STORE are internally buffered by the GPU and not flushed |
1527 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1528 | * MI commands. | |
c6df541c | 1529 | * |
f8973c21 CW |
1530 | * "Only the submission of the store operation is guaranteed. |
1531 | * The write result will be complete (coherent) some time later | |
1532 | * (this is practically a finite period but there is no guaranteed | |
1533 | * latency)." | |
1534 | * | |
1535 | * Empirically, we observe that we need a delay of at least 75us to | |
1536 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1537 | */ |
f8973c21 | 1538 | usleep_range(125, 250); |
c6df541c CW |
1539 | } |
1540 | ||
c04e0f3b CW |
1541 | static void |
1542 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1543 | { |
c033666a | 1544 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1545 | |
4cd53c0c DV |
1546 | /* Workaround to force correct ordering between irq and seqno writes on |
1547 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1548 | * ACTHD) before reading the status page. |
1549 | * | |
1550 | * Note that this effectively stalls the read by the time it takes to | |
1551 | * do a memory transaction, which more or less ensures that the write | |
1552 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1553 | * Alternatively we could delay the interrupt from the CS ring to give | |
1554 | * the write time to land, but that would incur a delay after every | |
1555 | * batch i.e. much more frequent than a delay when waiting for the | |
1556 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1557 | * |
1558 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1559 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1560 | */ |
bcbdb6d0 | 1561 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1562 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1563 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1564 | } |
1565 | ||
31bb59cc CW |
1566 | static void |
1567 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1568 | { |
31bb59cc | 1569 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1570 | } |
1571 | ||
1572 | static void | |
31bb59cc | 1573 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1574 | { |
31bb59cc | 1575 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1576 | } |
1577 | ||
31bb59cc CW |
1578 | static void |
1579 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1580 | { |
c033666a | 1581 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1582 | |
31bb59cc CW |
1583 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1584 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1585 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1586 | } |
1587 | ||
8187a2b7 | 1588 | static void |
31bb59cc | 1589 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1590 | { |
c033666a | 1591 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1592 | |
31bb59cc CW |
1593 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1594 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1595 | } |
1596 | ||
31bb59cc CW |
1597 | static void |
1598 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1599 | { |
c033666a | 1600 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1601 | |
31bb59cc CW |
1602 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1603 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1604 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1605 | } |
1606 | ||
1607 | static void | |
31bb59cc | 1608 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1609 | { |
c033666a | 1610 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1611 | |
31bb59cc CW |
1612 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1613 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1614 | } |
1615 | ||
b72f3acb | 1616 | static int |
7c9cf4e3 | 1617 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1618 | { |
7e37f889 | 1619 | struct intel_ring *ring = req->ring; |
b72f3acb CW |
1620 | int ret; |
1621 | ||
5fb9de1a | 1622 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1623 | if (ret) |
1624 | return ret; | |
1625 | ||
b5321f30 CW |
1626 | intel_ring_emit(ring, MI_FLUSH); |
1627 | intel_ring_emit(ring, MI_NOOP); | |
1628 | intel_ring_advance(ring); | |
b72f3acb | 1629 | return 0; |
d1b851fc ZN |
1630 | } |
1631 | ||
31bb59cc CW |
1632 | static void |
1633 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1634 | { |
c033666a | 1635 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1636 | |
61ff75ac CW |
1637 | I915_WRITE_IMR(engine, |
1638 | ~(engine->irq_enable_mask | | |
1639 | engine->irq_keep_mask)); | |
31bb59cc | 1640 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1641 | } |
1642 | ||
1643 | static void | |
31bb59cc | 1644 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1645 | { |
c033666a | 1646 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1647 | |
61ff75ac | 1648 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1649 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1650 | } |
1651 | ||
31bb59cc CW |
1652 | static void |
1653 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1654 | { |
c033666a | 1655 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1656 | |
31bb59cc CW |
1657 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1658 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1659 | } |
1660 | ||
1661 | static void | |
31bb59cc | 1662 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1663 | { |
c033666a | 1664 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1665 | |
31bb59cc CW |
1666 | I915_WRITE_IMR(engine, ~0); |
1667 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1668 | } |
1669 | ||
31bb59cc CW |
1670 | static void |
1671 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1672 | { |
c033666a | 1673 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1674 | |
61ff75ac CW |
1675 | I915_WRITE_IMR(engine, |
1676 | ~(engine->irq_enable_mask | | |
1677 | engine->irq_keep_mask)); | |
31bb59cc | 1678 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1679 | } |
1680 | ||
1681 | static void | |
31bb59cc | 1682 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1683 | { |
c033666a | 1684 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1685 | |
61ff75ac | 1686 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1687 | } |
1688 | ||
d1b851fc | 1689 | static int |
803688ba CW |
1690 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1691 | u64 offset, u32 length, | |
1692 | unsigned int dispatch_flags) | |
d1b851fc | 1693 | { |
7e37f889 | 1694 | struct intel_ring *ring = req->ring; |
e1f99ce6 | 1695 | int ret; |
78501eac | 1696 | |
5fb9de1a | 1697 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1698 | if (ret) |
1699 | return ret; | |
1700 | ||
b5321f30 | 1701 | intel_ring_emit(ring, |
65f56876 CW |
1702 | MI_BATCH_BUFFER_START | |
1703 | MI_BATCH_GTT | | |
8e004efc JH |
1704 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1705 | 0 : MI_BATCH_NON_SECURE_I965)); | |
b5321f30 CW |
1706 | intel_ring_emit(ring, offset); |
1707 | intel_ring_advance(ring); | |
78501eac | 1708 | |
d1b851fc ZN |
1709 | return 0; |
1710 | } | |
1711 | ||
b45305fc DV |
1712 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1713 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1714 | #define I830_TLB_ENTRIES (2) |
1715 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1716 | static int |
803688ba CW |
1717 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1718 | u64 offset, u32 len, | |
1719 | unsigned int dispatch_flags) | |
62fdfeaf | 1720 | { |
7e37f889 | 1721 | struct intel_ring *ring = req->ring; |
bde13ebd | 1722 | u32 cs_offset = i915_ggtt_offset(req->engine->scratch); |
c4e7a414 | 1723 | int ret; |
62fdfeaf | 1724 | |
5fb9de1a | 1725 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1726 | if (ret) |
1727 | return ret; | |
62fdfeaf | 1728 | |
c4d69da1 | 1729 | /* Evict the invalid PTE TLBs */ |
b5321f30 CW |
1730 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1731 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1732 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1733 | intel_ring_emit(ring, cs_offset); | |
1734 | intel_ring_emit(ring, 0xdeadbeef); | |
1735 | intel_ring_emit(ring, MI_NOOP); | |
1736 | intel_ring_advance(ring); | |
b45305fc | 1737 | |
8e004efc | 1738 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1739 | if (len > I830_BATCH_LIMIT) |
1740 | return -ENOSPC; | |
1741 | ||
5fb9de1a | 1742 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1743 | if (ret) |
1744 | return ret; | |
c4d69da1 CW |
1745 | |
1746 | /* Blit the batch (which has now all relocs applied) to the | |
1747 | * stable batch scratch bo area (so that the CS never | |
1748 | * stumbles over its tlb invalidation bug) ... | |
1749 | */ | |
b5321f30 CW |
1750 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1751 | intel_ring_emit(ring, | |
e2f80391 | 1752 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
b5321f30 CW |
1753 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
1754 | intel_ring_emit(ring, cs_offset); | |
1755 | intel_ring_emit(ring, 4096); | |
1756 | intel_ring_emit(ring, offset); | |
e2f80391 | 1757 | |
b5321f30 CW |
1758 | intel_ring_emit(ring, MI_FLUSH); |
1759 | intel_ring_emit(ring, MI_NOOP); | |
1760 | intel_ring_advance(ring); | |
b45305fc DV |
1761 | |
1762 | /* ... and execute it. */ | |
c4d69da1 | 1763 | offset = cs_offset; |
b45305fc | 1764 | } |
e1f99ce6 | 1765 | |
9d611c03 | 1766 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1767 | if (ret) |
1768 | return ret; | |
1769 | ||
b5321f30 CW |
1770 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1771 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1772 | 0 : MI_BATCH_NON_SECURE)); | |
1773 | intel_ring_advance(ring); | |
c4d69da1 | 1774 | |
fb3256da DV |
1775 | return 0; |
1776 | } | |
1777 | ||
1778 | static int | |
803688ba CW |
1779 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1780 | u64 offset, u32 len, | |
1781 | unsigned int dispatch_flags) | |
fb3256da | 1782 | { |
7e37f889 | 1783 | struct intel_ring *ring = req->ring; |
fb3256da DV |
1784 | int ret; |
1785 | ||
5fb9de1a | 1786 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1787 | if (ret) |
1788 | return ret; | |
1789 | ||
b5321f30 CW |
1790 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1791 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1792 | 0 : MI_BATCH_NON_SECURE)); | |
1793 | intel_ring_advance(ring); | |
62fdfeaf | 1794 | |
62fdfeaf EA |
1795 | return 0; |
1796 | } | |
1797 | ||
0bc40be8 | 1798 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1799 | { |
c033666a | 1800 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1801 | |
1802 | if (!dev_priv->status_page_dmah) | |
1803 | return; | |
1804 | ||
91c8a326 | 1805 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1806 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1807 | } |
1808 | ||
0bc40be8 | 1809 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1810 | { |
57e88531 | 1811 | struct i915_vma *vma; |
62fdfeaf | 1812 | |
57e88531 CW |
1813 | vma = fetch_and_zero(&engine->status_page.vma); |
1814 | if (!vma) | |
62fdfeaf | 1815 | return; |
62fdfeaf | 1816 | |
57e88531 CW |
1817 | i915_vma_unpin(vma); |
1818 | i915_gem_object_unpin_map(vma->obj); | |
1819 | i915_vma_put(vma); | |
62fdfeaf EA |
1820 | } |
1821 | ||
0bc40be8 | 1822 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1823 | { |
57e88531 CW |
1824 | struct drm_i915_gem_object *obj; |
1825 | struct i915_vma *vma; | |
1826 | unsigned int flags; | |
1827 | int ret; | |
e4ffd173 | 1828 | |
57e88531 CW |
1829 | obj = i915_gem_object_create(&engine->i915->drm, 4096); |
1830 | if (IS_ERR(obj)) { | |
1831 | DRM_ERROR("Failed to allocate status page\n"); | |
1832 | return PTR_ERR(obj); | |
1833 | } | |
62fdfeaf | 1834 | |
57e88531 CW |
1835 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1836 | if (ret) | |
1837 | goto err; | |
e3efda49 | 1838 | |
57e88531 CW |
1839 | vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL); |
1840 | if (IS_ERR(vma)) { | |
1841 | ret = PTR_ERR(vma); | |
1842 | goto err; | |
e3efda49 | 1843 | } |
62fdfeaf | 1844 | |
57e88531 CW |
1845 | flags = PIN_GLOBAL; |
1846 | if (!HAS_LLC(engine->i915)) | |
1847 | /* On g33, we cannot place HWS above 256MiB, so | |
1848 | * restrict its pinning to the low mappable arena. | |
1849 | * Though this restriction is not documented for | |
1850 | * gen4, gen5, or byt, they also behave similarly | |
1851 | * and hang if the HWS is placed at the top of the | |
1852 | * GTT. To generalise, it appears that all !llc | |
1853 | * platforms have issues with us placing the HWS | |
1854 | * above the mappable region (even though we never | |
1855 | * actualy map it). | |
1856 | */ | |
1857 | flags |= PIN_MAPPABLE; | |
1858 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
1859 | if (ret) | |
1860 | goto err; | |
62fdfeaf | 1861 | |
57e88531 | 1862 | engine->status_page.vma = vma; |
bde13ebd | 1863 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); |
57e88531 CW |
1864 | engine->status_page.page_addr = |
1865 | i915_gem_object_pin_map(obj, I915_MAP_WB); | |
62fdfeaf | 1866 | |
bde13ebd CW |
1867 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1868 | engine->name, i915_ggtt_offset(vma)); | |
62fdfeaf | 1869 | return 0; |
57e88531 CW |
1870 | |
1871 | err: | |
1872 | i915_gem_object_put(obj); | |
1873 | return ret; | |
62fdfeaf EA |
1874 | } |
1875 | ||
0bc40be8 | 1876 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1877 | { |
c033666a | 1878 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 | 1879 | |
57e88531 CW |
1880 | dev_priv->status_page_dmah = |
1881 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
1882 | if (!dev_priv->status_page_dmah) | |
1883 | return -ENOMEM; | |
6b8294a4 | 1884 | |
0bc40be8 TU |
1885 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1886 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1887 | |
1888 | return 0; | |
1889 | } | |
1890 | ||
aad29fbb | 1891 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1892 | { |
a687a43a | 1893 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
57e88531 | 1894 | unsigned int flags = PIN_GLOBAL | PIN_OFFSET_BIAS | 4096; |
9d80841e | 1895 | enum i915_map_type map; |
57e88531 | 1896 | struct i915_vma *vma = ring->vma; |
8305216f | 1897 | void *addr; |
7ba717cf TD |
1898 | int ret; |
1899 | ||
57e88531 | 1900 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1901 | |
9d80841e CW |
1902 | map = HAS_LLC(ring->engine->i915) ? I915_MAP_WB : I915_MAP_WC; |
1903 | ||
1904 | if (vma->obj->stolen) | |
57e88531 | 1905 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1906 | |
57e88531 | 1907 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1908 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1909 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1910 | else | |
1911 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1912 | if (unlikely(ret)) | |
def0c5f6 | 1913 | return ret; |
57e88531 | 1914 | } |
7ba717cf | 1915 | |
57e88531 CW |
1916 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1917 | if (unlikely(ret)) | |
1918 | return ret; | |
def0c5f6 | 1919 | |
9d80841e | 1920 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1921 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1922 | else | |
9d80841e | 1923 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1924 | if (IS_ERR(addr)) |
1925 | goto err; | |
7ba717cf | 1926 | |
32c04f16 | 1927 | ring->vaddr = addr; |
7ba717cf | 1928 | return 0; |
d2cad535 | 1929 | |
57e88531 CW |
1930 | err: |
1931 | i915_vma_unpin(vma); | |
1932 | return PTR_ERR(addr); | |
7ba717cf TD |
1933 | } |
1934 | ||
aad29fbb CW |
1935 | void intel_ring_unpin(struct intel_ring *ring) |
1936 | { | |
1937 | GEM_BUG_ON(!ring->vma); | |
1938 | GEM_BUG_ON(!ring->vaddr); | |
1939 | ||
9d80841e | 1940 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1941 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1942 | else |
1943 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1944 | ring->vaddr = NULL; |
1945 | ||
57e88531 | 1946 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1947 | } |
1948 | ||
57e88531 CW |
1949 | static struct i915_vma * |
1950 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1951 | { |
05394f39 | 1952 | struct drm_i915_gem_object *obj; |
57e88531 | 1953 | struct i915_vma *vma; |
62fdfeaf | 1954 | |
c58b735f CW |
1955 | obj = i915_gem_object_create_stolen(&dev_priv->drm, size); |
1956 | if (!obj) | |
57e88531 CW |
1957 | obj = i915_gem_object_create(&dev_priv->drm, size); |
1958 | if (IS_ERR(obj)) | |
1959 | return ERR_CAST(obj); | |
8187a2b7 | 1960 | |
24f3a8cf AG |
1961 | /* mark ring buffers as read-only from GPU side by default */ |
1962 | obj->gt_ro = 1; | |
1963 | ||
57e88531 CW |
1964 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
1965 | if (IS_ERR(vma)) | |
1966 | goto err; | |
1967 | ||
1968 | return vma; | |
e3efda49 | 1969 | |
57e88531 CW |
1970 | err: |
1971 | i915_gem_object_put(obj); | |
1972 | return vma; | |
e3efda49 CW |
1973 | } |
1974 | ||
7e37f889 CW |
1975 | struct intel_ring * |
1976 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1977 | { |
7e37f889 | 1978 | struct intel_ring *ring; |
57e88531 | 1979 | struct i915_vma *vma; |
01101fa7 | 1980 | |
8f942018 CW |
1981 | GEM_BUG_ON(!is_power_of_2(size)); |
1982 | ||
01101fa7 | 1983 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1984 | if (!ring) |
01101fa7 CW |
1985 | return ERR_PTR(-ENOMEM); |
1986 | ||
4a570db5 | 1987 | ring->engine = engine; |
01101fa7 | 1988 | |
675d9ad7 CW |
1989 | INIT_LIST_HEAD(&ring->request_list); |
1990 | ||
01101fa7 CW |
1991 | ring->size = size; |
1992 | /* Workaround an erratum on the i830 which causes a hang if | |
1993 | * the TAIL pointer points to within the last 2 cachelines | |
1994 | * of the buffer. | |
1995 | */ | |
1996 | ring->effective_size = size; | |
c033666a | 1997 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
1998 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1999 | ||
2000 | ring->last_retired_head = -1; | |
2001 | intel_ring_update_space(ring); | |
2002 | ||
57e88531 CW |
2003 | vma = intel_ring_create_vma(engine->i915, size); |
2004 | if (IS_ERR(vma)) { | |
01101fa7 | 2005 | kfree(ring); |
57e88531 | 2006 | return ERR_CAST(vma); |
01101fa7 | 2007 | } |
57e88531 | 2008 | ring->vma = vma; |
01101fa7 | 2009 | |
57e88531 | 2010 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2011 | return ring; |
2012 | } | |
2013 | ||
2014 | void | |
7e37f889 | 2015 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 2016 | { |
57e88531 | 2017 | i915_vma_put(ring->vma); |
608c1a52 | 2018 | list_del(&ring->link); |
01101fa7 CW |
2019 | kfree(ring); |
2020 | } | |
2021 | ||
0cb26a8e CW |
2022 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2023 | struct intel_engine_cs *engine) | |
2024 | { | |
2025 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2026 | int ret; | |
2027 | ||
91c8a326 | 2028 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2029 | |
2030 | if (ce->pin_count++) | |
2031 | return 0; | |
2032 | ||
2033 | if (ce->state) { | |
7abc98fa CW |
2034 | ret = i915_gem_object_set_to_gtt_domain(ce->state->obj, false); |
2035 | if (ret) | |
2036 | goto error; | |
2037 | ||
bf3783e5 CW |
2038 | ret = i915_vma_pin(ce->state, 0, ctx->ggtt_alignment, |
2039 | PIN_GLOBAL | PIN_HIGH); | |
0cb26a8e CW |
2040 | if (ret) |
2041 | goto error; | |
2042 | } | |
2043 | ||
c7c3c07d CW |
2044 | /* The kernel context is only used as a placeholder for flushing the |
2045 | * active context. It is never used for submitting user rendering and | |
2046 | * as such never requires the golden render context, and so we can skip | |
2047 | * emitting it when we switch to the kernel context. This is required | |
2048 | * as during eviction we cannot allocate and pin the renderstate in | |
2049 | * order to initialise the context. | |
2050 | */ | |
2051 | if (ctx == ctx->i915->kernel_context) | |
2052 | ce->initialised = true; | |
2053 | ||
9a6feaf0 | 2054 | i915_gem_context_get(ctx); |
0cb26a8e CW |
2055 | return 0; |
2056 | ||
2057 | error: | |
2058 | ce->pin_count = 0; | |
2059 | return ret; | |
2060 | } | |
2061 | ||
2062 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2063 | struct intel_engine_cs *engine) | |
2064 | { | |
2065 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2066 | ||
91c8a326 | 2067 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2068 | |
2069 | if (--ce->pin_count) | |
2070 | return; | |
2071 | ||
2072 | if (ce->state) | |
bf3783e5 | 2073 | i915_vma_unpin(ce->state); |
0cb26a8e | 2074 | |
9a6feaf0 | 2075 | i915_gem_context_put(ctx); |
0cb26a8e CW |
2076 | } |
2077 | ||
acd27845 | 2078 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 2079 | { |
acd27845 | 2080 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 2081 | struct intel_ring *ring; |
e3efda49 CW |
2082 | int ret; |
2083 | ||
0bc40be8 | 2084 | WARN_ON(engine->buffer); |
bfc882b4 | 2085 | |
019bf277 TU |
2086 | intel_engine_setup_common(engine); |
2087 | ||
0bc40be8 TU |
2088 | memset(engine->semaphore.sync_seqno, 0, |
2089 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2090 | |
019bf277 | 2091 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
2092 | if (ret) |
2093 | goto error; | |
e3efda49 | 2094 | |
0cb26a8e CW |
2095 | /* We may need to do things with the shrinker which |
2096 | * require us to immediately switch back to the default | |
2097 | * context. This can cause a problem as pinning the | |
2098 | * default context also requires GTT space which may not | |
2099 | * be available. To avoid this we always pin the default | |
2100 | * context. | |
2101 | */ | |
2102 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2103 | if (ret) | |
2104 | goto error; | |
2105 | ||
32c04f16 CW |
2106 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
2107 | if (IS_ERR(ring)) { | |
2108 | ret = PTR_ERR(ring); | |
b0366a54 DG |
2109 | goto error; |
2110 | } | |
01101fa7 | 2111 | |
c033666a | 2112 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2113 | ret = init_status_page(engine); |
e3efda49 | 2114 | if (ret) |
8ee14975 | 2115 | goto error; |
e3efda49 | 2116 | } else { |
0bc40be8 TU |
2117 | WARN_ON(engine->id != RCS); |
2118 | ret = init_phys_status_page(engine); | |
e3efda49 | 2119 | if (ret) |
8ee14975 | 2120 | goto error; |
e3efda49 CW |
2121 | } |
2122 | ||
aad29fbb | 2123 | ret = intel_ring_pin(ring); |
bfc882b4 | 2124 | if (ret) { |
57e88531 | 2125 | intel_ring_free(ring); |
bfc882b4 | 2126 | goto error; |
e3efda49 | 2127 | } |
57e88531 | 2128 | engine->buffer = ring; |
62fdfeaf | 2129 | |
8ee14975 | 2130 | return 0; |
351e3db2 | 2131 | |
8ee14975 | 2132 | error: |
7e37f889 | 2133 | intel_engine_cleanup(engine); |
8ee14975 | 2134 | return ret; |
62fdfeaf EA |
2135 | } |
2136 | ||
7e37f889 | 2137 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 2138 | { |
6402c330 | 2139 | struct drm_i915_private *dev_priv; |
33626e6a | 2140 | |
117897f4 | 2141 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2142 | return; |
2143 | ||
c033666a | 2144 | dev_priv = engine->i915; |
6402c330 | 2145 | |
0bc40be8 | 2146 | if (engine->buffer) { |
21a2c58a CW |
2147 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
2148 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 2149 | |
aad29fbb | 2150 | intel_ring_unpin(engine->buffer); |
7e37f889 | 2151 | intel_ring_free(engine->buffer); |
0bc40be8 | 2152 | engine->buffer = NULL; |
b0366a54 | 2153 | } |
78501eac | 2154 | |
0bc40be8 TU |
2155 | if (engine->cleanup) |
2156 | engine->cleanup(engine); | |
8d19215b | 2157 | |
c033666a | 2158 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2159 | cleanup_status_page(engine); |
7d3fdfff | 2160 | } else { |
0bc40be8 TU |
2161 | WARN_ON(engine->id != RCS); |
2162 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2163 | } |
44e895a8 | 2164 | |
96a945aa | 2165 | intel_engine_cleanup_common(engine); |
0cb26a8e CW |
2166 | |
2167 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2168 | ||
c033666a | 2169 | engine->i915 = NULL; |
62fdfeaf EA |
2170 | } |
2171 | ||
6689cb2b | 2172 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2173 | { |
6310346e CW |
2174 | int ret; |
2175 | ||
2176 | /* Flush enough space to reduce the likelihood of waiting after | |
2177 | * we start building the request - in which case we will just | |
2178 | * have to repeat work. | |
2179 | */ | |
a0442461 | 2180 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2181 | |
1dae2dfb | 2182 | request->ring = request->engine->buffer; |
6310346e CW |
2183 | |
2184 | ret = intel_ring_begin(request, 0); | |
2185 | if (ret) | |
2186 | return ret; | |
2187 | ||
a0442461 | 2188 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2189 | return 0; |
9d773091 CW |
2190 | } |
2191 | ||
987046ad CW |
2192 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2193 | { | |
7e37f889 | 2194 | struct intel_ring *ring = req->ring; |
987046ad | 2195 | struct drm_i915_gem_request *target; |
7da844c5 | 2196 | int ret; |
987046ad | 2197 | |
1dae2dfb CW |
2198 | intel_ring_update_space(ring); |
2199 | if (ring->space >= bytes) | |
987046ad CW |
2200 | return 0; |
2201 | ||
2202 | /* | |
2203 | * Space is reserved in the ringbuffer for finalising the request, | |
2204 | * as that cannot be allowed to fail. During request finalisation, | |
2205 | * reserved_space is set to 0 to stop the overallocation and the | |
2206 | * assumption is that then we never need to wait (which has the | |
2207 | * risk of failing with EINTR). | |
2208 | * | |
2209 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2210 | */ | |
0251a963 | 2211 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 2212 | |
675d9ad7 | 2213 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad CW |
2214 | unsigned space; |
2215 | ||
987046ad | 2216 | /* Would completion of this request free enough space? */ |
1dae2dfb CW |
2217 | space = __intel_ring_space(target->postfix, ring->tail, |
2218 | ring->size); | |
987046ad CW |
2219 | if (space >= bytes) |
2220 | break; | |
79bbcc29 | 2221 | } |
29b1b415 | 2222 | |
675d9ad7 | 2223 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
2224 | return -ENOSPC; |
2225 | ||
776f3236 | 2226 | ret = i915_wait_request(target, true, NULL, NO_WAITBOOST); |
7da844c5 CW |
2227 | if (ret) |
2228 | return ret; | |
2229 | ||
2230 | if (i915_reset_in_progress(&target->i915->gpu_error)) | |
2231 | return -EAGAIN; | |
2232 | ||
2233 | i915_gem_request_retire_upto(target); | |
2234 | ||
2235 | intel_ring_update_space(ring); | |
2236 | GEM_BUG_ON(ring->space < bytes); | |
2237 | return 0; | |
29b1b415 JH |
2238 | } |
2239 | ||
987046ad | 2240 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2241 | { |
7e37f889 | 2242 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
2243 | int remain_actual = ring->size - ring->tail; |
2244 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
2245 | int bytes = num_dwords * sizeof(u32); |
2246 | int total_bytes, wait_bytes; | |
79bbcc29 | 2247 | bool need_wrap = false; |
29b1b415 | 2248 | |
0251a963 | 2249 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2250 | |
79bbcc29 JH |
2251 | if (unlikely(bytes > remain_usable)) { |
2252 | /* | |
2253 | * Not enough space for the basic request. So need to flush | |
2254 | * out the remainder and then wait for base + reserved. | |
2255 | */ | |
2256 | wait_bytes = remain_actual + total_bytes; | |
2257 | need_wrap = true; | |
987046ad CW |
2258 | } else if (unlikely(total_bytes > remain_usable)) { |
2259 | /* | |
2260 | * The base request will fit but the reserved space | |
2261 | * falls off the end. So we don't need an immediate wrap | |
2262 | * and only need to effectively wait for the reserved | |
2263 | * size space from the start of ringbuffer. | |
2264 | */ | |
0251a963 | 2265 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2266 | } else { |
987046ad CW |
2267 | /* No wrapping required, just waiting. */ |
2268 | wait_bytes = total_bytes; | |
cbcc80df MK |
2269 | } |
2270 | ||
1dae2dfb | 2271 | if (wait_bytes > ring->space) { |
987046ad | 2272 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df MK |
2273 | if (unlikely(ret)) |
2274 | return ret; | |
2275 | } | |
2276 | ||
987046ad | 2277 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
2278 | GEM_BUG_ON(remain_actual > ring->space); |
2279 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 2280 | |
987046ad | 2281 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
2282 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
2283 | ring->tail = 0; | |
2284 | ring->space -= remain_actual; | |
987046ad | 2285 | } |
304d695c | 2286 | |
1dae2dfb CW |
2287 | ring->space -= bytes; |
2288 | GEM_BUG_ON(ring->space < 0); | |
304d695c | 2289 | return 0; |
8187a2b7 | 2290 | } |
78501eac | 2291 | |
753b1ad4 | 2292 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2293 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2294 | { |
7e37f889 | 2295 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
2296 | int num_dwords = |
2297 | (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); | |
753b1ad4 VS |
2298 | int ret; |
2299 | ||
2300 | if (num_dwords == 0) | |
2301 | return 0; | |
2302 | ||
18393f63 | 2303 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2304 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2305 | if (ret) |
2306 | return ret; | |
2307 | ||
2308 | while (num_dwords--) | |
b5321f30 | 2309 | intel_ring_emit(ring, MI_NOOP); |
753b1ad4 | 2310 | |
b5321f30 | 2311 | intel_ring_advance(ring); |
753b1ad4 VS |
2312 | |
2313 | return 0; | |
2314 | } | |
2315 | ||
c5efa1ad | 2316 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 2317 | { |
c5efa1ad | 2318 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2319 | |
76f8421f CW |
2320 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2321 | ||
881f47b6 | 2322 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2323 | |
2324 | /* Disable notification that the ring is IDLE. The GT | |
2325 | * will then assume that it is busy and bring it out of rc6. | |
2326 | */ | |
76f8421f CW |
2327 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2328 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2329 | |
2330 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2331 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2332 | |
12f55818 | 2333 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2334 | if (intel_wait_for_register_fw(dev_priv, |
2335 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2336 | GEN6_BSD_SLEEP_INDICATOR, | |
2337 | 0, | |
2338 | 50)) | |
12f55818 | 2339 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2340 | |
12f55818 | 2341 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2342 | i9xx_submit_request(request); |
12f55818 CW |
2343 | |
2344 | /* Let the ring send IDLE messages to the GT again, | |
2345 | * and so let it sleep to conserve power when idle. | |
2346 | */ | |
76f8421f CW |
2347 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2348 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2349 | ||
2350 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2351 | } |
2352 | ||
7c9cf4e3 | 2353 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 2354 | { |
7e37f889 | 2355 | struct intel_ring *ring = req->ring; |
71a77e07 | 2356 | uint32_t cmd; |
b72f3acb CW |
2357 | int ret; |
2358 | ||
5fb9de1a | 2359 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2360 | if (ret) |
2361 | return ret; | |
2362 | ||
71a77e07 | 2363 | cmd = MI_FLUSH_DW; |
c033666a | 2364 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2365 | cmd += 1; |
f0a1fb10 CW |
2366 | |
2367 | /* We always require a command barrier so that subsequent | |
2368 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2369 | * wrt the contents of the write cache being flushed to memory | |
2370 | * (and thus being coherent from the CPU). | |
2371 | */ | |
2372 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2373 | ||
9a289771 JB |
2374 | /* |
2375 | * Bspec vol 1c.5 - video engine command streamer: | |
2376 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2377 | * operation is complete. This bit is only valid when the | |
2378 | * Post-Sync Operation field is a value of 1h or 3h." | |
2379 | */ | |
7c9cf4e3 | 2380 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
2381 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2382 | ||
b5321f30 CW |
2383 | intel_ring_emit(ring, cmd); |
2384 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2385 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2386 | intel_ring_emit(ring, 0); /* upper addr */ |
2387 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2388 | } else { |
b5321f30 CW |
2389 | intel_ring_emit(ring, 0); |
2390 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2391 | } |
b5321f30 | 2392 | intel_ring_advance(ring); |
b72f3acb | 2393 | return 0; |
881f47b6 XH |
2394 | } |
2395 | ||
1c7a0623 | 2396 | static int |
803688ba CW |
2397 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
2398 | u64 offset, u32 len, | |
2399 | unsigned int dispatch_flags) | |
1c7a0623 | 2400 | { |
7e37f889 | 2401 | struct intel_ring *ring = req->ring; |
b5321f30 | 2402 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 2403 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2404 | int ret; |
2405 | ||
5fb9de1a | 2406 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2407 | if (ret) |
2408 | return ret; | |
2409 | ||
2410 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 | 2411 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2412 | (dispatch_flags & I915_DISPATCH_RS ? |
2413 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
b5321f30 CW |
2414 | intel_ring_emit(ring, lower_32_bits(offset)); |
2415 | intel_ring_emit(ring, upper_32_bits(offset)); | |
2416 | intel_ring_emit(ring, MI_NOOP); | |
2417 | intel_ring_advance(ring); | |
1c7a0623 BW |
2418 | |
2419 | return 0; | |
2420 | } | |
2421 | ||
d7d4eedd | 2422 | static int |
803688ba CW |
2423 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
2424 | u64 offset, u32 len, | |
2425 | unsigned int dispatch_flags) | |
d7d4eedd | 2426 | { |
7e37f889 | 2427 | struct intel_ring *ring = req->ring; |
d7d4eedd CW |
2428 | int ret; |
2429 | ||
5fb9de1a | 2430 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2431 | if (ret) |
2432 | return ret; | |
2433 | ||
b5321f30 | 2434 | intel_ring_emit(ring, |
77072258 | 2435 | MI_BATCH_BUFFER_START | |
8e004efc | 2436 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2437 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2438 | (dispatch_flags & I915_DISPATCH_RS ? | |
2439 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2440 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2441 | intel_ring_emit(ring, offset); |
2442 | intel_ring_advance(ring); | |
d7d4eedd CW |
2443 | |
2444 | return 0; | |
2445 | } | |
2446 | ||
881f47b6 | 2447 | static int |
803688ba CW |
2448 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
2449 | u64 offset, u32 len, | |
2450 | unsigned int dispatch_flags) | |
881f47b6 | 2451 | { |
7e37f889 | 2452 | struct intel_ring *ring = req->ring; |
0206e353 | 2453 | int ret; |
ab6f8e32 | 2454 | |
5fb9de1a | 2455 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2456 | if (ret) |
2457 | return ret; | |
e1f99ce6 | 2458 | |
b5321f30 | 2459 | intel_ring_emit(ring, |
d7d4eedd | 2460 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2461 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2462 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2463 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2464 | intel_ring_emit(ring, offset); |
2465 | intel_ring_advance(ring); | |
ab6f8e32 | 2466 | |
0206e353 | 2467 | return 0; |
881f47b6 XH |
2468 | } |
2469 | ||
549f7365 CW |
2470 | /* Blitter support (SandyBridge+) */ |
2471 | ||
7c9cf4e3 | 2472 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 2473 | { |
7e37f889 | 2474 | struct intel_ring *ring = req->ring; |
71a77e07 | 2475 | uint32_t cmd; |
b72f3acb CW |
2476 | int ret; |
2477 | ||
5fb9de1a | 2478 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2479 | if (ret) |
2480 | return ret; | |
2481 | ||
71a77e07 | 2482 | cmd = MI_FLUSH_DW; |
c033666a | 2483 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2484 | cmd += 1; |
f0a1fb10 CW |
2485 | |
2486 | /* We always require a command barrier so that subsequent | |
2487 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2488 | * wrt the contents of the write cache being flushed to memory | |
2489 | * (and thus being coherent from the CPU). | |
2490 | */ | |
2491 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2492 | ||
9a289771 JB |
2493 | /* |
2494 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2495 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2496 | * operation is complete. This bit is only valid when the | |
2497 | * Post-Sync Operation field is a value of 1h or 3h." | |
2498 | */ | |
7c9cf4e3 | 2499 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 2500 | cmd |= MI_INVALIDATE_TLB; |
b5321f30 CW |
2501 | intel_ring_emit(ring, cmd); |
2502 | intel_ring_emit(ring, | |
e2f80391 | 2503 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
c033666a | 2504 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2505 | intel_ring_emit(ring, 0); /* upper addr */ |
2506 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2507 | } else { |
b5321f30 CW |
2508 | intel_ring_emit(ring, 0); |
2509 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2510 | } |
b5321f30 | 2511 | intel_ring_advance(ring); |
fd3da6c9 | 2512 | |
b72f3acb | 2513 | return 0; |
8d19215b ZN |
2514 | } |
2515 | ||
d9a64610 TU |
2516 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2517 | struct intel_engine_cs *engine) | |
2518 | { | |
db3d4019 | 2519 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2520 | int ret, i; |
db3d4019 | 2521 | |
39df9190 | 2522 | if (!i915.semaphores) |
db3d4019 TU |
2523 | return; |
2524 | ||
51d545d0 CW |
2525 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
2526 | struct i915_vma *vma; | |
2527 | ||
91c8a326 | 2528 | obj = i915_gem_object_create(&dev_priv->drm, 4096); |
51d545d0 CW |
2529 | if (IS_ERR(obj)) |
2530 | goto err; | |
db3d4019 | 2531 | |
51d545d0 CW |
2532 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
2533 | if (IS_ERR(vma)) | |
2534 | goto err_obj; | |
2535 | ||
2536 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
2537 | if (ret) | |
2538 | goto err_obj; | |
2539 | ||
2540 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
2541 | if (ret) | |
2542 | goto err_obj; | |
2543 | ||
2544 | dev_priv->semaphore = vma; | |
2545 | } | |
d9a64610 TU |
2546 | |
2547 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 2548 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 2549 | |
ad7bdb2b | 2550 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 2551 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
2552 | |
2553 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 2554 | u32 ring_offset; |
1b9e6650 TU |
2555 | |
2556 | if (i != engine->id) | |
2557 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2558 | else | |
2559 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2560 | ||
2561 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2562 | } | |
d9a64610 | 2563 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 2564 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 2565 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
2566 | |
2567 | /* | |
2568 | * The current semaphore is only applied on pre-gen8 | |
2569 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2570 | * platform. So the semaphore between RCS and VCS2 is | |
2571 | * initialized as INVALID. Gen8 will initialize the | |
2572 | * sema between VCS2 and RCS later. | |
2573 | */ | |
318f89ca | 2574 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
2575 | static const struct { |
2576 | u32 wait_mbox; | |
2577 | i915_reg_t mbox_reg; | |
318f89ca TU |
2578 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
2579 | [RCS_HW] = { | |
2580 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2581 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2582 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 2583 | }, |
318f89ca TU |
2584 | [VCS_HW] = { |
2585 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2586 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2587 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 2588 | }, |
318f89ca TU |
2589 | [BCS_HW] = { |
2590 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2591 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2592 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 2593 | }, |
318f89ca TU |
2594 | [VECS_HW] = { |
2595 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2596 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2597 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
2598 | }, |
2599 | }; | |
2600 | u32 wait_mbox; | |
2601 | i915_reg_t mbox_reg; | |
2602 | ||
318f89ca | 2603 | if (i == engine->hw_id) { |
4b8e38a9 TU |
2604 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
2605 | mbox_reg = GEN6_NOSYNC; | |
2606 | } else { | |
318f89ca TU |
2607 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
2608 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
2609 | } |
2610 | ||
2611 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2612 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2613 | } | |
d9a64610 | 2614 | } |
51d545d0 CW |
2615 | |
2616 | return; | |
2617 | ||
2618 | err_obj: | |
2619 | i915_gem_object_put(obj); | |
2620 | err: | |
2621 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
2622 | i915.semaphores = 0; | |
d9a64610 TU |
2623 | } |
2624 | ||
ed003078 CW |
2625 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2626 | struct intel_engine_cs *engine) | |
2627 | { | |
c78d6061 TU |
2628 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2629 | ||
ed003078 | 2630 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2631 | engine->irq_enable = gen8_irq_enable; |
2632 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2633 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2634 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2635 | engine->irq_enable = gen6_irq_enable; |
2636 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2637 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2638 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2639 | engine->irq_enable = gen5_irq_enable; |
2640 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2641 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2642 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2643 | engine->irq_enable = i9xx_irq_enable; |
2644 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2645 | } else { |
31bb59cc CW |
2646 | engine->irq_enable = i8xx_irq_enable; |
2647 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2648 | } |
2649 | } | |
2650 | ||
06a2fe22 TU |
2651 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2652 | struct intel_engine_cs *engine) | |
2653 | { | |
618e4ca7 CW |
2654 | intel_ring_init_irq(dev_priv, engine); |
2655 | intel_ring_init_semaphores(dev_priv, engine); | |
2656 | ||
1d8a1337 | 2657 | engine->init_hw = init_ring_common; |
7445a2a4 | 2658 | |
ddd66c51 | 2659 | engine->emit_request = i9xx_emit_request; |
618e4ca7 CW |
2660 | if (i915.semaphores) |
2661 | engine->emit_request = gen6_sema_emit_request; | |
ddd66c51 | 2662 | engine->submit_request = i9xx_submit_request; |
6f7bef75 CW |
2663 | |
2664 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2665 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2666 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2667 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2668 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2669 | engine->emit_bb_start = i965_emit_bb_start; |
6f7bef75 | 2670 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
803688ba | 2671 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2672 | else |
803688ba | 2673 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2674 | } |
2675 | ||
8b3e2d36 | 2676 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2677 | { |
8b3e2d36 | 2678 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2679 | int ret; |
5c1143bb | 2680 | |
06a2fe22 TU |
2681 | intel_ring_default_vfuncs(dev_priv, engine); |
2682 | ||
61ff75ac CW |
2683 | if (HAS_L3_DPF(dev_priv)) |
2684 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2685 | |
c033666a | 2686 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2687 | engine->init_context = intel_rcs_ctx_init; |
ddd66c51 | 2688 | engine->emit_request = gen8_render_emit_request; |
c7fe7d25 | 2689 | engine->emit_flush = gen8_render_ring_flush; |
39df9190 | 2690 | if (i915.semaphores) |
e2f80391 | 2691 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2692 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2693 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2694 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2695 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2696 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2697 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2698 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2699 | } else { |
c033666a | 2700 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2701 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2702 | else |
c7fe7d25 | 2703 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2704 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2705 | } |
707d9cf9 | 2706 | |
c033666a | 2707 | if (IS_HASWELL(dev_priv)) |
803688ba | 2708 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2709 | |
e2f80391 TU |
2710 | engine->init_hw = init_render_ring; |
2711 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2712 | |
acd27845 | 2713 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2714 | if (ret) |
2715 | return ret; | |
2716 | ||
f8973c21 | 2717 | if (INTEL_GEN(dev_priv) >= 6) { |
56c0f1a7 | 2718 | ret = intel_engine_create_scratch(engine, 4096); |
7d5ea807 CW |
2719 | if (ret) |
2720 | return ret; | |
2721 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2722 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2723 | if (ret) |
2724 | return ret; | |
2725 | } | |
2726 | ||
2727 | return 0; | |
5c1143bb XH |
2728 | } |
2729 | ||
8b3e2d36 | 2730 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2731 | { |
8b3e2d36 | 2732 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2733 | |
06a2fe22 TU |
2734 | intel_ring_default_vfuncs(dev_priv, engine); |
2735 | ||
c033666a | 2736 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2737 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2738 | if (IS_GEN6(dev_priv)) |
c5efa1ad | 2739 | engine->submit_request = gen6_bsd_submit_request; |
c7fe7d25 | 2740 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2741 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2742 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2743 | } else { |
e2f80391 | 2744 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2745 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2746 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2747 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2748 | else |
e2f80391 | 2749 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2750 | } |
58fa3835 | 2751 | |
acd27845 | 2752 | return intel_init_ring_buffer(engine); |
5c1143bb | 2753 | } |
549f7365 | 2754 | |
845f74a7 | 2755 | /** |
62659920 | 2756 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2757 | */ |
8b3e2d36 | 2758 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2759 | { |
8b3e2d36 | 2760 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2761 | |
2762 | intel_ring_default_vfuncs(dev_priv, engine); | |
2763 | ||
c7fe7d25 | 2764 | engine->emit_flush = gen6_bsd_ring_flush; |
845f74a7 | 2765 | |
acd27845 | 2766 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2767 | } |
2768 | ||
8b3e2d36 | 2769 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2770 | { |
8b3e2d36 | 2771 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2772 | |
2773 | intel_ring_default_vfuncs(dev_priv, engine); | |
2774 | ||
c7fe7d25 | 2775 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2776 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2777 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2778 | |
acd27845 | 2779 | return intel_init_ring_buffer(engine); |
549f7365 | 2780 | } |
a7b9761d | 2781 | |
8b3e2d36 | 2782 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2783 | { |
8b3e2d36 | 2784 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2785 | |
2786 | intel_ring_default_vfuncs(dev_priv, engine); | |
2787 | ||
c7fe7d25 | 2788 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2789 | |
c78d6061 | 2790 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2791 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2792 | engine->irq_enable = hsw_vebox_irq_enable; |
2793 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2794 | } |
9a8a2213 | 2795 | |
acd27845 | 2796 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2797 | } |