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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
c7dca47b CW |
36 | static inline int ring_space(struct intel_ring_buffer *ring) |
37 | { | |
633cf8f5 | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
39 | if (space < 0) |
40 | space += ring->size; | |
41 | return space; | |
42 | } | |
43 | ||
09246732 CW |
44 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
45 | { | |
46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
47 | ||
48 | ring->tail &= ring->size - 1; | |
49 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) | |
50 | return; | |
51 | ring->write_tail(ring, ring->tail); | |
52 | } | |
53 | ||
b72f3acb | 54 | static int |
46f0f8d1 CW |
55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
56 | u32 invalidate_domains, | |
57 | u32 flush_domains) | |
58 | { | |
59 | u32 cmd; | |
60 | int ret; | |
61 | ||
62 | cmd = MI_FLUSH; | |
31b14c9f | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
64 | cmd |= MI_NO_WRITE_FLUSH; |
65 | ||
66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
67 | cmd |= MI_READ_FLUSH; | |
68 | ||
69 | ret = intel_ring_begin(ring, 2); | |
70 | if (ret) | |
71 | return ret; | |
72 | ||
73 | intel_ring_emit(ring, cmd); | |
74 | intel_ring_emit(ring, MI_NOOP); | |
75 | intel_ring_advance(ring); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int | |
81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
82 | u32 invalidate_domains, | |
83 | u32 flush_domains) | |
62fdfeaf | 84 | { |
78501eac | 85 | struct drm_device *dev = ring->dev; |
6f392d54 | 86 | u32 cmd; |
b72f3acb | 87 | int ret; |
6f392d54 | 88 | |
36d527de CW |
89 | /* |
90 | * read/write caches: | |
91 | * | |
92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
94 | * also flushed at 2d versus 3d pipeline switches. | |
95 | * | |
96 | * read-only caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
99 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
100 | * | |
101 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
102 | * | |
103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
104 | * invalidated when MI_EXE_FLUSH is set. | |
105 | * | |
106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
107 | * invalidated with every MI_FLUSH. | |
108 | * | |
109 | * TLBs: | |
110 | * | |
111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
114 | * are flushed at any MI_FLUSH. | |
115 | */ | |
116 | ||
117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
121 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 122 | |
36d527de CW |
123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
124 | (IS_G4X(dev) || IS_GEN5(dev))) | |
125 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 126 | |
36d527de CW |
127 | ret = intel_ring_begin(ring, 2); |
128 | if (ret) | |
129 | return ret; | |
b72f3acb | 130 | |
36d527de CW |
131 | intel_ring_emit(ring, cmd); |
132 | intel_ring_emit(ring, MI_NOOP); | |
133 | intel_ring_advance(ring); | |
b72f3acb CW |
134 | |
135 | return 0; | |
8187a2b7 ZN |
136 | } |
137 | ||
8d315287 JB |
138 | /** |
139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
140 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
142 | * | |
143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
144 | * produced by non-pipelined state commands), software needs to first | |
145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
146 | * 0. | |
147 | * | |
148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
150 | * | |
151 | * And the workaround for these two requires this workaround first: | |
152 | * | |
153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
154 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
155 | * flushes. | |
156 | * | |
157 | * And this last workaround is tricky because of the requirements on | |
158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
159 | * volume 2 part 1: | |
160 | * | |
161 | * "1 of the following must also be set: | |
162 | * - Render Target Cache Flush Enable ([12] of DW1) | |
163 | * - Depth Cache Flush Enable ([0] of DW1) | |
164 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
165 | * - Depth Stall ([13] of DW1) | |
166 | * - Post-Sync Operation ([13] of DW1) | |
167 | * - Notify Enable ([8] of DW1)" | |
168 | * | |
169 | * The cache flushes require the workaround flush that triggered this | |
170 | * one, so we can't use it. Depth stall would trigger the same. | |
171 | * Post-sync nonzero is what triggered this second workaround, so we | |
172 | * can't use that one either. Notify enable is IRQs, which aren't | |
173 | * really our business. That leaves only stall at scoreboard. | |
174 | */ | |
175 | static int | |
176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
177 | { | |
0d1aacac | 178 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
179 | int ret; |
180 | ||
181 | ||
182 | ret = intel_ring_begin(ring, 6); | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
194 | ||
195 | ret = intel_ring_begin(ring, 6); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
211 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
212 | u32 invalidate_domains, u32 flush_domains) | |
213 | { | |
214 | u32 flags = 0; | |
0d1aacac | 215 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
216 | int ret; |
217 | ||
b3111509 PZ |
218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
219 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
8d315287 JB |
223 | /* Just flush everything. Experiments have shown that reducing the |
224 | * number of bits based on the write domains has little performance | |
225 | * impact. | |
226 | */ | |
7d54a904 CW |
227 | if (flush_domains) { |
228 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
229 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
230 | /* | |
231 | * Ensure that any following seqno writes only happen | |
232 | * when the render cache is indeed flushed. | |
233 | */ | |
97f209bc | 234 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
235 | } |
236 | if (invalidate_domains) { | |
237 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
243 | /* | |
244 | * TLB invalidate requires a post-sync write. | |
245 | */ | |
3ac78313 | 246 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 247 | } |
8d315287 | 248 | |
6c6cf5aa | 249 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
250 | if (ret) |
251 | return ret; | |
252 | ||
6c6cf5aa | 253 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
254 | intel_ring_emit(ring, flags); |
255 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 256 | intel_ring_emit(ring, 0); |
8d315287 JB |
257 | intel_ring_advance(ring); |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
f3987631 PZ |
262 | static int |
263 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
264 | { | |
265 | int ret; | |
266 | ||
267 | ret = intel_ring_begin(ring, 4); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
272 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
273 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
274 | intel_ring_emit(ring, 0); | |
275 | intel_ring_emit(ring, 0); | |
276 | intel_ring_advance(ring); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
fd3da6c9 RV |
281 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
282 | { | |
283 | int ret; | |
284 | ||
285 | if (!ring->fbc_dirty) | |
286 | return 0; | |
287 | ||
37c1d94f | 288 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
289 | if (ret) |
290 | return ret; | |
fd3da6c9 RV |
291 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
292 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
293 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
294 | intel_ring_emit(ring, value); | |
37c1d94f VS |
295 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
296 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
297 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
298 | intel_ring_advance(ring); |
299 | ||
300 | ring->fbc_dirty = false; | |
301 | return 0; | |
302 | } | |
303 | ||
4772eaeb PZ |
304 | static int |
305 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
306 | u32 invalidate_domains, u32 flush_domains) | |
307 | { | |
308 | u32 flags = 0; | |
0d1aacac | 309 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
4772eaeb PZ |
310 | int ret; |
311 | ||
f3987631 PZ |
312 | /* |
313 | * Ensure that any following seqno writes only happen when the render | |
314 | * cache is indeed flushed. | |
315 | * | |
316 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
317 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
318 | * don't try to be clever and just set it unconditionally. | |
319 | */ | |
320 | flags |= PIPE_CONTROL_CS_STALL; | |
321 | ||
4772eaeb PZ |
322 | /* Just flush everything. Experiments have shown that reducing the |
323 | * number of bits based on the write domains has little performance | |
324 | * impact. | |
325 | */ | |
326 | if (flush_domains) { | |
327 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
328 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
329 | } |
330 | if (invalidate_domains) { | |
331 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
332 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
335 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
336 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
337 | /* | |
338 | * TLB invalidate requires a post-sync write. | |
339 | */ | |
340 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 341 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
342 | |
343 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
344 | * set before a pipe_control command that has the state cache | |
345 | * invalidate bit set. */ | |
346 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
347 | } |
348 | ||
349 | ret = intel_ring_begin(ring, 4); | |
350 | if (ret) | |
351 | return ret; | |
352 | ||
353 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
354 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 355 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
356 | intel_ring_emit(ring, 0); |
357 | intel_ring_advance(ring); | |
358 | ||
9688ecad | 359 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
360 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
361 | ||
4772eaeb PZ |
362 | return 0; |
363 | } | |
364 | ||
a5f3d68e BW |
365 | static int |
366 | gen8_render_ring_flush(struct intel_ring_buffer *ring, | |
367 | u32 invalidate_domains, u32 flush_domains) | |
368 | { | |
369 | u32 flags = 0; | |
370 | u32 scratch_addr = ring->scratch.gtt_offset + 128; | |
371 | int ret; | |
372 | ||
373 | flags |= PIPE_CONTROL_CS_STALL; | |
374 | ||
375 | if (flush_domains) { | |
376 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
377 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
378 | } | |
379 | if (invalidate_domains) { | |
380 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
381 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
382 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
383 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
384 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
385 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
386 | flags |= PIPE_CONTROL_QW_WRITE; | |
387 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
388 | } | |
389 | ||
390 | ret = intel_ring_begin(ring, 6); | |
391 | if (ret) | |
392 | return ret; | |
393 | ||
394 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
395 | intel_ring_emit(ring, flags); | |
396 | intel_ring_emit(ring, scratch_addr); | |
397 | intel_ring_emit(ring, 0); | |
398 | intel_ring_emit(ring, 0); | |
399 | intel_ring_emit(ring, 0); | |
400 | intel_ring_advance(ring); | |
401 | ||
402 | return 0; | |
403 | ||
404 | } | |
405 | ||
78501eac | 406 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 407 | u32 value) |
d46eefa2 | 408 | { |
78501eac | 409 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 410 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
411 | } |
412 | ||
78501eac | 413 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 414 | { |
78501eac CW |
415 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
416 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 417 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
418 | |
419 | return I915_READ(acthd_reg); | |
420 | } | |
421 | ||
035dc1e0 DV |
422 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
423 | { | |
424 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
425 | u32 addr; | |
426 | ||
427 | addr = dev_priv->status_page_dmah->busaddr; | |
428 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
429 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
430 | I915_WRITE(HWS_PGA, addr); | |
431 | } | |
432 | ||
78501eac | 433 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 434 | { |
b7884eb4 DV |
435 | struct drm_device *dev = ring->dev; |
436 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 437 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 438 | int ret = 0; |
8187a2b7 | 439 | u32 head; |
8187a2b7 | 440 | |
c8d9a590 | 441 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
b7884eb4 | 442 | |
035dc1e0 DV |
443 | if (I915_NEED_GFX_HWS(dev)) |
444 | intel_ring_setup_status_page(ring); | |
445 | else | |
446 | ring_setup_phys_status_page(ring); | |
447 | ||
8187a2b7 | 448 | /* Stop the ring if it's running. */ |
7f2ab699 | 449 | I915_WRITE_CTL(ring, 0); |
570ef608 | 450 | I915_WRITE_HEAD(ring, 0); |
78501eac | 451 | ring->write_tail(ring, 0); |
8187a2b7 | 452 | |
570ef608 | 453 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
454 | |
455 | /* G45 ring initialization fails to reset head to zero */ | |
456 | if (head != 0) { | |
6fd0d56e CW |
457 | DRM_DEBUG_KMS("%s head not reset to zero " |
458 | "ctl %08x head %08x tail %08x start %08x\n", | |
459 | ring->name, | |
460 | I915_READ_CTL(ring), | |
461 | I915_READ_HEAD(ring), | |
462 | I915_READ_TAIL(ring), | |
463 | I915_READ_START(ring)); | |
8187a2b7 | 464 | |
570ef608 | 465 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 466 | |
6fd0d56e CW |
467 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
468 | DRM_ERROR("failed to set %s head to zero " | |
469 | "ctl %08x head %08x tail %08x start %08x\n", | |
470 | ring->name, | |
471 | I915_READ_CTL(ring), | |
472 | I915_READ_HEAD(ring), | |
473 | I915_READ_TAIL(ring), | |
474 | I915_READ_START(ring)); | |
475 | } | |
8187a2b7 ZN |
476 | } |
477 | ||
0d8957c8 DV |
478 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
479 | * registers with the above sequence (the readback of the HEAD registers | |
480 | * also enforces ordering), otherwise the hw might lose the new ring | |
481 | * register values. */ | |
f343c5f6 | 482 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 483 | I915_WRITE_CTL(ring, |
ae69b42a | 484 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 485 | | RING_VALID); |
8187a2b7 | 486 | |
8187a2b7 | 487 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 488 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 489 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 490 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 CW |
491 | DRM_ERROR("%s initialization failed " |
492 | "ctl %08x head %08x tail %08x start %08x\n", | |
493 | ring->name, | |
494 | I915_READ_CTL(ring), | |
495 | I915_READ_HEAD(ring), | |
496 | I915_READ_TAIL(ring), | |
497 | I915_READ_START(ring)); | |
b7884eb4 DV |
498 | ret = -EIO; |
499 | goto out; | |
8187a2b7 ZN |
500 | } |
501 | ||
78501eac CW |
502 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
503 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 504 | else { |
c7dca47b | 505 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 506 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 507 | ring->space = ring_space(ring); |
c3b20037 | 508 | ring->last_retired_head = -1; |
8187a2b7 | 509 | } |
1ec14ad3 | 510 | |
50f018df CW |
511 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
512 | ||
b7884eb4 | 513 | out: |
c8d9a590 | 514 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
515 | |
516 | return ret; | |
8187a2b7 ZN |
517 | } |
518 | ||
c6df541c CW |
519 | static int |
520 | init_pipe_control(struct intel_ring_buffer *ring) | |
521 | { | |
c6df541c CW |
522 | int ret; |
523 | ||
0d1aacac | 524 | if (ring->scratch.obj) |
c6df541c CW |
525 | return 0; |
526 | ||
0d1aacac CW |
527 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
528 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
529 | DRM_ERROR("Failed to allocate seqno page\n"); |
530 | ret = -ENOMEM; | |
531 | goto err; | |
532 | } | |
e4ffd173 | 533 | |
0d1aacac | 534 | i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
c6df541c | 535 | |
0d1aacac | 536 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); |
c6df541c CW |
537 | if (ret) |
538 | goto err_unref; | |
539 | ||
0d1aacac CW |
540 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
541 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
542 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 543 | ret = -ENOMEM; |
c6df541c | 544 | goto err_unpin; |
56b085a0 | 545 | } |
c6df541c | 546 | |
2b1086cc | 547 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 548 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
549 | return 0; |
550 | ||
551 | err_unpin: | |
d7f46fc4 | 552 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 553 | err_unref: |
0d1aacac | 554 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 555 | err: |
c6df541c CW |
556 | return ret; |
557 | } | |
558 | ||
78501eac | 559 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 560 | { |
78501eac | 561 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 562 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 563 | int ret = init_ring_common(ring); |
a69ffdbf | 564 | |
1c8c38c5 | 565 | if (INTEL_INFO(dev)->gen > 3) |
6b26c86d | 566 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
567 | |
568 | /* We need to disable the AsyncFlip performance optimisations in order | |
569 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
570 | * programmed to '1' on all products. | |
8693a824 DL |
571 | * |
572 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv | |
1c8c38c5 CW |
573 | */ |
574 | if (INTEL_INFO(dev)->gen >= 6) | |
575 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
576 | ||
f05bb0c7 CW |
577 | /* Required for the hardware to program scanline values for waiting */ |
578 | if (INTEL_INFO(dev)->gen == 6) | |
579 | I915_WRITE(GFX_MODE, | |
580 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); | |
581 | ||
1c8c38c5 CW |
582 | if (IS_GEN7(dev)) |
583 | I915_WRITE(GFX_MODE_GEN7, | |
584 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
585 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
78501eac | 586 | |
8d315287 | 587 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
588 | ret = init_pipe_control(ring); |
589 | if (ret) | |
590 | return ret; | |
591 | } | |
592 | ||
5e13a0c5 | 593 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
594 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
595 | * "If this bit is set, STCunit will have LRA as replacement | |
596 | * policy. [...] This bit must be reset. LRA replacement | |
597 | * policy is not supported." | |
598 | */ | |
599 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 600 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
601 | |
602 | /* This is not explicitly set for GEN6, so read the register. | |
603 | * see intel_ring_mi_set_context() for why we care. | |
604 | * TODO: consider explicitly setting the bit for GEN5 | |
605 | */ | |
606 | ring->itlb_before_ctx_switch = | |
607 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
608 | } |
609 | ||
6b26c86d DV |
610 | if (INTEL_INFO(dev)->gen >= 6) |
611 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 612 | |
040d2baa | 613 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 614 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 615 | |
8187a2b7 ZN |
616 | return ret; |
617 | } | |
618 | ||
c6df541c CW |
619 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
620 | { | |
b45305fc DV |
621 | struct drm_device *dev = ring->dev; |
622 | ||
0d1aacac | 623 | if (ring->scratch.obj == NULL) |
c6df541c CW |
624 | return; |
625 | ||
0d1aacac CW |
626 | if (INTEL_INFO(dev)->gen >= 5) { |
627 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
d7f46fc4 | 628 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
0d1aacac | 629 | } |
aaf8a516 | 630 | |
0d1aacac CW |
631 | drm_gem_object_unreference(&ring->scratch.obj->base); |
632 | ring->scratch.obj = NULL; | |
c6df541c CW |
633 | } |
634 | ||
1ec14ad3 | 635 | static void |
c8c99b0f | 636 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 637 | u32 mmio_offset) |
1ec14ad3 | 638 | { |
ad776f8b BW |
639 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
640 | * of rings, it's easiest if we round up each individual update to a | |
641 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
642 | * even though the actual update only requires 3 dwords. | |
643 | */ | |
644 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 645 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 646 | intel_ring_emit(ring, mmio_offset); |
1823521d | 647 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
ad776f8b | 648 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
649 | } |
650 | ||
c8c99b0f BW |
651 | /** |
652 | * gen6_add_request - Update the semaphore mailbox registers | |
653 | * | |
654 | * @ring - ring that is adding a request | |
655 | * @seqno - return seqno stuck into the ring | |
656 | * | |
657 | * Update the mailbox registers in the *other* rings with the current seqno. | |
658 | * This acts like a signal in the canonical semaphore. | |
659 | */ | |
1ec14ad3 | 660 | static int |
9d773091 | 661 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 662 | { |
ad776f8b BW |
663 | struct drm_device *dev = ring->dev; |
664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
665 | struct intel_ring_buffer *useless; | |
52ed2325 | 666 | int i, ret, num_dwords = 4; |
1ec14ad3 | 667 | |
52ed2325 BW |
668 | if (i915_semaphore_is_enabled(dev)) |
669 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); | |
670 | #undef MBOX_UPDATE_DWORDS | |
671 | ||
672 | ret = intel_ring_begin(ring, num_dwords); | |
1ec14ad3 CW |
673 | if (ret) |
674 | return ret; | |
675 | ||
f0a9f74c BW |
676 | if (i915_semaphore_is_enabled(dev)) { |
677 | for_each_ring(useless, dev_priv, i) { | |
678 | u32 mbox_reg = ring->signal_mbox[i]; | |
679 | if (mbox_reg != GEN6_NOSYNC) | |
680 | update_mboxes(ring, mbox_reg); | |
681 | } | |
ad776f8b | 682 | } |
1ec14ad3 CW |
683 | |
684 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
685 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 686 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 687 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 688 | __intel_ring_advance(ring); |
1ec14ad3 | 689 | |
1ec14ad3 CW |
690 | return 0; |
691 | } | |
692 | ||
f72b3435 MK |
693 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
694 | u32 seqno) | |
695 | { | |
696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
697 | return dev_priv->last_seqno < seqno; | |
698 | } | |
699 | ||
c8c99b0f BW |
700 | /** |
701 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
702 | * | |
703 | * @waiter - ring that is waiting | |
704 | * @signaller - ring which has, or will signal | |
705 | * @seqno - seqno which the waiter will block on | |
706 | */ | |
707 | static int | |
686cb5f9 DV |
708 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
709 | struct intel_ring_buffer *signaller, | |
710 | u32 seqno) | |
1ec14ad3 CW |
711 | { |
712 | int ret; | |
c8c99b0f BW |
713 | u32 dw1 = MI_SEMAPHORE_MBOX | |
714 | MI_SEMAPHORE_COMPARE | | |
715 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 716 | |
1500f7ea BW |
717 | /* Throughout all of the GEM code, seqno passed implies our current |
718 | * seqno is >= the last seqno executed. However for hardware the | |
719 | * comparison is strictly greater than. | |
720 | */ | |
721 | seqno -= 1; | |
722 | ||
686cb5f9 DV |
723 | WARN_ON(signaller->semaphore_register[waiter->id] == |
724 | MI_SEMAPHORE_SYNC_INVALID); | |
725 | ||
c8c99b0f | 726 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
727 | if (ret) |
728 | return ret; | |
729 | ||
f72b3435 MK |
730 | /* If seqno wrap happened, omit the wait with no-ops */ |
731 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
732 | intel_ring_emit(waiter, | |
733 | dw1 | | |
734 | signaller->semaphore_register[waiter->id]); | |
735 | intel_ring_emit(waiter, seqno); | |
736 | intel_ring_emit(waiter, 0); | |
737 | intel_ring_emit(waiter, MI_NOOP); | |
738 | } else { | |
739 | intel_ring_emit(waiter, MI_NOOP); | |
740 | intel_ring_emit(waiter, MI_NOOP); | |
741 | intel_ring_emit(waiter, MI_NOOP); | |
742 | intel_ring_emit(waiter, MI_NOOP); | |
743 | } | |
c8c99b0f | 744 | intel_ring_advance(waiter); |
1ec14ad3 CW |
745 | |
746 | return 0; | |
747 | } | |
748 | ||
c6df541c CW |
749 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
750 | do { \ | |
fcbc34e4 KG |
751 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
752 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
753 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
754 | intel_ring_emit(ring__, 0); \ | |
755 | intel_ring_emit(ring__, 0); \ | |
756 | } while (0) | |
757 | ||
758 | static int | |
9d773091 | 759 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 760 | { |
0d1aacac | 761 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
c6df541c CW |
762 | int ret; |
763 | ||
764 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
765 | * incoherent with writes to memory, i.e. completely fubar, | |
766 | * so we need to use PIPE_NOTIFY instead. | |
767 | * | |
768 | * However, we also need to workaround the qword write | |
769 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
770 | * memory before requesting an interrupt. | |
771 | */ | |
772 | ret = intel_ring_begin(ring, 32); | |
773 | if (ret) | |
774 | return ret; | |
775 | ||
fcbc34e4 | 776 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
777 | PIPE_CONTROL_WRITE_FLUSH | |
778 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 779 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 780 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
781 | intel_ring_emit(ring, 0); |
782 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
783 | scratch_addr += 128; /* write to separate cachelines */ | |
784 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
785 | scratch_addr += 128; | |
786 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
787 | scratch_addr += 128; | |
788 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
789 | scratch_addr += 128; | |
790 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
791 | scratch_addr += 128; | |
792 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 793 | |
fcbc34e4 | 794 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
795 | PIPE_CONTROL_WRITE_FLUSH | |
796 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 797 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 798 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 799 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 800 | intel_ring_emit(ring, 0); |
09246732 | 801 | __intel_ring_advance(ring); |
c6df541c | 802 | |
c6df541c CW |
803 | return 0; |
804 | } | |
805 | ||
4cd53c0c | 806 | static u32 |
b2eadbc8 | 807 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 808 | { |
4cd53c0c DV |
809 | /* Workaround to force correct ordering between irq and seqno writes on |
810 | * ivb (and maybe also on snb) by reading from a CS register (like | |
811 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 812 | if (!lazy_coherency) |
4cd53c0c DV |
813 | intel_ring_get_active_head(ring); |
814 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
815 | } | |
816 | ||
8187a2b7 | 817 | static u32 |
b2eadbc8 | 818 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 819 | { |
1ec14ad3 CW |
820 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
821 | } | |
822 | ||
b70ec5bf MK |
823 | static void |
824 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
825 | { | |
826 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
827 | } | |
828 | ||
c6df541c | 829 | static u32 |
b2eadbc8 | 830 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c | 831 | { |
0d1aacac | 832 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
833 | } |
834 | ||
b70ec5bf MK |
835 | static void |
836 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
837 | { | |
0d1aacac | 838 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
839 | } |
840 | ||
e48d8634 DV |
841 | static bool |
842 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
843 | { | |
844 | struct drm_device *dev = ring->dev; | |
845 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 846 | unsigned long flags; |
e48d8634 DV |
847 | |
848 | if (!dev->irq_enabled) | |
849 | return false; | |
850 | ||
7338aefa | 851 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
852 | if (ring->irq_refcount++ == 0) |
853 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 854 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
855 | |
856 | return true; | |
857 | } | |
858 | ||
859 | static void | |
860 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
861 | { | |
862 | struct drm_device *dev = ring->dev; | |
863 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 864 | unsigned long flags; |
e48d8634 | 865 | |
7338aefa | 866 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
867 | if (--ring->irq_refcount == 0) |
868 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 869 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
870 | } |
871 | ||
b13c2b96 | 872 | static bool |
e3670319 | 873 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 874 | { |
78501eac | 875 | struct drm_device *dev = ring->dev; |
01a03331 | 876 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 877 | unsigned long flags; |
62fdfeaf | 878 | |
b13c2b96 CW |
879 | if (!dev->irq_enabled) |
880 | return false; | |
881 | ||
7338aefa | 882 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 883 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
884 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
885 | I915_WRITE(IMR, dev_priv->irq_mask); | |
886 | POSTING_READ(IMR); | |
887 | } | |
7338aefa | 888 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
889 | |
890 | return true; | |
62fdfeaf EA |
891 | } |
892 | ||
8187a2b7 | 893 | static void |
e3670319 | 894 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 895 | { |
78501eac | 896 | struct drm_device *dev = ring->dev; |
01a03331 | 897 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 898 | unsigned long flags; |
62fdfeaf | 899 | |
7338aefa | 900 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 901 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
902 | dev_priv->irq_mask |= ring->irq_enable_mask; |
903 | I915_WRITE(IMR, dev_priv->irq_mask); | |
904 | POSTING_READ(IMR); | |
905 | } | |
7338aefa | 906 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
907 | } |
908 | ||
c2798b19 CW |
909 | static bool |
910 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
911 | { | |
912 | struct drm_device *dev = ring->dev; | |
913 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 914 | unsigned long flags; |
c2798b19 CW |
915 | |
916 | if (!dev->irq_enabled) | |
917 | return false; | |
918 | ||
7338aefa | 919 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 920 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
921 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
922 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
923 | POSTING_READ16(IMR); | |
924 | } | |
7338aefa | 925 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
926 | |
927 | return true; | |
928 | } | |
929 | ||
930 | static void | |
931 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
932 | { | |
933 | struct drm_device *dev = ring->dev; | |
934 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 935 | unsigned long flags; |
c2798b19 | 936 | |
7338aefa | 937 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 938 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
939 | dev_priv->irq_mask |= ring->irq_enable_mask; |
940 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
941 | POSTING_READ16(IMR); | |
942 | } | |
7338aefa | 943 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
944 | } |
945 | ||
78501eac | 946 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 947 | { |
4593010b | 948 | struct drm_device *dev = ring->dev; |
78501eac | 949 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
950 | u32 mmio = 0; |
951 | ||
952 | /* The ring status page addresses are no longer next to the rest of | |
953 | * the ring registers as of gen7. | |
954 | */ | |
955 | if (IS_GEN7(dev)) { | |
956 | switch (ring->id) { | |
96154f2f | 957 | case RCS: |
4593010b EA |
958 | mmio = RENDER_HWS_PGA_GEN7; |
959 | break; | |
96154f2f | 960 | case BCS: |
4593010b EA |
961 | mmio = BLT_HWS_PGA_GEN7; |
962 | break; | |
96154f2f | 963 | case VCS: |
4593010b EA |
964 | mmio = BSD_HWS_PGA_GEN7; |
965 | break; | |
4a3dd19d | 966 | case VECS: |
9a8a2213 BW |
967 | mmio = VEBOX_HWS_PGA_GEN7; |
968 | break; | |
4593010b EA |
969 | } |
970 | } else if (IS_GEN6(ring->dev)) { | |
971 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
972 | } else { | |
eb0d4b75 | 973 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
974 | mmio = RING_HWS_PGA(ring->mmio_base); |
975 | } | |
976 | ||
78501eac CW |
977 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
978 | POSTING_READ(mmio); | |
884020bf CW |
979 | |
980 | /* Flush the TLB for this page */ | |
981 | if (INTEL_INFO(dev)->gen >= 6) { | |
982 | u32 reg = RING_INSTPM(ring->mmio_base); | |
983 | I915_WRITE(reg, | |
984 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
985 | INSTPM_SYNC_FLUSH)); | |
986 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
987 | 1000)) | |
988 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
989 | ring->name); | |
990 | } | |
8187a2b7 ZN |
991 | } |
992 | ||
b72f3acb | 993 | static int |
78501eac CW |
994 | bsd_ring_flush(struct intel_ring_buffer *ring, |
995 | u32 invalidate_domains, | |
996 | u32 flush_domains) | |
d1b851fc | 997 | { |
b72f3acb CW |
998 | int ret; |
999 | ||
b72f3acb CW |
1000 | ret = intel_ring_begin(ring, 2); |
1001 | if (ret) | |
1002 | return ret; | |
1003 | ||
1004 | intel_ring_emit(ring, MI_FLUSH); | |
1005 | intel_ring_emit(ring, MI_NOOP); | |
1006 | intel_ring_advance(ring); | |
1007 | return 0; | |
d1b851fc ZN |
1008 | } |
1009 | ||
3cce469c | 1010 | static int |
9d773091 | 1011 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 1012 | { |
3cce469c CW |
1013 | int ret; |
1014 | ||
1015 | ret = intel_ring_begin(ring, 4); | |
1016 | if (ret) | |
1017 | return ret; | |
6f392d54 | 1018 | |
3cce469c CW |
1019 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1020 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1021 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1022 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1023 | __intel_ring_advance(ring); |
d1b851fc | 1024 | |
3cce469c | 1025 | return 0; |
d1b851fc ZN |
1026 | } |
1027 | ||
0f46832f | 1028 | static bool |
25c06300 | 1029 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1030 | { |
1031 | struct drm_device *dev = ring->dev; | |
01a03331 | 1032 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1033 | unsigned long flags; |
0f46832f CW |
1034 | |
1035 | if (!dev->irq_enabled) | |
1036 | return false; | |
1037 | ||
7338aefa | 1038 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1039 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1040 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1041 | I915_WRITE_IMR(ring, |
1042 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1043 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1044 | else |
1045 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 1046 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1047 | } |
7338aefa | 1048 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1049 | |
1050 | return true; | |
1051 | } | |
1052 | ||
1053 | static void | |
25c06300 | 1054 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1055 | { |
1056 | struct drm_device *dev = ring->dev; | |
01a03331 | 1057 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1058 | unsigned long flags; |
0f46832f | 1059 | |
7338aefa | 1060 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1061 | if (--ring->irq_refcount == 0) { |
040d2baa | 1062 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1063 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1064 | else |
1065 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1066 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1067 | } |
7338aefa | 1068 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1069 | } |
1070 | ||
a19d2933 BW |
1071 | static bool |
1072 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |
1073 | { | |
1074 | struct drm_device *dev = ring->dev; | |
1075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1076 | unsigned long flags; | |
1077 | ||
1078 | if (!dev->irq_enabled) | |
1079 | return false; | |
1080 | ||
59cdb63d | 1081 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1082 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1083 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1084 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1085 | } |
59cdb63d | 1086 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1087 | |
1088 | return true; | |
1089 | } | |
1090 | ||
1091 | static void | |
1092 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |
1093 | { | |
1094 | struct drm_device *dev = ring->dev; | |
1095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1096 | unsigned long flags; | |
1097 | ||
1098 | if (!dev->irq_enabled) | |
1099 | return; | |
1100 | ||
59cdb63d | 1101 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1102 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1103 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1104 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1105 | } |
59cdb63d | 1106 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1107 | } |
1108 | ||
abd58f01 BW |
1109 | static bool |
1110 | gen8_ring_get_irq(struct intel_ring_buffer *ring) | |
1111 | { | |
1112 | struct drm_device *dev = ring->dev; | |
1113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1114 | unsigned long flags; | |
1115 | ||
1116 | if (!dev->irq_enabled) | |
1117 | return false; | |
1118 | ||
1119 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1120 | if (ring->irq_refcount++ == 0) { | |
1121 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1122 | I915_WRITE_IMR(ring, | |
1123 | ~(ring->irq_enable_mask | | |
1124 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1125 | } else { | |
1126 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1127 | } | |
1128 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1129 | } | |
1130 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1131 | ||
1132 | return true; | |
1133 | } | |
1134 | ||
1135 | static void | |
1136 | gen8_ring_put_irq(struct intel_ring_buffer *ring) | |
1137 | { | |
1138 | struct drm_device *dev = ring->dev; | |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | unsigned long flags; | |
1141 | ||
1142 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1143 | if (--ring->irq_refcount == 0) { | |
1144 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1145 | I915_WRITE_IMR(ring, | |
1146 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1147 | } else { | |
1148 | I915_WRITE_IMR(ring, ~0); | |
1149 | } | |
1150 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1151 | } | |
1152 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1153 | } | |
1154 | ||
d1b851fc | 1155 | static int |
d7d4eedd CW |
1156 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1157 | u32 offset, u32 length, | |
1158 | unsigned flags) | |
d1b851fc | 1159 | { |
e1f99ce6 | 1160 | int ret; |
78501eac | 1161 | |
e1f99ce6 CW |
1162 | ret = intel_ring_begin(ring, 2); |
1163 | if (ret) | |
1164 | return ret; | |
1165 | ||
78501eac | 1166 | intel_ring_emit(ring, |
65f56876 CW |
1167 | MI_BATCH_BUFFER_START | |
1168 | MI_BATCH_GTT | | |
d7d4eedd | 1169 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1170 | intel_ring_emit(ring, offset); |
78501eac CW |
1171 | intel_ring_advance(ring); |
1172 | ||
d1b851fc ZN |
1173 | return 0; |
1174 | } | |
1175 | ||
b45305fc DV |
1176 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1177 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1178 | static int |
fb3256da | 1179 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1180 | u32 offset, u32 len, |
1181 | unsigned flags) | |
62fdfeaf | 1182 | { |
c4e7a414 | 1183 | int ret; |
62fdfeaf | 1184 | |
b45305fc DV |
1185 | if (flags & I915_DISPATCH_PINNED) { |
1186 | ret = intel_ring_begin(ring, 4); | |
1187 | if (ret) | |
1188 | return ret; | |
62fdfeaf | 1189 | |
b45305fc DV |
1190 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1191 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1192 | intel_ring_emit(ring, offset + len - 8); | |
1193 | intel_ring_emit(ring, MI_NOOP); | |
1194 | intel_ring_advance(ring); | |
1195 | } else { | |
0d1aacac | 1196 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1197 | |
1198 | if (len > I830_BATCH_LIMIT) | |
1199 | return -ENOSPC; | |
1200 | ||
1201 | ret = intel_ring_begin(ring, 9+3); | |
1202 | if (ret) | |
1203 | return ret; | |
1204 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1205 | * scratch bo area (so that the CS never stumbles over its tlb | |
1206 | * invalidation bug) ... */ | |
1207 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1208 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1209 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1210 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1211 | intel_ring_emit(ring, 0); | |
1212 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1213 | intel_ring_emit(ring, cs_offset); | |
1214 | intel_ring_emit(ring, 0); | |
1215 | intel_ring_emit(ring, 4096); | |
1216 | intel_ring_emit(ring, offset); | |
1217 | intel_ring_emit(ring, MI_FLUSH); | |
1218 | ||
1219 | /* ... and execute it. */ | |
1220 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1221 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1222 | intel_ring_emit(ring, cs_offset + len - 8); | |
1223 | intel_ring_advance(ring); | |
1224 | } | |
e1f99ce6 | 1225 | |
fb3256da DV |
1226 | return 0; |
1227 | } | |
1228 | ||
1229 | static int | |
1230 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1231 | u32 offset, u32 len, |
1232 | unsigned flags) | |
fb3256da DV |
1233 | { |
1234 | int ret; | |
1235 | ||
1236 | ret = intel_ring_begin(ring, 2); | |
1237 | if (ret) | |
1238 | return ret; | |
1239 | ||
65f56876 | 1240 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1241 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1242 | intel_ring_advance(ring); |
62fdfeaf | 1243 | |
62fdfeaf EA |
1244 | return 0; |
1245 | } | |
1246 | ||
78501eac | 1247 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1248 | { |
05394f39 | 1249 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1250 | |
8187a2b7 ZN |
1251 | obj = ring->status_page.obj; |
1252 | if (obj == NULL) | |
62fdfeaf | 1253 | return; |
62fdfeaf | 1254 | |
9da3da66 | 1255 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1256 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1257 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1258 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1259 | } |
1260 | ||
78501eac | 1261 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1262 | { |
78501eac | 1263 | struct drm_device *dev = ring->dev; |
05394f39 | 1264 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1265 | int ret; |
1266 | ||
62fdfeaf EA |
1267 | obj = i915_gem_alloc_object(dev, 4096); |
1268 | if (obj == NULL) { | |
1269 | DRM_ERROR("Failed to allocate status page\n"); | |
1270 | ret = -ENOMEM; | |
1271 | goto err; | |
1272 | } | |
e4ffd173 CW |
1273 | |
1274 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1275 | |
c37e2204 | 1276 | ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); |
62fdfeaf | 1277 | if (ret != 0) { |
62fdfeaf EA |
1278 | goto err_unref; |
1279 | } | |
1280 | ||
f343c5f6 | 1281 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1282 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1283 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1284 | ret = -ENOMEM; |
62fdfeaf EA |
1285 | goto err_unpin; |
1286 | } | |
8187a2b7 ZN |
1287 | ring->status_page.obj = obj; |
1288 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1289 | |
8187a2b7 ZN |
1290 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1291 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1292 | |
1293 | return 0; | |
1294 | ||
1295 | err_unpin: | |
d7f46fc4 | 1296 | i915_gem_object_ggtt_unpin(obj); |
62fdfeaf | 1297 | err_unref: |
05394f39 | 1298 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1299 | err: |
8187a2b7 | 1300 | return ret; |
62fdfeaf EA |
1301 | } |
1302 | ||
035dc1e0 | 1303 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
6b8294a4 CW |
1304 | { |
1305 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1306 | |
1307 | if (!dev_priv->status_page_dmah) { | |
1308 | dev_priv->status_page_dmah = | |
1309 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1310 | if (!dev_priv->status_page_dmah) | |
1311 | return -ENOMEM; | |
1312 | } | |
1313 | ||
6b8294a4 CW |
1314 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1315 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
c43b5634 BW |
1320 | static int intel_init_ring_buffer(struct drm_device *dev, |
1321 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1322 | { |
05394f39 | 1323 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1324 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1325 | int ret; |
1326 | ||
8187a2b7 | 1327 | ring->dev = dev; |
23bc5982 CW |
1328 | INIT_LIST_HEAD(&ring->active_list); |
1329 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1330 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1331 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1332 | |
b259f673 | 1333 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1334 | |
8187a2b7 | 1335 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1336 | ret = init_status_page(ring); |
8187a2b7 ZN |
1337 | if (ret) |
1338 | return ret; | |
6b8294a4 CW |
1339 | } else { |
1340 | BUG_ON(ring->id != RCS); | |
035dc1e0 | 1341 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1342 | if (ret) |
1343 | return ret; | |
8187a2b7 | 1344 | } |
62fdfeaf | 1345 | |
ebc052e0 CW |
1346 | obj = NULL; |
1347 | if (!HAS_LLC(dev)) | |
1348 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1349 | if (obj == NULL) | |
1350 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1351 | if (obj == NULL) { |
1352 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1353 | ret = -ENOMEM; |
dd785e35 | 1354 | goto err_hws; |
62fdfeaf | 1355 | } |
62fdfeaf | 1356 | |
05394f39 | 1357 | ring->obj = obj; |
8187a2b7 | 1358 | |
c37e2204 | 1359 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1360 | if (ret) |
1361 | goto err_unref; | |
62fdfeaf | 1362 | |
3eef8918 CW |
1363 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1364 | if (ret) | |
1365 | goto err_unpin; | |
1366 | ||
dd2757f8 | 1367 | ring->virtual_start = |
f343c5f6 | 1368 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
dd2757f8 | 1369 | ring->size); |
4225d0f2 | 1370 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1371 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1372 | ret = -EINVAL; |
dd785e35 | 1373 | goto err_unpin; |
62fdfeaf EA |
1374 | } |
1375 | ||
78501eac | 1376 | ret = ring->init(ring); |
dd785e35 CW |
1377 | if (ret) |
1378 | goto err_unmap; | |
62fdfeaf | 1379 | |
55249baa CW |
1380 | /* Workaround an erratum on the i830 which causes a hang if |
1381 | * the TAIL pointer points to within the last 2 cachelines | |
1382 | * of the buffer. | |
1383 | */ | |
1384 | ring->effective_size = ring->size; | |
27c1cbd0 | 1385 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1386 | ring->effective_size -= 128; |
1387 | ||
c584fe47 | 1388 | return 0; |
dd785e35 CW |
1389 | |
1390 | err_unmap: | |
4225d0f2 | 1391 | iounmap(ring->virtual_start); |
dd785e35 | 1392 | err_unpin: |
d7f46fc4 | 1393 | i915_gem_object_ggtt_unpin(obj); |
dd785e35 | 1394 | err_unref: |
05394f39 CW |
1395 | drm_gem_object_unreference(&obj->base); |
1396 | ring->obj = NULL; | |
dd785e35 | 1397 | err_hws: |
78501eac | 1398 | cleanup_status_page(ring); |
8187a2b7 | 1399 | return ret; |
62fdfeaf EA |
1400 | } |
1401 | ||
78501eac | 1402 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1403 | { |
33626e6a CW |
1404 | struct drm_i915_private *dev_priv; |
1405 | int ret; | |
1406 | ||
05394f39 | 1407 | if (ring->obj == NULL) |
62fdfeaf EA |
1408 | return; |
1409 | ||
33626e6a CW |
1410 | /* Disable the ring buffer. The ring must be idle at this point */ |
1411 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1412 | ret = intel_ring_idle(ring); |
3d57e5bd | 1413 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
29ee3991 CW |
1414 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
1415 | ring->name, ret); | |
1416 | ||
33626e6a CW |
1417 | I915_WRITE_CTL(ring, 0); |
1418 | ||
4225d0f2 | 1419 | iounmap(ring->virtual_start); |
62fdfeaf | 1420 | |
d7f46fc4 | 1421 | i915_gem_object_ggtt_unpin(ring->obj); |
05394f39 CW |
1422 | drm_gem_object_unreference(&ring->obj->base); |
1423 | ring->obj = NULL; | |
3d57e5bd BW |
1424 | ring->preallocated_lazy_request = NULL; |
1425 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1426 | |
8d19215b ZN |
1427 | if (ring->cleanup) |
1428 | ring->cleanup(ring); | |
1429 | ||
78501eac | 1430 | cleanup_status_page(ring); |
62fdfeaf EA |
1431 | } |
1432 | ||
a71d8d94 CW |
1433 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
1434 | { | |
1435 | struct drm_i915_gem_request *request; | |
1f70999f | 1436 | u32 seqno = 0, tail; |
a71d8d94 CW |
1437 | int ret; |
1438 | ||
a71d8d94 CW |
1439 | if (ring->last_retired_head != -1) { |
1440 | ring->head = ring->last_retired_head; | |
1441 | ring->last_retired_head = -1; | |
1f70999f | 1442 | |
a71d8d94 CW |
1443 | ring->space = ring_space(ring); |
1444 | if (ring->space >= n) | |
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | list_for_each_entry(request, &ring->request_list, list) { | |
1449 | int space; | |
1450 | ||
1451 | if (request->tail == -1) | |
1452 | continue; | |
1453 | ||
633cf8f5 | 1454 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1455 | if (space < 0) |
1456 | space += ring->size; | |
1457 | if (space >= n) { | |
1458 | seqno = request->seqno; | |
1f70999f | 1459 | tail = request->tail; |
a71d8d94 CW |
1460 | break; |
1461 | } | |
1462 | ||
1463 | /* Consume this request in case we need more space than | |
1464 | * is available and so need to prevent a race between | |
1465 | * updating last_retired_head and direct reads of | |
1466 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1467 | */ | |
1468 | request->tail = -1; | |
1469 | } | |
1470 | ||
1471 | if (seqno == 0) | |
1472 | return -ENOSPC; | |
1473 | ||
1f70999f | 1474 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1475 | if (ret) |
1476 | return ret; | |
1477 | ||
1f70999f | 1478 | ring->head = tail; |
a71d8d94 CW |
1479 | ring->space = ring_space(ring); |
1480 | if (WARN_ON(ring->space < n)) | |
1481 | return -ENOSPC; | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
3e960501 | 1486 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1487 | { |
78501eac | 1488 | struct drm_device *dev = ring->dev; |
cae5852d | 1489 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1490 | unsigned long end; |
a71d8d94 | 1491 | int ret; |
c7dca47b | 1492 | |
a71d8d94 CW |
1493 | ret = intel_ring_wait_request(ring, n); |
1494 | if (ret != -ENOSPC) | |
1495 | return ret; | |
1496 | ||
09246732 CW |
1497 | /* force the tail write in case we have been skipping them */ |
1498 | __intel_ring_advance(ring); | |
1499 | ||
db53a302 | 1500 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1501 | /* With GEM the hangcheck timer should kick us out of the loop, |
1502 | * leaving it early runs the risk of corrupting GEM state (due | |
1503 | * to running on almost untested codepaths). But on resume | |
1504 | * timers don't work yet, so prevent a complete hang in that | |
1505 | * case by choosing an insanely large timeout. */ | |
1506 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1507 | |
8187a2b7 | 1508 | do { |
c7dca47b CW |
1509 | ring->head = I915_READ_HEAD(ring); |
1510 | ring->space = ring_space(ring); | |
62fdfeaf | 1511 | if (ring->space >= n) { |
db53a302 | 1512 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1513 | return 0; |
1514 | } | |
1515 | ||
1516 | if (dev->primary->master) { | |
1517 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1518 | if (master_priv->sarea_priv) | |
1519 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1520 | } | |
d1b851fc | 1521 | |
e60a0b10 | 1522 | msleep(1); |
d6b2c790 | 1523 | |
33196ded DV |
1524 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1525 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1526 | if (ret) |
1527 | return ret; | |
8187a2b7 | 1528 | } while (!time_after(jiffies, end)); |
db53a302 | 1529 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1530 | return -EBUSY; |
1531 | } | |
62fdfeaf | 1532 | |
3e960501 CW |
1533 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1534 | { | |
1535 | uint32_t __iomem *virt; | |
1536 | int rem = ring->size - ring->tail; | |
1537 | ||
1538 | if (ring->space < rem) { | |
1539 | int ret = ring_wait_for_space(ring, rem); | |
1540 | if (ret) | |
1541 | return ret; | |
1542 | } | |
1543 | ||
1544 | virt = ring->virtual_start + ring->tail; | |
1545 | rem /= 4; | |
1546 | while (rem--) | |
1547 | iowrite32(MI_NOOP, virt++); | |
1548 | ||
1549 | ring->tail = 0; | |
1550 | ring->space = ring_space(ring); | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | ||
1555 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1556 | { | |
1557 | u32 seqno; | |
1558 | int ret; | |
1559 | ||
1560 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1561 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1562 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1563 | if (ret) |
1564 | return ret; | |
1565 | } | |
1566 | ||
1567 | /* Wait upon the last request to be completed */ | |
1568 | if (list_empty(&ring->request_list)) | |
1569 | return 0; | |
1570 | ||
1571 | seqno = list_entry(ring->request_list.prev, | |
1572 | struct drm_i915_gem_request, | |
1573 | list)->seqno; | |
1574 | ||
1575 | return i915_wait_seqno(ring, seqno); | |
1576 | } | |
1577 | ||
9d773091 CW |
1578 | static int |
1579 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1580 | { | |
1823521d | 1581 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1582 | return 0; |
1583 | ||
3c0e234c CW |
1584 | if (ring->preallocated_lazy_request == NULL) { |
1585 | struct drm_i915_gem_request *request; | |
1586 | ||
1587 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1588 | if (request == NULL) | |
1589 | return -ENOMEM; | |
1590 | ||
1591 | ring->preallocated_lazy_request = request; | |
1592 | } | |
1593 | ||
1823521d | 1594 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1595 | } |
1596 | ||
304d695c CW |
1597 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
1598 | int bytes) | |
cbcc80df MK |
1599 | { |
1600 | int ret; | |
1601 | ||
1602 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1603 | ret = intel_wrap_ring_buffer(ring); | |
1604 | if (unlikely(ret)) | |
1605 | return ret; | |
1606 | } | |
1607 | ||
1608 | if (unlikely(ring->space < bytes)) { | |
1609 | ret = ring_wait_for_space(ring, bytes); | |
1610 | if (unlikely(ret)) | |
1611 | return ret; | |
1612 | } | |
1613 | ||
cbcc80df MK |
1614 | return 0; |
1615 | } | |
1616 | ||
e1f99ce6 CW |
1617 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1618 | int num_dwords) | |
8187a2b7 | 1619 | { |
de2b9985 | 1620 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1621 | int ret; |
78501eac | 1622 | |
33196ded DV |
1623 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1624 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1625 | if (ret) |
1626 | return ret; | |
21dd3734 | 1627 | |
304d695c CW |
1628 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1629 | if (ret) | |
1630 | return ret; | |
1631 | ||
9d773091 CW |
1632 | /* Preallocate the olr before touching the ring */ |
1633 | ret = intel_ring_alloc_seqno(ring); | |
1634 | if (ret) | |
1635 | return ret; | |
1636 | ||
304d695c CW |
1637 | ring->space -= num_dwords * sizeof(uint32_t); |
1638 | return 0; | |
8187a2b7 | 1639 | } |
78501eac | 1640 | |
f7e98ad4 | 1641 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1642 | { |
f7e98ad4 | 1643 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 | 1644 | |
1823521d | 1645 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1646 | |
f7e98ad4 MK |
1647 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1648 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1649 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
5020150b BW |
1650 | if (HAS_VEBOX(ring->dev)) |
1651 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); | |
e1f99ce6 | 1652 | } |
d97ed339 | 1653 | |
f7e98ad4 | 1654 | ring->set_seqno(ring, seqno); |
92cab734 | 1655 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1656 | } |
62fdfeaf | 1657 | |
78501eac | 1658 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1659 | u32 value) |
881f47b6 | 1660 | { |
0206e353 | 1661 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1662 | |
1663 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1664 | |
1665 | /* Disable notification that the ring is IDLE. The GT | |
1666 | * will then assume that it is busy and bring it out of rc6. | |
1667 | */ | |
0206e353 | 1668 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1669 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1670 | ||
1671 | /* Clear the context id. Here be magic! */ | |
1672 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1673 | |
12f55818 | 1674 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1675 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1676 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1677 | 50)) | |
1678 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1679 | |
12f55818 | 1680 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1681 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1682 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1683 | ||
1684 | /* Let the ring send IDLE messages to the GT again, | |
1685 | * and so let it sleep to conserve power when idle. | |
1686 | */ | |
0206e353 | 1687 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1688 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1689 | } |
1690 | ||
ea251324 BW |
1691 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1692 | u32 invalidate, u32 flush) | |
881f47b6 | 1693 | { |
71a77e07 | 1694 | uint32_t cmd; |
b72f3acb CW |
1695 | int ret; |
1696 | ||
b72f3acb CW |
1697 | ret = intel_ring_begin(ring, 4); |
1698 | if (ret) | |
1699 | return ret; | |
1700 | ||
71a77e07 | 1701 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1702 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1703 | cmd += 1; | |
9a289771 JB |
1704 | /* |
1705 | * Bspec vol 1c.5 - video engine command streamer: | |
1706 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1707 | * operation is complete. This bit is only valid when the | |
1708 | * Post-Sync Operation field is a value of 1h or 3h." | |
1709 | */ | |
71a77e07 | 1710 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1711 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1712 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1713 | intel_ring_emit(ring, cmd); |
9a289771 | 1714 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1715 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1716 | intel_ring_emit(ring, 0); /* upper addr */ | |
1717 | intel_ring_emit(ring, 0); /* value */ | |
1718 | } else { | |
1719 | intel_ring_emit(ring, 0); | |
1720 | intel_ring_emit(ring, MI_NOOP); | |
1721 | } | |
b72f3acb CW |
1722 | intel_ring_advance(ring); |
1723 | return 0; | |
881f47b6 XH |
1724 | } |
1725 | ||
1c7a0623 BW |
1726 | static int |
1727 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1728 | u32 offset, u32 len, | |
1729 | unsigned flags) | |
1730 | { | |
28cf5415 BW |
1731 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1732 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
1733 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
1734 | int ret; |
1735 | ||
1736 | ret = intel_ring_begin(ring, 4); | |
1737 | if (ret) | |
1738 | return ret; | |
1739 | ||
1740 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 1741 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
1c7a0623 BW |
1742 | intel_ring_emit(ring, offset); |
1743 | intel_ring_emit(ring, 0); | |
1744 | intel_ring_emit(ring, MI_NOOP); | |
1745 | intel_ring_advance(ring); | |
1746 | ||
1747 | return 0; | |
1748 | } | |
1749 | ||
d7d4eedd CW |
1750 | static int |
1751 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1752 | u32 offset, u32 len, | |
1753 | unsigned flags) | |
1754 | { | |
1755 | int ret; | |
1756 | ||
1757 | ret = intel_ring_begin(ring, 2); | |
1758 | if (ret) | |
1759 | return ret; | |
1760 | ||
1761 | intel_ring_emit(ring, | |
1762 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1763 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1764 | /* bit0-7 is the length on GEN6+ */ | |
1765 | intel_ring_emit(ring, offset); | |
1766 | intel_ring_advance(ring); | |
1767 | ||
1768 | return 0; | |
1769 | } | |
1770 | ||
881f47b6 | 1771 | static int |
78501eac | 1772 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1773 | u32 offset, u32 len, |
1774 | unsigned flags) | |
881f47b6 | 1775 | { |
0206e353 | 1776 | int ret; |
ab6f8e32 | 1777 | |
0206e353 AJ |
1778 | ret = intel_ring_begin(ring, 2); |
1779 | if (ret) | |
1780 | return ret; | |
e1f99ce6 | 1781 | |
d7d4eedd CW |
1782 | intel_ring_emit(ring, |
1783 | MI_BATCH_BUFFER_START | | |
1784 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1785 | /* bit0-7 is the length on GEN6+ */ |
1786 | intel_ring_emit(ring, offset); | |
1787 | intel_ring_advance(ring); | |
ab6f8e32 | 1788 | |
0206e353 | 1789 | return 0; |
881f47b6 XH |
1790 | } |
1791 | ||
549f7365 CW |
1792 | /* Blitter support (SandyBridge+) */ |
1793 | ||
ea251324 BW |
1794 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1795 | u32 invalidate, u32 flush) | |
8d19215b | 1796 | { |
fd3da6c9 | 1797 | struct drm_device *dev = ring->dev; |
71a77e07 | 1798 | uint32_t cmd; |
b72f3acb CW |
1799 | int ret; |
1800 | ||
6a233c78 | 1801 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1802 | if (ret) |
1803 | return ret; | |
1804 | ||
71a77e07 | 1805 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1806 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1807 | cmd += 1; | |
9a289771 JB |
1808 | /* |
1809 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1810 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1811 | * operation is complete. This bit is only valid when the | |
1812 | * Post-Sync Operation field is a value of 1h or 3h." | |
1813 | */ | |
71a77e07 | 1814 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1815 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1816 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1817 | intel_ring_emit(ring, cmd); |
9a289771 | 1818 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1819 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1820 | intel_ring_emit(ring, 0); /* upper addr */ | |
1821 | intel_ring_emit(ring, 0); /* value */ | |
1822 | } else { | |
1823 | intel_ring_emit(ring, 0); | |
1824 | intel_ring_emit(ring, MI_NOOP); | |
1825 | } | |
b72f3acb | 1826 | intel_ring_advance(ring); |
fd3da6c9 | 1827 | |
9688ecad | 1828 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
1829 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
1830 | ||
b72f3acb | 1831 | return 0; |
8d19215b ZN |
1832 | } |
1833 | ||
5c1143bb XH |
1834 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1835 | { | |
1836 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1837 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1838 | |
59465b5f DV |
1839 | ring->name = "render ring"; |
1840 | ring->id = RCS; | |
1841 | ring->mmio_base = RENDER_RING_BASE; | |
1842 | ||
1ec14ad3 CW |
1843 | if (INTEL_INFO(dev)->gen >= 6) { |
1844 | ring->add_request = gen6_add_request; | |
4772eaeb | 1845 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1846 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1847 | ring->flush = gen6_render_ring_flush; |
abd58f01 | 1848 | if (INTEL_INFO(dev)->gen >= 8) { |
a5f3d68e | 1849 | ring->flush = gen8_render_ring_flush; |
abd58f01 BW |
1850 | ring->irq_get = gen8_ring_get_irq; |
1851 | ring->irq_put = gen8_ring_put_irq; | |
1852 | } else { | |
1853 | ring->irq_get = gen6_ring_get_irq; | |
1854 | ring->irq_put = gen6_ring_put_irq; | |
1855 | } | |
cc609d5d | 1856 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1857 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1858 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1859 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1860 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1861 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1862 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1863 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1864 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1865 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1866 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1867 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1868 | } else if (IS_GEN5(dev)) { |
1869 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1870 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1871 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1872 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1873 | ring->irq_get = gen5_ring_get_irq; |
1874 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1875 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1876 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1877 | } else { |
8620a3a9 | 1878 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1879 | if (INTEL_INFO(dev)->gen < 4) |
1880 | ring->flush = gen2_render_ring_flush; | |
1881 | else | |
1882 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1883 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1884 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1885 | if (IS_GEN2(dev)) { |
1886 | ring->irq_get = i8xx_ring_get_irq; | |
1887 | ring->irq_put = i8xx_ring_put_irq; | |
1888 | } else { | |
1889 | ring->irq_get = i9xx_ring_get_irq; | |
1890 | ring->irq_put = i9xx_ring_put_irq; | |
1891 | } | |
e3670319 | 1892 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1893 | } |
59465b5f | 1894 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1895 | if (IS_HASWELL(dev)) |
1896 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
1897 | else if (IS_GEN8(dev)) |
1898 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 1899 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
1900 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1901 | else if (INTEL_INFO(dev)->gen >= 4) | |
1902 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1903 | else if (IS_I830(dev) || IS_845G(dev)) | |
1904 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1905 | else | |
1906 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1907 | ring->init = init_render_ring; |
1908 | ring->cleanup = render_ring_cleanup; | |
1909 | ||
b45305fc DV |
1910 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1911 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1912 | struct drm_i915_gem_object *obj; | |
1913 | int ret; | |
1914 | ||
1915 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1916 | if (obj == NULL) { | |
1917 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1918 | return -ENOMEM; | |
1919 | } | |
1920 | ||
c37e2204 | 1921 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
b45305fc DV |
1922 | if (ret != 0) { |
1923 | drm_gem_object_unreference(&obj->base); | |
1924 | DRM_ERROR("Failed to ping batch bo\n"); | |
1925 | return ret; | |
1926 | } | |
1927 | ||
0d1aacac CW |
1928 | ring->scratch.obj = obj; |
1929 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
1930 | } |
1931 | ||
1ec14ad3 | 1932 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1933 | } |
1934 | ||
e8616b6c CW |
1935 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1936 | { | |
1937 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1938 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
6b8294a4 | 1939 | int ret; |
e8616b6c | 1940 | |
59465b5f DV |
1941 | ring->name = "render ring"; |
1942 | ring->id = RCS; | |
1943 | ring->mmio_base = RENDER_RING_BASE; | |
1944 | ||
e8616b6c | 1945 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1946 | /* non-kms not supported on gen6+ */ |
1947 | return -ENODEV; | |
e8616b6c | 1948 | } |
28f0cbf7 DV |
1949 | |
1950 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1951 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1952 | * the special gen5 functions. */ | |
1953 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1954 | if (INTEL_INFO(dev)->gen < 4) |
1955 | ring->flush = gen2_render_ring_flush; | |
1956 | else | |
1957 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1958 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1959 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1960 | if (IS_GEN2(dev)) { |
1961 | ring->irq_get = i8xx_ring_get_irq; | |
1962 | ring->irq_put = i8xx_ring_put_irq; | |
1963 | } else { | |
1964 | ring->irq_get = i9xx_ring_get_irq; | |
1965 | ring->irq_put = i9xx_ring_put_irq; | |
1966 | } | |
28f0cbf7 | 1967 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1968 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1969 | if (INTEL_INFO(dev)->gen >= 4) |
1970 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1971 | else if (IS_I830(dev) || IS_845G(dev)) | |
1972 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1973 | else | |
1974 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1975 | ring->init = init_render_ring; |
1976 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
1977 | |
1978 | ring->dev = dev; | |
1979 | INIT_LIST_HEAD(&ring->active_list); | |
1980 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1981 | |
1982 | ring->size = size; | |
1983 | ring->effective_size = ring->size; | |
17f10fdc | 1984 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
e8616b6c CW |
1985 | ring->effective_size -= 128; |
1986 | ||
4225d0f2 DV |
1987 | ring->virtual_start = ioremap_wc(start, size); |
1988 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1989 | DRM_ERROR("can not ioremap virtual address for" |
1990 | " ring buffer\n"); | |
1991 | return -ENOMEM; | |
1992 | } | |
1993 | ||
6b8294a4 | 1994 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 1995 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1996 | if (ret) |
1997 | return ret; | |
1998 | } | |
1999 | ||
e8616b6c CW |
2000 | return 0; |
2001 | } | |
2002 | ||
5c1143bb XH |
2003 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2004 | { | |
2005 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2006 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2007 | |
58fa3835 DV |
2008 | ring->name = "bsd ring"; |
2009 | ring->id = VCS; | |
2010 | ||
0fd2c201 | 2011 | ring->write_tail = ring_write_tail; |
780f18c8 | 2012 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2013 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2014 | /* gen6 bsd needs a special wa for tail updates */ |
2015 | if (IS_GEN6(dev)) | |
2016 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2017 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2018 | ring->add_request = gen6_add_request; |
2019 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2020 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2021 | if (INTEL_INFO(dev)->gen >= 8) { |
2022 | ring->irq_enable_mask = | |
2023 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2024 | ring->irq_get = gen8_ring_get_irq; | |
2025 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2026 | ring->dispatch_execbuffer = |
2027 | gen8_ring_dispatch_execbuffer; | |
abd58f01 BW |
2028 | } else { |
2029 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2030 | ring->irq_get = gen6_ring_get_irq; | |
2031 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2032 | ring->dispatch_execbuffer = |
2033 | gen6_ring_dispatch_execbuffer; | |
abd58f01 | 2034 | } |
686cb5f9 | 2035 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2036 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
2037 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2038 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 2039 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
2040 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
2041 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
2042 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 2043 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
2044 | } else { |
2045 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2046 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2047 | ring->add_request = i9xx_add_request; |
58fa3835 | 2048 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2049 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2050 | if (IS_GEN5(dev)) { |
cc609d5d | 2051 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2052 | ring->irq_get = gen5_ring_get_irq; |
2053 | ring->irq_put = gen5_ring_put_irq; | |
2054 | } else { | |
e3670319 | 2055 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2056 | ring->irq_get = i9xx_ring_get_irq; |
2057 | ring->irq_put = i9xx_ring_put_irq; | |
2058 | } | |
fb3256da | 2059 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2060 | } |
2061 | ring->init = init_ring_common; | |
2062 | ||
1ec14ad3 | 2063 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2064 | } |
549f7365 CW |
2065 | |
2066 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
2067 | { | |
2068 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2069 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 2070 | |
3535d9dd DV |
2071 | ring->name = "blitter ring"; |
2072 | ring->id = BCS; | |
2073 | ||
2074 | ring->mmio_base = BLT_RING_BASE; | |
2075 | ring->write_tail = ring_write_tail; | |
ea251324 | 2076 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2077 | ring->add_request = gen6_add_request; |
2078 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2079 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2080 | if (INTEL_INFO(dev)->gen >= 8) { |
2081 | ring->irq_enable_mask = | |
2082 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2083 | ring->irq_get = gen8_ring_get_irq; | |
2084 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2085 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2086 | } else { |
2087 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2088 | ring->irq_get = gen6_ring_get_irq; | |
2089 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2090 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2091 | } |
686cb5f9 | 2092 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2093 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
2094 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2095 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 2096 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
2097 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
2098 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
2099 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 2100 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 2101 | ring->init = init_ring_common; |
549f7365 | 2102 | |
1ec14ad3 | 2103 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2104 | } |
a7b9761d | 2105 | |
9a8a2213 BW |
2106 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2107 | { | |
2108 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2109 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; | |
2110 | ||
2111 | ring->name = "video enhancement ring"; | |
2112 | ring->id = VECS; | |
2113 | ||
2114 | ring->mmio_base = VEBOX_RING_BASE; | |
2115 | ring->write_tail = ring_write_tail; | |
2116 | ring->flush = gen6_ring_flush; | |
2117 | ring->add_request = gen6_add_request; | |
2118 | ring->get_seqno = gen6_ring_get_seqno; | |
2119 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2120 | |
2121 | if (INTEL_INFO(dev)->gen >= 8) { | |
2122 | ring->irq_enable_mask = | |
40c499f9 | 2123 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2124 | ring->irq_get = gen8_ring_get_irq; |
2125 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2126 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2127 | } else { |
2128 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2129 | ring->irq_get = hsw_vebox_get_irq; | |
2130 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2131 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2132 | } |
9a8a2213 BW |
2133 | ring->sync_to = gen6_ring_sync; |
2134 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2135 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2136 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2137 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2138 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
2139 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
2140 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
2141 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
2142 | ring->init = init_ring_common; | |
2143 | ||
2144 | return intel_init_ring_buffer(dev, ring); | |
2145 | } | |
2146 | ||
a7b9761d CW |
2147 | int |
2148 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
2149 | { | |
2150 | int ret; | |
2151 | ||
2152 | if (!ring->gpu_caches_dirty) | |
2153 | return 0; | |
2154 | ||
2155 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2156 | if (ret) | |
2157 | return ret; | |
2158 | ||
2159 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2160 | ||
2161 | ring->gpu_caches_dirty = false; | |
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | int | |
2166 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
2167 | { | |
2168 | uint32_t flush_domains; | |
2169 | int ret; | |
2170 | ||
2171 | flush_domains = 0; | |
2172 | if (ring->gpu_caches_dirty) | |
2173 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2174 | ||
2175 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2176 | if (ret) | |
2177 | return ret; | |
2178 | ||
2179 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2180 | ||
2181 | ring->gpu_caches_dirty = false; | |
2182 | return 0; | |
2183 | } |