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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
18393f63 | 52 | |
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
4f54741e DG |
55 | int space = head - tail; |
56 | if (space <= 0) | |
1cf0ba14 | 57 | space += size; |
4f54741e | 58 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
59 | } |
60 | ||
ebd0fd4b DG |
61 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
62 | { | |
63 | if (ringbuf->last_retired_head != -1) { | |
64 | ringbuf->head = ringbuf->last_retired_head; | |
65 | ringbuf->last_retired_head = -1; | |
66 | } | |
67 | ||
68 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
69 | ringbuf->tail, ringbuf->size); | |
70 | } | |
71 | ||
82e104cc | 72 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 73 | { |
ebd0fd4b DG |
74 | intel_ring_update_space(ringbuf); |
75 | return ringbuf->space; | |
1cf0ba14 CW |
76 | } |
77 | ||
82e104cc | 78 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
81 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
82 | } | |
09246732 | 83 | |
a4872ba6 | 84 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 85 | { |
93b0a4e0 OM |
86 | struct intel_ringbuffer *ringbuf = ring->buffer; |
87 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 88 | if (intel_ring_stopped(ring)) |
09246732 | 89 | return; |
93b0a4e0 | 90 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
91 | } |
92 | ||
b72f3acb | 93 | static int |
a4872ba6 | 94 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
95 | u32 invalidate_domains, |
96 | u32 flush_domains) | |
97 | { | |
98 | u32 cmd; | |
99 | int ret; | |
100 | ||
101 | cmd = MI_FLUSH; | |
31b14c9f | 102 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
103 | cmd |= MI_NO_WRITE_FLUSH; |
104 | ||
105 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
106 | cmd |= MI_READ_FLUSH; | |
107 | ||
108 | ret = intel_ring_begin(ring, 2); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
112 | intel_ring_emit(ring, cmd); | |
113 | intel_ring_emit(ring, MI_NOOP); | |
114 | intel_ring_advance(ring); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | static int | |
a4872ba6 | 120 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
121 | u32 invalidate_domains, |
122 | u32 flush_domains) | |
62fdfeaf | 123 | { |
78501eac | 124 | struct drm_device *dev = ring->dev; |
6f392d54 | 125 | u32 cmd; |
b72f3acb | 126 | int ret; |
6f392d54 | 127 | |
36d527de CW |
128 | /* |
129 | * read/write caches: | |
130 | * | |
131 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
132 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
133 | * also flushed at 2d versus 3d pipeline switches. | |
134 | * | |
135 | * read-only caches: | |
136 | * | |
137 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
138 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
139 | * | |
140 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
141 | * | |
142 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
143 | * invalidated when MI_EXE_FLUSH is set. | |
144 | * | |
145 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
146 | * invalidated with every MI_FLUSH. | |
147 | * | |
148 | * TLBs: | |
149 | * | |
150 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
151 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
152 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
153 | * are flushed at any MI_FLUSH. | |
154 | */ | |
155 | ||
156 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 157 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 158 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
159 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
160 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 161 | |
36d527de CW |
162 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
163 | (IS_G4X(dev) || IS_GEN5(dev))) | |
164 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 165 | |
36d527de CW |
166 | ret = intel_ring_begin(ring, 2); |
167 | if (ret) | |
168 | return ret; | |
b72f3acb | 169 | |
36d527de CW |
170 | intel_ring_emit(ring, cmd); |
171 | intel_ring_emit(ring, MI_NOOP); | |
172 | intel_ring_advance(ring); | |
b72f3acb CW |
173 | |
174 | return 0; | |
8187a2b7 ZN |
175 | } |
176 | ||
8d315287 JB |
177 | /** |
178 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
179 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
180 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
181 | * | |
182 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
183 | * produced by non-pipelined state commands), software needs to first | |
184 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
185 | * 0. | |
186 | * | |
187 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
188 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
189 | * | |
190 | * And the workaround for these two requires this workaround first: | |
191 | * | |
192 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
193 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
194 | * flushes. | |
195 | * | |
196 | * And this last workaround is tricky because of the requirements on | |
197 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
198 | * volume 2 part 1: | |
199 | * | |
200 | * "1 of the following must also be set: | |
201 | * - Render Target Cache Flush Enable ([12] of DW1) | |
202 | * - Depth Cache Flush Enable ([0] of DW1) | |
203 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
204 | * - Depth Stall ([13] of DW1) | |
205 | * - Post-Sync Operation ([13] of DW1) | |
206 | * - Notify Enable ([8] of DW1)" | |
207 | * | |
208 | * The cache flushes require the workaround flush that triggered this | |
209 | * one, so we can't use it. Depth stall would trigger the same. | |
210 | * Post-sync nonzero is what triggered this second workaround, so we | |
211 | * can't use that one either. Notify enable is IRQs, which aren't | |
212 | * really our business. That leaves only stall at scoreboard. | |
213 | */ | |
214 | static int | |
a4872ba6 | 215 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 216 | { |
18393f63 | 217 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
218 | int ret; |
219 | ||
220 | ||
221 | ret = intel_ring_begin(ring, 6); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
226 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
227 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
228 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
229 | intel_ring_emit(ring, 0); /* low dword */ | |
230 | intel_ring_emit(ring, 0); /* high dword */ | |
231 | intel_ring_emit(ring, MI_NOOP); | |
232 | intel_ring_advance(ring); | |
233 | ||
234 | ret = intel_ring_begin(ring, 6); | |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
239 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
240 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
241 | intel_ring_emit(ring, 0); | |
242 | intel_ring_emit(ring, 0); | |
243 | intel_ring_emit(ring, MI_NOOP); | |
244 | intel_ring_advance(ring); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static int | |
a4872ba6 | 250 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
251 | u32 invalidate_domains, u32 flush_domains) |
252 | { | |
253 | u32 flags = 0; | |
18393f63 | 254 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
255 | int ret; |
256 | ||
b3111509 PZ |
257 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
258 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
259 | if (ret) | |
260 | return ret; | |
261 | ||
8d315287 JB |
262 | /* Just flush everything. Experiments have shown that reducing the |
263 | * number of bits based on the write domains has little performance | |
264 | * impact. | |
265 | */ | |
7d54a904 CW |
266 | if (flush_domains) { |
267 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
268 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
269 | /* | |
270 | * Ensure that any following seqno writes only happen | |
271 | * when the render cache is indeed flushed. | |
272 | */ | |
97f209bc | 273 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
274 | } |
275 | if (invalidate_domains) { | |
276 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
277 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
278 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
279 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
280 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
281 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
282 | /* | |
283 | * TLB invalidate requires a post-sync write. | |
284 | */ | |
3ac78313 | 285 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 286 | } |
8d315287 | 287 | |
6c6cf5aa | 288 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
289 | if (ret) |
290 | return ret; | |
291 | ||
6c6cf5aa | 292 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
293 | intel_ring_emit(ring, flags); |
294 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 295 | intel_ring_emit(ring, 0); |
8d315287 JB |
296 | intel_ring_advance(ring); |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
f3987631 | 301 | static int |
a4872ba6 | 302 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
303 | { |
304 | int ret; | |
305 | ||
306 | ret = intel_ring_begin(ring, 4); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
311 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
312 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
313 | intel_ring_emit(ring, 0); | |
314 | intel_ring_emit(ring, 0); | |
315 | intel_ring_advance(ring); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
a4872ba6 | 320 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
321 | { |
322 | int ret; | |
323 | ||
324 | if (!ring->fbc_dirty) | |
325 | return 0; | |
326 | ||
37c1d94f | 327 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
328 | if (ret) |
329 | return ret; | |
fd3da6c9 RV |
330 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
331 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
332 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
333 | intel_ring_emit(ring, value); | |
37c1d94f VS |
334 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
335 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
336 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
337 | intel_ring_advance(ring); |
338 | ||
339 | ring->fbc_dirty = false; | |
340 | return 0; | |
341 | } | |
342 | ||
4772eaeb | 343 | static int |
a4872ba6 | 344 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
345 | u32 invalidate_domains, u32 flush_domains) |
346 | { | |
347 | u32 flags = 0; | |
18393f63 | 348 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
349 | int ret; |
350 | ||
f3987631 PZ |
351 | /* |
352 | * Ensure that any following seqno writes only happen when the render | |
353 | * cache is indeed flushed. | |
354 | * | |
355 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
356 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
357 | * don't try to be clever and just set it unconditionally. | |
358 | */ | |
359 | flags |= PIPE_CONTROL_CS_STALL; | |
360 | ||
4772eaeb PZ |
361 | /* Just flush everything. Experiments have shown that reducing the |
362 | * number of bits based on the write domains has little performance | |
363 | * impact. | |
364 | */ | |
365 | if (flush_domains) { | |
366 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
367 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
368 | } |
369 | if (invalidate_domains) { | |
370 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
371 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
372 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
373 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
374 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
375 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
376 | /* | |
377 | * TLB invalidate requires a post-sync write. | |
378 | */ | |
379 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 380 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
381 | |
382 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
383 | * set before a pipe_control command that has the state cache | |
384 | * invalidate bit set. */ | |
385 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
386 | } |
387 | ||
388 | ret = intel_ring_begin(ring, 4); | |
389 | if (ret) | |
390 | return ret; | |
391 | ||
392 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
393 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 394 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
395 | intel_ring_emit(ring, 0); |
396 | intel_ring_advance(ring); | |
397 | ||
9688ecad | 398 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
399 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
400 | ||
4772eaeb PZ |
401 | return 0; |
402 | } | |
403 | ||
884ceace KG |
404 | static int |
405 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
406 | u32 flags, u32 scratch_addr) | |
407 | { | |
408 | int ret; | |
409 | ||
410 | ret = intel_ring_begin(ring, 6); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
414 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
415 | intel_ring_emit(ring, flags); | |
416 | intel_ring_emit(ring, scratch_addr); | |
417 | intel_ring_emit(ring, 0); | |
418 | intel_ring_emit(ring, 0); | |
419 | intel_ring_emit(ring, 0); | |
420 | intel_ring_advance(ring); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
a5f3d68e | 425 | static int |
a4872ba6 | 426 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
427 | u32 invalidate_domains, u32 flush_domains) |
428 | { | |
429 | u32 flags = 0; | |
18393f63 | 430 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 431 | int ret; |
a5f3d68e BW |
432 | |
433 | flags |= PIPE_CONTROL_CS_STALL; | |
434 | ||
435 | if (flush_domains) { | |
436 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
437 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
438 | } | |
439 | if (invalidate_domains) { | |
440 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
441 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
442 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
443 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
444 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
445 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
446 | flags |= PIPE_CONTROL_QW_WRITE; | |
447 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
448 | |
449 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
450 | ret = gen8_emit_pipe_control(ring, | |
451 | PIPE_CONTROL_CS_STALL | | |
452 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
453 | 0); | |
454 | if (ret) | |
455 | return ret; | |
a5f3d68e BW |
456 | } |
457 | ||
c5ad011d RV |
458 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
459 | if (ret) | |
460 | return ret; | |
461 | ||
462 | if (!invalidate_domains && flush_domains) | |
463 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
464 | ||
465 | return 0; | |
a5f3d68e BW |
466 | } |
467 | ||
a4872ba6 | 468 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 469 | u32 value) |
d46eefa2 | 470 | { |
4640c4ff | 471 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 472 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
473 | } |
474 | ||
a4872ba6 | 475 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 476 | { |
4640c4ff | 477 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 478 | u64 acthd; |
8187a2b7 | 479 | |
50877445 CW |
480 | if (INTEL_INFO(ring->dev)->gen >= 8) |
481 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
482 | RING_ACTHD_UDW(ring->mmio_base)); | |
483 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
484 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
485 | else | |
486 | acthd = I915_READ(ACTHD); | |
487 | ||
488 | return acthd; | |
8187a2b7 ZN |
489 | } |
490 | ||
a4872ba6 | 491 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
492 | { |
493 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
494 | u32 addr; | |
495 | ||
496 | addr = dev_priv->status_page_dmah->busaddr; | |
497 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
498 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
499 | I915_WRITE(HWS_PGA, addr); | |
500 | } | |
501 | ||
a4872ba6 | 502 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 503 | { |
9991ae78 | 504 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 505 | |
9991ae78 CW |
506 | if (!IS_GEN2(ring->dev)) { |
507 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
508 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
509 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
510 | /* Sometimes we observe that the idle flag is not |
511 | * set even though the ring is empty. So double | |
512 | * check before giving up. | |
513 | */ | |
514 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
515 | return false; | |
9991ae78 CW |
516 | } |
517 | } | |
b7884eb4 | 518 | |
7f2ab699 | 519 | I915_WRITE_CTL(ring, 0); |
570ef608 | 520 | I915_WRITE_HEAD(ring, 0); |
78501eac | 521 | ring->write_tail(ring, 0); |
8187a2b7 | 522 | |
9991ae78 CW |
523 | if (!IS_GEN2(ring->dev)) { |
524 | (void)I915_READ_CTL(ring); | |
525 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
526 | } | |
a51435a3 | 527 | |
9991ae78 CW |
528 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
529 | } | |
8187a2b7 | 530 | |
a4872ba6 | 531 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
532 | { |
533 | struct drm_device *dev = ring->dev; | |
534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
535 | struct intel_ringbuffer *ringbuf = ring->buffer; |
536 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
537 | int ret = 0; |
538 | ||
539 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
540 | ||
541 | if (!stop_ring(ring)) { | |
542 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
543 | DRM_DEBUG_KMS("%s head not reset to zero " |
544 | "ctl %08x head %08x tail %08x start %08x\n", | |
545 | ring->name, | |
546 | I915_READ_CTL(ring), | |
547 | I915_READ_HEAD(ring), | |
548 | I915_READ_TAIL(ring), | |
549 | I915_READ_START(ring)); | |
8187a2b7 | 550 | |
9991ae78 | 551 | if (!stop_ring(ring)) { |
6fd0d56e CW |
552 | DRM_ERROR("failed to set %s head to zero " |
553 | "ctl %08x head %08x tail %08x start %08x\n", | |
554 | ring->name, | |
555 | I915_READ_CTL(ring), | |
556 | I915_READ_HEAD(ring), | |
557 | I915_READ_TAIL(ring), | |
558 | I915_READ_START(ring)); | |
9991ae78 CW |
559 | ret = -EIO; |
560 | goto out; | |
6fd0d56e | 561 | } |
8187a2b7 ZN |
562 | } |
563 | ||
9991ae78 CW |
564 | if (I915_NEED_GFX_HWS(dev)) |
565 | intel_ring_setup_status_page(ring); | |
566 | else | |
567 | ring_setup_phys_status_page(ring); | |
568 | ||
ece4a17d JK |
569 | /* Enforce ordering by reading HEAD register back */ |
570 | I915_READ_HEAD(ring); | |
571 | ||
0d8957c8 DV |
572 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
573 | * registers with the above sequence (the readback of the HEAD registers | |
574 | * also enforces ordering), otherwise the hw might lose the new ring | |
575 | * register values. */ | |
f343c5f6 | 576 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
577 | |
578 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
579 | if (I915_READ_HEAD(ring)) | |
580 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", | |
581 | ring->name, I915_READ_HEAD(ring)); | |
582 | I915_WRITE_HEAD(ring, 0); | |
583 | (void)I915_READ_HEAD(ring); | |
584 | ||
7f2ab699 | 585 | I915_WRITE_CTL(ring, |
93b0a4e0 | 586 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 587 | | RING_VALID); |
8187a2b7 | 588 | |
8187a2b7 | 589 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 590 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 591 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 592 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 593 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
594 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
595 | ring->name, | |
596 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
597 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
598 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
599 | ret = -EIO; |
600 | goto out; | |
8187a2b7 ZN |
601 | } |
602 | ||
ebd0fd4b | 603 | ringbuf->last_retired_head = -1; |
5c6c6003 CW |
604 | ringbuf->head = I915_READ_HEAD(ring); |
605 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
ebd0fd4b | 606 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 607 | |
50f018df CW |
608 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
609 | ||
b7884eb4 | 610 | out: |
c8d9a590 | 611 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
612 | |
613 | return ret; | |
8187a2b7 ZN |
614 | } |
615 | ||
9b1136d5 OM |
616 | void |
617 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
618 | { | |
619 | struct drm_device *dev = ring->dev; | |
620 | ||
621 | if (ring->scratch.obj == NULL) | |
622 | return; | |
623 | ||
624 | if (INTEL_INFO(dev)->gen >= 5) { | |
625 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
626 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
627 | } | |
628 | ||
629 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
630 | ring->scratch.obj = NULL; | |
631 | } | |
632 | ||
633 | int | |
634 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 635 | { |
c6df541c CW |
636 | int ret; |
637 | ||
bfc882b4 | 638 | WARN_ON(ring->scratch.obj); |
c6df541c | 639 | |
0d1aacac CW |
640 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
641 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
642 | DRM_ERROR("Failed to allocate seqno page\n"); |
643 | ret = -ENOMEM; | |
644 | goto err; | |
645 | } | |
e4ffd173 | 646 | |
a9cc726c DV |
647 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
648 | if (ret) | |
649 | goto err_unref; | |
c6df541c | 650 | |
1ec9e26d | 651 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
652 | if (ret) |
653 | goto err_unref; | |
654 | ||
0d1aacac CW |
655 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
656 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
657 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 658 | ret = -ENOMEM; |
c6df541c | 659 | goto err_unpin; |
56b085a0 | 660 | } |
c6df541c | 661 | |
2b1086cc | 662 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 663 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
664 | return 0; |
665 | ||
666 | err_unpin: | |
d7f46fc4 | 667 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 668 | err_unref: |
0d1aacac | 669 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 670 | err: |
c6df541c CW |
671 | return ret; |
672 | } | |
673 | ||
771b9a53 MT |
674 | static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, |
675 | struct intel_context *ctx) | |
86d7f238 | 676 | { |
7225342a | 677 | int ret, i; |
888b5995 AS |
678 | struct drm_device *dev = ring->dev; |
679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7225342a | 680 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 681 | |
7225342a MK |
682 | if (WARN_ON(w->count == 0)) |
683 | return 0; | |
888b5995 | 684 | |
7225342a MK |
685 | ring->gpu_caches_dirty = true; |
686 | ret = intel_ring_flush_all_caches(ring); | |
687 | if (ret) | |
688 | return ret; | |
888b5995 | 689 | |
22a916aa | 690 | ret = intel_ring_begin(ring, (w->count * 2 + 2)); |
7225342a MK |
691 | if (ret) |
692 | return ret; | |
693 | ||
22a916aa | 694 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 695 | for (i = 0; i < w->count; i++) { |
7225342a MK |
696 | intel_ring_emit(ring, w->reg[i].addr); |
697 | intel_ring_emit(ring, w->reg[i].value); | |
698 | } | |
22a916aa | 699 | intel_ring_emit(ring, MI_NOOP); |
7225342a MK |
700 | |
701 | intel_ring_advance(ring); | |
702 | ||
703 | ring->gpu_caches_dirty = true; | |
704 | ret = intel_ring_flush_all_caches(ring); | |
705 | if (ret) | |
706 | return ret; | |
888b5995 | 707 | |
7225342a | 708 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 709 | |
7225342a | 710 | return 0; |
86d7f238 AS |
711 | } |
712 | ||
7225342a MK |
713 | static int wa_add(struct drm_i915_private *dev_priv, |
714 | const u32 addr, const u32 val, const u32 mask) | |
715 | { | |
716 | const u32 idx = dev_priv->workarounds.count; | |
717 | ||
718 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
719 | return -ENOSPC; | |
720 | ||
721 | dev_priv->workarounds.reg[idx].addr = addr; | |
722 | dev_priv->workarounds.reg[idx].value = val; | |
723 | dev_priv->workarounds.reg[idx].mask = mask; | |
724 | ||
725 | dev_priv->workarounds.count++; | |
726 | ||
727 | return 0; | |
86d7f238 AS |
728 | } |
729 | ||
7225342a MK |
730 | #define WA_REG(addr, val, mask) { \ |
731 | const int r = wa_add(dev_priv, (addr), (val), (mask)); \ | |
732 | if (r) \ | |
733 | return r; \ | |
734 | } | |
735 | ||
736 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
737 | WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff) | |
738 | ||
739 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
740 | WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff) | |
741 | ||
742 | #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask) | |
743 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask) | |
744 | ||
745 | #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff) | |
746 | ||
00e1e623 | 747 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
86d7f238 | 748 | { |
888b5995 AS |
749 | struct drm_device *dev = ring->dev; |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86d7f238 | 751 | |
86d7f238 | 752 | /* WaDisablePartialInstShootdown:bdw */ |
101b376d | 753 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
7225342a MK |
754 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
755 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | | |
756 | STALL_DOP_GATING_DISABLE); | |
86d7f238 | 757 | |
101b376d | 758 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
759 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
760 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 761 | |
7225342a MK |
762 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
763 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 AS |
764 | |
765 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
766 | * workaround for for a possible hang in the unlikely event a TLB | |
767 | * invalidation occurs during a PSD flush. | |
768 | */ | |
da09654d | 769 | /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ |
7225342a MK |
770 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
771 | HDC_FORCE_NON_COHERENT | | |
772 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); | |
86d7f238 AS |
773 | |
774 | /* Wa4x4STCOptimizationDisable:bdw */ | |
7225342a MK |
775 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
776 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
86d7f238 AS |
777 | |
778 | /* | |
779 | * BSpec recommends 8x4 when MSAA is used, | |
780 | * however in practice 16x4 seems fastest. | |
781 | * | |
782 | * Note that PS/WM thread counts depend on the WIZ hashing | |
783 | * disable bit, which we don't touch here, but it's good | |
784 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
785 | */ | |
7225342a MK |
786 | WA_SET_BIT_MASKED(GEN7_GT_MODE, |
787 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
888b5995 | 788 | |
86d7f238 AS |
789 | return 0; |
790 | } | |
791 | ||
00e1e623 VS |
792 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
793 | { | |
00e1e623 VS |
794 | struct drm_device *dev = ring->dev; |
795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
796 | ||
00e1e623 | 797 | /* WaDisablePartialInstShootdown:chv */ |
00e1e623 | 798 | /* WaDisableThreadStallDopClockGating:chv */ |
7225342a | 799 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
605f1433 AS |
800 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
801 | STALL_DOP_GATING_DISABLE); | |
00e1e623 | 802 | |
95289009 AS |
803 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
804 | * workaround for a possible hang in the unlikely event a TLB | |
805 | * invalidation occurs during a PSD flush. | |
806 | */ | |
807 | /* WaForceEnableNonCoherent:chv */ | |
808 | /* WaHdcDisableFetchWhenMasked:chv */ | |
809 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
810 | HDC_FORCE_NON_COHERENT | | |
811 | HDC_DONOT_FETCH_MEM_WHEN_MASKED); | |
812 | ||
7225342a MK |
813 | return 0; |
814 | } | |
815 | ||
771b9a53 | 816 | int init_workarounds_ring(struct intel_engine_cs *ring) |
7225342a MK |
817 | { |
818 | struct drm_device *dev = ring->dev; | |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | ||
821 | WARN_ON(ring->id != RCS); | |
822 | ||
823 | dev_priv->workarounds.count = 0; | |
824 | ||
825 | if (IS_BROADWELL(dev)) | |
826 | return bdw_init_workarounds(ring); | |
827 | ||
828 | if (IS_CHERRYVIEW(dev)) | |
829 | return chv_init_workarounds(ring); | |
00e1e623 VS |
830 | |
831 | return 0; | |
832 | } | |
833 | ||
a4872ba6 | 834 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 835 | { |
78501eac | 836 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 837 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 838 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
839 | if (ret) |
840 | return ret; | |
a69ffdbf | 841 | |
61a563a2 AG |
842 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
843 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 844 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
845 | |
846 | /* We need to disable the AsyncFlip performance optimisations in order | |
847 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
848 | * programmed to '1' on all products. | |
8693a824 | 849 | * |
b3f797ac | 850 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 | 851 | */ |
fbdcb068 | 852 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
1c8c38c5 CW |
853 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
854 | ||
f05bb0c7 | 855 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 856 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
857 | if (INTEL_INFO(dev)->gen == 6) |
858 | I915_WRITE(GFX_MODE, | |
aa83e30d | 859 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 860 | |
01fa0302 | 861 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
862 | if (IS_GEN7(dev)) |
863 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 864 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 865 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 866 | |
5e13a0c5 | 867 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
868 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
869 | * "If this bit is set, STCunit will have LRA as replacement | |
870 | * policy. [...] This bit must be reset. LRA replacement | |
871 | * policy is not supported." | |
872 | */ | |
873 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 874 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
875 | } |
876 | ||
6b26c86d DV |
877 | if (INTEL_INFO(dev)->gen >= 6) |
878 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 879 | |
040d2baa | 880 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 881 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 882 | |
7225342a | 883 | return init_workarounds_ring(ring); |
8187a2b7 ZN |
884 | } |
885 | ||
a4872ba6 | 886 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 887 | { |
b45305fc | 888 | struct drm_device *dev = ring->dev; |
3e78998a BW |
889 | struct drm_i915_private *dev_priv = dev->dev_private; |
890 | ||
891 | if (dev_priv->semaphore_obj) { | |
892 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
893 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
894 | dev_priv->semaphore_obj = NULL; | |
895 | } | |
b45305fc | 896 | |
9b1136d5 | 897 | intel_fini_pipe_control(ring); |
c6df541c CW |
898 | } |
899 | ||
3e78998a BW |
900 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
901 | unsigned int num_dwords) | |
902 | { | |
903 | #define MBOX_UPDATE_DWORDS 8 | |
904 | struct drm_device *dev = signaller->dev; | |
905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
906 | struct intel_engine_cs *waiter; | |
907 | int i, ret, num_rings; | |
908 | ||
909 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
910 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
911 | #undef MBOX_UPDATE_DWORDS | |
912 | ||
913 | ret = intel_ring_begin(signaller, num_dwords); | |
914 | if (ret) | |
915 | return ret; | |
916 | ||
917 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 918 | u32 seqno; |
3e78998a BW |
919 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
920 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
921 | continue; | |
922 | ||
6259cead JH |
923 | seqno = i915_gem_request_get_seqno( |
924 | signaller->outstanding_lazy_request); | |
3e78998a BW |
925 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
926 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
927 | PIPE_CONTROL_QW_WRITE | | |
928 | PIPE_CONTROL_FLUSH_ENABLE); | |
929 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
930 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 931 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
932 | intel_ring_emit(signaller, 0); |
933 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
934 | MI_SEMAPHORE_TARGET(waiter->id)); | |
935 | intel_ring_emit(signaller, 0); | |
936 | } | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
941 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
942 | unsigned int num_dwords) | |
943 | { | |
944 | #define MBOX_UPDATE_DWORDS 6 | |
945 | struct drm_device *dev = signaller->dev; | |
946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
947 | struct intel_engine_cs *waiter; | |
948 | int i, ret, num_rings; | |
949 | ||
950 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
951 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
952 | #undef MBOX_UPDATE_DWORDS | |
953 | ||
954 | ret = intel_ring_begin(signaller, num_dwords); | |
955 | if (ret) | |
956 | return ret; | |
957 | ||
958 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 959 | u32 seqno; |
3e78998a BW |
960 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
961 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
962 | continue; | |
963 | ||
6259cead JH |
964 | seqno = i915_gem_request_get_seqno( |
965 | signaller->outstanding_lazy_request); | |
3e78998a BW |
966 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
967 | MI_FLUSH_DW_OP_STOREDW); | |
968 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
969 | MI_FLUSH_DW_USE_GTT); | |
970 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 971 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
972 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
973 | MI_SEMAPHORE_TARGET(waiter->id)); | |
974 | intel_ring_emit(signaller, 0); | |
975 | } | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
a4872ba6 | 980 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 981 | unsigned int num_dwords) |
1ec14ad3 | 982 | { |
024a43e1 BW |
983 | struct drm_device *dev = signaller->dev; |
984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 985 | struct intel_engine_cs *useless; |
a1444b79 | 986 | int i, ret, num_rings; |
78325f2d | 987 | |
a1444b79 BW |
988 | #define MBOX_UPDATE_DWORDS 3 |
989 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
990 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
991 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
992 | |
993 | ret = intel_ring_begin(signaller, num_dwords); | |
994 | if (ret) | |
995 | return ret; | |
024a43e1 | 996 | |
78325f2d BW |
997 | for_each_ring(useless, dev_priv, i) { |
998 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
999 | if (mbox_reg != GEN6_NOSYNC) { | |
6259cead JH |
1000 | u32 seqno = i915_gem_request_get_seqno( |
1001 | signaller->outstanding_lazy_request); | |
78325f2d BW |
1002 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
1003 | intel_ring_emit(signaller, mbox_reg); | |
6259cead | 1004 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1005 | } |
1006 | } | |
024a43e1 | 1007 | |
a1444b79 BW |
1008 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1009 | if (num_rings % 2 == 0) | |
1010 | intel_ring_emit(signaller, MI_NOOP); | |
1011 | ||
024a43e1 | 1012 | return 0; |
1ec14ad3 CW |
1013 | } |
1014 | ||
c8c99b0f BW |
1015 | /** |
1016 | * gen6_add_request - Update the semaphore mailbox registers | |
1017 | * | |
1018 | * @ring - ring that is adding a request | |
1019 | * @seqno - return seqno stuck into the ring | |
1020 | * | |
1021 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1022 | * This acts like a signal in the canonical semaphore. | |
1023 | */ | |
1ec14ad3 | 1024 | static int |
a4872ba6 | 1025 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 1026 | { |
024a43e1 | 1027 | int ret; |
52ed2325 | 1028 | |
707d9cf9 BW |
1029 | if (ring->semaphore.signal) |
1030 | ret = ring->semaphore.signal(ring, 4); | |
1031 | else | |
1032 | ret = intel_ring_begin(ring, 4); | |
1033 | ||
1ec14ad3 CW |
1034 | if (ret) |
1035 | return ret; | |
1036 | ||
1ec14ad3 CW |
1037 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1038 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1039 | intel_ring_emit(ring, |
1040 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
1ec14ad3 | 1041 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1042 | __intel_ring_advance(ring); |
1ec14ad3 | 1043 | |
1ec14ad3 CW |
1044 | return 0; |
1045 | } | |
1046 | ||
f72b3435 MK |
1047 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1048 | u32 seqno) | |
1049 | { | |
1050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1051 | return dev_priv->last_seqno < seqno; | |
1052 | } | |
1053 | ||
c8c99b0f BW |
1054 | /** |
1055 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1056 | * | |
1057 | * @waiter - ring that is waiting | |
1058 | * @signaller - ring which has, or will signal | |
1059 | * @seqno - seqno which the waiter will block on | |
1060 | */ | |
5ee426ca BW |
1061 | |
1062 | static int | |
1063 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
1064 | struct intel_engine_cs *signaller, | |
1065 | u32 seqno) | |
1066 | { | |
1067 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
1068 | int ret; | |
1069 | ||
1070 | ret = intel_ring_begin(waiter, 4); | |
1071 | if (ret) | |
1072 | return ret; | |
1073 | ||
1074 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1075 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1076 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1077 | MI_SEMAPHORE_SAD_GTE_SDD); |
1078 | intel_ring_emit(waiter, seqno); | |
1079 | intel_ring_emit(waiter, | |
1080 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1081 | intel_ring_emit(waiter, | |
1082 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1083 | intel_ring_advance(waiter); | |
1084 | return 0; | |
1085 | } | |
1086 | ||
c8c99b0f | 1087 | static int |
a4872ba6 OM |
1088 | gen6_ring_sync(struct intel_engine_cs *waiter, |
1089 | struct intel_engine_cs *signaller, | |
686cb5f9 | 1090 | u32 seqno) |
1ec14ad3 | 1091 | { |
c8c99b0f BW |
1092 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1093 | MI_SEMAPHORE_COMPARE | | |
1094 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1095 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1096 | int ret; | |
1ec14ad3 | 1097 | |
1500f7ea BW |
1098 | /* Throughout all of the GEM code, seqno passed implies our current |
1099 | * seqno is >= the last seqno executed. However for hardware the | |
1100 | * comparison is strictly greater than. | |
1101 | */ | |
1102 | seqno -= 1; | |
1103 | ||
ebc348b2 | 1104 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1105 | |
c8c99b0f | 1106 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
1107 | if (ret) |
1108 | return ret; | |
1109 | ||
f72b3435 MK |
1110 | /* If seqno wrap happened, omit the wait with no-ops */ |
1111 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1112 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1113 | intel_ring_emit(waiter, seqno); |
1114 | intel_ring_emit(waiter, 0); | |
1115 | intel_ring_emit(waiter, MI_NOOP); | |
1116 | } else { | |
1117 | intel_ring_emit(waiter, MI_NOOP); | |
1118 | intel_ring_emit(waiter, MI_NOOP); | |
1119 | intel_ring_emit(waiter, MI_NOOP); | |
1120 | intel_ring_emit(waiter, MI_NOOP); | |
1121 | } | |
c8c99b0f | 1122 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1123 | |
1124 | return 0; | |
1125 | } | |
1126 | ||
c6df541c CW |
1127 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1128 | do { \ | |
fcbc34e4 KG |
1129 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1130 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1131 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1132 | intel_ring_emit(ring__, 0); \ | |
1133 | intel_ring_emit(ring__, 0); \ | |
1134 | } while (0) | |
1135 | ||
1136 | static int | |
a4872ba6 | 1137 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 1138 | { |
18393f63 | 1139 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1140 | int ret; |
1141 | ||
1142 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1143 | * incoherent with writes to memory, i.e. completely fubar, | |
1144 | * so we need to use PIPE_NOTIFY instead. | |
1145 | * | |
1146 | * However, we also need to workaround the qword write | |
1147 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1148 | * memory before requesting an interrupt. | |
1149 | */ | |
1150 | ret = intel_ring_begin(ring, 32); | |
1151 | if (ret) | |
1152 | return ret; | |
1153 | ||
fcbc34e4 | 1154 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1155 | PIPE_CONTROL_WRITE_FLUSH | |
1156 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 1157 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1158 | intel_ring_emit(ring, |
1159 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c CW |
1160 | intel_ring_emit(ring, 0); |
1161 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 1162 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 1163 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1164 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1165 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1166 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1167 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1168 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1169 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1170 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1171 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 1172 | |
fcbc34e4 | 1173 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1174 | PIPE_CONTROL_WRITE_FLUSH | |
1175 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1176 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 1177 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1178 | intel_ring_emit(ring, |
1179 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c | 1180 | intel_ring_emit(ring, 0); |
09246732 | 1181 | __intel_ring_advance(ring); |
c6df541c | 1182 | |
c6df541c CW |
1183 | return 0; |
1184 | } | |
1185 | ||
4cd53c0c | 1186 | static u32 |
a4872ba6 | 1187 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1188 | { |
4cd53c0c DV |
1189 | /* Workaround to force correct ordering between irq and seqno writes on |
1190 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1191 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1192 | if (!lazy_coherency) { |
1193 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1194 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1195 | } | |
1196 | ||
4cd53c0c DV |
1197 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1198 | } | |
1199 | ||
8187a2b7 | 1200 | static u32 |
a4872ba6 | 1201 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1202 | { |
1ec14ad3 CW |
1203 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1204 | } | |
1205 | ||
b70ec5bf | 1206 | static void |
a4872ba6 | 1207 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1208 | { |
1209 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1210 | } | |
1211 | ||
c6df541c | 1212 | static u32 |
a4872ba6 | 1213 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1214 | { |
0d1aacac | 1215 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1216 | } |
1217 | ||
b70ec5bf | 1218 | static void |
a4872ba6 | 1219 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1220 | { |
0d1aacac | 1221 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1222 | } |
1223 | ||
e48d8634 | 1224 | static bool |
a4872ba6 | 1225 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1226 | { |
1227 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1228 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1229 | unsigned long flags; |
e48d8634 | 1230 | |
7cd512f1 | 1231 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1232 | return false; |
1233 | ||
7338aefa | 1234 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1235 | if (ring->irq_refcount++ == 0) |
480c8033 | 1236 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1237 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1238 | |
1239 | return true; | |
1240 | } | |
1241 | ||
1242 | static void | |
a4872ba6 | 1243 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1244 | { |
1245 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1246 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1247 | unsigned long flags; |
e48d8634 | 1248 | |
7338aefa | 1249 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1250 | if (--ring->irq_refcount == 0) |
480c8033 | 1251 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1252 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1253 | } |
1254 | ||
b13c2b96 | 1255 | static bool |
a4872ba6 | 1256 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1257 | { |
78501eac | 1258 | struct drm_device *dev = ring->dev; |
4640c4ff | 1259 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1260 | unsigned long flags; |
62fdfeaf | 1261 | |
7cd512f1 | 1262 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1263 | return false; |
1264 | ||
7338aefa | 1265 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1266 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1267 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1268 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1269 | POSTING_READ(IMR); | |
1270 | } | |
7338aefa | 1271 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1272 | |
1273 | return true; | |
62fdfeaf EA |
1274 | } |
1275 | ||
8187a2b7 | 1276 | static void |
a4872ba6 | 1277 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1278 | { |
78501eac | 1279 | struct drm_device *dev = ring->dev; |
4640c4ff | 1280 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1281 | unsigned long flags; |
62fdfeaf | 1282 | |
7338aefa | 1283 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1284 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1285 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1286 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1287 | POSTING_READ(IMR); | |
1288 | } | |
7338aefa | 1289 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1290 | } |
1291 | ||
c2798b19 | 1292 | static bool |
a4872ba6 | 1293 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1294 | { |
1295 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1296 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1297 | unsigned long flags; |
c2798b19 | 1298 | |
7cd512f1 | 1299 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1300 | return false; |
1301 | ||
7338aefa | 1302 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1303 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1304 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1305 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1306 | POSTING_READ16(IMR); | |
1307 | } | |
7338aefa | 1308 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1309 | |
1310 | return true; | |
1311 | } | |
1312 | ||
1313 | static void | |
a4872ba6 | 1314 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1315 | { |
1316 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1317 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1318 | unsigned long flags; |
c2798b19 | 1319 | |
7338aefa | 1320 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1321 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1322 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1323 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1324 | POSTING_READ16(IMR); | |
1325 | } | |
7338aefa | 1326 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1327 | } |
1328 | ||
a4872ba6 | 1329 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1330 | { |
4593010b | 1331 | struct drm_device *dev = ring->dev; |
4640c4ff | 1332 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1333 | u32 mmio = 0; |
1334 | ||
1335 | /* The ring status page addresses are no longer next to the rest of | |
1336 | * the ring registers as of gen7. | |
1337 | */ | |
1338 | if (IS_GEN7(dev)) { | |
1339 | switch (ring->id) { | |
96154f2f | 1340 | case RCS: |
4593010b EA |
1341 | mmio = RENDER_HWS_PGA_GEN7; |
1342 | break; | |
96154f2f | 1343 | case BCS: |
4593010b EA |
1344 | mmio = BLT_HWS_PGA_GEN7; |
1345 | break; | |
77fe2ff3 ZY |
1346 | /* |
1347 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1348 | * gcc switch check warning | |
1349 | */ | |
1350 | case VCS2: | |
96154f2f | 1351 | case VCS: |
4593010b EA |
1352 | mmio = BSD_HWS_PGA_GEN7; |
1353 | break; | |
4a3dd19d | 1354 | case VECS: |
9a8a2213 BW |
1355 | mmio = VEBOX_HWS_PGA_GEN7; |
1356 | break; | |
4593010b EA |
1357 | } |
1358 | } else if (IS_GEN6(ring->dev)) { | |
1359 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1360 | } else { | |
eb0d4b75 | 1361 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1362 | mmio = RING_HWS_PGA(ring->mmio_base); |
1363 | } | |
1364 | ||
78501eac CW |
1365 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1366 | POSTING_READ(mmio); | |
884020bf | 1367 | |
dc616b89 DL |
1368 | /* |
1369 | * Flush the TLB for this page | |
1370 | * | |
1371 | * FIXME: These two bits have disappeared on gen8, so a question | |
1372 | * arises: do we still need this and if so how should we go about | |
1373 | * invalidating the TLB? | |
1374 | */ | |
1375 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1376 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1377 | |
1378 | /* ring should be idle before issuing a sync flush*/ | |
1379 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1380 | ||
884020bf CW |
1381 | I915_WRITE(reg, |
1382 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1383 | INSTPM_SYNC_FLUSH)); | |
1384 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1385 | 1000)) | |
1386 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1387 | ring->name); | |
1388 | } | |
8187a2b7 ZN |
1389 | } |
1390 | ||
b72f3acb | 1391 | static int |
a4872ba6 | 1392 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1393 | u32 invalidate_domains, |
1394 | u32 flush_domains) | |
d1b851fc | 1395 | { |
b72f3acb CW |
1396 | int ret; |
1397 | ||
b72f3acb CW |
1398 | ret = intel_ring_begin(ring, 2); |
1399 | if (ret) | |
1400 | return ret; | |
1401 | ||
1402 | intel_ring_emit(ring, MI_FLUSH); | |
1403 | intel_ring_emit(ring, MI_NOOP); | |
1404 | intel_ring_advance(ring); | |
1405 | return 0; | |
d1b851fc ZN |
1406 | } |
1407 | ||
3cce469c | 1408 | static int |
a4872ba6 | 1409 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1410 | { |
3cce469c CW |
1411 | int ret; |
1412 | ||
1413 | ret = intel_ring_begin(ring, 4); | |
1414 | if (ret) | |
1415 | return ret; | |
6f392d54 | 1416 | |
3cce469c CW |
1417 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1418 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1419 | intel_ring_emit(ring, |
1420 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
3cce469c | 1421 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1422 | __intel_ring_advance(ring); |
d1b851fc | 1423 | |
3cce469c | 1424 | return 0; |
d1b851fc ZN |
1425 | } |
1426 | ||
0f46832f | 1427 | static bool |
a4872ba6 | 1428 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1429 | { |
1430 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1431 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1432 | unsigned long flags; |
0f46832f | 1433 | |
7cd512f1 DV |
1434 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1435 | return false; | |
0f46832f | 1436 | |
7338aefa | 1437 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1438 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1439 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1440 | I915_WRITE_IMR(ring, |
1441 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1442 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1443 | else |
1444 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1445 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1446 | } |
7338aefa | 1447 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1448 | |
1449 | return true; | |
1450 | } | |
1451 | ||
1452 | static void | |
a4872ba6 | 1453 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1454 | { |
1455 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1456 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1457 | unsigned long flags; |
0f46832f | 1458 | |
7338aefa | 1459 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1460 | if (--ring->irq_refcount == 0) { |
040d2baa | 1461 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1462 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1463 | else |
1464 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1465 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1466 | } |
7338aefa | 1467 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1468 | } |
1469 | ||
a19d2933 | 1470 | static bool |
a4872ba6 | 1471 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1472 | { |
1473 | struct drm_device *dev = ring->dev; | |
1474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1475 | unsigned long flags; | |
1476 | ||
7cd512f1 | 1477 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1478 | return false; |
1479 | ||
59cdb63d | 1480 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1481 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1482 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1483 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1484 | } |
59cdb63d | 1485 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1486 | |
1487 | return true; | |
1488 | } | |
1489 | ||
1490 | static void | |
a4872ba6 | 1491 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1492 | { |
1493 | struct drm_device *dev = ring->dev; | |
1494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1495 | unsigned long flags; | |
1496 | ||
59cdb63d | 1497 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1498 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1499 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1500 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1501 | } |
59cdb63d | 1502 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1503 | } |
1504 | ||
abd58f01 | 1505 | static bool |
a4872ba6 | 1506 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1507 | { |
1508 | struct drm_device *dev = ring->dev; | |
1509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1510 | unsigned long flags; | |
1511 | ||
7cd512f1 | 1512 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1513 | return false; |
1514 | ||
1515 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1516 | if (ring->irq_refcount++ == 0) { | |
1517 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1518 | I915_WRITE_IMR(ring, | |
1519 | ~(ring->irq_enable_mask | | |
1520 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1521 | } else { | |
1522 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1523 | } | |
1524 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1525 | } | |
1526 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1527 | ||
1528 | return true; | |
1529 | } | |
1530 | ||
1531 | static void | |
a4872ba6 | 1532 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1533 | { |
1534 | struct drm_device *dev = ring->dev; | |
1535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1536 | unsigned long flags; | |
1537 | ||
1538 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1539 | if (--ring->irq_refcount == 0) { | |
1540 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1541 | I915_WRITE_IMR(ring, | |
1542 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1543 | } else { | |
1544 | I915_WRITE_IMR(ring, ~0); | |
1545 | } | |
1546 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1547 | } | |
1548 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1549 | } | |
1550 | ||
d1b851fc | 1551 | static int |
a4872ba6 | 1552 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1553 | u64 offset, u32 length, |
d7d4eedd | 1554 | unsigned flags) |
d1b851fc | 1555 | { |
e1f99ce6 | 1556 | int ret; |
78501eac | 1557 | |
e1f99ce6 CW |
1558 | ret = intel_ring_begin(ring, 2); |
1559 | if (ret) | |
1560 | return ret; | |
1561 | ||
78501eac | 1562 | intel_ring_emit(ring, |
65f56876 CW |
1563 | MI_BATCH_BUFFER_START | |
1564 | MI_BATCH_GTT | | |
d7d4eedd | 1565 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1566 | intel_ring_emit(ring, offset); |
78501eac CW |
1567 | intel_ring_advance(ring); |
1568 | ||
d1b851fc ZN |
1569 | return 0; |
1570 | } | |
1571 | ||
b45305fc DV |
1572 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1573 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1574 | #define I830_TLB_ENTRIES (2) |
1575 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1576 | static int |
a4872ba6 | 1577 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1578 | u64 offset, u32 len, |
d7d4eedd | 1579 | unsigned flags) |
62fdfeaf | 1580 | { |
c4d69da1 | 1581 | u32 cs_offset = ring->scratch.gtt_offset; |
c4e7a414 | 1582 | int ret; |
62fdfeaf | 1583 | |
c4d69da1 CW |
1584 | ret = intel_ring_begin(ring, 6); |
1585 | if (ret) | |
1586 | return ret; | |
62fdfeaf | 1587 | |
c4d69da1 CW |
1588 | /* Evict the invalid PTE TLBs */ |
1589 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); | |
1590 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1591 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1592 | intel_ring_emit(ring, cs_offset); | |
1593 | intel_ring_emit(ring, 0xdeadbeef); | |
1594 | intel_ring_emit(ring, MI_NOOP); | |
1595 | intel_ring_advance(ring); | |
b45305fc | 1596 | |
c4d69da1 | 1597 | if ((flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1598 | if (len > I830_BATCH_LIMIT) |
1599 | return -ENOSPC; | |
1600 | ||
c4d69da1 | 1601 | ret = intel_ring_begin(ring, 6 + 2); |
b45305fc DV |
1602 | if (ret) |
1603 | return ret; | |
c4d69da1 CW |
1604 | |
1605 | /* Blit the batch (which has now all relocs applied) to the | |
1606 | * stable batch scratch bo area (so that the CS never | |
1607 | * stumbles over its tlb invalidation bug) ... | |
1608 | */ | |
1609 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); | |
1610 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
611a7a4f | 1611 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
b45305fc | 1612 | intel_ring_emit(ring, cs_offset); |
b45305fc DV |
1613 | intel_ring_emit(ring, 4096); |
1614 | intel_ring_emit(ring, offset); | |
c4d69da1 | 1615 | |
b45305fc | 1616 | intel_ring_emit(ring, MI_FLUSH); |
c4d69da1 CW |
1617 | intel_ring_emit(ring, MI_NOOP); |
1618 | intel_ring_advance(ring); | |
b45305fc DV |
1619 | |
1620 | /* ... and execute it. */ | |
c4d69da1 | 1621 | offset = cs_offset; |
b45305fc | 1622 | } |
e1f99ce6 | 1623 | |
c4d69da1 CW |
1624 | ret = intel_ring_begin(ring, 4); |
1625 | if (ret) | |
1626 | return ret; | |
1627 | ||
1628 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1629 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1630 | intel_ring_emit(ring, offset + len - 8); | |
1631 | intel_ring_emit(ring, MI_NOOP); | |
1632 | intel_ring_advance(ring); | |
1633 | ||
fb3256da DV |
1634 | return 0; |
1635 | } | |
1636 | ||
1637 | static int | |
a4872ba6 | 1638 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1639 | u64 offset, u32 len, |
d7d4eedd | 1640 | unsigned flags) |
fb3256da DV |
1641 | { |
1642 | int ret; | |
1643 | ||
1644 | ret = intel_ring_begin(ring, 2); | |
1645 | if (ret) | |
1646 | return ret; | |
1647 | ||
65f56876 | 1648 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1649 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1650 | intel_ring_advance(ring); |
62fdfeaf | 1651 | |
62fdfeaf EA |
1652 | return 0; |
1653 | } | |
1654 | ||
a4872ba6 | 1655 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1656 | { |
05394f39 | 1657 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1658 | |
8187a2b7 ZN |
1659 | obj = ring->status_page.obj; |
1660 | if (obj == NULL) | |
62fdfeaf | 1661 | return; |
62fdfeaf | 1662 | |
9da3da66 | 1663 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1664 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1665 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1666 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1667 | } |
1668 | ||
a4872ba6 | 1669 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1670 | { |
05394f39 | 1671 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1672 | |
e3efda49 | 1673 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1674 | unsigned flags; |
e3efda49 | 1675 | int ret; |
e4ffd173 | 1676 | |
e3efda49 CW |
1677 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1678 | if (obj == NULL) { | |
1679 | DRM_ERROR("Failed to allocate status page\n"); | |
1680 | return -ENOMEM; | |
1681 | } | |
62fdfeaf | 1682 | |
e3efda49 CW |
1683 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1684 | if (ret) | |
1685 | goto err_unref; | |
1686 | ||
1f767e02 CW |
1687 | flags = 0; |
1688 | if (!HAS_LLC(ring->dev)) | |
1689 | /* On g33, we cannot place HWS above 256MiB, so | |
1690 | * restrict its pinning to the low mappable arena. | |
1691 | * Though this restriction is not documented for | |
1692 | * gen4, gen5, or byt, they also behave similarly | |
1693 | * and hang if the HWS is placed at the top of the | |
1694 | * GTT. To generalise, it appears that all !llc | |
1695 | * platforms have issues with us placing the HWS | |
1696 | * above the mappable region (even though we never | |
1697 | * actualy map it). | |
1698 | */ | |
1699 | flags |= PIN_MAPPABLE; | |
1700 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1701 | if (ret) { |
1702 | err_unref: | |
1703 | drm_gem_object_unreference(&obj->base); | |
1704 | return ret; | |
1705 | } | |
1706 | ||
1707 | ring->status_page.obj = obj; | |
1708 | } | |
62fdfeaf | 1709 | |
f343c5f6 | 1710 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1711 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1712 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1713 | |
8187a2b7 ZN |
1714 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1715 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1716 | |
1717 | return 0; | |
62fdfeaf EA |
1718 | } |
1719 | ||
a4872ba6 | 1720 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1721 | { |
1722 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1723 | |
1724 | if (!dev_priv->status_page_dmah) { | |
1725 | dev_priv->status_page_dmah = | |
1726 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1727 | if (!dev_priv->status_page_dmah) | |
1728 | return -ENOMEM; | |
1729 | } | |
1730 | ||
6b8294a4 CW |
1731 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1732 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | ||
7ba717cf | 1737 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 1738 | { |
2919d291 | 1739 | iounmap(ringbuf->virtual_start); |
7ba717cf | 1740 | ringbuf->virtual_start = NULL; |
2919d291 | 1741 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
1742 | } |
1743 | ||
1744 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
1745 | struct intel_ringbuffer *ringbuf) | |
1746 | { | |
1747 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1748 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
1749 | int ret; | |
1750 | ||
1751 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); | |
1752 | if (ret) | |
1753 | return ret; | |
1754 | ||
1755 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1756 | if (ret) { | |
1757 | i915_gem_object_ggtt_unpin(obj); | |
1758 | return ret; | |
1759 | } | |
1760 | ||
1761 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + | |
1762 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
1763 | if (ringbuf->virtual_start == NULL) { | |
1764 | i915_gem_object_ggtt_unpin(obj); | |
1765 | return -EINVAL; | |
1766 | } | |
1767 | ||
1768 | return 0; | |
1769 | } | |
1770 | ||
1771 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) | |
1772 | { | |
2919d291 OM |
1773 | drm_gem_object_unreference(&ringbuf->obj->base); |
1774 | ringbuf->obj = NULL; | |
1775 | } | |
1776 | ||
84c2377f OM |
1777 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1778 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1779 | { |
05394f39 | 1780 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1781 | |
ebc052e0 CW |
1782 | obj = NULL; |
1783 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1784 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1785 | if (obj == NULL) |
93b0a4e0 | 1786 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1787 | if (obj == NULL) |
1788 | return -ENOMEM; | |
8187a2b7 | 1789 | |
24f3a8cf AG |
1790 | /* mark ring buffers as read-only from GPU side by default */ |
1791 | obj->gt_ro = 1; | |
1792 | ||
93b0a4e0 | 1793 | ringbuf->obj = obj; |
e3efda49 | 1794 | |
7ba717cf | 1795 | return 0; |
e3efda49 CW |
1796 | } |
1797 | ||
1798 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1799 | struct intel_engine_cs *ring) |
e3efda49 | 1800 | { |
bfc882b4 | 1801 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
1802 | int ret; |
1803 | ||
bfc882b4 DV |
1804 | WARN_ON(ring->buffer); |
1805 | ||
1806 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1807 | if (!ringbuf) | |
1808 | return -ENOMEM; | |
1809 | ring->buffer = ringbuf; | |
8ee14975 | 1810 | |
e3efda49 CW |
1811 | ring->dev = dev; |
1812 | INIT_LIST_HEAD(&ring->active_list); | |
1813 | INIT_LIST_HEAD(&ring->request_list); | |
cc9130be | 1814 | INIT_LIST_HEAD(&ring->execlist_queue); |
93b0a4e0 | 1815 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1816 | ringbuf->ring = ring; |
ebc348b2 | 1817 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1818 | |
1819 | init_waitqueue_head(&ring->irq_queue); | |
1820 | ||
1821 | if (I915_NEED_GFX_HWS(dev)) { | |
1822 | ret = init_status_page(ring); | |
1823 | if (ret) | |
8ee14975 | 1824 | goto error; |
e3efda49 CW |
1825 | } else { |
1826 | BUG_ON(ring->id != RCS); | |
1827 | ret = init_phys_status_page(ring); | |
1828 | if (ret) | |
8ee14975 | 1829 | goto error; |
e3efda49 CW |
1830 | } |
1831 | ||
bfc882b4 | 1832 | WARN_ON(ringbuf->obj); |
7ba717cf | 1833 | |
bfc882b4 DV |
1834 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
1835 | if (ret) { | |
1836 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", | |
1837 | ring->name, ret); | |
1838 | goto error; | |
1839 | } | |
1840 | ||
1841 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
1842 | if (ret) { | |
1843 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
1844 | ring->name, ret); | |
1845 | intel_destroy_ringbuffer_obj(ringbuf); | |
1846 | goto error; | |
e3efda49 | 1847 | } |
62fdfeaf | 1848 | |
55249baa CW |
1849 | /* Workaround an erratum on the i830 which causes a hang if |
1850 | * the TAIL pointer points to within the last 2 cachelines | |
1851 | * of the buffer. | |
1852 | */ | |
93b0a4e0 | 1853 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1854 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1855 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1856 | |
44e895a8 BV |
1857 | ret = i915_cmd_parser_init_ring(ring); |
1858 | if (ret) | |
8ee14975 OM |
1859 | goto error; |
1860 | ||
8ee14975 | 1861 | return 0; |
351e3db2 | 1862 | |
8ee14975 OM |
1863 | error: |
1864 | kfree(ringbuf); | |
1865 | ring->buffer = NULL; | |
1866 | return ret; | |
62fdfeaf EA |
1867 | } |
1868 | ||
a4872ba6 | 1869 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1870 | { |
6402c330 JH |
1871 | struct drm_i915_private *dev_priv; |
1872 | struct intel_ringbuffer *ringbuf; | |
33626e6a | 1873 | |
93b0a4e0 | 1874 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1875 | return; |
1876 | ||
6402c330 JH |
1877 | dev_priv = to_i915(ring->dev); |
1878 | ringbuf = ring->buffer; | |
1879 | ||
e3efda49 | 1880 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1881 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1882 | |
7ba717cf | 1883 | intel_unpin_ringbuffer_obj(ringbuf); |
2919d291 | 1884 | intel_destroy_ringbuffer_obj(ringbuf); |
6259cead | 1885 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
78501eac | 1886 | |
8d19215b ZN |
1887 | if (ring->cleanup) |
1888 | ring->cleanup(ring); | |
1889 | ||
78501eac | 1890 | cleanup_status_page(ring); |
44e895a8 BV |
1891 | |
1892 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1893 | |
93b0a4e0 | 1894 | kfree(ringbuf); |
8ee14975 | 1895 | ring->buffer = NULL; |
62fdfeaf EA |
1896 | } |
1897 | ||
a4872ba6 | 1898 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1899 | { |
93b0a4e0 | 1900 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1901 | struct drm_i915_gem_request *request; |
a71d8d94 CW |
1902 | int ret; |
1903 | ||
ebd0fd4b DG |
1904 | if (intel_ring_space(ringbuf) >= n) |
1905 | return 0; | |
a71d8d94 CW |
1906 | |
1907 | list_for_each_entry(request, &ring->request_list, list) { | |
82e104cc OM |
1908 | if (__intel_ring_space(request->tail, ringbuf->tail, |
1909 | ringbuf->size) >= n) { | |
a71d8d94 CW |
1910 | break; |
1911 | } | |
a71d8d94 CW |
1912 | } |
1913 | ||
a4b3a571 | 1914 | if (&request->list == &ring->request_list) |
a71d8d94 CW |
1915 | return -ENOSPC; |
1916 | ||
a4b3a571 | 1917 | ret = i915_wait_request(request); |
a71d8d94 CW |
1918 | if (ret) |
1919 | return ret; | |
1920 | ||
1cf0ba14 | 1921 | i915_gem_retire_requests_ring(ring); |
a71d8d94 CW |
1922 | |
1923 | return 0; | |
1924 | } | |
1925 | ||
a4872ba6 | 1926 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1927 | { |
78501eac | 1928 | struct drm_device *dev = ring->dev; |
cae5852d | 1929 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1930 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1931 | unsigned long end; |
a71d8d94 | 1932 | int ret; |
c7dca47b | 1933 | |
a71d8d94 CW |
1934 | ret = intel_ring_wait_request(ring, n); |
1935 | if (ret != -ENOSPC) | |
1936 | return ret; | |
1937 | ||
09246732 CW |
1938 | /* force the tail write in case we have been skipping them */ |
1939 | __intel_ring_advance(ring); | |
1940 | ||
63ed2cb2 DV |
1941 | /* With GEM the hangcheck timer should kick us out of the loop, |
1942 | * leaving it early runs the risk of corrupting GEM state (due | |
1943 | * to running on almost untested codepaths). But on resume | |
1944 | * timers don't work yet, so prevent a complete hang in that | |
1945 | * case by choosing an insanely large timeout. */ | |
1946 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1947 | |
ebd0fd4b | 1948 | ret = 0; |
dcfe0506 | 1949 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1950 | do { |
ebd0fd4b DG |
1951 | if (intel_ring_space(ringbuf) >= n) |
1952 | break; | |
93b0a4e0 | 1953 | ringbuf->head = I915_READ_HEAD(ring); |
ebd0fd4b | 1954 | if (intel_ring_space(ringbuf) >= n) |
dcfe0506 | 1955 | break; |
62fdfeaf | 1956 | |
e60a0b10 | 1957 | msleep(1); |
d6b2c790 | 1958 | |
dcfe0506 CW |
1959 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1960 | ret = -ERESTARTSYS; | |
1961 | break; | |
1962 | } | |
1963 | ||
33196ded DV |
1964 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1965 | dev_priv->mm.interruptible); | |
d6b2c790 | 1966 | if (ret) |
dcfe0506 CW |
1967 | break; |
1968 | ||
1969 | if (time_after(jiffies, end)) { | |
1970 | ret = -EBUSY; | |
1971 | break; | |
1972 | } | |
1973 | } while (1); | |
db53a302 | 1974 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1975 | return ret; |
8187a2b7 | 1976 | } |
62fdfeaf | 1977 | |
a4872ba6 | 1978 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1979 | { |
1980 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1981 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1982 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1983 | |
93b0a4e0 | 1984 | if (ringbuf->space < rem) { |
3e960501 CW |
1985 | int ret = ring_wait_for_space(ring, rem); |
1986 | if (ret) | |
1987 | return ret; | |
1988 | } | |
1989 | ||
93b0a4e0 | 1990 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1991 | rem /= 4; |
1992 | while (rem--) | |
1993 | iowrite32(MI_NOOP, virt++); | |
1994 | ||
93b0a4e0 | 1995 | ringbuf->tail = 0; |
ebd0fd4b | 1996 | intel_ring_update_space(ringbuf); |
3e960501 CW |
1997 | |
1998 | return 0; | |
1999 | } | |
2000 | ||
a4872ba6 | 2001 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 | 2002 | { |
a4b3a571 | 2003 | struct drm_i915_gem_request *req; |
3e960501 CW |
2004 | int ret; |
2005 | ||
2006 | /* We need to add any requests required to flush the objects and ring */ | |
6259cead | 2007 | if (ring->outstanding_lazy_request) { |
9400ae5c | 2008 | ret = i915_add_request(ring); |
3e960501 CW |
2009 | if (ret) |
2010 | return ret; | |
2011 | } | |
2012 | ||
2013 | /* Wait upon the last request to be completed */ | |
2014 | if (list_empty(&ring->request_list)) | |
2015 | return 0; | |
2016 | ||
a4b3a571 | 2017 | req = list_entry(ring->request_list.prev, |
3e960501 | 2018 | struct drm_i915_gem_request, |
a4b3a571 | 2019 | list); |
3e960501 | 2020 | |
a4b3a571 | 2021 | return i915_wait_request(req); |
3e960501 CW |
2022 | } |
2023 | ||
9d773091 | 2024 | static int |
6259cead | 2025 | intel_ring_alloc_request(struct intel_engine_cs *ring) |
9d773091 | 2026 | { |
9eba5d4a JH |
2027 | int ret; |
2028 | struct drm_i915_gem_request *request; | |
2029 | ||
6259cead | 2030 | if (ring->outstanding_lazy_request) |
9d773091 | 2031 | return 0; |
3c0e234c | 2032 | |
9eba5d4a JH |
2033 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2034 | if (request == NULL) | |
2035 | return -ENOMEM; | |
3c0e234c | 2036 | |
abfe262a | 2037 | kref_init(&request->ref); |
ff79e857 | 2038 | request->ring = ring; |
abfe262a | 2039 | |
6259cead | 2040 | ret = i915_gem_get_seqno(ring->dev, &request->seqno); |
9eba5d4a JH |
2041 | if (ret) { |
2042 | kfree(request); | |
2043 | return ret; | |
3c0e234c CW |
2044 | } |
2045 | ||
6259cead | 2046 | ring->outstanding_lazy_request = request; |
9eba5d4a | 2047 | return 0; |
9d773091 CW |
2048 | } |
2049 | ||
a4872ba6 | 2050 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 2051 | int bytes) |
cbcc80df | 2052 | { |
93b0a4e0 | 2053 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
2054 | int ret; |
2055 | ||
93b0a4e0 | 2056 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
2057 | ret = intel_wrap_ring_buffer(ring); |
2058 | if (unlikely(ret)) | |
2059 | return ret; | |
2060 | } | |
2061 | ||
93b0a4e0 | 2062 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
2063 | ret = ring_wait_for_space(ring, bytes); |
2064 | if (unlikely(ret)) | |
2065 | return ret; | |
2066 | } | |
2067 | ||
cbcc80df MK |
2068 | return 0; |
2069 | } | |
2070 | ||
a4872ba6 | 2071 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 2072 | int num_dwords) |
8187a2b7 | 2073 | { |
4640c4ff | 2074 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 2075 | int ret; |
78501eac | 2076 | |
33196ded DV |
2077 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2078 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2079 | if (ret) |
2080 | return ret; | |
21dd3734 | 2081 | |
304d695c CW |
2082 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
2083 | if (ret) | |
2084 | return ret; | |
2085 | ||
9d773091 | 2086 | /* Preallocate the olr before touching the ring */ |
6259cead | 2087 | ret = intel_ring_alloc_request(ring); |
9d773091 CW |
2088 | if (ret) |
2089 | return ret; | |
2090 | ||
ee1b1e5e | 2091 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2092 | return 0; |
8187a2b7 | 2093 | } |
78501eac | 2094 | |
753b1ad4 | 2095 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 2096 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 2097 | { |
ee1b1e5e | 2098 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2099 | int ret; |
2100 | ||
2101 | if (num_dwords == 0) | |
2102 | return 0; | |
2103 | ||
18393f63 | 2104 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
2105 | ret = intel_ring_begin(ring, num_dwords); |
2106 | if (ret) | |
2107 | return ret; | |
2108 | ||
2109 | while (num_dwords--) | |
2110 | intel_ring_emit(ring, MI_NOOP); | |
2111 | ||
2112 | intel_ring_advance(ring); | |
2113 | ||
2114 | return 0; | |
2115 | } | |
2116 | ||
a4872ba6 | 2117 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 2118 | { |
3b2cc8ab OM |
2119 | struct drm_device *dev = ring->dev; |
2120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 2121 | |
6259cead | 2122 | BUG_ON(ring->outstanding_lazy_request); |
498d2ac1 | 2123 | |
3b2cc8ab | 2124 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
2125 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
2126 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 2127 | if (HAS_VEBOX(dev)) |
5020150b | 2128 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 2129 | } |
d97ed339 | 2130 | |
f7e98ad4 | 2131 | ring->set_seqno(ring, seqno); |
92cab734 | 2132 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 2133 | } |
62fdfeaf | 2134 | |
a4872ba6 | 2135 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 2136 | u32 value) |
881f47b6 | 2137 | { |
4640c4ff | 2138 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
2139 | |
2140 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2141 | |
2142 | /* Disable notification that the ring is IDLE. The GT | |
2143 | * will then assume that it is busy and bring it out of rc6. | |
2144 | */ | |
0206e353 | 2145 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2146 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2147 | ||
2148 | /* Clear the context id. Here be magic! */ | |
2149 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2150 | |
12f55818 | 2151 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2152 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2153 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2154 | 50)) | |
2155 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2156 | |
12f55818 | 2157 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 2158 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
2159 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
2160 | ||
2161 | /* Let the ring send IDLE messages to the GT again, | |
2162 | * and so let it sleep to conserve power when idle. | |
2163 | */ | |
0206e353 | 2164 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2165 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2166 | } |
2167 | ||
a4872ba6 | 2168 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2169 | u32 invalidate, u32 flush) |
881f47b6 | 2170 | { |
71a77e07 | 2171 | uint32_t cmd; |
b72f3acb CW |
2172 | int ret; |
2173 | ||
b72f3acb CW |
2174 | ret = intel_ring_begin(ring, 4); |
2175 | if (ret) | |
2176 | return ret; | |
2177 | ||
71a77e07 | 2178 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2179 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2180 | cmd += 1; | |
9a289771 JB |
2181 | /* |
2182 | * Bspec vol 1c.5 - video engine command streamer: | |
2183 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2184 | * operation is complete. This bit is only valid when the | |
2185 | * Post-Sync Operation field is a value of 1h or 3h." | |
2186 | */ | |
71a77e07 | 2187 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
2188 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
2189 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 2190 | intel_ring_emit(ring, cmd); |
9a289771 | 2191 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2192 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2193 | intel_ring_emit(ring, 0); /* upper addr */ | |
2194 | intel_ring_emit(ring, 0); /* value */ | |
2195 | } else { | |
2196 | intel_ring_emit(ring, 0); | |
2197 | intel_ring_emit(ring, MI_NOOP); | |
2198 | } | |
b72f3acb CW |
2199 | intel_ring_advance(ring); |
2200 | return 0; | |
881f47b6 XH |
2201 | } |
2202 | ||
1c7a0623 | 2203 | static int |
a4872ba6 | 2204 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2205 | u64 offset, u32 len, |
1c7a0623 BW |
2206 | unsigned flags) |
2207 | { | |
896ab1a5 | 2208 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2209 | int ret; |
2210 | ||
2211 | ret = intel_ring_begin(ring, 4); | |
2212 | if (ret) | |
2213 | return ret; | |
2214 | ||
2215 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2216 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2217 | intel_ring_emit(ring, lower_32_bits(offset)); |
2218 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2219 | intel_ring_emit(ring, MI_NOOP); |
2220 | intel_ring_advance(ring); | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
d7d4eedd | 2225 | static int |
a4872ba6 | 2226 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2227 | u64 offset, u32 len, |
d7d4eedd CW |
2228 | unsigned flags) |
2229 | { | |
2230 | int ret; | |
2231 | ||
2232 | ret = intel_ring_begin(ring, 2); | |
2233 | if (ret) | |
2234 | return ret; | |
2235 | ||
2236 | intel_ring_emit(ring, | |
77072258 CW |
2237 | MI_BATCH_BUFFER_START | |
2238 | (flags & I915_DISPATCH_SECURE ? | |
2239 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); | |
d7d4eedd CW |
2240 | /* bit0-7 is the length on GEN6+ */ |
2241 | intel_ring_emit(ring, offset); | |
2242 | intel_ring_advance(ring); | |
2243 | ||
2244 | return 0; | |
2245 | } | |
2246 | ||
881f47b6 | 2247 | static int |
a4872ba6 | 2248 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2249 | u64 offset, u32 len, |
d7d4eedd | 2250 | unsigned flags) |
881f47b6 | 2251 | { |
0206e353 | 2252 | int ret; |
ab6f8e32 | 2253 | |
0206e353 AJ |
2254 | ret = intel_ring_begin(ring, 2); |
2255 | if (ret) | |
2256 | return ret; | |
e1f99ce6 | 2257 | |
d7d4eedd CW |
2258 | intel_ring_emit(ring, |
2259 | MI_BATCH_BUFFER_START | | |
2260 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2261 | /* bit0-7 is the length on GEN6+ */ |
2262 | intel_ring_emit(ring, offset); | |
2263 | intel_ring_advance(ring); | |
ab6f8e32 | 2264 | |
0206e353 | 2265 | return 0; |
881f47b6 XH |
2266 | } |
2267 | ||
549f7365 CW |
2268 | /* Blitter support (SandyBridge+) */ |
2269 | ||
a4872ba6 | 2270 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2271 | u32 invalidate, u32 flush) |
8d19215b | 2272 | { |
fd3da6c9 | 2273 | struct drm_device *dev = ring->dev; |
1d73c2a8 | 2274 | struct drm_i915_private *dev_priv = dev->dev_private; |
71a77e07 | 2275 | uint32_t cmd; |
b72f3acb CW |
2276 | int ret; |
2277 | ||
6a233c78 | 2278 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2279 | if (ret) |
2280 | return ret; | |
2281 | ||
71a77e07 | 2282 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2283 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2284 | cmd += 1; | |
9a289771 JB |
2285 | /* |
2286 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2287 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2288 | * operation is complete. This bit is only valid when the | |
2289 | * Post-Sync Operation field is a value of 1h or 3h." | |
2290 | */ | |
71a77e07 | 2291 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2292 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2293 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2294 | intel_ring_emit(ring, cmd); |
9a289771 | 2295 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2296 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2297 | intel_ring_emit(ring, 0); /* upper addr */ | |
2298 | intel_ring_emit(ring, 0); /* value */ | |
2299 | } else { | |
2300 | intel_ring_emit(ring, 0); | |
2301 | intel_ring_emit(ring, MI_NOOP); | |
2302 | } | |
b72f3acb | 2303 | intel_ring_advance(ring); |
fd3da6c9 | 2304 | |
1d73c2a8 RV |
2305 | if (!invalidate && flush) { |
2306 | if (IS_GEN7(dev)) | |
2307 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
2308 | else if (IS_BROADWELL(dev)) | |
2309 | dev_priv->fbc.need_sw_cache_clean = true; | |
2310 | } | |
fd3da6c9 | 2311 | |
b72f3acb | 2312 | return 0; |
8d19215b ZN |
2313 | } |
2314 | ||
5c1143bb XH |
2315 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2316 | { | |
4640c4ff | 2317 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2318 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2319 | struct drm_i915_gem_object *obj; |
2320 | int ret; | |
5c1143bb | 2321 | |
59465b5f DV |
2322 | ring->name = "render ring"; |
2323 | ring->id = RCS; | |
2324 | ring->mmio_base = RENDER_RING_BASE; | |
2325 | ||
707d9cf9 | 2326 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2327 | if (i915_semaphore_is_enabled(dev)) { |
2328 | obj = i915_gem_alloc_object(dev, 4096); | |
2329 | if (obj == NULL) { | |
2330 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2331 | i915.semaphores = 0; | |
2332 | } else { | |
2333 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2334 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2335 | if (ret != 0) { | |
2336 | drm_gem_object_unreference(&obj->base); | |
2337 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2338 | i915.semaphores = 0; | |
2339 | } else | |
2340 | dev_priv->semaphore_obj = obj; | |
2341 | } | |
2342 | } | |
7225342a MK |
2343 | |
2344 | ring->init_context = intel_ring_workarounds_emit; | |
707d9cf9 BW |
2345 | ring->add_request = gen6_add_request; |
2346 | ring->flush = gen8_render_ring_flush; | |
2347 | ring->irq_get = gen8_ring_get_irq; | |
2348 | ring->irq_put = gen8_ring_put_irq; | |
2349 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2350 | ring->get_seqno = gen6_ring_get_seqno; | |
2351 | ring->set_seqno = ring_set_seqno; | |
2352 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2353 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2354 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2355 | ring->semaphore.signal = gen8_rcs_signal; |
2356 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2357 | } |
2358 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2359 | ring->add_request = gen6_add_request; |
4772eaeb | 2360 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2361 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2362 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2363 | ring->irq_get = gen6_ring_get_irq; |
2364 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2365 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2366 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2367 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2368 | if (i915_semaphore_is_enabled(dev)) { |
2369 | ring->semaphore.sync_to = gen6_ring_sync; | |
2370 | ring->semaphore.signal = gen6_signal; | |
2371 | /* | |
2372 | * The current semaphore is only applied on pre-gen8 | |
2373 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2374 | * platform. So the semaphore between RCS and VCS2 is | |
2375 | * initialized as INVALID. Gen8 will initialize the | |
2376 | * sema between VCS2 and RCS later. | |
2377 | */ | |
2378 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2379 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2380 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2381 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2382 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2383 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2384 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2385 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2386 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2387 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2388 | } | |
c6df541c CW |
2389 | } else if (IS_GEN5(dev)) { |
2390 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2391 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2392 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2393 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2394 | ring->irq_get = gen5_ring_get_irq; |
2395 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2396 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2397 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2398 | } else { |
8620a3a9 | 2399 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2400 | if (INTEL_INFO(dev)->gen < 4) |
2401 | ring->flush = gen2_render_ring_flush; | |
2402 | else | |
2403 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2404 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2405 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2406 | if (IS_GEN2(dev)) { |
2407 | ring->irq_get = i8xx_ring_get_irq; | |
2408 | ring->irq_put = i8xx_ring_put_irq; | |
2409 | } else { | |
2410 | ring->irq_get = i9xx_ring_get_irq; | |
2411 | ring->irq_put = i9xx_ring_put_irq; | |
2412 | } | |
e3670319 | 2413 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2414 | } |
59465b5f | 2415 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2416 | |
d7d4eedd CW |
2417 | if (IS_HASWELL(dev)) |
2418 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2419 | else if (IS_GEN8(dev)) |
2420 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2421 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2422 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2423 | else if (INTEL_INFO(dev)->gen >= 4) | |
2424 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2425 | else if (IS_I830(dev) || IS_845G(dev)) | |
2426 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2427 | else | |
2428 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
ecfe00d8 | 2429 | ring->init_hw = init_render_ring; |
59465b5f DV |
2430 | ring->cleanup = render_ring_cleanup; |
2431 | ||
b45305fc DV |
2432 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2433 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2434 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2435 | if (obj == NULL) { |
2436 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2437 | return -ENOMEM; | |
2438 | } | |
2439 | ||
be1fa129 | 2440 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2441 | if (ret != 0) { |
2442 | drm_gem_object_unreference(&obj->base); | |
2443 | DRM_ERROR("Failed to ping batch bo\n"); | |
2444 | return ret; | |
2445 | } | |
2446 | ||
0d1aacac CW |
2447 | ring->scratch.obj = obj; |
2448 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2449 | } |
2450 | ||
99be1dfe DV |
2451 | ret = intel_init_ring_buffer(dev, ring); |
2452 | if (ret) | |
2453 | return ret; | |
2454 | ||
2455 | if (INTEL_INFO(dev)->gen >= 5) { | |
2456 | ret = intel_init_pipe_control(ring); | |
2457 | if (ret) | |
2458 | return ret; | |
2459 | } | |
2460 | ||
2461 | return 0; | |
5c1143bb XH |
2462 | } |
2463 | ||
2464 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2465 | { | |
4640c4ff | 2466 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2467 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2468 | |
58fa3835 DV |
2469 | ring->name = "bsd ring"; |
2470 | ring->id = VCS; | |
2471 | ||
0fd2c201 | 2472 | ring->write_tail = ring_write_tail; |
780f18c8 | 2473 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2474 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2475 | /* gen6 bsd needs a special wa for tail updates */ |
2476 | if (IS_GEN6(dev)) | |
2477 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2478 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2479 | ring->add_request = gen6_add_request; |
2480 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2481 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2482 | if (INTEL_INFO(dev)->gen >= 8) { |
2483 | ring->irq_enable_mask = | |
2484 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2485 | ring->irq_get = gen8_ring_get_irq; | |
2486 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2487 | ring->dispatch_execbuffer = |
2488 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2489 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2490 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2491 | ring->semaphore.signal = gen8_xcs_signal; |
2492 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2493 | } |
abd58f01 BW |
2494 | } else { |
2495 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2496 | ring->irq_get = gen6_ring_get_irq; | |
2497 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2498 | ring->dispatch_execbuffer = |
2499 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2500 | if (i915_semaphore_is_enabled(dev)) { |
2501 | ring->semaphore.sync_to = gen6_ring_sync; | |
2502 | ring->semaphore.signal = gen6_signal; | |
2503 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2504 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2505 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2506 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2507 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2508 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2509 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2510 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2511 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2512 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2513 | } | |
abd58f01 | 2514 | } |
58fa3835 DV |
2515 | } else { |
2516 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2517 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2518 | ring->add_request = i9xx_add_request; |
58fa3835 | 2519 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2520 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2521 | if (IS_GEN5(dev)) { |
cc609d5d | 2522 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2523 | ring->irq_get = gen5_ring_get_irq; |
2524 | ring->irq_put = gen5_ring_put_irq; | |
2525 | } else { | |
e3670319 | 2526 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2527 | ring->irq_get = i9xx_ring_get_irq; |
2528 | ring->irq_put = i9xx_ring_put_irq; | |
2529 | } | |
fb3256da | 2530 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2531 | } |
ecfe00d8 | 2532 | ring->init_hw = init_ring_common; |
58fa3835 | 2533 | |
1ec14ad3 | 2534 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2535 | } |
549f7365 | 2536 | |
845f74a7 ZY |
2537 | /** |
2538 | * Initialize the second BSD ring for Broadwell GT3. | |
2539 | * It is noted that this only exists on Broadwell GT3. | |
2540 | */ | |
2541 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2542 | { | |
2543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2544 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2545 | |
2546 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2547 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2548 | return -EINVAL; | |
2549 | } | |
2550 | ||
f7b64236 | 2551 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2552 | ring->id = VCS2; |
2553 | ||
2554 | ring->write_tail = ring_write_tail; | |
2555 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2556 | ring->flush = gen6_bsd_ring_flush; | |
2557 | ring->add_request = gen6_add_request; | |
2558 | ring->get_seqno = gen6_ring_get_seqno; | |
2559 | ring->set_seqno = ring_set_seqno; | |
2560 | ring->irq_enable_mask = | |
2561 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2562 | ring->irq_get = gen8_ring_get_irq; | |
2563 | ring->irq_put = gen8_ring_put_irq; | |
2564 | ring->dispatch_execbuffer = | |
2565 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2566 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2567 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2568 | ring->semaphore.signal = gen8_xcs_signal; |
2569 | GEN8_RING_SEMAPHORE_INIT; | |
2570 | } | |
ecfe00d8 | 2571 | ring->init_hw = init_ring_common; |
845f74a7 ZY |
2572 | |
2573 | return intel_init_ring_buffer(dev, ring); | |
2574 | } | |
2575 | ||
549f7365 CW |
2576 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2577 | { | |
4640c4ff | 2578 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2579 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2580 | |
3535d9dd DV |
2581 | ring->name = "blitter ring"; |
2582 | ring->id = BCS; | |
2583 | ||
2584 | ring->mmio_base = BLT_RING_BASE; | |
2585 | ring->write_tail = ring_write_tail; | |
ea251324 | 2586 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2587 | ring->add_request = gen6_add_request; |
2588 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2589 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2590 | if (INTEL_INFO(dev)->gen >= 8) { |
2591 | ring->irq_enable_mask = | |
2592 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2593 | ring->irq_get = gen8_ring_get_irq; | |
2594 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2595 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2596 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2597 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2598 | ring->semaphore.signal = gen8_xcs_signal; |
2599 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2600 | } |
abd58f01 BW |
2601 | } else { |
2602 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2603 | ring->irq_get = gen6_ring_get_irq; | |
2604 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2605 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2606 | if (i915_semaphore_is_enabled(dev)) { |
2607 | ring->semaphore.signal = gen6_signal; | |
2608 | ring->semaphore.sync_to = gen6_ring_sync; | |
2609 | /* | |
2610 | * The current semaphore is only applied on pre-gen8 | |
2611 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2612 | * platform. So the semaphore between BCS and VCS2 is | |
2613 | * initialized as INVALID. Gen8 will initialize the | |
2614 | * sema between BCS and VCS2 later. | |
2615 | */ | |
2616 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2617 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2618 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2619 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2620 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2621 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2622 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2623 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2624 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2625 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2626 | } | |
abd58f01 | 2627 | } |
ecfe00d8 | 2628 | ring->init_hw = init_ring_common; |
549f7365 | 2629 | |
1ec14ad3 | 2630 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2631 | } |
a7b9761d | 2632 | |
9a8a2213 BW |
2633 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2634 | { | |
4640c4ff | 2635 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2636 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2637 | |
2638 | ring->name = "video enhancement ring"; | |
2639 | ring->id = VECS; | |
2640 | ||
2641 | ring->mmio_base = VEBOX_RING_BASE; | |
2642 | ring->write_tail = ring_write_tail; | |
2643 | ring->flush = gen6_ring_flush; | |
2644 | ring->add_request = gen6_add_request; | |
2645 | ring->get_seqno = gen6_ring_get_seqno; | |
2646 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2647 | |
2648 | if (INTEL_INFO(dev)->gen >= 8) { | |
2649 | ring->irq_enable_mask = | |
40c499f9 | 2650 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2651 | ring->irq_get = gen8_ring_get_irq; |
2652 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2653 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2654 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2655 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2656 | ring->semaphore.signal = gen8_xcs_signal; |
2657 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2658 | } |
abd58f01 BW |
2659 | } else { |
2660 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2661 | ring->irq_get = hsw_vebox_get_irq; | |
2662 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2663 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2664 | if (i915_semaphore_is_enabled(dev)) { |
2665 | ring->semaphore.sync_to = gen6_ring_sync; | |
2666 | ring->semaphore.signal = gen6_signal; | |
2667 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2668 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2669 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2670 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2671 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2672 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2673 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2674 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2675 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2676 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2677 | } | |
abd58f01 | 2678 | } |
ecfe00d8 | 2679 | ring->init_hw = init_ring_common; |
9a8a2213 BW |
2680 | |
2681 | return intel_init_ring_buffer(dev, ring); | |
2682 | } | |
2683 | ||
a7b9761d | 2684 | int |
a4872ba6 | 2685 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2686 | { |
2687 | int ret; | |
2688 | ||
2689 | if (!ring->gpu_caches_dirty) | |
2690 | return 0; | |
2691 | ||
2692 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2693 | if (ret) | |
2694 | return ret; | |
2695 | ||
2696 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2697 | ||
2698 | ring->gpu_caches_dirty = false; | |
2699 | return 0; | |
2700 | } | |
2701 | ||
2702 | int | |
a4872ba6 | 2703 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2704 | { |
2705 | uint32_t flush_domains; | |
2706 | int ret; | |
2707 | ||
2708 | flush_domains = 0; | |
2709 | if (ring->gpu_caches_dirty) | |
2710 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2711 | ||
2712 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2713 | if (ret) | |
2714 | return ret; | |
2715 | ||
2716 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2717 | ||
2718 | ring->gpu_caches_dirty = false; | |
2719 | return 0; | |
2720 | } | |
e3efda49 CW |
2721 | |
2722 | void | |
a4872ba6 | 2723 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2724 | { |
2725 | int ret; | |
2726 | ||
2727 | if (!intel_ring_initialized(ring)) | |
2728 | return; | |
2729 | ||
2730 | ret = intel_ring_idle(ring); | |
2731 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2732 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2733 | ring->name, ret); | |
2734 | ||
2735 | stop_ring(ring); | |
2736 | } |