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drm/i915: Enable the HiZ RAW Stall Optimization on Broadwell.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 382
add284a3
CW		 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
f3987631
PZ		 385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
b9e1faa7 397 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
9688ecad 401 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
4772eaeb
PZ		 404 return 0;
405}
406
884ceace
KG		 407static int
408gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410{
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426}
427
a5f3d68e 428static int
a4872ba6 429gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 430 u32 invalidate_domains, u32 flush_domains)
431{
432 u32 flags = 0;
18393f63 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 434 int ret;
a5f3d68e
BW		 435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
a5f3d68e
BW		 459 }
460
c5ad011d
RV		 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
a5f3d68e
BW		 469}
470
a4872ba6 471static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 472 u32 value)
d46eefa2 473{
4640c4ff 474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 475 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 476}
477
a4872ba6 478u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 479{
4640c4ff 480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 481 u64 acthd;
8187a2b7 482
50877445
CW		 483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
8187a2b7
ZN		 492}
493
a4872ba6 494static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503}
504
a4872ba6 505static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 506{
9991ae78 507 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 508
9991ae78
CW		 509 if (!IS_GEN2(ring->dev)) {
510 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 511 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
512 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 513 /* Sometimes we observe that the idle flag is not
514 * set even though the ring is empty. So double
515 * check before giving up.
516 */
517 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
518 return false;
9991ae78
CW		 519 }
520 }
b7884eb4 521
7f2ab699 522 I915_WRITE_CTL(ring, 0);
570ef608 523 I915_WRITE_HEAD(ring, 0);
78501eac 524 ring->write_tail(ring, 0);
8187a2b7 525
9991ae78
CW		 526 if (!IS_GEN2(ring->dev)) {
527 (void)I915_READ_CTL(ring);
528 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
529 }
a51435a3 530
9991ae78
CW		 531 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
532}
8187a2b7 533
a4872ba6 534static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 535{
536 struct drm_device *dev = ring->dev;
537 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 538 struct intel_ringbuffer *ringbuf = ring->buffer;
539 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 540 int ret = 0;
541
542 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
543
544 if (!stop_ring(ring)) {
545 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 546 DRM_DEBUG_KMS("%s head not reset to zero "
547 "ctl %08x head %08x tail %08x start %08x\n",
548 ring->name,
549 I915_READ_CTL(ring),
550 I915_READ_HEAD(ring),
551 I915_READ_TAIL(ring),
552 I915_READ_START(ring));
8187a2b7 553
9991ae78 554 if (!stop_ring(ring)) {
6fd0d56e
CW		 555 DRM_ERROR("failed to set %s head to zero "
556 "ctl %08x head %08x tail %08x start %08x\n",
557 ring->name,
558 I915_READ_CTL(ring),
559 I915_READ_HEAD(ring),
560 I915_READ_TAIL(ring),
561 I915_READ_START(ring));
9991ae78
CW		 562 ret = -EIO;
563 goto out;
6fd0d56e 564 }
8187a2b7
ZN		 565 }
566
9991ae78
CW		 567 if (I915_NEED_GFX_HWS(dev))
568 intel_ring_setup_status_page(ring);
569 else
570 ring_setup_phys_status_page(ring);
571
ece4a17d
JK		 572 /* Enforce ordering by reading HEAD register back */
573 I915_READ_HEAD(ring);
574
0d8957c8
DV		 575 /* Initialize the ring. This must happen _after_ we've cleared the ring
576 * registers with the above sequence (the readback of the HEAD registers
577 * also enforces ordering), otherwise the hw might lose the new ring
578 * register values. */
f343c5f6 579 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 580
581 /* WaClearRingBufHeadRegAtInit:ctg,elk */
582 if (I915_READ_HEAD(ring))
583 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
584 ring->name, I915_READ_HEAD(ring));
585 I915_WRITE_HEAD(ring, 0);
586 (void)I915_READ_HEAD(ring);
587
7f2ab699 588 I915_WRITE_CTL(ring,
93b0a4e0 589 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 590 | RING_VALID);
8187a2b7 591
8187a2b7 592 /* If the head is still not zero, the ring is dead */
f01db988 593 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 594 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 595 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 596 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 597 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
598 ring->name,
599 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
600 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
601 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 602 ret = -EIO;
603 goto out;
8187a2b7
ZN		 604 }
605
ebd0fd4b 606 ringbuf->last_retired_head = -1;
5c6c6003
CW		 607 ringbuf->head = I915_READ_HEAD(ring);
608 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 609 intel_ring_update_space(ringbuf);
1ec14ad3 610
50f018df
CW		 611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
612
b7884eb4 613out:
c8d9a590 614 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 615
616 return ret;
8187a2b7
ZN		 617}
618
9b1136d5
OM		 619void
620intel_fini_pipe_control(struct intel_engine_cs *ring)
621{
622 struct drm_device *dev = ring->dev;
623
624 if (ring->scratch.obj == NULL)
625 return;
626
627 if (INTEL_INFO(dev)->gen >= 5) {
628 kunmap(sg_page(ring->scratch.obj->pages->sgl));
629 i915_gem_object_ggtt_unpin(ring->scratch.obj);
630 }
631
632 drm_gem_object_unreference(&ring->scratch.obj->base);
633 ring->scratch.obj = NULL;
634}
635
636int
637intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 638{
c6df541c
CW		 639 int ret;
640
bfc882b4 641 WARN_ON(ring->scratch.obj);
c6df541c 642
0d1aacac
CW		 643 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
644 if (ring->scratch.obj == NULL) {
c6df541c
CW		 645 DRM_ERROR("Failed to allocate seqno page\n");
646 ret = -ENOMEM;
647 goto err;
648 }
e4ffd173 649
a9cc726c
DV		 650 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
651 if (ret)
652 goto err_unref;
c6df541c 653
1ec9e26d 654 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 655 if (ret)
656 goto err_unref;
657
0d1aacac
CW		 658 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
659 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
660 if (ring->scratch.cpu_page == NULL) {
56b085a0 661 ret = -ENOMEM;
c6df541c 662 goto err_unpin;
56b085a0 663 }
c6df541c 664
2b1086cc 665 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 666 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 667 return 0;
668
669err_unpin:
d7f46fc4 670 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 671err_unref:
0d1aacac 672 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 673err:
c6df541c
CW		 674 return ret;
675}
676
771b9a53
MT		 677static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
678 struct intel_context *ctx)
86d7f238 679{
7225342a 680 int ret, i;
888b5995
AS		 681 struct drm_device *dev = ring->dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 683 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 684
e6c1abb7 685 if (WARN_ON_ONCE(w->count == 0))
7225342a 686 return 0;
888b5995 687
7225342a
MK		 688 ring->gpu_caches_dirty = true;
689 ret = intel_ring_flush_all_caches(ring);
690 if (ret)
691 return ret;
888b5995 692
22a916aa 693 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 694 if (ret)
695 return ret;
696
22a916aa 697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 698 for (i = 0; i < w->count; i++) {
7225342a
MK		 699 intel_ring_emit(ring, w->reg[i].addr);
700 intel_ring_emit(ring, w->reg[i].value);
701 }
22a916aa 702 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 703
704 intel_ring_advance(ring);
705
706 ring->gpu_caches_dirty = true;
707 ret = intel_ring_flush_all_caches(ring);
708 if (ret)
709 return ret;
888b5995 710
7225342a 711 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 712
7225342a 713 return 0;
86d7f238
AS		 714}
715
8f0e2b9d
DV		 716static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
717 struct intel_context *ctx)
718{
719 int ret;
720
721 ret = intel_ring_workarounds_emit(ring, ctx);
722 if (ret != 0)
723 return ret;
724
725 ret = i915_gem_render_state_init(ring);
726 if (ret)
727 DRM_ERROR("init render state: %d\n", ret);
728
729 return ret;
730}
731
7225342a 732static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 733 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 734{
735 const u32 idx = dev_priv->workarounds.count;
736
737 if (WARN_ON(idx >= I915_MAX_WA_REGS))
738 return -ENOSPC;
739
740 dev_priv->workarounds.reg[idx].addr = addr;
741 dev_priv->workarounds.reg[idx].value = val;
742 dev_priv->workarounds.reg[idx].mask = mask;
743
744 dev_priv->workarounds.count++;
745
746 return 0;
86d7f238
AS		 747}
748
cf4b0de6
DL		 749#define WA_REG(addr, mask, val) { \
750 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 751 if (r) \
752 return r; \
753 }
754
755#define WA_SET_BIT_MASKED(addr, mask) \
26459343 756 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 757
758#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 759 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 760
98533251 761#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 762 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 763
cf4b0de6
DL		 764#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
765#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 766
cf4b0de6 767#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 768
00e1e623 769static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 770{
888b5995
AS		 771 struct drm_device *dev = ring->dev;
772 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 773
86d7f238 774 /* WaDisablePartialInstShootdown:bdw */
101b376d 775 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 776 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
777 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
778 STALL_DOP_GATING_DISABLE);
86d7f238 779
101b376d 780 /* WaDisableDopClockGating:bdw */
7225342a
MK		 781 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
782 DOP_CLOCK_GATING_DISABLE);
86d7f238 783
7225342a
MK		 784 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
785 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 786
787 /* Use Force Non-Coherent whenever executing a 3D context. This is a
788 * workaround for for a possible hang in the unlikely event a TLB
789 * invalidation occurs during a PSD flush.
790 */
1a252058 791 /* WaForceEnableNonCoherent:bdw */
f3f32360 792 /* WaHdcDisableFetchWhenMasked:bdw */
da09654d 793 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
7225342a
MK		 794 WA_SET_BIT_MASKED(HDC_CHICKEN0,
795 HDC_FORCE_NON_COHERENT |
f3f32360 796 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
7225342a 797 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 798
2701fc43
KG		 799 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
800 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
801 * polygons in the same 8x4 pixel/sample area to be processed without
802 * stalling waiting for the earlier ones to write to Hierarchical Z
803 * buffer."
804 *
805 * This optimization is off by default for Broadwell; turn it on.
806 */
807 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
808
86d7f238 809 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 810 WA_SET_BIT_MASKED(CACHE_MODE_1,
811 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 812
813 /*
814 * BSpec recommends 8x4 when MSAA is used,
815 * however in practice 16x4 seems fastest.
816 *
817 * Note that PS/WM thread counts depend on the WIZ hashing
818 * disable bit, which we don't touch here, but it's good
819 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
820 */
98533251
DL		 821 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
822 GEN6_WIZ_HASHING_MASK,
823 GEN6_WIZ_HASHING_16x4);
888b5995 824
86d7f238
AS		 825 return 0;
826}
827
00e1e623
VS		 828static int chv_init_workarounds(struct intel_engine_cs *ring)
829{
00e1e623
VS		 830 struct drm_device *dev = ring->dev;
831 struct drm_i915_private *dev_priv = dev->dev_private;
832
00e1e623 833 /* WaDisablePartialInstShootdown:chv */
00e1e623 834 /* WaDisableThreadStallDopClockGating:chv */
7225342a 835 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 836 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
837 STALL_DOP_GATING_DISABLE);
00e1e623 838
95289009
AS		 839 /* Use Force Non-Coherent whenever executing a 3D context. This is a
840 * workaround for a possible hang in the unlikely event a TLB
841 * invalidation occurs during a PSD flush.
842 */
843 /* WaForceEnableNonCoherent:chv */
844 /* WaHdcDisableFetchWhenMasked:chv */
845 WA_SET_BIT_MASKED(HDC_CHICKEN0,
846 HDC_FORCE_NON_COHERENT |
847 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
848
d60de81d
KG		 849 /* Improve HiZ throughput on CHV. */
850 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
851
7225342a
MK		 852 return 0;
853}
854
771b9a53 855int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 856{
857 struct drm_device *dev = ring->dev;
858 struct drm_i915_private *dev_priv = dev->dev_private;
859
860 WARN_ON(ring->id != RCS);
861
862 dev_priv->workarounds.count = 0;
863
864 if (IS_BROADWELL(dev))
865 return bdw_init_workarounds(ring);
866
867 if (IS_CHERRYVIEW(dev))
868 return chv_init_workarounds(ring);
00e1e623
VS		 869
870 return 0;
871}
872
a4872ba6 873static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 874{
78501eac 875 struct drm_device *dev = ring->dev;
1ec14ad3 876 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 877 int ret = init_ring_common(ring);
9c33baa6
KZ		 878 if (ret)
879 return ret;
a69ffdbf 880
61a563a2
AG		 881 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
882 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 883 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 884
885 /* We need to disable the AsyncFlip performance optimisations in order
886 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
887 * programmed to '1' on all products.
8693a824 888 *
b3f797ac 889 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 890 */
fbdcb068 891 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 892 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
893
f05bb0c7 894 /* Required for the hardware to program scanline values for waiting */
01fa0302 895 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 896 if (INTEL_INFO(dev)->gen == 6)
897 I915_WRITE(GFX_MODE,
aa83e30d 898 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 899
01fa0302 900 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 901 if (IS_GEN7(dev))
902 I915_WRITE(GFX_MODE_GEN7,
01fa0302 903 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 904 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 905
5e13a0c5 906 if (IS_GEN6(dev)) {
3a69ddd6
KG		 907 /* From the Sandybridge PRM, volume 1 part 3, page 24:
908 * "If this bit is set, STCunit will have LRA as replacement
909 * policy. [...] This bit must be reset. LRA replacement
910 * policy is not supported."
911 */
912 I915_WRITE(CACHE_MODE_0,
5e13a0c5 913 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 914 }
915
6b26c86d
DV		 916 if (INTEL_INFO(dev)->gen >= 6)
917 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 918
040d2baa 919 if (HAS_L3_DPF(dev))
35a85ac6 920 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 921
7225342a 922 return init_workarounds_ring(ring);
8187a2b7
ZN		 923}
924
a4872ba6 925static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 926{
b45305fc 927 struct drm_device *dev = ring->dev;
3e78998a
BW		 928 struct drm_i915_private *dev_priv = dev->dev_private;
929
930 if (dev_priv->semaphore_obj) {
931 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
932 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
933 dev_priv->semaphore_obj = NULL;
934 }
b45305fc 935
9b1136d5 936 intel_fini_pipe_control(ring);
c6df541c
CW		 937}
938
3e78998a
BW		 939static int gen8_rcs_signal(struct intel_engine_cs *signaller,
940 unsigned int num_dwords)
941{
942#define MBOX_UPDATE_DWORDS 8
943 struct drm_device *dev = signaller->dev;
944 struct drm_i915_private *dev_priv = dev->dev_private;
945 struct intel_engine_cs *waiter;
946 int i, ret, num_rings;
947
948 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
949 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
950#undef MBOX_UPDATE_DWORDS
951
952 ret = intel_ring_begin(signaller, num_dwords);
953 if (ret)
954 return ret;
955
956 for_each_ring(waiter, dev_priv, i) {
6259cead 957 u32 seqno;
3e78998a
BW		 958 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
959 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
960 continue;
961
6259cead
JH		 962 seqno = i915_gem_request_get_seqno(
963 signaller->outstanding_lazy_request);
3e78998a
BW		 964 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
965 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
966 PIPE_CONTROL_QW_WRITE |
967 PIPE_CONTROL_FLUSH_ENABLE);
968 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
969 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 970 intel_ring_emit(signaller, seqno);
3e78998a
BW		 971 intel_ring_emit(signaller, 0);
972 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
973 MI_SEMAPHORE_TARGET(waiter->id));
974 intel_ring_emit(signaller, 0);
975 }
976
977 return 0;
978}
979
980static int gen8_xcs_signal(struct intel_engine_cs *signaller,
981 unsigned int num_dwords)
982{
983#define MBOX_UPDATE_DWORDS 6
984 struct drm_device *dev = signaller->dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 struct intel_engine_cs *waiter;
987 int i, ret, num_rings;
988
989 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
990 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
991#undef MBOX_UPDATE_DWORDS
992
993 ret = intel_ring_begin(signaller, num_dwords);
994 if (ret)
995 return ret;
996
997 for_each_ring(waiter, dev_priv, i) {
6259cead 998 u32 seqno;
3e78998a
BW		 999 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1000 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1001 continue;
1002
6259cead
JH		 1003 seqno = i915_gem_request_get_seqno(
1004 signaller->outstanding_lazy_request);
3e78998a
BW		 1005 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1006 MI_FLUSH_DW_OP_STOREDW);
1007 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1008 MI_FLUSH_DW_USE_GTT);
1009 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1010 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1011 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1012 MI_SEMAPHORE_TARGET(waiter->id));
1013 intel_ring_emit(signaller, 0);
1014 }
1015
1016 return 0;
1017}
1018
a4872ba6 1019static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1020 unsigned int num_dwords)
1ec14ad3 1021{
024a43e1
BW		 1022 struct drm_device *dev = signaller->dev;
1023 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1024 struct intel_engine_cs *useless;
a1444b79 1025 int i, ret, num_rings;
78325f2d 1026
a1444b79
BW		 1027#define MBOX_UPDATE_DWORDS 3
1028 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1029 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1030#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1031
1032 ret = intel_ring_begin(signaller, num_dwords);
1033 if (ret)
1034 return ret;
024a43e1 1035
78325f2d
BW		 1036 for_each_ring(useless, dev_priv, i) {
1037 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1038 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1039 u32 seqno = i915_gem_request_get_seqno(
1040 signaller->outstanding_lazy_request);
78325f2d
BW		 1041 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1042 intel_ring_emit(signaller, mbox_reg);
6259cead 1043 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1044 }
1045 }
024a43e1 1046
a1444b79
BW		 1047 /* If num_dwords was rounded, make sure the tail pointer is correct */
1048 if (num_rings % 2 == 0)
1049 intel_ring_emit(signaller, MI_NOOP);
1050
024a43e1 1051 return 0;
1ec14ad3
CW		 1052}
1053
c8c99b0f
BW		 1054/**
1055 * gen6_add_request - Update the semaphore mailbox registers
1056 *
1057 * @ring - ring that is adding a request
1058 * @seqno - return seqno stuck into the ring
1059 *
1060 * Update the mailbox registers in the *other* rings with the current seqno.
1061 * This acts like a signal in the canonical semaphore.
1062 */
1ec14ad3 1063static int
a4872ba6 1064gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1065{
024a43e1 1066 int ret;
52ed2325 1067
707d9cf9
BW		 1068 if (ring->semaphore.signal)
1069 ret = ring->semaphore.signal(ring, 4);
1070 else
1071 ret = intel_ring_begin(ring, 4);
1072
1ec14ad3
CW		 1073 if (ret)
1074 return ret;
1075
1ec14ad3
CW		 1076 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1077 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1078 intel_ring_emit(ring,
1079 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1080 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1081 __intel_ring_advance(ring);
1ec14ad3 1082
1ec14ad3
CW		 1083 return 0;
1084}
1085
f72b3435
MK		 1086static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1087 u32 seqno)
1088{
1089 struct drm_i915_private *dev_priv = dev->dev_private;
1090 return dev_priv->last_seqno < seqno;
1091}
1092
c8c99b0f
BW		 1093/**
1094 * intel_ring_sync - sync the waiter to the signaller on seqno
1095 *
1096 * @waiter - ring that is waiting
1097 * @signaller - ring which has, or will signal
1098 * @seqno - seqno which the waiter will block on
1099 */
5ee426ca
BW		 1100
1101static int
1102gen8_ring_sync(struct intel_engine_cs *waiter,
1103 struct intel_engine_cs *signaller,
1104 u32 seqno)
1105{
1106 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1107 int ret;
1108
1109 ret = intel_ring_begin(waiter, 4);
1110 if (ret)
1111 return ret;
1112
1113 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1114 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1115 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1116 MI_SEMAPHORE_SAD_GTE_SDD);
1117 intel_ring_emit(waiter, seqno);
1118 intel_ring_emit(waiter,
1119 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1120 intel_ring_emit(waiter,
1121 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1122 intel_ring_advance(waiter);
1123 return 0;
1124}
1125
c8c99b0f 1126static int
a4872ba6
OM		 1127gen6_ring_sync(struct intel_engine_cs *waiter,
1128 struct intel_engine_cs *signaller,
686cb5f9 1129 u32 seqno)
1ec14ad3 1130{
c8c99b0f
BW		 1131 u32 dw1 = MI_SEMAPHORE_MBOX |
1132 MI_SEMAPHORE_COMPARE |
1133 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1134 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1135 int ret;
1ec14ad3 1136
1500f7ea
BW		 1137 /* Throughout all of the GEM code, seqno passed implies our current
1138 * seqno is >= the last seqno executed. However for hardware the
1139 * comparison is strictly greater than.
1140 */
1141 seqno -= 1;
1142
ebc348b2 1143 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1144
c8c99b0f 1145 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1146 if (ret)
1147 return ret;
1148
f72b3435
MK		 1149 /* If seqno wrap happened, omit the wait with no-ops */
1150 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1151 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1152 intel_ring_emit(waiter, seqno);
1153 intel_ring_emit(waiter, 0);
1154 intel_ring_emit(waiter, MI_NOOP);
1155 } else {
1156 intel_ring_emit(waiter, MI_NOOP);
1157 intel_ring_emit(waiter, MI_NOOP);
1158 intel_ring_emit(waiter, MI_NOOP);
1159 intel_ring_emit(waiter, MI_NOOP);
1160 }
c8c99b0f 1161 intel_ring_advance(waiter);
1ec14ad3
CW		 1162
1163 return 0;
1164}
1165
c6df541c
CW		 1166#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1167do { \
fcbc34e4
KG		 1168 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1169 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1170 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1171 intel_ring_emit(ring__, 0); \
1172 intel_ring_emit(ring__, 0); \
1173} while (0)
1174
1175static int
a4872ba6 1176pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1177{
18393f63 1178 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1179 int ret;
1180
1181 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1182 * incoherent with writes to memory, i.e. completely fubar,
1183 * so we need to use PIPE_NOTIFY instead.
1184 *
1185 * However, we also need to workaround the qword write
1186 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1187 * memory before requesting an interrupt.
1188 */
1189 ret = intel_ring_begin(ring, 32);
1190 if (ret)
1191 return ret;
1192
fcbc34e4 1193 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1194 PIPE_CONTROL_WRITE_FLUSH |
1195 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1196 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1197 intel_ring_emit(ring,
1198 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1199 intel_ring_emit(ring, 0);
1200 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1201 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1202 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1203 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1204 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1205 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1206 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1207 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1208 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1209 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1210 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1211
fcbc34e4 1212 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1213 PIPE_CONTROL_WRITE_FLUSH |
1214 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1215 PIPE_CONTROL_NOTIFY);
0d1aacac 1216 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1217 intel_ring_emit(ring,
1218 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1219 intel_ring_emit(ring, 0);
09246732 1220 __intel_ring_advance(ring);
c6df541c 1221
c6df541c
CW		 1222 return 0;
1223}
1224
4cd53c0c 1225static u32
a4872ba6 1226gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1227{
4cd53c0c
DV		 1228 /* Workaround to force correct ordering between irq and seqno writes on
1229 * ivb (and maybe also on snb) by reading from a CS register (like
1230 * ACTHD) before reading the status page. */
50877445
CW		 1231 if (!lazy_coherency) {
1232 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1233 POSTING_READ(RING_ACTHD(ring->mmio_base));
1234 }
1235
4cd53c0c
DV		 1236 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1237}
1238
8187a2b7 1239static u32
a4872ba6 1240ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1241{
1ec14ad3
CW		 1242 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1243}
1244
b70ec5bf 1245static void
a4872ba6 1246ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1247{
1248 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1249}
1250
c6df541c 1251static u32
a4872ba6 1252pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1253{
0d1aacac 1254 return ring->scratch.cpu_page[0];
c6df541c
CW		 1255}
1256
b70ec5bf 1257static void
a4872ba6 1258pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1259{
0d1aacac 1260 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1261}
1262
e48d8634 1263static bool
a4872ba6 1264gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1265{
1266 struct drm_device *dev = ring->dev;
4640c4ff 1267 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1268 unsigned long flags;
e48d8634 1269
7cd512f1 1270 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1271 return false;
1272
7338aefa 1273 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1274 if (ring->irq_refcount++ == 0)
480c8033 1275 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1276 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1277
1278 return true;
1279}
1280
1281static void
a4872ba6 1282gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1283{
1284 struct drm_device *dev = ring->dev;
4640c4ff 1285 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1286 unsigned long flags;
e48d8634 1287
7338aefa 1288 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1289 if (--ring->irq_refcount == 0)
480c8033 1290 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1291 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1292}
1293
b13c2b96 1294static bool
a4872ba6 1295i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1296{
78501eac 1297 struct drm_device *dev = ring->dev;
4640c4ff 1298 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1299 unsigned long flags;
62fdfeaf 1300
7cd512f1 1301 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1302 return false;
1303
7338aefa 1304 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1305 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1306 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1307 I915_WRITE(IMR, dev_priv->irq_mask);
1308 POSTING_READ(IMR);
1309 }
7338aefa 1310 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1311
1312 return true;
62fdfeaf
EA		 1313}
1314
8187a2b7 1315static void
a4872ba6 1316i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1317{
78501eac 1318 struct drm_device *dev = ring->dev;
4640c4ff 1319 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1320 unsigned long flags;
62fdfeaf 1321
7338aefa 1322 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1323 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1324 dev_priv->irq_mask |= ring->irq_enable_mask;
1325 I915_WRITE(IMR, dev_priv->irq_mask);
1326 POSTING_READ(IMR);
1327 }
7338aefa 1328 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1329}
1330
c2798b19 1331static bool
a4872ba6 1332i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1333{
1334 struct drm_device *dev = ring->dev;
4640c4ff 1335 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1336 unsigned long flags;
c2798b19 1337
7cd512f1 1338 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1339 return false;
1340
7338aefa 1341 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1342 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1343 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1344 I915_WRITE16(IMR, dev_priv->irq_mask);
1345 POSTING_READ16(IMR);
1346 }
7338aefa 1347 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1348
1349 return true;
1350}
1351
1352static void
a4872ba6 1353i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1354{
1355 struct drm_device *dev = ring->dev;
4640c4ff 1356 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1357 unsigned long flags;
c2798b19 1358
7338aefa 1359 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1360 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1361 dev_priv->irq_mask |= ring->irq_enable_mask;
1362 I915_WRITE16(IMR, dev_priv->irq_mask);
1363 POSTING_READ16(IMR);
1364 }
7338aefa 1365 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1366}
1367
a4872ba6 1368void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1369{
4593010b 1370 struct drm_device *dev = ring->dev;
4640c4ff 1371 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1372 u32 mmio = 0;
1373
1374 /* The ring status page addresses are no longer next to the rest of
1375 * the ring registers as of gen7.
1376 */
1377 if (IS_GEN7(dev)) {
1378 switch (ring->id) {
96154f2f 1379 case RCS:
4593010b
EA		 1380 mmio = RENDER_HWS_PGA_GEN7;
1381 break;
96154f2f 1382 case BCS:
4593010b
EA		 1383 mmio = BLT_HWS_PGA_GEN7;
1384 break;
77fe2ff3
ZY		 1385 /*
1386 * VCS2 actually doesn't exist on Gen7. Only shut up
1387 * gcc switch check warning
1388 */
1389 case VCS2:
96154f2f 1390 case VCS:
4593010b
EA		 1391 mmio = BSD_HWS_PGA_GEN7;
1392 break;
4a3dd19d 1393 case VECS:
9a8a2213
BW		 1394 mmio = VEBOX_HWS_PGA_GEN7;
1395 break;
4593010b
EA		 1396 }
1397 } else if (IS_GEN6(ring->dev)) {
1398 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1399 } else {
eb0d4b75 1400 /* XXX: gen8 returns to sanity */
4593010b
EA		 1401 mmio = RING_HWS_PGA(ring->mmio_base);
1402 }
1403
78501eac
CW		 1404 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1405 POSTING_READ(mmio);
884020bf 1406
dc616b89
DL		 1407 /*
1408 * Flush the TLB for this page
1409 *
1410 * FIXME: These two bits have disappeared on gen8, so a question
1411 * arises: do we still need this and if so how should we go about
1412 * invalidating the TLB?
1413 */
1414 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1415 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1416
1417 /* ring should be idle before issuing a sync flush*/
1418 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1419
884020bf
CW		 1420 I915_WRITE(reg,
1421 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1422 INSTPM_SYNC_FLUSH));
1423 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1424 1000))
1425 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1426 ring->name);
1427 }
8187a2b7
ZN		 1428}
1429
b72f3acb 1430static int
a4872ba6 1431bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1432 u32 invalidate_domains,
1433 u32 flush_domains)
d1b851fc 1434{
b72f3acb
CW		 1435 int ret;
1436
b72f3acb
CW		 1437 ret = intel_ring_begin(ring, 2);
1438 if (ret)
1439 return ret;
1440
1441 intel_ring_emit(ring, MI_FLUSH);
1442 intel_ring_emit(ring, MI_NOOP);
1443 intel_ring_advance(ring);
1444 return 0;
d1b851fc
ZN		 1445}
1446
3cce469c 1447static int
a4872ba6 1448i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1449{
3cce469c
CW		 1450 int ret;
1451
1452 ret = intel_ring_begin(ring, 4);
1453 if (ret)
1454 return ret;
6f392d54 1455
3cce469c
CW		 1456 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1457 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1458 intel_ring_emit(ring,
1459 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1460 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1461 __intel_ring_advance(ring);
d1b851fc 1462
3cce469c 1463 return 0;
d1b851fc
ZN		 1464}
1465
0f46832f 1466static bool
a4872ba6 1467gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1468{
1469 struct drm_device *dev = ring->dev;
4640c4ff 1470 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1471 unsigned long flags;
0f46832f 1472
7cd512f1
DV		 1473 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1474 return false;
0f46832f 1475
7338aefa 1476 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1477 if (ring->irq_refcount++ == 0) {
040d2baa 1478 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1479 I915_WRITE_IMR(ring,
1480 ~(ring->irq_enable_mask |
35a85ac6 1481 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1482 else
1483 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1484 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1485 }
7338aefa 1486 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1487
1488 return true;
1489}
1490
1491static void
a4872ba6 1492gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1493{
1494 struct drm_device *dev = ring->dev;
4640c4ff 1495 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1496 unsigned long flags;
0f46832f 1497
7338aefa 1498 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1499 if (--ring->irq_refcount == 0) {
040d2baa 1500 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1501 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1502 else
1503 I915_WRITE_IMR(ring, ~0);
480c8033 1504 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1505 }
7338aefa 1506 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1507}
1508
a19d2933 1509static bool
a4872ba6 1510hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1511{
1512 struct drm_device *dev = ring->dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 unsigned long flags;
1515
7cd512f1 1516 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1517 return false;
1518
59cdb63d 1519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1520 if (ring->irq_refcount++ == 0) {
a19d2933 1521 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1522 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1523 }
59cdb63d 1524 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1525
1526 return true;
1527}
1528
1529static void
a4872ba6 1530hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1531{
1532 struct drm_device *dev = ring->dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 unsigned long flags;
1535
59cdb63d 1536 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1537 if (--ring->irq_refcount == 0) {
a19d2933 1538 I915_WRITE_IMR(ring, ~0);
480c8033 1539 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1540 }
59cdb63d 1541 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1542}
1543
abd58f01 1544static bool
a4872ba6 1545gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1546{
1547 struct drm_device *dev = ring->dev;
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 unsigned long flags;
1550
7cd512f1 1551 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1552 return false;
1553
1554 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1555 if (ring->irq_refcount++ == 0) {
1556 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1557 I915_WRITE_IMR(ring,
1558 ~(ring->irq_enable_mask |
1559 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1560 } else {
1561 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1562 }
1563 POSTING_READ(RING_IMR(ring->mmio_base));
1564 }
1565 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1566
1567 return true;
1568}
1569
1570static void
a4872ba6 1571gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1572{
1573 struct drm_device *dev = ring->dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 unsigned long flags;
1576
1577 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1578 if (--ring->irq_refcount == 0) {
1579 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1580 I915_WRITE_IMR(ring,
1581 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1582 } else {
1583 I915_WRITE_IMR(ring, ~0);
1584 }
1585 POSTING_READ(RING_IMR(ring->mmio_base));
1586 }
1587 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1588}
1589
d1b851fc 1590static int
a4872ba6 1591i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1592 u64 offset, u32 length,
d7d4eedd 1593 unsigned flags)
d1b851fc 1594{
e1f99ce6 1595 int ret;
78501eac 1596
e1f99ce6
CW		 1597 ret = intel_ring_begin(ring, 2);
1598 if (ret)
1599 return ret;
1600
78501eac 1601 intel_ring_emit(ring,
65f56876
CW		 1602 MI_BATCH_BUFFER_START |
1603 MI_BATCH_GTT |
d7d4eedd 1604 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1605 intel_ring_emit(ring, offset);
78501eac
CW		 1606 intel_ring_advance(ring);
1607
d1b851fc
ZN		 1608 return 0;
1609}
1610
b45305fc
DV		 1611/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1612#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1613#define I830_TLB_ENTRIES (2)
1614#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1615static int
a4872ba6 1616i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1617 u64 offset, u32 len,
d7d4eedd 1618 unsigned flags)
62fdfeaf 1619{
c4d69da1 1620 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1621 int ret;
62fdfeaf 1622
c4d69da1
CW		 1623 ret = intel_ring_begin(ring, 6);
1624 if (ret)
1625 return ret;
62fdfeaf 1626
c4d69da1
CW		 1627 /* Evict the invalid PTE TLBs */
1628 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1629 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1630 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1631 intel_ring_emit(ring, cs_offset);
1632 intel_ring_emit(ring, 0xdeadbeef);
1633 intel_ring_emit(ring, MI_NOOP);
1634 intel_ring_advance(ring);
b45305fc 1635
c4d69da1 1636 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1637 if (len > I830_BATCH_LIMIT)
1638 return -ENOSPC;
1639
c4d69da1 1640 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1641 if (ret)
1642 return ret;
c4d69da1
CW		 1643
1644 /* Blit the batch (which has now all relocs applied) to the
1645 * stable batch scratch bo area (so that the CS never
1646 * stumbles over its tlb invalidation bug) ...
1647 */
1648 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1649 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1650 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1651 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1652 intel_ring_emit(ring, 4096);
1653 intel_ring_emit(ring, offset);
c4d69da1 1654
b45305fc 1655 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1656 intel_ring_emit(ring, MI_NOOP);
1657 intel_ring_advance(ring);
b45305fc
DV		 1658
1659 /* ... and execute it. */
c4d69da1 1660 offset = cs_offset;
b45305fc 1661 }
e1f99ce6 1662
c4d69da1
CW		 1663 ret = intel_ring_begin(ring, 4);
1664 if (ret)
1665 return ret;
1666
1667 intel_ring_emit(ring, MI_BATCH_BUFFER);
1668 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1669 intel_ring_emit(ring, offset + len - 8);
1670 intel_ring_emit(ring, MI_NOOP);
1671 intel_ring_advance(ring);
1672
fb3256da
DV		 1673 return 0;
1674}
1675
1676static int
a4872ba6 1677i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1678 u64 offset, u32 len,
d7d4eedd 1679 unsigned flags)
fb3256da
DV		 1680{
1681 int ret;
1682
1683 ret = intel_ring_begin(ring, 2);
1684 if (ret)
1685 return ret;
1686
65f56876 1687 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1688 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1689 intel_ring_advance(ring);
62fdfeaf 1690
62fdfeaf
EA		 1691 return 0;
1692}
1693
a4872ba6 1694static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1695{
05394f39 1696 struct drm_i915_gem_object *obj;
62fdfeaf 1697
8187a2b7
ZN		 1698 obj = ring->status_page.obj;
1699 if (obj == NULL)
62fdfeaf 1700 return;
62fdfeaf 1701
9da3da66 1702 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1703 i915_gem_object_ggtt_unpin(obj);
05394f39 1704 drm_gem_object_unreference(&obj->base);
8187a2b7 1705 ring->status_page.obj = NULL;
62fdfeaf
EA		 1706}
1707
a4872ba6 1708static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1709{
05394f39 1710 struct drm_i915_gem_object *obj;
62fdfeaf 1711
e3efda49 1712 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1713 unsigned flags;
e3efda49 1714 int ret;
e4ffd173 1715
e3efda49
CW		 1716 obj = i915_gem_alloc_object(ring->dev, 4096);
1717 if (obj == NULL) {
1718 DRM_ERROR("Failed to allocate status page\n");
1719 return -ENOMEM;
1720 }
62fdfeaf 1721
e3efda49
CW		 1722 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1723 if (ret)
1724 goto err_unref;
1725
1f767e02
CW		 1726 flags = 0;
1727 if (!HAS_LLC(ring->dev))
1728 /* On g33, we cannot place HWS above 256MiB, so
1729 * restrict its pinning to the low mappable arena.
1730 * Though this restriction is not documented for
1731 * gen4, gen5, or byt, they also behave similarly
1732 * and hang if the HWS is placed at the top of the
1733 * GTT. To generalise, it appears that all !llc
1734 * platforms have issues with us placing the HWS
1735 * above the mappable region (even though we never
1736 * actualy map it).
1737 */
1738 flags |= PIN_MAPPABLE;
1739 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1740 if (ret) {
1741err_unref:
1742 drm_gem_object_unreference(&obj->base);
1743 return ret;
1744 }
1745
1746 ring->status_page.obj = obj;
1747 }
62fdfeaf 1748
f343c5f6 1749 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1750 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1751 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1752
8187a2b7
ZN		 1753 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1754 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1755
1756 return 0;
62fdfeaf
EA		 1757}
1758
a4872ba6 1759static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1760{
1761 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1762
1763 if (!dev_priv->status_page_dmah) {
1764 dev_priv->status_page_dmah =
1765 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1766 if (!dev_priv->status_page_dmah)
1767 return -ENOMEM;
1768 }
1769
6b8294a4
CW		 1770 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1771 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1772
1773 return 0;
1774}
1775
7ba717cf 1776void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1777{
2919d291 1778 iounmap(ringbuf->virtual_start);
7ba717cf 1779 ringbuf->virtual_start = NULL;
2919d291 1780 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1781}
1782
1783int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1784 struct intel_ringbuffer *ringbuf)
1785{
1786 struct drm_i915_private *dev_priv = to_i915(dev);
1787 struct drm_i915_gem_object *obj = ringbuf->obj;
1788 int ret;
1789
1790 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1791 if (ret)
1792 return ret;
1793
1794 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1795 if (ret) {
1796 i915_gem_object_ggtt_unpin(obj);
1797 return ret;
1798 }
1799
1800 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1801 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1802 if (ringbuf->virtual_start == NULL) {
1803 i915_gem_object_ggtt_unpin(obj);
1804 return -EINVAL;
1805 }
1806
1807 return 0;
1808}
1809
1810void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1811{
2919d291
OM		 1812 drm_gem_object_unreference(&ringbuf->obj->base);
1813 ringbuf->obj = NULL;
1814}
1815
84c2377f
OM		 1816int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1817 struct intel_ringbuffer *ringbuf)
62fdfeaf 1818{
05394f39 1819 struct drm_i915_gem_object *obj;
62fdfeaf 1820
ebc052e0
CW		 1821 obj = NULL;
1822 if (!HAS_LLC(dev))
93b0a4e0 1823 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1824 if (obj == NULL)
93b0a4e0 1825 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1826 if (obj == NULL)
1827 return -ENOMEM;
8187a2b7 1828
24f3a8cf
AG		 1829 /* mark ring buffers as read-only from GPU side by default */
1830 obj->gt_ro = 1;
1831
93b0a4e0 1832 ringbuf->obj = obj;
e3efda49 1833
7ba717cf 1834 return 0;
e3efda49
CW		 1835}
1836
1837static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1838 struct intel_engine_cs *ring)
e3efda49 1839{
bfc882b4 1840 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1841 int ret;
1842
bfc882b4
DV		 1843 WARN_ON(ring->buffer);
1844
1845 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1846 if (!ringbuf)
1847 return -ENOMEM;
1848 ring->buffer = ringbuf;
8ee14975 1849
e3efda49
CW		 1850 ring->dev = dev;
1851 INIT_LIST_HEAD(&ring->active_list);
1852 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1853 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1854 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1855 ringbuf->ring = ring;
ebc348b2 1856 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1857
1858 init_waitqueue_head(&ring->irq_queue);
1859
1860 if (I915_NEED_GFX_HWS(dev)) {
1861 ret = init_status_page(ring);
1862 if (ret)
8ee14975 1863 goto error;
e3efda49
CW		 1864 } else {
1865 BUG_ON(ring->id != RCS);
1866 ret = init_phys_status_page(ring);
1867 if (ret)
8ee14975 1868 goto error;
e3efda49
CW		 1869 }
1870
bfc882b4 1871 WARN_ON(ringbuf->obj);
7ba717cf 1872
bfc882b4
DV		 1873 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1874 if (ret) {
1875 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1876 ring->name, ret);
1877 goto error;
1878 }
1879
1880 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1881 if (ret) {
1882 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1883 ring->name, ret);
1884 intel_destroy_ringbuffer_obj(ringbuf);
1885 goto error;
e3efda49 1886 }
62fdfeaf 1887
55249baa
CW		 1888 /* Workaround an erratum on the i830 which causes a hang if
1889 * the TAIL pointer points to within the last 2 cachelines
1890 * of the buffer.
1891 */
93b0a4e0 1892 ringbuf->effective_size = ringbuf->size;
e3efda49 1893 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1894 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1895
44e895a8
BV		 1896 ret = i915_cmd_parser_init_ring(ring);
1897 if (ret)
8ee14975
OM		 1898 goto error;
1899
8ee14975 1900 return 0;
351e3db2 1901
8ee14975
OM		 1902error:
1903 kfree(ringbuf);
1904 ring->buffer = NULL;
1905 return ret;
62fdfeaf
EA		 1906}
1907
a4872ba6 1908void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1909{
6402c330
JH		 1910 struct drm_i915_private *dev_priv;
1911 struct intel_ringbuffer *ringbuf;
33626e6a 1912
93b0a4e0 1913 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1914 return;
1915
6402c330
JH		 1916 dev_priv = to_i915(ring->dev);
1917 ringbuf = ring->buffer;
1918
e3efda49 1919 intel_stop_ring_buffer(ring);
de8f0a50 1920 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1921
7ba717cf 1922 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 1923 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 1924 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 1925
8d19215b
ZN		 1926 if (ring->cleanup)
1927 ring->cleanup(ring);
1928
78501eac 1929 cleanup_status_page(ring);
44e895a8
BV		 1930
1931 i915_cmd_parser_fini_ring(ring);
8ee14975 1932
93b0a4e0 1933 kfree(ringbuf);
8ee14975 1934 ring->buffer = NULL;
62fdfeaf
EA		 1935}
1936
a4872ba6 1937static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1938{
93b0a4e0 1939 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1940 struct drm_i915_gem_request *request;
a71d8d94
CW		 1941 int ret;
1942
ebd0fd4b
DG		 1943 if (intel_ring_space(ringbuf) >= n)
1944 return 0;
a71d8d94
CW		 1945
1946 list_for_each_entry(request, &ring->request_list, list) {
82e104cc
OM		 1947 if (__intel_ring_space(request->tail, ringbuf->tail,
1948 ringbuf->size) >= n) {
a71d8d94
CW		 1949 break;
1950 }
a71d8d94
CW		 1951 }
1952
a4b3a571 1953 if (&request->list == &ring->request_list)
a71d8d94
CW		 1954 return -ENOSPC;
1955
a4b3a571 1956 ret = i915_wait_request(request);
a71d8d94
CW		 1957 if (ret)
1958 return ret;
1959
1cf0ba14 1960 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 1961
1962 return 0;
1963}
1964
a4872ba6 1965static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1966{
78501eac 1967 struct drm_device *dev = ring->dev;
cae5852d 1968 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1969 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1970 unsigned long end;
a71d8d94 1971 int ret;
c7dca47b 1972
a71d8d94
CW		 1973 ret = intel_ring_wait_request(ring, n);
1974 if (ret != -ENOSPC)
1975 return ret;
1976
09246732
CW		 1977 /* force the tail write in case we have been skipping them */
1978 __intel_ring_advance(ring);
1979
63ed2cb2
DV		 1980 /* With GEM the hangcheck timer should kick us out of the loop,
1981 * leaving it early runs the risk of corrupting GEM state (due
1982 * to running on almost untested codepaths). But on resume
1983 * timers don't work yet, so prevent a complete hang in that
1984 * case by choosing an insanely large timeout. */
1985 end = jiffies + 60 * HZ;
e6bfaf85 1986
ebd0fd4b 1987 ret = 0;
dcfe0506 1988 trace_i915_ring_wait_begin(ring);
8187a2b7 1989 do {
ebd0fd4b
DG		 1990 if (intel_ring_space(ringbuf) >= n)
1991 break;
93b0a4e0 1992 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 1993 if (intel_ring_space(ringbuf) >= n)
dcfe0506 1994 break;
62fdfeaf 1995
e60a0b10 1996 msleep(1);
d6b2c790 1997
dcfe0506
CW		 1998 if (dev_priv->mm.interruptible && signal_pending(current)) {
1999 ret = -ERESTARTSYS;
2000 break;
2001 }
2002
33196ded
DV		 2003 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2004 dev_priv->mm.interruptible);
d6b2c790 2005 if (ret)
dcfe0506
CW		 2006 break;
2007
2008 if (time_after(jiffies, end)) {
2009 ret = -EBUSY;
2010 break;
2011 }
2012 } while (1);
db53a302 2013 trace_i915_ring_wait_end(ring);
dcfe0506 2014 return ret;
8187a2b7 2015}
62fdfeaf 2016
a4872ba6 2017static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2018{
2019 uint32_t __iomem *virt;
93b0a4e0
OM		 2020 struct intel_ringbuffer *ringbuf = ring->buffer;
2021 int rem = ringbuf->size - ringbuf->tail;
3e960501 2022
93b0a4e0 2023 if (ringbuf->space < rem) {
3e960501
CW		 2024 int ret = ring_wait_for_space(ring, rem);
2025 if (ret)
2026 return ret;
2027 }
2028
93b0a4e0 2029 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2030 rem /= 4;
2031 while (rem--)
2032 iowrite32(MI_NOOP, virt++);
2033
93b0a4e0 2034 ringbuf->tail = 0;
ebd0fd4b 2035 intel_ring_update_space(ringbuf);
3e960501
CW		 2036
2037 return 0;
2038}
2039
a4872ba6 2040int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2041{
a4b3a571 2042 struct drm_i915_gem_request *req;
3e960501
CW		 2043 int ret;
2044
2045 /* We need to add any requests required to flush the objects and ring */
6259cead 2046 if (ring->outstanding_lazy_request) {
9400ae5c 2047 ret = i915_add_request(ring);
3e960501
CW		 2048 if (ret)
2049 return ret;
2050 }
2051
2052 /* Wait upon the last request to be completed */
2053 if (list_empty(&ring->request_list))
2054 return 0;
2055
a4b3a571 2056 req = list_entry(ring->request_list.prev,
3e960501 2057 struct drm_i915_gem_request,
a4b3a571 2058 list);
3e960501 2059
a4b3a571 2060 return i915_wait_request(req);
3e960501
CW		 2061}
2062
9d773091 2063static int
6259cead 2064intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2065{
9eba5d4a
JH		 2066 int ret;
2067 struct drm_i915_gem_request *request;
67e2937b 2068 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2069
6259cead 2070 if (ring->outstanding_lazy_request)
9d773091 2071 return 0;
3c0e234c 2072
aaeb1ba0 2073 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2074 if (request == NULL)
2075 return -ENOMEM;
3c0e234c 2076
abfe262a 2077 kref_init(&request->ref);
ff79e857 2078 request->ring = ring;
67e2937b 2079 request->uniq = dev_private->request_uniq++;
abfe262a 2080
6259cead 2081 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2082 if (ret) {
2083 kfree(request);
2084 return ret;
3c0e234c
CW		 2085 }
2086
6259cead 2087 ring->outstanding_lazy_request = request;
9eba5d4a 2088 return 0;
9d773091
CW		 2089}
2090
a4872ba6 2091static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2092 int bytes)
cbcc80df 2093{
93b0a4e0 2094 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2095 int ret;
2096
93b0a4e0 2097 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2098 ret = intel_wrap_ring_buffer(ring);
2099 if (unlikely(ret))
2100 return ret;
2101 }
2102
93b0a4e0 2103 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2104 ret = ring_wait_for_space(ring, bytes);
2105 if (unlikely(ret))
2106 return ret;
2107 }
2108
cbcc80df
MK		 2109 return 0;
2110}
2111
a4872ba6 2112int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2113 int num_dwords)
8187a2b7 2114{
4640c4ff 2115 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2116 int ret;
78501eac 2117
33196ded
DV		 2118 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2119 dev_priv->mm.interruptible);
de2b9985
DV		 2120 if (ret)
2121 return ret;
21dd3734 2122
304d695c
CW		 2123 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2124 if (ret)
2125 return ret;
2126
9d773091 2127 /* Preallocate the olr before touching the ring */
6259cead 2128 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2129 if (ret)
2130 return ret;
2131
ee1b1e5e 2132 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2133 return 0;
8187a2b7 2134}
78501eac 2135
753b1ad4 2136/* Align the ring tail to a cacheline boundary */
a4872ba6 2137int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2138{
ee1b1e5e 2139 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2140 int ret;
2141
2142 if (num_dwords == 0)
2143 return 0;
2144
18393f63 2145 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2146 ret = intel_ring_begin(ring, num_dwords);
2147 if (ret)
2148 return ret;
2149
2150 while (num_dwords--)
2151 intel_ring_emit(ring, MI_NOOP);
2152
2153 intel_ring_advance(ring);
2154
2155 return 0;
2156}
2157
a4872ba6 2158void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2159{
3b2cc8ab
OM		 2160 struct drm_device *dev = ring->dev;
2161 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2162
6259cead 2163 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2164
3b2cc8ab 2165 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2166 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2167 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2168 if (HAS_VEBOX(dev))
5020150b 2169 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2170 }
d97ed339 2171
f7e98ad4 2172 ring->set_seqno(ring, seqno);
92cab734 2173 ring->hangcheck.seqno = seqno;
8187a2b7 2174}
62fdfeaf 2175
a4872ba6 2176static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2177 u32 value)
881f47b6 2178{
4640c4ff 2179 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2180
2181 /* Every tail move must follow the sequence below */
12f55818
CW		 2182
2183 /* Disable notification that the ring is IDLE. The GT
2184 * will then assume that it is busy and bring it out of rc6.
2185 */
0206e353 2186 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2187 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2188
2189 /* Clear the context id. Here be magic! */
2190 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2191
12f55818 2192 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2193 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2194 GEN6_BSD_SLEEP_INDICATOR) == 0,
2195 50))
2196 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2197
12f55818 2198 /* Now that the ring is fully powered up, update the tail */
0206e353 2199 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2200 POSTING_READ(RING_TAIL(ring->mmio_base));
2201
2202 /* Let the ring send IDLE messages to the GT again,
2203 * and so let it sleep to conserve power when idle.
2204 */
0206e353 2205 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2206 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2207}
2208
a4872ba6 2209static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2210 u32 invalidate, u32 flush)
881f47b6 2211{
71a77e07 2212 uint32_t cmd;
b72f3acb
CW		 2213 int ret;
2214
b72f3acb
CW		 2215 ret = intel_ring_begin(ring, 4);
2216 if (ret)
2217 return ret;
2218
71a77e07 2219 cmd = MI_FLUSH_DW;
075b3bba
BW		 2220 if (INTEL_INFO(ring->dev)->gen >= 8)
2221 cmd += 1;
9a289771
JB		 2222 /*
2223 * Bspec vol 1c.5 - video engine command streamer:
2224 * "If ENABLED, all TLBs will be invalidated once the flush
2225 * operation is complete. This bit is only valid when the
2226 * Post-Sync Operation field is a value of 1h or 3h."
2227 */
71a77e07 2228 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2229 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2230 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2231 intel_ring_emit(ring, cmd);
9a289771 2232 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2233 if (INTEL_INFO(ring->dev)->gen >= 8) {
2234 intel_ring_emit(ring, 0); /* upper addr */
2235 intel_ring_emit(ring, 0); /* value */
2236 } else {
2237 intel_ring_emit(ring, 0);
2238 intel_ring_emit(ring, MI_NOOP);
2239 }
b72f3acb
CW		 2240 intel_ring_advance(ring);
2241 return 0;
881f47b6
XH		 2242}
2243
1c7a0623 2244static int
a4872ba6 2245gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2246 u64 offset, u32 len,
1c7a0623
BW		 2247 unsigned flags)
2248{
896ab1a5 2249 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2250 int ret;
2251
2252 ret = intel_ring_begin(ring, 4);
2253 if (ret)
2254 return ret;
2255
2256 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2257 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2258 intel_ring_emit(ring, lower_32_bits(offset));
2259 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2260 intel_ring_emit(ring, MI_NOOP);
2261 intel_ring_advance(ring);
2262
2263 return 0;
2264}
2265
d7d4eedd 2266static int
a4872ba6 2267hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2268 u64 offset, u32 len,
d7d4eedd
CW		 2269 unsigned flags)
2270{
2271 int ret;
2272
2273 ret = intel_ring_begin(ring, 2);
2274 if (ret)
2275 return ret;
2276
2277 intel_ring_emit(ring,
77072258
CW		 2278 MI_BATCH_BUFFER_START |
2279 (flags & I915_DISPATCH_SECURE ?
2280 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2281 /* bit0-7 is the length on GEN6+ */
2282 intel_ring_emit(ring, offset);
2283 intel_ring_advance(ring);
2284
2285 return 0;
2286}
2287
881f47b6 2288static int
a4872ba6 2289gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2290 u64 offset, u32 len,
d7d4eedd 2291 unsigned flags)
881f47b6 2292{
0206e353 2293 int ret;
ab6f8e32 2294
0206e353
AJ		 2295 ret = intel_ring_begin(ring, 2);
2296 if (ret)
2297 return ret;
e1f99ce6 2298
d7d4eedd
CW		 2299 intel_ring_emit(ring,
2300 MI_BATCH_BUFFER_START |
2301 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2302 /* bit0-7 is the length on GEN6+ */
2303 intel_ring_emit(ring, offset);
2304 intel_ring_advance(ring);
ab6f8e32 2305
0206e353 2306 return 0;
881f47b6
XH		 2307}
2308
549f7365
CW		 2309/* Blitter support (SandyBridge+) */
2310
a4872ba6 2311static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2312 u32 invalidate, u32 flush)
8d19215b 2313{
fd3da6c9 2314 struct drm_device *dev = ring->dev;
1d73c2a8 2315 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2316 uint32_t cmd;
b72f3acb
CW		 2317 int ret;
2318
6a233c78 2319 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2320 if (ret)
2321 return ret;
2322
71a77e07 2323 cmd = MI_FLUSH_DW;
075b3bba
BW		 2324 if (INTEL_INFO(ring->dev)->gen >= 8)
2325 cmd += 1;
9a289771
JB		 2326 /*
2327 * Bspec vol 1c.3 - blitter engine command streamer:
2328 * "If ENABLED, all TLBs will be invalidated once the flush
2329 * operation is complete. This bit is only valid when the
2330 * Post-Sync Operation field is a value of 1h or 3h."
2331 */
71a77e07 2332 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2333 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2334 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2335 intel_ring_emit(ring, cmd);
9a289771 2336 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2337 if (INTEL_INFO(ring->dev)->gen >= 8) {
2338 intel_ring_emit(ring, 0); /* upper addr */
2339 intel_ring_emit(ring, 0); /* value */
2340 } else {
2341 intel_ring_emit(ring, 0);
2342 intel_ring_emit(ring, MI_NOOP);
2343 }
b72f3acb 2344 intel_ring_advance(ring);
fd3da6c9 2345
1d73c2a8
RV		 2346 if (!invalidate && flush) {
2347 if (IS_GEN7(dev))
2348 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2349 else if (IS_BROADWELL(dev))
2350 dev_priv->fbc.need_sw_cache_clean = true;
2351 }
fd3da6c9 2352
b72f3acb 2353 return 0;
8d19215b
ZN		 2354}
2355
5c1143bb
XH		 2356int intel_init_render_ring_buffer(struct drm_device *dev)
2357{
4640c4ff 2358 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2359 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2360 struct drm_i915_gem_object *obj;
2361 int ret;
5c1143bb 2362
59465b5f
DV		 2363 ring->name = "render ring";
2364 ring->id = RCS;
2365 ring->mmio_base = RENDER_RING_BASE;
2366
707d9cf9 2367 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2368 if (i915_semaphore_is_enabled(dev)) {
2369 obj = i915_gem_alloc_object(dev, 4096);
2370 if (obj == NULL) {
2371 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2372 i915.semaphores = 0;
2373 } else {
2374 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2375 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2376 if (ret != 0) {
2377 drm_gem_object_unreference(&obj->base);
2378 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2379 i915.semaphores = 0;
2380 } else
2381 dev_priv->semaphore_obj = obj;
2382 }
2383 }
7225342a 2384
8f0e2b9d 2385 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2386 ring->add_request = gen6_add_request;
2387 ring->flush = gen8_render_ring_flush;
2388 ring->irq_get = gen8_ring_get_irq;
2389 ring->irq_put = gen8_ring_put_irq;
2390 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2391 ring->get_seqno = gen6_ring_get_seqno;
2392 ring->set_seqno = ring_set_seqno;
2393 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2394 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2395 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2396 ring->semaphore.signal = gen8_rcs_signal;
2397 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2398 }
2399 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2400 ring->add_request = gen6_add_request;
4772eaeb 2401 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2402 if (INTEL_INFO(dev)->gen == 6)
b3111509 2403 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2404 ring->irq_get = gen6_ring_get_irq;
2405 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2406 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2407 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2408 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2409 if (i915_semaphore_is_enabled(dev)) {
2410 ring->semaphore.sync_to = gen6_ring_sync;
2411 ring->semaphore.signal = gen6_signal;
2412 /*
2413 * The current semaphore is only applied on pre-gen8
2414 * platform. And there is no VCS2 ring on the pre-gen8
2415 * platform. So the semaphore between RCS and VCS2 is
2416 * initialized as INVALID. Gen8 will initialize the
2417 * sema between VCS2 and RCS later.
2418 */
2419 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2420 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2421 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2422 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2423 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2424 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2425 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2426 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2427 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2428 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2429 }
c6df541c
CW		 2430 } else if (IS_GEN5(dev)) {
2431 ring->add_request = pc_render_add_request;
46f0f8d1 2432 ring->flush = gen4_render_ring_flush;
c6df541c 2433 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2434 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2435 ring->irq_get = gen5_ring_get_irq;
2436 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2437 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2438 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2439 } else {
8620a3a9 2440 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2441 if (INTEL_INFO(dev)->gen < 4)
2442 ring->flush = gen2_render_ring_flush;
2443 else
2444 ring->flush = gen4_render_ring_flush;
59465b5f 2445 ring->get_seqno = ring_get_seqno;
b70ec5bf 2446 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2447 if (IS_GEN2(dev)) {
2448 ring->irq_get = i8xx_ring_get_irq;
2449 ring->irq_put = i8xx_ring_put_irq;
2450 } else {
2451 ring->irq_get = i9xx_ring_get_irq;
2452 ring->irq_put = i9xx_ring_put_irq;
2453 }
e3670319 2454 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2455 }
59465b5f 2456 ring->write_tail = ring_write_tail;
707d9cf9 2457
d7d4eedd
CW		 2458 if (IS_HASWELL(dev))
2459 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2460 else if (IS_GEN8(dev))
2461 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2462 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2463 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2464 else if (INTEL_INFO(dev)->gen >= 4)
2465 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2466 else if (IS_I830(dev) || IS_845G(dev))
2467 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2468 else
2469 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2470 ring->init_hw = init_render_ring;
59465b5f
DV		 2471 ring->cleanup = render_ring_cleanup;
2472
b45305fc
DV		 2473 /* Workaround batchbuffer to combat CS tlb bug. */
2474 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2475 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2476 if (obj == NULL) {
2477 DRM_ERROR("Failed to allocate batch bo\n");
2478 return -ENOMEM;
2479 }
2480
be1fa129 2481 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2482 if (ret != 0) {
2483 drm_gem_object_unreference(&obj->base);
2484 DRM_ERROR("Failed to ping batch bo\n");
2485 return ret;
2486 }
2487
0d1aacac
CW		 2488 ring->scratch.obj = obj;
2489 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2490 }
2491
99be1dfe
DV		 2492 ret = intel_init_ring_buffer(dev, ring);
2493 if (ret)
2494 return ret;
2495
2496 if (INTEL_INFO(dev)->gen >= 5) {
2497 ret = intel_init_pipe_control(ring);
2498 if (ret)
2499 return ret;
2500 }
2501
2502 return 0;
5c1143bb
XH		 2503}
2504
2505int intel_init_bsd_ring_buffer(struct drm_device *dev)
2506{
4640c4ff 2507 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2508 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2509
58fa3835
DV		 2510 ring->name = "bsd ring";
2511 ring->id = VCS;
2512
0fd2c201 2513 ring->write_tail = ring_write_tail;
780f18c8 2514 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2515 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2516 /* gen6 bsd needs a special wa for tail updates */
2517 if (IS_GEN6(dev))
2518 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2519 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2520 ring->add_request = gen6_add_request;
2521 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2522 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2523 if (INTEL_INFO(dev)->gen >= 8) {
2524 ring->irq_enable_mask =
2525 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2526 ring->irq_get = gen8_ring_get_irq;
2527 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2528 ring->dispatch_execbuffer =
2529 gen8_ring_dispatch_execbuffer;
707d9cf9 2530 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2531 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2532 ring->semaphore.signal = gen8_xcs_signal;
2533 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2534 }
abd58f01
BW		 2535 } else {
2536 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2537 ring->irq_get = gen6_ring_get_irq;
2538 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2539 ring->dispatch_execbuffer =
2540 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2541 if (i915_semaphore_is_enabled(dev)) {
2542 ring->semaphore.sync_to = gen6_ring_sync;
2543 ring->semaphore.signal = gen6_signal;
2544 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2545 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2546 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2547 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2548 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2549 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2550 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2551 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2552 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2553 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2554 }
abd58f01 2555 }
58fa3835
DV		 2556 } else {
2557 ring->mmio_base = BSD_RING_BASE;
58fa3835 2558 ring->flush = bsd_ring_flush;
8620a3a9 2559 ring->add_request = i9xx_add_request;
58fa3835 2560 ring->get_seqno = ring_get_seqno;
b70ec5bf 2561 ring->set_seqno = ring_set_seqno;
e48d8634 2562 if (IS_GEN5(dev)) {
cc609d5d 2563 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2564 ring->irq_get = gen5_ring_get_irq;
2565 ring->irq_put = gen5_ring_put_irq;
2566 } else {
e3670319 2567 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2568 ring->irq_get = i9xx_ring_get_irq;
2569 ring->irq_put = i9xx_ring_put_irq;
2570 }
fb3256da 2571 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2572 }
ecfe00d8 2573 ring->init_hw = init_ring_common;
58fa3835 2574
1ec14ad3 2575 return intel_init_ring_buffer(dev, ring);
5c1143bb 2576}
549f7365 2577
845f74a7
ZY		 2578/**
2579 * Initialize the second BSD ring for Broadwell GT3.
2580 * It is noted that this only exists on Broadwell GT3.
2581 */
2582int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2583{
2584 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2585 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2586
2587 if ((INTEL_INFO(dev)->gen != 8)) {
2588 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2589 return -EINVAL;
2590 }
2591
f7b64236 2592 ring->name = "bsd2 ring";
845f74a7
ZY		 2593 ring->id = VCS2;
2594
2595 ring->write_tail = ring_write_tail;
2596 ring->mmio_base = GEN8_BSD2_RING_BASE;
2597 ring->flush = gen6_bsd_ring_flush;
2598 ring->add_request = gen6_add_request;
2599 ring->get_seqno = gen6_ring_get_seqno;
2600 ring->set_seqno = ring_set_seqno;
2601 ring->irq_enable_mask =
2602 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2603 ring->irq_get = gen8_ring_get_irq;
2604 ring->irq_put = gen8_ring_put_irq;
2605 ring->dispatch_execbuffer =
2606 gen8_ring_dispatch_execbuffer;
3e78998a 2607 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2608 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2609 ring->semaphore.signal = gen8_xcs_signal;
2610 GEN8_RING_SEMAPHORE_INIT;
2611 }
ecfe00d8 2612 ring->init_hw = init_ring_common;
845f74a7
ZY		 2613
2614 return intel_init_ring_buffer(dev, ring);
2615}
2616
549f7365
CW		 2617int intel_init_blt_ring_buffer(struct drm_device *dev)
2618{
4640c4ff 2619 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2620 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2621
3535d9dd
DV		 2622 ring->name = "blitter ring";
2623 ring->id = BCS;
2624
2625 ring->mmio_base = BLT_RING_BASE;
2626 ring->write_tail = ring_write_tail;
ea251324 2627 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2628 ring->add_request = gen6_add_request;
2629 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2630 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2631 if (INTEL_INFO(dev)->gen >= 8) {
2632 ring->irq_enable_mask =
2633 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2634 ring->irq_get = gen8_ring_get_irq;
2635 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2636 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2637 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2638 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2639 ring->semaphore.signal = gen8_xcs_signal;
2640 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2641 }
abd58f01
BW		 2642 } else {
2643 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2644 ring->irq_get = gen6_ring_get_irq;
2645 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2646 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2647 if (i915_semaphore_is_enabled(dev)) {
2648 ring->semaphore.signal = gen6_signal;
2649 ring->semaphore.sync_to = gen6_ring_sync;
2650 /*
2651 * The current semaphore is only applied on pre-gen8
2652 * platform. And there is no VCS2 ring on the pre-gen8
2653 * platform. So the semaphore between BCS and VCS2 is
2654 * initialized as INVALID. Gen8 will initialize the
2655 * sema between BCS and VCS2 later.
2656 */
2657 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2658 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2659 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2660 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2661 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2662 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2663 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2664 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2665 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2666 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2667 }
abd58f01 2668 }
ecfe00d8 2669 ring->init_hw = init_ring_common;
549f7365 2670
1ec14ad3 2671 return intel_init_ring_buffer(dev, ring);
549f7365 2672}
a7b9761d 2673
9a8a2213
BW		 2674int intel_init_vebox_ring_buffer(struct drm_device *dev)
2675{
4640c4ff 2676 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2677 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2678
2679 ring->name = "video enhancement ring";
2680 ring->id = VECS;
2681
2682 ring->mmio_base = VEBOX_RING_BASE;
2683 ring->write_tail = ring_write_tail;
2684 ring->flush = gen6_ring_flush;
2685 ring->add_request = gen6_add_request;
2686 ring->get_seqno = gen6_ring_get_seqno;
2687 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2688
2689 if (INTEL_INFO(dev)->gen >= 8) {
2690 ring->irq_enable_mask =
40c499f9 2691 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2692 ring->irq_get = gen8_ring_get_irq;
2693 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2694 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2695 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2696 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2697 ring->semaphore.signal = gen8_xcs_signal;
2698 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2699 }
abd58f01
BW		 2700 } else {
2701 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2702 ring->irq_get = hsw_vebox_get_irq;
2703 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2704 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2705 if (i915_semaphore_is_enabled(dev)) {
2706 ring->semaphore.sync_to = gen6_ring_sync;
2707 ring->semaphore.signal = gen6_signal;
2708 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2709 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2710 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2711 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2712 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2713 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2714 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2715 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2716 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2717 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2718 }
abd58f01 2719 }
ecfe00d8 2720 ring->init_hw = init_ring_common;
9a8a2213
BW		 2721
2722 return intel_init_ring_buffer(dev, ring);
2723}
2724
a7b9761d 2725int
a4872ba6 2726intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2727{
2728 int ret;
2729
2730 if (!ring->gpu_caches_dirty)
2731 return 0;
2732
2733 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2734 if (ret)
2735 return ret;
2736
2737 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2738
2739 ring->gpu_caches_dirty = false;
2740 return 0;
2741}
2742
2743int
a4872ba6 2744intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2745{
2746 uint32_t flush_domains;
2747 int ret;
2748
2749 flush_domains = 0;
2750 if (ring->gpu_caches_dirty)
2751 flush_domains = I915_GEM_GPU_DOMAINS;
2752
2753 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2754 if (ret)
2755 return ret;
2756
2757 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2758
2759 ring->gpu_caches_dirty = false;
2760 return 0;
2761}
e3efda49
CW		 2762
2763void
a4872ba6 2764intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2765{
2766 int ret;
2767
2768 if (!intel_ring_initialized(ring))
2769 return;
2770
2771 ret = intel_ring_idle(ring);
2772 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2773 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2774 ring->name, ret);
2775
2776 stop_ring(ring);
2777}
Linux kernel - Deliverables
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