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drm/i915: Reserve ring buffer space for i915_add_request() commands
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
4772eaeb 320static int
a4872ba6 321gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 322 u32 invalidate_domains, u32 flush_domains)
323{
324 u32 flags = 0;
18393f63 325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 326 int ret;
327
f3987631
PZ		 328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
4772eaeb
PZ		 338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 345 }
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 354 /*
355 * TLB invalidate requires a post-sync write.
356 */
357 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 359
add284a3
CW		 360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
361
f3987631
PZ		 362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 366 }
367
368 ret = intel_ring_begin(ring, 4);
369 if (ret)
370 return ret;
371
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
b9e1faa7 374 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
377
378 return 0;
379}
380
884ceace
KG		 381static int
382gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
384{
385 int ret;
386
387 ret = intel_ring_begin(ring, 6);
388 if (ret)
389 return ret;
390
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
398
399 return 0;
400}
401
a5f3d68e 402static int
a4872ba6 403gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 404 u32 invalidate_domains, u32 flush_domains)
405{
406 u32 flags = 0;
18393f63 407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 408 int ret;
a5f3d68e
BW		 409
410 flags |= PIPE_CONTROL_CS_STALL;
411
412 if (flush_domains) {
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
415 }
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 425
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
430 0);
431 if (ret)
432 return ret;
a5f3d68e
BW		 433 }
434
6e0b3f8d 435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
a5f3d68e
BW		 436}
437
a4872ba6 438static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 439 u32 value)
d46eefa2 440{
4640c4ff 441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 442 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 443}
444
a4872ba6 445u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 448 u64 acthd;
8187a2b7 449
50877445
CW		 450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
455 else
456 acthd = I915_READ(ACTHD);
457
458 return acthd;
8187a2b7
ZN		 459}
460
a4872ba6 461static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 462{
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
464 u32 addr;
465
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
470}
471
af75f269
DL		 472static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
473{
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
476 u32 mmio = 0;
477
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
480 */
481 if (IS_GEN7(dev)) {
482 switch (ring->id) {
483 case RCS:
484 mmio = RENDER_HWS_PGA_GEN7;
485 break;
486 case BCS:
487 mmio = BLT_HWS_PGA_GEN7;
488 break;
489 /*
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
492 */
493 case VCS2:
494 case VCS:
495 mmio = BSD_HWS_PGA_GEN7;
496 break;
497 case VECS:
498 mmio = VEBOX_HWS_PGA_GEN7;
499 break;
500 }
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
503 } else {
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
506 }
507
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
509 POSTING_READ(mmio);
510
511 /*
512 * Flush the TLB for this page
513 *
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
517 */
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
520
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
523
524 I915_WRITE(reg,
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
526 INSTPM_SYNC_FLUSH));
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
528 1000))
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
530 ring->name);
531 }
532}
533
a4872ba6 534static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 535{
9991ae78 536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 537
9991ae78
CW		 538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
545 */
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
547 return false;
9991ae78
CW		 548 }
549 }
b7884eb4 550
7f2ab699 551 I915_WRITE_CTL(ring, 0);
570ef608 552 I915_WRITE_HEAD(ring, 0);
78501eac 553 ring->write_tail(ring, 0);
8187a2b7 554
9991ae78
CW		 555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
558 }
a51435a3 559
9991ae78
CW		 560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
561}
8187a2b7 562
a4872ba6 563static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 564{
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 569 int ret = 0;
570
59bad947 571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 572
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 ring->name,
578 I915_READ_CTL(ring),
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
8187a2b7 582
9991ae78 583 if (!stop_ring(ring)) {
6fd0d56e
CW		 584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 ring->name,
587 I915_READ_CTL(ring),
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
9991ae78
CW		 591 ret = -EIO;
592 goto out;
6fd0d56e 593 }
8187a2b7
ZN		 594 }
595
9991ae78
CW		 596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
598 else
599 ring_setup_phys_status_page(ring);
600
ece4a17d
JK		 601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
603
0d8957c8
DV		 604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
f343c5f6 608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
616
7f2ab699 617 I915_WRITE_CTL(ring,
93b0a4e0 618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 619 | RING_VALID);
8187a2b7 620
8187a2b7 621 /* If the head is still not zero, the ring is dead */
f01db988 622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 625 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 ring->name,
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 631 ret = -EIO;
632 goto out;
8187a2b7
ZN		 633 }
634
ebd0fd4b 635 ringbuf->last_retired_head = -1;
5c6c6003
CW		 636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 638 intel_ring_update_space(ringbuf);
1ec14ad3 639
50f018df
CW		 640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
641
b7884eb4 642out:
59bad947 643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 644
645 return ret;
8187a2b7
ZN		 646}
647
9b1136d5
OM		 648void
649intel_fini_pipe_control(struct intel_engine_cs *ring)
650{
651 struct drm_device *dev = ring->dev;
652
653 if (ring->scratch.obj == NULL)
654 return;
655
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(sg_page(ring->scratch.obj->pages->sgl));
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
659 }
660
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
663}
664
665int
666intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 667{
c6df541c
CW		 668 int ret;
669
bfc882b4 670 WARN_ON(ring->scratch.obj);
c6df541c 671
0d1aacac
CW		 672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
c6df541c
CW		 674 DRM_ERROR("Failed to allocate seqno page\n");
675 ret = -ENOMEM;
676 goto err;
677 }
e4ffd173 678
a9cc726c
DV		 679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
680 if (ret)
681 goto err_unref;
c6df541c 682
1ec9e26d 683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 684 if (ret)
685 goto err_unref;
686
0d1aacac
CW		 687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
689 if (ring->scratch.cpu_page == NULL) {
56b085a0 690 ret = -ENOMEM;
c6df541c 691 goto err_unpin;
56b085a0 692 }
c6df541c 693
2b1086cc 694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 695 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 696 return 0;
697
698err_unpin:
d7f46fc4 699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 700err_unref:
0d1aacac 701 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 702err:
c6df541c
CW		 703 return ret;
704}
705
771b9a53
MT		 706static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
86d7f238 708{
7225342a 709 int ret, i;
888b5995
AS		 710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 712 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 713
e6c1abb7 714 if (WARN_ON_ONCE(w->count == 0))
7225342a 715 return 0;
888b5995 716
7225342a
MK		 717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
719 if (ret)
720 return ret;
888b5995 721
22a916aa 722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 723 if (ret)
724 return ret;
725
22a916aa 726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 727 for (i = 0; i < w->count; i++) {
7225342a
MK		 728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
730 }
22a916aa 731 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 732
733 intel_ring_advance(ring);
734
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
737 if (ret)
738 return ret;
888b5995 739
7225342a 740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 741
7225342a 742 return 0;
86d7f238
AS		 743}
744
8f0e2b9d
DV		 745static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
747{
748 int ret;
749
750 ret = intel_ring_workarounds_emit(ring, ctx);
751 if (ret != 0)
752 return ret;
753
754 ret = i915_gem_render_state_init(ring);
755 if (ret)
756 DRM_ERROR("init render state: %d\n", ret);
757
758 return ret;
759}
760
7225342a 761static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 762 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 763{
764 const u32 idx = dev_priv->workarounds.count;
765
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
767 return -ENOSPC;
768
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
772
773 dev_priv->workarounds.count++;
774
775 return 0;
86d7f238
AS		 776}
777
cf4b0de6
DL		 778#define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 780 if (r) \
781 return r; \
782 }
783
784#define WA_SET_BIT_MASKED(addr, mask) \
26459343 785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 786
787#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 789
98533251 790#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 792
cf4b0de6
DL		 793#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 795
cf4b0de6 796#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 797
00e1e623 798static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 799{
888b5995
AS		 800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 802
9cc83020
VS		 803 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
804
2441f877
VS		 805 /* WaDisableAsyncFlipPerfMode:bdw */
806 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
807
86d7f238 808 /* WaDisablePartialInstShootdown:bdw */
101b376d 809 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 810 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
811 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
812 STALL_DOP_GATING_DISABLE);
86d7f238 813
101b376d 814 /* WaDisableDopClockGating:bdw */
7225342a
MK		 815 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
816 DOP_CLOCK_GATING_DISABLE);
86d7f238 817
7225342a
MK		 818 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
819 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 820
821 /* Use Force Non-Coherent whenever executing a 3D context. This is a
822 * workaround for for a possible hang in the unlikely event a TLB
823 * invalidation occurs during a PSD flush.
824 */
7225342a 825 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 826 /* WaForceEnableNonCoherent:bdw */
7225342a 827 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 828 /* WaForceContextSaveRestoreNonCoherent:bdw */
829 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
830 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 831 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 832 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 833 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 834
2701fc43
KG		 835 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
836 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
837 * polygons in the same 8x4 pixel/sample area to be processed without
838 * stalling waiting for the earlier ones to write to Hierarchical Z
839 * buffer."
840 *
841 * This optimization is off by default for Broadwell; turn it on.
842 */
843 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
844
86d7f238 845 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 846 WA_SET_BIT_MASKED(CACHE_MODE_1,
847 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 848
849 /*
850 * BSpec recommends 8x4 when MSAA is used,
851 * however in practice 16x4 seems fastest.
852 *
853 * Note that PS/WM thread counts depend on the WIZ hashing
854 * disable bit, which we don't touch here, but it's good
855 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
856 */
98533251
DL		 857 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
858 GEN6_WIZ_HASHING_MASK,
859 GEN6_WIZ_HASHING_16x4);
888b5995 860
86d7f238
AS		 861 return 0;
862}
863
00e1e623
VS		 864static int chv_init_workarounds(struct intel_engine_cs *ring)
865{
00e1e623
VS		 866 struct drm_device *dev = ring->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
868
9cc83020
VS		 869 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
870
2441f877
VS		 871 /* WaDisableAsyncFlipPerfMode:chv */
872 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
873
00e1e623 874 /* WaDisablePartialInstShootdown:chv */
00e1e623 875 /* WaDisableThreadStallDopClockGating:chv */
7225342a 876 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 877 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
878 STALL_DOP_GATING_DISABLE);
00e1e623 879
95289009
AS		 880 /* Use Force Non-Coherent whenever executing a 3D context. This is a
881 * workaround for a possible hang in the unlikely event a TLB
882 * invalidation occurs during a PSD flush.
883 */
884 /* WaForceEnableNonCoherent:chv */
885 /* WaHdcDisableFetchWhenMasked:chv */
886 WA_SET_BIT_MASKED(HDC_CHICKEN0,
887 HDC_FORCE_NON_COHERENT |
888 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
889
973a5b06
KG		 890 /* According to the CACHE_MODE_0 default value documentation, some
891 * CHV platforms disable this optimization by default. Turn it on.
892 */
893 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
894
14bc16e3
VS		 895 /* Wa4x4STCOptimizationDisable:chv */
896 WA_SET_BIT_MASKED(CACHE_MODE_1,
897 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
898
d60de81d
KG		 899 /* Improve HiZ throughput on CHV. */
900 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
901
e7fc2436
VS		 902 /*
903 * BSpec recommends 8x4 when MSAA is used,
904 * however in practice 16x4 seems fastest.
905 *
906 * Note that PS/WM thread counts depend on the WIZ hashing
907 * disable bit, which we don't touch here, but it's good
908 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
909 */
910 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
911 GEN6_WIZ_HASHING_MASK,
912 GEN6_WIZ_HASHING_16x4);
913
7225342a
MK		 914 return 0;
915}
916
3b106531
HN		 917static int gen9_init_workarounds(struct intel_engine_cs *ring)
918{
ab0dfafe
HN		 919 struct drm_device *dev = ring->dev;
920 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 921 uint32_t tmp;
ab0dfafe 922
b0e6f6d4 923 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
926
a119a6e6 927 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
930
d2a31dbd
NH		 931 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
932 INTEL_REVID(dev) == SKL_REVID_B0)) ||
933 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
934 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 935 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
936 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 937 }
938
a13d215f
NH		 939 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
940 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
941 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 942 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
943 GEN9_RHWO_OPTIMIZATION_DISABLE);
944 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
945 DISABLE_PIXEL_MASK_CAMMING);
946 }
947
27a1b688
NH		 948 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
949 IS_BROXTON(dev)) {
950 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
952 GEN9_ENABLE_YV12_BUGFIX);
953 }
954
5068368c 955 /* Wa4x4STCOptimizationDisable:skl,bxt */
1840481f
HN		 956 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
957
27160c96 958 /* WaDisablePartialResolveInVc:skl,bxt */
9370cd98
DL		 959 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
960
16be17af 961 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 962 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
963 GEN9_CCS_TLB_PREFETCH_ENABLE);
964
5a2ae95e
ID		 965 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
966 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
967 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 968 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
969 PIXEL_MASK_CAMMING_DISABLE);
970
8ea6f892
ID		 971 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
972 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
973 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
974 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
975 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
976 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
977
3b106531
HN		 978 return 0;
979}
980
b7668791
DL		 981static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
982{
983 struct drm_device *dev = ring->dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u8 vals[3] = { 0, 0, 0 };
986 unsigned int i;
987
988 for (i = 0; i < 3; i++) {
989 u8 ss;
990
991 /*
992 * Only consider slices where one, and only one, subslice has 7
993 * EUs
994 */
995 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
996 continue;
997
998 /*
999 * subslice_7eu[i] != 0 (because of the check above) and
1000 * ss_max == 4 (maximum number of subslices possible per slice)
1001 *
1002 * -> 0 <= ss <= 3;
1003 */
1004 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1005 vals[i] = 3 - ss;
1006 }
1007
1008 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1009 return 0;
1010
1011 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1013 GEN9_IZ_HASHING_MASK(2) |
1014 GEN9_IZ_HASHING_MASK(1) |
1015 GEN9_IZ_HASHING_MASK(0),
1016 GEN9_IZ_HASHING(2, vals[2]) |
1017 GEN9_IZ_HASHING(1, vals[1]) |
1018 GEN9_IZ_HASHING(0, vals[0]));
1019
1020 return 0;
1021}
1022
1023
8d205494
DL		 1024static int skl_init_workarounds(struct intel_engine_cs *ring)
1025{
d0bbbc4f
DL		 1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028
8d205494
DL		 1029 gen9_init_workarounds(ring);
1030
d0bbbc4f
DL		 1031 /* WaDisablePowerCompilerClockGating:skl */
1032 if (INTEL_REVID(dev) == SKL_REVID_B0)
1033 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1034 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1035
b62adbd1
NH		 1036 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1037 /*
1038 *Use Force Non-Coherent whenever executing a 3D context. This
1039 * is a workaround for a possible hang in the unlikely event
1040 * a TLB invalidation occurs during a PSD flush.
1041 */
1042 /* WaForceEnableNonCoherent:skl */
1043 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1044 HDC_FORCE_NON_COHERENT);
1045 }
1046
5b6fd12a
VS		 1047 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1048 INTEL_REVID(dev) == SKL_REVID_D0)
1049 /* WaBarrierPerformanceFixDisable:skl */
1050 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1051 HDC_FENCE_DEST_SLM_DISABLE |
1052 HDC_BARRIER_PERFORMANCE_DISABLE);
1053
b7668791 1054 return skl_tune_iz_hashing(ring);
7225342a
MK		 1055}
1056
cae0437f
NH		 1057static int bxt_init_workarounds(struct intel_engine_cs *ring)
1058{
dfb601e6
NH		 1059 struct drm_device *dev = ring->dev;
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1061
cae0437f
NH		 1062 gen9_init_workarounds(ring);
1063
dfb601e6
NH		 1064 /* WaDisableThreadStallDopClockGating:bxt */
1065 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1066 STALL_DOP_GATING_DISABLE);
1067
983b4b9d
NH		 1068 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1069 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1070 WA_SET_BIT_MASKED(
1071 GEN7_HALF_SLICE_CHICKEN1,
1072 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1073 }
1074
cae0437f
NH		 1075 return 0;
1076}
1077
771b9a53 1078int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1079{
1080 struct drm_device *dev = ring->dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082
1083 WARN_ON(ring->id != RCS);
1084
1085 dev_priv->workarounds.count = 0;
1086
1087 if (IS_BROADWELL(dev))
1088 return bdw_init_workarounds(ring);
1089
1090 if (IS_CHERRYVIEW(dev))
1091 return chv_init_workarounds(ring);
00e1e623 1092
8d205494
DL		 1093 if (IS_SKYLAKE(dev))
1094 return skl_init_workarounds(ring);
cae0437f
NH		 1095
1096 if (IS_BROXTON(dev))
1097 return bxt_init_workarounds(ring);
3b106531 1098
00e1e623
VS		 1099 return 0;
1100}
1101
a4872ba6 1102static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1103{
78501eac 1104 struct drm_device *dev = ring->dev;
1ec14ad3 1105 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1106 int ret = init_ring_common(ring);
9c33baa6
KZ		 1107 if (ret)
1108 return ret;
a69ffdbf 1109
61a563a2
AG		 1110 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1111 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1112 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1113
1114 /* We need to disable the AsyncFlip performance optimisations in order
1115 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1116 * programmed to '1' on all products.
8693a824 1117 *
2441f877 1118 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1119 */
2441f877 1120 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1121 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1122
f05bb0c7 1123 /* Required for the hardware to program scanline values for waiting */
01fa0302 1124 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1125 if (INTEL_INFO(dev)->gen == 6)
1126 I915_WRITE(GFX_MODE,
aa83e30d 1127 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1128
01fa0302 1129 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1130 if (IS_GEN7(dev))
1131 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1132 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1133 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1134
5e13a0c5 1135 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1136 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1137 * "If this bit is set, STCunit will have LRA as replacement
1138 * policy. [...] This bit must be reset. LRA replacement
1139 * policy is not supported."
1140 */
1141 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1142 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1143 }
1144
9cc83020 1145 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1146 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1147
040d2baa 1148 if (HAS_L3_DPF(dev))
35a85ac6 1149 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1150
7225342a 1151 return init_workarounds_ring(ring);
8187a2b7
ZN		 1152}
1153
a4872ba6 1154static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1155{
b45305fc 1156 struct drm_device *dev = ring->dev;
3e78998a
BW		 1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158
1159 if (dev_priv->semaphore_obj) {
1160 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1161 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1162 dev_priv->semaphore_obj = NULL;
1163 }
b45305fc 1164
9b1136d5 1165 intel_fini_pipe_control(ring);
c6df541c
CW		 1166}
1167
3e78998a
BW		 1168static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1169 unsigned int num_dwords)
1170{
1171#define MBOX_UPDATE_DWORDS 8
1172 struct drm_device *dev = signaller->dev;
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 struct intel_engine_cs *waiter;
1175 int i, ret, num_rings;
1176
1177 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1178 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1179#undef MBOX_UPDATE_DWORDS
1180
1181 ret = intel_ring_begin(signaller, num_dwords);
1182 if (ret)
1183 return ret;
1184
1185 for_each_ring(waiter, dev_priv, i) {
6259cead 1186 u32 seqno;
3e78998a
BW		 1187 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1188 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1189 continue;
1190
6259cead
JH		 1191 seqno = i915_gem_request_get_seqno(
1192 signaller->outstanding_lazy_request);
3e78998a
BW		 1193 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1194 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1195 PIPE_CONTROL_QW_WRITE |
1196 PIPE_CONTROL_FLUSH_ENABLE);
1197 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1198 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1199 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1200 intel_ring_emit(signaller, 0);
1201 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1202 MI_SEMAPHORE_TARGET(waiter->id));
1203 intel_ring_emit(signaller, 0);
1204 }
1205
1206 return 0;
1207}
1208
1209static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1210 unsigned int num_dwords)
1211{
1212#define MBOX_UPDATE_DWORDS 6
1213 struct drm_device *dev = signaller->dev;
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 struct intel_engine_cs *waiter;
1216 int i, ret, num_rings;
1217
1218 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1219 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1220#undef MBOX_UPDATE_DWORDS
1221
1222 ret = intel_ring_begin(signaller, num_dwords);
1223 if (ret)
1224 return ret;
1225
1226 for_each_ring(waiter, dev_priv, i) {
6259cead 1227 u32 seqno;
3e78998a
BW		 1228 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1229 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1230 continue;
1231
6259cead
JH		 1232 seqno = i915_gem_request_get_seqno(
1233 signaller->outstanding_lazy_request);
3e78998a
BW		 1234 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1235 MI_FLUSH_DW_OP_STOREDW);
1236 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1237 MI_FLUSH_DW_USE_GTT);
1238 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1239 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1240 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1241 MI_SEMAPHORE_TARGET(waiter->id));
1242 intel_ring_emit(signaller, 0);
1243 }
1244
1245 return 0;
1246}
1247
a4872ba6 1248static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1249 unsigned int num_dwords)
1ec14ad3 1250{
024a43e1
BW		 1251 struct drm_device *dev = signaller->dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1253 struct intel_engine_cs *useless;
a1444b79 1254 int i, ret, num_rings;
78325f2d 1255
a1444b79
BW		 1256#define MBOX_UPDATE_DWORDS 3
1257 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1258 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1259#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1260
1261 ret = intel_ring_begin(signaller, num_dwords);
1262 if (ret)
1263 return ret;
024a43e1 1264
78325f2d
BW		 1265 for_each_ring(useless, dev_priv, i) {
1266 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1267 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1268 u32 seqno = i915_gem_request_get_seqno(
1269 signaller->outstanding_lazy_request);
78325f2d
BW		 1270 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1271 intel_ring_emit(signaller, mbox_reg);
6259cead 1272 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1273 }
1274 }
024a43e1 1275
a1444b79
BW		 1276 /* If num_dwords was rounded, make sure the tail pointer is correct */
1277 if (num_rings % 2 == 0)
1278 intel_ring_emit(signaller, MI_NOOP);
1279
024a43e1 1280 return 0;
1ec14ad3
CW		 1281}
1282
c8c99b0f
BW		 1283/**
1284 * gen6_add_request - Update the semaphore mailbox registers
1285 *
1286 * @ring - ring that is adding a request
1287 * @seqno - return seqno stuck into the ring
1288 *
1289 * Update the mailbox registers in the *other* rings with the current seqno.
1290 * This acts like a signal in the canonical semaphore.
1291 */
1ec14ad3 1292static int
a4872ba6 1293gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1294{
024a43e1 1295 int ret;
52ed2325 1296
707d9cf9
BW		 1297 if (ring->semaphore.signal)
1298 ret = ring->semaphore.signal(ring, 4);
1299 else
1300 ret = intel_ring_begin(ring, 4);
1301
1ec14ad3
CW		 1302 if (ret)
1303 return ret;
1304
1ec14ad3
CW		 1305 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1306 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1307 intel_ring_emit(ring,
1308 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1309 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1310 __intel_ring_advance(ring);
1ec14ad3 1311
1ec14ad3
CW		 1312 return 0;
1313}
1314
f72b3435
MK		 1315static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1316 u32 seqno)
1317{
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 return dev_priv->last_seqno < seqno;
1320}
1321
c8c99b0f
BW		 1322/**
1323 * intel_ring_sync - sync the waiter to the signaller on seqno
1324 *
1325 * @waiter - ring that is waiting
1326 * @signaller - ring which has, or will signal
1327 * @seqno - seqno which the waiter will block on
1328 */
5ee426ca
BW		 1329
1330static int
1331gen8_ring_sync(struct intel_engine_cs *waiter,
1332 struct intel_engine_cs *signaller,
1333 u32 seqno)
1334{
1335 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1336 int ret;
1337
1338 ret = intel_ring_begin(waiter, 4);
1339 if (ret)
1340 return ret;
1341
1342 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1343 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1344 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1345 MI_SEMAPHORE_SAD_GTE_SDD);
1346 intel_ring_emit(waiter, seqno);
1347 intel_ring_emit(waiter,
1348 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1349 intel_ring_emit(waiter,
1350 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1351 intel_ring_advance(waiter);
1352 return 0;
1353}
1354
c8c99b0f 1355static int
a4872ba6
OM		 1356gen6_ring_sync(struct intel_engine_cs *waiter,
1357 struct intel_engine_cs *signaller,
686cb5f9 1358 u32 seqno)
1ec14ad3 1359{
c8c99b0f
BW		 1360 u32 dw1 = MI_SEMAPHORE_MBOX |
1361 MI_SEMAPHORE_COMPARE |
1362 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1363 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1364 int ret;
1ec14ad3 1365
1500f7ea
BW		 1366 /* Throughout all of the GEM code, seqno passed implies our current
1367 * seqno is >= the last seqno executed. However for hardware the
1368 * comparison is strictly greater than.
1369 */
1370 seqno -= 1;
1371
ebc348b2 1372 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1373
c8c99b0f 1374 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1375 if (ret)
1376 return ret;
1377
f72b3435
MK		 1378 /* If seqno wrap happened, omit the wait with no-ops */
1379 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1380 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1381 intel_ring_emit(waiter, seqno);
1382 intel_ring_emit(waiter, 0);
1383 intel_ring_emit(waiter, MI_NOOP);
1384 } else {
1385 intel_ring_emit(waiter, MI_NOOP);
1386 intel_ring_emit(waiter, MI_NOOP);
1387 intel_ring_emit(waiter, MI_NOOP);
1388 intel_ring_emit(waiter, MI_NOOP);
1389 }
c8c99b0f 1390 intel_ring_advance(waiter);
1ec14ad3
CW		 1391
1392 return 0;
1393}
1394
c6df541c
CW		 1395#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1396do { \
fcbc34e4
KG		 1397 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1398 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1399 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1400 intel_ring_emit(ring__, 0); \
1401 intel_ring_emit(ring__, 0); \
1402} while (0)
1403
1404static int
a4872ba6 1405pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1406{
18393f63 1407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1408 int ret;
1409
1410 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1411 * incoherent with writes to memory, i.e. completely fubar,
1412 * so we need to use PIPE_NOTIFY instead.
1413 *
1414 * However, we also need to workaround the qword write
1415 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1416 * memory before requesting an interrupt.
1417 */
1418 ret = intel_ring_begin(ring, 32);
1419 if (ret)
1420 return ret;
1421
fcbc34e4 1422 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1423 PIPE_CONTROL_WRITE_FLUSH |
1424 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1425 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1426 intel_ring_emit(ring,
1427 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1428 intel_ring_emit(ring, 0);
1429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1430 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1431 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1432 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1433 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1434 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1435 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1436 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1437 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1438 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1439 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1440
fcbc34e4 1441 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1442 PIPE_CONTROL_WRITE_FLUSH |
1443 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1444 PIPE_CONTROL_NOTIFY);
0d1aacac 1445 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1446 intel_ring_emit(ring,
1447 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1448 intel_ring_emit(ring, 0);
09246732 1449 __intel_ring_advance(ring);
c6df541c 1450
c6df541c
CW		 1451 return 0;
1452}
1453
4cd53c0c 1454static u32
a4872ba6 1455gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1456{
4cd53c0c
DV		 1457 /* Workaround to force correct ordering between irq and seqno writes on
1458 * ivb (and maybe also on snb) by reading from a CS register (like
1459 * ACTHD) before reading the status page. */
50877445
CW		 1460 if (!lazy_coherency) {
1461 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1462 POSTING_READ(RING_ACTHD(ring->mmio_base));
1463 }
1464
4cd53c0c
DV		 1465 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1466}
1467
8187a2b7 1468static u32
a4872ba6 1469ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1470{
1ec14ad3
CW		 1471 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1472}
1473
b70ec5bf 1474static void
a4872ba6 1475ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1476{
1477 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1478}
1479
c6df541c 1480static u32
a4872ba6 1481pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1482{
0d1aacac 1483 return ring->scratch.cpu_page[0];
c6df541c
CW		 1484}
1485
b70ec5bf 1486static void
a4872ba6 1487pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1488{
0d1aacac 1489 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1490}
1491
e48d8634 1492static bool
a4872ba6 1493gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1494{
1495 struct drm_device *dev = ring->dev;
4640c4ff 1496 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1497 unsigned long flags;
e48d8634 1498
7cd512f1 1499 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1500 return false;
1501
7338aefa 1502 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1503 if (ring->irq_refcount++ == 0)
480c8033 1504 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1505 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1506
1507 return true;
1508}
1509
1510static void
a4872ba6 1511gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1512{
1513 struct drm_device *dev = ring->dev;
4640c4ff 1514 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1515 unsigned long flags;
e48d8634 1516
7338aefa 1517 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1518 if (--ring->irq_refcount == 0)
480c8033 1519 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1520 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1521}
1522
b13c2b96 1523static bool
a4872ba6 1524i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1525{
78501eac 1526 struct drm_device *dev = ring->dev;
4640c4ff 1527 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1528 unsigned long flags;
62fdfeaf 1529
7cd512f1 1530 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1531 return false;
1532
7338aefa 1533 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1534 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1535 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1536 I915_WRITE(IMR, dev_priv->irq_mask);
1537 POSTING_READ(IMR);
1538 }
7338aefa 1539 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1540
1541 return true;
62fdfeaf
EA		 1542}
1543
8187a2b7 1544static void
a4872ba6 1545i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1546{
78501eac 1547 struct drm_device *dev = ring->dev;
4640c4ff 1548 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1549 unsigned long flags;
62fdfeaf 1550
7338aefa 1551 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1552 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1553 dev_priv->irq_mask |= ring->irq_enable_mask;
1554 I915_WRITE(IMR, dev_priv->irq_mask);
1555 POSTING_READ(IMR);
1556 }
7338aefa 1557 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1558}
1559
c2798b19 1560static bool
a4872ba6 1561i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1562{
1563 struct drm_device *dev = ring->dev;
4640c4ff 1564 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1565 unsigned long flags;
c2798b19 1566
7cd512f1 1567 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1568 return false;
1569
7338aefa 1570 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1571 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1572 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1573 I915_WRITE16(IMR, dev_priv->irq_mask);
1574 POSTING_READ16(IMR);
1575 }
7338aefa 1576 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1577
1578 return true;
1579}
1580
1581static void
a4872ba6 1582i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1583{
1584 struct drm_device *dev = ring->dev;
4640c4ff 1585 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1586 unsigned long flags;
c2798b19 1587
7338aefa 1588 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1589 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1590 dev_priv->irq_mask |= ring->irq_enable_mask;
1591 I915_WRITE16(IMR, dev_priv->irq_mask);
1592 POSTING_READ16(IMR);
1593 }
7338aefa 1594 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1595}
1596
b72f3acb 1597static int
a4872ba6 1598bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1599 u32 invalidate_domains,
1600 u32 flush_domains)
d1b851fc 1601{
b72f3acb
CW		 1602 int ret;
1603
b72f3acb
CW		 1604 ret = intel_ring_begin(ring, 2);
1605 if (ret)
1606 return ret;
1607
1608 intel_ring_emit(ring, MI_FLUSH);
1609 intel_ring_emit(ring, MI_NOOP);
1610 intel_ring_advance(ring);
1611 return 0;
d1b851fc
ZN		 1612}
1613
3cce469c 1614static int
a4872ba6 1615i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1616{
3cce469c
CW		 1617 int ret;
1618
1619 ret = intel_ring_begin(ring, 4);
1620 if (ret)
1621 return ret;
6f392d54 1622
3cce469c
CW		 1623 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1624 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1625 intel_ring_emit(ring,
1626 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1627 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1628 __intel_ring_advance(ring);
d1b851fc 1629
3cce469c 1630 return 0;
d1b851fc
ZN		 1631}
1632
0f46832f 1633static bool
a4872ba6 1634gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1635{
1636 struct drm_device *dev = ring->dev;
4640c4ff 1637 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1638 unsigned long flags;
0f46832f 1639
7cd512f1
DV		 1640 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1641 return false;
0f46832f 1642
7338aefa 1643 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1644 if (ring->irq_refcount++ == 0) {
040d2baa 1645 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1646 I915_WRITE_IMR(ring,
1647 ~(ring->irq_enable_mask |
35a85ac6 1648 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1649 else
1650 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1651 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1652 }
7338aefa 1653 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1654
1655 return true;
1656}
1657
1658static void
a4872ba6 1659gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1660{
1661 struct drm_device *dev = ring->dev;
4640c4ff 1662 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1663 unsigned long flags;
0f46832f 1664
7338aefa 1665 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1666 if (--ring->irq_refcount == 0) {
040d2baa 1667 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1668 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1669 else
1670 I915_WRITE_IMR(ring, ~0);
480c8033 1671 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1672 }
7338aefa 1673 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1674}
1675
a19d2933 1676static bool
a4872ba6 1677hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1678{
1679 struct drm_device *dev = ring->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 unsigned long flags;
1682
7cd512f1 1683 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1684 return false;
1685
59cdb63d 1686 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1687 if (ring->irq_refcount++ == 0) {
a19d2933 1688 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1689 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1690 }
59cdb63d 1691 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1692
1693 return true;
1694}
1695
1696static void
a4872ba6 1697hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1698{
1699 struct drm_device *dev = ring->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 unsigned long flags;
1702
59cdb63d 1703 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1704 if (--ring->irq_refcount == 0) {
a19d2933 1705 I915_WRITE_IMR(ring, ~0);
480c8033 1706 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1707 }
59cdb63d 1708 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1709}
1710
abd58f01 1711static bool
a4872ba6 1712gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1713{
1714 struct drm_device *dev = ring->dev;
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 unsigned long flags;
1717
7cd512f1 1718 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1719 return false;
1720
1721 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1722 if (ring->irq_refcount++ == 0) {
1723 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1724 I915_WRITE_IMR(ring,
1725 ~(ring->irq_enable_mask |
1726 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1727 } else {
1728 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1729 }
1730 POSTING_READ(RING_IMR(ring->mmio_base));
1731 }
1732 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1733
1734 return true;
1735}
1736
1737static void
a4872ba6 1738gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1739{
1740 struct drm_device *dev = ring->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 unsigned long flags;
1743
1744 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1745 if (--ring->irq_refcount == 0) {
1746 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1747 I915_WRITE_IMR(ring,
1748 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1749 } else {
1750 I915_WRITE_IMR(ring, ~0);
1751 }
1752 POSTING_READ(RING_IMR(ring->mmio_base));
1753 }
1754 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1755}
1756
d1b851fc 1757static int
a4872ba6 1758i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1759 u64 offset, u32 length,
8e004efc 1760 unsigned dispatch_flags)
d1b851fc 1761{
e1f99ce6 1762 int ret;
78501eac 1763
e1f99ce6
CW		 1764 ret = intel_ring_begin(ring, 2);
1765 if (ret)
1766 return ret;
1767
78501eac 1768 intel_ring_emit(ring,
65f56876
CW		 1769 MI_BATCH_BUFFER_START |
1770 MI_BATCH_GTT |
8e004efc
JH		 1771 (dispatch_flags & I915_DISPATCH_SECURE ?
1772 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1773 intel_ring_emit(ring, offset);
78501eac
CW		 1774 intel_ring_advance(ring);
1775
d1b851fc
ZN		 1776 return 0;
1777}
1778
b45305fc
DV		 1779/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1780#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1781#define I830_TLB_ENTRIES (2)
1782#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1783static int
a4872ba6 1784i830_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 1785 u64 offset, u32 len,
1786 unsigned dispatch_flags)
62fdfeaf 1787{
c4d69da1 1788 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1789 int ret;
62fdfeaf 1790
c4d69da1
CW		 1791 ret = intel_ring_begin(ring, 6);
1792 if (ret)
1793 return ret;
62fdfeaf 1794
c4d69da1
CW		 1795 /* Evict the invalid PTE TLBs */
1796 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1797 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1798 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1799 intel_ring_emit(ring, cs_offset);
1800 intel_ring_emit(ring, 0xdeadbeef);
1801 intel_ring_emit(ring, MI_NOOP);
1802 intel_ring_advance(ring);
b45305fc 1803
8e004efc 1804 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1805 if (len > I830_BATCH_LIMIT)
1806 return -ENOSPC;
1807
c4d69da1 1808 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1809 if (ret)
1810 return ret;
c4d69da1
CW		 1811
1812 /* Blit the batch (which has now all relocs applied) to the
1813 * stable batch scratch bo area (so that the CS never
1814 * stumbles over its tlb invalidation bug) ...
1815 */
1816 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1817 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1818 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1819 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1820 intel_ring_emit(ring, 4096);
1821 intel_ring_emit(ring, offset);
c4d69da1 1822
b45305fc 1823 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1824 intel_ring_emit(ring, MI_NOOP);
1825 intel_ring_advance(ring);
b45305fc
DV		 1826
1827 /* ... and execute it. */
c4d69da1 1828 offset = cs_offset;
b45305fc 1829 }
e1f99ce6 1830
c4d69da1
CW		 1831 ret = intel_ring_begin(ring, 4);
1832 if (ret)
1833 return ret;
1834
1835 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1836 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1837 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1838 intel_ring_emit(ring, offset + len - 8);
1839 intel_ring_emit(ring, MI_NOOP);
1840 intel_ring_advance(ring);
1841
fb3256da
DV		 1842 return 0;
1843}
1844
1845static int
a4872ba6 1846i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1847 u64 offset, u32 len,
8e004efc 1848 unsigned dispatch_flags)
fb3256da
DV		 1849{
1850 int ret;
1851
1852 ret = intel_ring_begin(ring, 2);
1853 if (ret)
1854 return ret;
1855
65f56876 1856 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1857 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1858 0 : MI_BATCH_NON_SECURE));
c4e7a414 1859 intel_ring_advance(ring);
62fdfeaf 1860
62fdfeaf
EA		 1861 return 0;
1862}
1863
a4872ba6 1864static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1865{
05394f39 1866 struct drm_i915_gem_object *obj;
62fdfeaf 1867
8187a2b7
ZN		 1868 obj = ring->status_page.obj;
1869 if (obj == NULL)
62fdfeaf 1870 return;
62fdfeaf 1871
9da3da66 1872 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1873 i915_gem_object_ggtt_unpin(obj);
05394f39 1874 drm_gem_object_unreference(&obj->base);
8187a2b7 1875 ring->status_page.obj = NULL;
62fdfeaf
EA		 1876}
1877
a4872ba6 1878static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1879{
05394f39 1880 struct drm_i915_gem_object *obj;
62fdfeaf 1881
e3efda49 1882 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1883 unsigned flags;
e3efda49 1884 int ret;
e4ffd173 1885
e3efda49
CW		 1886 obj = i915_gem_alloc_object(ring->dev, 4096);
1887 if (obj == NULL) {
1888 DRM_ERROR("Failed to allocate status page\n");
1889 return -ENOMEM;
1890 }
62fdfeaf 1891
e3efda49
CW		 1892 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1893 if (ret)
1894 goto err_unref;
1895
1f767e02
CW		 1896 flags = 0;
1897 if (!HAS_LLC(ring->dev))
1898 /* On g33, we cannot place HWS above 256MiB, so
1899 * restrict its pinning to the low mappable arena.
1900 * Though this restriction is not documented for
1901 * gen4, gen5, or byt, they also behave similarly
1902 * and hang if the HWS is placed at the top of the
1903 * GTT. To generalise, it appears that all !llc
1904 * platforms have issues with us placing the HWS
1905 * above the mappable region (even though we never
1906 * actualy map it).
1907 */
1908 flags |= PIN_MAPPABLE;
1909 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1910 if (ret) {
1911err_unref:
1912 drm_gem_object_unreference(&obj->base);
1913 return ret;
1914 }
1915
1916 ring->status_page.obj = obj;
1917 }
62fdfeaf 1918
f343c5f6 1919 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1920 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1921 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1922
8187a2b7
ZN		 1923 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1924 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1925
1926 return 0;
62fdfeaf
EA		 1927}
1928
a4872ba6 1929static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1930{
1931 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1932
1933 if (!dev_priv->status_page_dmah) {
1934 dev_priv->status_page_dmah =
1935 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1936 if (!dev_priv->status_page_dmah)
1937 return -ENOMEM;
1938 }
1939
6b8294a4
CW		 1940 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1941 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1942
1943 return 0;
1944}
1945
7ba717cf 1946void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1947{
2919d291 1948 iounmap(ringbuf->virtual_start);
7ba717cf 1949 ringbuf->virtual_start = NULL;
2919d291 1950 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1951}
1952
1953int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1954 struct intel_ringbuffer *ringbuf)
1955{
1956 struct drm_i915_private *dev_priv = to_i915(dev);
1957 struct drm_i915_gem_object *obj = ringbuf->obj;
1958 int ret;
1959
1960 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1961 if (ret)
1962 return ret;
1963
1964 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1965 if (ret) {
1966 i915_gem_object_ggtt_unpin(obj);
1967 return ret;
1968 }
1969
1970 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1971 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1972 if (ringbuf->virtual_start == NULL) {
1973 i915_gem_object_ggtt_unpin(obj);
1974 return -EINVAL;
1975 }
1976
1977 return 0;
1978}
1979
1980void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1981{
2919d291
OM		 1982 drm_gem_object_unreference(&ringbuf->obj->base);
1983 ringbuf->obj = NULL;
1984}
1985
84c2377f
OM		 1986int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1987 struct intel_ringbuffer *ringbuf)
62fdfeaf 1988{
05394f39 1989 struct drm_i915_gem_object *obj;
62fdfeaf 1990
ebc052e0
CW		 1991 obj = NULL;
1992 if (!HAS_LLC(dev))
93b0a4e0 1993 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1994 if (obj == NULL)
93b0a4e0 1995 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1996 if (obj == NULL)
1997 return -ENOMEM;
8187a2b7 1998
24f3a8cf
AG		 1999 /* mark ring buffers as read-only from GPU side by default */
2000 obj->gt_ro = 1;
2001
93b0a4e0 2002 ringbuf->obj = obj;
e3efda49 2003
7ba717cf 2004 return 0;
e3efda49
CW		 2005}
2006
2007static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2008 struct intel_engine_cs *ring)
e3efda49 2009{
bfc882b4 2010 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2011 int ret;
2012
bfc882b4
DV		 2013 WARN_ON(ring->buffer);
2014
2015 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2016 if (!ringbuf)
2017 return -ENOMEM;
2018 ring->buffer = ringbuf;
8ee14975 2019
e3efda49
CW		 2020 ring->dev = dev;
2021 INIT_LIST_HEAD(&ring->active_list);
2022 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2023 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2024 i915_gem_batch_pool_init(dev, &ring->batch_pool);
93b0a4e0 2025 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2026 ringbuf->ring = ring;
ebc348b2 2027 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2028
2029 init_waitqueue_head(&ring->irq_queue);
2030
2031 if (I915_NEED_GFX_HWS(dev)) {
2032 ret = init_status_page(ring);
2033 if (ret)
8ee14975 2034 goto error;
e3efda49
CW		 2035 } else {
2036 BUG_ON(ring->id != RCS);
2037 ret = init_phys_status_page(ring);
2038 if (ret)
8ee14975 2039 goto error;
e3efda49
CW		 2040 }
2041
bfc882b4 2042 WARN_ON(ringbuf->obj);
7ba717cf 2043
bfc882b4
DV		 2044 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2045 if (ret) {
2046 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2047 ring->name, ret);
2048 goto error;
2049 }
2050
2051 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2052 if (ret) {
2053 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2054 ring->name, ret);
2055 intel_destroy_ringbuffer_obj(ringbuf);
2056 goto error;
e3efda49 2057 }
62fdfeaf 2058
55249baa
CW		 2059 /* Workaround an erratum on the i830 which causes a hang if
2060 * the TAIL pointer points to within the last 2 cachelines
2061 * of the buffer.
2062 */
93b0a4e0 2063 ringbuf->effective_size = ringbuf->size;
e3efda49 2064 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2065 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2066
44e895a8
BV		 2067 ret = i915_cmd_parser_init_ring(ring);
2068 if (ret)
8ee14975
OM		 2069 goto error;
2070
8ee14975 2071 return 0;
351e3db2 2072
8ee14975
OM		 2073error:
2074 kfree(ringbuf);
2075 ring->buffer = NULL;
2076 return ret;
62fdfeaf
EA		 2077}
2078
a4872ba6 2079void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2080{
6402c330
JH		 2081 struct drm_i915_private *dev_priv;
2082 struct intel_ringbuffer *ringbuf;
33626e6a 2083
93b0a4e0 2084 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2085 return;
2086
6402c330
JH		 2087 dev_priv = to_i915(ring->dev);
2088 ringbuf = ring->buffer;
2089
e3efda49 2090 intel_stop_ring_buffer(ring);
de8f0a50 2091 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2092
7ba717cf 2093 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2094 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2095 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2096
8d19215b
ZN		 2097 if (ring->cleanup)
2098 ring->cleanup(ring);
2099
78501eac 2100 cleanup_status_page(ring);
44e895a8
BV		 2101
2102 i915_cmd_parser_fini_ring(ring);
06fbca71 2103 i915_gem_batch_pool_fini(&ring->batch_pool);
8ee14975 2104
93b0a4e0 2105 kfree(ringbuf);
8ee14975 2106 ring->buffer = NULL;
62fdfeaf
EA		 2107}
2108
595e1eeb 2109static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2110{
93b0a4e0 2111 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2112 struct drm_i915_gem_request *request;
b4716185
CW		 2113 unsigned space;
2114 int ret;
a71d8d94 2115
29b1b415
JH		 2116 /* The whole point of reserving space is to not wait! */
2117 WARN_ON(ringbuf->reserved_in_use);
2118
ebd0fd4b
DG		 2119 if (intel_ring_space(ringbuf) >= n)
2120 return 0;
a71d8d94
CW		 2121
2122 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2123 space = __intel_ring_space(request->postfix, ringbuf->tail,
2124 ringbuf->size);
2125 if (space >= n)
a71d8d94 2126 break;
a71d8d94
CW		 2127 }
2128
595e1eeb 2129 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2130 return -ENOSPC;
2131
a4b3a571 2132 ret = i915_wait_request(request);
a71d8d94
CW		 2133 if (ret)
2134 return ret;
2135
b4716185 2136 ringbuf->space = space;
a71d8d94
CW		 2137 return 0;
2138}
2139
a4872ba6 2140static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2141{
2142 uint32_t __iomem *virt;
93b0a4e0
OM		 2143 struct intel_ringbuffer *ringbuf = ring->buffer;
2144 int rem = ringbuf->size - ringbuf->tail;
3e960501 2145
29b1b415
JH		 2146 /* Can't wrap if space has already been reserved! */
2147 WARN_ON(ringbuf->reserved_in_use);
2148
93b0a4e0 2149 if (ringbuf->space < rem) {
3e960501
CW		 2150 int ret = ring_wait_for_space(ring, rem);
2151 if (ret)
2152 return ret;
2153 }
2154
93b0a4e0 2155 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2156 rem /= 4;
2157 while (rem--)
2158 iowrite32(MI_NOOP, virt++);
2159
93b0a4e0 2160 ringbuf->tail = 0;
ebd0fd4b 2161 intel_ring_update_space(ringbuf);
3e960501
CW		 2162
2163 return 0;
2164}
2165
a4872ba6 2166int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2167{
a4b3a571 2168 struct drm_i915_gem_request *req;
3e960501
CW		 2169 int ret;
2170
2171 /* We need to add any requests required to flush the objects and ring */
6259cead 2172 if (ring->outstanding_lazy_request) {
9400ae5c 2173 ret = i915_add_request(ring);
3e960501
CW		 2174 if (ret)
2175 return ret;
2176 }
2177
2178 /* Wait upon the last request to be completed */
2179 if (list_empty(&ring->request_list))
2180 return 0;
2181
a4b3a571 2182 req = list_entry(ring->request_list.prev,
b4716185
CW		 2183 struct drm_i915_gem_request,
2184 list);
2185
2186 /* Make sure we do not trigger any retires */
2187 return __i915_wait_request(req,
2188 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2189 to_i915(ring->dev)->mm.interruptible,
2190 NULL, NULL);
3e960501
CW		 2191}
2192
6689cb2b 2193int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2194{
6689cb2b 2195 request->ringbuf = request->ring->buffer;
9eba5d4a 2196 return 0;
9d773091
CW		 2197}
2198
29b1b415
JH		 2199void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2200{
2201 /* NB: Until request management is fully tidied up and the OLR is
2202 * removed, there are too many ways for get false hits on this
2203 * anti-recursion check! */
2204 /*WARN_ON(ringbuf->reserved_size);*/
2205 WARN_ON(ringbuf->reserved_in_use);
2206
2207 ringbuf->reserved_size = size;
2208
2209 /*
2210 * Really need to call _begin() here but that currently leads to
2211 * recursion problems! This will be fixed later but for now just
2212 * return and hope for the best. Note that there is only a real
2213 * problem if the create of the request never actually calls _begin()
2214 * but if they are not submitting any work then why did they create
2215 * the request in the first place?
2216 */
2217}
2218
2219void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2220{
2221 WARN_ON(ringbuf->reserved_in_use);
2222
2223 ringbuf->reserved_size = 0;
2224 ringbuf->reserved_in_use = false;
2225}
2226
2227void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2228{
2229 WARN_ON(ringbuf->reserved_in_use);
2230
2231 ringbuf->reserved_in_use = true;
2232 ringbuf->reserved_tail = ringbuf->tail;
2233}
2234
2235void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2236{
2237 WARN_ON(!ringbuf->reserved_in_use);
2238 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2239 "request reserved size too small: %d vs %d!\n",
2240 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2241
2242 ringbuf->reserved_size = 0;
2243 ringbuf->reserved_in_use = false;
2244}
2245
2246static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2247{
93b0a4e0 2248 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2249 int ret;
2250
29b1b415
JH		 2251 /*
2252 * Add on the reserved size to the request to make sure that after
2253 * the intended commands have been emitted, there is guaranteed to
2254 * still be enough free space to send them to the hardware.
2255 */
2256 if (!ringbuf->reserved_in_use)
2257 bytes += ringbuf->reserved_size;
2258
93b0a4e0 2259 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2260 ret = intel_wrap_ring_buffer(ring);
2261 if (unlikely(ret))
2262 return ret;
29b1b415
JH		 2263
2264 if(ringbuf->reserved_size) {
2265 uint32_t size = ringbuf->reserved_size;
2266
2267 intel_ring_reserved_space_cancel(ringbuf);
2268 intel_ring_reserved_space_reserve(ringbuf, size);
2269 }
cbcc80df
MK		 2270 }
2271
93b0a4e0 2272 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2273 ret = ring_wait_for_space(ring, bytes);
2274 if (unlikely(ret))
2275 return ret;
2276 }
2277
cbcc80df
MK		 2278 return 0;
2279}
2280
a4872ba6 2281int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2282 int num_dwords)
8187a2b7 2283{
4640c4ff 2284 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2285 int ret;
78501eac 2286
33196ded
DV		 2287 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2288 dev_priv->mm.interruptible);
de2b9985
DV		 2289 if (ret)
2290 return ret;
21dd3734 2291
304d695c
CW		 2292 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2293 if (ret)
2294 return ret;
2295
9d773091 2296 /* Preallocate the olr before touching the ring */
6689cb2b 2297 ret = i915_gem_request_alloc(ring, ring->default_context);
9d773091
CW		 2298 if (ret)
2299 return ret;
2300
ee1b1e5e 2301 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2302 return 0;
8187a2b7 2303}
78501eac 2304
753b1ad4 2305/* Align the ring tail to a cacheline boundary */
a4872ba6 2306int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2307{
ee1b1e5e 2308 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2309 int ret;
2310
2311 if (num_dwords == 0)
2312 return 0;
2313
18393f63 2314 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2315 ret = intel_ring_begin(ring, num_dwords);
2316 if (ret)
2317 return ret;
2318
2319 while (num_dwords--)
2320 intel_ring_emit(ring, MI_NOOP);
2321
2322 intel_ring_advance(ring);
2323
2324 return 0;
2325}
2326
a4872ba6 2327void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2328{
3b2cc8ab
OM		 2329 struct drm_device *dev = ring->dev;
2330 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2331
6259cead 2332 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2333
3b2cc8ab 2334 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2335 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2336 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2337 if (HAS_VEBOX(dev))
5020150b 2338 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2339 }
d97ed339 2340
f7e98ad4 2341 ring->set_seqno(ring, seqno);
92cab734 2342 ring->hangcheck.seqno = seqno;
8187a2b7 2343}
62fdfeaf 2344
a4872ba6 2345static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2346 u32 value)
881f47b6 2347{
4640c4ff 2348 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2349
2350 /* Every tail move must follow the sequence below */
12f55818
CW		 2351
2352 /* Disable notification that the ring is IDLE. The GT
2353 * will then assume that it is busy and bring it out of rc6.
2354 */
0206e353 2355 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2356 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2357
2358 /* Clear the context id. Here be magic! */
2359 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2360
12f55818 2361 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2362 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2363 GEN6_BSD_SLEEP_INDICATOR) == 0,
2364 50))
2365 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2366
12f55818 2367 /* Now that the ring is fully powered up, update the tail */
0206e353 2368 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2369 POSTING_READ(RING_TAIL(ring->mmio_base));
2370
2371 /* Let the ring send IDLE messages to the GT again,
2372 * and so let it sleep to conserve power when idle.
2373 */
0206e353 2374 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2375 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2376}
2377
a4872ba6 2378static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2379 u32 invalidate, u32 flush)
881f47b6 2380{
71a77e07 2381 uint32_t cmd;
b72f3acb
CW		 2382 int ret;
2383
b72f3acb
CW		 2384 ret = intel_ring_begin(ring, 4);
2385 if (ret)
2386 return ret;
2387
71a77e07 2388 cmd = MI_FLUSH_DW;
075b3bba
BW		 2389 if (INTEL_INFO(ring->dev)->gen >= 8)
2390 cmd += 1;
f0a1fb10
CW		 2391
2392 /* We always require a command barrier so that subsequent
2393 * commands, such as breadcrumb interrupts, are strictly ordered
2394 * wrt the contents of the write cache being flushed to memory
2395 * (and thus being coherent from the CPU).
2396 */
2397 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2398
9a289771
JB		 2399 /*
2400 * Bspec vol 1c.5 - video engine command streamer:
2401 * "If ENABLED, all TLBs will be invalidated once the flush
2402 * operation is complete. This bit is only valid when the
2403 * Post-Sync Operation field is a value of 1h or 3h."
2404 */
71a77e07 2405 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2406 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2407
71a77e07 2408 intel_ring_emit(ring, cmd);
9a289771 2409 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2410 if (INTEL_INFO(ring->dev)->gen >= 8) {
2411 intel_ring_emit(ring, 0); /* upper addr */
2412 intel_ring_emit(ring, 0); /* value */
2413 } else {
2414 intel_ring_emit(ring, 0);
2415 intel_ring_emit(ring, MI_NOOP);
2416 }
b72f3acb
CW		 2417 intel_ring_advance(ring);
2418 return 0;
881f47b6
XH		 2419}
2420
1c7a0623 2421static int
a4872ba6 2422gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2423 u64 offset, u32 len,
8e004efc 2424 unsigned dispatch_flags)
1c7a0623 2425{
8e004efc
JH		 2426 bool ppgtt = USES_PPGTT(ring->dev) &&
2427 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2428 int ret;
2429
2430 ret = intel_ring_begin(ring, 4);
2431 if (ret)
2432 return ret;
2433
2434 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2435 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2436 intel_ring_emit(ring, lower_32_bits(offset));
2437 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2438 intel_ring_emit(ring, MI_NOOP);
2439 intel_ring_advance(ring);
2440
2441 return 0;
2442}
2443
d7d4eedd 2444static int
a4872ba6 2445hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 2446 u64 offset, u32 len,
2447 unsigned dispatch_flags)
d7d4eedd
CW		 2448{
2449 int ret;
2450
2451 ret = intel_ring_begin(ring, 2);
2452 if (ret)
2453 return ret;
2454
2455 intel_ring_emit(ring,
77072258 2456 MI_BATCH_BUFFER_START |
8e004efc 2457 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2458 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2459 /* bit0-7 is the length on GEN6+ */
2460 intel_ring_emit(ring, offset);
2461 intel_ring_advance(ring);
2462
2463 return 0;
2464}
2465
881f47b6 2466static int
a4872ba6 2467gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2468 u64 offset, u32 len,
8e004efc 2469 unsigned dispatch_flags)
881f47b6 2470{
0206e353 2471 int ret;
ab6f8e32 2472
0206e353
AJ		 2473 ret = intel_ring_begin(ring, 2);
2474 if (ret)
2475 return ret;
e1f99ce6 2476
d7d4eedd
CW		 2477 intel_ring_emit(ring,
2478 MI_BATCH_BUFFER_START |
8e004efc
JH		 2479 (dispatch_flags & I915_DISPATCH_SECURE ?
2480 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2481 /* bit0-7 is the length on GEN6+ */
2482 intel_ring_emit(ring, offset);
2483 intel_ring_advance(ring);
ab6f8e32 2484
0206e353 2485 return 0;
881f47b6
XH		 2486}
2487
549f7365
CW		 2488/* Blitter support (SandyBridge+) */
2489
a4872ba6 2490static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2491 u32 invalidate, u32 flush)
8d19215b 2492{
fd3da6c9 2493 struct drm_device *dev = ring->dev;
71a77e07 2494 uint32_t cmd;
b72f3acb
CW		 2495 int ret;
2496
6a233c78 2497 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2498 if (ret)
2499 return ret;
2500
71a77e07 2501 cmd = MI_FLUSH_DW;
dbef0f15 2502 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2503 cmd += 1;
f0a1fb10
CW		 2504
2505 /* We always require a command barrier so that subsequent
2506 * commands, such as breadcrumb interrupts, are strictly ordered
2507 * wrt the contents of the write cache being flushed to memory
2508 * (and thus being coherent from the CPU).
2509 */
2510 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2511
9a289771
JB		 2512 /*
2513 * Bspec vol 1c.3 - blitter engine command streamer:
2514 * "If ENABLED, all TLBs will be invalidated once the flush
2515 * operation is complete. This bit is only valid when the
2516 * Post-Sync Operation field is a value of 1h or 3h."
2517 */
71a77e07 2518 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2519 cmd |= MI_INVALIDATE_TLB;
71a77e07 2520 intel_ring_emit(ring, cmd);
9a289771 2521 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2522 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2523 intel_ring_emit(ring, 0); /* upper addr */
2524 intel_ring_emit(ring, 0); /* value */
2525 } else {
2526 intel_ring_emit(ring, 0);
2527 intel_ring_emit(ring, MI_NOOP);
2528 }
b72f3acb 2529 intel_ring_advance(ring);
fd3da6c9 2530
b72f3acb 2531 return 0;
8d19215b
ZN		 2532}
2533
5c1143bb
XH		 2534int intel_init_render_ring_buffer(struct drm_device *dev)
2535{
4640c4ff 2536 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2537 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2538 struct drm_i915_gem_object *obj;
2539 int ret;
5c1143bb 2540
59465b5f
DV		 2541 ring->name = "render ring";
2542 ring->id = RCS;
2543 ring->mmio_base = RENDER_RING_BASE;
2544
707d9cf9 2545 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2546 if (i915_semaphore_is_enabled(dev)) {
2547 obj = i915_gem_alloc_object(dev, 4096);
2548 if (obj == NULL) {
2549 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2550 i915.semaphores = 0;
2551 } else {
2552 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2553 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2554 if (ret != 0) {
2555 drm_gem_object_unreference(&obj->base);
2556 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2557 i915.semaphores = 0;
2558 } else
2559 dev_priv->semaphore_obj = obj;
2560 }
2561 }
7225342a 2562
8f0e2b9d 2563 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2564 ring->add_request = gen6_add_request;
2565 ring->flush = gen8_render_ring_flush;
2566 ring->irq_get = gen8_ring_get_irq;
2567 ring->irq_put = gen8_ring_put_irq;
2568 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2569 ring->get_seqno = gen6_ring_get_seqno;
2570 ring->set_seqno = ring_set_seqno;
2571 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2572 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2573 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2574 ring->semaphore.signal = gen8_rcs_signal;
2575 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2576 }
2577 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2578 ring->add_request = gen6_add_request;
4772eaeb 2579 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2580 if (INTEL_INFO(dev)->gen == 6)
b3111509 2581 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2582 ring->irq_get = gen6_ring_get_irq;
2583 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2584 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2585 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2586 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2587 if (i915_semaphore_is_enabled(dev)) {
2588 ring->semaphore.sync_to = gen6_ring_sync;
2589 ring->semaphore.signal = gen6_signal;
2590 /*
2591 * The current semaphore is only applied on pre-gen8
2592 * platform. And there is no VCS2 ring on the pre-gen8
2593 * platform. So the semaphore between RCS and VCS2 is
2594 * initialized as INVALID. Gen8 will initialize the
2595 * sema between VCS2 and RCS later.
2596 */
2597 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2598 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2599 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2600 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2601 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2602 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2603 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2604 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2605 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2606 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2607 }
c6df541c
CW		 2608 } else if (IS_GEN5(dev)) {
2609 ring->add_request = pc_render_add_request;
46f0f8d1 2610 ring->flush = gen4_render_ring_flush;
c6df541c 2611 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2612 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2613 ring->irq_get = gen5_ring_get_irq;
2614 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2615 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2616 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2617 } else {
8620a3a9 2618 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2619 if (INTEL_INFO(dev)->gen < 4)
2620 ring->flush = gen2_render_ring_flush;
2621 else
2622 ring->flush = gen4_render_ring_flush;
59465b5f 2623 ring->get_seqno = ring_get_seqno;
b70ec5bf 2624 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2625 if (IS_GEN2(dev)) {
2626 ring->irq_get = i8xx_ring_get_irq;
2627 ring->irq_put = i8xx_ring_put_irq;
2628 } else {
2629 ring->irq_get = i9xx_ring_get_irq;
2630 ring->irq_put = i9xx_ring_put_irq;
2631 }
e3670319 2632 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2633 }
59465b5f 2634 ring->write_tail = ring_write_tail;
707d9cf9 2635
d7d4eedd
CW		 2636 if (IS_HASWELL(dev))
2637 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2638 else if (IS_GEN8(dev))
2639 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2640 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2641 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2642 else if (INTEL_INFO(dev)->gen >= 4)
2643 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2644 else if (IS_I830(dev) || IS_845G(dev))
2645 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2646 else
2647 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2648 ring->init_hw = init_render_ring;
59465b5f
DV		 2649 ring->cleanup = render_ring_cleanup;
2650
b45305fc
DV		 2651 /* Workaround batchbuffer to combat CS tlb bug. */
2652 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2653 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2654 if (obj == NULL) {
2655 DRM_ERROR("Failed to allocate batch bo\n");
2656 return -ENOMEM;
2657 }
2658
be1fa129 2659 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2660 if (ret != 0) {
2661 drm_gem_object_unreference(&obj->base);
2662 DRM_ERROR("Failed to ping batch bo\n");
2663 return ret;
2664 }
2665
0d1aacac
CW		 2666 ring->scratch.obj = obj;
2667 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2668 }
2669
99be1dfe
DV		 2670 ret = intel_init_ring_buffer(dev, ring);
2671 if (ret)
2672 return ret;
2673
2674 if (INTEL_INFO(dev)->gen >= 5) {
2675 ret = intel_init_pipe_control(ring);
2676 if (ret)
2677 return ret;
2678 }
2679
2680 return 0;
5c1143bb
XH		 2681}
2682
2683int intel_init_bsd_ring_buffer(struct drm_device *dev)
2684{
4640c4ff 2685 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2686 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2687
58fa3835
DV		 2688 ring->name = "bsd ring";
2689 ring->id = VCS;
2690
0fd2c201 2691 ring->write_tail = ring_write_tail;
780f18c8 2692 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2693 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2694 /* gen6 bsd needs a special wa for tail updates */
2695 if (IS_GEN6(dev))
2696 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2697 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2698 ring->add_request = gen6_add_request;
2699 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2700 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2701 if (INTEL_INFO(dev)->gen >= 8) {
2702 ring->irq_enable_mask =
2703 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2704 ring->irq_get = gen8_ring_get_irq;
2705 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2706 ring->dispatch_execbuffer =
2707 gen8_ring_dispatch_execbuffer;
707d9cf9 2708 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2709 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2710 ring->semaphore.signal = gen8_xcs_signal;
2711 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2712 }
abd58f01
BW		 2713 } else {
2714 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2715 ring->irq_get = gen6_ring_get_irq;
2716 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2717 ring->dispatch_execbuffer =
2718 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2719 if (i915_semaphore_is_enabled(dev)) {
2720 ring->semaphore.sync_to = gen6_ring_sync;
2721 ring->semaphore.signal = gen6_signal;
2722 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2723 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2724 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2725 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2726 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2727 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2728 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2729 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2730 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2731 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2732 }
abd58f01 2733 }
58fa3835
DV		 2734 } else {
2735 ring->mmio_base = BSD_RING_BASE;
58fa3835 2736 ring->flush = bsd_ring_flush;
8620a3a9 2737 ring->add_request = i9xx_add_request;
58fa3835 2738 ring->get_seqno = ring_get_seqno;
b70ec5bf 2739 ring->set_seqno = ring_set_seqno;
e48d8634 2740 if (IS_GEN5(dev)) {
cc609d5d 2741 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2742 ring->irq_get = gen5_ring_get_irq;
2743 ring->irq_put = gen5_ring_put_irq;
2744 } else {
e3670319 2745 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2746 ring->irq_get = i9xx_ring_get_irq;
2747 ring->irq_put = i9xx_ring_put_irq;
2748 }
fb3256da 2749 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2750 }
ecfe00d8 2751 ring->init_hw = init_ring_common;
58fa3835 2752
1ec14ad3 2753 return intel_init_ring_buffer(dev, ring);
5c1143bb 2754}
549f7365 2755
845f74a7 2756/**
62659920 2757 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2758 */
2759int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2760{
2761 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2762 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2763
f7b64236 2764 ring->name = "bsd2 ring";
845f74a7
ZY		 2765 ring->id = VCS2;
2766
2767 ring->write_tail = ring_write_tail;
2768 ring->mmio_base = GEN8_BSD2_RING_BASE;
2769 ring->flush = gen6_bsd_ring_flush;
2770 ring->add_request = gen6_add_request;
2771 ring->get_seqno = gen6_ring_get_seqno;
2772 ring->set_seqno = ring_set_seqno;
2773 ring->irq_enable_mask =
2774 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2775 ring->irq_get = gen8_ring_get_irq;
2776 ring->irq_put = gen8_ring_put_irq;
2777 ring->dispatch_execbuffer =
2778 gen8_ring_dispatch_execbuffer;
3e78998a 2779 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2780 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2781 ring->semaphore.signal = gen8_xcs_signal;
2782 GEN8_RING_SEMAPHORE_INIT;
2783 }
ecfe00d8 2784 ring->init_hw = init_ring_common;
845f74a7
ZY		 2785
2786 return intel_init_ring_buffer(dev, ring);
2787}
2788
549f7365
CW		 2789int intel_init_blt_ring_buffer(struct drm_device *dev)
2790{
4640c4ff 2791 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2792 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2793
3535d9dd
DV		 2794 ring->name = "blitter ring";
2795 ring->id = BCS;
2796
2797 ring->mmio_base = BLT_RING_BASE;
2798 ring->write_tail = ring_write_tail;
ea251324 2799 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2800 ring->add_request = gen6_add_request;
2801 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2802 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2803 if (INTEL_INFO(dev)->gen >= 8) {
2804 ring->irq_enable_mask =
2805 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2806 ring->irq_get = gen8_ring_get_irq;
2807 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2808 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2809 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2810 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2811 ring->semaphore.signal = gen8_xcs_signal;
2812 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2813 }
abd58f01
BW		 2814 } else {
2815 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2816 ring->irq_get = gen6_ring_get_irq;
2817 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2818 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2819 if (i915_semaphore_is_enabled(dev)) {
2820 ring->semaphore.signal = gen6_signal;
2821 ring->semaphore.sync_to = gen6_ring_sync;
2822 /*
2823 * The current semaphore is only applied on pre-gen8
2824 * platform. And there is no VCS2 ring on the pre-gen8
2825 * platform. So the semaphore between BCS and VCS2 is
2826 * initialized as INVALID. Gen8 will initialize the
2827 * sema between BCS and VCS2 later.
2828 */
2829 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2830 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2831 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2832 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2833 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2834 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2835 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2836 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2837 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2838 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2839 }
abd58f01 2840 }
ecfe00d8 2841 ring->init_hw = init_ring_common;
549f7365 2842
1ec14ad3 2843 return intel_init_ring_buffer(dev, ring);
549f7365 2844}
a7b9761d 2845
9a8a2213
BW		 2846int intel_init_vebox_ring_buffer(struct drm_device *dev)
2847{
4640c4ff 2848 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2849 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2850
2851 ring->name = "video enhancement ring";
2852 ring->id = VECS;
2853
2854 ring->mmio_base = VEBOX_RING_BASE;
2855 ring->write_tail = ring_write_tail;
2856 ring->flush = gen6_ring_flush;
2857 ring->add_request = gen6_add_request;
2858 ring->get_seqno = gen6_ring_get_seqno;
2859 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2860
2861 if (INTEL_INFO(dev)->gen >= 8) {
2862 ring->irq_enable_mask =
40c499f9 2863 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2864 ring->irq_get = gen8_ring_get_irq;
2865 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2866 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2867 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2868 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2869 ring->semaphore.signal = gen8_xcs_signal;
2870 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2871 }
abd58f01
BW		 2872 } else {
2873 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2874 ring->irq_get = hsw_vebox_get_irq;
2875 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2876 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2877 if (i915_semaphore_is_enabled(dev)) {
2878 ring->semaphore.sync_to = gen6_ring_sync;
2879 ring->semaphore.signal = gen6_signal;
2880 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2881 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2882 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2883 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2884 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2885 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2886 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2887 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2888 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2889 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2890 }
abd58f01 2891 }
ecfe00d8 2892 ring->init_hw = init_ring_common;
9a8a2213
BW		 2893
2894 return intel_init_ring_buffer(dev, ring);
2895}
2896
a7b9761d 2897int
a4872ba6 2898intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2899{
2900 int ret;
2901
2902 if (!ring->gpu_caches_dirty)
2903 return 0;
2904
2905 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2906 if (ret)
2907 return ret;
2908
2909 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2910
2911 ring->gpu_caches_dirty = false;
2912 return 0;
2913}
2914
2915int
a4872ba6 2916intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2917{
2918 uint32_t flush_domains;
2919 int ret;
2920
2921 flush_domains = 0;
2922 if (ring->gpu_caches_dirty)
2923 flush_domains = I915_GEM_GPU_DOMAINS;
2924
2925 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2926 if (ret)
2927 return ret;
2928
2929 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2930
2931 ring->gpu_caches_dirty = false;
2932 return 0;
2933}
e3efda49
CW		 2934
2935void
a4872ba6 2936intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2937{
2938 int ret;
2939
2940 if (!intel_ring_initialized(ring))
2941 return;
2942
2943 ret = intel_ring_idle(ring);
2944 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2945 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2946 ring->name, ret);
2947
2948 stop_ring(ring);
2949}
Linux kernel - Deliverables
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