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drm/i915: Remove unnecessary goto in intel_primary_plane_disable()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
376 /*
377 * TLB invalidate requires a post-sync write.
378 */
379 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 380 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631
PZ		 381
382 /* Workaround: we must issue a pipe_control with CS-stall bit
383 * set before a pipe_control command that has the state cache
384 * invalidate bit set. */
385 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 386 }
387
388 ret = intel_ring_begin(ring, 4);
389 if (ret)
390 return ret;
391
392 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
393 intel_ring_emit(ring, flags);
b9e1faa7 394 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 395 intel_ring_emit(ring, 0);
396 intel_ring_advance(ring);
397
9688ecad 398 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 399 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
400
4772eaeb
PZ		 401 return 0;
402}
403
884ceace
KG		 404static int
405gen8_emit_pipe_control(struct intel_engine_cs *ring,
406 u32 flags, u32 scratch_addr)
407{
408 int ret;
409
410 ret = intel_ring_begin(ring, 6);
411 if (ret)
412 return ret;
413
414 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
415 intel_ring_emit(ring, flags);
416 intel_ring_emit(ring, scratch_addr);
417 intel_ring_emit(ring, 0);
418 intel_ring_emit(ring, 0);
419 intel_ring_emit(ring, 0);
420 intel_ring_advance(ring);
421
422 return 0;
423}
424
a5f3d68e 425static int
a4872ba6 426gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 427 u32 invalidate_domains, u32 flush_domains)
428{
429 u32 flags = 0;
18393f63 430 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 431 int ret;
a5f3d68e
BW		 432
433 flags |= PIPE_CONTROL_CS_STALL;
434
435 if (flush_domains) {
436 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
437 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
438 }
439 if (invalidate_domains) {
440 flags |= PIPE_CONTROL_TLB_INVALIDATE;
441 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
442 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
443 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
444 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_QW_WRITE;
447 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 448
449 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
450 ret = gen8_emit_pipe_control(ring,
451 PIPE_CONTROL_CS_STALL |
452 PIPE_CONTROL_STALL_AT_SCOREBOARD,
453 0);
454 if (ret)
455 return ret;
a5f3d68e
BW		 456 }
457
c5ad011d
RV		 458 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
459 if (ret)
460 return ret;
461
462 if (!invalidate_domains && flush_domains)
463 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
464
465 return 0;
a5f3d68e
BW		 466}
467
a4872ba6 468static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 469 u32 value)
d46eefa2 470{
4640c4ff 471 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 472 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 473}
474
a4872ba6 475u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 476{
4640c4ff 477 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 478 u64 acthd;
8187a2b7 479
50877445
CW		 480 if (INTEL_INFO(ring->dev)->gen >= 8)
481 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
482 RING_ACTHD_UDW(ring->mmio_base));
483 else if (INTEL_INFO(ring->dev)->gen >= 4)
484 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
485 else
486 acthd = I915_READ(ACTHD);
487
488 return acthd;
8187a2b7
ZN		 489}
490
a4872ba6 491static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 492{
493 struct drm_i915_private *dev_priv = ring->dev->dev_private;
494 u32 addr;
495
496 addr = dev_priv->status_page_dmah->busaddr;
497 if (INTEL_INFO(ring->dev)->gen >= 4)
498 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
499 I915_WRITE(HWS_PGA, addr);
500}
501
a4872ba6 502static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 503{
9991ae78 504 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 505
9991ae78
CW		 506 if (!IS_GEN2(ring->dev)) {
507 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 508 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
509 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 510 /* Sometimes we observe that the idle flag is not
511 * set even though the ring is empty. So double
512 * check before giving up.
513 */
514 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
515 return false;
9991ae78
CW		 516 }
517 }
b7884eb4 518
7f2ab699 519 I915_WRITE_CTL(ring, 0);
570ef608 520 I915_WRITE_HEAD(ring, 0);
78501eac 521 ring->write_tail(ring, 0);
8187a2b7 522
9991ae78
CW		 523 if (!IS_GEN2(ring->dev)) {
524 (void)I915_READ_CTL(ring);
525 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
526 }
a51435a3 527
9991ae78
CW		 528 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
529}
8187a2b7 530
a4872ba6 531static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 532{
533 struct drm_device *dev = ring->dev;
534 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 535 struct intel_ringbuffer *ringbuf = ring->buffer;
536 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 537 int ret = 0;
538
539 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
540
541 if (!stop_ring(ring)) {
542 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 543 DRM_DEBUG_KMS("%s head not reset to zero "
544 "ctl %08x head %08x tail %08x start %08x\n",
545 ring->name,
546 I915_READ_CTL(ring),
547 I915_READ_HEAD(ring),
548 I915_READ_TAIL(ring),
549 I915_READ_START(ring));
8187a2b7 550
9991ae78 551 if (!stop_ring(ring)) {
6fd0d56e
CW		 552 DRM_ERROR("failed to set %s head to zero "
553 "ctl %08x head %08x tail %08x start %08x\n",
554 ring->name,
555 I915_READ_CTL(ring),
556 I915_READ_HEAD(ring),
557 I915_READ_TAIL(ring),
558 I915_READ_START(ring));
9991ae78
CW		 559 ret = -EIO;
560 goto out;
6fd0d56e 561 }
8187a2b7
ZN		 562 }
563
9991ae78
CW		 564 if (I915_NEED_GFX_HWS(dev))
565 intel_ring_setup_status_page(ring);
566 else
567 ring_setup_phys_status_page(ring);
568
ece4a17d
JK		 569 /* Enforce ordering by reading HEAD register back */
570 I915_READ_HEAD(ring);
571
0d8957c8
DV		 572 /* Initialize the ring. This must happen _after_ we've cleared the ring
573 * registers with the above sequence (the readback of the HEAD registers
574 * also enforces ordering), otherwise the hw might lose the new ring
575 * register values. */
f343c5f6 576 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 577
578 /* WaClearRingBufHeadRegAtInit:ctg,elk */
579 if (I915_READ_HEAD(ring))
580 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
581 ring->name, I915_READ_HEAD(ring));
582 I915_WRITE_HEAD(ring, 0);
583 (void)I915_READ_HEAD(ring);
584
7f2ab699 585 I915_WRITE_CTL(ring,
93b0a4e0 586 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 587 | RING_VALID);
8187a2b7 588
8187a2b7 589 /* If the head is still not zero, the ring is dead */
f01db988 590 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 591 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 592 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 593 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 594 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
595 ring->name,
596 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
597 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
598 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 599 ret = -EIO;
600 goto out;
8187a2b7
ZN		 601 }
602
ebd0fd4b 603 ringbuf->last_retired_head = -1;
5c6c6003
CW		 604 ringbuf->head = I915_READ_HEAD(ring);
605 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 606 intel_ring_update_space(ringbuf);
1ec14ad3 607
50f018df
CW		 608 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
609
b7884eb4 610out:
c8d9a590 611 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 612
613 return ret;
8187a2b7
ZN		 614}
615
9b1136d5
OM		 616void
617intel_fini_pipe_control(struct intel_engine_cs *ring)
618{
619 struct drm_device *dev = ring->dev;
620
621 if (ring->scratch.obj == NULL)
622 return;
623
624 if (INTEL_INFO(dev)->gen >= 5) {
625 kunmap(sg_page(ring->scratch.obj->pages->sgl));
626 i915_gem_object_ggtt_unpin(ring->scratch.obj);
627 }
628
629 drm_gem_object_unreference(&ring->scratch.obj->base);
630 ring->scratch.obj = NULL;
631}
632
633int
634intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 635{
c6df541c
CW		 636 int ret;
637
0d1aacac 638 if (ring->scratch.obj)
c6df541c
CW		 639 return 0;
640
0d1aacac
CW		 641 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
642 if (ring->scratch.obj == NULL) {
c6df541c
CW		 643 DRM_ERROR("Failed to allocate seqno page\n");
644 ret = -ENOMEM;
645 goto err;
646 }
e4ffd173 647
a9cc726c
DV		 648 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
649 if (ret)
650 goto err_unref;
c6df541c 651
1ec9e26d 652 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 653 if (ret)
654 goto err_unref;
655
0d1aacac
CW		 656 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
657 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
658 if (ring->scratch.cpu_page == NULL) {
56b085a0 659 ret = -ENOMEM;
c6df541c 660 goto err_unpin;
56b085a0 661 }
c6df541c 662
2b1086cc 663 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 664 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 665 return 0;
666
667err_unpin:
d7f46fc4 668 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 669err_unref:
0d1aacac 670 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 671err:
c6df541c
CW		 672 return ret;
673}
674
771b9a53
MT		 675static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
676 struct intel_context *ctx)
86d7f238 677{
7225342a 678 int ret, i;
888b5995
AS		 679 struct drm_device *dev = ring->dev;
680 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 681 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 682
7225342a
MK		 683 if (WARN_ON(w->count == 0))
684 return 0;
888b5995 685
7225342a
MK		 686 ring->gpu_caches_dirty = true;
687 ret = intel_ring_flush_all_caches(ring);
688 if (ret)
689 return ret;
888b5995 690
22a916aa 691 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 692 if (ret)
693 return ret;
694
22a916aa 695 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 696 for (i = 0; i < w->count; i++) {
7225342a
MK		 697 intel_ring_emit(ring, w->reg[i].addr);
698 intel_ring_emit(ring, w->reg[i].value);
699 }
22a916aa 700 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 701
702 intel_ring_advance(ring);
703
704 ring->gpu_caches_dirty = true;
705 ret = intel_ring_flush_all_caches(ring);
706 if (ret)
707 return ret;
888b5995 708
7225342a 709 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 710
7225342a 711 return 0;
86d7f238
AS		 712}
713
7225342a
MK		 714static int wa_add(struct drm_i915_private *dev_priv,
715 const u32 addr, const u32 val, const u32 mask)
716{
717 const u32 idx = dev_priv->workarounds.count;
718
719 if (WARN_ON(idx >= I915_MAX_WA_REGS))
720 return -ENOSPC;
721
722 dev_priv->workarounds.reg[idx].addr = addr;
723 dev_priv->workarounds.reg[idx].value = val;
724 dev_priv->workarounds.reg[idx].mask = mask;
725
726 dev_priv->workarounds.count++;
727
728 return 0;
86d7f238
AS		 729}
730
7225342a
MK		 731#define WA_REG(addr, val, mask) { \
732 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
733 if (r) \
734 return r; \
735 }
736
737#define WA_SET_BIT_MASKED(addr, mask) \
738 WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
739
740#define WA_CLR_BIT_MASKED(addr, mask) \
741 WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
742
743#define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
744#define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
745
746#define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
747
00e1e623 748static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 749{
888b5995
AS		 750 struct drm_device *dev = ring->dev;
751 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 752
86d7f238 753 /* WaDisablePartialInstShootdown:bdw */
101b376d 754 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 755 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
756 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
757 STALL_DOP_GATING_DISABLE);
86d7f238 758
101b376d 759 /* WaDisableDopClockGating:bdw */
7225342a
MK		 760 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
761 DOP_CLOCK_GATING_DISABLE);
86d7f238 762
7225342a
MK		 763 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
764 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 765
766 /* Use Force Non-Coherent whenever executing a 3D context. This is a
767 * workaround for for a possible hang in the unlikely event a TLB
768 * invalidation occurs during a PSD flush.
769 */
da09654d 770 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
7225342a
MK		 771 WA_SET_BIT_MASKED(HDC_CHICKEN0,
772 HDC_FORCE_NON_COHERENT |
773 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238
AS		 774
775 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 776 WA_SET_BIT_MASKED(CACHE_MODE_1,
777 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 778
779 /*
780 * BSpec recommends 8x4 when MSAA is used,
781 * however in practice 16x4 seems fastest.
782 *
783 * Note that PS/WM thread counts depend on the WIZ hashing
784 * disable bit, which we don't touch here, but it's good
785 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
786 */
7225342a
MK		 787 WA_SET_BIT_MASKED(GEN7_GT_MODE,
788 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
888b5995 789
86d7f238
AS		 790 return 0;
791}
792
00e1e623
VS		 793static int chv_init_workarounds(struct intel_engine_cs *ring)
794{
00e1e623
VS		 795 struct drm_device *dev = ring->dev;
796 struct drm_i915_private *dev_priv = dev->dev_private;
797
00e1e623 798 /* WaDisablePartialInstShootdown:chv */
00e1e623 799 /* WaDisableThreadStallDopClockGating:chv */
7225342a 800 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 801 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
802 STALL_DOP_GATING_DISABLE);
00e1e623 803
95289009
AS		 804 /* Use Force Non-Coherent whenever executing a 3D context. This is a
805 * workaround for a possible hang in the unlikely event a TLB
806 * invalidation occurs during a PSD flush.
807 */
808 /* WaForceEnableNonCoherent:chv */
809 /* WaHdcDisableFetchWhenMasked:chv */
810 WA_SET_BIT_MASKED(HDC_CHICKEN0,
811 HDC_FORCE_NON_COHERENT |
812 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
813
7225342a
MK		 814 return 0;
815}
816
771b9a53 817int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 818{
819 struct drm_device *dev = ring->dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
821
822 WARN_ON(ring->id != RCS);
823
824 dev_priv->workarounds.count = 0;
825
826 if (IS_BROADWELL(dev))
827 return bdw_init_workarounds(ring);
828
829 if (IS_CHERRYVIEW(dev))
830 return chv_init_workarounds(ring);
00e1e623
VS		 831
832 return 0;
833}
834
a4872ba6 835static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 836{
78501eac 837 struct drm_device *dev = ring->dev;
1ec14ad3 838 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 839 int ret = init_ring_common(ring);
9c33baa6
KZ		 840 if (ret)
841 return ret;
a69ffdbf 842
61a563a2
AG		 843 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
844 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 845 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 846
847 /* We need to disable the AsyncFlip performance optimisations in order
848 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
849 * programmed to '1' on all products.
8693a824 850 *
b3f797ac 851 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 852 */
fbdcb068 853 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 854 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
855
f05bb0c7 856 /* Required for the hardware to program scanline values for waiting */
01fa0302 857 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 858 if (INTEL_INFO(dev)->gen == 6)
859 I915_WRITE(GFX_MODE,
aa83e30d 860 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 861
01fa0302 862 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 863 if (IS_GEN7(dev))
864 I915_WRITE(GFX_MODE_GEN7,
01fa0302 865 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 866 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 867
5e13a0c5 868 if (IS_GEN6(dev)) {
3a69ddd6
KG		 869 /* From the Sandybridge PRM, volume 1 part 3, page 24:
870 * "If this bit is set, STCunit will have LRA as replacement
871 * policy. [...] This bit must be reset. LRA replacement
872 * policy is not supported."
873 */
874 I915_WRITE(CACHE_MODE_0,
5e13a0c5 875 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 876 }
877
6b26c86d
DV		 878 if (INTEL_INFO(dev)->gen >= 6)
879 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 880
040d2baa 881 if (HAS_L3_DPF(dev))
35a85ac6 882 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 883
7225342a 884 return init_workarounds_ring(ring);
8187a2b7
ZN		 885}
886
a4872ba6 887static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 888{
b45305fc 889 struct drm_device *dev = ring->dev;
3e78998a
BW		 890 struct drm_i915_private *dev_priv = dev->dev_private;
891
892 if (dev_priv->semaphore_obj) {
893 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
894 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
895 dev_priv->semaphore_obj = NULL;
896 }
b45305fc 897
9b1136d5 898 intel_fini_pipe_control(ring);
c6df541c
CW		 899}
900
3e78998a
BW		 901static int gen8_rcs_signal(struct intel_engine_cs *signaller,
902 unsigned int num_dwords)
903{
904#define MBOX_UPDATE_DWORDS 8
905 struct drm_device *dev = signaller->dev;
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 struct intel_engine_cs *waiter;
908 int i, ret, num_rings;
909
910 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
911 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
912#undef MBOX_UPDATE_DWORDS
913
914 ret = intel_ring_begin(signaller, num_dwords);
915 if (ret)
916 return ret;
917
918 for_each_ring(waiter, dev_priv, i) {
6259cead 919 u32 seqno;
3e78998a
BW		 920 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
921 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
922 continue;
923
6259cead
JH		 924 seqno = i915_gem_request_get_seqno(
925 signaller->outstanding_lazy_request);
3e78998a
BW		 926 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
927 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
928 PIPE_CONTROL_QW_WRITE |
929 PIPE_CONTROL_FLUSH_ENABLE);
930 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
931 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 932 intel_ring_emit(signaller, seqno);
3e78998a
BW		 933 intel_ring_emit(signaller, 0);
934 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
935 MI_SEMAPHORE_TARGET(waiter->id));
936 intel_ring_emit(signaller, 0);
937 }
938
939 return 0;
940}
941
942static int gen8_xcs_signal(struct intel_engine_cs *signaller,
943 unsigned int num_dwords)
944{
945#define MBOX_UPDATE_DWORDS 6
946 struct drm_device *dev = signaller->dev;
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 struct intel_engine_cs *waiter;
949 int i, ret, num_rings;
950
951 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
952 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
953#undef MBOX_UPDATE_DWORDS
954
955 ret = intel_ring_begin(signaller, num_dwords);
956 if (ret)
957 return ret;
958
959 for_each_ring(waiter, dev_priv, i) {
6259cead 960 u32 seqno;
3e78998a
BW		 961 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
962 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
963 continue;
964
6259cead
JH		 965 seqno = i915_gem_request_get_seqno(
966 signaller->outstanding_lazy_request);
3e78998a
BW		 967 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
968 MI_FLUSH_DW_OP_STOREDW);
969 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
970 MI_FLUSH_DW_USE_GTT);
971 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 972 intel_ring_emit(signaller, seqno);
3e78998a
BW		 973 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
974 MI_SEMAPHORE_TARGET(waiter->id));
975 intel_ring_emit(signaller, 0);
976 }
977
978 return 0;
979}
980
a4872ba6 981static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 982 unsigned int num_dwords)
1ec14ad3 983{
024a43e1
BW		 984 struct drm_device *dev = signaller->dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 986 struct intel_engine_cs *useless;
a1444b79 987 int i, ret, num_rings;
78325f2d 988
a1444b79
BW		 989#define MBOX_UPDATE_DWORDS 3
990 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
991 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
992#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 993
994 ret = intel_ring_begin(signaller, num_dwords);
995 if (ret)
996 return ret;
024a43e1 997
78325f2d
BW		 998 for_each_ring(useless, dev_priv, i) {
999 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1000 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1001 u32 seqno = i915_gem_request_get_seqno(
1002 signaller->outstanding_lazy_request);
78325f2d
BW		 1003 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1004 intel_ring_emit(signaller, mbox_reg);
6259cead 1005 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1006 }
1007 }
024a43e1 1008
a1444b79
BW		 1009 /* If num_dwords was rounded, make sure the tail pointer is correct */
1010 if (num_rings % 2 == 0)
1011 intel_ring_emit(signaller, MI_NOOP);
1012
024a43e1 1013 return 0;
1ec14ad3
CW		 1014}
1015
c8c99b0f
BW		 1016/**
1017 * gen6_add_request - Update the semaphore mailbox registers
1018 *
1019 * @ring - ring that is adding a request
1020 * @seqno - return seqno stuck into the ring
1021 *
1022 * Update the mailbox registers in the *other* rings with the current seqno.
1023 * This acts like a signal in the canonical semaphore.
1024 */
1ec14ad3 1025static int
a4872ba6 1026gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1027{
024a43e1 1028 int ret;
52ed2325 1029
707d9cf9
BW		 1030 if (ring->semaphore.signal)
1031 ret = ring->semaphore.signal(ring, 4);
1032 else
1033 ret = intel_ring_begin(ring, 4);
1034
1ec14ad3
CW		 1035 if (ret)
1036 return ret;
1037
1ec14ad3
CW		 1038 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1039 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1040 intel_ring_emit(ring,
1041 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1042 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1043 __intel_ring_advance(ring);
1ec14ad3 1044
1ec14ad3
CW		 1045 return 0;
1046}
1047
f72b3435
MK		 1048static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1049 u32 seqno)
1050{
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1052 return dev_priv->last_seqno < seqno;
1053}
1054
c8c99b0f
BW		 1055/**
1056 * intel_ring_sync - sync the waiter to the signaller on seqno
1057 *
1058 * @waiter - ring that is waiting
1059 * @signaller - ring which has, or will signal
1060 * @seqno - seqno which the waiter will block on
1061 */
5ee426ca
BW		 1062
1063static int
1064gen8_ring_sync(struct intel_engine_cs *waiter,
1065 struct intel_engine_cs *signaller,
1066 u32 seqno)
1067{
1068 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1069 int ret;
1070
1071 ret = intel_ring_begin(waiter, 4);
1072 if (ret)
1073 return ret;
1074
1075 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1076 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1077 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1078 MI_SEMAPHORE_SAD_GTE_SDD);
1079 intel_ring_emit(waiter, seqno);
1080 intel_ring_emit(waiter,
1081 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1082 intel_ring_emit(waiter,
1083 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1084 intel_ring_advance(waiter);
1085 return 0;
1086}
1087
c8c99b0f 1088static int
a4872ba6
OM		 1089gen6_ring_sync(struct intel_engine_cs *waiter,
1090 struct intel_engine_cs *signaller,
686cb5f9 1091 u32 seqno)
1ec14ad3 1092{
c8c99b0f
BW		 1093 u32 dw1 = MI_SEMAPHORE_MBOX |
1094 MI_SEMAPHORE_COMPARE |
1095 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1096 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1097 int ret;
1ec14ad3 1098
1500f7ea
BW		 1099 /* Throughout all of the GEM code, seqno passed implies our current
1100 * seqno is >= the last seqno executed. However for hardware the
1101 * comparison is strictly greater than.
1102 */
1103 seqno -= 1;
1104
ebc348b2 1105 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1106
c8c99b0f 1107 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1108 if (ret)
1109 return ret;
1110
f72b3435
MK		 1111 /* If seqno wrap happened, omit the wait with no-ops */
1112 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1113 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1114 intel_ring_emit(waiter, seqno);
1115 intel_ring_emit(waiter, 0);
1116 intel_ring_emit(waiter, MI_NOOP);
1117 } else {
1118 intel_ring_emit(waiter, MI_NOOP);
1119 intel_ring_emit(waiter, MI_NOOP);
1120 intel_ring_emit(waiter, MI_NOOP);
1121 intel_ring_emit(waiter, MI_NOOP);
1122 }
c8c99b0f 1123 intel_ring_advance(waiter);
1ec14ad3
CW		 1124
1125 return 0;
1126}
1127
c6df541c
CW		 1128#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1129do { \
fcbc34e4
KG		 1130 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1131 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1132 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1133 intel_ring_emit(ring__, 0); \
1134 intel_ring_emit(ring__, 0); \
1135} while (0)
1136
1137static int
a4872ba6 1138pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1139{
18393f63 1140 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1141 int ret;
1142
1143 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1144 * incoherent with writes to memory, i.e. completely fubar,
1145 * so we need to use PIPE_NOTIFY instead.
1146 *
1147 * However, we also need to workaround the qword write
1148 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1149 * memory before requesting an interrupt.
1150 */
1151 ret = intel_ring_begin(ring, 32);
1152 if (ret)
1153 return ret;
1154
fcbc34e4 1155 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1156 PIPE_CONTROL_WRITE_FLUSH |
1157 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1158 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1159 intel_ring_emit(ring,
1160 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1161 intel_ring_emit(ring, 0);
1162 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1163 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1164 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1165 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1166 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1167 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1168 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1169 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1170 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1171 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1172 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1173
fcbc34e4 1174 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1175 PIPE_CONTROL_WRITE_FLUSH |
1176 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1177 PIPE_CONTROL_NOTIFY);
0d1aacac 1178 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1179 intel_ring_emit(ring,
1180 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1181 intel_ring_emit(ring, 0);
09246732 1182 __intel_ring_advance(ring);
c6df541c 1183
c6df541c
CW		 1184 return 0;
1185}
1186
4cd53c0c 1187static u32
a4872ba6 1188gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1189{
4cd53c0c
DV		 1190 /* Workaround to force correct ordering between irq and seqno writes on
1191 * ivb (and maybe also on snb) by reading from a CS register (like
1192 * ACTHD) before reading the status page. */
50877445
CW		 1193 if (!lazy_coherency) {
1194 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1195 POSTING_READ(RING_ACTHD(ring->mmio_base));
1196 }
1197
4cd53c0c
DV		 1198 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1199}
1200
8187a2b7 1201static u32
a4872ba6 1202ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1203{
1ec14ad3
CW		 1204 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1205}
1206
b70ec5bf 1207static void
a4872ba6 1208ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1209{
1210 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1211}
1212
c6df541c 1213static u32
a4872ba6 1214pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1215{
0d1aacac 1216 return ring->scratch.cpu_page[0];
c6df541c
CW		 1217}
1218
b70ec5bf 1219static void
a4872ba6 1220pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1221{
0d1aacac 1222 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1223}
1224
e48d8634 1225static bool
a4872ba6 1226gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1227{
1228 struct drm_device *dev = ring->dev;
4640c4ff 1229 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1230 unsigned long flags;
e48d8634 1231
7cd512f1 1232 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1233 return false;
1234
7338aefa 1235 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1236 if (ring->irq_refcount++ == 0)
480c8033 1237 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1238 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1239
1240 return true;
1241}
1242
1243static void
a4872ba6 1244gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1245{
1246 struct drm_device *dev = ring->dev;
4640c4ff 1247 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1248 unsigned long flags;
e48d8634 1249
7338aefa 1250 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1251 if (--ring->irq_refcount == 0)
480c8033 1252 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1253 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1254}
1255
b13c2b96 1256static bool
a4872ba6 1257i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1258{
78501eac 1259 struct drm_device *dev = ring->dev;
4640c4ff 1260 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1261 unsigned long flags;
62fdfeaf 1262
7cd512f1 1263 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1264 return false;
1265
7338aefa 1266 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1267 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1268 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1269 I915_WRITE(IMR, dev_priv->irq_mask);
1270 POSTING_READ(IMR);
1271 }
7338aefa 1272 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1273
1274 return true;
62fdfeaf
EA		 1275}
1276
8187a2b7 1277static void
a4872ba6 1278i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1279{
78501eac 1280 struct drm_device *dev = ring->dev;
4640c4ff 1281 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1282 unsigned long flags;
62fdfeaf 1283
7338aefa 1284 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1285 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1286 dev_priv->irq_mask |= ring->irq_enable_mask;
1287 I915_WRITE(IMR, dev_priv->irq_mask);
1288 POSTING_READ(IMR);
1289 }
7338aefa 1290 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1291}
1292
c2798b19 1293static bool
a4872ba6 1294i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1295{
1296 struct drm_device *dev = ring->dev;
4640c4ff 1297 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1298 unsigned long flags;
c2798b19 1299
7cd512f1 1300 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1301 return false;
1302
7338aefa 1303 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1304 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1305 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1306 I915_WRITE16(IMR, dev_priv->irq_mask);
1307 POSTING_READ16(IMR);
1308 }
7338aefa 1309 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1310
1311 return true;
1312}
1313
1314static void
a4872ba6 1315i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1316{
1317 struct drm_device *dev = ring->dev;
4640c4ff 1318 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1319 unsigned long flags;
c2798b19 1320
7338aefa 1321 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1322 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1323 dev_priv->irq_mask |= ring->irq_enable_mask;
1324 I915_WRITE16(IMR, dev_priv->irq_mask);
1325 POSTING_READ16(IMR);
1326 }
7338aefa 1327 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1328}
1329
a4872ba6 1330void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1331{
4593010b 1332 struct drm_device *dev = ring->dev;
4640c4ff 1333 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1334 u32 mmio = 0;
1335
1336 /* The ring status page addresses are no longer next to the rest of
1337 * the ring registers as of gen7.
1338 */
1339 if (IS_GEN7(dev)) {
1340 switch (ring->id) {
96154f2f 1341 case RCS:
4593010b
EA		 1342 mmio = RENDER_HWS_PGA_GEN7;
1343 break;
96154f2f 1344 case BCS:
4593010b
EA		 1345 mmio = BLT_HWS_PGA_GEN7;
1346 break;
77fe2ff3
ZY		 1347 /*
1348 * VCS2 actually doesn't exist on Gen7. Only shut up
1349 * gcc switch check warning
1350 */
1351 case VCS2:
96154f2f 1352 case VCS:
4593010b
EA		 1353 mmio = BSD_HWS_PGA_GEN7;
1354 break;
4a3dd19d 1355 case VECS:
9a8a2213
BW		 1356 mmio = VEBOX_HWS_PGA_GEN7;
1357 break;
4593010b
EA		 1358 }
1359 } else if (IS_GEN6(ring->dev)) {
1360 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1361 } else {
eb0d4b75 1362 /* XXX: gen8 returns to sanity */
4593010b
EA		 1363 mmio = RING_HWS_PGA(ring->mmio_base);
1364 }
1365
78501eac
CW		 1366 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1367 POSTING_READ(mmio);
884020bf 1368
dc616b89
DL		 1369 /*
1370 * Flush the TLB for this page
1371 *
1372 * FIXME: These two bits have disappeared on gen8, so a question
1373 * arises: do we still need this and if so how should we go about
1374 * invalidating the TLB?
1375 */
1376 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1377 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1378
1379 /* ring should be idle before issuing a sync flush*/
1380 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1381
884020bf
CW		 1382 I915_WRITE(reg,
1383 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1384 INSTPM_SYNC_FLUSH));
1385 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1386 1000))
1387 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1388 ring->name);
1389 }
8187a2b7
ZN		 1390}
1391
b72f3acb 1392static int
a4872ba6 1393bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1394 u32 invalidate_domains,
1395 u32 flush_domains)
d1b851fc 1396{
b72f3acb
CW		 1397 int ret;
1398
b72f3acb
CW		 1399 ret = intel_ring_begin(ring, 2);
1400 if (ret)
1401 return ret;
1402
1403 intel_ring_emit(ring, MI_FLUSH);
1404 intel_ring_emit(ring, MI_NOOP);
1405 intel_ring_advance(ring);
1406 return 0;
d1b851fc
ZN		 1407}
1408
3cce469c 1409static int
a4872ba6 1410i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1411{
3cce469c
CW		 1412 int ret;
1413
1414 ret = intel_ring_begin(ring, 4);
1415 if (ret)
1416 return ret;
6f392d54 1417
3cce469c
CW		 1418 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1419 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1420 intel_ring_emit(ring,
1421 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1422 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1423 __intel_ring_advance(ring);
d1b851fc 1424
3cce469c 1425 return 0;
d1b851fc
ZN		 1426}
1427
0f46832f 1428static bool
a4872ba6 1429gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1430{
1431 struct drm_device *dev = ring->dev;
4640c4ff 1432 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1433 unsigned long flags;
0f46832f 1434
7cd512f1
DV		 1435 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1436 return false;
0f46832f 1437
7338aefa 1438 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1439 if (ring->irq_refcount++ == 0) {
040d2baa 1440 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1441 I915_WRITE_IMR(ring,
1442 ~(ring->irq_enable_mask |
35a85ac6 1443 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1444 else
1445 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1446 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1447 }
7338aefa 1448 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1449
1450 return true;
1451}
1452
1453static void
a4872ba6 1454gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1455{
1456 struct drm_device *dev = ring->dev;
4640c4ff 1457 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1458 unsigned long flags;
0f46832f 1459
7338aefa 1460 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1461 if (--ring->irq_refcount == 0) {
040d2baa 1462 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1463 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1464 else
1465 I915_WRITE_IMR(ring, ~0);
480c8033 1466 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1467 }
7338aefa 1468 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1469}
1470
a19d2933 1471static bool
a4872ba6 1472hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1473{
1474 struct drm_device *dev = ring->dev;
1475 struct drm_i915_private *dev_priv = dev->dev_private;
1476 unsigned long flags;
1477
7cd512f1 1478 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1479 return false;
1480
59cdb63d 1481 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1482 if (ring->irq_refcount++ == 0) {
a19d2933 1483 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1484 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1485 }
59cdb63d 1486 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1487
1488 return true;
1489}
1490
1491static void
a4872ba6 1492hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1493{
1494 struct drm_device *dev = ring->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 unsigned long flags;
1497
59cdb63d 1498 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1499 if (--ring->irq_refcount == 0) {
a19d2933 1500 I915_WRITE_IMR(ring, ~0);
480c8033 1501 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1502 }
59cdb63d 1503 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1504}
1505
abd58f01 1506static bool
a4872ba6 1507gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1508{
1509 struct drm_device *dev = ring->dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511 unsigned long flags;
1512
7cd512f1 1513 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1514 return false;
1515
1516 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1517 if (ring->irq_refcount++ == 0) {
1518 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1519 I915_WRITE_IMR(ring,
1520 ~(ring->irq_enable_mask |
1521 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1522 } else {
1523 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1524 }
1525 POSTING_READ(RING_IMR(ring->mmio_base));
1526 }
1527 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1528
1529 return true;
1530}
1531
1532static void
a4872ba6 1533gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1534{
1535 struct drm_device *dev = ring->dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 unsigned long flags;
1538
1539 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1540 if (--ring->irq_refcount == 0) {
1541 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1542 I915_WRITE_IMR(ring,
1543 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1544 } else {
1545 I915_WRITE_IMR(ring, ~0);
1546 }
1547 POSTING_READ(RING_IMR(ring->mmio_base));
1548 }
1549 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1550}
1551
d1b851fc 1552static int
a4872ba6 1553i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1554 u64 offset, u32 length,
d7d4eedd 1555 unsigned flags)
d1b851fc 1556{
e1f99ce6 1557 int ret;
78501eac 1558
e1f99ce6
CW		 1559 ret = intel_ring_begin(ring, 2);
1560 if (ret)
1561 return ret;
1562
78501eac 1563 intel_ring_emit(ring,
65f56876
CW		 1564 MI_BATCH_BUFFER_START |
1565 MI_BATCH_GTT |
d7d4eedd 1566 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1567 intel_ring_emit(ring, offset);
78501eac
CW		 1568 intel_ring_advance(ring);
1569
d1b851fc
ZN		 1570 return 0;
1571}
1572
b45305fc
DV		 1573/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1574#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1575#define I830_TLB_ENTRIES (2)
1576#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1577static int
a4872ba6 1578i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1579 u64 offset, u32 len,
d7d4eedd 1580 unsigned flags)
62fdfeaf 1581{
c4d69da1 1582 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1583 int ret;
62fdfeaf 1584
c4d69da1
CW		 1585 ret = intel_ring_begin(ring, 6);
1586 if (ret)
1587 return ret;
62fdfeaf 1588
c4d69da1
CW		 1589 /* Evict the invalid PTE TLBs */
1590 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1591 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1592 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1593 intel_ring_emit(ring, cs_offset);
1594 intel_ring_emit(ring, 0xdeadbeef);
1595 intel_ring_emit(ring, MI_NOOP);
1596 intel_ring_advance(ring);
b45305fc 1597
c4d69da1 1598 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1599 if (len > I830_BATCH_LIMIT)
1600 return -ENOSPC;
1601
c4d69da1 1602 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1603 if (ret)
1604 return ret;
c4d69da1
CW		 1605
1606 /* Blit the batch (which has now all relocs applied) to the
1607 * stable batch scratch bo area (so that the CS never
1608 * stumbles over its tlb invalidation bug) ...
1609 */
1610 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1611 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1612 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1613 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1614 intel_ring_emit(ring, 4096);
1615 intel_ring_emit(ring, offset);
c4d69da1 1616
b45305fc 1617 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1618 intel_ring_emit(ring, MI_NOOP);
1619 intel_ring_advance(ring);
b45305fc
DV		 1620
1621 /* ... and execute it. */
c4d69da1 1622 offset = cs_offset;
b45305fc 1623 }
e1f99ce6 1624
c4d69da1
CW		 1625 ret = intel_ring_begin(ring, 4);
1626 if (ret)
1627 return ret;
1628
1629 intel_ring_emit(ring, MI_BATCH_BUFFER);
1630 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1631 intel_ring_emit(ring, offset + len - 8);
1632 intel_ring_emit(ring, MI_NOOP);
1633 intel_ring_advance(ring);
1634
fb3256da
DV		 1635 return 0;
1636}
1637
1638static int
a4872ba6 1639i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1640 u64 offset, u32 len,
d7d4eedd 1641 unsigned flags)
fb3256da
DV		 1642{
1643 int ret;
1644
1645 ret = intel_ring_begin(ring, 2);
1646 if (ret)
1647 return ret;
1648
65f56876 1649 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1650 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1651 intel_ring_advance(ring);
62fdfeaf 1652
62fdfeaf
EA		 1653 return 0;
1654}
1655
a4872ba6 1656static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1657{
05394f39 1658 struct drm_i915_gem_object *obj;
62fdfeaf 1659
8187a2b7
ZN		 1660 obj = ring->status_page.obj;
1661 if (obj == NULL)
62fdfeaf 1662 return;
62fdfeaf 1663
9da3da66 1664 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1665 i915_gem_object_ggtt_unpin(obj);
05394f39 1666 drm_gem_object_unreference(&obj->base);
8187a2b7 1667 ring->status_page.obj = NULL;
62fdfeaf
EA		 1668}
1669
a4872ba6 1670static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1671{
05394f39 1672 struct drm_i915_gem_object *obj;
62fdfeaf 1673
e3efda49 1674 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1675 unsigned flags;
e3efda49 1676 int ret;
e4ffd173 1677
e3efda49
CW		 1678 obj = i915_gem_alloc_object(ring->dev, 4096);
1679 if (obj == NULL) {
1680 DRM_ERROR("Failed to allocate status page\n");
1681 return -ENOMEM;
1682 }
62fdfeaf 1683
e3efda49
CW		 1684 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1685 if (ret)
1686 goto err_unref;
1687
1f767e02
CW		 1688 flags = 0;
1689 if (!HAS_LLC(ring->dev))
1690 /* On g33, we cannot place HWS above 256MiB, so
1691 * restrict its pinning to the low mappable arena.
1692 * Though this restriction is not documented for
1693 * gen4, gen5, or byt, they also behave similarly
1694 * and hang if the HWS is placed at the top of the
1695 * GTT. To generalise, it appears that all !llc
1696 * platforms have issues with us placing the HWS
1697 * above the mappable region (even though we never
1698 * actualy map it).
1699 */
1700 flags |= PIN_MAPPABLE;
1701 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1702 if (ret) {
1703err_unref:
1704 drm_gem_object_unreference(&obj->base);
1705 return ret;
1706 }
1707
1708 ring->status_page.obj = obj;
1709 }
62fdfeaf 1710
f343c5f6 1711 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1712 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1713 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1714
8187a2b7
ZN		 1715 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1716 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1717
1718 return 0;
62fdfeaf
EA		 1719}
1720
a4872ba6 1721static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1722{
1723 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1724
1725 if (!dev_priv->status_page_dmah) {
1726 dev_priv->status_page_dmah =
1727 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1728 if (!dev_priv->status_page_dmah)
1729 return -ENOMEM;
1730 }
1731
6b8294a4
CW		 1732 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1733 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1734
1735 return 0;
1736}
1737
7ba717cf 1738void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1739{
2919d291 1740 iounmap(ringbuf->virtual_start);
7ba717cf 1741 ringbuf->virtual_start = NULL;
2919d291 1742 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1743}
1744
1745int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1746 struct intel_ringbuffer *ringbuf)
1747{
1748 struct drm_i915_private *dev_priv = to_i915(dev);
1749 struct drm_i915_gem_object *obj = ringbuf->obj;
1750 int ret;
1751
1752 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1753 if (ret)
1754 return ret;
1755
1756 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1757 if (ret) {
1758 i915_gem_object_ggtt_unpin(obj);
1759 return ret;
1760 }
1761
1762 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1763 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1764 if (ringbuf->virtual_start == NULL) {
1765 i915_gem_object_ggtt_unpin(obj);
1766 return -EINVAL;
1767 }
1768
1769 return 0;
1770}
1771
1772void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1773{
2919d291
OM		 1774 drm_gem_object_unreference(&ringbuf->obj->base);
1775 ringbuf->obj = NULL;
1776}
1777
84c2377f
OM		 1778int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1779 struct intel_ringbuffer *ringbuf)
62fdfeaf 1780{
05394f39 1781 struct drm_i915_gem_object *obj;
62fdfeaf 1782
ebc052e0
CW		 1783 obj = NULL;
1784 if (!HAS_LLC(dev))
93b0a4e0 1785 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1786 if (obj == NULL)
93b0a4e0 1787 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1788 if (obj == NULL)
1789 return -ENOMEM;
8187a2b7 1790
24f3a8cf
AG		 1791 /* mark ring buffers as read-only from GPU side by default */
1792 obj->gt_ro = 1;
1793
93b0a4e0 1794 ringbuf->obj = obj;
e3efda49 1795
7ba717cf 1796 return 0;
e3efda49
CW		 1797}
1798
1799static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1800 struct intel_engine_cs *ring)
e3efda49 1801{
8ee14975 1802 struct intel_ringbuffer *ringbuf = ring->buffer;
e3efda49
CW		 1803 int ret;
1804
8ee14975
OM		 1805 if (ringbuf == NULL) {
1806 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1807 if (!ringbuf)
1808 return -ENOMEM;
1809 ring->buffer = ringbuf;
1810 }
1811
e3efda49
CW		 1812 ring->dev = dev;
1813 INIT_LIST_HEAD(&ring->active_list);
1814 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1815 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1816 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1817 ringbuf->ring = ring;
ebc348b2 1818 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1819
1820 init_waitqueue_head(&ring->irq_queue);
1821
1822 if (I915_NEED_GFX_HWS(dev)) {
1823 ret = init_status_page(ring);
1824 if (ret)
8ee14975 1825 goto error;
e3efda49
CW		 1826 } else {
1827 BUG_ON(ring->id != RCS);
1828 ret = init_phys_status_page(ring);
1829 if (ret)
8ee14975 1830 goto error;
e3efda49
CW		 1831 }
1832
7ba717cf
TD		 1833 if (ringbuf->obj == NULL) {
1834 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1835 if (ret) {
1836 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1837 ring->name, ret);
1838 goto error;
1839 }
1840
1841 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1842 if (ret) {
1843 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1844 ring->name, ret);
1845 intel_destroy_ringbuffer_obj(ringbuf);
1846 goto error;
1847 }
e3efda49 1848 }
62fdfeaf 1849
55249baa
CW		 1850 /* Workaround an erratum on the i830 which causes a hang if
1851 * the TAIL pointer points to within the last 2 cachelines
1852 * of the buffer.
1853 */
93b0a4e0 1854 ringbuf->effective_size = ringbuf->size;
e3efda49 1855 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1856 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1857
44e895a8
BV		 1858 ret = i915_cmd_parser_init_ring(ring);
1859 if (ret)
8ee14975
OM		 1860 goto error;
1861
8ee14975 1862 return 0;
351e3db2 1863
8ee14975
OM		 1864error:
1865 kfree(ringbuf);
1866 ring->buffer = NULL;
1867 return ret;
62fdfeaf
EA		 1868}
1869
a4872ba6 1870void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1871{
6402c330
JH		 1872 struct drm_i915_private *dev_priv;
1873 struct intel_ringbuffer *ringbuf;
33626e6a 1874
93b0a4e0 1875 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1876 return;
1877
6402c330
JH		 1878 dev_priv = to_i915(ring->dev);
1879 ringbuf = ring->buffer;
1880
e3efda49 1881 intel_stop_ring_buffer(ring);
de8f0a50 1882 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1883
7ba717cf 1884 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 1885 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 1886 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 1887
8d19215b
ZN		 1888 if (ring->cleanup)
1889 ring->cleanup(ring);
1890
78501eac 1891 cleanup_status_page(ring);
44e895a8
BV		 1892
1893 i915_cmd_parser_fini_ring(ring);
8ee14975 1894
93b0a4e0 1895 kfree(ringbuf);
8ee14975 1896 ring->buffer = NULL;
62fdfeaf
EA		 1897}
1898
a4872ba6 1899static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1900{
93b0a4e0 1901 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1902 struct drm_i915_gem_request *request;
a71d8d94
CW		 1903 int ret;
1904
ebd0fd4b
DG		 1905 if (intel_ring_space(ringbuf) >= n)
1906 return 0;
a71d8d94
CW		 1907
1908 list_for_each_entry(request, &ring->request_list, list) {
82e104cc
OM		 1909 if (__intel_ring_space(request->tail, ringbuf->tail,
1910 ringbuf->size) >= n) {
a71d8d94
CW		 1911 break;
1912 }
a71d8d94
CW		 1913 }
1914
a4b3a571 1915 if (&request->list == &ring->request_list)
a71d8d94
CW		 1916 return -ENOSPC;
1917
a4b3a571 1918 ret = i915_wait_request(request);
a71d8d94
CW		 1919 if (ret)
1920 return ret;
1921
1cf0ba14 1922 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 1923
1924 return 0;
1925}
1926
a4872ba6 1927static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1928{
78501eac 1929 struct drm_device *dev = ring->dev;
cae5852d 1930 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1931 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1932 unsigned long end;
a71d8d94 1933 int ret;
c7dca47b 1934
a71d8d94
CW		 1935 ret = intel_ring_wait_request(ring, n);
1936 if (ret != -ENOSPC)
1937 return ret;
1938
09246732
CW		 1939 /* force the tail write in case we have been skipping them */
1940 __intel_ring_advance(ring);
1941
63ed2cb2
DV		 1942 /* With GEM the hangcheck timer should kick us out of the loop,
1943 * leaving it early runs the risk of corrupting GEM state (due
1944 * to running on almost untested codepaths). But on resume
1945 * timers don't work yet, so prevent a complete hang in that
1946 * case by choosing an insanely large timeout. */
1947 end = jiffies + 60 * HZ;
e6bfaf85 1948
ebd0fd4b 1949 ret = 0;
dcfe0506 1950 trace_i915_ring_wait_begin(ring);
8187a2b7 1951 do {
ebd0fd4b
DG		 1952 if (intel_ring_space(ringbuf) >= n)
1953 break;
93b0a4e0 1954 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 1955 if (intel_ring_space(ringbuf) >= n)
dcfe0506 1956 break;
62fdfeaf 1957
e60a0b10 1958 msleep(1);
d6b2c790 1959
dcfe0506
CW		 1960 if (dev_priv->mm.interruptible && signal_pending(current)) {
1961 ret = -ERESTARTSYS;
1962 break;
1963 }
1964
33196ded
DV		 1965 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1966 dev_priv->mm.interruptible);
d6b2c790 1967 if (ret)
dcfe0506
CW		 1968 break;
1969
1970 if (time_after(jiffies, end)) {
1971 ret = -EBUSY;
1972 break;
1973 }
1974 } while (1);
db53a302 1975 trace_i915_ring_wait_end(ring);
dcfe0506 1976 return ret;
8187a2b7 1977}
62fdfeaf 1978
a4872ba6 1979static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 1980{
1981 uint32_t __iomem *virt;
93b0a4e0
OM		 1982 struct intel_ringbuffer *ringbuf = ring->buffer;
1983 int rem = ringbuf->size - ringbuf->tail;
3e960501 1984
93b0a4e0 1985 if (ringbuf->space < rem) {
3e960501
CW		 1986 int ret = ring_wait_for_space(ring, rem);
1987 if (ret)
1988 return ret;
1989 }
1990
93b0a4e0 1991 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 1992 rem /= 4;
1993 while (rem--)
1994 iowrite32(MI_NOOP, virt++);
1995
93b0a4e0 1996 ringbuf->tail = 0;
ebd0fd4b 1997 intel_ring_update_space(ringbuf);
3e960501
CW		 1998
1999 return 0;
2000}
2001
a4872ba6 2002int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2003{
a4b3a571 2004 struct drm_i915_gem_request *req;
3e960501
CW		 2005 int ret;
2006
2007 /* We need to add any requests required to flush the objects and ring */
6259cead 2008 if (ring->outstanding_lazy_request) {
9400ae5c 2009 ret = i915_add_request(ring);
3e960501
CW		 2010 if (ret)
2011 return ret;
2012 }
2013
2014 /* Wait upon the last request to be completed */
2015 if (list_empty(&ring->request_list))
2016 return 0;
2017
a4b3a571 2018 req = list_entry(ring->request_list.prev,
3e960501 2019 struct drm_i915_gem_request,
a4b3a571 2020 list);
3e960501 2021
a4b3a571 2022 return i915_wait_request(req);
3e960501
CW		 2023}
2024
9d773091 2025static int
6259cead 2026intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2027{
9eba5d4a
JH		 2028 int ret;
2029 struct drm_i915_gem_request *request;
2030
6259cead 2031 if (ring->outstanding_lazy_request)
9d773091 2032 return 0;
3c0e234c 2033
9eba5d4a
JH		 2034 request = kmalloc(sizeof(*request), GFP_KERNEL);
2035 if (request == NULL)
2036 return -ENOMEM;
3c0e234c 2037
abfe262a 2038 kref_init(&request->ref);
ff79e857 2039 request->ring = ring;
abfe262a 2040
6259cead 2041 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2042 if (ret) {
2043 kfree(request);
2044 return ret;
3c0e234c
CW		 2045 }
2046
6259cead 2047 ring->outstanding_lazy_request = request;
9eba5d4a 2048 return 0;
9d773091
CW		 2049}
2050
a4872ba6 2051static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2052 int bytes)
cbcc80df 2053{
93b0a4e0 2054 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2055 int ret;
2056
93b0a4e0 2057 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2058 ret = intel_wrap_ring_buffer(ring);
2059 if (unlikely(ret))
2060 return ret;
2061 }
2062
93b0a4e0 2063 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2064 ret = ring_wait_for_space(ring, bytes);
2065 if (unlikely(ret))
2066 return ret;
2067 }
2068
cbcc80df
MK		 2069 return 0;
2070}
2071
a4872ba6 2072int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2073 int num_dwords)
8187a2b7 2074{
4640c4ff 2075 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2076 int ret;
78501eac 2077
33196ded
DV		 2078 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2079 dev_priv->mm.interruptible);
de2b9985
DV		 2080 if (ret)
2081 return ret;
21dd3734 2082
304d695c
CW		 2083 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2084 if (ret)
2085 return ret;
2086
9d773091 2087 /* Preallocate the olr before touching the ring */
6259cead 2088 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2089 if (ret)
2090 return ret;
2091
ee1b1e5e 2092 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2093 return 0;
8187a2b7 2094}
78501eac 2095
753b1ad4 2096/* Align the ring tail to a cacheline boundary */
a4872ba6 2097int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2098{
ee1b1e5e 2099 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2100 int ret;
2101
2102 if (num_dwords == 0)
2103 return 0;
2104
18393f63 2105 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2106 ret = intel_ring_begin(ring, num_dwords);
2107 if (ret)
2108 return ret;
2109
2110 while (num_dwords--)
2111 intel_ring_emit(ring, MI_NOOP);
2112
2113 intel_ring_advance(ring);
2114
2115 return 0;
2116}
2117
a4872ba6 2118void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2119{
3b2cc8ab
OM		 2120 struct drm_device *dev = ring->dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2122
6259cead 2123 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2124
3b2cc8ab 2125 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2126 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2127 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2128 if (HAS_VEBOX(dev))
5020150b 2129 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2130 }
d97ed339 2131
f7e98ad4 2132 ring->set_seqno(ring, seqno);
92cab734 2133 ring->hangcheck.seqno = seqno;
8187a2b7 2134}
62fdfeaf 2135
a4872ba6 2136static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2137 u32 value)
881f47b6 2138{
4640c4ff 2139 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2140
2141 /* Every tail move must follow the sequence below */
12f55818
CW		 2142
2143 /* Disable notification that the ring is IDLE. The GT
2144 * will then assume that it is busy and bring it out of rc6.
2145 */
0206e353 2146 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2147 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2148
2149 /* Clear the context id. Here be magic! */
2150 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2151
12f55818 2152 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2153 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2154 GEN6_BSD_SLEEP_INDICATOR) == 0,
2155 50))
2156 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2157
12f55818 2158 /* Now that the ring is fully powered up, update the tail */
0206e353 2159 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2160 POSTING_READ(RING_TAIL(ring->mmio_base));
2161
2162 /* Let the ring send IDLE messages to the GT again,
2163 * and so let it sleep to conserve power when idle.
2164 */
0206e353 2165 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2166 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2167}
2168
a4872ba6 2169static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2170 u32 invalidate, u32 flush)
881f47b6 2171{
71a77e07 2172 uint32_t cmd;
b72f3acb
CW		 2173 int ret;
2174
b72f3acb
CW		 2175 ret = intel_ring_begin(ring, 4);
2176 if (ret)
2177 return ret;
2178
71a77e07 2179 cmd = MI_FLUSH_DW;
075b3bba
BW		 2180 if (INTEL_INFO(ring->dev)->gen >= 8)
2181 cmd += 1;
9a289771
JB		 2182 /*
2183 * Bspec vol 1c.5 - video engine command streamer:
2184 * "If ENABLED, all TLBs will be invalidated once the flush
2185 * operation is complete. This bit is only valid when the
2186 * Post-Sync Operation field is a value of 1h or 3h."
2187 */
71a77e07 2188 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2189 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2190 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2191 intel_ring_emit(ring, cmd);
9a289771 2192 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2193 if (INTEL_INFO(ring->dev)->gen >= 8) {
2194 intel_ring_emit(ring, 0); /* upper addr */
2195 intel_ring_emit(ring, 0); /* value */
2196 } else {
2197 intel_ring_emit(ring, 0);
2198 intel_ring_emit(ring, MI_NOOP);
2199 }
b72f3acb
CW		 2200 intel_ring_advance(ring);
2201 return 0;
881f47b6
XH		 2202}
2203
1c7a0623 2204static int
a4872ba6 2205gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2206 u64 offset, u32 len,
1c7a0623
BW		 2207 unsigned flags)
2208{
896ab1a5 2209 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2210 int ret;
2211
2212 ret = intel_ring_begin(ring, 4);
2213 if (ret)
2214 return ret;
2215
2216 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2217 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2218 intel_ring_emit(ring, lower_32_bits(offset));
2219 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2220 intel_ring_emit(ring, MI_NOOP);
2221 intel_ring_advance(ring);
2222
2223 return 0;
2224}
2225
d7d4eedd 2226static int
a4872ba6 2227hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2228 u64 offset, u32 len,
d7d4eedd
CW		 2229 unsigned flags)
2230{
2231 int ret;
2232
2233 ret = intel_ring_begin(ring, 2);
2234 if (ret)
2235 return ret;
2236
2237 intel_ring_emit(ring,
77072258
CW		 2238 MI_BATCH_BUFFER_START |
2239 (flags & I915_DISPATCH_SECURE ?
2240 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2241 /* bit0-7 is the length on GEN6+ */
2242 intel_ring_emit(ring, offset);
2243 intel_ring_advance(ring);
2244
2245 return 0;
2246}
2247
881f47b6 2248static int
a4872ba6 2249gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2250 u64 offset, u32 len,
d7d4eedd 2251 unsigned flags)
881f47b6 2252{
0206e353 2253 int ret;
ab6f8e32 2254
0206e353
AJ		 2255 ret = intel_ring_begin(ring, 2);
2256 if (ret)
2257 return ret;
e1f99ce6 2258
d7d4eedd
CW		 2259 intel_ring_emit(ring,
2260 MI_BATCH_BUFFER_START |
2261 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2262 /* bit0-7 is the length on GEN6+ */
2263 intel_ring_emit(ring, offset);
2264 intel_ring_advance(ring);
ab6f8e32 2265
0206e353 2266 return 0;
881f47b6
XH		 2267}
2268
549f7365
CW		 2269/* Blitter support (SandyBridge+) */
2270
a4872ba6 2271static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2272 u32 invalidate, u32 flush)
8d19215b 2273{
fd3da6c9 2274 struct drm_device *dev = ring->dev;
1d73c2a8 2275 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2276 uint32_t cmd;
b72f3acb
CW		 2277 int ret;
2278
6a233c78 2279 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2280 if (ret)
2281 return ret;
2282
71a77e07 2283 cmd = MI_FLUSH_DW;
075b3bba
BW		 2284 if (INTEL_INFO(ring->dev)->gen >= 8)
2285 cmd += 1;
9a289771
JB		 2286 /*
2287 * Bspec vol 1c.3 - blitter engine command streamer:
2288 * "If ENABLED, all TLBs will be invalidated once the flush
2289 * operation is complete. This bit is only valid when the
2290 * Post-Sync Operation field is a value of 1h or 3h."
2291 */
71a77e07 2292 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2293 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2294 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2295 intel_ring_emit(ring, cmd);
9a289771 2296 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2297 if (INTEL_INFO(ring->dev)->gen >= 8) {
2298 intel_ring_emit(ring, 0); /* upper addr */
2299 intel_ring_emit(ring, 0); /* value */
2300 } else {
2301 intel_ring_emit(ring, 0);
2302 intel_ring_emit(ring, MI_NOOP);
2303 }
b72f3acb 2304 intel_ring_advance(ring);
fd3da6c9 2305
1d73c2a8
RV		 2306 if (!invalidate && flush) {
2307 if (IS_GEN7(dev))
2308 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2309 else if (IS_BROADWELL(dev))
2310 dev_priv->fbc.need_sw_cache_clean = true;
2311 }
fd3da6c9 2312
b72f3acb 2313 return 0;
8d19215b
ZN		 2314}
2315
5c1143bb
XH		 2316int intel_init_render_ring_buffer(struct drm_device *dev)
2317{
4640c4ff 2318 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2319 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2320 struct drm_i915_gem_object *obj;
2321 int ret;
5c1143bb 2322
59465b5f
DV		 2323 ring->name = "render ring";
2324 ring->id = RCS;
2325 ring->mmio_base = RENDER_RING_BASE;
2326
707d9cf9 2327 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2328 if (i915_semaphore_is_enabled(dev)) {
2329 obj = i915_gem_alloc_object(dev, 4096);
2330 if (obj == NULL) {
2331 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2332 i915.semaphores = 0;
2333 } else {
2334 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2335 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2336 if (ret != 0) {
2337 drm_gem_object_unreference(&obj->base);
2338 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2339 i915.semaphores = 0;
2340 } else
2341 dev_priv->semaphore_obj = obj;
2342 }
2343 }
7225342a
MK		 2344
2345 ring->init_context = intel_ring_workarounds_emit;
707d9cf9
BW		 2346 ring->add_request = gen6_add_request;
2347 ring->flush = gen8_render_ring_flush;
2348 ring->irq_get = gen8_ring_get_irq;
2349 ring->irq_put = gen8_ring_put_irq;
2350 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2351 ring->get_seqno = gen6_ring_get_seqno;
2352 ring->set_seqno = ring_set_seqno;
2353 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2354 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2355 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2356 ring->semaphore.signal = gen8_rcs_signal;
2357 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2358 }
2359 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2360 ring->add_request = gen6_add_request;
4772eaeb 2361 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2362 if (INTEL_INFO(dev)->gen == 6)
b3111509 2363 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2364 ring->irq_get = gen6_ring_get_irq;
2365 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2366 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2367 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2368 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2369 if (i915_semaphore_is_enabled(dev)) {
2370 ring->semaphore.sync_to = gen6_ring_sync;
2371 ring->semaphore.signal = gen6_signal;
2372 /*
2373 * The current semaphore is only applied on pre-gen8
2374 * platform. And there is no VCS2 ring on the pre-gen8
2375 * platform. So the semaphore between RCS and VCS2 is
2376 * initialized as INVALID. Gen8 will initialize the
2377 * sema between VCS2 and RCS later.
2378 */
2379 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2380 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2381 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2382 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2383 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2384 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2385 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2386 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2387 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2388 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2389 }
c6df541c
CW		 2390 } else if (IS_GEN5(dev)) {
2391 ring->add_request = pc_render_add_request;
46f0f8d1 2392 ring->flush = gen4_render_ring_flush;
c6df541c 2393 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2394 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2395 ring->irq_get = gen5_ring_get_irq;
2396 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2397 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2398 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2399 } else {
8620a3a9 2400 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2401 if (INTEL_INFO(dev)->gen < 4)
2402 ring->flush = gen2_render_ring_flush;
2403 else
2404 ring->flush = gen4_render_ring_flush;
59465b5f 2405 ring->get_seqno = ring_get_seqno;
b70ec5bf 2406 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2407 if (IS_GEN2(dev)) {
2408 ring->irq_get = i8xx_ring_get_irq;
2409 ring->irq_put = i8xx_ring_put_irq;
2410 } else {
2411 ring->irq_get = i9xx_ring_get_irq;
2412 ring->irq_put = i9xx_ring_put_irq;
2413 }
e3670319 2414 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2415 }
59465b5f 2416 ring->write_tail = ring_write_tail;
707d9cf9 2417
d7d4eedd
CW		 2418 if (IS_HASWELL(dev))
2419 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2420 else if (IS_GEN8(dev))
2421 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2422 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2423 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2424 else if (INTEL_INFO(dev)->gen >= 4)
2425 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2426 else if (IS_I830(dev) || IS_845G(dev))
2427 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2428 else
2429 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2430 ring->init_hw = init_render_ring;
59465b5f
DV		 2431 ring->cleanup = render_ring_cleanup;
2432
b45305fc
DV		 2433 /* Workaround batchbuffer to combat CS tlb bug. */
2434 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2435 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2436 if (obj == NULL) {
2437 DRM_ERROR("Failed to allocate batch bo\n");
2438 return -ENOMEM;
2439 }
2440
be1fa129 2441 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2442 if (ret != 0) {
2443 drm_gem_object_unreference(&obj->base);
2444 DRM_ERROR("Failed to ping batch bo\n");
2445 return ret;
2446 }
2447
0d1aacac
CW		 2448 ring->scratch.obj = obj;
2449 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2450 }
2451
99be1dfe
DV		 2452 ret = intel_init_ring_buffer(dev, ring);
2453 if (ret)
2454 return ret;
2455
2456 if (INTEL_INFO(dev)->gen >= 5) {
2457 ret = intel_init_pipe_control(ring);
2458 if (ret)
2459 return ret;
2460 }
2461
2462 return 0;
5c1143bb
XH		 2463}
2464
2465int intel_init_bsd_ring_buffer(struct drm_device *dev)
2466{
4640c4ff 2467 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2468 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2469
58fa3835
DV		 2470 ring->name = "bsd ring";
2471 ring->id = VCS;
2472
0fd2c201 2473 ring->write_tail = ring_write_tail;
780f18c8 2474 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2475 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2476 /* gen6 bsd needs a special wa for tail updates */
2477 if (IS_GEN6(dev))
2478 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2479 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2480 ring->add_request = gen6_add_request;
2481 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2482 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2483 if (INTEL_INFO(dev)->gen >= 8) {
2484 ring->irq_enable_mask =
2485 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2486 ring->irq_get = gen8_ring_get_irq;
2487 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2488 ring->dispatch_execbuffer =
2489 gen8_ring_dispatch_execbuffer;
707d9cf9 2490 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2491 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2492 ring->semaphore.signal = gen8_xcs_signal;
2493 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2494 }
abd58f01
BW		 2495 } else {
2496 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2497 ring->irq_get = gen6_ring_get_irq;
2498 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2499 ring->dispatch_execbuffer =
2500 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2501 if (i915_semaphore_is_enabled(dev)) {
2502 ring->semaphore.sync_to = gen6_ring_sync;
2503 ring->semaphore.signal = gen6_signal;
2504 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2505 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2506 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2507 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2508 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2509 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2510 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2511 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2512 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2513 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2514 }
abd58f01 2515 }
58fa3835
DV		 2516 } else {
2517 ring->mmio_base = BSD_RING_BASE;
58fa3835 2518 ring->flush = bsd_ring_flush;
8620a3a9 2519 ring->add_request = i9xx_add_request;
58fa3835 2520 ring->get_seqno = ring_get_seqno;
b70ec5bf 2521 ring->set_seqno = ring_set_seqno;
e48d8634 2522 if (IS_GEN5(dev)) {
cc609d5d 2523 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2524 ring->irq_get = gen5_ring_get_irq;
2525 ring->irq_put = gen5_ring_put_irq;
2526 } else {
e3670319 2527 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2528 ring->irq_get = i9xx_ring_get_irq;
2529 ring->irq_put = i9xx_ring_put_irq;
2530 }
fb3256da 2531 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2532 }
ecfe00d8 2533 ring->init_hw = init_ring_common;
58fa3835 2534
1ec14ad3 2535 return intel_init_ring_buffer(dev, ring);
5c1143bb 2536}
549f7365 2537
845f74a7
ZY		 2538/**
2539 * Initialize the second BSD ring for Broadwell GT3.
2540 * It is noted that this only exists on Broadwell GT3.
2541 */
2542int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2543{
2544 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2545 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2546
2547 if ((INTEL_INFO(dev)->gen != 8)) {
2548 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2549 return -EINVAL;
2550 }
2551
f7b64236 2552 ring->name = "bsd2 ring";
845f74a7
ZY		 2553 ring->id = VCS2;
2554
2555 ring->write_tail = ring_write_tail;
2556 ring->mmio_base = GEN8_BSD2_RING_BASE;
2557 ring->flush = gen6_bsd_ring_flush;
2558 ring->add_request = gen6_add_request;
2559 ring->get_seqno = gen6_ring_get_seqno;
2560 ring->set_seqno = ring_set_seqno;
2561 ring->irq_enable_mask =
2562 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2563 ring->irq_get = gen8_ring_get_irq;
2564 ring->irq_put = gen8_ring_put_irq;
2565 ring->dispatch_execbuffer =
2566 gen8_ring_dispatch_execbuffer;
3e78998a 2567 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2568 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2569 ring->semaphore.signal = gen8_xcs_signal;
2570 GEN8_RING_SEMAPHORE_INIT;
2571 }
ecfe00d8 2572 ring->init_hw = init_ring_common;
845f74a7
ZY		 2573
2574 return intel_init_ring_buffer(dev, ring);
2575}
2576
549f7365
CW		 2577int intel_init_blt_ring_buffer(struct drm_device *dev)
2578{
4640c4ff 2579 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2580 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2581
3535d9dd
DV		 2582 ring->name = "blitter ring";
2583 ring->id = BCS;
2584
2585 ring->mmio_base = BLT_RING_BASE;
2586 ring->write_tail = ring_write_tail;
ea251324 2587 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2588 ring->add_request = gen6_add_request;
2589 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2590 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2591 if (INTEL_INFO(dev)->gen >= 8) {
2592 ring->irq_enable_mask =
2593 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2594 ring->irq_get = gen8_ring_get_irq;
2595 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2596 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2597 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2598 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2599 ring->semaphore.signal = gen8_xcs_signal;
2600 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2601 }
abd58f01
BW		 2602 } else {
2603 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2604 ring->irq_get = gen6_ring_get_irq;
2605 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2606 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2607 if (i915_semaphore_is_enabled(dev)) {
2608 ring->semaphore.signal = gen6_signal;
2609 ring->semaphore.sync_to = gen6_ring_sync;
2610 /*
2611 * The current semaphore is only applied on pre-gen8
2612 * platform. And there is no VCS2 ring on the pre-gen8
2613 * platform. So the semaphore between BCS and VCS2 is
2614 * initialized as INVALID. Gen8 will initialize the
2615 * sema between BCS and VCS2 later.
2616 */
2617 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2618 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2619 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2620 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2621 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2622 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2623 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2624 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2625 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2626 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2627 }
abd58f01 2628 }
ecfe00d8 2629 ring->init_hw = init_ring_common;
549f7365 2630
1ec14ad3 2631 return intel_init_ring_buffer(dev, ring);
549f7365 2632}
a7b9761d 2633
9a8a2213
BW		 2634int intel_init_vebox_ring_buffer(struct drm_device *dev)
2635{
4640c4ff 2636 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2637 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2638
2639 ring->name = "video enhancement ring";
2640 ring->id = VECS;
2641
2642 ring->mmio_base = VEBOX_RING_BASE;
2643 ring->write_tail = ring_write_tail;
2644 ring->flush = gen6_ring_flush;
2645 ring->add_request = gen6_add_request;
2646 ring->get_seqno = gen6_ring_get_seqno;
2647 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2648
2649 if (INTEL_INFO(dev)->gen >= 8) {
2650 ring->irq_enable_mask =
40c499f9 2651 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2652 ring->irq_get = gen8_ring_get_irq;
2653 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2654 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2655 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2656 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2657 ring->semaphore.signal = gen8_xcs_signal;
2658 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2659 }
abd58f01
BW		 2660 } else {
2661 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2662 ring->irq_get = hsw_vebox_get_irq;
2663 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2664 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2665 if (i915_semaphore_is_enabled(dev)) {
2666 ring->semaphore.sync_to = gen6_ring_sync;
2667 ring->semaphore.signal = gen6_signal;
2668 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2669 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2670 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2671 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2672 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2673 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2674 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2675 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2676 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2677 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2678 }
abd58f01 2679 }
ecfe00d8 2680 ring->init_hw = init_ring_common;
9a8a2213
BW		 2681
2682 return intel_init_ring_buffer(dev, ring);
2683}
2684
a7b9761d 2685int
a4872ba6 2686intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2687{
2688 int ret;
2689
2690 if (!ring->gpu_caches_dirty)
2691 return 0;
2692
2693 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2694 if (ret)
2695 return ret;
2696
2697 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2698
2699 ring->gpu_caches_dirty = false;
2700 return 0;
2701}
2702
2703int
a4872ba6 2704intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2705{
2706 uint32_t flush_domains;
2707 int ret;
2708
2709 flush_domains = 0;
2710 if (ring->gpu_caches_dirty)
2711 flush_domains = I915_GEM_GPU_DOMAINS;
2712
2713 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2714 if (ret)
2715 return ret;
2716
2717 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2718
2719 ring->gpu_caches_dirty = false;
2720 return 0;
2721}
e3efda49
CW		 2722
2723void
a4872ba6 2724intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2725{
2726 int ret;
2727
2728 if (!intel_ring_initialized(ring))
2729 return;
2730
2731 ret = intel_ring_idle(ring);
2732 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2733 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2734 ring->name, ret);
2735
2736 stop_ring(ring);
2737}
Linux kernel - Deliverables
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