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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
8d315287 JB |
37 | /* |
38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
39 | * over cache flushing. | |
40 | */ | |
41 | struct pipe_control { | |
42 | struct drm_i915_gem_object *obj; | |
43 | volatile u32 *cpu_page; | |
44 | u32 gtt_offset; | |
45 | }; | |
46 | ||
c7dca47b CW |
47 | static inline int ring_space(struct intel_ring_buffer *ring) |
48 | { | |
49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); | |
50 | if (space < 0) | |
51 | space += ring->size; | |
52 | return space; | |
53 | } | |
54 | ||
b72f3acb | 55 | static int |
46f0f8d1 CW |
56 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
57 | u32 invalidate_domains, | |
58 | u32 flush_domains) | |
59 | { | |
60 | u32 cmd; | |
61 | int ret; | |
62 | ||
63 | cmd = MI_FLUSH; | |
31b14c9f | 64 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
65 | cmd |= MI_NO_WRITE_FLUSH; |
66 | ||
67 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
68 | cmd |= MI_READ_FLUSH; | |
69 | ||
70 | ret = intel_ring_begin(ring, 2); | |
71 | if (ret) | |
72 | return ret; | |
73 | ||
74 | intel_ring_emit(ring, cmd); | |
75 | intel_ring_emit(ring, MI_NOOP); | |
76 | intel_ring_advance(ring); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int | |
82 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
83 | u32 invalidate_domains, | |
84 | u32 flush_domains) | |
62fdfeaf | 85 | { |
78501eac | 86 | struct drm_device *dev = ring->dev; |
6f392d54 | 87 | u32 cmd; |
b72f3acb | 88 | int ret; |
6f392d54 | 89 | |
36d527de CW |
90 | /* |
91 | * read/write caches: | |
92 | * | |
93 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
94 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
95 | * also flushed at 2d versus 3d pipeline switches. | |
96 | * | |
97 | * read-only caches: | |
98 | * | |
99 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
100 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
101 | * | |
102 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
103 | * | |
104 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
105 | * invalidated when MI_EXE_FLUSH is set. | |
106 | * | |
107 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
108 | * invalidated with every MI_FLUSH. | |
109 | * | |
110 | * TLBs: | |
111 | * | |
112 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
113 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
114 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
115 | * are flushed at any MI_FLUSH. | |
116 | */ | |
117 | ||
118 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 119 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 120 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
121 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
122 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 123 | |
36d527de CW |
124 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
125 | (IS_G4X(dev) || IS_GEN5(dev))) | |
126 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 127 | |
36d527de CW |
128 | ret = intel_ring_begin(ring, 2); |
129 | if (ret) | |
130 | return ret; | |
b72f3acb | 131 | |
36d527de CW |
132 | intel_ring_emit(ring, cmd); |
133 | intel_ring_emit(ring, MI_NOOP); | |
134 | intel_ring_advance(ring); | |
b72f3acb CW |
135 | |
136 | return 0; | |
8187a2b7 ZN |
137 | } |
138 | ||
8d315287 JB |
139 | /** |
140 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
141 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
142 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
143 | * | |
144 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
145 | * produced by non-pipelined state commands), software needs to first | |
146 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
147 | * 0. | |
148 | * | |
149 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
150 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
151 | * | |
152 | * And the workaround for these two requires this workaround first: | |
153 | * | |
154 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
155 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
156 | * flushes. | |
157 | * | |
158 | * And this last workaround is tricky because of the requirements on | |
159 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
160 | * volume 2 part 1: | |
161 | * | |
162 | * "1 of the following must also be set: | |
163 | * - Render Target Cache Flush Enable ([12] of DW1) | |
164 | * - Depth Cache Flush Enable ([0] of DW1) | |
165 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
166 | * - Depth Stall ([13] of DW1) | |
167 | * - Post-Sync Operation ([13] of DW1) | |
168 | * - Notify Enable ([8] of DW1)" | |
169 | * | |
170 | * The cache flushes require the workaround flush that triggered this | |
171 | * one, so we can't use it. Depth stall would trigger the same. | |
172 | * Post-sync nonzero is what triggered this second workaround, so we | |
173 | * can't use that one either. Notify enable is IRQs, which aren't | |
174 | * really our business. That leaves only stall at scoreboard. | |
175 | */ | |
176 | static int | |
177 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
178 | { | |
179 | struct pipe_control *pc = ring->private; | |
180 | u32 scratch_addr = pc->gtt_offset + 128; | |
181 | int ret; | |
182 | ||
183 | ||
184 | ret = intel_ring_begin(ring, 6); | |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
189 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
190 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
191 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
192 | intel_ring_emit(ring, 0); /* low dword */ | |
193 | intel_ring_emit(ring, 0); /* high dword */ | |
194 | intel_ring_emit(ring, MI_NOOP); | |
195 | intel_ring_advance(ring); | |
196 | ||
197 | ret = intel_ring_begin(ring, 6); | |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
202 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
203 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
204 | intel_ring_emit(ring, 0); | |
205 | intel_ring_emit(ring, 0); | |
206 | intel_ring_emit(ring, MI_NOOP); | |
207 | intel_ring_advance(ring); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
213 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
214 | u32 invalidate_domains, u32 flush_domains) | |
215 | { | |
216 | u32 flags = 0; | |
217 | struct pipe_control *pc = ring->private; | |
218 | u32 scratch_addr = pc->gtt_offset + 128; | |
219 | int ret; | |
220 | ||
8d315287 JB |
221 | /* Just flush everything. Experiments have shown that reducing the |
222 | * number of bits based on the write domains has little performance | |
223 | * impact. | |
224 | */ | |
7d54a904 CW |
225 | if (flush_domains) { |
226 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
227 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
228 | /* | |
229 | * Ensure that any following seqno writes only happen | |
230 | * when the render cache is indeed flushed. | |
231 | */ | |
97f209bc | 232 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
233 | } |
234 | if (invalidate_domains) { | |
235 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
236 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
237 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
241 | /* | |
242 | * TLB invalidate requires a post-sync write. | |
243 | */ | |
244 | flags |= PIPE_CONTROL_QW_WRITE; | |
245 | } | |
8d315287 | 246 | |
6c6cf5aa | 247 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
248 | if (ret) |
249 | return ret; | |
250 | ||
6c6cf5aa | 251 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
252 | intel_ring_emit(ring, flags); |
253 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 254 | intel_ring_emit(ring, 0); |
8d315287 JB |
255 | intel_ring_advance(ring); |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
6c6cf5aa CW |
260 | static int |
261 | gen6_render_ring_flush__wa(struct intel_ring_buffer *ring, | |
262 | u32 invalidate_domains, u32 flush_domains) | |
263 | { | |
264 | int ret; | |
265 | ||
266 | /* Force SNB workarounds for PIPE_CONTROL flushes */ | |
267 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | return gen6_render_ring_flush(ring, invalidate_domains, flush_domains); | |
272 | } | |
273 | ||
78501eac | 274 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 275 | u32 value) |
d46eefa2 | 276 | { |
78501eac | 277 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 278 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
279 | } |
280 | ||
78501eac | 281 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 282 | { |
78501eac CW |
283 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
284 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 285 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
286 | |
287 | return I915_READ(acthd_reg); | |
288 | } | |
289 | ||
78501eac | 290 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 291 | { |
b7884eb4 DV |
292 | struct drm_device *dev = ring->dev; |
293 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 294 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 295 | int ret = 0; |
8187a2b7 | 296 | u32 head; |
8187a2b7 | 297 | |
b7884eb4 DV |
298 | if (HAS_FORCE_WAKE(dev)) |
299 | gen6_gt_force_wake_get(dev_priv); | |
300 | ||
8187a2b7 | 301 | /* Stop the ring if it's running. */ |
7f2ab699 | 302 | I915_WRITE_CTL(ring, 0); |
570ef608 | 303 | I915_WRITE_HEAD(ring, 0); |
78501eac | 304 | ring->write_tail(ring, 0); |
8187a2b7 | 305 | |
570ef608 | 306 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
307 | |
308 | /* G45 ring initialization fails to reset head to zero */ | |
309 | if (head != 0) { | |
6fd0d56e CW |
310 | DRM_DEBUG_KMS("%s head not reset to zero " |
311 | "ctl %08x head %08x tail %08x start %08x\n", | |
312 | ring->name, | |
313 | I915_READ_CTL(ring), | |
314 | I915_READ_HEAD(ring), | |
315 | I915_READ_TAIL(ring), | |
316 | I915_READ_START(ring)); | |
8187a2b7 | 317 | |
570ef608 | 318 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 319 | |
6fd0d56e CW |
320 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
321 | DRM_ERROR("failed to set %s head to zero " | |
322 | "ctl %08x head %08x tail %08x start %08x\n", | |
323 | ring->name, | |
324 | I915_READ_CTL(ring), | |
325 | I915_READ_HEAD(ring), | |
326 | I915_READ_TAIL(ring), | |
327 | I915_READ_START(ring)); | |
328 | } | |
8187a2b7 ZN |
329 | } |
330 | ||
0d8957c8 DV |
331 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
332 | * registers with the above sequence (the readback of the HEAD registers | |
333 | * also enforces ordering), otherwise the hw might lose the new ring | |
334 | * register values. */ | |
335 | I915_WRITE_START(ring, obj->gtt_offset); | |
7f2ab699 | 336 | I915_WRITE_CTL(ring, |
ae69b42a | 337 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 338 | | RING_VALID); |
8187a2b7 | 339 | |
8187a2b7 | 340 | /* If the head is still not zero, the ring is dead */ |
f01db988 SP |
341 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
342 | I915_READ_START(ring) == obj->gtt_offset && | |
343 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 CW |
344 | DRM_ERROR("%s initialization failed " |
345 | "ctl %08x head %08x tail %08x start %08x\n", | |
346 | ring->name, | |
347 | I915_READ_CTL(ring), | |
348 | I915_READ_HEAD(ring), | |
349 | I915_READ_TAIL(ring), | |
350 | I915_READ_START(ring)); | |
b7884eb4 DV |
351 | ret = -EIO; |
352 | goto out; | |
8187a2b7 ZN |
353 | } |
354 | ||
78501eac CW |
355 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
356 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 357 | else { |
c7dca47b | 358 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 359 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 360 | ring->space = ring_space(ring); |
c3b20037 | 361 | ring->last_retired_head = -1; |
8187a2b7 | 362 | } |
1ec14ad3 | 363 | |
b7884eb4 DV |
364 | out: |
365 | if (HAS_FORCE_WAKE(dev)) | |
366 | gen6_gt_force_wake_put(dev_priv); | |
367 | ||
368 | return ret; | |
8187a2b7 ZN |
369 | } |
370 | ||
c6df541c CW |
371 | static int |
372 | init_pipe_control(struct intel_ring_buffer *ring) | |
373 | { | |
374 | struct pipe_control *pc; | |
375 | struct drm_i915_gem_object *obj; | |
376 | int ret; | |
377 | ||
378 | if (ring->private) | |
379 | return 0; | |
380 | ||
381 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
382 | if (!pc) | |
383 | return -ENOMEM; | |
384 | ||
385 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
386 | if (obj == NULL) { | |
387 | DRM_ERROR("Failed to allocate seqno page\n"); | |
388 | ret = -ENOMEM; | |
389 | goto err; | |
390 | } | |
e4ffd173 CW |
391 | |
392 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c CW |
393 | |
394 | ret = i915_gem_object_pin(obj, 4096, true); | |
395 | if (ret) | |
396 | goto err_unref; | |
397 | ||
398 | pc->gtt_offset = obj->gtt_offset; | |
399 | pc->cpu_page = kmap(obj->pages[0]); | |
400 | if (pc->cpu_page == NULL) | |
401 | goto err_unpin; | |
402 | ||
403 | pc->obj = obj; | |
404 | ring->private = pc; | |
405 | return 0; | |
406 | ||
407 | err_unpin: | |
408 | i915_gem_object_unpin(obj); | |
409 | err_unref: | |
410 | drm_gem_object_unreference(&obj->base); | |
411 | err: | |
412 | kfree(pc); | |
413 | return ret; | |
414 | } | |
415 | ||
416 | static void | |
417 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
418 | { | |
419 | struct pipe_control *pc = ring->private; | |
420 | struct drm_i915_gem_object *obj; | |
421 | ||
422 | if (!ring->private) | |
423 | return; | |
424 | ||
425 | obj = pc->obj; | |
426 | kunmap(obj->pages[0]); | |
427 | i915_gem_object_unpin(obj); | |
428 | drm_gem_object_unreference(&obj->base); | |
429 | ||
430 | kfree(pc); | |
431 | ring->private = NULL; | |
432 | } | |
433 | ||
78501eac | 434 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 435 | { |
78501eac | 436 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 437 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 438 | int ret = init_ring_common(ring); |
a69ffdbf | 439 | |
a6c45cf0 | 440 | if (INTEL_INFO(dev)->gen > 3) { |
6b26c86d | 441 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
b095cd0a JB |
442 | if (IS_GEN7(dev)) |
443 | I915_WRITE(GFX_MODE_GEN7, | |
6b26c86d DV |
444 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
445 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
8187a2b7 | 446 | } |
78501eac | 447 | |
8d315287 | 448 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
449 | ret = init_pipe_control(ring); |
450 | if (ret) | |
451 | return ret; | |
452 | } | |
453 | ||
5e13a0c5 | 454 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
455 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
456 | * "If this bit is set, STCunit will have LRA as replacement | |
457 | * policy. [...] This bit must be reset. LRA replacement | |
458 | * policy is not supported." | |
459 | */ | |
460 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 461 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
462 | |
463 | /* This is not explicitly set for GEN6, so read the register. | |
464 | * see intel_ring_mi_set_context() for why we care. | |
465 | * TODO: consider explicitly setting the bit for GEN5 | |
466 | */ | |
467 | ring->itlb_before_ctx_switch = | |
468 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
469 | } |
470 | ||
6b26c86d DV |
471 | if (INTEL_INFO(dev)->gen >= 6) |
472 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 473 | |
e1ef7cc2 | 474 | if (HAS_L3_GPU_CACHE(dev)) |
15b9f80e BW |
475 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
476 | ||
8187a2b7 ZN |
477 | return ret; |
478 | } | |
479 | ||
c6df541c CW |
480 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
481 | { | |
482 | if (!ring->private) | |
483 | return; | |
484 | ||
485 | cleanup_pipe_control(ring); | |
486 | } | |
487 | ||
1ec14ad3 | 488 | static void |
c8c99b0f BW |
489 | update_mboxes(struct intel_ring_buffer *ring, |
490 | u32 seqno, | |
491 | u32 mmio_offset) | |
1ec14ad3 | 492 | { |
c8c99b0f BW |
493 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
494 | MI_SEMAPHORE_GLOBAL_GTT | | |
495 | MI_SEMAPHORE_REGISTER | | |
496 | MI_SEMAPHORE_UPDATE); | |
1ec14ad3 | 497 | intel_ring_emit(ring, seqno); |
c8c99b0f | 498 | intel_ring_emit(ring, mmio_offset); |
1ec14ad3 CW |
499 | } |
500 | ||
c8c99b0f BW |
501 | /** |
502 | * gen6_add_request - Update the semaphore mailbox registers | |
503 | * | |
504 | * @ring - ring that is adding a request | |
505 | * @seqno - return seqno stuck into the ring | |
506 | * | |
507 | * Update the mailbox registers in the *other* rings with the current seqno. | |
508 | * This acts like a signal in the canonical semaphore. | |
509 | */ | |
1ec14ad3 CW |
510 | static int |
511 | gen6_add_request(struct intel_ring_buffer *ring, | |
c8c99b0f | 512 | u32 *seqno) |
1ec14ad3 | 513 | { |
c8c99b0f BW |
514 | u32 mbox1_reg; |
515 | u32 mbox2_reg; | |
1ec14ad3 CW |
516 | int ret; |
517 | ||
518 | ret = intel_ring_begin(ring, 10); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
c8c99b0f BW |
522 | mbox1_reg = ring->signal_mbox[0]; |
523 | mbox2_reg = ring->signal_mbox[1]; | |
1ec14ad3 | 524 | |
53d227f2 | 525 | *seqno = i915_gem_next_request_seqno(ring); |
c8c99b0f BW |
526 | |
527 | update_mboxes(ring, *seqno, mbox1_reg); | |
528 | update_mboxes(ring, *seqno, mbox2_reg); | |
1ec14ad3 CW |
529 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
530 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
c8c99b0f | 531 | intel_ring_emit(ring, *seqno); |
1ec14ad3 CW |
532 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
533 | intel_ring_advance(ring); | |
534 | ||
1ec14ad3 CW |
535 | return 0; |
536 | } | |
537 | ||
c8c99b0f BW |
538 | /** |
539 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
540 | * | |
541 | * @waiter - ring that is waiting | |
542 | * @signaller - ring which has, or will signal | |
543 | * @seqno - seqno which the waiter will block on | |
544 | */ | |
545 | static int | |
686cb5f9 DV |
546 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
547 | struct intel_ring_buffer *signaller, | |
548 | u32 seqno) | |
1ec14ad3 CW |
549 | { |
550 | int ret; | |
c8c99b0f BW |
551 | u32 dw1 = MI_SEMAPHORE_MBOX | |
552 | MI_SEMAPHORE_COMPARE | | |
553 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 554 | |
1500f7ea BW |
555 | /* Throughout all of the GEM code, seqno passed implies our current |
556 | * seqno is >= the last seqno executed. However for hardware the | |
557 | * comparison is strictly greater than. | |
558 | */ | |
559 | seqno -= 1; | |
560 | ||
686cb5f9 DV |
561 | WARN_ON(signaller->semaphore_register[waiter->id] == |
562 | MI_SEMAPHORE_SYNC_INVALID); | |
563 | ||
c8c99b0f | 564 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
565 | if (ret) |
566 | return ret; | |
567 | ||
686cb5f9 DV |
568 | intel_ring_emit(waiter, |
569 | dw1 | signaller->semaphore_register[waiter->id]); | |
c8c99b0f BW |
570 | intel_ring_emit(waiter, seqno); |
571 | intel_ring_emit(waiter, 0); | |
572 | intel_ring_emit(waiter, MI_NOOP); | |
573 | intel_ring_advance(waiter); | |
1ec14ad3 CW |
574 | |
575 | return 0; | |
576 | } | |
577 | ||
c6df541c CW |
578 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
579 | do { \ | |
fcbc34e4 KG |
580 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
581 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
582 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
583 | intel_ring_emit(ring__, 0); \ | |
584 | intel_ring_emit(ring__, 0); \ | |
585 | } while (0) | |
586 | ||
587 | static int | |
588 | pc_render_add_request(struct intel_ring_buffer *ring, | |
589 | u32 *result) | |
590 | { | |
53d227f2 | 591 | u32 seqno = i915_gem_next_request_seqno(ring); |
c6df541c CW |
592 | struct pipe_control *pc = ring->private; |
593 | u32 scratch_addr = pc->gtt_offset + 128; | |
594 | int ret; | |
595 | ||
596 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
597 | * incoherent with writes to memory, i.e. completely fubar, | |
598 | * so we need to use PIPE_NOTIFY instead. | |
599 | * | |
600 | * However, we also need to workaround the qword write | |
601 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
602 | * memory before requesting an interrupt. | |
603 | */ | |
604 | ret = intel_ring_begin(ring, 32); | |
605 | if (ret) | |
606 | return ret; | |
607 | ||
fcbc34e4 | 608 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
609 | PIPE_CONTROL_WRITE_FLUSH | |
610 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
c6df541c CW |
611 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
612 | intel_ring_emit(ring, seqno); | |
613 | intel_ring_emit(ring, 0); | |
614 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
615 | scratch_addr += 128; /* write to separate cachelines */ | |
616 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
617 | scratch_addr += 128; | |
618 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
619 | scratch_addr += 128; | |
620 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
621 | scratch_addr += 128; | |
622 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
623 | scratch_addr += 128; | |
624 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 625 | |
fcbc34e4 | 626 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
627 | PIPE_CONTROL_WRITE_FLUSH | |
628 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c CW |
629 | PIPE_CONTROL_NOTIFY); |
630 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
631 | intel_ring_emit(ring, seqno); | |
632 | intel_ring_emit(ring, 0); | |
633 | intel_ring_advance(ring); | |
634 | ||
635 | *result = seqno; | |
636 | return 0; | |
637 | } | |
638 | ||
4cd53c0c | 639 | static u32 |
b2eadbc8 | 640 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 641 | { |
4cd53c0c DV |
642 | /* Workaround to force correct ordering between irq and seqno writes on |
643 | * ivb (and maybe also on snb) by reading from a CS register (like | |
644 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 645 | if (!lazy_coherency) |
4cd53c0c DV |
646 | intel_ring_get_active_head(ring); |
647 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
648 | } | |
649 | ||
8187a2b7 | 650 | static u32 |
b2eadbc8 | 651 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 652 | { |
1ec14ad3 CW |
653 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
654 | } | |
655 | ||
c6df541c | 656 | static u32 |
b2eadbc8 | 657 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c CW |
658 | { |
659 | struct pipe_control *pc = ring->private; | |
660 | return pc->cpu_page[0]; | |
661 | } | |
662 | ||
e48d8634 DV |
663 | static bool |
664 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
665 | { | |
666 | struct drm_device *dev = ring->dev; | |
667 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 668 | unsigned long flags; |
e48d8634 DV |
669 | |
670 | if (!dev->irq_enabled) | |
671 | return false; | |
672 | ||
7338aefa | 673 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
674 | if (ring->irq_refcount++ == 0) { |
675 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; | |
676 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
677 | POSTING_READ(GTIMR); | |
678 | } | |
7338aefa | 679 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
680 | |
681 | return true; | |
682 | } | |
683 | ||
684 | static void | |
685 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
686 | { | |
687 | struct drm_device *dev = ring->dev; | |
688 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 689 | unsigned long flags; |
e48d8634 | 690 | |
7338aefa | 691 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
692 | if (--ring->irq_refcount == 0) { |
693 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; | |
694 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
695 | POSTING_READ(GTIMR); | |
696 | } | |
7338aefa | 697 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
698 | } |
699 | ||
b13c2b96 | 700 | static bool |
e3670319 | 701 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 702 | { |
78501eac | 703 | struct drm_device *dev = ring->dev; |
01a03331 | 704 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 705 | unsigned long flags; |
62fdfeaf | 706 | |
b13c2b96 CW |
707 | if (!dev->irq_enabled) |
708 | return false; | |
709 | ||
7338aefa | 710 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
711 | if (ring->irq_refcount++ == 0) { |
712 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
713 | I915_WRITE(IMR, dev_priv->irq_mask); | |
714 | POSTING_READ(IMR); | |
715 | } | |
7338aefa | 716 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
717 | |
718 | return true; | |
62fdfeaf EA |
719 | } |
720 | ||
8187a2b7 | 721 | static void |
e3670319 | 722 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 723 | { |
78501eac | 724 | struct drm_device *dev = ring->dev; |
01a03331 | 725 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 726 | unsigned long flags; |
62fdfeaf | 727 | |
7338aefa | 728 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
729 | if (--ring->irq_refcount == 0) { |
730 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
731 | I915_WRITE(IMR, dev_priv->irq_mask); | |
732 | POSTING_READ(IMR); | |
733 | } | |
7338aefa | 734 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
735 | } |
736 | ||
c2798b19 CW |
737 | static bool |
738 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
739 | { | |
740 | struct drm_device *dev = ring->dev; | |
741 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 742 | unsigned long flags; |
c2798b19 CW |
743 | |
744 | if (!dev->irq_enabled) | |
745 | return false; | |
746 | ||
7338aefa | 747 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
748 | if (ring->irq_refcount++ == 0) { |
749 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
750 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
751 | POSTING_READ16(IMR); | |
752 | } | |
7338aefa | 753 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
754 | |
755 | return true; | |
756 | } | |
757 | ||
758 | static void | |
759 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
760 | { | |
761 | struct drm_device *dev = ring->dev; | |
762 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 763 | unsigned long flags; |
c2798b19 | 764 | |
7338aefa | 765 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
766 | if (--ring->irq_refcount == 0) { |
767 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
768 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
769 | POSTING_READ16(IMR); | |
770 | } | |
7338aefa | 771 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
772 | } |
773 | ||
78501eac | 774 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 775 | { |
4593010b | 776 | struct drm_device *dev = ring->dev; |
78501eac | 777 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
778 | u32 mmio = 0; |
779 | ||
780 | /* The ring status page addresses are no longer next to the rest of | |
781 | * the ring registers as of gen7. | |
782 | */ | |
783 | if (IS_GEN7(dev)) { | |
784 | switch (ring->id) { | |
96154f2f | 785 | case RCS: |
4593010b EA |
786 | mmio = RENDER_HWS_PGA_GEN7; |
787 | break; | |
96154f2f | 788 | case BCS: |
4593010b EA |
789 | mmio = BLT_HWS_PGA_GEN7; |
790 | break; | |
96154f2f | 791 | case VCS: |
4593010b EA |
792 | mmio = BSD_HWS_PGA_GEN7; |
793 | break; | |
794 | } | |
795 | } else if (IS_GEN6(ring->dev)) { | |
796 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
797 | } else { | |
798 | mmio = RING_HWS_PGA(ring->mmio_base); | |
799 | } | |
800 | ||
78501eac CW |
801 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
802 | POSTING_READ(mmio); | |
8187a2b7 ZN |
803 | } |
804 | ||
b72f3acb | 805 | static int |
78501eac CW |
806 | bsd_ring_flush(struct intel_ring_buffer *ring, |
807 | u32 invalidate_domains, | |
808 | u32 flush_domains) | |
d1b851fc | 809 | { |
b72f3acb CW |
810 | int ret; |
811 | ||
b72f3acb CW |
812 | ret = intel_ring_begin(ring, 2); |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | intel_ring_emit(ring, MI_FLUSH); | |
817 | intel_ring_emit(ring, MI_NOOP); | |
818 | intel_ring_advance(ring); | |
819 | return 0; | |
d1b851fc ZN |
820 | } |
821 | ||
3cce469c | 822 | static int |
8620a3a9 | 823 | i9xx_add_request(struct intel_ring_buffer *ring, |
3cce469c | 824 | u32 *result) |
d1b851fc ZN |
825 | { |
826 | u32 seqno; | |
3cce469c CW |
827 | int ret; |
828 | ||
829 | ret = intel_ring_begin(ring, 4); | |
830 | if (ret) | |
831 | return ret; | |
6f392d54 | 832 | |
53d227f2 | 833 | seqno = i915_gem_next_request_seqno(ring); |
6f392d54 | 834 | |
3cce469c CW |
835 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
836 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
837 | intel_ring_emit(ring, seqno); | |
838 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
839 | intel_ring_advance(ring); | |
d1b851fc | 840 | |
3cce469c CW |
841 | *result = seqno; |
842 | return 0; | |
d1b851fc ZN |
843 | } |
844 | ||
0f46832f | 845 | static bool |
25c06300 | 846 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
847 | { |
848 | struct drm_device *dev = ring->dev; | |
01a03331 | 849 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 850 | unsigned long flags; |
0f46832f CW |
851 | |
852 | if (!dev->irq_enabled) | |
853 | return false; | |
854 | ||
4cd53c0c DV |
855 | /* It looks like we need to prevent the gt from suspending while waiting |
856 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
857 | * blt/bsd rings on ivb. */ | |
99ffa162 | 858 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 859 | |
7338aefa | 860 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 861 | if (ring->irq_refcount++ == 0) { |
e1ef7cc2 | 862 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
15b9f80e BW |
863 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
864 | GEN6_RENDER_L3_PARITY_ERROR)); | |
865 | else | |
866 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
f637fde4 DV |
867 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
868 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
869 | POSTING_READ(GTIMR); | |
0f46832f | 870 | } |
7338aefa | 871 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
872 | |
873 | return true; | |
874 | } | |
875 | ||
876 | static void | |
25c06300 | 877 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
878 | { |
879 | struct drm_device *dev = ring->dev; | |
01a03331 | 880 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 881 | unsigned long flags; |
0f46832f | 882 | |
7338aefa | 883 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 884 | if (--ring->irq_refcount == 0) { |
e1ef7cc2 | 885 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
15b9f80e BW |
886 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
887 | else | |
888 | I915_WRITE_IMR(ring, ~0); | |
f637fde4 DV |
889 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
890 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
891 | POSTING_READ(GTIMR); | |
1ec14ad3 | 892 | } |
7338aefa | 893 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 894 | |
99ffa162 | 895 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
896 | } |
897 | ||
d1b851fc | 898 | static int |
fb3256da | 899 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 900 | { |
e1f99ce6 | 901 | int ret; |
78501eac | 902 | |
e1f99ce6 CW |
903 | ret = intel_ring_begin(ring, 2); |
904 | if (ret) | |
905 | return ret; | |
906 | ||
78501eac | 907 | intel_ring_emit(ring, |
65f56876 CW |
908 | MI_BATCH_BUFFER_START | |
909 | MI_BATCH_GTT | | |
78501eac | 910 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 911 | intel_ring_emit(ring, offset); |
78501eac CW |
912 | intel_ring_advance(ring); |
913 | ||
d1b851fc ZN |
914 | return 0; |
915 | } | |
916 | ||
8187a2b7 | 917 | static int |
fb3256da | 918 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 919 | u32 offset, u32 len) |
62fdfeaf | 920 | { |
c4e7a414 | 921 | int ret; |
62fdfeaf | 922 | |
fb3256da DV |
923 | ret = intel_ring_begin(ring, 4); |
924 | if (ret) | |
925 | return ret; | |
62fdfeaf | 926 | |
fb3256da DV |
927 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
928 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
929 | intel_ring_emit(ring, offset + len - 8); | |
930 | intel_ring_emit(ring, 0); | |
931 | intel_ring_advance(ring); | |
e1f99ce6 | 932 | |
fb3256da DV |
933 | return 0; |
934 | } | |
935 | ||
936 | static int | |
937 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
938 | u32 offset, u32 len) | |
939 | { | |
940 | int ret; | |
941 | ||
942 | ret = intel_ring_begin(ring, 2); | |
943 | if (ret) | |
944 | return ret; | |
945 | ||
65f56876 | 946 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
fb3256da | 947 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
c4e7a414 | 948 | intel_ring_advance(ring); |
62fdfeaf | 949 | |
62fdfeaf EA |
950 | return 0; |
951 | } | |
952 | ||
78501eac | 953 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 954 | { |
05394f39 | 955 | struct drm_i915_gem_object *obj; |
62fdfeaf | 956 | |
8187a2b7 ZN |
957 | obj = ring->status_page.obj; |
958 | if (obj == NULL) | |
62fdfeaf | 959 | return; |
62fdfeaf | 960 | |
05394f39 | 961 | kunmap(obj->pages[0]); |
62fdfeaf | 962 | i915_gem_object_unpin(obj); |
05394f39 | 963 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 964 | ring->status_page.obj = NULL; |
62fdfeaf EA |
965 | } |
966 | ||
78501eac | 967 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 968 | { |
78501eac | 969 | struct drm_device *dev = ring->dev; |
05394f39 | 970 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
971 | int ret; |
972 | ||
62fdfeaf EA |
973 | obj = i915_gem_alloc_object(dev, 4096); |
974 | if (obj == NULL) { | |
975 | DRM_ERROR("Failed to allocate status page\n"); | |
976 | ret = -ENOMEM; | |
977 | goto err; | |
978 | } | |
e4ffd173 CW |
979 | |
980 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 981 | |
75e9e915 | 982 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 983 | if (ret != 0) { |
62fdfeaf EA |
984 | goto err_unref; |
985 | } | |
986 | ||
05394f39 CW |
987 | ring->status_page.gfx_addr = obj->gtt_offset; |
988 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 989 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 990 | ret = -ENOMEM; |
62fdfeaf EA |
991 | goto err_unpin; |
992 | } | |
8187a2b7 ZN |
993 | ring->status_page.obj = obj; |
994 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 995 | |
78501eac | 996 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
997 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
998 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
999 | |
1000 | return 0; | |
1001 | ||
1002 | err_unpin: | |
1003 | i915_gem_object_unpin(obj); | |
1004 | err_unref: | |
05394f39 | 1005 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1006 | err: |
8187a2b7 | 1007 | return ret; |
62fdfeaf EA |
1008 | } |
1009 | ||
c43b5634 BW |
1010 | static int intel_init_ring_buffer(struct drm_device *dev, |
1011 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1012 | { |
05394f39 | 1013 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1014 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1015 | int ret; |
1016 | ||
8187a2b7 | 1017 | ring->dev = dev; |
23bc5982 CW |
1018 | INIT_LIST_HEAD(&ring->active_list); |
1019 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1020 | ring->size = 32 * PAGE_SIZE; |
0dc79fb2 | 1021 | |
b259f673 | 1022 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1023 | |
8187a2b7 | 1024 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1025 | ret = init_status_page(ring); |
8187a2b7 ZN |
1026 | if (ret) |
1027 | return ret; | |
1028 | } | |
62fdfeaf | 1029 | |
8187a2b7 | 1030 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
1031 | if (obj == NULL) { |
1032 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1033 | ret = -ENOMEM; |
dd785e35 | 1034 | goto err_hws; |
62fdfeaf | 1035 | } |
62fdfeaf | 1036 | |
05394f39 | 1037 | ring->obj = obj; |
8187a2b7 | 1038 | |
75e9e915 | 1039 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
1040 | if (ret) |
1041 | goto err_unref; | |
62fdfeaf | 1042 | |
3eef8918 CW |
1043 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1044 | if (ret) | |
1045 | goto err_unpin; | |
1046 | ||
dd2757f8 DV |
1047 | ring->virtual_start = |
1048 | ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, | |
1049 | ring->size); | |
4225d0f2 | 1050 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1051 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1052 | ret = -EINVAL; |
dd785e35 | 1053 | goto err_unpin; |
62fdfeaf EA |
1054 | } |
1055 | ||
78501eac | 1056 | ret = ring->init(ring); |
dd785e35 CW |
1057 | if (ret) |
1058 | goto err_unmap; | |
62fdfeaf | 1059 | |
55249baa CW |
1060 | /* Workaround an erratum on the i830 which causes a hang if |
1061 | * the TAIL pointer points to within the last 2 cachelines | |
1062 | * of the buffer. | |
1063 | */ | |
1064 | ring->effective_size = ring->size; | |
27c1cbd0 | 1065 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1066 | ring->effective_size -= 128; |
1067 | ||
c584fe47 | 1068 | return 0; |
dd785e35 CW |
1069 | |
1070 | err_unmap: | |
4225d0f2 | 1071 | iounmap(ring->virtual_start); |
dd785e35 CW |
1072 | err_unpin: |
1073 | i915_gem_object_unpin(obj); | |
1074 | err_unref: | |
05394f39 CW |
1075 | drm_gem_object_unreference(&obj->base); |
1076 | ring->obj = NULL; | |
dd785e35 | 1077 | err_hws: |
78501eac | 1078 | cleanup_status_page(ring); |
8187a2b7 | 1079 | return ret; |
62fdfeaf EA |
1080 | } |
1081 | ||
78501eac | 1082 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1083 | { |
33626e6a CW |
1084 | struct drm_i915_private *dev_priv; |
1085 | int ret; | |
1086 | ||
05394f39 | 1087 | if (ring->obj == NULL) |
62fdfeaf EA |
1088 | return; |
1089 | ||
33626e6a CW |
1090 | /* Disable the ring buffer. The ring must be idle at this point */ |
1091 | dev_priv = ring->dev->dev_private; | |
96f298aa | 1092 | ret = intel_wait_ring_idle(ring); |
29ee3991 CW |
1093 | if (ret) |
1094 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
1095 | ring->name, ret); | |
1096 | ||
33626e6a CW |
1097 | I915_WRITE_CTL(ring, 0); |
1098 | ||
4225d0f2 | 1099 | iounmap(ring->virtual_start); |
62fdfeaf | 1100 | |
05394f39 CW |
1101 | i915_gem_object_unpin(ring->obj); |
1102 | drm_gem_object_unreference(&ring->obj->base); | |
1103 | ring->obj = NULL; | |
78501eac | 1104 | |
8d19215b ZN |
1105 | if (ring->cleanup) |
1106 | ring->cleanup(ring); | |
1107 | ||
78501eac | 1108 | cleanup_status_page(ring); |
62fdfeaf EA |
1109 | } |
1110 | ||
78501eac | 1111 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1112 | { |
4225d0f2 | 1113 | uint32_t __iomem *virt; |
55249baa | 1114 | int rem = ring->size - ring->tail; |
62fdfeaf | 1115 | |
8187a2b7 | 1116 | if (ring->space < rem) { |
78501eac | 1117 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
1118 | if (ret) |
1119 | return ret; | |
1120 | } | |
62fdfeaf | 1121 | |
4225d0f2 DV |
1122 | virt = ring->virtual_start + ring->tail; |
1123 | rem /= 4; | |
1124 | while (rem--) | |
1125 | iowrite32(MI_NOOP, virt++); | |
62fdfeaf | 1126 | |
8187a2b7 | 1127 | ring->tail = 0; |
c7dca47b | 1128 | ring->space = ring_space(ring); |
62fdfeaf EA |
1129 | |
1130 | return 0; | |
1131 | } | |
1132 | ||
a71d8d94 CW |
1133 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1134 | { | |
a71d8d94 CW |
1135 | int ret; |
1136 | ||
199b2bc2 | 1137 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1138 | if (!ret) |
1139 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1140 | |
1141 | return ret; | |
1142 | } | |
1143 | ||
1144 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1145 | { | |
1146 | struct drm_i915_gem_request *request; | |
1147 | u32 seqno = 0; | |
1148 | int ret; | |
1149 | ||
1150 | i915_gem_retire_requests_ring(ring); | |
1151 | ||
1152 | if (ring->last_retired_head != -1) { | |
1153 | ring->head = ring->last_retired_head; | |
1154 | ring->last_retired_head = -1; | |
1155 | ring->space = ring_space(ring); | |
1156 | if (ring->space >= n) | |
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | list_for_each_entry(request, &ring->request_list, list) { | |
1161 | int space; | |
1162 | ||
1163 | if (request->tail == -1) | |
1164 | continue; | |
1165 | ||
1166 | space = request->tail - (ring->tail + 8); | |
1167 | if (space < 0) | |
1168 | space += ring->size; | |
1169 | if (space >= n) { | |
1170 | seqno = request->seqno; | |
1171 | break; | |
1172 | } | |
1173 | ||
1174 | /* Consume this request in case we need more space than | |
1175 | * is available and so need to prevent a race between | |
1176 | * updating last_retired_head and direct reads of | |
1177 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1178 | */ | |
1179 | request->tail = -1; | |
1180 | } | |
1181 | ||
1182 | if (seqno == 0) | |
1183 | return -ENOSPC; | |
1184 | ||
1185 | ret = intel_ring_wait_seqno(ring, seqno); | |
1186 | if (ret) | |
1187 | return ret; | |
1188 | ||
1189 | if (WARN_ON(ring->last_retired_head == -1)) | |
1190 | return -ENOSPC; | |
1191 | ||
1192 | ring->head = ring->last_retired_head; | |
1193 | ring->last_retired_head = -1; | |
1194 | ring->space = ring_space(ring); | |
1195 | if (WARN_ON(ring->space < n)) | |
1196 | return -ENOSPC; | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
78501eac | 1201 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1202 | { |
78501eac | 1203 | struct drm_device *dev = ring->dev; |
cae5852d | 1204 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1205 | unsigned long end; |
a71d8d94 | 1206 | int ret; |
c7dca47b | 1207 | |
a71d8d94 CW |
1208 | ret = intel_ring_wait_request(ring, n); |
1209 | if (ret != -ENOSPC) | |
1210 | return ret; | |
1211 | ||
db53a302 | 1212 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1213 | /* With GEM the hangcheck timer should kick us out of the loop, |
1214 | * leaving it early runs the risk of corrupting GEM state (due | |
1215 | * to running on almost untested codepaths). But on resume | |
1216 | * timers don't work yet, so prevent a complete hang in that | |
1217 | * case by choosing an insanely large timeout. */ | |
1218 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1219 | |
8187a2b7 | 1220 | do { |
c7dca47b CW |
1221 | ring->head = I915_READ_HEAD(ring); |
1222 | ring->space = ring_space(ring); | |
62fdfeaf | 1223 | if (ring->space >= n) { |
db53a302 | 1224 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1225 | return 0; |
1226 | } | |
1227 | ||
1228 | if (dev->primary->master) { | |
1229 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1230 | if (master_priv->sarea_priv) | |
1231 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1232 | } | |
d1b851fc | 1233 | |
e60a0b10 | 1234 | msleep(1); |
d6b2c790 DV |
1235 | |
1236 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); | |
1237 | if (ret) | |
1238 | return ret; | |
8187a2b7 | 1239 | } while (!time_after(jiffies, end)); |
db53a302 | 1240 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1241 | return -EBUSY; |
1242 | } | |
62fdfeaf | 1243 | |
e1f99ce6 CW |
1244 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1245 | int num_dwords) | |
8187a2b7 | 1246 | { |
de2b9985 | 1247 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
be26a10b | 1248 | int n = 4*num_dwords; |
e1f99ce6 | 1249 | int ret; |
78501eac | 1250 | |
de2b9985 DV |
1251 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
1252 | if (ret) | |
1253 | return ret; | |
21dd3734 | 1254 | |
55249baa | 1255 | if (unlikely(ring->tail + n > ring->effective_size)) { |
e1f99ce6 CW |
1256 | ret = intel_wrap_ring_buffer(ring); |
1257 | if (unlikely(ret)) | |
1258 | return ret; | |
1259 | } | |
78501eac | 1260 | |
e1f99ce6 CW |
1261 | if (unlikely(ring->space < n)) { |
1262 | ret = intel_wait_ring_buffer(ring, n); | |
1263 | if (unlikely(ret)) | |
1264 | return ret; | |
1265 | } | |
d97ed339 CW |
1266 | |
1267 | ring->space -= n; | |
e1f99ce6 | 1268 | return 0; |
8187a2b7 | 1269 | } |
62fdfeaf | 1270 | |
78501eac | 1271 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1272 | { |
e5eb3d63 DV |
1273 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1274 | ||
d97ed339 | 1275 | ring->tail &= ring->size - 1; |
e5eb3d63 DV |
1276 | if (dev_priv->stop_rings & intel_ring_flag(ring)) |
1277 | return; | |
78501eac | 1278 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1279 | } |
62fdfeaf | 1280 | |
881f47b6 | 1281 | |
78501eac | 1282 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1283 | u32 value) |
881f47b6 | 1284 | { |
0206e353 | 1285 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1286 | |
1287 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1288 | |
1289 | /* Disable notification that the ring is IDLE. The GT | |
1290 | * will then assume that it is busy and bring it out of rc6. | |
1291 | */ | |
0206e353 | 1292 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1293 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1294 | ||
1295 | /* Clear the context id. Here be magic! */ | |
1296 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1297 | |
12f55818 | 1298 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1299 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1300 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1301 | 50)) | |
1302 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1303 | |
12f55818 | 1304 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1305 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1306 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1307 | ||
1308 | /* Let the ring send IDLE messages to the GT again, | |
1309 | * and so let it sleep to conserve power when idle. | |
1310 | */ | |
0206e353 | 1311 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1312 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1313 | } |
1314 | ||
b72f3acb | 1315 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1316 | u32 invalidate, u32 flush) |
881f47b6 | 1317 | { |
71a77e07 | 1318 | uint32_t cmd; |
b72f3acb CW |
1319 | int ret; |
1320 | ||
b72f3acb CW |
1321 | ret = intel_ring_begin(ring, 4); |
1322 | if (ret) | |
1323 | return ret; | |
1324 | ||
71a77e07 CW |
1325 | cmd = MI_FLUSH_DW; |
1326 | if (invalidate & I915_GEM_GPU_DOMAINS) | |
1327 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | |
1328 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1329 | intel_ring_emit(ring, 0); |
1330 | intel_ring_emit(ring, 0); | |
71a77e07 | 1331 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1332 | intel_ring_advance(ring); |
1333 | return 0; | |
881f47b6 XH |
1334 | } |
1335 | ||
1336 | static int | |
78501eac | 1337 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 1338 | u32 offset, u32 len) |
881f47b6 | 1339 | { |
0206e353 | 1340 | int ret; |
ab6f8e32 | 1341 | |
0206e353 AJ |
1342 | ret = intel_ring_begin(ring, 2); |
1343 | if (ret) | |
1344 | return ret; | |
e1f99ce6 | 1345 | |
0206e353 AJ |
1346 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1347 | /* bit0-7 is the length on GEN6+ */ | |
1348 | intel_ring_emit(ring, offset); | |
1349 | intel_ring_advance(ring); | |
ab6f8e32 | 1350 | |
0206e353 | 1351 | return 0; |
881f47b6 XH |
1352 | } |
1353 | ||
549f7365 CW |
1354 | /* Blitter support (SandyBridge+) */ |
1355 | ||
b72f3acb | 1356 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1357 | u32 invalidate, u32 flush) |
8d19215b | 1358 | { |
71a77e07 | 1359 | uint32_t cmd; |
b72f3acb CW |
1360 | int ret; |
1361 | ||
6a233c78 | 1362 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1363 | if (ret) |
1364 | return ret; | |
1365 | ||
71a77e07 CW |
1366 | cmd = MI_FLUSH_DW; |
1367 | if (invalidate & I915_GEM_DOMAIN_RENDER) | |
1368 | cmd |= MI_INVALIDATE_TLB; | |
1369 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1370 | intel_ring_emit(ring, 0); |
1371 | intel_ring_emit(ring, 0); | |
71a77e07 | 1372 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1373 | intel_ring_advance(ring); |
1374 | return 0; | |
8d19215b ZN |
1375 | } |
1376 | ||
5c1143bb XH |
1377 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1378 | { | |
1379 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1380 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1381 | |
59465b5f DV |
1382 | ring->name = "render ring"; |
1383 | ring->id = RCS; | |
1384 | ring->mmio_base = RENDER_RING_BASE; | |
1385 | ||
1ec14ad3 CW |
1386 | if (INTEL_INFO(dev)->gen >= 6) { |
1387 | ring->add_request = gen6_add_request; | |
8d315287 | 1388 | ring->flush = gen6_render_ring_flush; |
6c6cf5aa CW |
1389 | if (INTEL_INFO(dev)->gen == 6) |
1390 | ring->flush = gen6_render_ring_flush__wa; | |
25c06300 BW |
1391 | ring->irq_get = gen6_ring_get_irq; |
1392 | ring->irq_put = gen6_ring_put_irq; | |
6a848ccb | 1393 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
4cd53c0c | 1394 | ring->get_seqno = gen6_ring_get_seqno; |
686cb5f9 | 1395 | ring->sync_to = gen6_ring_sync; |
59465b5f DV |
1396 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
1397 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; | |
1398 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; | |
1399 | ring->signal_mbox[0] = GEN6_VRSYNC; | |
1400 | ring->signal_mbox[1] = GEN6_BRSYNC; | |
c6df541c CW |
1401 | } else if (IS_GEN5(dev)) { |
1402 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1403 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1404 | ring->get_seqno = pc_render_get_seqno; |
e48d8634 DV |
1405 | ring->irq_get = gen5_ring_get_irq; |
1406 | ring->irq_put = gen5_ring_put_irq; | |
e3670319 | 1407 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
59465b5f | 1408 | } else { |
8620a3a9 | 1409 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1410 | if (INTEL_INFO(dev)->gen < 4) |
1411 | ring->flush = gen2_render_ring_flush; | |
1412 | else | |
1413 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1414 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1415 | if (IS_GEN2(dev)) { |
1416 | ring->irq_get = i8xx_ring_get_irq; | |
1417 | ring->irq_put = i8xx_ring_put_irq; | |
1418 | } else { | |
1419 | ring->irq_get = i9xx_ring_get_irq; | |
1420 | ring->irq_put = i9xx_ring_put_irq; | |
1421 | } | |
e3670319 | 1422 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1423 | } |
59465b5f | 1424 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1425 | if (INTEL_INFO(dev)->gen >= 6) |
1426 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
1427 | else if (INTEL_INFO(dev)->gen >= 4) | |
1428 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1429 | else if (IS_I830(dev) || IS_845G(dev)) | |
1430 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1431 | else | |
1432 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1433 | ring->init = init_render_ring; |
1434 | ring->cleanup = render_ring_cleanup; | |
1435 | ||
5c1143bb XH |
1436 | |
1437 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1438 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1439 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1440 | } |
1441 | ||
1ec14ad3 | 1442 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1443 | } |
1444 | ||
e8616b6c CW |
1445 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1446 | { | |
1447 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1448 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
1449 | ||
59465b5f DV |
1450 | ring->name = "render ring"; |
1451 | ring->id = RCS; | |
1452 | ring->mmio_base = RENDER_RING_BASE; | |
1453 | ||
e8616b6c | 1454 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1455 | /* non-kms not supported on gen6+ */ |
1456 | return -ENODEV; | |
e8616b6c | 1457 | } |
28f0cbf7 DV |
1458 | |
1459 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1460 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1461 | * the special gen5 functions. */ | |
1462 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1463 | if (INTEL_INFO(dev)->gen < 4) |
1464 | ring->flush = gen2_render_ring_flush; | |
1465 | else | |
1466 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1467 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1468 | if (IS_GEN2(dev)) { |
1469 | ring->irq_get = i8xx_ring_get_irq; | |
1470 | ring->irq_put = i8xx_ring_put_irq; | |
1471 | } else { | |
1472 | ring->irq_get = i9xx_ring_get_irq; | |
1473 | ring->irq_put = i9xx_ring_put_irq; | |
1474 | } | |
28f0cbf7 | 1475 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1476 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1477 | if (INTEL_INFO(dev)->gen >= 4) |
1478 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1479 | else if (IS_I830(dev) || IS_845G(dev)) | |
1480 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1481 | else | |
1482 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1483 | ring->init = init_render_ring; |
1484 | ring->cleanup = render_ring_cleanup; | |
e8616b6c | 1485 | |
f3234706 KP |
1486 | if (!I915_NEED_GFX_HWS(dev)) |
1487 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1488 | ||
e8616b6c CW |
1489 | ring->dev = dev; |
1490 | INIT_LIST_HEAD(&ring->active_list); | |
1491 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1492 | |
1493 | ring->size = size; | |
1494 | ring->effective_size = ring->size; | |
1495 | if (IS_I830(ring->dev)) | |
1496 | ring->effective_size -= 128; | |
1497 | ||
4225d0f2 DV |
1498 | ring->virtual_start = ioremap_wc(start, size); |
1499 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1500 | DRM_ERROR("can not ioremap virtual address for" |
1501 | " ring buffer\n"); | |
1502 | return -ENOMEM; | |
1503 | } | |
1504 | ||
e8616b6c CW |
1505 | return 0; |
1506 | } | |
1507 | ||
5c1143bb XH |
1508 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1509 | { | |
1510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1511 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1512 | |
58fa3835 DV |
1513 | ring->name = "bsd ring"; |
1514 | ring->id = VCS; | |
1515 | ||
0fd2c201 | 1516 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1517 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1518 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1519 | /* gen6 bsd needs a special wa for tail updates */ |
1520 | if (IS_GEN6(dev)) | |
1521 | ring->write_tail = gen6_bsd_ring_write_tail; | |
58fa3835 DV |
1522 | ring->flush = gen6_ring_flush; |
1523 | ring->add_request = gen6_add_request; | |
1524 | ring->get_seqno = gen6_ring_get_seqno; | |
1525 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; | |
1526 | ring->irq_get = gen6_ring_get_irq; | |
1527 | ring->irq_put = gen6_ring_put_irq; | |
1528 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1529 | ring->sync_to = gen6_ring_sync; |
58fa3835 DV |
1530 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
1531 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; | |
1532 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; | |
1533 | ring->signal_mbox[0] = GEN6_RVSYNC; | |
1534 | ring->signal_mbox[1] = GEN6_BVSYNC; | |
1535 | } else { | |
1536 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1537 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1538 | ring->add_request = i9xx_add_request; |
58fa3835 | 1539 | ring->get_seqno = ring_get_seqno; |
e48d8634 | 1540 | if (IS_GEN5(dev)) { |
e3670319 | 1541 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
e48d8634 DV |
1542 | ring->irq_get = gen5_ring_get_irq; |
1543 | ring->irq_put = gen5_ring_put_irq; | |
1544 | } else { | |
e3670319 | 1545 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1546 | ring->irq_get = i9xx_ring_get_irq; |
1547 | ring->irq_put = i9xx_ring_put_irq; | |
1548 | } | |
fb3256da | 1549 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1550 | } |
1551 | ring->init = init_ring_common; | |
1552 | ||
5c1143bb | 1553 | |
1ec14ad3 | 1554 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1555 | } |
549f7365 CW |
1556 | |
1557 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1558 | { | |
1559 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1560 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1561 | |
3535d9dd DV |
1562 | ring->name = "blitter ring"; |
1563 | ring->id = BCS; | |
1564 | ||
1565 | ring->mmio_base = BLT_RING_BASE; | |
1566 | ring->write_tail = ring_write_tail; | |
1567 | ring->flush = blt_ring_flush; | |
1568 | ring->add_request = gen6_add_request; | |
1569 | ring->get_seqno = gen6_ring_get_seqno; | |
1570 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; | |
1571 | ring->irq_get = gen6_ring_get_irq; | |
1572 | ring->irq_put = gen6_ring_put_irq; | |
1573 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1574 | ring->sync_to = gen6_ring_sync; |
3535d9dd DV |
1575 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
1576 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; | |
1577 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; | |
1578 | ring->signal_mbox[0] = GEN6_RBSYNC; | |
1579 | ring->signal_mbox[1] = GEN6_VBSYNC; | |
1580 | ring->init = init_ring_common; | |
549f7365 | 1581 | |
1ec14ad3 | 1582 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1583 | } |
a7b9761d CW |
1584 | |
1585 | int | |
1586 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
1587 | { | |
1588 | int ret; | |
1589 | ||
1590 | if (!ring->gpu_caches_dirty) | |
1591 | return 0; | |
1592 | ||
1593 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1594 | if (ret) | |
1595 | return ret; | |
1596 | ||
1597 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1598 | ||
1599 | ring->gpu_caches_dirty = false; | |
1600 | return 0; | |
1601 | } | |
1602 | ||
1603 | int | |
1604 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
1605 | { | |
1606 | uint32_t flush_domains; | |
1607 | int ret; | |
1608 | ||
1609 | flush_domains = 0; | |
1610 | if (ring->gpu_caches_dirty) | |
1611 | flush_domains = I915_GEM_GPU_DOMAINS; | |
1612 | ||
1613 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1614 | if (ret) | |
1615 | return ret; | |
1616 | ||
1617 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1618 | ||
1619 | ring->gpu_caches_dirty = false; | |
1620 | return 0; | |
1621 | } |