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drm/i915: Update ring->dispatch_execbuffer() to take a request structure
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
6258fbe2 84static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a84c3ae1 94gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
a84c3ae1 98 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
31b14c9f 103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
109 ret = intel_ring_begin(ring, 2);
110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118}
119
120static int
a84c3ae1 121gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 122 u32 invalidate_domains,
123 u32 flush_domains)
62fdfeaf 124{
a84c3ae1 125 struct intel_engine_cs *ring = req->ring;
78501eac 126 struct drm_device *dev = ring->dev;
6f392d54 127 u32 cmd;
b72f3acb 128 int ret;
6f392d54 129
36d527de
CW		 130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 160 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
62fdfeaf 163
36d527de
CW		 164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
70eac33e 167
36d527de
CW		 168 ret = intel_ring_begin(ring, 2);
169 if (ret)
170 return ret;
b72f3acb 171
36d527de
CW		 172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
b72f3acb
CW		 175
176 return 0;
8187a2b7
ZN		 177}
178
8d315287
JB		 179/**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216static int
f2cf1fcc 217intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 218{
f2cf1fcc 219 struct intel_engine_cs *ring = req->ring;
18393f63 220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 221 int ret;
222
223
224 ret = intel_ring_begin(ring, 6);
225 if (ret)
226 return ret;
227
228 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
229 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
230 PIPE_CONTROL_STALL_AT_SCOREBOARD);
231 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
232 intel_ring_emit(ring, 0); /* low dword */
233 intel_ring_emit(ring, 0); /* high dword */
234 intel_ring_emit(ring, MI_NOOP);
235 intel_ring_advance(ring);
236
237 ret = intel_ring_begin(ring, 6);
238 if (ret)
239 return ret;
240
241 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
242 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
243 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, 0);
246 intel_ring_emit(ring, MI_NOOP);
247 intel_ring_advance(ring);
248
249 return 0;
250}
251
252static int
a84c3ae1
JH		 253gen6_render_ring_flush(struct drm_i915_gem_request *req,
254 u32 invalidate_domains, u32 flush_domains)
8d315287 255{
a84c3ae1 256 struct intel_engine_cs *ring = req->ring;
8d315287 257 u32 flags = 0;
18393f63 258 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 259 int ret;
260
b3111509 261 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 262 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 263 if (ret)
264 return ret;
265
8d315287
JB		 266 /* Just flush everything. Experiments have shown that reducing the
267 * number of bits based on the write domains has little performance
268 * impact.
269 */
7d54a904
CW		 270 if (flush_domains) {
271 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
272 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
273 /*
274 * Ensure that any following seqno writes only happen
275 * when the render cache is indeed flushed.
276 */
97f209bc 277 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 278 }
279 if (invalidate_domains) {
280 flags |= PIPE_CONTROL_TLB_INVALIDATE;
281 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
285 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
286 /*
287 * TLB invalidate requires a post-sync write.
288 */
3ac78313 289 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 290 }
8d315287 291
6c6cf5aa 292 ret = intel_ring_begin(ring, 4);
8d315287
JB		 293 if (ret)
294 return ret;
295
6c6cf5aa 296 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 297 intel_ring_emit(ring, flags);
298 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 299 intel_ring_emit(ring, 0);
8d315287
JB		 300 intel_ring_advance(ring);
301
302 return 0;
303}
304
f3987631 305static int
f2cf1fcc 306gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 307{
f2cf1fcc 308 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 309 int ret;
310
311 ret = intel_ring_begin(ring, 4);
312 if (ret)
313 return ret;
314
315 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
316 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
317 PIPE_CONTROL_STALL_AT_SCOREBOARD);
318 intel_ring_emit(ring, 0);
319 intel_ring_emit(ring, 0);
320 intel_ring_advance(ring);
321
322 return 0;
323}
324
4772eaeb 325static int
a84c3ae1 326gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 327 u32 invalidate_domains, u32 flush_domains)
328{
a84c3ae1 329 struct intel_engine_cs *ring = req->ring;
4772eaeb 330 u32 flags = 0;
18393f63 331 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 332 int ret;
333
f3987631
PZ		 334 /*
335 * Ensure that any following seqno writes only happen when the render
336 * cache is indeed flushed.
337 *
338 * Workaround: 4th PIPE_CONTROL command (except the ones with only
339 * read-cache invalidate bits set) must have the CS_STALL bit set. We
340 * don't try to be clever and just set it unconditionally.
341 */
342 flags |= PIPE_CONTROL_CS_STALL;
343
4772eaeb
PZ		 344 /* Just flush everything. Experiments have shown that reducing the
345 * number of bits based on the write domains has little performance
346 * impact.
347 */
348 if (flush_domains) {
349 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
350 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 351 }
352 if (invalidate_domains) {
353 flags |= PIPE_CONTROL_TLB_INVALIDATE;
354 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
358 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 359 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 360 /*
361 * TLB invalidate requires a post-sync write.
362 */
363 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 364 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 365
add284a3
CW		 366 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
367
f3987631
PZ		 368 /* Workaround: we must issue a pipe_control with CS-stall bit
369 * set before a pipe_control command that has the state cache
370 * invalidate bit set. */
f2cf1fcc 371 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 372 }
373
374 ret = intel_ring_begin(ring, 4);
375 if (ret)
376 return ret;
377
378 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
379 intel_ring_emit(ring, flags);
b9e1faa7 380 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 381 intel_ring_emit(ring, 0);
382 intel_ring_advance(ring);
383
384 return 0;
385}
386
884ceace 387static int
f2cf1fcc 388gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 389 u32 flags, u32 scratch_addr)
390{
f2cf1fcc 391 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 392 int ret;
393
394 ret = intel_ring_begin(ring, 6);
395 if (ret)
396 return ret;
397
398 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
399 intel_ring_emit(ring, flags);
400 intel_ring_emit(ring, scratch_addr);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_emit(ring, 0);
404 intel_ring_advance(ring);
405
406 return 0;
407}
408
a5f3d68e 409static int
a84c3ae1 410gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 411 u32 invalidate_domains, u32 flush_domains)
412{
413 u32 flags = 0;
f2cf1fcc 414 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 415 int ret;
a5f3d68e
BW		 416
417 flags |= PIPE_CONTROL_CS_STALL;
418
419 if (flush_domains) {
420 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
421 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
422 }
423 if (invalidate_domains) {
424 flags |= PIPE_CONTROL_TLB_INVALIDATE;
425 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
430 flags |= PIPE_CONTROL_QW_WRITE;
431 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 432
433 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 434 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 435 PIPE_CONTROL_CS_STALL |
436 PIPE_CONTROL_STALL_AT_SCOREBOARD,
437 0);
438 if (ret)
439 return ret;
a5f3d68e
BW		 440 }
441
f2cf1fcc 442 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 443}
444
a4872ba6 445static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 446 u32 value)
d46eefa2 447{
4640c4ff 448 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 449 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 450}
451
a4872ba6 452u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 453{
4640c4ff 454 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 455 u64 acthd;
8187a2b7 456
50877445
CW		 457 if (INTEL_INFO(ring->dev)->gen >= 8)
458 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
459 RING_ACTHD_UDW(ring->mmio_base));
460 else if (INTEL_INFO(ring->dev)->gen >= 4)
461 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
462 else
463 acthd = I915_READ(ACTHD);
464
465 return acthd;
8187a2b7
ZN		 466}
467
a4872ba6 468static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 469{
470 struct drm_i915_private *dev_priv = ring->dev->dev_private;
471 u32 addr;
472
473 addr = dev_priv->status_page_dmah->busaddr;
474 if (INTEL_INFO(ring->dev)->gen >= 4)
475 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
476 I915_WRITE(HWS_PGA, addr);
477}
478
af75f269
DL		 479static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
480{
481 struct drm_device *dev = ring->dev;
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 mmio = 0;
484
485 /* The ring status page addresses are no longer next to the rest of
486 * the ring registers as of gen7.
487 */
488 if (IS_GEN7(dev)) {
489 switch (ring->id) {
490 case RCS:
491 mmio = RENDER_HWS_PGA_GEN7;
492 break;
493 case BCS:
494 mmio = BLT_HWS_PGA_GEN7;
495 break;
496 /*
497 * VCS2 actually doesn't exist on Gen7. Only shut up
498 * gcc switch check warning
499 */
500 case VCS2:
501 case VCS:
502 mmio = BSD_HWS_PGA_GEN7;
503 break;
504 case VECS:
505 mmio = VEBOX_HWS_PGA_GEN7;
506 break;
507 }
508 } else if (IS_GEN6(ring->dev)) {
509 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
510 } else {
511 /* XXX: gen8 returns to sanity */
512 mmio = RING_HWS_PGA(ring->mmio_base);
513 }
514
515 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
516 POSTING_READ(mmio);
517
518 /*
519 * Flush the TLB for this page
520 *
521 * FIXME: These two bits have disappeared on gen8, so a question
522 * arises: do we still need this and if so how should we go about
523 * invalidating the TLB?
524 */
525 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
526 u32 reg = RING_INSTPM(ring->mmio_base);
527
528 /* ring should be idle before issuing a sync flush*/
529 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
530
531 I915_WRITE(reg,
532 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
533 INSTPM_SYNC_FLUSH));
534 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
535 1000))
536 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
537 ring->name);
538 }
539}
540
a4872ba6 541static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 542{
9991ae78 543 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 544
9991ae78
CW		 545 if (!IS_GEN2(ring->dev)) {
546 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 547 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
548 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 549 /* Sometimes we observe that the idle flag is not
550 * set even though the ring is empty. So double
551 * check before giving up.
552 */
553 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
554 return false;
9991ae78
CW		 555 }
556 }
b7884eb4 557
7f2ab699 558 I915_WRITE_CTL(ring, 0);
570ef608 559 I915_WRITE_HEAD(ring, 0);
78501eac 560 ring->write_tail(ring, 0);
8187a2b7 561
9991ae78
CW		 562 if (!IS_GEN2(ring->dev)) {
563 (void)I915_READ_CTL(ring);
564 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
565 }
a51435a3 566
9991ae78
CW		 567 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
568}
8187a2b7 569
a4872ba6 570static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 571{
572 struct drm_device *dev = ring->dev;
573 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 574 struct intel_ringbuffer *ringbuf = ring->buffer;
575 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 576 int ret = 0;
577
59bad947 578 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 579
580 if (!stop_ring(ring)) {
581 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 582 DRM_DEBUG_KMS("%s head not reset to zero "
583 "ctl %08x head %08x tail %08x start %08x\n",
584 ring->name,
585 I915_READ_CTL(ring),
586 I915_READ_HEAD(ring),
587 I915_READ_TAIL(ring),
588 I915_READ_START(ring));
8187a2b7 589
9991ae78 590 if (!stop_ring(ring)) {
6fd0d56e
CW		 591 DRM_ERROR("failed to set %s head to zero "
592 "ctl %08x head %08x tail %08x start %08x\n",
593 ring->name,
594 I915_READ_CTL(ring),
595 I915_READ_HEAD(ring),
596 I915_READ_TAIL(ring),
597 I915_READ_START(ring));
9991ae78
CW		 598 ret = -EIO;
599 goto out;
6fd0d56e 600 }
8187a2b7
ZN		 601 }
602
9991ae78
CW		 603 if (I915_NEED_GFX_HWS(dev))
604 intel_ring_setup_status_page(ring);
605 else
606 ring_setup_phys_status_page(ring);
607
ece4a17d
JK		 608 /* Enforce ordering by reading HEAD register back */
609 I915_READ_HEAD(ring);
610
0d8957c8
DV		 611 /* Initialize the ring. This must happen _after_ we've cleared the ring
612 * registers with the above sequence (the readback of the HEAD registers
613 * also enforces ordering), otherwise the hw might lose the new ring
614 * register values. */
f343c5f6 615 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 616
617 /* WaClearRingBufHeadRegAtInit:ctg,elk */
618 if (I915_READ_HEAD(ring))
619 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
620 ring->name, I915_READ_HEAD(ring));
621 I915_WRITE_HEAD(ring, 0);
622 (void)I915_READ_HEAD(ring);
623
7f2ab699 624 I915_WRITE_CTL(ring,
93b0a4e0 625 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 626 | RING_VALID);
8187a2b7 627
8187a2b7 628 /* If the head is still not zero, the ring is dead */
f01db988 629 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 630 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 631 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 632 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 633 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
634 ring->name,
635 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
636 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
637 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 638 ret = -EIO;
639 goto out;
8187a2b7
ZN		 640 }
641
ebd0fd4b 642 ringbuf->last_retired_head = -1;
5c6c6003
CW		 643 ringbuf->head = I915_READ_HEAD(ring);
644 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 645 intel_ring_update_space(ringbuf);
1ec14ad3 646
50f018df
CW		 647 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
648
b7884eb4 649out:
59bad947 650 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 651
652 return ret;
8187a2b7
ZN		 653}
654
9b1136d5
OM		 655void
656intel_fini_pipe_control(struct intel_engine_cs *ring)
657{
658 struct drm_device *dev = ring->dev;
659
660 if (ring->scratch.obj == NULL)
661 return;
662
663 if (INTEL_INFO(dev)->gen >= 5) {
664 kunmap(sg_page(ring->scratch.obj->pages->sgl));
665 i915_gem_object_ggtt_unpin(ring->scratch.obj);
666 }
667
668 drm_gem_object_unreference(&ring->scratch.obj->base);
669 ring->scratch.obj = NULL;
670}
671
672int
673intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 674{
c6df541c
CW		 675 int ret;
676
bfc882b4 677 WARN_ON(ring->scratch.obj);
c6df541c 678
0d1aacac
CW		 679 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
680 if (ring->scratch.obj == NULL) {
c6df541c
CW		 681 DRM_ERROR("Failed to allocate seqno page\n");
682 ret = -ENOMEM;
683 goto err;
684 }
e4ffd173 685
a9cc726c
DV		 686 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
687 if (ret)
688 goto err_unref;
c6df541c 689
1ec9e26d 690 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 691 if (ret)
692 goto err_unref;
693
0d1aacac
CW		 694 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
695 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
696 if (ring->scratch.cpu_page == NULL) {
56b085a0 697 ret = -ENOMEM;
c6df541c 698 goto err_unpin;
56b085a0 699 }
c6df541c 700
2b1086cc 701 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 702 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 703 return 0;
704
705err_unpin:
d7f46fc4 706 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 707err_unref:
0d1aacac 708 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 709err:
c6df541c
CW		 710 return ret;
711}
712
e2be4faf 713static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 714{
7225342a 715 int ret, i;
e2be4faf 716 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 717 struct drm_device *dev = ring->dev;
718 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 719 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 720
e6c1abb7 721 if (WARN_ON_ONCE(w->count == 0))
7225342a 722 return 0;
888b5995 723
7225342a 724 ring->gpu_caches_dirty = true;
4866d729 725 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 726 if (ret)
727 return ret;
888b5995 728
22a916aa 729 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 730 if (ret)
731 return ret;
732
22a916aa 733 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 734 for (i = 0; i < w->count; i++) {
7225342a
MK		 735 intel_ring_emit(ring, w->reg[i].addr);
736 intel_ring_emit(ring, w->reg[i].value);
737 }
22a916aa 738 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 739
740 intel_ring_advance(ring);
741
742 ring->gpu_caches_dirty = true;
4866d729 743 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 744 if (ret)
745 return ret;
888b5995 746
7225342a 747 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 748
7225342a 749 return 0;
86d7f238
AS		 750}
751
8753181e 752static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 753{
754 int ret;
755
e2be4faf 756 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 757 if (ret != 0)
758 return ret;
759
be01363f 760 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 761 if (ret)
762 DRM_ERROR("init render state: %d\n", ret);
763
764 return ret;
765}
766
7225342a 767static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 768 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 769{
770 const u32 idx = dev_priv->workarounds.count;
771
772 if (WARN_ON(idx >= I915_MAX_WA_REGS))
773 return -ENOSPC;
774
775 dev_priv->workarounds.reg[idx].addr = addr;
776 dev_priv->workarounds.reg[idx].value = val;
777 dev_priv->workarounds.reg[idx].mask = mask;
778
779 dev_priv->workarounds.count++;
780
781 return 0;
86d7f238
AS		 782}
783
cf4b0de6
DL		 784#define WA_REG(addr, mask, val) { \
785 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 786 if (r) \
787 return r; \
788 }
789
790#define WA_SET_BIT_MASKED(addr, mask) \
26459343 791 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 792
793#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 794 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 795
98533251 796#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 797 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 798
cf4b0de6
DL		 799#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
800#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 801
cf4b0de6 802#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 803
00e1e623 804static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 805{
888b5995
AS		 806 struct drm_device *dev = ring->dev;
807 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 808
9cc83020
VS		 809 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
810
2441f877
VS		 811 /* WaDisableAsyncFlipPerfMode:bdw */
812 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
813
86d7f238 814 /* WaDisablePartialInstShootdown:bdw */
101b376d 815 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 816 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
817 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
818 STALL_DOP_GATING_DISABLE);
86d7f238 819
101b376d 820 /* WaDisableDopClockGating:bdw */
7225342a
MK		 821 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
822 DOP_CLOCK_GATING_DISABLE);
86d7f238 823
7225342a
MK		 824 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
825 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 826
827 /* Use Force Non-Coherent whenever executing a 3D context. This is a
828 * workaround for for a possible hang in the unlikely event a TLB
829 * invalidation occurs during a PSD flush.
830 */
7225342a 831 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 832 /* WaForceEnableNonCoherent:bdw */
7225342a 833 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 834 /* WaForceContextSaveRestoreNonCoherent:bdw */
835 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
836 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 837 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 838 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 839 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 840
2701fc43
KG		 841 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
842 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
843 * polygons in the same 8x4 pixel/sample area to be processed without
844 * stalling waiting for the earlier ones to write to Hierarchical Z
845 * buffer."
846 *
847 * This optimization is off by default for Broadwell; turn it on.
848 */
849 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
850
86d7f238 851 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 852 WA_SET_BIT_MASKED(CACHE_MODE_1,
853 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 854
855 /*
856 * BSpec recommends 8x4 when MSAA is used,
857 * however in practice 16x4 seems fastest.
858 *
859 * Note that PS/WM thread counts depend on the WIZ hashing
860 * disable bit, which we don't touch here, but it's good
861 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
862 */
98533251
DL		 863 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
864 GEN6_WIZ_HASHING_MASK,
865 GEN6_WIZ_HASHING_16x4);
888b5995 866
86d7f238
AS		 867 return 0;
868}
869
00e1e623
VS		 870static int chv_init_workarounds(struct intel_engine_cs *ring)
871{
00e1e623
VS		 872 struct drm_device *dev = ring->dev;
873 struct drm_i915_private *dev_priv = dev->dev_private;
874
9cc83020
VS		 875 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
876
2441f877
VS		 877 /* WaDisableAsyncFlipPerfMode:chv */
878 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
879
00e1e623 880 /* WaDisablePartialInstShootdown:chv */
00e1e623 881 /* WaDisableThreadStallDopClockGating:chv */
7225342a 882 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 883 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
884 STALL_DOP_GATING_DISABLE);
00e1e623 885
95289009
AS		 886 /* Use Force Non-Coherent whenever executing a 3D context. This is a
887 * workaround for a possible hang in the unlikely event a TLB
888 * invalidation occurs during a PSD flush.
889 */
890 /* WaForceEnableNonCoherent:chv */
891 /* WaHdcDisableFetchWhenMasked:chv */
892 WA_SET_BIT_MASKED(HDC_CHICKEN0,
893 HDC_FORCE_NON_COHERENT |
894 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
895
973a5b06
KG		 896 /* According to the CACHE_MODE_0 default value documentation, some
897 * CHV platforms disable this optimization by default. Turn it on.
898 */
899 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
900
14bc16e3
VS		 901 /* Wa4x4STCOptimizationDisable:chv */
902 WA_SET_BIT_MASKED(CACHE_MODE_1,
903 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
904
d60de81d
KG		 905 /* Improve HiZ throughput on CHV. */
906 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
907
e7fc2436
VS		 908 /*
909 * BSpec recommends 8x4 when MSAA is used,
910 * however in practice 16x4 seems fastest.
911 *
912 * Note that PS/WM thread counts depend on the WIZ hashing
913 * disable bit, which we don't touch here, but it's good
914 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
915 */
916 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
917 GEN6_WIZ_HASHING_MASK,
918 GEN6_WIZ_HASHING_16x4);
919
7225342a
MK		 920 return 0;
921}
922
3b106531
HN		 923static int gen9_init_workarounds(struct intel_engine_cs *ring)
924{
ab0dfafe
HN		 925 struct drm_device *dev = ring->dev;
926 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 927 uint32_t tmp;
ab0dfafe 928
b0e6f6d4 929 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 930 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
931 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
932
a119a6e6 933 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 934 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
935 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
936
d2a31dbd
NH		 937 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
938 INTEL_REVID(dev) == SKL_REVID_B0)) ||
939 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
940 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 941 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
942 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 943 }
944
a13d215f
NH		 945 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
946 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
947 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 948 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
949 GEN9_RHWO_OPTIMIZATION_DISABLE);
950 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
951 DISABLE_PIXEL_MASK_CAMMING);
952 }
953
27a1b688
NH		 954 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
955 IS_BROXTON(dev)) {
956 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 957 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
958 GEN9_ENABLE_YV12_BUGFIX);
959 }
960
5068368c 961 /* Wa4x4STCOptimizationDisable:skl,bxt */
1840481f
HN		 962 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
963
27160c96 964 /* WaDisablePartialResolveInVc:skl,bxt */
9370cd98
DL		 965 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
966
16be17af 967 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 968 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
969 GEN9_CCS_TLB_PREFETCH_ENABLE);
970
5a2ae95e
ID		 971 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
972 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
973 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 974 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
975 PIXEL_MASK_CAMMING_DISABLE);
976
8ea6f892
ID		 977 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
978 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
979 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
980 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
981 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
982 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
983
3b106531
HN		 984 return 0;
985}
986
b7668791
DL		 987static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
988{
989 struct drm_device *dev = ring->dev;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u8 vals[3] = { 0, 0, 0 };
992 unsigned int i;
993
994 for (i = 0; i < 3; i++) {
995 u8 ss;
996
997 /*
998 * Only consider slices where one, and only one, subslice has 7
999 * EUs
1000 */
1001 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1002 continue;
1003
1004 /*
1005 * subslice_7eu[i] != 0 (because of the check above) and
1006 * ss_max == 4 (maximum number of subslices possible per slice)
1007 *
1008 * -> 0 <= ss <= 3;
1009 */
1010 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1011 vals[i] = 3 - ss;
1012 }
1013
1014 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1015 return 0;
1016
1017 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1018 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1019 GEN9_IZ_HASHING_MASK(2) |
1020 GEN9_IZ_HASHING_MASK(1) |
1021 GEN9_IZ_HASHING_MASK(0),
1022 GEN9_IZ_HASHING(2, vals[2]) |
1023 GEN9_IZ_HASHING(1, vals[1]) |
1024 GEN9_IZ_HASHING(0, vals[0]));
1025
1026 return 0;
1027}
1028
1029
8d205494
DL		 1030static int skl_init_workarounds(struct intel_engine_cs *ring)
1031{
d0bbbc4f
DL		 1032 struct drm_device *dev = ring->dev;
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034
8d205494
DL		 1035 gen9_init_workarounds(ring);
1036
d0bbbc4f
DL		 1037 /* WaDisablePowerCompilerClockGating:skl */
1038 if (INTEL_REVID(dev) == SKL_REVID_B0)
1039 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1040 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1041
b62adbd1
NH		 1042 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1043 /*
1044 *Use Force Non-Coherent whenever executing a 3D context. This
1045 * is a workaround for a possible hang in the unlikely event
1046 * a TLB invalidation occurs during a PSD flush.
1047 */
1048 /* WaForceEnableNonCoherent:skl */
1049 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1050 HDC_FORCE_NON_COHERENT);
1051 }
1052
5b6fd12a
VS		 1053 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1054 INTEL_REVID(dev) == SKL_REVID_D0)
1055 /* WaBarrierPerformanceFixDisable:skl */
1056 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1057 HDC_FENCE_DEST_SLM_DISABLE |
1058 HDC_BARRIER_PERFORMANCE_DISABLE);
1059
b7668791 1060 return skl_tune_iz_hashing(ring);
7225342a
MK		 1061}
1062
cae0437f
NH		 1063static int bxt_init_workarounds(struct intel_engine_cs *ring)
1064{
dfb601e6
NH		 1065 struct drm_device *dev = ring->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067
cae0437f
NH		 1068 gen9_init_workarounds(ring);
1069
dfb601e6
NH		 1070 /* WaDisableThreadStallDopClockGating:bxt */
1071 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1072 STALL_DOP_GATING_DISABLE);
1073
983b4b9d
NH		 1074 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1075 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1076 WA_SET_BIT_MASKED(
1077 GEN7_HALF_SLICE_CHICKEN1,
1078 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1079 }
1080
cae0437f
NH		 1081 return 0;
1082}
1083
771b9a53 1084int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1085{
1086 struct drm_device *dev = ring->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088
1089 WARN_ON(ring->id != RCS);
1090
1091 dev_priv->workarounds.count = 0;
1092
1093 if (IS_BROADWELL(dev))
1094 return bdw_init_workarounds(ring);
1095
1096 if (IS_CHERRYVIEW(dev))
1097 return chv_init_workarounds(ring);
00e1e623 1098
8d205494
DL		 1099 if (IS_SKYLAKE(dev))
1100 return skl_init_workarounds(ring);
cae0437f
NH		 1101
1102 if (IS_BROXTON(dev))
1103 return bxt_init_workarounds(ring);
3b106531 1104
00e1e623
VS		 1105 return 0;
1106}
1107
a4872ba6 1108static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1109{
78501eac 1110 struct drm_device *dev = ring->dev;
1ec14ad3 1111 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1112 int ret = init_ring_common(ring);
9c33baa6
KZ		 1113 if (ret)
1114 return ret;
a69ffdbf 1115
61a563a2
AG		 1116 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1117 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1118 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1119
1120 /* We need to disable the AsyncFlip performance optimisations in order
1121 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1122 * programmed to '1' on all products.
8693a824 1123 *
2441f877 1124 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1125 */
2441f877 1126 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1127 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1128
f05bb0c7 1129 /* Required for the hardware to program scanline values for waiting */
01fa0302 1130 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1131 if (INTEL_INFO(dev)->gen == 6)
1132 I915_WRITE(GFX_MODE,
aa83e30d 1133 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1134
01fa0302 1135 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1136 if (IS_GEN7(dev))
1137 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1138 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1139 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1140
5e13a0c5 1141 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1142 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1143 * "If this bit is set, STCunit will have LRA as replacement
1144 * policy. [...] This bit must be reset. LRA replacement
1145 * policy is not supported."
1146 */
1147 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1148 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1149 }
1150
9cc83020 1151 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1152 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1153
040d2baa 1154 if (HAS_L3_DPF(dev))
35a85ac6 1155 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1156
7225342a 1157 return init_workarounds_ring(ring);
8187a2b7
ZN		 1158}
1159
a4872ba6 1160static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1161{
b45305fc 1162 struct drm_device *dev = ring->dev;
3e78998a
BW		 1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164
1165 if (dev_priv->semaphore_obj) {
1166 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1167 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1168 dev_priv->semaphore_obj = NULL;
1169 }
b45305fc 1170
9b1136d5 1171 intel_fini_pipe_control(ring);
c6df541c
CW		 1172}
1173
3e78998a
BW		 1174static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1175 unsigned int num_dwords)
1176{
1177#define MBOX_UPDATE_DWORDS 8
1178 struct drm_device *dev = signaller->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct intel_engine_cs *waiter;
1181 int i, ret, num_rings;
1182
1183 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1184 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1185#undef MBOX_UPDATE_DWORDS
1186
1187 ret = intel_ring_begin(signaller, num_dwords);
1188 if (ret)
1189 return ret;
1190
1191 for_each_ring(waiter, dev_priv, i) {
6259cead 1192 u32 seqno;
3e78998a
BW		 1193 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1194 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1195 continue;
1196
6259cead
JH		 1197 seqno = i915_gem_request_get_seqno(
1198 signaller->outstanding_lazy_request);
3e78998a
BW		 1199 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1200 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1201 PIPE_CONTROL_QW_WRITE |
1202 PIPE_CONTROL_FLUSH_ENABLE);
1203 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1204 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1205 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1206 intel_ring_emit(signaller, 0);
1207 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1208 MI_SEMAPHORE_TARGET(waiter->id));
1209 intel_ring_emit(signaller, 0);
1210 }
1211
1212 return 0;
1213}
1214
1215static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1216 unsigned int num_dwords)
1217{
1218#define MBOX_UPDATE_DWORDS 6
1219 struct drm_device *dev = signaller->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 struct intel_engine_cs *waiter;
1222 int i, ret, num_rings;
1223
1224 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1225 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1226#undef MBOX_UPDATE_DWORDS
1227
1228 ret = intel_ring_begin(signaller, num_dwords);
1229 if (ret)
1230 return ret;
1231
1232 for_each_ring(waiter, dev_priv, i) {
6259cead 1233 u32 seqno;
3e78998a
BW		 1234 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1235 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1236 continue;
1237
6259cead
JH		 1238 seqno = i915_gem_request_get_seqno(
1239 signaller->outstanding_lazy_request);
3e78998a
BW		 1240 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1241 MI_FLUSH_DW_OP_STOREDW);
1242 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1243 MI_FLUSH_DW_USE_GTT);
1244 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1245 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1246 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1247 MI_SEMAPHORE_TARGET(waiter->id));
1248 intel_ring_emit(signaller, 0);
1249 }
1250
1251 return 0;
1252}
1253
a4872ba6 1254static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1255 unsigned int num_dwords)
1ec14ad3 1256{
024a43e1
BW		 1257 struct drm_device *dev = signaller->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1259 struct intel_engine_cs *useless;
a1444b79 1260 int i, ret, num_rings;
78325f2d 1261
a1444b79
BW		 1262#define MBOX_UPDATE_DWORDS 3
1263 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1264 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1265#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1266
1267 ret = intel_ring_begin(signaller, num_dwords);
1268 if (ret)
1269 return ret;
024a43e1 1270
78325f2d
BW		 1271 for_each_ring(useless, dev_priv, i) {
1272 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1273 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1274 u32 seqno = i915_gem_request_get_seqno(
1275 signaller->outstanding_lazy_request);
78325f2d
BW		 1276 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1277 intel_ring_emit(signaller, mbox_reg);
6259cead 1278 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1279 }
1280 }
024a43e1 1281
a1444b79
BW		 1282 /* If num_dwords was rounded, make sure the tail pointer is correct */
1283 if (num_rings % 2 == 0)
1284 intel_ring_emit(signaller, MI_NOOP);
1285
024a43e1 1286 return 0;
1ec14ad3
CW		 1287}
1288
c8c99b0f
BW		 1289/**
1290 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1291 *
1292 * @request - request to write to the ring
c8c99b0f
BW		 1293 *
1294 * Update the mailbox registers in the *other* rings with the current seqno.
1295 * This acts like a signal in the canonical semaphore.
1296 */
1ec14ad3 1297static int
ee044a88 1298gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1299{
ee044a88 1300 struct intel_engine_cs *ring = req->ring;
024a43e1 1301 int ret;
52ed2325 1302
707d9cf9
BW		 1303 if (ring->semaphore.signal)
1304 ret = ring->semaphore.signal(ring, 4);
1305 else
1306 ret = intel_ring_begin(ring, 4);
1307
1ec14ad3
CW		 1308 if (ret)
1309 return ret;
1310
1ec14ad3
CW		 1311 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1312 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1313 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1314 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1315 __intel_ring_advance(ring);
1ec14ad3 1316
1ec14ad3
CW		 1317 return 0;
1318}
1319
f72b3435
MK		 1320static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1321 u32 seqno)
1322{
1323 struct drm_i915_private *dev_priv = dev->dev_private;
1324 return dev_priv->last_seqno < seqno;
1325}
1326
c8c99b0f
BW		 1327/**
1328 * intel_ring_sync - sync the waiter to the signaller on seqno
1329 *
1330 * @waiter - ring that is waiting
1331 * @signaller - ring which has, or will signal
1332 * @seqno - seqno which the waiter will block on
1333 */
5ee426ca
BW		 1334
1335static int
1336gen8_ring_sync(struct intel_engine_cs *waiter,
1337 struct intel_engine_cs *signaller,
1338 u32 seqno)
1339{
1340 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1341 int ret;
1342
1343 ret = intel_ring_begin(waiter, 4);
1344 if (ret)
1345 return ret;
1346
1347 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1348 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1349 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1350 MI_SEMAPHORE_SAD_GTE_SDD);
1351 intel_ring_emit(waiter, seqno);
1352 intel_ring_emit(waiter,
1353 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1354 intel_ring_emit(waiter,
1355 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1356 intel_ring_advance(waiter);
1357 return 0;
1358}
1359
c8c99b0f 1360static int
a4872ba6
OM		 1361gen6_ring_sync(struct intel_engine_cs *waiter,
1362 struct intel_engine_cs *signaller,
686cb5f9 1363 u32 seqno)
1ec14ad3 1364{
c8c99b0f
BW		 1365 u32 dw1 = MI_SEMAPHORE_MBOX |
1366 MI_SEMAPHORE_COMPARE |
1367 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1368 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1369 int ret;
1ec14ad3 1370
1500f7ea
BW		 1371 /* Throughout all of the GEM code, seqno passed implies our current
1372 * seqno is >= the last seqno executed. However for hardware the
1373 * comparison is strictly greater than.
1374 */
1375 seqno -= 1;
1376
ebc348b2 1377 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1378
c8c99b0f 1379 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1380 if (ret)
1381 return ret;
1382
f72b3435
MK		 1383 /* If seqno wrap happened, omit the wait with no-ops */
1384 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1385 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1386 intel_ring_emit(waiter, seqno);
1387 intel_ring_emit(waiter, 0);
1388 intel_ring_emit(waiter, MI_NOOP);
1389 } else {
1390 intel_ring_emit(waiter, MI_NOOP);
1391 intel_ring_emit(waiter, MI_NOOP);
1392 intel_ring_emit(waiter, MI_NOOP);
1393 intel_ring_emit(waiter, MI_NOOP);
1394 }
c8c99b0f 1395 intel_ring_advance(waiter);
1ec14ad3
CW		 1396
1397 return 0;
1398}
1399
c6df541c
CW		 1400#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1401do { \
fcbc34e4
KG		 1402 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1403 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1404 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1405 intel_ring_emit(ring__, 0); \
1406 intel_ring_emit(ring__, 0); \
1407} while (0)
1408
1409static int
ee044a88 1410pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1411{
ee044a88 1412 struct intel_engine_cs *ring = req->ring;
18393f63 1413 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1414 int ret;
1415
1416 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1417 * incoherent with writes to memory, i.e. completely fubar,
1418 * so we need to use PIPE_NOTIFY instead.
1419 *
1420 * However, we also need to workaround the qword write
1421 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1422 * memory before requesting an interrupt.
1423 */
1424 ret = intel_ring_begin(ring, 32);
1425 if (ret)
1426 return ret;
1427
fcbc34e4 1428 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1429 PIPE_CONTROL_WRITE_FLUSH |
1430 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1431 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1432 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1433 intel_ring_emit(ring, 0);
1434 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1435 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1436 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1437 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1438 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1439 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1440 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1441 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1442 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1443 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1444 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1445
fcbc34e4 1446 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1447 PIPE_CONTROL_WRITE_FLUSH |
1448 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1449 PIPE_CONTROL_NOTIFY);
0d1aacac 1450 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1451 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1452 intel_ring_emit(ring, 0);
09246732 1453 __intel_ring_advance(ring);
c6df541c 1454
c6df541c
CW		 1455 return 0;
1456}
1457
4cd53c0c 1458static u32
a4872ba6 1459gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1460{
4cd53c0c
DV		 1461 /* Workaround to force correct ordering between irq and seqno writes on
1462 * ivb (and maybe also on snb) by reading from a CS register (like
1463 * ACTHD) before reading the status page. */
50877445
CW		 1464 if (!lazy_coherency) {
1465 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1466 POSTING_READ(RING_ACTHD(ring->mmio_base));
1467 }
1468
4cd53c0c
DV		 1469 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1470}
1471
8187a2b7 1472static u32
a4872ba6 1473ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1474{
1ec14ad3
CW		 1475 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1476}
1477
b70ec5bf 1478static void
a4872ba6 1479ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1480{
1481 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1482}
1483
c6df541c 1484static u32
a4872ba6 1485pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1486{
0d1aacac 1487 return ring->scratch.cpu_page[0];
c6df541c
CW		 1488}
1489
b70ec5bf 1490static void
a4872ba6 1491pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1492{
0d1aacac 1493 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1494}
1495
e48d8634 1496static bool
a4872ba6 1497gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1498{
1499 struct drm_device *dev = ring->dev;
4640c4ff 1500 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1501 unsigned long flags;
e48d8634 1502
7cd512f1 1503 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1504 return false;
1505
7338aefa 1506 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1507 if (ring->irq_refcount++ == 0)
480c8033 1508 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1509 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1510
1511 return true;
1512}
1513
1514static void
a4872ba6 1515gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1516{
1517 struct drm_device *dev = ring->dev;
4640c4ff 1518 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1519 unsigned long flags;
e48d8634 1520
7338aefa 1521 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1522 if (--ring->irq_refcount == 0)
480c8033 1523 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1524 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1525}
1526
b13c2b96 1527static bool
a4872ba6 1528i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1529{
78501eac 1530 struct drm_device *dev = ring->dev;
4640c4ff 1531 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1532 unsigned long flags;
62fdfeaf 1533
7cd512f1 1534 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1535 return false;
1536
7338aefa 1537 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1538 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1539 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1540 I915_WRITE(IMR, dev_priv->irq_mask);
1541 POSTING_READ(IMR);
1542 }
7338aefa 1543 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1544
1545 return true;
62fdfeaf
EA		 1546}
1547
8187a2b7 1548static void
a4872ba6 1549i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1550{
78501eac 1551 struct drm_device *dev = ring->dev;
4640c4ff 1552 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1553 unsigned long flags;
62fdfeaf 1554
7338aefa 1555 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1556 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1557 dev_priv->irq_mask |= ring->irq_enable_mask;
1558 I915_WRITE(IMR, dev_priv->irq_mask);
1559 POSTING_READ(IMR);
1560 }
7338aefa 1561 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1562}
1563
c2798b19 1564static bool
a4872ba6 1565i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1566{
1567 struct drm_device *dev = ring->dev;
4640c4ff 1568 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1569 unsigned long flags;
c2798b19 1570
7cd512f1 1571 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1572 return false;
1573
7338aefa 1574 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1575 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1576 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1577 I915_WRITE16(IMR, dev_priv->irq_mask);
1578 POSTING_READ16(IMR);
1579 }
7338aefa 1580 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1581
1582 return true;
1583}
1584
1585static void
a4872ba6 1586i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1587{
1588 struct drm_device *dev = ring->dev;
4640c4ff 1589 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1590 unsigned long flags;
c2798b19 1591
7338aefa 1592 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1593 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1594 dev_priv->irq_mask |= ring->irq_enable_mask;
1595 I915_WRITE16(IMR, dev_priv->irq_mask);
1596 POSTING_READ16(IMR);
1597 }
7338aefa 1598 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1599}
1600
b72f3acb 1601static int
a84c3ae1 1602bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1603 u32 invalidate_domains,
1604 u32 flush_domains)
d1b851fc 1605{
a84c3ae1 1606 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1607 int ret;
1608
b72f3acb
CW		 1609 ret = intel_ring_begin(ring, 2);
1610 if (ret)
1611 return ret;
1612
1613 intel_ring_emit(ring, MI_FLUSH);
1614 intel_ring_emit(ring, MI_NOOP);
1615 intel_ring_advance(ring);
1616 return 0;
d1b851fc
ZN		 1617}
1618
3cce469c 1619static int
ee044a88 1620i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1621{
ee044a88 1622 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1623 int ret;
1624
1625 ret = intel_ring_begin(ring, 4);
1626 if (ret)
1627 return ret;
6f392d54 1628
3cce469c
CW		 1629 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1630 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1631 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1632 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1633 __intel_ring_advance(ring);
d1b851fc 1634
3cce469c 1635 return 0;
d1b851fc
ZN		 1636}
1637
0f46832f 1638static bool
a4872ba6 1639gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1640{
1641 struct drm_device *dev = ring->dev;
4640c4ff 1642 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1643 unsigned long flags;
0f46832f 1644
7cd512f1
DV		 1645 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1646 return false;
0f46832f 1647
7338aefa 1648 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1649 if (ring->irq_refcount++ == 0) {
040d2baa 1650 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1651 I915_WRITE_IMR(ring,
1652 ~(ring->irq_enable_mask |
35a85ac6 1653 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1654 else
1655 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1656 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1657 }
7338aefa 1658 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1659
1660 return true;
1661}
1662
1663static void
a4872ba6 1664gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1665{
1666 struct drm_device *dev = ring->dev;
4640c4ff 1667 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1668 unsigned long flags;
0f46832f 1669
7338aefa 1670 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1671 if (--ring->irq_refcount == 0) {
040d2baa 1672 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1673 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1674 else
1675 I915_WRITE_IMR(ring, ~0);
480c8033 1676 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1677 }
7338aefa 1678 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1679}
1680
a19d2933 1681static bool
a4872ba6 1682hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1683{
1684 struct drm_device *dev = ring->dev;
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686 unsigned long flags;
1687
7cd512f1 1688 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1689 return false;
1690
59cdb63d 1691 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1692 if (ring->irq_refcount++ == 0) {
a19d2933 1693 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1694 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1695 }
59cdb63d 1696 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1697
1698 return true;
1699}
1700
1701static void
a4872ba6 1702hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1703{
1704 struct drm_device *dev = ring->dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 unsigned long flags;
1707
59cdb63d 1708 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1709 if (--ring->irq_refcount == 0) {
a19d2933 1710 I915_WRITE_IMR(ring, ~0);
480c8033 1711 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1712 }
59cdb63d 1713 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1714}
1715
abd58f01 1716static bool
a4872ba6 1717gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1718{
1719 struct drm_device *dev = ring->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 unsigned long flags;
1722
7cd512f1 1723 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1724 return false;
1725
1726 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1727 if (ring->irq_refcount++ == 0) {
1728 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1729 I915_WRITE_IMR(ring,
1730 ~(ring->irq_enable_mask |
1731 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1732 } else {
1733 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1734 }
1735 POSTING_READ(RING_IMR(ring->mmio_base));
1736 }
1737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1738
1739 return true;
1740}
1741
1742static void
a4872ba6 1743gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1744{
1745 struct drm_device *dev = ring->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 unsigned long flags;
1748
1749 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1750 if (--ring->irq_refcount == 0) {
1751 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1752 I915_WRITE_IMR(ring,
1753 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1754 } else {
1755 I915_WRITE_IMR(ring, ~0);
1756 }
1757 POSTING_READ(RING_IMR(ring->mmio_base));
1758 }
1759 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1760}
1761
d1b851fc 1762static int
53fddaf7 1763i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1764 u64 offset, u32 length,
8e004efc 1765 unsigned dispatch_flags)
d1b851fc 1766{
53fddaf7 1767 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1768 int ret;
78501eac 1769
e1f99ce6
CW		 1770 ret = intel_ring_begin(ring, 2);
1771 if (ret)
1772 return ret;
1773
78501eac 1774 intel_ring_emit(ring,
65f56876
CW		 1775 MI_BATCH_BUFFER_START |
1776 MI_BATCH_GTT |
8e004efc
JH		 1777 (dispatch_flags & I915_DISPATCH_SECURE ?
1778 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1779 intel_ring_emit(ring, offset);
78501eac
CW		 1780 intel_ring_advance(ring);
1781
d1b851fc
ZN		 1782 return 0;
1783}
1784
b45305fc
DV		 1785/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1786#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1787#define I830_TLB_ENTRIES (2)
1788#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1789static int
53fddaf7 1790i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1791 u64 offset, u32 len,
1792 unsigned dispatch_flags)
62fdfeaf 1793{
53fddaf7 1794 struct intel_engine_cs *ring = req->ring;
c4d69da1 1795 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1796 int ret;
62fdfeaf 1797
c4d69da1
CW		 1798 ret = intel_ring_begin(ring, 6);
1799 if (ret)
1800 return ret;
62fdfeaf 1801
c4d69da1
CW		 1802 /* Evict the invalid PTE TLBs */
1803 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1804 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1805 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1806 intel_ring_emit(ring, cs_offset);
1807 intel_ring_emit(ring, 0xdeadbeef);
1808 intel_ring_emit(ring, MI_NOOP);
1809 intel_ring_advance(ring);
b45305fc 1810
8e004efc 1811 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1812 if (len > I830_BATCH_LIMIT)
1813 return -ENOSPC;
1814
c4d69da1 1815 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1816 if (ret)
1817 return ret;
c4d69da1
CW		 1818
1819 /* Blit the batch (which has now all relocs applied) to the
1820 * stable batch scratch bo area (so that the CS never
1821 * stumbles over its tlb invalidation bug) ...
1822 */
1823 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1824 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1825 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1826 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1827 intel_ring_emit(ring, 4096);
1828 intel_ring_emit(ring, offset);
c4d69da1 1829
b45305fc 1830 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1831 intel_ring_emit(ring, MI_NOOP);
1832 intel_ring_advance(ring);
b45305fc
DV		 1833
1834 /* ... and execute it. */
c4d69da1 1835 offset = cs_offset;
b45305fc 1836 }
e1f99ce6 1837
c4d69da1
CW		 1838 ret = intel_ring_begin(ring, 4);
1839 if (ret)
1840 return ret;
1841
1842 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1843 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1844 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1845 intel_ring_emit(ring, offset + len - 8);
1846 intel_ring_emit(ring, MI_NOOP);
1847 intel_ring_advance(ring);
1848
fb3256da
DV		 1849 return 0;
1850}
1851
1852static int
53fddaf7 1853i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1854 u64 offset, u32 len,
8e004efc 1855 unsigned dispatch_flags)
fb3256da 1856{
53fddaf7 1857 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1858 int ret;
1859
1860 ret = intel_ring_begin(ring, 2);
1861 if (ret)
1862 return ret;
1863
65f56876 1864 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1865 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1866 0 : MI_BATCH_NON_SECURE));
c4e7a414 1867 intel_ring_advance(ring);
62fdfeaf 1868
62fdfeaf
EA		 1869 return 0;
1870}
1871
a4872ba6 1872static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1873{
05394f39 1874 struct drm_i915_gem_object *obj;
62fdfeaf 1875
8187a2b7
ZN		 1876 obj = ring->status_page.obj;
1877 if (obj == NULL)
62fdfeaf 1878 return;
62fdfeaf 1879
9da3da66 1880 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1881 i915_gem_object_ggtt_unpin(obj);
05394f39 1882 drm_gem_object_unreference(&obj->base);
8187a2b7 1883 ring->status_page.obj = NULL;
62fdfeaf
EA		 1884}
1885
a4872ba6 1886static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1887{
05394f39 1888 struct drm_i915_gem_object *obj;
62fdfeaf 1889
e3efda49 1890 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1891 unsigned flags;
e3efda49 1892 int ret;
e4ffd173 1893
e3efda49
CW		 1894 obj = i915_gem_alloc_object(ring->dev, 4096);
1895 if (obj == NULL) {
1896 DRM_ERROR("Failed to allocate status page\n");
1897 return -ENOMEM;
1898 }
62fdfeaf 1899
e3efda49
CW		 1900 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1901 if (ret)
1902 goto err_unref;
1903
1f767e02
CW		 1904 flags = 0;
1905 if (!HAS_LLC(ring->dev))
1906 /* On g33, we cannot place HWS above 256MiB, so
1907 * restrict its pinning to the low mappable arena.
1908 * Though this restriction is not documented for
1909 * gen4, gen5, or byt, they also behave similarly
1910 * and hang if the HWS is placed at the top of the
1911 * GTT. To generalise, it appears that all !llc
1912 * platforms have issues with us placing the HWS
1913 * above the mappable region (even though we never
1914 * actualy map it).
1915 */
1916 flags |= PIN_MAPPABLE;
1917 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1918 if (ret) {
1919err_unref:
1920 drm_gem_object_unreference(&obj->base);
1921 return ret;
1922 }
1923
1924 ring->status_page.obj = obj;
1925 }
62fdfeaf 1926
f343c5f6 1927 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1928 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1929 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1930
8187a2b7
ZN		 1931 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1932 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1933
1934 return 0;
62fdfeaf
EA		 1935}
1936
a4872ba6 1937static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1938{
1939 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1940
1941 if (!dev_priv->status_page_dmah) {
1942 dev_priv->status_page_dmah =
1943 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1944 if (!dev_priv->status_page_dmah)
1945 return -ENOMEM;
1946 }
1947
6b8294a4
CW		 1948 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1949 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1950
1951 return 0;
1952}
1953
7ba717cf 1954void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1955{
2919d291 1956 iounmap(ringbuf->virtual_start);
7ba717cf 1957 ringbuf->virtual_start = NULL;
2919d291 1958 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1959}
1960
1961int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1962 struct intel_ringbuffer *ringbuf)
1963{
1964 struct drm_i915_private *dev_priv = to_i915(dev);
1965 struct drm_i915_gem_object *obj = ringbuf->obj;
1966 int ret;
1967
1968 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1969 if (ret)
1970 return ret;
1971
1972 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1973 if (ret) {
1974 i915_gem_object_ggtt_unpin(obj);
1975 return ret;
1976 }
1977
1978 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1979 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1980 if (ringbuf->virtual_start == NULL) {
1981 i915_gem_object_ggtt_unpin(obj);
1982 return -EINVAL;
1983 }
1984
1985 return 0;
1986}
1987
1988void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1989{
2919d291
OM		 1990 drm_gem_object_unreference(&ringbuf->obj->base);
1991 ringbuf->obj = NULL;
1992}
1993
84c2377f
OM		 1994int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1995 struct intel_ringbuffer *ringbuf)
62fdfeaf 1996{
05394f39 1997 struct drm_i915_gem_object *obj;
62fdfeaf 1998
ebc052e0
CW		 1999 obj = NULL;
2000 if (!HAS_LLC(dev))
93b0a4e0 2001 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2002 if (obj == NULL)
93b0a4e0 2003 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2004 if (obj == NULL)
2005 return -ENOMEM;
8187a2b7 2006
24f3a8cf
AG		 2007 /* mark ring buffers as read-only from GPU side by default */
2008 obj->gt_ro = 1;
2009
93b0a4e0 2010 ringbuf->obj = obj;
e3efda49 2011
7ba717cf 2012 return 0;
e3efda49
CW		 2013}
2014
2015static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2016 struct intel_engine_cs *ring)
e3efda49 2017{
bfc882b4 2018 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2019 int ret;
2020
bfc882b4
DV		 2021 WARN_ON(ring->buffer);
2022
2023 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2024 if (!ringbuf)
2025 return -ENOMEM;
2026 ring->buffer = ringbuf;
8ee14975 2027
e3efda49
CW		 2028 ring->dev = dev;
2029 INIT_LIST_HEAD(&ring->active_list);
2030 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2031 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2032 i915_gem_batch_pool_init(dev, &ring->batch_pool);
93b0a4e0 2033 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2034 ringbuf->ring = ring;
ebc348b2 2035 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2036
2037 init_waitqueue_head(&ring->irq_queue);
2038
2039 if (I915_NEED_GFX_HWS(dev)) {
2040 ret = init_status_page(ring);
2041 if (ret)
8ee14975 2042 goto error;
e3efda49
CW		 2043 } else {
2044 BUG_ON(ring->id != RCS);
2045 ret = init_phys_status_page(ring);
2046 if (ret)
8ee14975 2047 goto error;
e3efda49
CW		 2048 }
2049
bfc882b4 2050 WARN_ON(ringbuf->obj);
7ba717cf 2051
bfc882b4
DV		 2052 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2053 if (ret) {
2054 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2055 ring->name, ret);
2056 goto error;
2057 }
2058
2059 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2060 if (ret) {
2061 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2062 ring->name, ret);
2063 intel_destroy_ringbuffer_obj(ringbuf);
2064 goto error;
e3efda49 2065 }
62fdfeaf 2066
55249baa
CW		 2067 /* Workaround an erratum on the i830 which causes a hang if
2068 * the TAIL pointer points to within the last 2 cachelines
2069 * of the buffer.
2070 */
93b0a4e0 2071 ringbuf->effective_size = ringbuf->size;
e3efda49 2072 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2073 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2074
44e895a8
BV		 2075 ret = i915_cmd_parser_init_ring(ring);
2076 if (ret)
8ee14975
OM		 2077 goto error;
2078
8ee14975 2079 return 0;
351e3db2 2080
8ee14975
OM		 2081error:
2082 kfree(ringbuf);
2083 ring->buffer = NULL;
2084 return ret;
62fdfeaf
EA		 2085}
2086
a4872ba6 2087void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2088{
6402c330
JH		 2089 struct drm_i915_private *dev_priv;
2090 struct intel_ringbuffer *ringbuf;
33626e6a 2091
93b0a4e0 2092 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2093 return;
2094
6402c330
JH		 2095 dev_priv = to_i915(ring->dev);
2096 ringbuf = ring->buffer;
2097
e3efda49 2098 intel_stop_ring_buffer(ring);
de8f0a50 2099 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2100
7ba717cf 2101 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2102 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2103 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2104
8d19215b
ZN		 2105 if (ring->cleanup)
2106 ring->cleanup(ring);
2107
78501eac 2108 cleanup_status_page(ring);
44e895a8
BV		 2109
2110 i915_cmd_parser_fini_ring(ring);
06fbca71 2111 i915_gem_batch_pool_fini(&ring->batch_pool);
8ee14975 2112
93b0a4e0 2113 kfree(ringbuf);
8ee14975 2114 ring->buffer = NULL;
62fdfeaf
EA		 2115}
2116
595e1eeb 2117static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2118{
93b0a4e0 2119 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2120 struct drm_i915_gem_request *request;
b4716185
CW		 2121 unsigned space;
2122 int ret;
a71d8d94 2123
29b1b415
JH		 2124 /* The whole point of reserving space is to not wait! */
2125 WARN_ON(ringbuf->reserved_in_use);
2126
ebd0fd4b
DG		 2127 if (intel_ring_space(ringbuf) >= n)
2128 return 0;
a71d8d94
CW		 2129
2130 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2131 space = __intel_ring_space(request->postfix, ringbuf->tail,
2132 ringbuf->size);
2133 if (space >= n)
a71d8d94 2134 break;
a71d8d94
CW		 2135 }
2136
595e1eeb 2137 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2138 return -ENOSPC;
2139
a4b3a571 2140 ret = i915_wait_request(request);
a71d8d94
CW		 2141 if (ret)
2142 return ret;
2143
b4716185 2144 ringbuf->space = space;
a71d8d94
CW		 2145 return 0;
2146}
2147
a4872ba6 2148static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2149{
2150 uint32_t __iomem *virt;
93b0a4e0
OM		 2151 struct intel_ringbuffer *ringbuf = ring->buffer;
2152 int rem = ringbuf->size - ringbuf->tail;
3e960501 2153
29b1b415
JH		 2154 /* Can't wrap if space has already been reserved! */
2155 WARN_ON(ringbuf->reserved_in_use);
2156
93b0a4e0 2157 if (ringbuf->space < rem) {
3e960501
CW		 2158 int ret = ring_wait_for_space(ring, rem);
2159 if (ret)
2160 return ret;
2161 }
2162
93b0a4e0 2163 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2164 rem /= 4;
2165 while (rem--)
2166 iowrite32(MI_NOOP, virt++);
2167
93b0a4e0 2168 ringbuf->tail = 0;
ebd0fd4b 2169 intel_ring_update_space(ringbuf);
3e960501
CW		 2170
2171 return 0;
2172}
2173
a4872ba6 2174int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2175{
a4b3a571 2176 struct drm_i915_gem_request *req;
3e960501
CW		 2177
2178 /* We need to add any requests required to flush the objects and ring */
75289874 2179 WARN_ON(ring->outstanding_lazy_request);
bf7dc5b7 2180 if (ring->outstanding_lazy_request)
75289874 2181 i915_add_request(ring->outstanding_lazy_request);
3e960501
CW		 2182
2183 /* Wait upon the last request to be completed */
2184 if (list_empty(&ring->request_list))
2185 return 0;
2186
a4b3a571 2187 req = list_entry(ring->request_list.prev,
b4716185
CW		 2188 struct drm_i915_gem_request,
2189 list);
2190
2191 /* Make sure we do not trigger any retires */
2192 return __i915_wait_request(req,
2193 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2194 to_i915(ring->dev)->mm.interruptible,
2195 NULL, NULL);
3e960501
CW		 2196}
2197
6689cb2b 2198int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2199{
6689cb2b 2200 request->ringbuf = request->ring->buffer;
9eba5d4a 2201 return 0;
9d773091
CW		 2202}
2203
29b1b415
JH		 2204void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2205{
2206 /* NB: Until request management is fully tidied up and the OLR is
2207 * removed, there are too many ways for get false hits on this
2208 * anti-recursion check! */
2209 /*WARN_ON(ringbuf->reserved_size);*/
2210 WARN_ON(ringbuf->reserved_in_use);
2211
2212 ringbuf->reserved_size = size;
2213
2214 /*
2215 * Really need to call _begin() here but that currently leads to
2216 * recursion problems! This will be fixed later but for now just
2217 * return and hope for the best. Note that there is only a real
2218 * problem if the create of the request never actually calls _begin()
2219 * but if they are not submitting any work then why did they create
2220 * the request in the first place?
2221 */
2222}
2223
2224void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2225{
2226 WARN_ON(ringbuf->reserved_in_use);
2227
2228 ringbuf->reserved_size = 0;
2229 ringbuf->reserved_in_use = false;
2230}
2231
2232void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2233{
2234 WARN_ON(ringbuf->reserved_in_use);
2235
2236 ringbuf->reserved_in_use = true;
2237 ringbuf->reserved_tail = ringbuf->tail;
2238}
2239
2240void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2241{
2242 WARN_ON(!ringbuf->reserved_in_use);
2243 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2244 "request reserved size too small: %d vs %d!\n",
2245 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2246
2247 ringbuf->reserved_size = 0;
2248 ringbuf->reserved_in_use = false;
2249}
2250
2251static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2252{
93b0a4e0 2253 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2254 int ret;
2255
29b1b415
JH		 2256 /*
2257 * Add on the reserved size to the request to make sure that after
2258 * the intended commands have been emitted, there is guaranteed to
2259 * still be enough free space to send them to the hardware.
2260 */
2261 if (!ringbuf->reserved_in_use)
2262 bytes += ringbuf->reserved_size;
2263
93b0a4e0 2264 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2265 ret = intel_wrap_ring_buffer(ring);
2266 if (unlikely(ret))
2267 return ret;
29b1b415
JH		 2268
2269 if(ringbuf->reserved_size) {
2270 uint32_t size = ringbuf->reserved_size;
2271
2272 intel_ring_reserved_space_cancel(ringbuf);
2273 intel_ring_reserved_space_reserve(ringbuf, size);
2274 }
cbcc80df
MK		 2275 }
2276
93b0a4e0 2277 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2278 ret = ring_wait_for_space(ring, bytes);
2279 if (unlikely(ret))
2280 return ret;
2281 }
2282
cbcc80df
MK		 2283 return 0;
2284}
2285
a4872ba6 2286int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2287 int num_dwords)
8187a2b7 2288{
217e46b5 2289 struct drm_i915_gem_request *req;
4640c4ff 2290 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2291 int ret;
78501eac 2292
33196ded
DV		 2293 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2294 dev_priv->mm.interruptible);
de2b9985
DV		 2295 if (ret)
2296 return ret;
21dd3734 2297
304d695c
CW		 2298 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2299 if (ret)
2300 return ret;
2301
9d773091 2302 /* Preallocate the olr before touching the ring */
217e46b5 2303 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
9d773091
CW		 2304 if (ret)
2305 return ret;
2306
ee1b1e5e 2307 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2308 return 0;
8187a2b7 2309}
78501eac 2310
753b1ad4 2311/* Align the ring tail to a cacheline boundary */
a4872ba6 2312int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2313{
ee1b1e5e 2314 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2315 int ret;
2316
2317 if (num_dwords == 0)
2318 return 0;
2319
18393f63 2320 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2321 ret = intel_ring_begin(ring, num_dwords);
2322 if (ret)
2323 return ret;
2324
2325 while (num_dwords--)
2326 intel_ring_emit(ring, MI_NOOP);
2327
2328 intel_ring_advance(ring);
2329
2330 return 0;
2331}
2332
a4872ba6 2333void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2334{
3b2cc8ab
OM		 2335 struct drm_device *dev = ring->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2337
6259cead 2338 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2339
3b2cc8ab 2340 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2341 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2342 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2343 if (HAS_VEBOX(dev))
5020150b 2344 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2345 }
d97ed339 2346
f7e98ad4 2347 ring->set_seqno(ring, seqno);
92cab734 2348 ring->hangcheck.seqno = seqno;
8187a2b7 2349}
62fdfeaf 2350
a4872ba6 2351static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2352 u32 value)
881f47b6 2353{
4640c4ff 2354 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2355
2356 /* Every tail move must follow the sequence below */
12f55818
CW		 2357
2358 /* Disable notification that the ring is IDLE. The GT
2359 * will then assume that it is busy and bring it out of rc6.
2360 */
0206e353 2361 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2362 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2363
2364 /* Clear the context id. Here be magic! */
2365 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2366
12f55818 2367 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2368 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2369 GEN6_BSD_SLEEP_INDICATOR) == 0,
2370 50))
2371 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2372
12f55818 2373 /* Now that the ring is fully powered up, update the tail */
0206e353 2374 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2375 POSTING_READ(RING_TAIL(ring->mmio_base));
2376
2377 /* Let the ring send IDLE messages to the GT again,
2378 * and so let it sleep to conserve power when idle.
2379 */
0206e353 2380 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2381 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2382}
2383
a84c3ae1 2384static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2385 u32 invalidate, u32 flush)
881f47b6 2386{
a84c3ae1 2387 struct intel_engine_cs *ring = req->ring;
71a77e07 2388 uint32_t cmd;
b72f3acb
CW		 2389 int ret;
2390
b72f3acb
CW		 2391 ret = intel_ring_begin(ring, 4);
2392 if (ret)
2393 return ret;
2394
71a77e07 2395 cmd = MI_FLUSH_DW;
075b3bba
BW		 2396 if (INTEL_INFO(ring->dev)->gen >= 8)
2397 cmd += 1;
f0a1fb10
CW		 2398
2399 /* We always require a command barrier so that subsequent
2400 * commands, such as breadcrumb interrupts, are strictly ordered
2401 * wrt the contents of the write cache being flushed to memory
2402 * (and thus being coherent from the CPU).
2403 */
2404 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2405
9a289771
JB		 2406 /*
2407 * Bspec vol 1c.5 - video engine command streamer:
2408 * "If ENABLED, all TLBs will be invalidated once the flush
2409 * operation is complete. This bit is only valid when the
2410 * Post-Sync Operation field is a value of 1h or 3h."
2411 */
71a77e07 2412 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2413 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2414
71a77e07 2415 intel_ring_emit(ring, cmd);
9a289771 2416 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2417 if (INTEL_INFO(ring->dev)->gen >= 8) {
2418 intel_ring_emit(ring, 0); /* upper addr */
2419 intel_ring_emit(ring, 0); /* value */
2420 } else {
2421 intel_ring_emit(ring, 0);
2422 intel_ring_emit(ring, MI_NOOP);
2423 }
b72f3acb
CW		 2424 intel_ring_advance(ring);
2425 return 0;
881f47b6
XH		 2426}
2427
1c7a0623 2428static int
53fddaf7 2429gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2430 u64 offset, u32 len,
8e004efc 2431 unsigned dispatch_flags)
1c7a0623 2432{
53fddaf7 2433 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2434 bool ppgtt = USES_PPGTT(ring->dev) &&
2435 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2436 int ret;
2437
2438 ret = intel_ring_begin(ring, 4);
2439 if (ret)
2440 return ret;
2441
2442 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2443 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2444 intel_ring_emit(ring, lower_32_bits(offset));
2445 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2446 intel_ring_emit(ring, MI_NOOP);
2447 intel_ring_advance(ring);
2448
2449 return 0;
2450}
2451
d7d4eedd 2452static int
53fddaf7 2453hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2454 u64 offset, u32 len,
2455 unsigned dispatch_flags)
d7d4eedd 2456{
53fddaf7 2457 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2458 int ret;
2459
2460 ret = intel_ring_begin(ring, 2);
2461 if (ret)
2462 return ret;
2463
2464 intel_ring_emit(ring,
77072258 2465 MI_BATCH_BUFFER_START |
8e004efc 2466 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2467 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2468 /* bit0-7 is the length on GEN6+ */
2469 intel_ring_emit(ring, offset);
2470 intel_ring_advance(ring);
2471
2472 return 0;
2473}
2474
881f47b6 2475static int
53fddaf7 2476gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2477 u64 offset, u32 len,
8e004efc 2478 unsigned dispatch_flags)
881f47b6 2479{
53fddaf7 2480 struct intel_engine_cs *ring = req->ring;
0206e353 2481 int ret;
ab6f8e32 2482
0206e353
AJ		 2483 ret = intel_ring_begin(ring, 2);
2484 if (ret)
2485 return ret;
e1f99ce6 2486
d7d4eedd
CW		 2487 intel_ring_emit(ring,
2488 MI_BATCH_BUFFER_START |
8e004efc
JH		 2489 (dispatch_flags & I915_DISPATCH_SECURE ?
2490 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2491 /* bit0-7 is the length on GEN6+ */
2492 intel_ring_emit(ring, offset);
2493 intel_ring_advance(ring);
ab6f8e32 2494
0206e353 2495 return 0;
881f47b6
XH		 2496}
2497
549f7365
CW		 2498/* Blitter support (SandyBridge+) */
2499
a84c3ae1 2500static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2501 u32 invalidate, u32 flush)
8d19215b 2502{
a84c3ae1 2503 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2504 struct drm_device *dev = ring->dev;
71a77e07 2505 uint32_t cmd;
b72f3acb
CW		 2506 int ret;
2507
6a233c78 2508 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2509 if (ret)
2510 return ret;
2511
71a77e07 2512 cmd = MI_FLUSH_DW;
dbef0f15 2513 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2514 cmd += 1;
f0a1fb10
CW		 2515
2516 /* We always require a command barrier so that subsequent
2517 * commands, such as breadcrumb interrupts, are strictly ordered
2518 * wrt the contents of the write cache being flushed to memory
2519 * (and thus being coherent from the CPU).
2520 */
2521 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2522
9a289771
JB		 2523 /*
2524 * Bspec vol 1c.3 - blitter engine command streamer:
2525 * "If ENABLED, all TLBs will be invalidated once the flush
2526 * operation is complete. This bit is only valid when the
2527 * Post-Sync Operation field is a value of 1h or 3h."
2528 */
71a77e07 2529 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2530 cmd |= MI_INVALIDATE_TLB;
71a77e07 2531 intel_ring_emit(ring, cmd);
9a289771 2532 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2533 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2534 intel_ring_emit(ring, 0); /* upper addr */
2535 intel_ring_emit(ring, 0); /* value */
2536 } else {
2537 intel_ring_emit(ring, 0);
2538 intel_ring_emit(ring, MI_NOOP);
2539 }
b72f3acb 2540 intel_ring_advance(ring);
fd3da6c9 2541
b72f3acb 2542 return 0;
8d19215b
ZN		 2543}
2544
5c1143bb
XH		 2545int intel_init_render_ring_buffer(struct drm_device *dev)
2546{
4640c4ff 2547 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2548 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2549 struct drm_i915_gem_object *obj;
2550 int ret;
5c1143bb 2551
59465b5f
DV		 2552 ring->name = "render ring";
2553 ring->id = RCS;
2554 ring->mmio_base = RENDER_RING_BASE;
2555
707d9cf9 2556 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2557 if (i915_semaphore_is_enabled(dev)) {
2558 obj = i915_gem_alloc_object(dev, 4096);
2559 if (obj == NULL) {
2560 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2561 i915.semaphores = 0;
2562 } else {
2563 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2564 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2565 if (ret != 0) {
2566 drm_gem_object_unreference(&obj->base);
2567 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2568 i915.semaphores = 0;
2569 } else
2570 dev_priv->semaphore_obj = obj;
2571 }
2572 }
7225342a 2573
8f0e2b9d 2574 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2575 ring->add_request = gen6_add_request;
2576 ring->flush = gen8_render_ring_flush;
2577 ring->irq_get = gen8_ring_get_irq;
2578 ring->irq_put = gen8_ring_put_irq;
2579 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2580 ring->get_seqno = gen6_ring_get_seqno;
2581 ring->set_seqno = ring_set_seqno;
2582 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2583 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2584 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2585 ring->semaphore.signal = gen8_rcs_signal;
2586 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2587 }
2588 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2589 ring->add_request = gen6_add_request;
4772eaeb 2590 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2591 if (INTEL_INFO(dev)->gen == 6)
b3111509 2592 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2593 ring->irq_get = gen6_ring_get_irq;
2594 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2595 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2596 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2597 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2598 if (i915_semaphore_is_enabled(dev)) {
2599 ring->semaphore.sync_to = gen6_ring_sync;
2600 ring->semaphore.signal = gen6_signal;
2601 /*
2602 * The current semaphore is only applied on pre-gen8
2603 * platform. And there is no VCS2 ring on the pre-gen8
2604 * platform. So the semaphore between RCS and VCS2 is
2605 * initialized as INVALID. Gen8 will initialize the
2606 * sema between VCS2 and RCS later.
2607 */
2608 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2609 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2610 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2611 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2612 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2613 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2614 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2615 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2616 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2617 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2618 }
c6df541c
CW		 2619 } else if (IS_GEN5(dev)) {
2620 ring->add_request = pc_render_add_request;
46f0f8d1 2621 ring->flush = gen4_render_ring_flush;
c6df541c 2622 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2623 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2624 ring->irq_get = gen5_ring_get_irq;
2625 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2626 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2627 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2628 } else {
8620a3a9 2629 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2630 if (INTEL_INFO(dev)->gen < 4)
2631 ring->flush = gen2_render_ring_flush;
2632 else
2633 ring->flush = gen4_render_ring_flush;
59465b5f 2634 ring->get_seqno = ring_get_seqno;
b70ec5bf 2635 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2636 if (IS_GEN2(dev)) {
2637 ring->irq_get = i8xx_ring_get_irq;
2638 ring->irq_put = i8xx_ring_put_irq;
2639 } else {
2640 ring->irq_get = i9xx_ring_get_irq;
2641 ring->irq_put = i9xx_ring_put_irq;
2642 }
e3670319 2643 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2644 }
59465b5f 2645 ring->write_tail = ring_write_tail;
707d9cf9 2646
d7d4eedd
CW		 2647 if (IS_HASWELL(dev))
2648 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2649 else if (IS_GEN8(dev))
2650 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2651 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2652 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2653 else if (INTEL_INFO(dev)->gen >= 4)
2654 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2655 else if (IS_I830(dev) || IS_845G(dev))
2656 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2657 else
2658 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2659 ring->init_hw = init_render_ring;
59465b5f
DV		 2660 ring->cleanup = render_ring_cleanup;
2661
b45305fc
DV		 2662 /* Workaround batchbuffer to combat CS tlb bug. */
2663 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2664 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2665 if (obj == NULL) {
2666 DRM_ERROR("Failed to allocate batch bo\n");
2667 return -ENOMEM;
2668 }
2669
be1fa129 2670 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2671 if (ret != 0) {
2672 drm_gem_object_unreference(&obj->base);
2673 DRM_ERROR("Failed to ping batch bo\n");
2674 return ret;
2675 }
2676
0d1aacac
CW		 2677 ring->scratch.obj = obj;
2678 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2679 }
2680
99be1dfe
DV		 2681 ret = intel_init_ring_buffer(dev, ring);
2682 if (ret)
2683 return ret;
2684
2685 if (INTEL_INFO(dev)->gen >= 5) {
2686 ret = intel_init_pipe_control(ring);
2687 if (ret)
2688 return ret;
2689 }
2690
2691 return 0;
5c1143bb
XH		 2692}
2693
2694int intel_init_bsd_ring_buffer(struct drm_device *dev)
2695{
4640c4ff 2696 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2697 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2698
58fa3835
DV		 2699 ring->name = "bsd ring";
2700 ring->id = VCS;
2701
0fd2c201 2702 ring->write_tail = ring_write_tail;
780f18c8 2703 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2704 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2705 /* gen6 bsd needs a special wa for tail updates */
2706 if (IS_GEN6(dev))
2707 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2708 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2709 ring->add_request = gen6_add_request;
2710 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2711 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2712 if (INTEL_INFO(dev)->gen >= 8) {
2713 ring->irq_enable_mask =
2714 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2715 ring->irq_get = gen8_ring_get_irq;
2716 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2717 ring->dispatch_execbuffer =
2718 gen8_ring_dispatch_execbuffer;
707d9cf9 2719 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2720 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2721 ring->semaphore.signal = gen8_xcs_signal;
2722 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2723 }
abd58f01
BW		 2724 } else {
2725 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2726 ring->irq_get = gen6_ring_get_irq;
2727 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2728 ring->dispatch_execbuffer =
2729 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2730 if (i915_semaphore_is_enabled(dev)) {
2731 ring->semaphore.sync_to = gen6_ring_sync;
2732 ring->semaphore.signal = gen6_signal;
2733 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2734 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2735 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2736 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2737 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2738 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2739 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2740 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2741 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2742 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2743 }
abd58f01 2744 }
58fa3835
DV		 2745 } else {
2746 ring->mmio_base = BSD_RING_BASE;
58fa3835 2747 ring->flush = bsd_ring_flush;
8620a3a9 2748 ring->add_request = i9xx_add_request;
58fa3835 2749 ring->get_seqno = ring_get_seqno;
b70ec5bf 2750 ring->set_seqno = ring_set_seqno;
e48d8634 2751 if (IS_GEN5(dev)) {
cc609d5d 2752 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2753 ring->irq_get = gen5_ring_get_irq;
2754 ring->irq_put = gen5_ring_put_irq;
2755 } else {
e3670319 2756 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2757 ring->irq_get = i9xx_ring_get_irq;
2758 ring->irq_put = i9xx_ring_put_irq;
2759 }
fb3256da 2760 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2761 }
ecfe00d8 2762 ring->init_hw = init_ring_common;
58fa3835 2763
1ec14ad3 2764 return intel_init_ring_buffer(dev, ring);
5c1143bb 2765}
549f7365 2766
845f74a7 2767/**
62659920 2768 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2769 */
2770int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2771{
2772 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2773 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2774
f7b64236 2775 ring->name = "bsd2 ring";
845f74a7
ZY		 2776 ring->id = VCS2;
2777
2778 ring->write_tail = ring_write_tail;
2779 ring->mmio_base = GEN8_BSD2_RING_BASE;
2780 ring->flush = gen6_bsd_ring_flush;
2781 ring->add_request = gen6_add_request;
2782 ring->get_seqno = gen6_ring_get_seqno;
2783 ring->set_seqno = ring_set_seqno;
2784 ring->irq_enable_mask =
2785 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2786 ring->irq_get = gen8_ring_get_irq;
2787 ring->irq_put = gen8_ring_put_irq;
2788 ring->dispatch_execbuffer =
2789 gen8_ring_dispatch_execbuffer;
3e78998a 2790 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2791 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2792 ring->semaphore.signal = gen8_xcs_signal;
2793 GEN8_RING_SEMAPHORE_INIT;
2794 }
ecfe00d8 2795 ring->init_hw = init_ring_common;
845f74a7
ZY		 2796
2797 return intel_init_ring_buffer(dev, ring);
2798}
2799
549f7365
CW		 2800int intel_init_blt_ring_buffer(struct drm_device *dev)
2801{
4640c4ff 2802 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2803 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2804
3535d9dd
DV		 2805 ring->name = "blitter ring";
2806 ring->id = BCS;
2807
2808 ring->mmio_base = BLT_RING_BASE;
2809 ring->write_tail = ring_write_tail;
ea251324 2810 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2811 ring->add_request = gen6_add_request;
2812 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2813 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2814 if (INTEL_INFO(dev)->gen >= 8) {
2815 ring->irq_enable_mask =
2816 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2817 ring->irq_get = gen8_ring_get_irq;
2818 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2819 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2820 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2821 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2822 ring->semaphore.signal = gen8_xcs_signal;
2823 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2824 }
abd58f01
BW		 2825 } else {
2826 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2827 ring->irq_get = gen6_ring_get_irq;
2828 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2829 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2830 if (i915_semaphore_is_enabled(dev)) {
2831 ring->semaphore.signal = gen6_signal;
2832 ring->semaphore.sync_to = gen6_ring_sync;
2833 /*
2834 * The current semaphore is only applied on pre-gen8
2835 * platform. And there is no VCS2 ring on the pre-gen8
2836 * platform. So the semaphore between BCS and VCS2 is
2837 * initialized as INVALID. Gen8 will initialize the
2838 * sema between BCS and VCS2 later.
2839 */
2840 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2841 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2842 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2843 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2844 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2845 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2846 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2847 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2848 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2849 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2850 }
abd58f01 2851 }
ecfe00d8 2852 ring->init_hw = init_ring_common;
549f7365 2853
1ec14ad3 2854 return intel_init_ring_buffer(dev, ring);
549f7365 2855}
a7b9761d 2856
9a8a2213
BW		 2857int intel_init_vebox_ring_buffer(struct drm_device *dev)
2858{
4640c4ff 2859 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2860 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2861
2862 ring->name = "video enhancement ring";
2863 ring->id = VECS;
2864
2865 ring->mmio_base = VEBOX_RING_BASE;
2866 ring->write_tail = ring_write_tail;
2867 ring->flush = gen6_ring_flush;
2868 ring->add_request = gen6_add_request;
2869 ring->get_seqno = gen6_ring_get_seqno;
2870 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2871
2872 if (INTEL_INFO(dev)->gen >= 8) {
2873 ring->irq_enable_mask =
40c499f9 2874 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2875 ring->irq_get = gen8_ring_get_irq;
2876 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2877 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2878 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2879 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2880 ring->semaphore.signal = gen8_xcs_signal;
2881 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2882 }
abd58f01
BW		 2883 } else {
2884 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2885 ring->irq_get = hsw_vebox_get_irq;
2886 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2887 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2888 if (i915_semaphore_is_enabled(dev)) {
2889 ring->semaphore.sync_to = gen6_ring_sync;
2890 ring->semaphore.signal = gen6_signal;
2891 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2892 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2893 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2894 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2895 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2896 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2897 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2898 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2899 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2900 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2901 }
abd58f01 2902 }
ecfe00d8 2903 ring->init_hw = init_ring_common;
9a8a2213
BW		 2904
2905 return intel_init_ring_buffer(dev, ring);
2906}
2907
a7b9761d 2908int
4866d729 2909intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2910{
4866d729 2911 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2912 int ret;
2913
2914 if (!ring->gpu_caches_dirty)
2915 return 0;
2916
a84c3ae1 2917 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2918 if (ret)
2919 return ret;
2920
a84c3ae1 2921 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2922
2923 ring->gpu_caches_dirty = false;
2924 return 0;
2925}
2926
2927int
2f20055d 2928intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2929{
2f20055d 2930 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2931 uint32_t flush_domains;
2932 int ret;
2933
2934 flush_domains = 0;
2935 if (ring->gpu_caches_dirty)
2936 flush_domains = I915_GEM_GPU_DOMAINS;
2937
a84c3ae1 2938 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2939 if (ret)
2940 return ret;
2941
a84c3ae1 2942 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2943
2944 ring->gpu_caches_dirty = false;
2945 return 0;
2946}
e3efda49
CW		 2947
2948void
a4872ba6 2949intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2950{
2951 int ret;
2952
2953 if (!intel_ring_initialized(ring))
2954 return;
2955
2956 ret = intel_ring_idle(ring);
2957 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2958 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2959 ring->name, ret);
2960
2961 stop_ring(ring);
2962}
Linux kernel - Deliverables
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