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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
52 | ||
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
1cf0ba14 | 55 | int space = head - (tail + I915_RING_FREE_SPACE); |
c7dca47b | 56 | if (space < 0) |
1cf0ba14 | 57 | space += size; |
c7dca47b CW |
58 | return space; |
59 | } | |
60 | ||
82e104cc | 61 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 62 | { |
82e104cc OM |
63 | return __intel_ring_space(ringbuf->head & HEAD_ADDR, |
64 | ringbuf->tail, ringbuf->size); | |
1cf0ba14 CW |
65 | } |
66 | ||
82e104cc | 67 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
68 | { |
69 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
70 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
71 | } | |
09246732 | 72 | |
a4872ba6 | 73 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 74 | { |
93b0a4e0 OM |
75 | struct intel_ringbuffer *ringbuf = ring->buffer; |
76 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 77 | if (intel_ring_stopped(ring)) |
09246732 | 78 | return; |
93b0a4e0 | 79 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
80 | } |
81 | ||
b72f3acb | 82 | static int |
a4872ba6 | 83 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
84 | u32 invalidate_domains, |
85 | u32 flush_domains) | |
86 | { | |
87 | u32 cmd; | |
88 | int ret; | |
89 | ||
90 | cmd = MI_FLUSH; | |
31b14c9f | 91 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
92 | cmd |= MI_NO_WRITE_FLUSH; |
93 | ||
94 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
95 | cmd |= MI_READ_FLUSH; | |
96 | ||
97 | ret = intel_ring_begin(ring, 2); | |
98 | if (ret) | |
99 | return ret; | |
100 | ||
101 | intel_ring_emit(ring, cmd); | |
102 | intel_ring_emit(ring, MI_NOOP); | |
103 | intel_ring_advance(ring); | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
108 | static int | |
a4872ba6 | 109 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
110 | u32 invalidate_domains, |
111 | u32 flush_domains) | |
62fdfeaf | 112 | { |
78501eac | 113 | struct drm_device *dev = ring->dev; |
6f392d54 | 114 | u32 cmd; |
b72f3acb | 115 | int ret; |
6f392d54 | 116 | |
36d527de CW |
117 | /* |
118 | * read/write caches: | |
119 | * | |
120 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
121 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
122 | * also flushed at 2d versus 3d pipeline switches. | |
123 | * | |
124 | * read-only caches: | |
125 | * | |
126 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
127 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
128 | * | |
129 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
130 | * | |
131 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
132 | * invalidated when MI_EXE_FLUSH is set. | |
133 | * | |
134 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
135 | * invalidated with every MI_FLUSH. | |
136 | * | |
137 | * TLBs: | |
138 | * | |
139 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
140 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
141 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
142 | * are flushed at any MI_FLUSH. | |
143 | */ | |
144 | ||
145 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 146 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 147 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
148 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
149 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 150 | |
36d527de CW |
151 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
152 | (IS_G4X(dev) || IS_GEN5(dev))) | |
153 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 154 | |
36d527de CW |
155 | ret = intel_ring_begin(ring, 2); |
156 | if (ret) | |
157 | return ret; | |
b72f3acb | 158 | |
36d527de CW |
159 | intel_ring_emit(ring, cmd); |
160 | intel_ring_emit(ring, MI_NOOP); | |
161 | intel_ring_advance(ring); | |
b72f3acb CW |
162 | |
163 | return 0; | |
8187a2b7 ZN |
164 | } |
165 | ||
8d315287 JB |
166 | /** |
167 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
168 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
169 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
170 | * | |
171 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
172 | * produced by non-pipelined state commands), software needs to first | |
173 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
174 | * 0. | |
175 | * | |
176 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
177 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
178 | * | |
179 | * And the workaround for these two requires this workaround first: | |
180 | * | |
181 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
182 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
183 | * flushes. | |
184 | * | |
185 | * And this last workaround is tricky because of the requirements on | |
186 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
187 | * volume 2 part 1: | |
188 | * | |
189 | * "1 of the following must also be set: | |
190 | * - Render Target Cache Flush Enable ([12] of DW1) | |
191 | * - Depth Cache Flush Enable ([0] of DW1) | |
192 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
193 | * - Depth Stall ([13] of DW1) | |
194 | * - Post-Sync Operation ([13] of DW1) | |
195 | * - Notify Enable ([8] of DW1)" | |
196 | * | |
197 | * The cache flushes require the workaround flush that triggered this | |
198 | * one, so we can't use it. Depth stall would trigger the same. | |
199 | * Post-sync nonzero is what triggered this second workaround, so we | |
200 | * can't use that one either. Notify enable is IRQs, which aren't | |
201 | * really our business. That leaves only stall at scoreboard. | |
202 | */ | |
203 | static int | |
a4872ba6 | 204 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 205 | { |
18393f63 | 206 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
207 | int ret; |
208 | ||
209 | ||
210 | ret = intel_ring_begin(ring, 6); | |
211 | if (ret) | |
212 | return ret; | |
213 | ||
214 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
215 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
216 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
217 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
218 | intel_ring_emit(ring, 0); /* low dword */ | |
219 | intel_ring_emit(ring, 0); /* high dword */ | |
220 | intel_ring_emit(ring, MI_NOOP); | |
221 | intel_ring_advance(ring); | |
222 | ||
223 | ret = intel_ring_begin(ring, 6); | |
224 | if (ret) | |
225 | return ret; | |
226 | ||
227 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
228 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
229 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
230 | intel_ring_emit(ring, 0); | |
231 | intel_ring_emit(ring, 0); | |
232 | intel_ring_emit(ring, MI_NOOP); | |
233 | intel_ring_advance(ring); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static int | |
a4872ba6 | 239 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
240 | u32 invalidate_domains, u32 flush_domains) |
241 | { | |
242 | u32 flags = 0; | |
18393f63 | 243 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
244 | int ret; |
245 | ||
b3111509 PZ |
246 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
247 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
248 | if (ret) | |
249 | return ret; | |
250 | ||
8d315287 JB |
251 | /* Just flush everything. Experiments have shown that reducing the |
252 | * number of bits based on the write domains has little performance | |
253 | * impact. | |
254 | */ | |
7d54a904 CW |
255 | if (flush_domains) { |
256 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
257 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
258 | /* | |
259 | * Ensure that any following seqno writes only happen | |
260 | * when the render cache is indeed flushed. | |
261 | */ | |
97f209bc | 262 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
263 | } |
264 | if (invalidate_domains) { | |
265 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
266 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
267 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
268 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
269 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
270 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
271 | /* | |
272 | * TLB invalidate requires a post-sync write. | |
273 | */ | |
3ac78313 | 274 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 275 | } |
8d315287 | 276 | |
6c6cf5aa | 277 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
278 | if (ret) |
279 | return ret; | |
280 | ||
6c6cf5aa | 281 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
282 | intel_ring_emit(ring, flags); |
283 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 284 | intel_ring_emit(ring, 0); |
8d315287 JB |
285 | intel_ring_advance(ring); |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
f3987631 | 290 | static int |
a4872ba6 | 291 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
292 | { |
293 | int ret; | |
294 | ||
295 | ret = intel_ring_begin(ring, 4); | |
296 | if (ret) | |
297 | return ret; | |
298 | ||
299 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
300 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
301 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
302 | intel_ring_emit(ring, 0); | |
303 | intel_ring_emit(ring, 0); | |
304 | intel_ring_advance(ring); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
a4872ba6 | 309 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
310 | { |
311 | int ret; | |
312 | ||
313 | if (!ring->fbc_dirty) | |
314 | return 0; | |
315 | ||
37c1d94f | 316 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
317 | if (ret) |
318 | return ret; | |
fd3da6c9 RV |
319 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
320 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
321 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
322 | intel_ring_emit(ring, value); | |
37c1d94f VS |
323 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
324 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
325 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
326 | intel_ring_advance(ring); |
327 | ||
328 | ring->fbc_dirty = false; | |
329 | return 0; | |
330 | } | |
331 | ||
4772eaeb | 332 | static int |
a4872ba6 | 333 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
334 | u32 invalidate_domains, u32 flush_domains) |
335 | { | |
336 | u32 flags = 0; | |
18393f63 | 337 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
338 | int ret; |
339 | ||
f3987631 PZ |
340 | /* |
341 | * Ensure that any following seqno writes only happen when the render | |
342 | * cache is indeed flushed. | |
343 | * | |
344 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
345 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
346 | * don't try to be clever and just set it unconditionally. | |
347 | */ | |
348 | flags |= PIPE_CONTROL_CS_STALL; | |
349 | ||
4772eaeb PZ |
350 | /* Just flush everything. Experiments have shown that reducing the |
351 | * number of bits based on the write domains has little performance | |
352 | * impact. | |
353 | */ | |
354 | if (flush_domains) { | |
355 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
356 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
357 | } |
358 | if (invalidate_domains) { | |
359 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
360 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
361 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
362 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
363 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
364 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
365 | /* | |
366 | * TLB invalidate requires a post-sync write. | |
367 | */ | |
368 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 369 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
370 | |
371 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
372 | * set before a pipe_control command that has the state cache | |
373 | * invalidate bit set. */ | |
374 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
375 | } |
376 | ||
377 | ret = intel_ring_begin(ring, 4); | |
378 | if (ret) | |
379 | return ret; | |
380 | ||
381 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
382 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 383 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
384 | intel_ring_emit(ring, 0); |
385 | intel_ring_advance(ring); | |
386 | ||
9688ecad | 387 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
388 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
389 | ||
4772eaeb PZ |
390 | return 0; |
391 | } | |
392 | ||
884ceace KG |
393 | static int |
394 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
395 | u32 flags, u32 scratch_addr) | |
396 | { | |
397 | int ret; | |
398 | ||
399 | ret = intel_ring_begin(ring, 6); | |
400 | if (ret) | |
401 | return ret; | |
402 | ||
403 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
404 | intel_ring_emit(ring, flags); | |
405 | intel_ring_emit(ring, scratch_addr); | |
406 | intel_ring_emit(ring, 0); | |
407 | intel_ring_emit(ring, 0); | |
408 | intel_ring_emit(ring, 0); | |
409 | intel_ring_advance(ring); | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
a5f3d68e | 414 | static int |
a4872ba6 | 415 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
416 | u32 invalidate_domains, u32 flush_domains) |
417 | { | |
418 | u32 flags = 0; | |
18393f63 | 419 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 420 | int ret; |
a5f3d68e BW |
421 | |
422 | flags |= PIPE_CONTROL_CS_STALL; | |
423 | ||
424 | if (flush_domains) { | |
425 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
426 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
427 | } | |
428 | if (invalidate_domains) { | |
429 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
430 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
431 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
432 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
433 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
434 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
435 | flags |= PIPE_CONTROL_QW_WRITE; | |
436 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
437 | |
438 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
439 | ret = gen8_emit_pipe_control(ring, | |
440 | PIPE_CONTROL_CS_STALL | | |
441 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
442 | 0); | |
443 | if (ret) | |
444 | return ret; | |
a5f3d68e BW |
445 | } |
446 | ||
884ceace | 447 | return gen8_emit_pipe_control(ring, flags, scratch_addr); |
a5f3d68e BW |
448 | } |
449 | ||
a4872ba6 | 450 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 451 | u32 value) |
d46eefa2 | 452 | { |
4640c4ff | 453 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 454 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
455 | } |
456 | ||
a4872ba6 | 457 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 458 | { |
4640c4ff | 459 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 460 | u64 acthd; |
8187a2b7 | 461 | |
50877445 CW |
462 | if (INTEL_INFO(ring->dev)->gen >= 8) |
463 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
464 | RING_ACTHD_UDW(ring->mmio_base)); | |
465 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
466 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
467 | else | |
468 | acthd = I915_READ(ACTHD); | |
469 | ||
470 | return acthd; | |
8187a2b7 ZN |
471 | } |
472 | ||
a4872ba6 | 473 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
474 | { |
475 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
476 | u32 addr; | |
477 | ||
478 | addr = dev_priv->status_page_dmah->busaddr; | |
479 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
480 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
481 | I915_WRITE(HWS_PGA, addr); | |
482 | } | |
483 | ||
a4872ba6 | 484 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 485 | { |
9991ae78 | 486 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 487 | |
9991ae78 CW |
488 | if (!IS_GEN2(ring->dev)) { |
489 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
490 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
491 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
492 | /* Sometimes we observe that the idle flag is not |
493 | * set even though the ring is empty. So double | |
494 | * check before giving up. | |
495 | */ | |
496 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
497 | return false; | |
9991ae78 CW |
498 | } |
499 | } | |
b7884eb4 | 500 | |
7f2ab699 | 501 | I915_WRITE_CTL(ring, 0); |
570ef608 | 502 | I915_WRITE_HEAD(ring, 0); |
78501eac | 503 | ring->write_tail(ring, 0); |
8187a2b7 | 504 | |
9991ae78 CW |
505 | if (!IS_GEN2(ring->dev)) { |
506 | (void)I915_READ_CTL(ring); | |
507 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
508 | } | |
a51435a3 | 509 | |
9991ae78 CW |
510 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
511 | } | |
8187a2b7 | 512 | |
a4872ba6 | 513 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
514 | { |
515 | struct drm_device *dev = ring->dev; | |
516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
517 | struct intel_ringbuffer *ringbuf = ring->buffer; |
518 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
519 | int ret = 0; |
520 | ||
521 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
522 | ||
523 | if (!stop_ring(ring)) { | |
524 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
525 | DRM_DEBUG_KMS("%s head not reset to zero " |
526 | "ctl %08x head %08x tail %08x start %08x\n", | |
527 | ring->name, | |
528 | I915_READ_CTL(ring), | |
529 | I915_READ_HEAD(ring), | |
530 | I915_READ_TAIL(ring), | |
531 | I915_READ_START(ring)); | |
8187a2b7 | 532 | |
9991ae78 | 533 | if (!stop_ring(ring)) { |
6fd0d56e CW |
534 | DRM_ERROR("failed to set %s head to zero " |
535 | "ctl %08x head %08x tail %08x start %08x\n", | |
536 | ring->name, | |
537 | I915_READ_CTL(ring), | |
538 | I915_READ_HEAD(ring), | |
539 | I915_READ_TAIL(ring), | |
540 | I915_READ_START(ring)); | |
9991ae78 CW |
541 | ret = -EIO; |
542 | goto out; | |
6fd0d56e | 543 | } |
8187a2b7 ZN |
544 | } |
545 | ||
9991ae78 CW |
546 | if (I915_NEED_GFX_HWS(dev)) |
547 | intel_ring_setup_status_page(ring); | |
548 | else | |
549 | ring_setup_phys_status_page(ring); | |
550 | ||
ece4a17d JK |
551 | /* Enforce ordering by reading HEAD register back */ |
552 | I915_READ_HEAD(ring); | |
553 | ||
0d8957c8 DV |
554 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
555 | * registers with the above sequence (the readback of the HEAD registers | |
556 | * also enforces ordering), otherwise the hw might lose the new ring | |
557 | * register values. */ | |
f343c5f6 | 558 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 559 | I915_WRITE_CTL(ring, |
93b0a4e0 | 560 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 561 | | RING_VALID); |
8187a2b7 | 562 | |
8187a2b7 | 563 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 564 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 565 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 566 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 567 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
568 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
569 | ring->name, | |
570 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
571 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
572 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
573 | ret = -EIO; |
574 | goto out; | |
8187a2b7 ZN |
575 | } |
576 | ||
78501eac CW |
577 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
578 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 579 | else { |
93b0a4e0 OM |
580 | ringbuf->head = I915_READ_HEAD(ring); |
581 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
82e104cc | 582 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 583 | ringbuf->last_retired_head = -1; |
8187a2b7 | 584 | } |
1ec14ad3 | 585 | |
50f018df CW |
586 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
587 | ||
b7884eb4 | 588 | out: |
c8d9a590 | 589 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
590 | |
591 | return ret; | |
8187a2b7 ZN |
592 | } |
593 | ||
9b1136d5 OM |
594 | void |
595 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
596 | { | |
597 | struct drm_device *dev = ring->dev; | |
598 | ||
599 | if (ring->scratch.obj == NULL) | |
600 | return; | |
601 | ||
602 | if (INTEL_INFO(dev)->gen >= 5) { | |
603 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
604 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
605 | } | |
606 | ||
607 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
608 | ring->scratch.obj = NULL; | |
609 | } | |
610 | ||
611 | int | |
612 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 613 | { |
c6df541c CW |
614 | int ret; |
615 | ||
0d1aacac | 616 | if (ring->scratch.obj) |
c6df541c CW |
617 | return 0; |
618 | ||
0d1aacac CW |
619 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
620 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
621 | DRM_ERROR("Failed to allocate seqno page\n"); |
622 | ret = -ENOMEM; | |
623 | goto err; | |
624 | } | |
e4ffd173 | 625 | |
a9cc726c DV |
626 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
627 | if (ret) | |
628 | goto err_unref; | |
c6df541c | 629 | |
1ec9e26d | 630 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
631 | if (ret) |
632 | goto err_unref; | |
633 | ||
0d1aacac CW |
634 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
635 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
636 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 637 | ret = -ENOMEM; |
c6df541c | 638 | goto err_unpin; |
56b085a0 | 639 | } |
c6df541c | 640 | |
2b1086cc | 641 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 642 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
643 | return 0; |
644 | ||
645 | err_unpin: | |
d7f46fc4 | 646 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 647 | err_unref: |
0d1aacac | 648 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 649 | err: |
c6df541c CW |
650 | return ret; |
651 | } | |
652 | ||
a4872ba6 | 653 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 654 | { |
78501eac | 655 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 656 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 657 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
658 | if (ret) |
659 | return ret; | |
a69ffdbf | 660 | |
61a563a2 AG |
661 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
662 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 663 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
664 | |
665 | /* We need to disable the AsyncFlip performance optimisations in order | |
666 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
667 | * programmed to '1' on all products. | |
8693a824 | 668 | * |
b3f797ac | 669 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 CW |
670 | */ |
671 | if (INTEL_INFO(dev)->gen >= 6) | |
672 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
673 | ||
f05bb0c7 | 674 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 675 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
676 | if (INTEL_INFO(dev)->gen == 6) |
677 | I915_WRITE(GFX_MODE, | |
aa83e30d | 678 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 679 | |
01fa0302 | 680 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
681 | if (IS_GEN7(dev)) |
682 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 683 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 684 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 685 | |
8d315287 | 686 | if (INTEL_INFO(dev)->gen >= 5) { |
9b1136d5 | 687 | ret = intel_init_pipe_control(ring); |
c6df541c CW |
688 | if (ret) |
689 | return ret; | |
690 | } | |
691 | ||
5e13a0c5 | 692 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
693 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
694 | * "If this bit is set, STCunit will have LRA as replacement | |
695 | * policy. [...] This bit must be reset. LRA replacement | |
696 | * policy is not supported." | |
697 | */ | |
698 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 699 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
700 | } |
701 | ||
6b26c86d DV |
702 | if (INTEL_INFO(dev)->gen >= 6) |
703 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 704 | |
040d2baa | 705 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 706 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 707 | |
8187a2b7 ZN |
708 | return ret; |
709 | } | |
710 | ||
a4872ba6 | 711 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 712 | { |
b45305fc | 713 | struct drm_device *dev = ring->dev; |
3e78998a BW |
714 | struct drm_i915_private *dev_priv = dev->dev_private; |
715 | ||
716 | if (dev_priv->semaphore_obj) { | |
717 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
718 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
719 | dev_priv->semaphore_obj = NULL; | |
720 | } | |
b45305fc | 721 | |
9b1136d5 | 722 | intel_fini_pipe_control(ring); |
c6df541c CW |
723 | } |
724 | ||
3e78998a BW |
725 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
726 | unsigned int num_dwords) | |
727 | { | |
728 | #define MBOX_UPDATE_DWORDS 8 | |
729 | struct drm_device *dev = signaller->dev; | |
730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
731 | struct intel_engine_cs *waiter; | |
732 | int i, ret, num_rings; | |
733 | ||
734 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
735 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
736 | #undef MBOX_UPDATE_DWORDS | |
737 | ||
738 | ret = intel_ring_begin(signaller, num_dwords); | |
739 | if (ret) | |
740 | return ret; | |
741 | ||
742 | for_each_ring(waiter, dev_priv, i) { | |
743 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
744 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
745 | continue; | |
746 | ||
747 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
748 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
749 | PIPE_CONTROL_QW_WRITE | | |
750 | PIPE_CONTROL_FLUSH_ENABLE); | |
751 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
752 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
753 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
754 | intel_ring_emit(signaller, 0); | |
755 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
756 | MI_SEMAPHORE_TARGET(waiter->id)); | |
757 | intel_ring_emit(signaller, 0); | |
758 | } | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
764 | unsigned int num_dwords) | |
765 | { | |
766 | #define MBOX_UPDATE_DWORDS 6 | |
767 | struct drm_device *dev = signaller->dev; | |
768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
769 | struct intel_engine_cs *waiter; | |
770 | int i, ret, num_rings; | |
771 | ||
772 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
773 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
774 | #undef MBOX_UPDATE_DWORDS | |
775 | ||
776 | ret = intel_ring_begin(signaller, num_dwords); | |
777 | if (ret) | |
778 | return ret; | |
779 | ||
780 | for_each_ring(waiter, dev_priv, i) { | |
781 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
782 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
783 | continue; | |
784 | ||
785 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | | |
786 | MI_FLUSH_DW_OP_STOREDW); | |
787 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
788 | MI_FLUSH_DW_USE_GTT); | |
789 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
790 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
791 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
792 | MI_SEMAPHORE_TARGET(waiter->id)); | |
793 | intel_ring_emit(signaller, 0); | |
794 | } | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
a4872ba6 | 799 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 800 | unsigned int num_dwords) |
1ec14ad3 | 801 | { |
024a43e1 BW |
802 | struct drm_device *dev = signaller->dev; |
803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 804 | struct intel_engine_cs *useless; |
a1444b79 | 805 | int i, ret, num_rings; |
78325f2d | 806 | |
a1444b79 BW |
807 | #define MBOX_UPDATE_DWORDS 3 |
808 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
809 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
810 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
811 | |
812 | ret = intel_ring_begin(signaller, num_dwords); | |
813 | if (ret) | |
814 | return ret; | |
024a43e1 | 815 | |
78325f2d BW |
816 | for_each_ring(useless, dev_priv, i) { |
817 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
818 | if (mbox_reg != GEN6_NOSYNC) { | |
819 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); | |
820 | intel_ring_emit(signaller, mbox_reg); | |
821 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
78325f2d BW |
822 | } |
823 | } | |
024a43e1 | 824 | |
a1444b79 BW |
825 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
826 | if (num_rings % 2 == 0) | |
827 | intel_ring_emit(signaller, MI_NOOP); | |
828 | ||
024a43e1 | 829 | return 0; |
1ec14ad3 CW |
830 | } |
831 | ||
c8c99b0f BW |
832 | /** |
833 | * gen6_add_request - Update the semaphore mailbox registers | |
834 | * | |
835 | * @ring - ring that is adding a request | |
836 | * @seqno - return seqno stuck into the ring | |
837 | * | |
838 | * Update the mailbox registers in the *other* rings with the current seqno. | |
839 | * This acts like a signal in the canonical semaphore. | |
840 | */ | |
1ec14ad3 | 841 | static int |
a4872ba6 | 842 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 843 | { |
024a43e1 | 844 | int ret; |
52ed2325 | 845 | |
707d9cf9 BW |
846 | if (ring->semaphore.signal) |
847 | ret = ring->semaphore.signal(ring, 4); | |
848 | else | |
849 | ret = intel_ring_begin(ring, 4); | |
850 | ||
1ec14ad3 CW |
851 | if (ret) |
852 | return ret; | |
853 | ||
1ec14ad3 CW |
854 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
855 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 856 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 857 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 858 | __intel_ring_advance(ring); |
1ec14ad3 | 859 | |
1ec14ad3 CW |
860 | return 0; |
861 | } | |
862 | ||
f72b3435 MK |
863 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
864 | u32 seqno) | |
865 | { | |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
867 | return dev_priv->last_seqno < seqno; | |
868 | } | |
869 | ||
c8c99b0f BW |
870 | /** |
871 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
872 | * | |
873 | * @waiter - ring that is waiting | |
874 | * @signaller - ring which has, or will signal | |
875 | * @seqno - seqno which the waiter will block on | |
876 | */ | |
5ee426ca BW |
877 | |
878 | static int | |
879 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
880 | struct intel_engine_cs *signaller, | |
881 | u32 seqno) | |
882 | { | |
883 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
884 | int ret; | |
885 | ||
886 | ret = intel_ring_begin(waiter, 4); | |
887 | if (ret) | |
888 | return ret; | |
889 | ||
890 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
891 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 892 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
893 | MI_SEMAPHORE_SAD_GTE_SDD); |
894 | intel_ring_emit(waiter, seqno); | |
895 | intel_ring_emit(waiter, | |
896 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
897 | intel_ring_emit(waiter, | |
898 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
899 | intel_ring_advance(waiter); | |
900 | return 0; | |
901 | } | |
902 | ||
c8c99b0f | 903 | static int |
a4872ba6 OM |
904 | gen6_ring_sync(struct intel_engine_cs *waiter, |
905 | struct intel_engine_cs *signaller, | |
686cb5f9 | 906 | u32 seqno) |
1ec14ad3 | 907 | { |
c8c99b0f BW |
908 | u32 dw1 = MI_SEMAPHORE_MBOX | |
909 | MI_SEMAPHORE_COMPARE | | |
910 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
911 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
912 | int ret; | |
1ec14ad3 | 913 | |
1500f7ea BW |
914 | /* Throughout all of the GEM code, seqno passed implies our current |
915 | * seqno is >= the last seqno executed. However for hardware the | |
916 | * comparison is strictly greater than. | |
917 | */ | |
918 | seqno -= 1; | |
919 | ||
ebc348b2 | 920 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 921 | |
c8c99b0f | 922 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
923 | if (ret) |
924 | return ret; | |
925 | ||
f72b3435 MK |
926 | /* If seqno wrap happened, omit the wait with no-ops */ |
927 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 928 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
929 | intel_ring_emit(waiter, seqno); |
930 | intel_ring_emit(waiter, 0); | |
931 | intel_ring_emit(waiter, MI_NOOP); | |
932 | } else { | |
933 | intel_ring_emit(waiter, MI_NOOP); | |
934 | intel_ring_emit(waiter, MI_NOOP); | |
935 | intel_ring_emit(waiter, MI_NOOP); | |
936 | intel_ring_emit(waiter, MI_NOOP); | |
937 | } | |
c8c99b0f | 938 | intel_ring_advance(waiter); |
1ec14ad3 CW |
939 | |
940 | return 0; | |
941 | } | |
942 | ||
c6df541c CW |
943 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
944 | do { \ | |
fcbc34e4 KG |
945 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
946 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
947 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
948 | intel_ring_emit(ring__, 0); \ | |
949 | intel_ring_emit(ring__, 0); \ | |
950 | } while (0) | |
951 | ||
952 | static int | |
a4872ba6 | 953 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 954 | { |
18393f63 | 955 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
956 | int ret; |
957 | ||
958 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
959 | * incoherent with writes to memory, i.e. completely fubar, | |
960 | * so we need to use PIPE_NOTIFY instead. | |
961 | * | |
962 | * However, we also need to workaround the qword write | |
963 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
964 | * memory before requesting an interrupt. | |
965 | */ | |
966 | ret = intel_ring_begin(ring, 32); | |
967 | if (ret) | |
968 | return ret; | |
969 | ||
fcbc34e4 | 970 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
971 | PIPE_CONTROL_WRITE_FLUSH | |
972 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 973 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 974 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
975 | intel_ring_emit(ring, 0); |
976 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 977 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 978 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 979 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 980 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 981 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 982 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 983 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 984 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 985 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 986 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 987 | |
fcbc34e4 | 988 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
989 | PIPE_CONTROL_WRITE_FLUSH | |
990 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 991 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 992 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 993 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 994 | intel_ring_emit(ring, 0); |
09246732 | 995 | __intel_ring_advance(ring); |
c6df541c | 996 | |
c6df541c CW |
997 | return 0; |
998 | } | |
999 | ||
4cd53c0c | 1000 | static u32 |
a4872ba6 | 1001 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1002 | { |
4cd53c0c DV |
1003 | /* Workaround to force correct ordering between irq and seqno writes on |
1004 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1005 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1006 | if (!lazy_coherency) { |
1007 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1008 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1009 | } | |
1010 | ||
4cd53c0c DV |
1011 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1012 | } | |
1013 | ||
8187a2b7 | 1014 | static u32 |
a4872ba6 | 1015 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1016 | { |
1ec14ad3 CW |
1017 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1018 | } | |
1019 | ||
b70ec5bf | 1020 | static void |
a4872ba6 | 1021 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1022 | { |
1023 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1024 | } | |
1025 | ||
c6df541c | 1026 | static u32 |
a4872ba6 | 1027 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1028 | { |
0d1aacac | 1029 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1030 | } |
1031 | ||
b70ec5bf | 1032 | static void |
a4872ba6 | 1033 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1034 | { |
0d1aacac | 1035 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1036 | } |
1037 | ||
e48d8634 | 1038 | static bool |
a4872ba6 | 1039 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1040 | { |
1041 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1042 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1043 | unsigned long flags; |
e48d8634 DV |
1044 | |
1045 | if (!dev->irq_enabled) | |
1046 | return false; | |
1047 | ||
7338aefa | 1048 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1049 | if (ring->irq_refcount++ == 0) |
480c8033 | 1050 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1051 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1052 | |
1053 | return true; | |
1054 | } | |
1055 | ||
1056 | static void | |
a4872ba6 | 1057 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1058 | { |
1059 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1060 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1061 | unsigned long flags; |
e48d8634 | 1062 | |
7338aefa | 1063 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1064 | if (--ring->irq_refcount == 0) |
480c8033 | 1065 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1066 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1067 | } |
1068 | ||
b13c2b96 | 1069 | static bool |
a4872ba6 | 1070 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1071 | { |
78501eac | 1072 | struct drm_device *dev = ring->dev; |
4640c4ff | 1073 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1074 | unsigned long flags; |
62fdfeaf | 1075 | |
b13c2b96 CW |
1076 | if (!dev->irq_enabled) |
1077 | return false; | |
1078 | ||
7338aefa | 1079 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1080 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1081 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1082 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1083 | POSTING_READ(IMR); | |
1084 | } | |
7338aefa | 1085 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1086 | |
1087 | return true; | |
62fdfeaf EA |
1088 | } |
1089 | ||
8187a2b7 | 1090 | static void |
a4872ba6 | 1091 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1092 | { |
78501eac | 1093 | struct drm_device *dev = ring->dev; |
4640c4ff | 1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1095 | unsigned long flags; |
62fdfeaf | 1096 | |
7338aefa | 1097 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1098 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1099 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1100 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1101 | POSTING_READ(IMR); | |
1102 | } | |
7338aefa | 1103 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1104 | } |
1105 | ||
c2798b19 | 1106 | static bool |
a4872ba6 | 1107 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1108 | { |
1109 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1110 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1111 | unsigned long flags; |
c2798b19 CW |
1112 | |
1113 | if (!dev->irq_enabled) | |
1114 | return false; | |
1115 | ||
7338aefa | 1116 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1117 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1118 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1119 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1120 | POSTING_READ16(IMR); | |
1121 | } | |
7338aefa | 1122 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1123 | |
1124 | return true; | |
1125 | } | |
1126 | ||
1127 | static void | |
a4872ba6 | 1128 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1129 | { |
1130 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1131 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1132 | unsigned long flags; |
c2798b19 | 1133 | |
7338aefa | 1134 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1135 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1136 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1137 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1138 | POSTING_READ16(IMR); | |
1139 | } | |
7338aefa | 1140 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1141 | } |
1142 | ||
a4872ba6 | 1143 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1144 | { |
4593010b | 1145 | struct drm_device *dev = ring->dev; |
4640c4ff | 1146 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1147 | u32 mmio = 0; |
1148 | ||
1149 | /* The ring status page addresses are no longer next to the rest of | |
1150 | * the ring registers as of gen7. | |
1151 | */ | |
1152 | if (IS_GEN7(dev)) { | |
1153 | switch (ring->id) { | |
96154f2f | 1154 | case RCS: |
4593010b EA |
1155 | mmio = RENDER_HWS_PGA_GEN7; |
1156 | break; | |
96154f2f | 1157 | case BCS: |
4593010b EA |
1158 | mmio = BLT_HWS_PGA_GEN7; |
1159 | break; | |
77fe2ff3 ZY |
1160 | /* |
1161 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1162 | * gcc switch check warning | |
1163 | */ | |
1164 | case VCS2: | |
96154f2f | 1165 | case VCS: |
4593010b EA |
1166 | mmio = BSD_HWS_PGA_GEN7; |
1167 | break; | |
4a3dd19d | 1168 | case VECS: |
9a8a2213 BW |
1169 | mmio = VEBOX_HWS_PGA_GEN7; |
1170 | break; | |
4593010b EA |
1171 | } |
1172 | } else if (IS_GEN6(ring->dev)) { | |
1173 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1174 | } else { | |
eb0d4b75 | 1175 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1176 | mmio = RING_HWS_PGA(ring->mmio_base); |
1177 | } | |
1178 | ||
78501eac CW |
1179 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1180 | POSTING_READ(mmio); | |
884020bf | 1181 | |
dc616b89 DL |
1182 | /* |
1183 | * Flush the TLB for this page | |
1184 | * | |
1185 | * FIXME: These two bits have disappeared on gen8, so a question | |
1186 | * arises: do we still need this and if so how should we go about | |
1187 | * invalidating the TLB? | |
1188 | */ | |
1189 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1190 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1191 | |
1192 | /* ring should be idle before issuing a sync flush*/ | |
1193 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1194 | ||
884020bf CW |
1195 | I915_WRITE(reg, |
1196 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1197 | INSTPM_SYNC_FLUSH)); | |
1198 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1199 | 1000)) | |
1200 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1201 | ring->name); | |
1202 | } | |
8187a2b7 ZN |
1203 | } |
1204 | ||
b72f3acb | 1205 | static int |
a4872ba6 | 1206 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1207 | u32 invalidate_domains, |
1208 | u32 flush_domains) | |
d1b851fc | 1209 | { |
b72f3acb CW |
1210 | int ret; |
1211 | ||
b72f3acb CW |
1212 | ret = intel_ring_begin(ring, 2); |
1213 | if (ret) | |
1214 | return ret; | |
1215 | ||
1216 | intel_ring_emit(ring, MI_FLUSH); | |
1217 | intel_ring_emit(ring, MI_NOOP); | |
1218 | intel_ring_advance(ring); | |
1219 | return 0; | |
d1b851fc ZN |
1220 | } |
1221 | ||
3cce469c | 1222 | static int |
a4872ba6 | 1223 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1224 | { |
3cce469c CW |
1225 | int ret; |
1226 | ||
1227 | ret = intel_ring_begin(ring, 4); | |
1228 | if (ret) | |
1229 | return ret; | |
6f392d54 | 1230 | |
3cce469c CW |
1231 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1232 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1233 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1234 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1235 | __intel_ring_advance(ring); |
d1b851fc | 1236 | |
3cce469c | 1237 | return 0; |
d1b851fc ZN |
1238 | } |
1239 | ||
0f46832f | 1240 | static bool |
a4872ba6 | 1241 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1242 | { |
1243 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1244 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1245 | unsigned long flags; |
0f46832f CW |
1246 | |
1247 | if (!dev->irq_enabled) | |
1248 | return false; | |
1249 | ||
7338aefa | 1250 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1251 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1252 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1253 | I915_WRITE_IMR(ring, |
1254 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1255 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1256 | else |
1257 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1258 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1259 | } |
7338aefa | 1260 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1261 | |
1262 | return true; | |
1263 | } | |
1264 | ||
1265 | static void | |
a4872ba6 | 1266 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1267 | { |
1268 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1269 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1270 | unsigned long flags; |
0f46832f | 1271 | |
7338aefa | 1272 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1273 | if (--ring->irq_refcount == 0) { |
040d2baa | 1274 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1275 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1276 | else |
1277 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1278 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1279 | } |
7338aefa | 1280 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1281 | } |
1282 | ||
a19d2933 | 1283 | static bool |
a4872ba6 | 1284 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1285 | { |
1286 | struct drm_device *dev = ring->dev; | |
1287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1288 | unsigned long flags; | |
1289 | ||
1290 | if (!dev->irq_enabled) | |
1291 | return false; | |
1292 | ||
59cdb63d | 1293 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1294 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1295 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1296 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1297 | } |
59cdb63d | 1298 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1299 | |
1300 | return true; | |
1301 | } | |
1302 | ||
1303 | static void | |
a4872ba6 | 1304 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1305 | { |
1306 | struct drm_device *dev = ring->dev; | |
1307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1308 | unsigned long flags; | |
1309 | ||
1310 | if (!dev->irq_enabled) | |
1311 | return; | |
1312 | ||
59cdb63d | 1313 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1314 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1315 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1316 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1317 | } |
59cdb63d | 1318 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1319 | } |
1320 | ||
abd58f01 | 1321 | static bool |
a4872ba6 | 1322 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1323 | { |
1324 | struct drm_device *dev = ring->dev; | |
1325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1326 | unsigned long flags; | |
1327 | ||
1328 | if (!dev->irq_enabled) | |
1329 | return false; | |
1330 | ||
1331 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1332 | if (ring->irq_refcount++ == 0) { | |
1333 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1334 | I915_WRITE_IMR(ring, | |
1335 | ~(ring->irq_enable_mask | | |
1336 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1337 | } else { | |
1338 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1339 | } | |
1340 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1341 | } | |
1342 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1343 | ||
1344 | return true; | |
1345 | } | |
1346 | ||
1347 | static void | |
a4872ba6 | 1348 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1349 | { |
1350 | struct drm_device *dev = ring->dev; | |
1351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1352 | unsigned long flags; | |
1353 | ||
1354 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1355 | if (--ring->irq_refcount == 0) { | |
1356 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1357 | I915_WRITE_IMR(ring, | |
1358 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1359 | } else { | |
1360 | I915_WRITE_IMR(ring, ~0); | |
1361 | } | |
1362 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1363 | } | |
1364 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1365 | } | |
1366 | ||
d1b851fc | 1367 | static int |
a4872ba6 | 1368 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1369 | u64 offset, u32 length, |
d7d4eedd | 1370 | unsigned flags) |
d1b851fc | 1371 | { |
e1f99ce6 | 1372 | int ret; |
78501eac | 1373 | |
e1f99ce6 CW |
1374 | ret = intel_ring_begin(ring, 2); |
1375 | if (ret) | |
1376 | return ret; | |
1377 | ||
78501eac | 1378 | intel_ring_emit(ring, |
65f56876 CW |
1379 | MI_BATCH_BUFFER_START | |
1380 | MI_BATCH_GTT | | |
d7d4eedd | 1381 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1382 | intel_ring_emit(ring, offset); |
78501eac CW |
1383 | intel_ring_advance(ring); |
1384 | ||
d1b851fc ZN |
1385 | return 0; |
1386 | } | |
1387 | ||
b45305fc DV |
1388 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1389 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1390 | static int |
a4872ba6 | 1391 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1392 | u64 offset, u32 len, |
d7d4eedd | 1393 | unsigned flags) |
62fdfeaf | 1394 | { |
c4e7a414 | 1395 | int ret; |
62fdfeaf | 1396 | |
b45305fc DV |
1397 | if (flags & I915_DISPATCH_PINNED) { |
1398 | ret = intel_ring_begin(ring, 4); | |
1399 | if (ret) | |
1400 | return ret; | |
62fdfeaf | 1401 | |
b45305fc DV |
1402 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1403 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1404 | intel_ring_emit(ring, offset + len - 8); | |
1405 | intel_ring_emit(ring, MI_NOOP); | |
1406 | intel_ring_advance(ring); | |
1407 | } else { | |
0d1aacac | 1408 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1409 | |
1410 | if (len > I830_BATCH_LIMIT) | |
1411 | return -ENOSPC; | |
1412 | ||
1413 | ret = intel_ring_begin(ring, 9+3); | |
1414 | if (ret) | |
1415 | return ret; | |
1416 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1417 | * scratch bo area (so that the CS never stumbles over its tlb | |
1418 | * invalidation bug) ... */ | |
1419 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1420 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1421 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1422 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1423 | intel_ring_emit(ring, 0); | |
1424 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1425 | intel_ring_emit(ring, cs_offset); | |
1426 | intel_ring_emit(ring, 0); | |
1427 | intel_ring_emit(ring, 4096); | |
1428 | intel_ring_emit(ring, offset); | |
1429 | intel_ring_emit(ring, MI_FLUSH); | |
1430 | ||
1431 | /* ... and execute it. */ | |
1432 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1433 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1434 | intel_ring_emit(ring, cs_offset + len - 8); | |
1435 | intel_ring_advance(ring); | |
1436 | } | |
e1f99ce6 | 1437 | |
fb3256da DV |
1438 | return 0; |
1439 | } | |
1440 | ||
1441 | static int | |
a4872ba6 | 1442 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1443 | u64 offset, u32 len, |
d7d4eedd | 1444 | unsigned flags) |
fb3256da DV |
1445 | { |
1446 | int ret; | |
1447 | ||
1448 | ret = intel_ring_begin(ring, 2); | |
1449 | if (ret) | |
1450 | return ret; | |
1451 | ||
65f56876 | 1452 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1453 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1454 | intel_ring_advance(ring); |
62fdfeaf | 1455 | |
62fdfeaf EA |
1456 | return 0; |
1457 | } | |
1458 | ||
a4872ba6 | 1459 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1460 | { |
05394f39 | 1461 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1462 | |
8187a2b7 ZN |
1463 | obj = ring->status_page.obj; |
1464 | if (obj == NULL) | |
62fdfeaf | 1465 | return; |
62fdfeaf | 1466 | |
9da3da66 | 1467 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1468 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1469 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1470 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1471 | } |
1472 | ||
a4872ba6 | 1473 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1474 | { |
05394f39 | 1475 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1476 | |
e3efda49 | 1477 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1478 | unsigned flags; |
e3efda49 | 1479 | int ret; |
e4ffd173 | 1480 | |
e3efda49 CW |
1481 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1482 | if (obj == NULL) { | |
1483 | DRM_ERROR("Failed to allocate status page\n"); | |
1484 | return -ENOMEM; | |
1485 | } | |
62fdfeaf | 1486 | |
e3efda49 CW |
1487 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1488 | if (ret) | |
1489 | goto err_unref; | |
1490 | ||
1f767e02 CW |
1491 | flags = 0; |
1492 | if (!HAS_LLC(ring->dev)) | |
1493 | /* On g33, we cannot place HWS above 256MiB, so | |
1494 | * restrict its pinning to the low mappable arena. | |
1495 | * Though this restriction is not documented for | |
1496 | * gen4, gen5, or byt, they also behave similarly | |
1497 | * and hang if the HWS is placed at the top of the | |
1498 | * GTT. To generalise, it appears that all !llc | |
1499 | * platforms have issues with us placing the HWS | |
1500 | * above the mappable region (even though we never | |
1501 | * actualy map it). | |
1502 | */ | |
1503 | flags |= PIN_MAPPABLE; | |
1504 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1505 | if (ret) { |
1506 | err_unref: | |
1507 | drm_gem_object_unreference(&obj->base); | |
1508 | return ret; | |
1509 | } | |
1510 | ||
1511 | ring->status_page.obj = obj; | |
1512 | } | |
62fdfeaf | 1513 | |
f343c5f6 | 1514 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1515 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1516 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1517 | |
8187a2b7 ZN |
1518 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1519 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1520 | |
1521 | return 0; | |
62fdfeaf EA |
1522 | } |
1523 | ||
a4872ba6 | 1524 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1525 | { |
1526 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1527 | |
1528 | if (!dev_priv->status_page_dmah) { | |
1529 | dev_priv->status_page_dmah = | |
1530 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1531 | if (!dev_priv->status_page_dmah) | |
1532 | return -ENOMEM; | |
1533 | } | |
1534 | ||
6b8294a4 CW |
1535 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1536 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
84c2377f | 1541 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 OM |
1542 | { |
1543 | if (!ringbuf->obj) | |
1544 | return; | |
1545 | ||
1546 | iounmap(ringbuf->virtual_start); | |
1547 | i915_gem_object_ggtt_unpin(ringbuf->obj); | |
1548 | drm_gem_object_unreference(&ringbuf->obj->base); | |
1549 | ringbuf->obj = NULL; | |
1550 | } | |
1551 | ||
84c2377f OM |
1552 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1553 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1554 | { |
e3efda49 | 1555 | struct drm_i915_private *dev_priv = to_i915(dev); |
05394f39 | 1556 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
1557 | int ret; |
1558 | ||
2919d291 | 1559 | if (ringbuf->obj) |
e3efda49 | 1560 | return 0; |
62fdfeaf | 1561 | |
ebc052e0 CW |
1562 | obj = NULL; |
1563 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1564 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1565 | if (obj == NULL) |
93b0a4e0 | 1566 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1567 | if (obj == NULL) |
1568 | return -ENOMEM; | |
8187a2b7 | 1569 | |
24f3a8cf AG |
1570 | /* mark ring buffers as read-only from GPU side by default */ |
1571 | obj->gt_ro = 1; | |
1572 | ||
1ec9e26d | 1573 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1574 | if (ret) |
1575 | goto err_unref; | |
62fdfeaf | 1576 | |
3eef8918 CW |
1577 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1578 | if (ret) | |
1579 | goto err_unpin; | |
1580 | ||
93b0a4e0 | 1581 | ringbuf->virtual_start = |
f343c5f6 | 1582 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
93b0a4e0 OM |
1583 | ringbuf->size); |
1584 | if (ringbuf->virtual_start == NULL) { | |
8187a2b7 | 1585 | ret = -EINVAL; |
dd785e35 | 1586 | goto err_unpin; |
62fdfeaf EA |
1587 | } |
1588 | ||
93b0a4e0 | 1589 | ringbuf->obj = obj; |
e3efda49 CW |
1590 | return 0; |
1591 | ||
1592 | err_unpin: | |
1593 | i915_gem_object_ggtt_unpin(obj); | |
1594 | err_unref: | |
1595 | drm_gem_object_unreference(&obj->base); | |
1596 | return ret; | |
1597 | } | |
1598 | ||
1599 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1600 | struct intel_engine_cs *ring) |
e3efda49 | 1601 | { |
8ee14975 | 1602 | struct intel_ringbuffer *ringbuf = ring->buffer; |
e3efda49 CW |
1603 | int ret; |
1604 | ||
8ee14975 OM |
1605 | if (ringbuf == NULL) { |
1606 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1607 | if (!ringbuf) | |
1608 | return -ENOMEM; | |
1609 | ring->buffer = ringbuf; | |
1610 | } | |
1611 | ||
e3efda49 CW |
1612 | ring->dev = dev; |
1613 | INIT_LIST_HEAD(&ring->active_list); | |
1614 | INIT_LIST_HEAD(&ring->request_list); | |
93b0a4e0 | 1615 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1616 | ringbuf->ring = ring; |
ebc348b2 | 1617 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1618 | |
1619 | init_waitqueue_head(&ring->irq_queue); | |
1620 | ||
1621 | if (I915_NEED_GFX_HWS(dev)) { | |
1622 | ret = init_status_page(ring); | |
1623 | if (ret) | |
8ee14975 | 1624 | goto error; |
e3efda49 CW |
1625 | } else { |
1626 | BUG_ON(ring->id != RCS); | |
1627 | ret = init_phys_status_page(ring); | |
1628 | if (ret) | |
8ee14975 | 1629 | goto error; |
e3efda49 CW |
1630 | } |
1631 | ||
2919d291 | 1632 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
e3efda49 CW |
1633 | if (ret) { |
1634 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); | |
8ee14975 | 1635 | goto error; |
e3efda49 | 1636 | } |
62fdfeaf | 1637 | |
55249baa CW |
1638 | /* Workaround an erratum on the i830 which causes a hang if |
1639 | * the TAIL pointer points to within the last 2 cachelines | |
1640 | * of the buffer. | |
1641 | */ | |
93b0a4e0 | 1642 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1643 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1644 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1645 | |
44e895a8 BV |
1646 | ret = i915_cmd_parser_init_ring(ring); |
1647 | if (ret) | |
8ee14975 OM |
1648 | goto error; |
1649 | ||
1650 | ret = ring->init(ring); | |
1651 | if (ret) | |
1652 | goto error; | |
1653 | ||
1654 | return 0; | |
351e3db2 | 1655 | |
8ee14975 OM |
1656 | error: |
1657 | kfree(ringbuf); | |
1658 | ring->buffer = NULL; | |
1659 | return ret; | |
62fdfeaf EA |
1660 | } |
1661 | ||
a4872ba6 | 1662 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1663 | { |
e3efda49 | 1664 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
93b0a4e0 | 1665 | struct intel_ringbuffer *ringbuf = ring->buffer; |
33626e6a | 1666 | |
93b0a4e0 | 1667 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1668 | return; |
1669 | ||
e3efda49 | 1670 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1671 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1672 | |
2919d291 | 1673 | intel_destroy_ringbuffer_obj(ringbuf); |
3d57e5bd BW |
1674 | ring->preallocated_lazy_request = NULL; |
1675 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1676 | |
8d19215b ZN |
1677 | if (ring->cleanup) |
1678 | ring->cleanup(ring); | |
1679 | ||
78501eac | 1680 | cleanup_status_page(ring); |
44e895a8 BV |
1681 | |
1682 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1683 | |
93b0a4e0 | 1684 | kfree(ringbuf); |
8ee14975 | 1685 | ring->buffer = NULL; |
62fdfeaf EA |
1686 | } |
1687 | ||
a4872ba6 | 1688 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1689 | { |
93b0a4e0 | 1690 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1691 | struct drm_i915_gem_request *request; |
1cf0ba14 | 1692 | u32 seqno = 0; |
a71d8d94 CW |
1693 | int ret; |
1694 | ||
93b0a4e0 OM |
1695 | if (ringbuf->last_retired_head != -1) { |
1696 | ringbuf->head = ringbuf->last_retired_head; | |
1697 | ringbuf->last_retired_head = -1; | |
1f70999f | 1698 | |
82e104cc | 1699 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 1700 | if (ringbuf->space >= n) |
a71d8d94 CW |
1701 | return 0; |
1702 | } | |
1703 | ||
1704 | list_for_each_entry(request, &ring->request_list, list) { | |
82e104cc OM |
1705 | if (__intel_ring_space(request->tail, ringbuf->tail, |
1706 | ringbuf->size) >= n) { | |
a71d8d94 CW |
1707 | seqno = request->seqno; |
1708 | break; | |
1709 | } | |
a71d8d94 CW |
1710 | } |
1711 | ||
1712 | if (seqno == 0) | |
1713 | return -ENOSPC; | |
1714 | ||
1f70999f | 1715 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1716 | if (ret) |
1717 | return ret; | |
1718 | ||
1cf0ba14 | 1719 | i915_gem_retire_requests_ring(ring); |
93b0a4e0 OM |
1720 | ringbuf->head = ringbuf->last_retired_head; |
1721 | ringbuf->last_retired_head = -1; | |
a71d8d94 | 1722 | |
82e104cc | 1723 | ringbuf->space = intel_ring_space(ringbuf); |
a71d8d94 CW |
1724 | return 0; |
1725 | } | |
1726 | ||
a4872ba6 | 1727 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1728 | { |
78501eac | 1729 | struct drm_device *dev = ring->dev; |
cae5852d | 1730 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1731 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1732 | unsigned long end; |
a71d8d94 | 1733 | int ret; |
c7dca47b | 1734 | |
a71d8d94 CW |
1735 | ret = intel_ring_wait_request(ring, n); |
1736 | if (ret != -ENOSPC) | |
1737 | return ret; | |
1738 | ||
09246732 CW |
1739 | /* force the tail write in case we have been skipping them */ |
1740 | __intel_ring_advance(ring); | |
1741 | ||
63ed2cb2 DV |
1742 | /* With GEM the hangcheck timer should kick us out of the loop, |
1743 | * leaving it early runs the risk of corrupting GEM state (due | |
1744 | * to running on almost untested codepaths). But on resume | |
1745 | * timers don't work yet, so prevent a complete hang in that | |
1746 | * case by choosing an insanely large timeout. */ | |
1747 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1748 | |
dcfe0506 | 1749 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1750 | do { |
93b0a4e0 | 1751 | ringbuf->head = I915_READ_HEAD(ring); |
82e104cc | 1752 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 1753 | if (ringbuf->space >= n) { |
dcfe0506 CW |
1754 | ret = 0; |
1755 | break; | |
62fdfeaf EA |
1756 | } |
1757 | ||
fb19e2ac DV |
1758 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1759 | dev->primary->master) { | |
62fdfeaf EA |
1760 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1761 | if (master_priv->sarea_priv) | |
1762 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1763 | } | |
d1b851fc | 1764 | |
e60a0b10 | 1765 | msleep(1); |
d6b2c790 | 1766 | |
dcfe0506 CW |
1767 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1768 | ret = -ERESTARTSYS; | |
1769 | break; | |
1770 | } | |
1771 | ||
33196ded DV |
1772 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1773 | dev_priv->mm.interruptible); | |
d6b2c790 | 1774 | if (ret) |
dcfe0506 CW |
1775 | break; |
1776 | ||
1777 | if (time_after(jiffies, end)) { | |
1778 | ret = -EBUSY; | |
1779 | break; | |
1780 | } | |
1781 | } while (1); | |
db53a302 | 1782 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1783 | return ret; |
8187a2b7 | 1784 | } |
62fdfeaf | 1785 | |
a4872ba6 | 1786 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1787 | { |
1788 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1789 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1790 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1791 | |
93b0a4e0 | 1792 | if (ringbuf->space < rem) { |
3e960501 CW |
1793 | int ret = ring_wait_for_space(ring, rem); |
1794 | if (ret) | |
1795 | return ret; | |
1796 | } | |
1797 | ||
93b0a4e0 | 1798 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1799 | rem /= 4; |
1800 | while (rem--) | |
1801 | iowrite32(MI_NOOP, virt++); | |
1802 | ||
93b0a4e0 | 1803 | ringbuf->tail = 0; |
82e104cc | 1804 | ringbuf->space = intel_ring_space(ringbuf); |
3e960501 CW |
1805 | |
1806 | return 0; | |
1807 | } | |
1808 | ||
a4872ba6 | 1809 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 CW |
1810 | { |
1811 | u32 seqno; | |
1812 | int ret; | |
1813 | ||
1814 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1815 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1816 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1817 | if (ret) |
1818 | return ret; | |
1819 | } | |
1820 | ||
1821 | /* Wait upon the last request to be completed */ | |
1822 | if (list_empty(&ring->request_list)) | |
1823 | return 0; | |
1824 | ||
1825 | seqno = list_entry(ring->request_list.prev, | |
1826 | struct drm_i915_gem_request, | |
1827 | list)->seqno; | |
1828 | ||
1829 | return i915_wait_seqno(ring, seqno); | |
1830 | } | |
1831 | ||
9d773091 | 1832 | static int |
a4872ba6 | 1833 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
9d773091 | 1834 | { |
1823521d | 1835 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1836 | return 0; |
1837 | ||
3c0e234c CW |
1838 | if (ring->preallocated_lazy_request == NULL) { |
1839 | struct drm_i915_gem_request *request; | |
1840 | ||
1841 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1842 | if (request == NULL) | |
1843 | return -ENOMEM; | |
1844 | ||
1845 | ring->preallocated_lazy_request = request; | |
1846 | } | |
1847 | ||
1823521d | 1848 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1849 | } |
1850 | ||
a4872ba6 | 1851 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 1852 | int bytes) |
cbcc80df | 1853 | { |
93b0a4e0 | 1854 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
1855 | int ret; |
1856 | ||
93b0a4e0 | 1857 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
1858 | ret = intel_wrap_ring_buffer(ring); |
1859 | if (unlikely(ret)) | |
1860 | return ret; | |
1861 | } | |
1862 | ||
93b0a4e0 | 1863 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
1864 | ret = ring_wait_for_space(ring, bytes); |
1865 | if (unlikely(ret)) | |
1866 | return ret; | |
1867 | } | |
1868 | ||
cbcc80df MK |
1869 | return 0; |
1870 | } | |
1871 | ||
a4872ba6 | 1872 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 1873 | int num_dwords) |
8187a2b7 | 1874 | { |
4640c4ff | 1875 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1876 | int ret; |
78501eac | 1877 | |
33196ded DV |
1878 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1879 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1880 | if (ret) |
1881 | return ret; | |
21dd3734 | 1882 | |
304d695c CW |
1883 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1884 | if (ret) | |
1885 | return ret; | |
1886 | ||
9d773091 CW |
1887 | /* Preallocate the olr before touching the ring */ |
1888 | ret = intel_ring_alloc_seqno(ring); | |
1889 | if (ret) | |
1890 | return ret; | |
1891 | ||
ee1b1e5e | 1892 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 1893 | return 0; |
8187a2b7 | 1894 | } |
78501eac | 1895 | |
753b1ad4 | 1896 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 1897 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 1898 | { |
ee1b1e5e | 1899 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
1900 | int ret; |
1901 | ||
1902 | if (num_dwords == 0) | |
1903 | return 0; | |
1904 | ||
18393f63 | 1905 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
1906 | ret = intel_ring_begin(ring, num_dwords); |
1907 | if (ret) | |
1908 | return ret; | |
1909 | ||
1910 | while (num_dwords--) | |
1911 | intel_ring_emit(ring, MI_NOOP); | |
1912 | ||
1913 | intel_ring_advance(ring); | |
1914 | ||
1915 | return 0; | |
1916 | } | |
1917 | ||
a4872ba6 | 1918 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 1919 | { |
3b2cc8ab OM |
1920 | struct drm_device *dev = ring->dev; |
1921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 1922 | |
1823521d | 1923 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1924 | |
3b2cc8ab | 1925 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
1926 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
1927 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 1928 | if (HAS_VEBOX(dev)) |
5020150b | 1929 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 1930 | } |
d97ed339 | 1931 | |
f7e98ad4 | 1932 | ring->set_seqno(ring, seqno); |
92cab734 | 1933 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1934 | } |
62fdfeaf | 1935 | |
a4872ba6 | 1936 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 1937 | u32 value) |
881f47b6 | 1938 | { |
4640c4ff | 1939 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1940 | |
1941 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1942 | |
1943 | /* Disable notification that the ring is IDLE. The GT | |
1944 | * will then assume that it is busy and bring it out of rc6. | |
1945 | */ | |
0206e353 | 1946 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1947 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1948 | ||
1949 | /* Clear the context id. Here be magic! */ | |
1950 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1951 | |
12f55818 | 1952 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1953 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1954 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1955 | 50)) | |
1956 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1957 | |
12f55818 | 1958 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1959 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1960 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1961 | ||
1962 | /* Let the ring send IDLE messages to the GT again, | |
1963 | * and so let it sleep to conserve power when idle. | |
1964 | */ | |
0206e353 | 1965 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1966 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1967 | } |
1968 | ||
a4872ba6 | 1969 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 1970 | u32 invalidate, u32 flush) |
881f47b6 | 1971 | { |
71a77e07 | 1972 | uint32_t cmd; |
b72f3acb CW |
1973 | int ret; |
1974 | ||
b72f3acb CW |
1975 | ret = intel_ring_begin(ring, 4); |
1976 | if (ret) | |
1977 | return ret; | |
1978 | ||
71a77e07 | 1979 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1980 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1981 | cmd += 1; | |
9a289771 JB |
1982 | /* |
1983 | * Bspec vol 1c.5 - video engine command streamer: | |
1984 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1985 | * operation is complete. This bit is only valid when the | |
1986 | * Post-Sync Operation field is a value of 1h or 3h." | |
1987 | */ | |
71a77e07 | 1988 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1989 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1990 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1991 | intel_ring_emit(ring, cmd); |
9a289771 | 1992 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1993 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1994 | intel_ring_emit(ring, 0); /* upper addr */ | |
1995 | intel_ring_emit(ring, 0); /* value */ | |
1996 | } else { | |
1997 | intel_ring_emit(ring, 0); | |
1998 | intel_ring_emit(ring, MI_NOOP); | |
1999 | } | |
b72f3acb CW |
2000 | intel_ring_advance(ring); |
2001 | return 0; | |
881f47b6 XH |
2002 | } |
2003 | ||
1c7a0623 | 2004 | static int |
a4872ba6 | 2005 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2006 | u64 offset, u32 len, |
1c7a0623 BW |
2007 | unsigned flags) |
2008 | { | |
28cf5415 BW |
2009 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
2010 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
2011 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
2012 | int ret; |
2013 | ||
2014 | ret = intel_ring_begin(ring, 4); | |
2015 | if (ret) | |
2016 | return ret; | |
2017 | ||
2018 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2019 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2020 | intel_ring_emit(ring, lower_32_bits(offset)); |
2021 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2022 | intel_ring_emit(ring, MI_NOOP); |
2023 | intel_ring_advance(ring); | |
2024 | ||
2025 | return 0; | |
2026 | } | |
2027 | ||
d7d4eedd | 2028 | static int |
a4872ba6 | 2029 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2030 | u64 offset, u32 len, |
d7d4eedd CW |
2031 | unsigned flags) |
2032 | { | |
2033 | int ret; | |
2034 | ||
2035 | ret = intel_ring_begin(ring, 2); | |
2036 | if (ret) | |
2037 | return ret; | |
2038 | ||
2039 | intel_ring_emit(ring, | |
2040 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
2041 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
2042 | /* bit0-7 is the length on GEN6+ */ | |
2043 | intel_ring_emit(ring, offset); | |
2044 | intel_ring_advance(ring); | |
2045 | ||
2046 | return 0; | |
2047 | } | |
2048 | ||
881f47b6 | 2049 | static int |
a4872ba6 | 2050 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2051 | u64 offset, u32 len, |
d7d4eedd | 2052 | unsigned flags) |
881f47b6 | 2053 | { |
0206e353 | 2054 | int ret; |
ab6f8e32 | 2055 | |
0206e353 AJ |
2056 | ret = intel_ring_begin(ring, 2); |
2057 | if (ret) | |
2058 | return ret; | |
e1f99ce6 | 2059 | |
d7d4eedd CW |
2060 | intel_ring_emit(ring, |
2061 | MI_BATCH_BUFFER_START | | |
2062 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2063 | /* bit0-7 is the length on GEN6+ */ |
2064 | intel_ring_emit(ring, offset); | |
2065 | intel_ring_advance(ring); | |
ab6f8e32 | 2066 | |
0206e353 | 2067 | return 0; |
881f47b6 XH |
2068 | } |
2069 | ||
549f7365 CW |
2070 | /* Blitter support (SandyBridge+) */ |
2071 | ||
a4872ba6 | 2072 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2073 | u32 invalidate, u32 flush) |
8d19215b | 2074 | { |
fd3da6c9 | 2075 | struct drm_device *dev = ring->dev; |
71a77e07 | 2076 | uint32_t cmd; |
b72f3acb CW |
2077 | int ret; |
2078 | ||
6a233c78 | 2079 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2080 | if (ret) |
2081 | return ret; | |
2082 | ||
71a77e07 | 2083 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2084 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2085 | cmd += 1; | |
9a289771 JB |
2086 | /* |
2087 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2088 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2089 | * operation is complete. This bit is only valid when the | |
2090 | * Post-Sync Operation field is a value of 1h or 3h." | |
2091 | */ | |
71a77e07 | 2092 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2093 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2094 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2095 | intel_ring_emit(ring, cmd); |
9a289771 | 2096 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2097 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2098 | intel_ring_emit(ring, 0); /* upper addr */ | |
2099 | intel_ring_emit(ring, 0); /* value */ | |
2100 | } else { | |
2101 | intel_ring_emit(ring, 0); | |
2102 | intel_ring_emit(ring, MI_NOOP); | |
2103 | } | |
b72f3acb | 2104 | intel_ring_advance(ring); |
fd3da6c9 | 2105 | |
9688ecad | 2106 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
2107 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
2108 | ||
b72f3acb | 2109 | return 0; |
8d19215b ZN |
2110 | } |
2111 | ||
5c1143bb XH |
2112 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2113 | { | |
4640c4ff | 2114 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2115 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2116 | struct drm_i915_gem_object *obj; |
2117 | int ret; | |
5c1143bb | 2118 | |
59465b5f DV |
2119 | ring->name = "render ring"; |
2120 | ring->id = RCS; | |
2121 | ring->mmio_base = RENDER_RING_BASE; | |
2122 | ||
707d9cf9 | 2123 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2124 | if (i915_semaphore_is_enabled(dev)) { |
2125 | obj = i915_gem_alloc_object(dev, 4096); | |
2126 | if (obj == NULL) { | |
2127 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2128 | i915.semaphores = 0; | |
2129 | } else { | |
2130 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2131 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2132 | if (ret != 0) { | |
2133 | drm_gem_object_unreference(&obj->base); | |
2134 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2135 | i915.semaphores = 0; | |
2136 | } else | |
2137 | dev_priv->semaphore_obj = obj; | |
2138 | } | |
2139 | } | |
707d9cf9 BW |
2140 | ring->add_request = gen6_add_request; |
2141 | ring->flush = gen8_render_ring_flush; | |
2142 | ring->irq_get = gen8_ring_get_irq; | |
2143 | ring->irq_put = gen8_ring_put_irq; | |
2144 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2145 | ring->get_seqno = gen6_ring_get_seqno; | |
2146 | ring->set_seqno = ring_set_seqno; | |
2147 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2148 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2149 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2150 | ring->semaphore.signal = gen8_rcs_signal; |
2151 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2152 | } |
2153 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2154 | ring->add_request = gen6_add_request; |
4772eaeb | 2155 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2156 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2157 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2158 | ring->irq_get = gen6_ring_get_irq; |
2159 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2160 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2161 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2162 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2163 | if (i915_semaphore_is_enabled(dev)) { |
2164 | ring->semaphore.sync_to = gen6_ring_sync; | |
2165 | ring->semaphore.signal = gen6_signal; | |
2166 | /* | |
2167 | * The current semaphore is only applied on pre-gen8 | |
2168 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2169 | * platform. So the semaphore between RCS and VCS2 is | |
2170 | * initialized as INVALID. Gen8 will initialize the | |
2171 | * sema between VCS2 and RCS later. | |
2172 | */ | |
2173 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2174 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2175 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2176 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2177 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2178 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2179 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2180 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2181 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2182 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2183 | } | |
c6df541c CW |
2184 | } else if (IS_GEN5(dev)) { |
2185 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2186 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2187 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2188 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2189 | ring->irq_get = gen5_ring_get_irq; |
2190 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2191 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2192 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2193 | } else { |
8620a3a9 | 2194 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2195 | if (INTEL_INFO(dev)->gen < 4) |
2196 | ring->flush = gen2_render_ring_flush; | |
2197 | else | |
2198 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2199 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2200 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2201 | if (IS_GEN2(dev)) { |
2202 | ring->irq_get = i8xx_ring_get_irq; | |
2203 | ring->irq_put = i8xx_ring_put_irq; | |
2204 | } else { | |
2205 | ring->irq_get = i9xx_ring_get_irq; | |
2206 | ring->irq_put = i9xx_ring_put_irq; | |
2207 | } | |
e3670319 | 2208 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2209 | } |
59465b5f | 2210 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2211 | |
d7d4eedd CW |
2212 | if (IS_HASWELL(dev)) |
2213 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2214 | else if (IS_GEN8(dev)) |
2215 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2216 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2217 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2218 | else if (INTEL_INFO(dev)->gen >= 4) | |
2219 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2220 | else if (IS_I830(dev) || IS_845G(dev)) | |
2221 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2222 | else | |
2223 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2224 | ring->init = init_render_ring; |
2225 | ring->cleanup = render_ring_cleanup; | |
2226 | ||
b45305fc DV |
2227 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2228 | if (HAS_BROKEN_CS_TLB(dev)) { | |
b45305fc DV |
2229 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
2230 | if (obj == NULL) { | |
2231 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2232 | return -ENOMEM; | |
2233 | } | |
2234 | ||
be1fa129 | 2235 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2236 | if (ret != 0) { |
2237 | drm_gem_object_unreference(&obj->base); | |
2238 | DRM_ERROR("Failed to ping batch bo\n"); | |
2239 | return ret; | |
2240 | } | |
2241 | ||
0d1aacac CW |
2242 | ring->scratch.obj = obj; |
2243 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2244 | } |
2245 | ||
1ec14ad3 | 2246 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
2247 | } |
2248 | ||
e8616b6c CW |
2249 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2250 | { | |
4640c4ff | 2251 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2252 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
8ee14975 | 2253 | struct intel_ringbuffer *ringbuf = ring->buffer; |
6b8294a4 | 2254 | int ret; |
e8616b6c | 2255 | |
8ee14975 OM |
2256 | if (ringbuf == NULL) { |
2257 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
2258 | if (!ringbuf) | |
2259 | return -ENOMEM; | |
2260 | ring->buffer = ringbuf; | |
2261 | } | |
2262 | ||
59465b5f DV |
2263 | ring->name = "render ring"; |
2264 | ring->id = RCS; | |
2265 | ring->mmio_base = RENDER_RING_BASE; | |
2266 | ||
e8616b6c | 2267 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a | 2268 | /* non-kms not supported on gen6+ */ |
8ee14975 OM |
2269 | ret = -ENODEV; |
2270 | goto err_ringbuf; | |
e8616b6c | 2271 | } |
28f0cbf7 DV |
2272 | |
2273 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2274 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2275 | * the special gen5 functions. */ | |
2276 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2277 | if (INTEL_INFO(dev)->gen < 4) |
2278 | ring->flush = gen2_render_ring_flush; | |
2279 | else | |
2280 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2281 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2282 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2283 | if (IS_GEN2(dev)) { |
2284 | ring->irq_get = i8xx_ring_get_irq; | |
2285 | ring->irq_put = i8xx_ring_put_irq; | |
2286 | } else { | |
2287 | ring->irq_get = i9xx_ring_get_irq; | |
2288 | ring->irq_put = i9xx_ring_put_irq; | |
2289 | } | |
28f0cbf7 | 2290 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2291 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2292 | if (INTEL_INFO(dev)->gen >= 4) |
2293 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2294 | else if (IS_I830(dev) || IS_845G(dev)) | |
2295 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2296 | else | |
2297 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2298 | ring->init = init_render_ring; |
2299 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2300 | |
2301 | ring->dev = dev; | |
2302 | INIT_LIST_HEAD(&ring->active_list); | |
2303 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c | 2304 | |
93b0a4e0 OM |
2305 | ringbuf->size = size; |
2306 | ringbuf->effective_size = ringbuf->size; | |
17f10fdc | 2307 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
93b0a4e0 | 2308 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
e8616b6c | 2309 | |
93b0a4e0 OM |
2310 | ringbuf->virtual_start = ioremap_wc(start, size); |
2311 | if (ringbuf->virtual_start == NULL) { | |
e8616b6c CW |
2312 | DRM_ERROR("can not ioremap virtual address for" |
2313 | " ring buffer\n"); | |
8ee14975 OM |
2314 | ret = -ENOMEM; |
2315 | goto err_ringbuf; | |
e8616b6c CW |
2316 | } |
2317 | ||
6b8294a4 | 2318 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2319 | ret = init_phys_status_page(ring); |
6b8294a4 | 2320 | if (ret) |
8ee14975 | 2321 | goto err_vstart; |
6b8294a4 CW |
2322 | } |
2323 | ||
e8616b6c | 2324 | return 0; |
8ee14975 OM |
2325 | |
2326 | err_vstart: | |
93b0a4e0 | 2327 | iounmap(ringbuf->virtual_start); |
8ee14975 OM |
2328 | err_ringbuf: |
2329 | kfree(ringbuf); | |
2330 | ring->buffer = NULL; | |
2331 | return ret; | |
e8616b6c CW |
2332 | } |
2333 | ||
5c1143bb XH |
2334 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2335 | { | |
4640c4ff | 2336 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2337 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2338 | |
58fa3835 DV |
2339 | ring->name = "bsd ring"; |
2340 | ring->id = VCS; | |
2341 | ||
0fd2c201 | 2342 | ring->write_tail = ring_write_tail; |
780f18c8 | 2343 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2344 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2345 | /* gen6 bsd needs a special wa for tail updates */ |
2346 | if (IS_GEN6(dev)) | |
2347 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2348 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2349 | ring->add_request = gen6_add_request; |
2350 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2351 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2352 | if (INTEL_INFO(dev)->gen >= 8) { |
2353 | ring->irq_enable_mask = | |
2354 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2355 | ring->irq_get = gen8_ring_get_irq; | |
2356 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2357 | ring->dispatch_execbuffer = |
2358 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2359 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2360 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2361 | ring->semaphore.signal = gen8_xcs_signal; |
2362 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2363 | } |
abd58f01 BW |
2364 | } else { |
2365 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2366 | ring->irq_get = gen6_ring_get_irq; | |
2367 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2368 | ring->dispatch_execbuffer = |
2369 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2370 | if (i915_semaphore_is_enabled(dev)) { |
2371 | ring->semaphore.sync_to = gen6_ring_sync; | |
2372 | ring->semaphore.signal = gen6_signal; | |
2373 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2374 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2375 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2376 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2377 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2378 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2379 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2380 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2381 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2382 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2383 | } | |
abd58f01 | 2384 | } |
58fa3835 DV |
2385 | } else { |
2386 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2387 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2388 | ring->add_request = i9xx_add_request; |
58fa3835 | 2389 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2390 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2391 | if (IS_GEN5(dev)) { |
cc609d5d | 2392 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2393 | ring->irq_get = gen5_ring_get_irq; |
2394 | ring->irq_put = gen5_ring_put_irq; | |
2395 | } else { | |
e3670319 | 2396 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2397 | ring->irq_get = i9xx_ring_get_irq; |
2398 | ring->irq_put = i9xx_ring_put_irq; | |
2399 | } | |
fb3256da | 2400 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2401 | } |
2402 | ring->init = init_ring_common; | |
2403 | ||
1ec14ad3 | 2404 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2405 | } |
549f7365 | 2406 | |
845f74a7 ZY |
2407 | /** |
2408 | * Initialize the second BSD ring for Broadwell GT3. | |
2409 | * It is noted that this only exists on Broadwell GT3. | |
2410 | */ | |
2411 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2412 | { | |
2413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2414 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2415 | |
2416 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2417 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2418 | return -EINVAL; | |
2419 | } | |
2420 | ||
f7b64236 | 2421 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2422 | ring->id = VCS2; |
2423 | ||
2424 | ring->write_tail = ring_write_tail; | |
2425 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2426 | ring->flush = gen6_bsd_ring_flush; | |
2427 | ring->add_request = gen6_add_request; | |
2428 | ring->get_seqno = gen6_ring_get_seqno; | |
2429 | ring->set_seqno = ring_set_seqno; | |
2430 | ring->irq_enable_mask = | |
2431 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2432 | ring->irq_get = gen8_ring_get_irq; | |
2433 | ring->irq_put = gen8_ring_put_irq; | |
2434 | ring->dispatch_execbuffer = | |
2435 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2436 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2437 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2438 | ring->semaphore.signal = gen8_xcs_signal; |
2439 | GEN8_RING_SEMAPHORE_INIT; | |
2440 | } | |
845f74a7 ZY |
2441 | ring->init = init_ring_common; |
2442 | ||
2443 | return intel_init_ring_buffer(dev, ring); | |
2444 | } | |
2445 | ||
549f7365 CW |
2446 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2447 | { | |
4640c4ff | 2448 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2449 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2450 | |
3535d9dd DV |
2451 | ring->name = "blitter ring"; |
2452 | ring->id = BCS; | |
2453 | ||
2454 | ring->mmio_base = BLT_RING_BASE; | |
2455 | ring->write_tail = ring_write_tail; | |
ea251324 | 2456 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2457 | ring->add_request = gen6_add_request; |
2458 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2459 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2460 | if (INTEL_INFO(dev)->gen >= 8) { |
2461 | ring->irq_enable_mask = | |
2462 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2463 | ring->irq_get = gen8_ring_get_irq; | |
2464 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2465 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2466 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2467 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2468 | ring->semaphore.signal = gen8_xcs_signal; |
2469 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2470 | } |
abd58f01 BW |
2471 | } else { |
2472 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2473 | ring->irq_get = gen6_ring_get_irq; | |
2474 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2475 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2476 | if (i915_semaphore_is_enabled(dev)) { |
2477 | ring->semaphore.signal = gen6_signal; | |
2478 | ring->semaphore.sync_to = gen6_ring_sync; | |
2479 | /* | |
2480 | * The current semaphore is only applied on pre-gen8 | |
2481 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2482 | * platform. So the semaphore between BCS and VCS2 is | |
2483 | * initialized as INVALID. Gen8 will initialize the | |
2484 | * sema between BCS and VCS2 later. | |
2485 | */ | |
2486 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2487 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2488 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2489 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2490 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2491 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2492 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2493 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2494 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2495 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2496 | } | |
abd58f01 | 2497 | } |
3535d9dd | 2498 | ring->init = init_ring_common; |
549f7365 | 2499 | |
1ec14ad3 | 2500 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2501 | } |
a7b9761d | 2502 | |
9a8a2213 BW |
2503 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2504 | { | |
4640c4ff | 2505 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2506 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2507 | |
2508 | ring->name = "video enhancement ring"; | |
2509 | ring->id = VECS; | |
2510 | ||
2511 | ring->mmio_base = VEBOX_RING_BASE; | |
2512 | ring->write_tail = ring_write_tail; | |
2513 | ring->flush = gen6_ring_flush; | |
2514 | ring->add_request = gen6_add_request; | |
2515 | ring->get_seqno = gen6_ring_get_seqno; | |
2516 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2517 | |
2518 | if (INTEL_INFO(dev)->gen >= 8) { | |
2519 | ring->irq_enable_mask = | |
40c499f9 | 2520 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2521 | ring->irq_get = gen8_ring_get_irq; |
2522 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2523 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2524 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2525 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2526 | ring->semaphore.signal = gen8_xcs_signal; |
2527 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2528 | } |
abd58f01 BW |
2529 | } else { |
2530 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2531 | ring->irq_get = hsw_vebox_get_irq; | |
2532 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2533 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2534 | if (i915_semaphore_is_enabled(dev)) { |
2535 | ring->semaphore.sync_to = gen6_ring_sync; | |
2536 | ring->semaphore.signal = gen6_signal; | |
2537 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2538 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2539 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2540 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2541 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2542 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2543 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2544 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2545 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2546 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2547 | } | |
abd58f01 | 2548 | } |
9a8a2213 BW |
2549 | ring->init = init_ring_common; |
2550 | ||
2551 | return intel_init_ring_buffer(dev, ring); | |
2552 | } | |
2553 | ||
a7b9761d | 2554 | int |
a4872ba6 | 2555 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2556 | { |
2557 | int ret; | |
2558 | ||
2559 | if (!ring->gpu_caches_dirty) | |
2560 | return 0; | |
2561 | ||
2562 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2563 | if (ret) | |
2564 | return ret; | |
2565 | ||
2566 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2567 | ||
2568 | ring->gpu_caches_dirty = false; | |
2569 | return 0; | |
2570 | } | |
2571 | ||
2572 | int | |
a4872ba6 | 2573 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2574 | { |
2575 | uint32_t flush_domains; | |
2576 | int ret; | |
2577 | ||
2578 | flush_domains = 0; | |
2579 | if (ring->gpu_caches_dirty) | |
2580 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2581 | ||
2582 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2583 | if (ret) | |
2584 | return ret; | |
2585 | ||
2586 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2587 | ||
2588 | ring->gpu_caches_dirty = false; | |
2589 | return 0; | |
2590 | } | |
e3efda49 CW |
2591 | |
2592 | void | |
a4872ba6 | 2593 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2594 | { |
2595 | int ret; | |
2596 | ||
2597 | if (!intel_ring_initialized(ring)) | |
2598 | return; | |
2599 | ||
2600 | ret = intel_ring_idle(ring); | |
2601 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2602 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2603 | ring->name, ret); | |
2604 | ||
2605 | stop_ring(ring); | |
2606 | } |