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drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
6258fbe2 84static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a84c3ae1 94gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
a84c3ae1 98 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
31b14c9f 103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
5fb9de1a 109 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118}
119
120static int
a84c3ae1 121gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 122 u32 invalidate_domains,
123 u32 flush_domains)
62fdfeaf 124{
a84c3ae1 125 struct intel_engine_cs *ring = req->ring;
78501eac 126 struct drm_device *dev = ring->dev;
6f392d54 127 u32 cmd;
b72f3acb 128 int ret;
6f392d54 129
36d527de
CW		 130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 160 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
62fdfeaf 163
36d527de
CW		 164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
70eac33e 167
5fb9de1a 168 ret = intel_ring_begin(req, 2);
36d527de
CW		 169 if (ret)
170 return ret;
b72f3acb 171
36d527de
CW		 172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
b72f3acb
CW		 175
176 return 0;
8187a2b7
ZN		 177}
178
8d315287
JB		 179/**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216static int
f2cf1fcc 217intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 218{
f2cf1fcc 219 struct intel_engine_cs *ring = req->ring;
18393f63 220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 221 int ret;
222
5fb9de1a 223 ret = intel_ring_begin(req, 6);
8d315287
JB		 224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
5fb9de1a 236 ret = intel_ring_begin(req, 6);
8d315287
JB		 237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
251static int
a84c3ae1
JH		 252gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
8d315287 254{
a84c3ae1 255 struct intel_engine_cs *ring = req->ring;
8d315287 256 u32 flags = 0;
18393f63 257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 258 int ret;
259
b3111509 260 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 261 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 262 if (ret)
263 return ret;
264
8d315287
JB		 265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
7d54a904
CW		 269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
97f209bc 276 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
3ac78313 288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 289 }
8d315287 290
5fb9de1a 291 ret = intel_ring_begin(req, 4);
8d315287
JB		 292 if (ret)
293 return ret;
294
6c6cf5aa 295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 298 intel_ring_emit(ring, 0);
8d315287
JB		 299 intel_ring_advance(ring);
300
301 return 0;
302}
303
f3987631 304static int
f2cf1fcc 305gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 306{
f2cf1fcc 307 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 308 int ret;
309
5fb9de1a 310 ret = intel_ring_begin(req, 4);
f3987631
PZ		 311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322}
323
4772eaeb 324static int
a84c3ae1 325gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 326 u32 invalidate_domains, u32 flush_domains)
327{
a84c3ae1 328 struct intel_engine_cs *ring = req->ring;
4772eaeb 329 u32 flags = 0;
18393f63 330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 331 int ret;
332
f3987631
PZ		 333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
4772eaeb
PZ		 343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 364
add284a3
CW		 365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
f3987631
PZ		 367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
f2cf1fcc 370 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 371 }
372
5fb9de1a 373 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
b9e1faa7 379 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384}
385
884ceace 386static int
f2cf1fcc 387gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 388 u32 flags, u32 scratch_addr)
389{
f2cf1fcc 390 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 391 int ret;
392
5fb9de1a 393 ret = intel_ring_begin(req, 6);
884ceace
KG		 394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406}
407
a5f3d68e 408static int
a84c3ae1 409gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 410 u32 invalidate_domains, u32 flush_domains)
411{
412 u32 flags = 0;
f2cf1fcc 413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 414 int ret;
a5f3d68e
BW		 415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 433 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
a5f3d68e
BW		 439 }
440
f2cf1fcc 441 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 442}
443
a4872ba6 444static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 445 u32 value)
d46eefa2 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 448 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 449}
450
a4872ba6 451u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 452{
4640c4ff 453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 454 u64 acthd;
8187a2b7 455
50877445
CW		 456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
8187a2b7
ZN		 465}
466
a4872ba6 467static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 468{
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476}
477
af75f269
DL		 478static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479{
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538}
539
a4872ba6 540static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 541{
9991ae78 542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 543
9991ae78
CW		 544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
9991ae78
CW		 554 }
555 }
b7884eb4 556
7f2ab699 557 I915_WRITE_CTL(ring, 0);
570ef608 558 I915_WRITE_HEAD(ring, 0);
78501eac 559 ring->write_tail(ring, 0);
8187a2b7 560
9991ae78
CW		 561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
a51435a3 565
9991ae78
CW		 566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567}
8187a2b7 568
a4872ba6 569static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 570{
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 575 int ret = 0;
576
59bad947 577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
8187a2b7 588
9991ae78 589 if (!stop_ring(ring)) {
6fd0d56e
CW		 590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
9991ae78
CW		 597 ret = -EIO;
598 goto out;
6fd0d56e 599 }
8187a2b7
ZN		 600 }
601
9991ae78
CW		 602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
ece4a17d
JK		 607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
0d8957c8
DV		 610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
f343c5f6 614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
7f2ab699 623 I915_WRITE_CTL(ring,
93b0a4e0 624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 625 | RING_VALID);
8187a2b7 626
8187a2b7 627 /* If the head is still not zero, the ring is dead */
f01db988 628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 631 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 637 ret = -EIO;
638 goto out;
8187a2b7
ZN		 639 }
640
ebd0fd4b 641 ringbuf->last_retired_head = -1;
5c6c6003
CW		 642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 644 intel_ring_update_space(ringbuf);
1ec14ad3 645
50f018df
CW		 646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
b7884eb4 648out:
59bad947 649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 650
651 return ret;
8187a2b7
ZN		 652}
653
9b1136d5
OM		 654void
655intel_fini_pipe_control(struct intel_engine_cs *ring)
656{
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669}
670
671int
672intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 673{
c6df541c
CW		 674 int ret;
675
bfc882b4 676 WARN_ON(ring->scratch.obj);
c6df541c 677
0d1aacac
CW		 678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
c6df541c
CW		 680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
e4ffd173 684
a9cc726c
DV		 685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
c6df541c 688
1ec9e26d 689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 690 if (ret)
691 goto err_unref;
692
0d1aacac
CW		 693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
56b085a0 696 ret = -ENOMEM;
c6df541c 697 goto err_unpin;
56b085a0 698 }
c6df541c 699
2b1086cc 700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 701 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 702 return 0;
703
704err_unpin:
d7f46fc4 705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 706err_unref:
0d1aacac 707 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 708err:
c6df541c
CW		 709 return ret;
710}
711
e2be4faf 712static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 713{
7225342a 714 int ret, i;
e2be4faf 715 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 718 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 719
e6c1abb7 720 if (WARN_ON_ONCE(w->count == 0))
7225342a 721 return 0;
888b5995 722
7225342a 723 ring->gpu_caches_dirty = true;
4866d729 724 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 725 if (ret)
726 return ret;
888b5995 727
5fb9de1a 728 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 729 if (ret)
730 return ret;
731
22a916aa 732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 733 for (i = 0; i < w->count; i++) {
7225342a
MK		 734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
22a916aa 737 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
4866d729 742 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 743 if (ret)
744 return ret;
888b5995 745
7225342a 746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 747
7225342a 748 return 0;
86d7f238
AS		 749}
750
8753181e 751static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 752{
753 int ret;
754
e2be4faf 755 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 756 if (ret != 0)
757 return ret;
758
be01363f 759 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764}
765
7225342a 766static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 767 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 768{
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
86d7f238
AS		 781}
782
ca5a0fbd 783#define WA_REG(addr, mask, val) do { \
cf4b0de6 784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 785 if (r) \
786 return r; \
ca5a0fbd 787 } while (0)
7225342a
MK		 788
789#define WA_SET_BIT_MASKED(addr, mask) \
26459343 790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 791
792#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 794
98533251 795#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 797
cf4b0de6
DL		 798#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 800
cf4b0de6 801#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 802
e9a64ada
AS		 803static int gen8_init_workarounds(struct intel_engine_cs *ring)
804{
68c6198b
AS		 805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807
808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 809
717d84d6
AS		 810 /* WaDisableAsyncFlipPerfMode:bdw,chv */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
e9a64ada
AS		 813 return 0;
814}
815
00e1e623 816static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 817{
e9a64ada 818 int ret;
888b5995
AS		 819 struct drm_device *dev = ring->dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 821
e9a64ada
AS		 822 ret = gen8_init_workarounds(ring);
823 if (ret)
824 return ret;
825
86d7f238 826 /* WaDisablePartialInstShootdown:bdw */
101b376d 827 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 828 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
829 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
830 STALL_DOP_GATING_DISABLE);
86d7f238 831
101b376d 832 /* WaDisableDopClockGating:bdw */
7225342a
MK		 833 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
834 DOP_CLOCK_GATING_DISABLE);
86d7f238 835
7225342a
MK		 836 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
837 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 838
839 /* Use Force Non-Coherent whenever executing a 3D context. This is a
840 * workaround for for a possible hang in the unlikely event a TLB
841 * invalidation occurs during a PSD flush.
842 */
7225342a 843 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 844 /* WaForceEnableNonCoherent:bdw */
7225342a 845 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 846 /* WaForceContextSaveRestoreNonCoherent:bdw */
847 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
848 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 849 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 850 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 851 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 852
2701fc43
KG		 853 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
854 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
855 * polygons in the same 8x4 pixel/sample area to be processed without
856 * stalling waiting for the earlier ones to write to Hierarchical Z
857 * buffer."
858 *
859 * This optimization is off by default for Broadwell; turn it on.
860 */
861 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
862
86d7f238 863 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 864 WA_SET_BIT_MASKED(CACHE_MODE_1,
865 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 866
867 /*
868 * BSpec recommends 8x4 when MSAA is used,
869 * however in practice 16x4 seems fastest.
870 *
871 * Note that PS/WM thread counts depend on the WIZ hashing
872 * disable bit, which we don't touch here, but it's good
873 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
874 */
98533251
DL		 875 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
876 GEN6_WIZ_HASHING_MASK,
877 GEN6_WIZ_HASHING_16x4);
888b5995 878
86d7f238
AS		 879 return 0;
880}
881
00e1e623
VS		 882static int chv_init_workarounds(struct intel_engine_cs *ring)
883{
e9a64ada 884 int ret;
00e1e623
VS		 885 struct drm_device *dev = ring->dev;
886 struct drm_i915_private *dev_priv = dev->dev_private;
887
e9a64ada
AS		 888 ret = gen8_init_workarounds(ring);
889 if (ret)
890 return ret;
891
00e1e623 892 /* WaDisablePartialInstShootdown:chv */
00e1e623 893 /* WaDisableThreadStallDopClockGating:chv */
7225342a 894 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 895 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
896 STALL_DOP_GATING_DISABLE);
00e1e623 897
95289009
AS		 898 /* Use Force Non-Coherent whenever executing a 3D context. This is a
899 * workaround for a possible hang in the unlikely event a TLB
900 * invalidation occurs during a PSD flush.
901 */
902 /* WaForceEnableNonCoherent:chv */
903 /* WaHdcDisableFetchWhenMasked:chv */
904 WA_SET_BIT_MASKED(HDC_CHICKEN0,
905 HDC_FORCE_NON_COHERENT |
906 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
907
973a5b06
KG		 908 /* According to the CACHE_MODE_0 default value documentation, some
909 * CHV platforms disable this optimization by default. Turn it on.
910 */
911 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
912
14bc16e3
VS		 913 /* Wa4x4STCOptimizationDisable:chv */
914 WA_SET_BIT_MASKED(CACHE_MODE_1,
915 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
916
d60de81d
KG		 917 /* Improve HiZ throughput on CHV. */
918 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
919
e7fc2436
VS		 920 /*
921 * BSpec recommends 8x4 when MSAA is used,
922 * however in practice 16x4 seems fastest.
923 *
924 * Note that PS/WM thread counts depend on the WIZ hashing
925 * disable bit, which we don't touch here, but it's good
926 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
927 */
928 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
929 GEN6_WIZ_HASHING_MASK,
930 GEN6_WIZ_HASHING_16x4);
931
7225342a
MK		 932 return 0;
933}
934
3b106531
HN		 935static int gen9_init_workarounds(struct intel_engine_cs *ring)
936{
ab0dfafe
HN		 937 struct drm_device *dev = ring->dev;
938 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 939 uint32_t tmp;
ab0dfafe 940
b0e6f6d4 941 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 942 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
943 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
944
a119a6e6 945 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 946 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
947 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
948
d2a31dbd
NH		 949 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
950 INTEL_REVID(dev) == SKL_REVID_B0)) ||
951 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
952 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 953 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
954 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 955 }
956
a13d215f
NH		 957 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
958 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
959 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 960 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
961 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 962 /*
963 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
964 * but we do that in per ctx batchbuffer as there is an issue
965 * with this register not getting restored on ctx restore
966 */
183c6dac
DL		 967 }
968
27a1b688
NH		 969 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
970 IS_BROXTON(dev)) {
971 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 972 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
973 GEN9_ENABLE_YV12_BUGFIX);
974 }
975
5068368c 976 /* Wa4x4STCOptimizationDisable:skl,bxt */
27160c96 977 /* WaDisablePartialResolveInVc:skl,bxt */
60294683
AS		 978 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
979 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 980
16be17af 981 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 982 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
983 GEN9_CCS_TLB_PREFETCH_ENABLE);
984
5a2ae95e
ID		 985 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
986 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
987 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 988 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
989 PIXEL_MASK_CAMMING_DISABLE);
990
8ea6f892
ID		 991 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
992 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
993 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
994 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
995 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
996 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
997
8c761609
AS		 998 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
999 if (IS_SKYLAKE(dev) ||
1000 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
1001 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1002 GEN8_SAMPLER_POWER_BYPASS_DIS);
1003 }
1004
6b6d5626
RB		 1005 /* WaDisableSTUnitPowerOptimization:skl,bxt */
1006 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1007
3b106531
HN		 1008 return 0;
1009}
1010
b7668791
DL		 1011static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1012{
1013 struct drm_device *dev = ring->dev;
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 u8 vals[3] = { 0, 0, 0 };
1016 unsigned int i;
1017
1018 for (i = 0; i < 3; i++) {
1019 u8 ss;
1020
1021 /*
1022 * Only consider slices where one, and only one, subslice has 7
1023 * EUs
1024 */
1025 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1026 continue;
1027
1028 /*
1029 * subslice_7eu[i] != 0 (because of the check above) and
1030 * ss_max == 4 (maximum number of subslices possible per slice)
1031 *
1032 * -> 0 <= ss <= 3;
1033 */
1034 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1035 vals[i] = 3 - ss;
1036 }
1037
1038 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1039 return 0;
1040
1041 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1042 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1043 GEN9_IZ_HASHING_MASK(2) |
1044 GEN9_IZ_HASHING_MASK(1) |
1045 GEN9_IZ_HASHING_MASK(0),
1046 GEN9_IZ_HASHING(2, vals[2]) |
1047 GEN9_IZ_HASHING(1, vals[1]) |
1048 GEN9_IZ_HASHING(0, vals[0]));
1049
1050 return 0;
1051}
1052
1053
8d205494
DL		 1054static int skl_init_workarounds(struct intel_engine_cs *ring)
1055{
aa0011a8 1056 int ret;
d0bbbc4f
DL		 1057 struct drm_device *dev = ring->dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059
aa0011a8
AS		 1060 ret = gen9_init_workarounds(ring);
1061 if (ret)
1062 return ret;
8d205494 1063
d0bbbc4f
DL		 1064 /* WaDisablePowerCompilerClockGating:skl */
1065 if (INTEL_REVID(dev) == SKL_REVID_B0)
1066 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1067 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1068
b62adbd1
NH		 1069 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1070 /*
1071 *Use Force Non-Coherent whenever executing a 3D context. This
1072 * is a workaround for a possible hang in the unlikely event
1073 * a TLB invalidation occurs during a PSD flush.
1074 */
1075 /* WaForceEnableNonCoherent:skl */
1076 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1077 HDC_FORCE_NON_COHERENT);
1078 }
1079
5b6fd12a
VS		 1080 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1081 INTEL_REVID(dev) == SKL_REVID_D0)
1082 /* WaBarrierPerformanceFixDisable:skl */
1083 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1084 HDC_FENCE_DEST_SLM_DISABLE |
1085 HDC_BARRIER_PERFORMANCE_DISABLE);
1086
9bd9dfb4
MK		 1087 /* WaDisableSbeCacheDispatchPortSharing:skl */
1088 if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1089 WA_SET_BIT_MASKED(
1090 GEN7_HALF_SLICE_CHICKEN1,
1091 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1092 }
1093
b7668791 1094 return skl_tune_iz_hashing(ring);
7225342a
MK		 1095}
1096
cae0437f
NH		 1097static int bxt_init_workarounds(struct intel_engine_cs *ring)
1098{
aa0011a8 1099 int ret;
dfb601e6
NH		 1100 struct drm_device *dev = ring->dev;
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102
aa0011a8
AS		 1103 ret = gen9_init_workarounds(ring);
1104 if (ret)
1105 return ret;
cae0437f 1106
dfb601e6
NH		 1107 /* WaDisableThreadStallDopClockGating:bxt */
1108 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1109 STALL_DOP_GATING_DISABLE);
1110
983b4b9d
NH		 1111 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1112 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1113 WA_SET_BIT_MASKED(
1114 GEN7_HALF_SLICE_CHICKEN1,
1115 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1116 }
1117
cae0437f
NH		 1118 return 0;
1119}
1120
771b9a53 1121int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1122{
1123 struct drm_device *dev = ring->dev;
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126 WARN_ON(ring->id != RCS);
1127
1128 dev_priv->workarounds.count = 0;
1129
1130 if (IS_BROADWELL(dev))
1131 return bdw_init_workarounds(ring);
1132
1133 if (IS_CHERRYVIEW(dev))
1134 return chv_init_workarounds(ring);
00e1e623 1135
8d205494
DL		 1136 if (IS_SKYLAKE(dev))
1137 return skl_init_workarounds(ring);
cae0437f
NH		 1138
1139 if (IS_BROXTON(dev))
1140 return bxt_init_workarounds(ring);
3b106531 1141
00e1e623
VS		 1142 return 0;
1143}
1144
a4872ba6 1145static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1146{
78501eac 1147 struct drm_device *dev = ring->dev;
1ec14ad3 1148 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1149 int ret = init_ring_common(ring);
9c33baa6
KZ		 1150 if (ret)
1151 return ret;
a69ffdbf 1152
61a563a2
AG		 1153 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1154 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1155 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1156
1157 /* We need to disable the AsyncFlip performance optimisations in order
1158 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1159 * programmed to '1' on all products.
8693a824 1160 *
2441f877 1161 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1162 */
2441f877 1163 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1164 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1165
f05bb0c7 1166 /* Required for the hardware to program scanline values for waiting */
01fa0302 1167 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1168 if (INTEL_INFO(dev)->gen == 6)
1169 I915_WRITE(GFX_MODE,
aa83e30d 1170 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1171
01fa0302 1172 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1173 if (IS_GEN7(dev))
1174 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1175 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1176 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1177
5e13a0c5 1178 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1179 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1180 * "If this bit is set, STCunit will have LRA as replacement
1181 * policy. [...] This bit must be reset. LRA replacement
1182 * policy is not supported."
1183 */
1184 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1185 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1186 }
1187
9cc83020 1188 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1189 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1190
040d2baa 1191 if (HAS_L3_DPF(dev))
35a85ac6 1192 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1193
7225342a 1194 return init_workarounds_ring(ring);
8187a2b7
ZN		 1195}
1196
a4872ba6 1197static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1198{
b45305fc 1199 struct drm_device *dev = ring->dev;
3e78998a
BW		 1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201
1202 if (dev_priv->semaphore_obj) {
1203 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1204 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1205 dev_priv->semaphore_obj = NULL;
1206 }
b45305fc 1207
9b1136d5 1208 intel_fini_pipe_control(ring);
c6df541c
CW		 1209}
1210
f7169687 1211static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1212 unsigned int num_dwords)
1213{
1214#define MBOX_UPDATE_DWORDS 8
f7169687 1215 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1216 struct drm_device *dev = signaller->dev;
1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 struct intel_engine_cs *waiter;
1219 int i, ret, num_rings;
1220
1221 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1222 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1223#undef MBOX_UPDATE_DWORDS
1224
5fb9de1a 1225 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1226 if (ret)
1227 return ret;
1228
1229 for_each_ring(waiter, dev_priv, i) {
6259cead 1230 u32 seqno;
3e78998a
BW		 1231 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1232 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1233 continue;
1234
f7169687 1235 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1236 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1237 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1238 PIPE_CONTROL_QW_WRITE |
1239 PIPE_CONTROL_FLUSH_ENABLE);
1240 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1241 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1242 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1243 intel_ring_emit(signaller, 0);
1244 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1245 MI_SEMAPHORE_TARGET(waiter->id));
1246 intel_ring_emit(signaller, 0);
1247 }
1248
1249 return 0;
1250}
1251
f7169687 1252static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1253 unsigned int num_dwords)
1254{
1255#define MBOX_UPDATE_DWORDS 6
f7169687 1256 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1257 struct drm_device *dev = signaller->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 struct intel_engine_cs *waiter;
1260 int i, ret, num_rings;
1261
1262 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1263 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1264#undef MBOX_UPDATE_DWORDS
1265
5fb9de1a 1266 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1267 if (ret)
1268 return ret;
1269
1270 for_each_ring(waiter, dev_priv, i) {
6259cead 1271 u32 seqno;
3e78998a
BW		 1272 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1273 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1274 continue;
1275
f7169687 1276 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1277 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1278 MI_FLUSH_DW_OP_STOREDW);
1279 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1280 MI_FLUSH_DW_USE_GTT);
1281 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1282 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1283 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1284 MI_SEMAPHORE_TARGET(waiter->id));
1285 intel_ring_emit(signaller, 0);
1286 }
1287
1288 return 0;
1289}
1290
f7169687 1291static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1292 unsigned int num_dwords)
1ec14ad3 1293{
f7169687 1294 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1295 struct drm_device *dev = signaller->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1297 struct intel_engine_cs *useless;
a1444b79 1298 int i, ret, num_rings;
78325f2d 1299
a1444b79
BW		 1300#define MBOX_UPDATE_DWORDS 3
1301 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1302 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1303#undef MBOX_UPDATE_DWORDS
024a43e1 1304
5fb9de1a 1305 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1306 if (ret)
1307 return ret;
024a43e1 1308
78325f2d
BW		 1309 for_each_ring(useless, dev_priv, i) {
1310 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1311 if (mbox_reg != GEN6_NOSYNC) {
f7169687 1312 u32 seqno = i915_gem_request_get_seqno(signaller_req);
78325f2d
BW		 1313 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1314 intel_ring_emit(signaller, mbox_reg);
6259cead 1315 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1316 }
1317 }
024a43e1 1318
a1444b79
BW		 1319 /* If num_dwords was rounded, make sure the tail pointer is correct */
1320 if (num_rings % 2 == 0)
1321 intel_ring_emit(signaller, MI_NOOP);
1322
024a43e1 1323 return 0;
1ec14ad3
CW		 1324}
1325
c8c99b0f
BW		 1326/**
1327 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1328 *
1329 * @request - request to write to the ring
c8c99b0f
BW		 1330 *
1331 * Update the mailbox registers in the *other* rings with the current seqno.
1332 * This acts like a signal in the canonical semaphore.
1333 */
1ec14ad3 1334static int
ee044a88 1335gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1336{
ee044a88 1337 struct intel_engine_cs *ring = req->ring;
024a43e1 1338 int ret;
52ed2325 1339
707d9cf9 1340 if (ring->semaphore.signal)
f7169687 1341 ret = ring->semaphore.signal(req, 4);
707d9cf9 1342 else
5fb9de1a 1343 ret = intel_ring_begin(req, 4);
707d9cf9 1344
1ec14ad3
CW		 1345 if (ret)
1346 return ret;
1347
1ec14ad3
CW		 1348 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1349 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1350 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1351 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1352 __intel_ring_advance(ring);
1ec14ad3 1353
1ec14ad3
CW		 1354 return 0;
1355}
1356
f72b3435
MK		 1357static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1358 u32 seqno)
1359{
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 return dev_priv->last_seqno < seqno;
1362}
1363
c8c99b0f
BW		 1364/**
1365 * intel_ring_sync - sync the waiter to the signaller on seqno
1366 *
1367 * @waiter - ring that is waiting
1368 * @signaller - ring which has, or will signal
1369 * @seqno - seqno which the waiter will block on
1370 */
5ee426ca
BW		 1371
1372static int
599d924c 1373gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1374 struct intel_engine_cs *signaller,
1375 u32 seqno)
1376{
599d924c 1377 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1378 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1379 int ret;
1380
5fb9de1a 1381 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1382 if (ret)
1383 return ret;
1384
1385 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1386 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1387 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1388 MI_SEMAPHORE_SAD_GTE_SDD);
1389 intel_ring_emit(waiter, seqno);
1390 intel_ring_emit(waiter,
1391 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1392 intel_ring_emit(waiter,
1393 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1394 intel_ring_advance(waiter);
1395 return 0;
1396}
1397
c8c99b0f 1398static int
599d924c 1399gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1400 struct intel_engine_cs *signaller,
686cb5f9 1401 u32 seqno)
1ec14ad3 1402{
599d924c 1403 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1404 u32 dw1 = MI_SEMAPHORE_MBOX |
1405 MI_SEMAPHORE_COMPARE |
1406 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1407 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1408 int ret;
1ec14ad3 1409
1500f7ea
BW		 1410 /* Throughout all of the GEM code, seqno passed implies our current
1411 * seqno is >= the last seqno executed. However for hardware the
1412 * comparison is strictly greater than.
1413 */
1414 seqno -= 1;
1415
ebc348b2 1416 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1417
5fb9de1a 1418 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1419 if (ret)
1420 return ret;
1421
f72b3435
MK		 1422 /* If seqno wrap happened, omit the wait with no-ops */
1423 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1424 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1425 intel_ring_emit(waiter, seqno);
1426 intel_ring_emit(waiter, 0);
1427 intel_ring_emit(waiter, MI_NOOP);
1428 } else {
1429 intel_ring_emit(waiter, MI_NOOP);
1430 intel_ring_emit(waiter, MI_NOOP);
1431 intel_ring_emit(waiter, MI_NOOP);
1432 intel_ring_emit(waiter, MI_NOOP);
1433 }
c8c99b0f 1434 intel_ring_advance(waiter);
1ec14ad3
CW		 1435
1436 return 0;
1437}
1438
c6df541c
CW		 1439#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1440do { \
fcbc34e4
KG		 1441 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1442 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1443 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1444 intel_ring_emit(ring__, 0); \
1445 intel_ring_emit(ring__, 0); \
1446} while (0)
1447
1448static int
ee044a88 1449pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1450{
ee044a88 1451 struct intel_engine_cs *ring = req->ring;
18393f63 1452 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1453 int ret;
1454
1455 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1456 * incoherent with writes to memory, i.e. completely fubar,
1457 * so we need to use PIPE_NOTIFY instead.
1458 *
1459 * However, we also need to workaround the qword write
1460 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1461 * memory before requesting an interrupt.
1462 */
5fb9de1a 1463 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1464 if (ret)
1465 return ret;
1466
fcbc34e4 1467 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1468 PIPE_CONTROL_WRITE_FLUSH |
1469 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1470 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1471 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1472 intel_ring_emit(ring, 0);
1473 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1474 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1475 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1476 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1477 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1478 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1479 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1480 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1481 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1482 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1483 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1484
fcbc34e4 1485 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1486 PIPE_CONTROL_WRITE_FLUSH |
1487 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1488 PIPE_CONTROL_NOTIFY);
0d1aacac 1489 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1490 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1491 intel_ring_emit(ring, 0);
09246732 1492 __intel_ring_advance(ring);
c6df541c 1493
c6df541c
CW		 1494 return 0;
1495}
1496
4cd53c0c 1497static u32
a4872ba6 1498gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1499{
4cd53c0c
DV		 1500 /* Workaround to force correct ordering between irq and seqno writes on
1501 * ivb (and maybe also on snb) by reading from a CS register (like
1502 * ACTHD) before reading the status page. */
50877445
CW		 1503 if (!lazy_coherency) {
1504 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1505 POSTING_READ(RING_ACTHD(ring->mmio_base));
1506 }
1507
4cd53c0c
DV		 1508 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1509}
1510
8187a2b7 1511static u32
a4872ba6 1512ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1513{
1ec14ad3
CW		 1514 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1515}
1516
b70ec5bf 1517static void
a4872ba6 1518ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1519{
1520 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1521}
1522
c6df541c 1523static u32
a4872ba6 1524pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1525{
0d1aacac 1526 return ring->scratch.cpu_page[0];
c6df541c
CW		 1527}
1528
b70ec5bf 1529static void
a4872ba6 1530pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1531{
0d1aacac 1532 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1533}
1534
e48d8634 1535static bool
a4872ba6 1536gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1537{
1538 struct drm_device *dev = ring->dev;
4640c4ff 1539 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1540 unsigned long flags;
e48d8634 1541
7cd512f1 1542 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1543 return false;
1544
7338aefa 1545 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1546 if (ring->irq_refcount++ == 0)
480c8033 1547 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1548 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1549
1550 return true;
1551}
1552
1553static void
a4872ba6 1554gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1555{
1556 struct drm_device *dev = ring->dev;
4640c4ff 1557 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1558 unsigned long flags;
e48d8634 1559
7338aefa 1560 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1561 if (--ring->irq_refcount == 0)
480c8033 1562 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1563 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1564}
1565
b13c2b96 1566static bool
a4872ba6 1567i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1568{
78501eac 1569 struct drm_device *dev = ring->dev;
4640c4ff 1570 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1571 unsigned long flags;
62fdfeaf 1572
7cd512f1 1573 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1574 return false;
1575
7338aefa 1576 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1577 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1578 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1579 I915_WRITE(IMR, dev_priv->irq_mask);
1580 POSTING_READ(IMR);
1581 }
7338aefa 1582 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1583
1584 return true;
62fdfeaf
EA		 1585}
1586
8187a2b7 1587static void
a4872ba6 1588i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1589{
78501eac 1590 struct drm_device *dev = ring->dev;
4640c4ff 1591 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1592 unsigned long flags;
62fdfeaf 1593
7338aefa 1594 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1595 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1596 dev_priv->irq_mask |= ring->irq_enable_mask;
1597 I915_WRITE(IMR, dev_priv->irq_mask);
1598 POSTING_READ(IMR);
1599 }
7338aefa 1600 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1601}
1602
c2798b19 1603static bool
a4872ba6 1604i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1605{
1606 struct drm_device *dev = ring->dev;
4640c4ff 1607 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1608 unsigned long flags;
c2798b19 1609
7cd512f1 1610 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1611 return false;
1612
7338aefa 1613 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1614 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1615 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1616 I915_WRITE16(IMR, dev_priv->irq_mask);
1617 POSTING_READ16(IMR);
1618 }
7338aefa 1619 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1620
1621 return true;
1622}
1623
1624static void
a4872ba6 1625i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1626{
1627 struct drm_device *dev = ring->dev;
4640c4ff 1628 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1629 unsigned long flags;
c2798b19 1630
7338aefa 1631 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1632 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1633 dev_priv->irq_mask |= ring->irq_enable_mask;
1634 I915_WRITE16(IMR, dev_priv->irq_mask);
1635 POSTING_READ16(IMR);
1636 }
7338aefa 1637 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1638}
1639
b72f3acb 1640static int
a84c3ae1 1641bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1642 u32 invalidate_domains,
1643 u32 flush_domains)
d1b851fc 1644{
a84c3ae1 1645 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1646 int ret;
1647
5fb9de1a 1648 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1649 if (ret)
1650 return ret;
1651
1652 intel_ring_emit(ring, MI_FLUSH);
1653 intel_ring_emit(ring, MI_NOOP);
1654 intel_ring_advance(ring);
1655 return 0;
d1b851fc
ZN		 1656}
1657
3cce469c 1658static int
ee044a88 1659i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1660{
ee044a88 1661 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1662 int ret;
1663
5fb9de1a 1664 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1665 if (ret)
1666 return ret;
6f392d54 1667
3cce469c
CW		 1668 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1669 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1670 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1671 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1672 __intel_ring_advance(ring);
d1b851fc 1673
3cce469c 1674 return 0;
d1b851fc
ZN		 1675}
1676
0f46832f 1677static bool
a4872ba6 1678gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1679{
1680 struct drm_device *dev = ring->dev;
4640c4ff 1681 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1682 unsigned long flags;
0f46832f 1683
7cd512f1
DV		 1684 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1685 return false;
0f46832f 1686
7338aefa 1687 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1688 if (ring->irq_refcount++ == 0) {
040d2baa 1689 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1690 I915_WRITE_IMR(ring,
1691 ~(ring->irq_enable_mask |
35a85ac6 1692 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1693 else
1694 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1695 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1696 }
7338aefa 1697 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1698
1699 return true;
1700}
1701
1702static void
a4872ba6 1703gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1704{
1705 struct drm_device *dev = ring->dev;
4640c4ff 1706 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1707 unsigned long flags;
0f46832f 1708
7338aefa 1709 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1710 if (--ring->irq_refcount == 0) {
040d2baa 1711 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1712 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1713 else
1714 I915_WRITE_IMR(ring, ~0);
480c8033 1715 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1716 }
7338aefa 1717 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1718}
1719
a19d2933 1720static bool
a4872ba6 1721hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1722{
1723 struct drm_device *dev = ring->dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 unsigned long flags;
1726
7cd512f1 1727 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1728 return false;
1729
59cdb63d 1730 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1731 if (ring->irq_refcount++ == 0) {
a19d2933 1732 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1733 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1734 }
59cdb63d 1735 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1736
1737 return true;
1738}
1739
1740static void
a4872ba6 1741hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1742{
1743 struct drm_device *dev = ring->dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 unsigned long flags;
1746
59cdb63d 1747 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1748 if (--ring->irq_refcount == 0) {
a19d2933 1749 I915_WRITE_IMR(ring, ~0);
480c8033 1750 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1751 }
59cdb63d 1752 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1753}
1754
abd58f01 1755static bool
a4872ba6 1756gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1757{
1758 struct drm_device *dev = ring->dev;
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 unsigned long flags;
1761
7cd512f1 1762 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1763 return false;
1764
1765 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1766 if (ring->irq_refcount++ == 0) {
1767 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1768 I915_WRITE_IMR(ring,
1769 ~(ring->irq_enable_mask |
1770 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1771 } else {
1772 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1773 }
1774 POSTING_READ(RING_IMR(ring->mmio_base));
1775 }
1776 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1777
1778 return true;
1779}
1780
1781static void
a4872ba6 1782gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1783{
1784 struct drm_device *dev = ring->dev;
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1786 unsigned long flags;
1787
1788 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1789 if (--ring->irq_refcount == 0) {
1790 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1791 I915_WRITE_IMR(ring,
1792 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1793 } else {
1794 I915_WRITE_IMR(ring, ~0);
1795 }
1796 POSTING_READ(RING_IMR(ring->mmio_base));
1797 }
1798 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1799}
1800
d1b851fc 1801static int
53fddaf7 1802i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1803 u64 offset, u32 length,
8e004efc 1804 unsigned dispatch_flags)
d1b851fc 1805{
53fddaf7 1806 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1807 int ret;
78501eac 1808
5fb9de1a 1809 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1810 if (ret)
1811 return ret;
1812
78501eac 1813 intel_ring_emit(ring,
65f56876
CW		 1814 MI_BATCH_BUFFER_START |
1815 MI_BATCH_GTT |
8e004efc
JH		 1816 (dispatch_flags & I915_DISPATCH_SECURE ?
1817 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1818 intel_ring_emit(ring, offset);
78501eac
CW		 1819 intel_ring_advance(ring);
1820
d1b851fc
ZN		 1821 return 0;
1822}
1823
b45305fc
DV		 1824/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1825#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1826#define I830_TLB_ENTRIES (2)
1827#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1828static int
53fddaf7 1829i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1830 u64 offset, u32 len,
1831 unsigned dispatch_flags)
62fdfeaf 1832{
53fddaf7 1833 struct intel_engine_cs *ring = req->ring;
c4d69da1 1834 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1835 int ret;
62fdfeaf 1836
5fb9de1a 1837 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1838 if (ret)
1839 return ret;
62fdfeaf 1840
c4d69da1
CW		 1841 /* Evict the invalid PTE TLBs */
1842 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1843 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1844 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1845 intel_ring_emit(ring, cs_offset);
1846 intel_ring_emit(ring, 0xdeadbeef);
1847 intel_ring_emit(ring, MI_NOOP);
1848 intel_ring_advance(ring);
b45305fc 1849
8e004efc 1850 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1851 if (len > I830_BATCH_LIMIT)
1852 return -ENOSPC;
1853
5fb9de1a 1854 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1855 if (ret)
1856 return ret;
c4d69da1
CW		 1857
1858 /* Blit the batch (which has now all relocs applied) to the
1859 * stable batch scratch bo area (so that the CS never
1860 * stumbles over its tlb invalidation bug) ...
1861 */
1862 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1863 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1864 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1865 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1866 intel_ring_emit(ring, 4096);
1867 intel_ring_emit(ring, offset);
c4d69da1 1868
b45305fc 1869 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1870 intel_ring_emit(ring, MI_NOOP);
1871 intel_ring_advance(ring);
b45305fc
DV		 1872
1873 /* ... and execute it. */
c4d69da1 1874 offset = cs_offset;
b45305fc 1875 }
e1f99ce6 1876
5fb9de1a 1877 ret = intel_ring_begin(req, 4);
c4d69da1
CW		 1878 if (ret)
1879 return ret;
1880
1881 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1882 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1883 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1884 intel_ring_emit(ring, offset + len - 8);
1885 intel_ring_emit(ring, MI_NOOP);
1886 intel_ring_advance(ring);
1887
fb3256da
DV		 1888 return 0;
1889}
1890
1891static int
53fddaf7 1892i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1893 u64 offset, u32 len,
8e004efc 1894 unsigned dispatch_flags)
fb3256da 1895{
53fddaf7 1896 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1897 int ret;
1898
5fb9de1a 1899 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1900 if (ret)
1901 return ret;
1902
65f56876 1903 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1904 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1905 0 : MI_BATCH_NON_SECURE));
c4e7a414 1906 intel_ring_advance(ring);
62fdfeaf 1907
62fdfeaf
EA		 1908 return 0;
1909}
1910
a4872ba6 1911static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1912{
05394f39 1913 struct drm_i915_gem_object *obj;
62fdfeaf 1914
8187a2b7
ZN		 1915 obj = ring->status_page.obj;
1916 if (obj == NULL)
62fdfeaf 1917 return;
62fdfeaf 1918
9da3da66 1919 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1920 i915_gem_object_ggtt_unpin(obj);
05394f39 1921 drm_gem_object_unreference(&obj->base);
8187a2b7 1922 ring->status_page.obj = NULL;
62fdfeaf
EA		 1923}
1924
a4872ba6 1925static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1926{
05394f39 1927 struct drm_i915_gem_object *obj;
62fdfeaf 1928
e3efda49 1929 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1930 unsigned flags;
e3efda49 1931 int ret;
e4ffd173 1932
e3efda49
CW		 1933 obj = i915_gem_alloc_object(ring->dev, 4096);
1934 if (obj == NULL) {
1935 DRM_ERROR("Failed to allocate status page\n");
1936 return -ENOMEM;
1937 }
62fdfeaf 1938
e3efda49
CW		 1939 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1940 if (ret)
1941 goto err_unref;
1942
1f767e02
CW		 1943 flags = 0;
1944 if (!HAS_LLC(ring->dev))
1945 /* On g33, we cannot place HWS above 256MiB, so
1946 * restrict its pinning to the low mappable arena.
1947 * Though this restriction is not documented for
1948 * gen4, gen5, or byt, they also behave similarly
1949 * and hang if the HWS is placed at the top of the
1950 * GTT. To generalise, it appears that all !llc
1951 * platforms have issues with us placing the HWS
1952 * above the mappable region (even though we never
1953 * actualy map it).
1954 */
1955 flags |= PIN_MAPPABLE;
1956 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1957 if (ret) {
1958err_unref:
1959 drm_gem_object_unreference(&obj->base);
1960 return ret;
1961 }
1962
1963 ring->status_page.obj = obj;
1964 }
62fdfeaf 1965
f343c5f6 1966 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1967 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1968 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1969
8187a2b7
ZN		 1970 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1971 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1972
1973 return 0;
62fdfeaf
EA		 1974}
1975
a4872ba6 1976static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1977{
1978 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1979
1980 if (!dev_priv->status_page_dmah) {
1981 dev_priv->status_page_dmah =
1982 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1983 if (!dev_priv->status_page_dmah)
1984 return -ENOMEM;
1985 }
1986
6b8294a4
CW		 1987 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1988 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1989
1990 return 0;
1991}
1992
7ba717cf 1993void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1994{
2919d291 1995 iounmap(ringbuf->virtual_start);
7ba717cf 1996 ringbuf->virtual_start = NULL;
2919d291 1997 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1998}
1999
2000int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2001 struct intel_ringbuffer *ringbuf)
2002{
2003 struct drm_i915_private *dev_priv = to_i915(dev);
2004 struct drm_i915_gem_object *obj = ringbuf->obj;
2005 int ret;
2006
2007 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2008 if (ret)
2009 return ret;
2010
2011 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2012 if (ret) {
2013 i915_gem_object_ggtt_unpin(obj);
2014 return ret;
2015 }
2016
2017 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2018 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2019 if (ringbuf->virtual_start == NULL) {
2020 i915_gem_object_ggtt_unpin(obj);
2021 return -EINVAL;
2022 }
2023
2024 return 0;
2025}
2026
01101fa7 2027static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2028{
2919d291
OM		 2029 drm_gem_object_unreference(&ringbuf->obj->base);
2030 ringbuf->obj = NULL;
2031}
2032
01101fa7
CW		 2033static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2034 struct intel_ringbuffer *ringbuf)
62fdfeaf 2035{
05394f39 2036 struct drm_i915_gem_object *obj;
62fdfeaf 2037
ebc052e0
CW		 2038 obj = NULL;
2039 if (!HAS_LLC(dev))
93b0a4e0 2040 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2041 if (obj == NULL)
93b0a4e0 2042 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2043 if (obj == NULL)
2044 return -ENOMEM;
8187a2b7 2045
24f3a8cf
AG		 2046 /* mark ring buffers as read-only from GPU side by default */
2047 obj->gt_ro = 1;
2048
93b0a4e0 2049 ringbuf->obj = obj;
e3efda49 2050
7ba717cf 2051 return 0;
e3efda49
CW		 2052}
2053
01101fa7
CW		 2054struct intel_ringbuffer *
2055intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2056{
2057 struct intel_ringbuffer *ring;
2058 int ret;
2059
2060 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2061 if (ring == NULL)
2062 return ERR_PTR(-ENOMEM);
2063
2064 ring->ring = engine;
2065
2066 ring->size = size;
2067 /* Workaround an erratum on the i830 which causes a hang if
2068 * the TAIL pointer points to within the last 2 cachelines
2069 * of the buffer.
2070 */
2071 ring->effective_size = size;
2072 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2073 ring->effective_size -= 2 * CACHELINE_BYTES;
2074
2075 ring->last_retired_head = -1;
2076 intel_ring_update_space(ring);
2077
2078 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2079 if (ret) {
2080 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2081 engine->name, ret);
2082 kfree(ring);
2083 return ERR_PTR(ret);
2084 }
2085
2086 return ring;
2087}
2088
2089void
2090intel_ringbuffer_free(struct intel_ringbuffer *ring)
2091{
2092 intel_destroy_ringbuffer_obj(ring);
2093 kfree(ring);
2094}
2095
e3efda49 2096static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2097 struct intel_engine_cs *ring)
e3efda49 2098{
bfc882b4 2099 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2100 int ret;
2101
bfc882b4
DV		 2102 WARN_ON(ring->buffer);
2103
e3efda49
CW		 2104 ring->dev = dev;
2105 INIT_LIST_HEAD(&ring->active_list);
2106 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2107 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2108 i915_gem_batch_pool_init(dev, &ring->batch_pool);
ebc348b2 2109 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2110
2111 init_waitqueue_head(&ring->irq_queue);
2112
01101fa7
CW		 2113 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2114 if (IS_ERR(ringbuf))
2115 return PTR_ERR(ringbuf);
2116 ring->buffer = ringbuf;
2117
e3efda49
CW		 2118 if (I915_NEED_GFX_HWS(dev)) {
2119 ret = init_status_page(ring);
2120 if (ret)
8ee14975 2121 goto error;
e3efda49
CW		 2122 } else {
2123 BUG_ON(ring->id != RCS);
2124 ret = init_phys_status_page(ring);
2125 if (ret)
8ee14975 2126 goto error;
e3efda49
CW		 2127 }
2128
bfc882b4
DV		 2129 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2130 if (ret) {
2131 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2132 ring->name, ret);
2133 intel_destroy_ringbuffer_obj(ringbuf);
2134 goto error;
e3efda49 2135 }
62fdfeaf 2136
44e895a8
BV		 2137 ret = i915_cmd_parser_init_ring(ring);
2138 if (ret)
8ee14975
OM		 2139 goto error;
2140
8ee14975 2141 return 0;
351e3db2 2142
8ee14975 2143error:
01101fa7 2144 intel_ringbuffer_free(ringbuf);
8ee14975
OM		 2145 ring->buffer = NULL;
2146 return ret;
62fdfeaf
EA		 2147}
2148
a4872ba6 2149void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2150{
6402c330 2151 struct drm_i915_private *dev_priv;
33626e6a 2152
93b0a4e0 2153 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2154 return;
2155
6402c330 2156 dev_priv = to_i915(ring->dev);
6402c330 2157
e3efda49 2158 intel_stop_ring_buffer(ring);
de8f0a50 2159 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2160
01101fa7
CW		 2161 intel_unpin_ringbuffer_obj(ring->buffer);
2162 intel_ringbuffer_free(ring->buffer);
2163 ring->buffer = NULL;
78501eac 2164
8d19215b
ZN		 2165 if (ring->cleanup)
2166 ring->cleanup(ring);
2167
78501eac 2168 cleanup_status_page(ring);
44e895a8
BV		 2169
2170 i915_cmd_parser_fini_ring(ring);
06fbca71 2171 i915_gem_batch_pool_fini(&ring->batch_pool);
62fdfeaf
EA		 2172}
2173
595e1eeb 2174static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2175{
93b0a4e0 2176 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2177 struct drm_i915_gem_request *request;
b4716185
CW		 2178 unsigned space;
2179 int ret;
a71d8d94 2180
ebd0fd4b
DG		 2181 if (intel_ring_space(ringbuf) >= n)
2182 return 0;
a71d8d94 2183
79bbcc29
JH		 2184 /* The whole point of reserving space is to not wait! */
2185 WARN_ON(ringbuf->reserved_in_use);
2186
a71d8d94 2187 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2188 space = __intel_ring_space(request->postfix, ringbuf->tail,
2189 ringbuf->size);
2190 if (space >= n)
a71d8d94 2191 break;
a71d8d94
CW		 2192 }
2193
595e1eeb 2194 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2195 return -ENOSPC;
2196
a4b3a571 2197 ret = i915_wait_request(request);
a71d8d94
CW		 2198 if (ret)
2199 return ret;
2200
b4716185 2201 ringbuf->space = space;
a71d8d94
CW		 2202 return 0;
2203}
2204
79bbcc29 2205static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
3e960501
CW		 2206{
2207 uint32_t __iomem *virt;
93b0a4e0 2208 int rem = ringbuf->size - ringbuf->tail;
3e960501 2209
93b0a4e0 2210 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2211 rem /= 4;
2212 while (rem--)
2213 iowrite32(MI_NOOP, virt++);
2214
93b0a4e0 2215 ringbuf->tail = 0;
ebd0fd4b 2216 intel_ring_update_space(ringbuf);
3e960501
CW		 2217}
2218
a4872ba6 2219int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2220{
a4b3a571 2221 struct drm_i915_gem_request *req;
3e960501 2222
3e960501
CW		 2223 /* Wait upon the last request to be completed */
2224 if (list_empty(&ring->request_list))
2225 return 0;
2226
a4b3a571 2227 req = list_entry(ring->request_list.prev,
b4716185
CW		 2228 struct drm_i915_gem_request,
2229 list);
2230
2231 /* Make sure we do not trigger any retires */
2232 return __i915_wait_request(req,
2233 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2234 to_i915(ring->dev)->mm.interruptible,
2235 NULL, NULL);
3e960501
CW		 2236}
2237
6689cb2b 2238int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2239{
6689cb2b 2240 request->ringbuf = request->ring->buffer;
9eba5d4a 2241 return 0;
9d773091
CW		 2242}
2243
ccd98fe4
JH		 2244int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2245{
2246 /*
2247 * The first call merely notes the reserve request and is common for
2248 * all back ends. The subsequent localised _begin() call actually
2249 * ensures that the reservation is available. Without the begin, if
2250 * the request creator immediately submitted the request without
2251 * adding any commands to it then there might not actually be
2252 * sufficient room for the submission commands.
2253 */
2254 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2255
2256 return intel_ring_begin(request, 0);
2257}
2258
29b1b415
JH		 2259void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2260{
ccd98fe4 2261 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2262 WARN_ON(ringbuf->reserved_in_use);
2263
2264 ringbuf->reserved_size = size;
29b1b415
JH		 2265}
2266
2267void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2268{
2269 WARN_ON(ringbuf->reserved_in_use);
2270
2271 ringbuf->reserved_size = 0;
2272 ringbuf->reserved_in_use = false;
2273}
2274
2275void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2276{
2277 WARN_ON(ringbuf->reserved_in_use);
2278
2279 ringbuf->reserved_in_use = true;
2280 ringbuf->reserved_tail = ringbuf->tail;
2281}
2282
2283void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2284{
2285 WARN_ON(!ringbuf->reserved_in_use);
79bbcc29
JH		 2286 if (ringbuf->tail > ringbuf->reserved_tail) {
2287 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2288 "request reserved size too small: %d vs %d!\n",
2289 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2290 } else {
2291 /*
2292 * The ring was wrapped while the reserved space was in use.
2293 * That means that some unknown amount of the ring tail was
2294 * no-op filled and skipped. Thus simply adding the ring size
2295 * to the tail and doing the above space check will not work.
2296 * Rather than attempt to track how much tail was skipped,
2297 * it is much simpler to say that also skipping the sanity
2298 * check every once in a while is not a big issue.
2299 */
2300 }
29b1b415
JH		 2301
2302 ringbuf->reserved_size = 0;
2303 ringbuf->reserved_in_use = false;
2304}
2305
2306static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2307{
93b0a4e0 2308 struct intel_ringbuffer *ringbuf = ring->buffer;
79bbcc29
JH		 2309 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2310 int remain_actual = ringbuf->size - ringbuf->tail;
2311 int ret, total_bytes, wait_bytes = 0;
2312 bool need_wrap = false;
29b1b415 2313
79bbcc29
JH		 2314 if (ringbuf->reserved_in_use)
2315 total_bytes = bytes;
2316 else
2317 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2318
79bbcc29
JH		 2319 if (unlikely(bytes > remain_usable)) {
2320 /*
2321 * Not enough space for the basic request. So need to flush
2322 * out the remainder and then wait for base + reserved.
2323 */
2324 wait_bytes = remain_actual + total_bytes;
2325 need_wrap = true;
2326 } else {
2327 if (unlikely(total_bytes > remain_usable)) {
2328 /*
2329 * The base request will fit but the reserved space
2330 * falls off the end. So only need to to wait for the
2331 * reserved size after flushing out the remainder.
2332 */
2333 wait_bytes = remain_actual + ringbuf->reserved_size;
2334 need_wrap = true;
2335 } else if (total_bytes > ringbuf->space) {
2336 /* No wrapping required, just waiting. */
2337 wait_bytes = total_bytes;
29b1b415 2338 }
cbcc80df
MK		 2339 }
2340
79bbcc29
JH		 2341 if (wait_bytes) {
2342 ret = ring_wait_for_space(ring, wait_bytes);
cbcc80df
MK		 2343 if (unlikely(ret))
2344 return ret;
79bbcc29
JH		 2345
2346 if (need_wrap)
2347 __wrap_ring_buffer(ringbuf);
cbcc80df
MK		 2348 }
2349
cbcc80df
MK		 2350 return 0;
2351}
2352
5fb9de1a 2353int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2354 int num_dwords)
8187a2b7 2355{
5fb9de1a
JH		 2356 struct intel_engine_cs *ring;
2357 struct drm_i915_private *dev_priv;
e1f99ce6 2358 int ret;
78501eac 2359
5fb9de1a
JH		 2360 WARN_ON(req == NULL);
2361 ring = req->ring;
2362 dev_priv = ring->dev->dev_private;
2363
33196ded
DV		 2364 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2365 dev_priv->mm.interruptible);
de2b9985
DV		 2366 if (ret)
2367 return ret;
21dd3734 2368
304d695c
CW		 2369 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2370 if (ret)
2371 return ret;
2372
ee1b1e5e 2373 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2374 return 0;
8187a2b7 2375}
78501eac 2376
753b1ad4 2377/* Align the ring tail to a cacheline boundary */
bba09b12 2378int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2379{
bba09b12 2380 struct intel_engine_cs *ring = req->ring;
ee1b1e5e 2381 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2382 int ret;
2383
2384 if (num_dwords == 0)
2385 return 0;
2386
18393f63 2387 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2388 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2389 if (ret)
2390 return ret;
2391
2392 while (num_dwords--)
2393 intel_ring_emit(ring, MI_NOOP);
2394
2395 intel_ring_advance(ring);
2396
2397 return 0;
2398}
2399
a4872ba6 2400void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2401{
3b2cc8ab
OM		 2402 struct drm_device *dev = ring->dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2404
3b2cc8ab 2405 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2406 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2407 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2408 if (HAS_VEBOX(dev))
5020150b 2409 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2410 }
d97ed339 2411
f7e98ad4 2412 ring->set_seqno(ring, seqno);
92cab734 2413 ring->hangcheck.seqno = seqno;
8187a2b7 2414}
62fdfeaf 2415
a4872ba6 2416static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2417 u32 value)
881f47b6 2418{
4640c4ff 2419 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2420
2421 /* Every tail move must follow the sequence below */
12f55818
CW		 2422
2423 /* Disable notification that the ring is IDLE. The GT
2424 * will then assume that it is busy and bring it out of rc6.
2425 */
0206e353 2426 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2427 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2428
2429 /* Clear the context id. Here be magic! */
2430 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2431
12f55818 2432 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2433 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2434 GEN6_BSD_SLEEP_INDICATOR) == 0,
2435 50))
2436 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2437
12f55818 2438 /* Now that the ring is fully powered up, update the tail */
0206e353 2439 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2440 POSTING_READ(RING_TAIL(ring->mmio_base));
2441
2442 /* Let the ring send IDLE messages to the GT again,
2443 * and so let it sleep to conserve power when idle.
2444 */
0206e353 2445 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2446 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2447}
2448
a84c3ae1 2449static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2450 u32 invalidate, u32 flush)
881f47b6 2451{
a84c3ae1 2452 struct intel_engine_cs *ring = req->ring;
71a77e07 2453 uint32_t cmd;
b72f3acb
CW		 2454 int ret;
2455
5fb9de1a 2456 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2457 if (ret)
2458 return ret;
2459
71a77e07 2460 cmd = MI_FLUSH_DW;
075b3bba
BW		 2461 if (INTEL_INFO(ring->dev)->gen >= 8)
2462 cmd += 1;
f0a1fb10
CW		 2463
2464 /* We always require a command barrier so that subsequent
2465 * commands, such as breadcrumb interrupts, are strictly ordered
2466 * wrt the contents of the write cache being flushed to memory
2467 * (and thus being coherent from the CPU).
2468 */
2469 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2470
9a289771
JB		 2471 /*
2472 * Bspec vol 1c.5 - video engine command streamer:
2473 * "If ENABLED, all TLBs will be invalidated once the flush
2474 * operation is complete. This bit is only valid when the
2475 * Post-Sync Operation field is a value of 1h or 3h."
2476 */
71a77e07 2477 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2478 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2479
71a77e07 2480 intel_ring_emit(ring, cmd);
9a289771 2481 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2482 if (INTEL_INFO(ring->dev)->gen >= 8) {
2483 intel_ring_emit(ring, 0); /* upper addr */
2484 intel_ring_emit(ring, 0); /* value */
2485 } else {
2486 intel_ring_emit(ring, 0);
2487 intel_ring_emit(ring, MI_NOOP);
2488 }
b72f3acb
CW		 2489 intel_ring_advance(ring);
2490 return 0;
881f47b6
XH		 2491}
2492
1c7a0623 2493static int
53fddaf7 2494gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2495 u64 offset, u32 len,
8e004efc 2496 unsigned dispatch_flags)
1c7a0623 2497{
53fddaf7 2498 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2499 bool ppgtt = USES_PPGTT(ring->dev) &&
2500 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2501 int ret;
2502
5fb9de1a 2503 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2504 if (ret)
2505 return ret;
2506
2507 /* FIXME(BDW): Address space and security selectors. */
919032ec
AJ		 2508 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2509 (dispatch_flags & I915_DISPATCH_RS ?
2510 MI_BATCH_RESOURCE_STREAMER : 0));
9bcb144c
BW		 2511 intel_ring_emit(ring, lower_32_bits(offset));
2512 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2513 intel_ring_emit(ring, MI_NOOP);
2514 intel_ring_advance(ring);
2515
2516 return 0;
2517}
2518
d7d4eedd 2519static int
53fddaf7 2520hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2521 u64 offset, u32 len,
2522 unsigned dispatch_flags)
d7d4eedd 2523{
53fddaf7 2524 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2525 int ret;
2526
5fb9de1a 2527 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2528 if (ret)
2529 return ret;
2530
2531 intel_ring_emit(ring,
77072258 2532 MI_BATCH_BUFFER_START |
8e004efc 2533 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2534 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2535 (dispatch_flags & I915_DISPATCH_RS ?
2536 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd
CW		 2537 /* bit0-7 is the length on GEN6+ */
2538 intel_ring_emit(ring, offset);
2539 intel_ring_advance(ring);
2540
2541 return 0;
2542}
2543
881f47b6 2544static int
53fddaf7 2545gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2546 u64 offset, u32 len,
8e004efc 2547 unsigned dispatch_flags)
881f47b6 2548{
53fddaf7 2549 struct intel_engine_cs *ring = req->ring;
0206e353 2550 int ret;
ab6f8e32 2551
5fb9de1a 2552 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2553 if (ret)
2554 return ret;
e1f99ce6 2555
d7d4eedd
CW		 2556 intel_ring_emit(ring,
2557 MI_BATCH_BUFFER_START |
8e004efc
JH		 2558 (dispatch_flags & I915_DISPATCH_SECURE ?
2559 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2560 /* bit0-7 is the length on GEN6+ */
2561 intel_ring_emit(ring, offset);
2562 intel_ring_advance(ring);
ab6f8e32 2563
0206e353 2564 return 0;
881f47b6
XH		 2565}
2566
549f7365
CW		 2567/* Blitter support (SandyBridge+) */
2568
a84c3ae1 2569static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2570 u32 invalidate, u32 flush)
8d19215b 2571{
a84c3ae1 2572 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2573 struct drm_device *dev = ring->dev;
71a77e07 2574 uint32_t cmd;
b72f3acb
CW		 2575 int ret;
2576
5fb9de1a 2577 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2578 if (ret)
2579 return ret;
2580
71a77e07 2581 cmd = MI_FLUSH_DW;
dbef0f15 2582 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2583 cmd += 1;
f0a1fb10
CW		 2584
2585 /* We always require a command barrier so that subsequent
2586 * commands, such as breadcrumb interrupts, are strictly ordered
2587 * wrt the contents of the write cache being flushed to memory
2588 * (and thus being coherent from the CPU).
2589 */
2590 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2591
9a289771
JB		 2592 /*
2593 * Bspec vol 1c.3 - blitter engine command streamer:
2594 * "If ENABLED, all TLBs will be invalidated once the flush
2595 * operation is complete. This bit is only valid when the
2596 * Post-Sync Operation field is a value of 1h or 3h."
2597 */
71a77e07 2598 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2599 cmd |= MI_INVALIDATE_TLB;
71a77e07 2600 intel_ring_emit(ring, cmd);
9a289771 2601 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2602 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2603 intel_ring_emit(ring, 0); /* upper addr */
2604 intel_ring_emit(ring, 0); /* value */
2605 } else {
2606 intel_ring_emit(ring, 0);
2607 intel_ring_emit(ring, MI_NOOP);
2608 }
b72f3acb 2609 intel_ring_advance(ring);
fd3da6c9 2610
b72f3acb 2611 return 0;
8d19215b
ZN		 2612}
2613
5c1143bb
XH		 2614int intel_init_render_ring_buffer(struct drm_device *dev)
2615{
4640c4ff 2616 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2617 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2618 struct drm_i915_gem_object *obj;
2619 int ret;
5c1143bb 2620
59465b5f
DV		 2621 ring->name = "render ring";
2622 ring->id = RCS;
2623 ring->mmio_base = RENDER_RING_BASE;
2624
707d9cf9 2625 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2626 if (i915_semaphore_is_enabled(dev)) {
2627 obj = i915_gem_alloc_object(dev, 4096);
2628 if (obj == NULL) {
2629 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2630 i915.semaphores = 0;
2631 } else {
2632 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2633 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2634 if (ret != 0) {
2635 drm_gem_object_unreference(&obj->base);
2636 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2637 i915.semaphores = 0;
2638 } else
2639 dev_priv->semaphore_obj = obj;
2640 }
2641 }
7225342a 2642
8f0e2b9d 2643 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2644 ring->add_request = gen6_add_request;
2645 ring->flush = gen8_render_ring_flush;
2646 ring->irq_get = gen8_ring_get_irq;
2647 ring->irq_put = gen8_ring_put_irq;
2648 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2649 ring->get_seqno = gen6_ring_get_seqno;
2650 ring->set_seqno = ring_set_seqno;
2651 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2652 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2653 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2654 ring->semaphore.signal = gen8_rcs_signal;
2655 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2656 }
2657 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2658 ring->add_request = gen6_add_request;
4772eaeb 2659 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2660 if (INTEL_INFO(dev)->gen == 6)
b3111509 2661 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2662 ring->irq_get = gen6_ring_get_irq;
2663 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2664 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2665 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2666 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2667 if (i915_semaphore_is_enabled(dev)) {
2668 ring->semaphore.sync_to = gen6_ring_sync;
2669 ring->semaphore.signal = gen6_signal;
2670 /*
2671 * The current semaphore is only applied on pre-gen8
2672 * platform. And there is no VCS2 ring on the pre-gen8
2673 * platform. So the semaphore between RCS and VCS2 is
2674 * initialized as INVALID. Gen8 will initialize the
2675 * sema between VCS2 and RCS later.
2676 */
2677 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2678 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2679 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2680 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2681 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2682 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2683 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2684 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2685 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2686 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2687 }
c6df541c
CW		 2688 } else if (IS_GEN5(dev)) {
2689 ring->add_request = pc_render_add_request;
46f0f8d1 2690 ring->flush = gen4_render_ring_flush;
c6df541c 2691 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2692 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2693 ring->irq_get = gen5_ring_get_irq;
2694 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2695 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2696 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2697 } else {
8620a3a9 2698 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2699 if (INTEL_INFO(dev)->gen < 4)
2700 ring->flush = gen2_render_ring_flush;
2701 else
2702 ring->flush = gen4_render_ring_flush;
59465b5f 2703 ring->get_seqno = ring_get_seqno;
b70ec5bf 2704 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2705 if (IS_GEN2(dev)) {
2706 ring->irq_get = i8xx_ring_get_irq;
2707 ring->irq_put = i8xx_ring_put_irq;
2708 } else {
2709 ring->irq_get = i9xx_ring_get_irq;
2710 ring->irq_put = i9xx_ring_put_irq;
2711 }
e3670319 2712 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2713 }
59465b5f 2714 ring->write_tail = ring_write_tail;
707d9cf9 2715
d7d4eedd
CW		 2716 if (IS_HASWELL(dev))
2717 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2718 else if (IS_GEN8(dev))
2719 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2720 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2721 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2722 else if (INTEL_INFO(dev)->gen >= 4)
2723 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2724 else if (IS_I830(dev) || IS_845G(dev))
2725 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2726 else
2727 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2728 ring->init_hw = init_render_ring;
59465b5f
DV		 2729 ring->cleanup = render_ring_cleanup;
2730
b45305fc
DV		 2731 /* Workaround batchbuffer to combat CS tlb bug. */
2732 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2733 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2734 if (obj == NULL) {
2735 DRM_ERROR("Failed to allocate batch bo\n");
2736 return -ENOMEM;
2737 }
2738
be1fa129 2739 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2740 if (ret != 0) {
2741 drm_gem_object_unreference(&obj->base);
2742 DRM_ERROR("Failed to ping batch bo\n");
2743 return ret;
2744 }
2745
0d1aacac
CW		 2746 ring->scratch.obj = obj;
2747 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2748 }
2749
99be1dfe
DV		 2750 ret = intel_init_ring_buffer(dev, ring);
2751 if (ret)
2752 return ret;
2753
2754 if (INTEL_INFO(dev)->gen >= 5) {
2755 ret = intel_init_pipe_control(ring);
2756 if (ret)
2757 return ret;
2758 }
2759
2760 return 0;
5c1143bb
XH		 2761}
2762
2763int intel_init_bsd_ring_buffer(struct drm_device *dev)
2764{
4640c4ff 2765 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2766 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2767
58fa3835
DV		 2768 ring->name = "bsd ring";
2769 ring->id = VCS;
2770
0fd2c201 2771 ring->write_tail = ring_write_tail;
780f18c8 2772 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2773 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2774 /* gen6 bsd needs a special wa for tail updates */
2775 if (IS_GEN6(dev))
2776 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2777 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2778 ring->add_request = gen6_add_request;
2779 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2780 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2781 if (INTEL_INFO(dev)->gen >= 8) {
2782 ring->irq_enable_mask =
2783 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2784 ring->irq_get = gen8_ring_get_irq;
2785 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2786 ring->dispatch_execbuffer =
2787 gen8_ring_dispatch_execbuffer;
707d9cf9 2788 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2789 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2790 ring->semaphore.signal = gen8_xcs_signal;
2791 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2792 }
abd58f01
BW		 2793 } else {
2794 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2795 ring->irq_get = gen6_ring_get_irq;
2796 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2797 ring->dispatch_execbuffer =
2798 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2799 if (i915_semaphore_is_enabled(dev)) {
2800 ring->semaphore.sync_to = gen6_ring_sync;
2801 ring->semaphore.signal = gen6_signal;
2802 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2803 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2804 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2805 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2806 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2807 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2808 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2809 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2810 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2811 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2812 }
abd58f01 2813 }
58fa3835
DV		 2814 } else {
2815 ring->mmio_base = BSD_RING_BASE;
58fa3835 2816 ring->flush = bsd_ring_flush;
8620a3a9 2817 ring->add_request = i9xx_add_request;
58fa3835 2818 ring->get_seqno = ring_get_seqno;
b70ec5bf 2819 ring->set_seqno = ring_set_seqno;
e48d8634 2820 if (IS_GEN5(dev)) {
cc609d5d 2821 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2822 ring->irq_get = gen5_ring_get_irq;
2823 ring->irq_put = gen5_ring_put_irq;
2824 } else {
e3670319 2825 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2826 ring->irq_get = i9xx_ring_get_irq;
2827 ring->irq_put = i9xx_ring_put_irq;
2828 }
fb3256da 2829 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2830 }
ecfe00d8 2831 ring->init_hw = init_ring_common;
58fa3835 2832
1ec14ad3 2833 return intel_init_ring_buffer(dev, ring);
5c1143bb 2834}
549f7365 2835
845f74a7 2836/**
62659920 2837 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2838 */
2839int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2840{
2841 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2842 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2843
f7b64236 2844 ring->name = "bsd2 ring";
845f74a7
ZY		 2845 ring->id = VCS2;
2846
2847 ring->write_tail = ring_write_tail;
2848 ring->mmio_base = GEN8_BSD2_RING_BASE;
2849 ring->flush = gen6_bsd_ring_flush;
2850 ring->add_request = gen6_add_request;
2851 ring->get_seqno = gen6_ring_get_seqno;
2852 ring->set_seqno = ring_set_seqno;
2853 ring->irq_enable_mask =
2854 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2855 ring->irq_get = gen8_ring_get_irq;
2856 ring->irq_put = gen8_ring_put_irq;
2857 ring->dispatch_execbuffer =
2858 gen8_ring_dispatch_execbuffer;
3e78998a 2859 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2860 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2861 ring->semaphore.signal = gen8_xcs_signal;
2862 GEN8_RING_SEMAPHORE_INIT;
2863 }
ecfe00d8 2864 ring->init_hw = init_ring_common;
845f74a7
ZY		 2865
2866 return intel_init_ring_buffer(dev, ring);
2867}
2868
549f7365
CW		 2869int intel_init_blt_ring_buffer(struct drm_device *dev)
2870{
4640c4ff 2871 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2872 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2873
3535d9dd
DV		 2874 ring->name = "blitter ring";
2875 ring->id = BCS;
2876
2877 ring->mmio_base = BLT_RING_BASE;
2878 ring->write_tail = ring_write_tail;
ea251324 2879 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2880 ring->add_request = gen6_add_request;
2881 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2882 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2883 if (INTEL_INFO(dev)->gen >= 8) {
2884 ring->irq_enable_mask =
2885 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2886 ring->irq_get = gen8_ring_get_irq;
2887 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2888 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2889 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2890 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2891 ring->semaphore.signal = gen8_xcs_signal;
2892 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2893 }
abd58f01
BW		 2894 } else {
2895 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2896 ring->irq_get = gen6_ring_get_irq;
2897 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2898 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2899 if (i915_semaphore_is_enabled(dev)) {
2900 ring->semaphore.signal = gen6_signal;
2901 ring->semaphore.sync_to = gen6_ring_sync;
2902 /*
2903 * The current semaphore is only applied on pre-gen8
2904 * platform. And there is no VCS2 ring on the pre-gen8
2905 * platform. So the semaphore between BCS and VCS2 is
2906 * initialized as INVALID. Gen8 will initialize the
2907 * sema between BCS and VCS2 later.
2908 */
2909 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2910 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2911 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2912 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2913 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2914 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2915 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2916 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2917 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2918 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2919 }
abd58f01 2920 }
ecfe00d8 2921 ring->init_hw = init_ring_common;
549f7365 2922
1ec14ad3 2923 return intel_init_ring_buffer(dev, ring);
549f7365 2924}
a7b9761d 2925
9a8a2213
BW		 2926int intel_init_vebox_ring_buffer(struct drm_device *dev)
2927{
4640c4ff 2928 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2929 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2930
2931 ring->name = "video enhancement ring";
2932 ring->id = VECS;
2933
2934 ring->mmio_base = VEBOX_RING_BASE;
2935 ring->write_tail = ring_write_tail;
2936 ring->flush = gen6_ring_flush;
2937 ring->add_request = gen6_add_request;
2938 ring->get_seqno = gen6_ring_get_seqno;
2939 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2940
2941 if (INTEL_INFO(dev)->gen >= 8) {
2942 ring->irq_enable_mask =
40c499f9 2943 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2944 ring->irq_get = gen8_ring_get_irq;
2945 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2946 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2947 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2948 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2949 ring->semaphore.signal = gen8_xcs_signal;
2950 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2951 }
abd58f01
BW		 2952 } else {
2953 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2954 ring->irq_get = hsw_vebox_get_irq;
2955 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2956 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2957 if (i915_semaphore_is_enabled(dev)) {
2958 ring->semaphore.sync_to = gen6_ring_sync;
2959 ring->semaphore.signal = gen6_signal;
2960 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2961 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2962 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2963 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2964 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2965 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2966 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2967 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2968 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2969 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2970 }
abd58f01 2971 }
ecfe00d8 2972 ring->init_hw = init_ring_common;
9a8a2213
BW		 2973
2974 return intel_init_ring_buffer(dev, ring);
2975}
2976
a7b9761d 2977int
4866d729 2978intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2979{
4866d729 2980 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2981 int ret;
2982
2983 if (!ring->gpu_caches_dirty)
2984 return 0;
2985
a84c3ae1 2986 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2987 if (ret)
2988 return ret;
2989
a84c3ae1 2990 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2991
2992 ring->gpu_caches_dirty = false;
2993 return 0;
2994}
2995
2996int
2f20055d 2997intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2998{
2f20055d 2999 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 3000 uint32_t flush_domains;
3001 int ret;
3002
3003 flush_domains = 0;
3004 if (ring->gpu_caches_dirty)
3005 flush_domains = I915_GEM_GPU_DOMAINS;
3006
a84c3ae1 3007 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3008 if (ret)
3009 return ret;
3010
a84c3ae1 3011 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3012
3013 ring->gpu_caches_dirty = false;
3014 return 0;
3015}
e3efda49
CW		 3016
3017void
a4872ba6 3018intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 3019{
3020 int ret;
3021
3022 if (!intel_ring_initialized(ring))
3023 return;
3024
3025 ret = intel_ring_idle(ring);
3026 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3027 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3028 ring->name, ret);
3029
3030 stop_ring(ring);
3031}
Linux kernel - Deliverables
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