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drm/i915: Make vlv and chv forcewake put generic.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 382
add284a3
CW		 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
f3987631
PZ		 385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
b9e1faa7 397 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
9688ecad 401 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
4772eaeb
PZ		 404 return 0;
405}
406
884ceace
KG		 407static int
408gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410{
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426}
427
a5f3d68e 428static int
a4872ba6 429gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 430 u32 invalidate_domains, u32 flush_domains)
431{
432 u32 flags = 0;
18393f63 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 434 int ret;
a5f3d68e
BW		 435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
a5f3d68e
BW		 459 }
460
c5ad011d
RV		 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
a5f3d68e
BW		 469}
470
a4872ba6 471static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 472 u32 value)
d46eefa2 473{
4640c4ff 474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 475 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 476}
477
a4872ba6 478u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 479{
4640c4ff 480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 481 u64 acthd;
8187a2b7 482
50877445
CW		 483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
8187a2b7
ZN		 492}
493
a4872ba6 494static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503}
504
a4872ba6 505static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 506{
9991ae78 507 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 508
9991ae78
CW		 509 if (!IS_GEN2(ring->dev)) {
510 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 511 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
512 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 513 /* Sometimes we observe that the idle flag is not
514 * set even though the ring is empty. So double
515 * check before giving up.
516 */
517 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
518 return false;
9991ae78
CW		 519 }
520 }
b7884eb4 521
7f2ab699 522 I915_WRITE_CTL(ring, 0);
570ef608 523 I915_WRITE_HEAD(ring, 0);
78501eac 524 ring->write_tail(ring, 0);
8187a2b7 525
9991ae78
CW		 526 if (!IS_GEN2(ring->dev)) {
527 (void)I915_READ_CTL(ring);
528 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
529 }
a51435a3 530
9991ae78
CW		 531 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
532}
8187a2b7 533
a4872ba6 534static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 535{
536 struct drm_device *dev = ring->dev;
537 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 538 struct intel_ringbuffer *ringbuf = ring->buffer;
539 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 540 int ret = 0;
541
542 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
543
544 if (!stop_ring(ring)) {
545 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 546 DRM_DEBUG_KMS("%s head not reset to zero "
547 "ctl %08x head %08x tail %08x start %08x\n",
548 ring->name,
549 I915_READ_CTL(ring),
550 I915_READ_HEAD(ring),
551 I915_READ_TAIL(ring),
552 I915_READ_START(ring));
8187a2b7 553
9991ae78 554 if (!stop_ring(ring)) {
6fd0d56e
CW		 555 DRM_ERROR("failed to set %s head to zero "
556 "ctl %08x head %08x tail %08x start %08x\n",
557 ring->name,
558 I915_READ_CTL(ring),
559 I915_READ_HEAD(ring),
560 I915_READ_TAIL(ring),
561 I915_READ_START(ring));
9991ae78
CW		 562 ret = -EIO;
563 goto out;
6fd0d56e 564 }
8187a2b7
ZN		 565 }
566
9991ae78
CW		 567 if (I915_NEED_GFX_HWS(dev))
568 intel_ring_setup_status_page(ring);
569 else
570 ring_setup_phys_status_page(ring);
571
ece4a17d
JK		 572 /* Enforce ordering by reading HEAD register back */
573 I915_READ_HEAD(ring);
574
0d8957c8
DV		 575 /* Initialize the ring. This must happen _after_ we've cleared the ring
576 * registers with the above sequence (the readback of the HEAD registers
577 * also enforces ordering), otherwise the hw might lose the new ring
578 * register values. */
f343c5f6 579 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 580
581 /* WaClearRingBufHeadRegAtInit:ctg,elk */
582 if (I915_READ_HEAD(ring))
583 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
584 ring->name, I915_READ_HEAD(ring));
585 I915_WRITE_HEAD(ring, 0);
586 (void)I915_READ_HEAD(ring);
587
7f2ab699 588 I915_WRITE_CTL(ring,
93b0a4e0 589 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 590 | RING_VALID);
8187a2b7 591
8187a2b7 592 /* If the head is still not zero, the ring is dead */
f01db988 593 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 594 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 595 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 596 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 597 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
598 ring->name,
599 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
600 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
601 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 602 ret = -EIO;
603 goto out;
8187a2b7
ZN		 604 }
605
ebd0fd4b 606 ringbuf->last_retired_head = -1;
5c6c6003
CW		 607 ringbuf->head = I915_READ_HEAD(ring);
608 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 609 intel_ring_update_space(ringbuf);
1ec14ad3 610
50f018df
CW		 611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
612
b7884eb4 613out:
c8d9a590 614 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 615
616 return ret;
8187a2b7
ZN		 617}
618
9b1136d5
OM		 619void
620intel_fini_pipe_control(struct intel_engine_cs *ring)
621{
622 struct drm_device *dev = ring->dev;
623
624 if (ring->scratch.obj == NULL)
625 return;
626
627 if (INTEL_INFO(dev)->gen >= 5) {
628 kunmap(sg_page(ring->scratch.obj->pages->sgl));
629 i915_gem_object_ggtt_unpin(ring->scratch.obj);
630 }
631
632 drm_gem_object_unreference(&ring->scratch.obj->base);
633 ring->scratch.obj = NULL;
634}
635
636int
637intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 638{
c6df541c
CW		 639 int ret;
640
bfc882b4 641 WARN_ON(ring->scratch.obj);
c6df541c 642
0d1aacac
CW		 643 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
644 if (ring->scratch.obj == NULL) {
c6df541c
CW		 645 DRM_ERROR("Failed to allocate seqno page\n");
646 ret = -ENOMEM;
647 goto err;
648 }
e4ffd173 649
a9cc726c
DV		 650 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
651 if (ret)
652 goto err_unref;
c6df541c 653
1ec9e26d 654 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 655 if (ret)
656 goto err_unref;
657
0d1aacac
CW		 658 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
659 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
660 if (ring->scratch.cpu_page == NULL) {
56b085a0 661 ret = -ENOMEM;
c6df541c 662 goto err_unpin;
56b085a0 663 }
c6df541c 664
2b1086cc 665 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 666 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 667 return 0;
668
669err_unpin:
d7f46fc4 670 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 671err_unref:
0d1aacac 672 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 673err:
c6df541c
CW		 674 return ret;
675}
676
771b9a53
MT		 677static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
678 struct intel_context *ctx)
86d7f238 679{
7225342a 680 int ret, i;
888b5995
AS		 681 struct drm_device *dev = ring->dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 683 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 684
e6c1abb7 685 if (WARN_ON_ONCE(w->count == 0))
7225342a 686 return 0;
888b5995 687
7225342a
MK		 688 ring->gpu_caches_dirty = true;
689 ret = intel_ring_flush_all_caches(ring);
690 if (ret)
691 return ret;
888b5995 692
22a916aa 693 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 694 if (ret)
695 return ret;
696
22a916aa 697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 698 for (i = 0; i < w->count; i++) {
7225342a
MK		 699 intel_ring_emit(ring, w->reg[i].addr);
700 intel_ring_emit(ring, w->reg[i].value);
701 }
22a916aa 702 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 703
704 intel_ring_advance(ring);
705
706 ring->gpu_caches_dirty = true;
707 ret = intel_ring_flush_all_caches(ring);
708 if (ret)
709 return ret;
888b5995 710
7225342a 711 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 712
7225342a 713 return 0;
86d7f238
AS		 714}
715
8f0e2b9d
DV		 716static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
717 struct intel_context *ctx)
718{
719 int ret;
720
721 ret = intel_ring_workarounds_emit(ring, ctx);
722 if (ret != 0)
723 return ret;
724
725 ret = i915_gem_render_state_init(ring);
726 if (ret)
727 DRM_ERROR("init render state: %d\n", ret);
728
729 return ret;
730}
731
7225342a 732static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 733 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 734{
735 const u32 idx = dev_priv->workarounds.count;
736
737 if (WARN_ON(idx >= I915_MAX_WA_REGS))
738 return -ENOSPC;
739
740 dev_priv->workarounds.reg[idx].addr = addr;
741 dev_priv->workarounds.reg[idx].value = val;
742 dev_priv->workarounds.reg[idx].mask = mask;
743
744 dev_priv->workarounds.count++;
745
746 return 0;
86d7f238
AS		 747}
748
cf4b0de6
DL		 749#define WA_REG(addr, mask, val) { \
750 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 751 if (r) \
752 return r; \
753 }
754
755#define WA_SET_BIT_MASKED(addr, mask) \
26459343 756 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 757
758#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 759 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 760
98533251 761#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 762 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 763
cf4b0de6
DL		 764#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
765#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 766
cf4b0de6 767#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 768
00e1e623 769static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 770{
888b5995
AS		 771 struct drm_device *dev = ring->dev;
772 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 773
86d7f238 774 /* WaDisablePartialInstShootdown:bdw */
101b376d 775 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 776 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
777 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
778 STALL_DOP_GATING_DISABLE);
86d7f238 779
101b376d 780 /* WaDisableDopClockGating:bdw */
7225342a
MK		 781 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
782 DOP_CLOCK_GATING_DISABLE);
86d7f238 783
7225342a
MK		 784 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
785 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 786
787 /* Use Force Non-Coherent whenever executing a 3D context. This is a
788 * workaround for for a possible hang in the unlikely event a TLB
789 * invalidation occurs during a PSD flush.
790 */
1a252058 791 /* WaForceEnableNonCoherent:bdw */
f3f32360 792 /* WaHdcDisableFetchWhenMasked:bdw */
da09654d 793 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
7225342a
MK		 794 WA_SET_BIT_MASKED(HDC_CHICKEN0,
795 HDC_FORCE_NON_COHERENT |
f3f32360 796 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
7225342a 797 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 798
2701fc43
KG		 799 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
800 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
801 * polygons in the same 8x4 pixel/sample area to be processed without
802 * stalling waiting for the earlier ones to write to Hierarchical Z
803 * buffer."
804 *
805 * This optimization is off by default for Broadwell; turn it on.
806 */
807 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
808
86d7f238 809 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 810 WA_SET_BIT_MASKED(CACHE_MODE_1,
811 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 812
813 /*
814 * BSpec recommends 8x4 when MSAA is used,
815 * however in practice 16x4 seems fastest.
816 *
817 * Note that PS/WM thread counts depend on the WIZ hashing
818 * disable bit, which we don't touch here, but it's good
819 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
820 */
98533251
DL		 821 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
822 GEN6_WIZ_HASHING_MASK,
823 GEN6_WIZ_HASHING_16x4);
888b5995 824
86d7f238
AS		 825 return 0;
826}
827
00e1e623
VS		 828static int chv_init_workarounds(struct intel_engine_cs *ring)
829{
00e1e623
VS		 830 struct drm_device *dev = ring->dev;
831 struct drm_i915_private *dev_priv = dev->dev_private;
832
00e1e623 833 /* WaDisablePartialInstShootdown:chv */
00e1e623 834 /* WaDisableThreadStallDopClockGating:chv */
7225342a 835 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 836 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
837 STALL_DOP_GATING_DISABLE);
00e1e623 838
95289009
AS		 839 /* Use Force Non-Coherent whenever executing a 3D context. This is a
840 * workaround for a possible hang in the unlikely event a TLB
841 * invalidation occurs during a PSD flush.
842 */
843 /* WaForceEnableNonCoherent:chv */
844 /* WaHdcDisableFetchWhenMasked:chv */
845 WA_SET_BIT_MASKED(HDC_CHICKEN0,
846 HDC_FORCE_NON_COHERENT |
847 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
848
973a5b06
KG		 849 /* According to the CACHE_MODE_0 default value documentation, some
850 * CHV platforms disable this optimization by default. Turn it on.
851 */
852 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
853
d60de81d
KG		 854 /* Improve HiZ throughput on CHV. */
855 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
856
7225342a
MK		 857 return 0;
858}
859
771b9a53 860int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 861{
862 struct drm_device *dev = ring->dev;
863 struct drm_i915_private *dev_priv = dev->dev_private;
864
865 WARN_ON(ring->id != RCS);
866
867 dev_priv->workarounds.count = 0;
868
869 if (IS_BROADWELL(dev))
870 return bdw_init_workarounds(ring);
871
872 if (IS_CHERRYVIEW(dev))
873 return chv_init_workarounds(ring);
00e1e623
VS		 874
875 return 0;
876}
877
a4872ba6 878static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 879{
78501eac 880 struct drm_device *dev = ring->dev;
1ec14ad3 881 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 882 int ret = init_ring_common(ring);
9c33baa6
KZ		 883 if (ret)
884 return ret;
a69ffdbf 885
61a563a2
AG		 886 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
887 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 888 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 889
890 /* We need to disable the AsyncFlip performance optimisations in order
891 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
892 * programmed to '1' on all products.
8693a824 893 *
b3f797ac 894 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 895 */
fbdcb068 896 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 897 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
898
f05bb0c7 899 /* Required for the hardware to program scanline values for waiting */
01fa0302 900 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 901 if (INTEL_INFO(dev)->gen == 6)
902 I915_WRITE(GFX_MODE,
aa83e30d 903 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 904
01fa0302 905 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 906 if (IS_GEN7(dev))
907 I915_WRITE(GFX_MODE_GEN7,
01fa0302 908 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 909 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 910
5e13a0c5 911 if (IS_GEN6(dev)) {
3a69ddd6
KG		 912 /* From the Sandybridge PRM, volume 1 part 3, page 24:
913 * "If this bit is set, STCunit will have LRA as replacement
914 * policy. [...] This bit must be reset. LRA replacement
915 * policy is not supported."
916 */
917 I915_WRITE(CACHE_MODE_0,
5e13a0c5 918 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 919 }
920
6b26c86d
DV		 921 if (INTEL_INFO(dev)->gen >= 6)
922 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 923
040d2baa 924 if (HAS_L3_DPF(dev))
35a85ac6 925 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 926
7225342a 927 return init_workarounds_ring(ring);
8187a2b7
ZN		 928}
929
a4872ba6 930static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 931{
b45305fc 932 struct drm_device *dev = ring->dev;
3e78998a
BW		 933 struct drm_i915_private *dev_priv = dev->dev_private;
934
935 if (dev_priv->semaphore_obj) {
936 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
937 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
938 dev_priv->semaphore_obj = NULL;
939 }
b45305fc 940
9b1136d5 941 intel_fini_pipe_control(ring);
c6df541c
CW		 942}
943
3e78998a
BW		 944static int gen8_rcs_signal(struct intel_engine_cs *signaller,
945 unsigned int num_dwords)
946{
947#define MBOX_UPDATE_DWORDS 8
948 struct drm_device *dev = signaller->dev;
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 struct intel_engine_cs *waiter;
951 int i, ret, num_rings;
952
953 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
954 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
955#undef MBOX_UPDATE_DWORDS
956
957 ret = intel_ring_begin(signaller, num_dwords);
958 if (ret)
959 return ret;
960
961 for_each_ring(waiter, dev_priv, i) {
6259cead 962 u32 seqno;
3e78998a
BW		 963 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
964 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
965 continue;
966
6259cead
JH		 967 seqno = i915_gem_request_get_seqno(
968 signaller->outstanding_lazy_request);
3e78998a
BW		 969 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
970 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
971 PIPE_CONTROL_QW_WRITE |
972 PIPE_CONTROL_FLUSH_ENABLE);
973 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
974 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 975 intel_ring_emit(signaller, seqno);
3e78998a
BW		 976 intel_ring_emit(signaller, 0);
977 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
978 MI_SEMAPHORE_TARGET(waiter->id));
979 intel_ring_emit(signaller, 0);
980 }
981
982 return 0;
983}
984
985static int gen8_xcs_signal(struct intel_engine_cs *signaller,
986 unsigned int num_dwords)
987{
988#define MBOX_UPDATE_DWORDS 6
989 struct drm_device *dev = signaller->dev;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 struct intel_engine_cs *waiter;
992 int i, ret, num_rings;
993
994 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
995 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
996#undef MBOX_UPDATE_DWORDS
997
998 ret = intel_ring_begin(signaller, num_dwords);
999 if (ret)
1000 return ret;
1001
1002 for_each_ring(waiter, dev_priv, i) {
6259cead 1003 u32 seqno;
3e78998a
BW		 1004 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1005 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1006 continue;
1007
6259cead
JH		 1008 seqno = i915_gem_request_get_seqno(
1009 signaller->outstanding_lazy_request);
3e78998a
BW		 1010 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1011 MI_FLUSH_DW_OP_STOREDW);
1012 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1013 MI_FLUSH_DW_USE_GTT);
1014 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1015 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1016 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1017 MI_SEMAPHORE_TARGET(waiter->id));
1018 intel_ring_emit(signaller, 0);
1019 }
1020
1021 return 0;
1022}
1023
a4872ba6 1024static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1025 unsigned int num_dwords)
1ec14ad3 1026{
024a43e1
BW		 1027 struct drm_device *dev = signaller->dev;
1028 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1029 struct intel_engine_cs *useless;
a1444b79 1030 int i, ret, num_rings;
78325f2d 1031
a1444b79
BW		 1032#define MBOX_UPDATE_DWORDS 3
1033 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1034 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1035#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1036
1037 ret = intel_ring_begin(signaller, num_dwords);
1038 if (ret)
1039 return ret;
024a43e1 1040
78325f2d
BW		 1041 for_each_ring(useless, dev_priv, i) {
1042 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1043 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1044 u32 seqno = i915_gem_request_get_seqno(
1045 signaller->outstanding_lazy_request);
78325f2d
BW		 1046 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1047 intel_ring_emit(signaller, mbox_reg);
6259cead 1048 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1049 }
1050 }
024a43e1 1051
a1444b79
BW		 1052 /* If num_dwords was rounded, make sure the tail pointer is correct */
1053 if (num_rings % 2 == 0)
1054 intel_ring_emit(signaller, MI_NOOP);
1055
024a43e1 1056 return 0;
1ec14ad3
CW		 1057}
1058
c8c99b0f
BW		 1059/**
1060 * gen6_add_request - Update the semaphore mailbox registers
1061 *
1062 * @ring - ring that is adding a request
1063 * @seqno - return seqno stuck into the ring
1064 *
1065 * Update the mailbox registers in the *other* rings with the current seqno.
1066 * This acts like a signal in the canonical semaphore.
1067 */
1ec14ad3 1068static int
a4872ba6 1069gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1070{
024a43e1 1071 int ret;
52ed2325 1072
707d9cf9
BW		 1073 if (ring->semaphore.signal)
1074 ret = ring->semaphore.signal(ring, 4);
1075 else
1076 ret = intel_ring_begin(ring, 4);
1077
1ec14ad3
CW		 1078 if (ret)
1079 return ret;
1080
1ec14ad3
CW		 1081 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1082 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1083 intel_ring_emit(ring,
1084 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1085 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1086 __intel_ring_advance(ring);
1ec14ad3 1087
1ec14ad3
CW		 1088 return 0;
1089}
1090
f72b3435
MK		 1091static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1092 u32 seqno)
1093{
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 return dev_priv->last_seqno < seqno;
1096}
1097
c8c99b0f
BW		 1098/**
1099 * intel_ring_sync - sync the waiter to the signaller on seqno
1100 *
1101 * @waiter - ring that is waiting
1102 * @signaller - ring which has, or will signal
1103 * @seqno - seqno which the waiter will block on
1104 */
5ee426ca
BW		 1105
1106static int
1107gen8_ring_sync(struct intel_engine_cs *waiter,
1108 struct intel_engine_cs *signaller,
1109 u32 seqno)
1110{
1111 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1112 int ret;
1113
1114 ret = intel_ring_begin(waiter, 4);
1115 if (ret)
1116 return ret;
1117
1118 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1119 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1120 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1121 MI_SEMAPHORE_SAD_GTE_SDD);
1122 intel_ring_emit(waiter, seqno);
1123 intel_ring_emit(waiter,
1124 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1125 intel_ring_emit(waiter,
1126 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1127 intel_ring_advance(waiter);
1128 return 0;
1129}
1130
c8c99b0f 1131static int
a4872ba6
OM		 1132gen6_ring_sync(struct intel_engine_cs *waiter,
1133 struct intel_engine_cs *signaller,
686cb5f9 1134 u32 seqno)
1ec14ad3 1135{
c8c99b0f
BW		 1136 u32 dw1 = MI_SEMAPHORE_MBOX |
1137 MI_SEMAPHORE_COMPARE |
1138 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1139 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1140 int ret;
1ec14ad3 1141
1500f7ea
BW		 1142 /* Throughout all of the GEM code, seqno passed implies our current
1143 * seqno is >= the last seqno executed. However for hardware the
1144 * comparison is strictly greater than.
1145 */
1146 seqno -= 1;
1147
ebc348b2 1148 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1149
c8c99b0f 1150 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1151 if (ret)
1152 return ret;
1153
f72b3435
MK		 1154 /* If seqno wrap happened, omit the wait with no-ops */
1155 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1156 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1157 intel_ring_emit(waiter, seqno);
1158 intel_ring_emit(waiter, 0);
1159 intel_ring_emit(waiter, MI_NOOP);
1160 } else {
1161 intel_ring_emit(waiter, MI_NOOP);
1162 intel_ring_emit(waiter, MI_NOOP);
1163 intel_ring_emit(waiter, MI_NOOP);
1164 intel_ring_emit(waiter, MI_NOOP);
1165 }
c8c99b0f 1166 intel_ring_advance(waiter);
1ec14ad3
CW		 1167
1168 return 0;
1169}
1170
c6df541c
CW		 1171#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1172do { \
fcbc34e4
KG		 1173 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1174 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1175 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1176 intel_ring_emit(ring__, 0); \
1177 intel_ring_emit(ring__, 0); \
1178} while (0)
1179
1180static int
a4872ba6 1181pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1182{
18393f63 1183 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1184 int ret;
1185
1186 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1187 * incoherent with writes to memory, i.e. completely fubar,
1188 * so we need to use PIPE_NOTIFY instead.
1189 *
1190 * However, we also need to workaround the qword write
1191 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1192 * memory before requesting an interrupt.
1193 */
1194 ret = intel_ring_begin(ring, 32);
1195 if (ret)
1196 return ret;
1197
fcbc34e4 1198 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1199 PIPE_CONTROL_WRITE_FLUSH |
1200 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1201 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1202 intel_ring_emit(ring,
1203 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1204 intel_ring_emit(ring, 0);
1205 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1206 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1207 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1208 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1209 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1210 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1211 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1212 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1213 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1214 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1215 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1216
fcbc34e4 1217 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1218 PIPE_CONTROL_WRITE_FLUSH |
1219 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1220 PIPE_CONTROL_NOTIFY);
0d1aacac 1221 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1222 intel_ring_emit(ring,
1223 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1224 intel_ring_emit(ring, 0);
09246732 1225 __intel_ring_advance(ring);
c6df541c 1226
c6df541c
CW		 1227 return 0;
1228}
1229
4cd53c0c 1230static u32
a4872ba6 1231gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1232{
4cd53c0c
DV		 1233 /* Workaround to force correct ordering between irq and seqno writes on
1234 * ivb (and maybe also on snb) by reading from a CS register (like
1235 * ACTHD) before reading the status page. */
50877445
CW		 1236 if (!lazy_coherency) {
1237 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1238 POSTING_READ(RING_ACTHD(ring->mmio_base));
1239 }
1240
4cd53c0c
DV		 1241 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1242}
1243
8187a2b7 1244static u32
a4872ba6 1245ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1246{
1ec14ad3
CW		 1247 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1248}
1249
b70ec5bf 1250static void
a4872ba6 1251ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1252{
1253 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1254}
1255
c6df541c 1256static u32
a4872ba6 1257pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1258{
0d1aacac 1259 return ring->scratch.cpu_page[0];
c6df541c
CW		 1260}
1261
b70ec5bf 1262static void
a4872ba6 1263pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1264{
0d1aacac 1265 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1266}
1267
e48d8634 1268static bool
a4872ba6 1269gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1270{
1271 struct drm_device *dev = ring->dev;
4640c4ff 1272 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1273 unsigned long flags;
e48d8634 1274
7cd512f1 1275 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1276 return false;
1277
7338aefa 1278 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1279 if (ring->irq_refcount++ == 0)
480c8033 1280 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1281 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1282
1283 return true;
1284}
1285
1286static void
a4872ba6 1287gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1288{
1289 struct drm_device *dev = ring->dev;
4640c4ff 1290 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1291 unsigned long flags;
e48d8634 1292
7338aefa 1293 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1294 if (--ring->irq_refcount == 0)
480c8033 1295 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1296 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1297}
1298
b13c2b96 1299static bool
a4872ba6 1300i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1301{
78501eac 1302 struct drm_device *dev = ring->dev;
4640c4ff 1303 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1304 unsigned long flags;
62fdfeaf 1305
7cd512f1 1306 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1307 return false;
1308
7338aefa 1309 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1310 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1311 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1312 I915_WRITE(IMR, dev_priv->irq_mask);
1313 POSTING_READ(IMR);
1314 }
7338aefa 1315 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1316
1317 return true;
62fdfeaf
EA		 1318}
1319
8187a2b7 1320static void
a4872ba6 1321i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1322{
78501eac 1323 struct drm_device *dev = ring->dev;
4640c4ff 1324 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1325 unsigned long flags;
62fdfeaf 1326
7338aefa 1327 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1328 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1329 dev_priv->irq_mask |= ring->irq_enable_mask;
1330 I915_WRITE(IMR, dev_priv->irq_mask);
1331 POSTING_READ(IMR);
1332 }
7338aefa 1333 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1334}
1335
c2798b19 1336static bool
a4872ba6 1337i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1338{
1339 struct drm_device *dev = ring->dev;
4640c4ff 1340 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1341 unsigned long flags;
c2798b19 1342
7cd512f1 1343 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1344 return false;
1345
7338aefa 1346 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1347 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1348 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1349 I915_WRITE16(IMR, dev_priv->irq_mask);
1350 POSTING_READ16(IMR);
1351 }
7338aefa 1352 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1353
1354 return true;
1355}
1356
1357static void
a4872ba6 1358i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1359{
1360 struct drm_device *dev = ring->dev;
4640c4ff 1361 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1362 unsigned long flags;
c2798b19 1363
7338aefa 1364 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1365 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1366 dev_priv->irq_mask |= ring->irq_enable_mask;
1367 I915_WRITE16(IMR, dev_priv->irq_mask);
1368 POSTING_READ16(IMR);
1369 }
7338aefa 1370 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1371}
1372
a4872ba6 1373void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1374{
4593010b 1375 struct drm_device *dev = ring->dev;
4640c4ff 1376 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1377 u32 mmio = 0;
1378
1379 /* The ring status page addresses are no longer next to the rest of
1380 * the ring registers as of gen7.
1381 */
1382 if (IS_GEN7(dev)) {
1383 switch (ring->id) {
96154f2f 1384 case RCS:
4593010b
EA		 1385 mmio = RENDER_HWS_PGA_GEN7;
1386 break;
96154f2f 1387 case BCS:
4593010b
EA		 1388 mmio = BLT_HWS_PGA_GEN7;
1389 break;
77fe2ff3
ZY		 1390 /*
1391 * VCS2 actually doesn't exist on Gen7. Only shut up
1392 * gcc switch check warning
1393 */
1394 case VCS2:
96154f2f 1395 case VCS:
4593010b
EA		 1396 mmio = BSD_HWS_PGA_GEN7;
1397 break;
4a3dd19d 1398 case VECS:
9a8a2213
BW		 1399 mmio = VEBOX_HWS_PGA_GEN7;
1400 break;
4593010b
EA		 1401 }
1402 } else if (IS_GEN6(ring->dev)) {
1403 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1404 } else {
eb0d4b75 1405 /* XXX: gen8 returns to sanity */
4593010b
EA		 1406 mmio = RING_HWS_PGA(ring->mmio_base);
1407 }
1408
78501eac
CW		 1409 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1410 POSTING_READ(mmio);
884020bf 1411
dc616b89
DL		 1412 /*
1413 * Flush the TLB for this page
1414 *
1415 * FIXME: These two bits have disappeared on gen8, so a question
1416 * arises: do we still need this and if so how should we go about
1417 * invalidating the TLB?
1418 */
1419 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1420 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1421
1422 /* ring should be idle before issuing a sync flush*/
1423 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1424
884020bf
CW		 1425 I915_WRITE(reg,
1426 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1427 INSTPM_SYNC_FLUSH));
1428 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1429 1000))
1430 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1431 ring->name);
1432 }
8187a2b7
ZN		 1433}
1434
b72f3acb 1435static int
a4872ba6 1436bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1437 u32 invalidate_domains,
1438 u32 flush_domains)
d1b851fc 1439{
b72f3acb
CW		 1440 int ret;
1441
b72f3acb
CW		 1442 ret = intel_ring_begin(ring, 2);
1443 if (ret)
1444 return ret;
1445
1446 intel_ring_emit(ring, MI_FLUSH);
1447 intel_ring_emit(ring, MI_NOOP);
1448 intel_ring_advance(ring);
1449 return 0;
d1b851fc
ZN		 1450}
1451
3cce469c 1452static int
a4872ba6 1453i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1454{
3cce469c
CW		 1455 int ret;
1456
1457 ret = intel_ring_begin(ring, 4);
1458 if (ret)
1459 return ret;
6f392d54 1460
3cce469c
CW		 1461 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1462 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1463 intel_ring_emit(ring,
1464 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1465 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1466 __intel_ring_advance(ring);
d1b851fc 1467
3cce469c 1468 return 0;
d1b851fc
ZN		 1469}
1470
0f46832f 1471static bool
a4872ba6 1472gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1473{
1474 struct drm_device *dev = ring->dev;
4640c4ff 1475 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1476 unsigned long flags;
0f46832f 1477
7cd512f1
DV		 1478 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1479 return false;
0f46832f 1480
7338aefa 1481 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1482 if (ring->irq_refcount++ == 0) {
040d2baa 1483 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1484 I915_WRITE_IMR(ring,
1485 ~(ring->irq_enable_mask |
35a85ac6 1486 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1487 else
1488 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1489 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1490 }
7338aefa 1491 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1492
1493 return true;
1494}
1495
1496static void
a4872ba6 1497gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1498{
1499 struct drm_device *dev = ring->dev;
4640c4ff 1500 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1501 unsigned long flags;
0f46832f 1502
7338aefa 1503 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1504 if (--ring->irq_refcount == 0) {
040d2baa 1505 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1506 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1507 else
1508 I915_WRITE_IMR(ring, ~0);
480c8033 1509 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1510 }
7338aefa 1511 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1512}
1513
a19d2933 1514static bool
a4872ba6 1515hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1516{
1517 struct drm_device *dev = ring->dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 unsigned long flags;
1520
7cd512f1 1521 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1522 return false;
1523
59cdb63d 1524 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1525 if (ring->irq_refcount++ == 0) {
a19d2933 1526 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1527 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1528 }
59cdb63d 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1530
1531 return true;
1532}
1533
1534static void
a4872ba6 1535hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1536{
1537 struct drm_device *dev = ring->dev;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 unsigned long flags;
1540
59cdb63d 1541 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1542 if (--ring->irq_refcount == 0) {
a19d2933 1543 I915_WRITE_IMR(ring, ~0);
480c8033 1544 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1545 }
59cdb63d 1546 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1547}
1548
abd58f01 1549static bool
a4872ba6 1550gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1551{
1552 struct drm_device *dev = ring->dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 unsigned long flags;
1555
7cd512f1 1556 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1557 return false;
1558
1559 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1560 if (ring->irq_refcount++ == 0) {
1561 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1562 I915_WRITE_IMR(ring,
1563 ~(ring->irq_enable_mask |
1564 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1565 } else {
1566 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1567 }
1568 POSTING_READ(RING_IMR(ring->mmio_base));
1569 }
1570 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1571
1572 return true;
1573}
1574
1575static void
a4872ba6 1576gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1577{
1578 struct drm_device *dev = ring->dev;
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1583 if (--ring->irq_refcount == 0) {
1584 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1585 I915_WRITE_IMR(ring,
1586 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1587 } else {
1588 I915_WRITE_IMR(ring, ~0);
1589 }
1590 POSTING_READ(RING_IMR(ring->mmio_base));
1591 }
1592 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1593}
1594
d1b851fc 1595static int
a4872ba6 1596i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1597 u64 offset, u32 length,
d7d4eedd 1598 unsigned flags)
d1b851fc 1599{
e1f99ce6 1600 int ret;
78501eac 1601
e1f99ce6
CW		 1602 ret = intel_ring_begin(ring, 2);
1603 if (ret)
1604 return ret;
1605
78501eac 1606 intel_ring_emit(ring,
65f56876
CW		 1607 MI_BATCH_BUFFER_START |
1608 MI_BATCH_GTT |
d7d4eedd 1609 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1610 intel_ring_emit(ring, offset);
78501eac
CW		 1611 intel_ring_advance(ring);
1612
d1b851fc
ZN		 1613 return 0;
1614}
1615
b45305fc
DV		 1616/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1617#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1618#define I830_TLB_ENTRIES (2)
1619#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1620static int
a4872ba6 1621i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1622 u64 offset, u32 len,
d7d4eedd 1623 unsigned flags)
62fdfeaf 1624{
c4d69da1 1625 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1626 int ret;
62fdfeaf 1627
c4d69da1
CW		 1628 ret = intel_ring_begin(ring, 6);
1629 if (ret)
1630 return ret;
62fdfeaf 1631
c4d69da1
CW		 1632 /* Evict the invalid PTE TLBs */
1633 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1634 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1635 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1636 intel_ring_emit(ring, cs_offset);
1637 intel_ring_emit(ring, 0xdeadbeef);
1638 intel_ring_emit(ring, MI_NOOP);
1639 intel_ring_advance(ring);
b45305fc 1640
c4d69da1 1641 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1642 if (len > I830_BATCH_LIMIT)
1643 return -ENOSPC;
1644
c4d69da1 1645 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1646 if (ret)
1647 return ret;
c4d69da1
CW		 1648
1649 /* Blit the batch (which has now all relocs applied) to the
1650 * stable batch scratch bo area (so that the CS never
1651 * stumbles over its tlb invalidation bug) ...
1652 */
1653 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1654 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1655 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1656 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1657 intel_ring_emit(ring, 4096);
1658 intel_ring_emit(ring, offset);
c4d69da1 1659
b45305fc 1660 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1661 intel_ring_emit(ring, MI_NOOP);
1662 intel_ring_advance(ring);
b45305fc
DV		 1663
1664 /* ... and execute it. */
c4d69da1 1665 offset = cs_offset;
b45305fc 1666 }
e1f99ce6 1667
c4d69da1
CW		 1668 ret = intel_ring_begin(ring, 4);
1669 if (ret)
1670 return ret;
1671
1672 intel_ring_emit(ring, MI_BATCH_BUFFER);
1673 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1674 intel_ring_emit(ring, offset + len - 8);
1675 intel_ring_emit(ring, MI_NOOP);
1676 intel_ring_advance(ring);
1677
fb3256da
DV		 1678 return 0;
1679}
1680
1681static int
a4872ba6 1682i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1683 u64 offset, u32 len,
d7d4eedd 1684 unsigned flags)
fb3256da
DV		 1685{
1686 int ret;
1687
1688 ret = intel_ring_begin(ring, 2);
1689 if (ret)
1690 return ret;
1691
65f56876 1692 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1693 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1694 intel_ring_advance(ring);
62fdfeaf 1695
62fdfeaf
EA		 1696 return 0;
1697}
1698
a4872ba6 1699static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1700{
05394f39 1701 struct drm_i915_gem_object *obj;
62fdfeaf 1702
8187a2b7
ZN		 1703 obj = ring->status_page.obj;
1704 if (obj == NULL)
62fdfeaf 1705 return;
62fdfeaf 1706
9da3da66 1707 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1708 i915_gem_object_ggtt_unpin(obj);
05394f39 1709 drm_gem_object_unreference(&obj->base);
8187a2b7 1710 ring->status_page.obj = NULL;
62fdfeaf
EA		 1711}
1712
a4872ba6 1713static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1714{
05394f39 1715 struct drm_i915_gem_object *obj;
62fdfeaf 1716
e3efda49 1717 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1718 unsigned flags;
e3efda49 1719 int ret;
e4ffd173 1720
e3efda49
CW		 1721 obj = i915_gem_alloc_object(ring->dev, 4096);
1722 if (obj == NULL) {
1723 DRM_ERROR("Failed to allocate status page\n");
1724 return -ENOMEM;
1725 }
62fdfeaf 1726
e3efda49
CW		 1727 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1728 if (ret)
1729 goto err_unref;
1730
1f767e02
CW		 1731 flags = 0;
1732 if (!HAS_LLC(ring->dev))
1733 /* On g33, we cannot place HWS above 256MiB, so
1734 * restrict its pinning to the low mappable arena.
1735 * Though this restriction is not documented for
1736 * gen4, gen5, or byt, they also behave similarly
1737 * and hang if the HWS is placed at the top of the
1738 * GTT. To generalise, it appears that all !llc
1739 * platforms have issues with us placing the HWS
1740 * above the mappable region (even though we never
1741 * actualy map it).
1742 */
1743 flags |= PIN_MAPPABLE;
1744 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1745 if (ret) {
1746err_unref:
1747 drm_gem_object_unreference(&obj->base);
1748 return ret;
1749 }
1750
1751 ring->status_page.obj = obj;
1752 }
62fdfeaf 1753
f343c5f6 1754 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1755 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1756 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1757
8187a2b7
ZN		 1758 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1759 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1760
1761 return 0;
62fdfeaf
EA		 1762}
1763
a4872ba6 1764static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1765{
1766 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1767
1768 if (!dev_priv->status_page_dmah) {
1769 dev_priv->status_page_dmah =
1770 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1771 if (!dev_priv->status_page_dmah)
1772 return -ENOMEM;
1773 }
1774
6b8294a4
CW		 1775 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1776 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1777
1778 return 0;
1779}
1780
7ba717cf 1781void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1782{
2919d291 1783 iounmap(ringbuf->virtual_start);
7ba717cf 1784 ringbuf->virtual_start = NULL;
2919d291 1785 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1786}
1787
1788int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1789 struct intel_ringbuffer *ringbuf)
1790{
1791 struct drm_i915_private *dev_priv = to_i915(dev);
1792 struct drm_i915_gem_object *obj = ringbuf->obj;
1793 int ret;
1794
1795 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1796 if (ret)
1797 return ret;
1798
1799 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1800 if (ret) {
1801 i915_gem_object_ggtt_unpin(obj);
1802 return ret;
1803 }
1804
1805 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1806 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1807 if (ringbuf->virtual_start == NULL) {
1808 i915_gem_object_ggtt_unpin(obj);
1809 return -EINVAL;
1810 }
1811
1812 return 0;
1813}
1814
1815void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1816{
2919d291
OM		 1817 drm_gem_object_unreference(&ringbuf->obj->base);
1818 ringbuf->obj = NULL;
1819}
1820
84c2377f
OM		 1821int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1822 struct intel_ringbuffer *ringbuf)
62fdfeaf 1823{
05394f39 1824 struct drm_i915_gem_object *obj;
62fdfeaf 1825
ebc052e0
CW		 1826 obj = NULL;
1827 if (!HAS_LLC(dev))
93b0a4e0 1828 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1829 if (obj == NULL)
93b0a4e0 1830 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1831 if (obj == NULL)
1832 return -ENOMEM;
8187a2b7 1833
24f3a8cf
AG		 1834 /* mark ring buffers as read-only from GPU side by default */
1835 obj->gt_ro = 1;
1836
93b0a4e0 1837 ringbuf->obj = obj;
e3efda49 1838
7ba717cf 1839 return 0;
e3efda49
CW		 1840}
1841
1842static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1843 struct intel_engine_cs *ring)
e3efda49 1844{
bfc882b4 1845 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1846 int ret;
1847
bfc882b4
DV		 1848 WARN_ON(ring->buffer);
1849
1850 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1851 if (!ringbuf)
1852 return -ENOMEM;
1853 ring->buffer = ringbuf;
8ee14975 1854
e3efda49
CW		 1855 ring->dev = dev;
1856 INIT_LIST_HEAD(&ring->active_list);
1857 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1858 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1859 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1860 ringbuf->ring = ring;
ebc348b2 1861 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1862
1863 init_waitqueue_head(&ring->irq_queue);
1864
1865 if (I915_NEED_GFX_HWS(dev)) {
1866 ret = init_status_page(ring);
1867 if (ret)
8ee14975 1868 goto error;
e3efda49
CW		 1869 } else {
1870 BUG_ON(ring->id != RCS);
1871 ret = init_phys_status_page(ring);
1872 if (ret)
8ee14975 1873 goto error;
e3efda49
CW		 1874 }
1875
bfc882b4 1876 WARN_ON(ringbuf->obj);
7ba717cf 1877
bfc882b4
DV		 1878 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1879 if (ret) {
1880 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1881 ring->name, ret);
1882 goto error;
1883 }
1884
1885 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1886 if (ret) {
1887 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1888 ring->name, ret);
1889 intel_destroy_ringbuffer_obj(ringbuf);
1890 goto error;
e3efda49 1891 }
62fdfeaf 1892
55249baa
CW		 1893 /* Workaround an erratum on the i830 which causes a hang if
1894 * the TAIL pointer points to within the last 2 cachelines
1895 * of the buffer.
1896 */
93b0a4e0 1897 ringbuf->effective_size = ringbuf->size;
e3efda49 1898 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1899 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1900
44e895a8
BV		 1901 ret = i915_cmd_parser_init_ring(ring);
1902 if (ret)
8ee14975
OM		 1903 goto error;
1904
8ee14975 1905 return 0;
351e3db2 1906
8ee14975
OM		 1907error:
1908 kfree(ringbuf);
1909 ring->buffer = NULL;
1910 return ret;
62fdfeaf
EA		 1911}
1912
a4872ba6 1913void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1914{
6402c330
JH		 1915 struct drm_i915_private *dev_priv;
1916 struct intel_ringbuffer *ringbuf;
33626e6a 1917
93b0a4e0 1918 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1919 return;
1920
6402c330
JH		 1921 dev_priv = to_i915(ring->dev);
1922 ringbuf = ring->buffer;
1923
e3efda49 1924 intel_stop_ring_buffer(ring);
de8f0a50 1925 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1926
7ba717cf 1927 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 1928 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 1929 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 1930
8d19215b
ZN		 1931 if (ring->cleanup)
1932 ring->cleanup(ring);
1933
78501eac 1934 cleanup_status_page(ring);
44e895a8
BV		 1935
1936 i915_cmd_parser_fini_ring(ring);
8ee14975 1937
93b0a4e0 1938 kfree(ringbuf);
8ee14975 1939 ring->buffer = NULL;
62fdfeaf
EA		 1940}
1941
a4872ba6 1942static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1943{
93b0a4e0 1944 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1945 struct drm_i915_gem_request *request;
a71d8d94
CW		 1946 int ret;
1947
ebd0fd4b
DG		 1948 if (intel_ring_space(ringbuf) >= n)
1949 return 0;
a71d8d94
CW		 1950
1951 list_for_each_entry(request, &ring->request_list, list) {
72f95afa 1952 if (__intel_ring_space(request->postfix, ringbuf->tail,
82e104cc 1953 ringbuf->size) >= n) {
a71d8d94
CW		 1954 break;
1955 }
a71d8d94
CW		 1956 }
1957
a4b3a571 1958 if (&request->list == &ring->request_list)
a71d8d94
CW		 1959 return -ENOSPC;
1960
a4b3a571 1961 ret = i915_wait_request(request);
a71d8d94
CW		 1962 if (ret)
1963 return ret;
1964
1cf0ba14 1965 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 1966
1967 return 0;
1968}
1969
a4872ba6 1970static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1971{
78501eac 1972 struct drm_device *dev = ring->dev;
cae5852d 1973 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1974 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1975 unsigned long end;
a71d8d94 1976 int ret;
c7dca47b 1977
a71d8d94
CW		 1978 ret = intel_ring_wait_request(ring, n);
1979 if (ret != -ENOSPC)
1980 return ret;
1981
09246732
CW		 1982 /* force the tail write in case we have been skipping them */
1983 __intel_ring_advance(ring);
1984
63ed2cb2
DV		 1985 /* With GEM the hangcheck timer should kick us out of the loop,
1986 * leaving it early runs the risk of corrupting GEM state (due
1987 * to running on almost untested codepaths). But on resume
1988 * timers don't work yet, so prevent a complete hang in that
1989 * case by choosing an insanely large timeout. */
1990 end = jiffies + 60 * HZ;
e6bfaf85 1991
ebd0fd4b 1992 ret = 0;
dcfe0506 1993 trace_i915_ring_wait_begin(ring);
8187a2b7 1994 do {
ebd0fd4b
DG		 1995 if (intel_ring_space(ringbuf) >= n)
1996 break;
93b0a4e0 1997 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 1998 if (intel_ring_space(ringbuf) >= n)
dcfe0506 1999 break;
62fdfeaf 2000
e60a0b10 2001 msleep(1);
d6b2c790 2002
dcfe0506
CW		 2003 if (dev_priv->mm.interruptible && signal_pending(current)) {
2004 ret = -ERESTARTSYS;
2005 break;
2006 }
2007
33196ded
DV		 2008 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2009 dev_priv->mm.interruptible);
d6b2c790 2010 if (ret)
dcfe0506
CW		 2011 break;
2012
2013 if (time_after(jiffies, end)) {
2014 ret = -EBUSY;
2015 break;
2016 }
2017 } while (1);
db53a302 2018 trace_i915_ring_wait_end(ring);
dcfe0506 2019 return ret;
8187a2b7 2020}
62fdfeaf 2021
a4872ba6 2022static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2023{
2024 uint32_t __iomem *virt;
93b0a4e0
OM		 2025 struct intel_ringbuffer *ringbuf = ring->buffer;
2026 int rem = ringbuf->size - ringbuf->tail;
3e960501 2027
93b0a4e0 2028 if (ringbuf->space < rem) {
3e960501
CW		 2029 int ret = ring_wait_for_space(ring, rem);
2030 if (ret)
2031 return ret;
2032 }
2033
93b0a4e0 2034 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2035 rem /= 4;
2036 while (rem--)
2037 iowrite32(MI_NOOP, virt++);
2038
93b0a4e0 2039 ringbuf->tail = 0;
ebd0fd4b 2040 intel_ring_update_space(ringbuf);
3e960501
CW		 2041
2042 return 0;
2043}
2044
a4872ba6 2045int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2046{
a4b3a571 2047 struct drm_i915_gem_request *req;
3e960501
CW		 2048 int ret;
2049
2050 /* We need to add any requests required to flush the objects and ring */
6259cead 2051 if (ring->outstanding_lazy_request) {
9400ae5c 2052 ret = i915_add_request(ring);
3e960501
CW		 2053 if (ret)
2054 return ret;
2055 }
2056
2057 /* Wait upon the last request to be completed */
2058 if (list_empty(&ring->request_list))
2059 return 0;
2060
a4b3a571 2061 req = list_entry(ring->request_list.prev,
3e960501 2062 struct drm_i915_gem_request,
a4b3a571 2063 list);
3e960501 2064
a4b3a571 2065 return i915_wait_request(req);
3e960501
CW		 2066}
2067
9d773091 2068static int
6259cead 2069intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2070{
9eba5d4a
JH		 2071 int ret;
2072 struct drm_i915_gem_request *request;
67e2937b 2073 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2074
6259cead 2075 if (ring->outstanding_lazy_request)
9d773091 2076 return 0;
3c0e234c 2077
aaeb1ba0 2078 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2079 if (request == NULL)
2080 return -ENOMEM;
3c0e234c 2081
abfe262a 2082 kref_init(&request->ref);
ff79e857 2083 request->ring = ring;
67e2937b 2084 request->uniq = dev_private->request_uniq++;
abfe262a 2085
6259cead 2086 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2087 if (ret) {
2088 kfree(request);
2089 return ret;
3c0e234c
CW		 2090 }
2091
6259cead 2092 ring->outstanding_lazy_request = request;
9eba5d4a 2093 return 0;
9d773091
CW		 2094}
2095
a4872ba6 2096static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2097 int bytes)
cbcc80df 2098{
93b0a4e0 2099 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2100 int ret;
2101
93b0a4e0 2102 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2103 ret = intel_wrap_ring_buffer(ring);
2104 if (unlikely(ret))
2105 return ret;
2106 }
2107
93b0a4e0 2108 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2109 ret = ring_wait_for_space(ring, bytes);
2110 if (unlikely(ret))
2111 return ret;
2112 }
2113
cbcc80df
MK		 2114 return 0;
2115}
2116
a4872ba6 2117int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2118 int num_dwords)
8187a2b7 2119{
4640c4ff 2120 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2121 int ret;
78501eac 2122
33196ded
DV		 2123 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2124 dev_priv->mm.interruptible);
de2b9985
DV		 2125 if (ret)
2126 return ret;
21dd3734 2127
304d695c
CW		 2128 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2129 if (ret)
2130 return ret;
2131
9d773091 2132 /* Preallocate the olr before touching the ring */
6259cead 2133 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2134 if (ret)
2135 return ret;
2136
ee1b1e5e 2137 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2138 return 0;
8187a2b7 2139}
78501eac 2140
753b1ad4 2141/* Align the ring tail to a cacheline boundary */
a4872ba6 2142int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2143{
ee1b1e5e 2144 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2145 int ret;
2146
2147 if (num_dwords == 0)
2148 return 0;
2149
18393f63 2150 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2151 ret = intel_ring_begin(ring, num_dwords);
2152 if (ret)
2153 return ret;
2154
2155 while (num_dwords--)
2156 intel_ring_emit(ring, MI_NOOP);
2157
2158 intel_ring_advance(ring);
2159
2160 return 0;
2161}
2162
a4872ba6 2163void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2164{
3b2cc8ab
OM		 2165 struct drm_device *dev = ring->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2167
6259cead 2168 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2169
3b2cc8ab 2170 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2171 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2172 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2173 if (HAS_VEBOX(dev))
5020150b 2174 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2175 }
d97ed339 2176
f7e98ad4 2177 ring->set_seqno(ring, seqno);
92cab734 2178 ring->hangcheck.seqno = seqno;
8187a2b7 2179}
62fdfeaf 2180
a4872ba6 2181static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2182 u32 value)
881f47b6 2183{
4640c4ff 2184 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2185
2186 /* Every tail move must follow the sequence below */
12f55818
CW		 2187
2188 /* Disable notification that the ring is IDLE. The GT
2189 * will then assume that it is busy and bring it out of rc6.
2190 */
0206e353 2191 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2192 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2193
2194 /* Clear the context id. Here be magic! */
2195 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2196
12f55818 2197 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2198 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2199 GEN6_BSD_SLEEP_INDICATOR) == 0,
2200 50))
2201 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2202
12f55818 2203 /* Now that the ring is fully powered up, update the tail */
0206e353 2204 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2205 POSTING_READ(RING_TAIL(ring->mmio_base));
2206
2207 /* Let the ring send IDLE messages to the GT again,
2208 * and so let it sleep to conserve power when idle.
2209 */
0206e353 2210 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2211 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2212}
2213
a4872ba6 2214static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2215 u32 invalidate, u32 flush)
881f47b6 2216{
71a77e07 2217 uint32_t cmd;
b72f3acb
CW		 2218 int ret;
2219
b72f3acb
CW		 2220 ret = intel_ring_begin(ring, 4);
2221 if (ret)
2222 return ret;
2223
71a77e07 2224 cmd = MI_FLUSH_DW;
075b3bba
BW		 2225 if (INTEL_INFO(ring->dev)->gen >= 8)
2226 cmd += 1;
9a289771
JB		 2227 /*
2228 * Bspec vol 1c.5 - video engine command streamer:
2229 * "If ENABLED, all TLBs will be invalidated once the flush
2230 * operation is complete. This bit is only valid when the
2231 * Post-Sync Operation field is a value of 1h or 3h."
2232 */
71a77e07 2233 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2234 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2235 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2236 intel_ring_emit(ring, cmd);
9a289771 2237 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2238 if (INTEL_INFO(ring->dev)->gen >= 8) {
2239 intel_ring_emit(ring, 0); /* upper addr */
2240 intel_ring_emit(ring, 0); /* value */
2241 } else {
2242 intel_ring_emit(ring, 0);
2243 intel_ring_emit(ring, MI_NOOP);
2244 }
b72f3acb
CW		 2245 intel_ring_advance(ring);
2246 return 0;
881f47b6
XH		 2247}
2248
1c7a0623 2249static int
a4872ba6 2250gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2251 u64 offset, u32 len,
1c7a0623
BW		 2252 unsigned flags)
2253{
896ab1a5 2254 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2255 int ret;
2256
2257 ret = intel_ring_begin(ring, 4);
2258 if (ret)
2259 return ret;
2260
2261 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2262 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2263 intel_ring_emit(ring, lower_32_bits(offset));
2264 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2265 intel_ring_emit(ring, MI_NOOP);
2266 intel_ring_advance(ring);
2267
2268 return 0;
2269}
2270
d7d4eedd 2271static int
a4872ba6 2272hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2273 u64 offset, u32 len,
d7d4eedd
CW		 2274 unsigned flags)
2275{
2276 int ret;
2277
2278 ret = intel_ring_begin(ring, 2);
2279 if (ret)
2280 return ret;
2281
2282 intel_ring_emit(ring,
77072258
CW		 2283 MI_BATCH_BUFFER_START |
2284 (flags & I915_DISPATCH_SECURE ?
2285 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2286 /* bit0-7 is the length on GEN6+ */
2287 intel_ring_emit(ring, offset);
2288 intel_ring_advance(ring);
2289
2290 return 0;
2291}
2292
881f47b6 2293static int
a4872ba6 2294gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2295 u64 offset, u32 len,
d7d4eedd 2296 unsigned flags)
881f47b6 2297{
0206e353 2298 int ret;
ab6f8e32 2299
0206e353
AJ		 2300 ret = intel_ring_begin(ring, 2);
2301 if (ret)
2302 return ret;
e1f99ce6 2303
d7d4eedd
CW		 2304 intel_ring_emit(ring,
2305 MI_BATCH_BUFFER_START |
2306 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2307 /* bit0-7 is the length on GEN6+ */
2308 intel_ring_emit(ring, offset);
2309 intel_ring_advance(ring);
ab6f8e32 2310
0206e353 2311 return 0;
881f47b6
XH		 2312}
2313
549f7365
CW		 2314/* Blitter support (SandyBridge+) */
2315
a4872ba6 2316static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2317 u32 invalidate, u32 flush)
8d19215b 2318{
fd3da6c9 2319 struct drm_device *dev = ring->dev;
1d73c2a8 2320 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2321 uint32_t cmd;
b72f3acb
CW		 2322 int ret;
2323
6a233c78 2324 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2325 if (ret)
2326 return ret;
2327
71a77e07 2328 cmd = MI_FLUSH_DW;
075b3bba
BW		 2329 if (INTEL_INFO(ring->dev)->gen >= 8)
2330 cmd += 1;
9a289771
JB		 2331 /*
2332 * Bspec vol 1c.3 - blitter engine command streamer:
2333 * "If ENABLED, all TLBs will be invalidated once the flush
2334 * operation is complete. This bit is only valid when the
2335 * Post-Sync Operation field is a value of 1h or 3h."
2336 */
71a77e07 2337 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2338 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2339 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2340 intel_ring_emit(ring, cmd);
9a289771 2341 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2342 if (INTEL_INFO(ring->dev)->gen >= 8) {
2343 intel_ring_emit(ring, 0); /* upper addr */
2344 intel_ring_emit(ring, 0); /* value */
2345 } else {
2346 intel_ring_emit(ring, 0);
2347 intel_ring_emit(ring, MI_NOOP);
2348 }
b72f3acb 2349 intel_ring_advance(ring);
fd3da6c9 2350
1d73c2a8
RV		 2351 if (!invalidate && flush) {
2352 if (IS_GEN7(dev))
2353 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2354 else if (IS_BROADWELL(dev))
2355 dev_priv->fbc.need_sw_cache_clean = true;
2356 }
fd3da6c9 2357
b72f3acb 2358 return 0;
8d19215b
ZN		 2359}
2360
5c1143bb
XH		 2361int intel_init_render_ring_buffer(struct drm_device *dev)
2362{
4640c4ff 2363 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2364 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2365 struct drm_i915_gem_object *obj;
2366 int ret;
5c1143bb 2367
59465b5f
DV		 2368 ring->name = "render ring";
2369 ring->id = RCS;
2370 ring->mmio_base = RENDER_RING_BASE;
2371
707d9cf9 2372 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2373 if (i915_semaphore_is_enabled(dev)) {
2374 obj = i915_gem_alloc_object(dev, 4096);
2375 if (obj == NULL) {
2376 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2377 i915.semaphores = 0;
2378 } else {
2379 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2380 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2381 if (ret != 0) {
2382 drm_gem_object_unreference(&obj->base);
2383 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2384 i915.semaphores = 0;
2385 } else
2386 dev_priv->semaphore_obj = obj;
2387 }
2388 }
7225342a 2389
8f0e2b9d 2390 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2391 ring->add_request = gen6_add_request;
2392 ring->flush = gen8_render_ring_flush;
2393 ring->irq_get = gen8_ring_get_irq;
2394 ring->irq_put = gen8_ring_put_irq;
2395 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2396 ring->get_seqno = gen6_ring_get_seqno;
2397 ring->set_seqno = ring_set_seqno;
2398 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2399 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2400 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2401 ring->semaphore.signal = gen8_rcs_signal;
2402 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2403 }
2404 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2405 ring->add_request = gen6_add_request;
4772eaeb 2406 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2407 if (INTEL_INFO(dev)->gen == 6)
b3111509 2408 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2409 ring->irq_get = gen6_ring_get_irq;
2410 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2411 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2412 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2413 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2414 if (i915_semaphore_is_enabled(dev)) {
2415 ring->semaphore.sync_to = gen6_ring_sync;
2416 ring->semaphore.signal = gen6_signal;
2417 /*
2418 * The current semaphore is only applied on pre-gen8
2419 * platform. And there is no VCS2 ring on the pre-gen8
2420 * platform. So the semaphore between RCS and VCS2 is
2421 * initialized as INVALID. Gen8 will initialize the
2422 * sema between VCS2 and RCS later.
2423 */
2424 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2425 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2426 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2427 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2428 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2429 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2430 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2431 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2432 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2433 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2434 }
c6df541c
CW		 2435 } else if (IS_GEN5(dev)) {
2436 ring->add_request = pc_render_add_request;
46f0f8d1 2437 ring->flush = gen4_render_ring_flush;
c6df541c 2438 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2439 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2440 ring->irq_get = gen5_ring_get_irq;
2441 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2442 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2443 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2444 } else {
8620a3a9 2445 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2446 if (INTEL_INFO(dev)->gen < 4)
2447 ring->flush = gen2_render_ring_flush;
2448 else
2449 ring->flush = gen4_render_ring_flush;
59465b5f 2450 ring->get_seqno = ring_get_seqno;
b70ec5bf 2451 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2452 if (IS_GEN2(dev)) {
2453 ring->irq_get = i8xx_ring_get_irq;
2454 ring->irq_put = i8xx_ring_put_irq;
2455 } else {
2456 ring->irq_get = i9xx_ring_get_irq;
2457 ring->irq_put = i9xx_ring_put_irq;
2458 }
e3670319 2459 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2460 }
59465b5f 2461 ring->write_tail = ring_write_tail;
707d9cf9 2462
d7d4eedd
CW		 2463 if (IS_HASWELL(dev))
2464 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2465 else if (IS_GEN8(dev))
2466 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2467 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2468 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2469 else if (INTEL_INFO(dev)->gen >= 4)
2470 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2471 else if (IS_I830(dev) || IS_845G(dev))
2472 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2473 else
2474 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2475 ring->init_hw = init_render_ring;
59465b5f
DV		 2476 ring->cleanup = render_ring_cleanup;
2477
b45305fc
DV		 2478 /* Workaround batchbuffer to combat CS tlb bug. */
2479 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2480 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2481 if (obj == NULL) {
2482 DRM_ERROR("Failed to allocate batch bo\n");
2483 return -ENOMEM;
2484 }
2485
be1fa129 2486 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2487 if (ret != 0) {
2488 drm_gem_object_unreference(&obj->base);
2489 DRM_ERROR("Failed to ping batch bo\n");
2490 return ret;
2491 }
2492
0d1aacac
CW		 2493 ring->scratch.obj = obj;
2494 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2495 }
2496
99be1dfe
DV		 2497 ret = intel_init_ring_buffer(dev, ring);
2498 if (ret)
2499 return ret;
2500
2501 if (INTEL_INFO(dev)->gen >= 5) {
2502 ret = intel_init_pipe_control(ring);
2503 if (ret)
2504 return ret;
2505 }
2506
2507 return 0;
5c1143bb
XH		 2508}
2509
2510int intel_init_bsd_ring_buffer(struct drm_device *dev)
2511{
4640c4ff 2512 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2513 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2514
58fa3835
DV		 2515 ring->name = "bsd ring";
2516 ring->id = VCS;
2517
0fd2c201 2518 ring->write_tail = ring_write_tail;
780f18c8 2519 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2520 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2521 /* gen6 bsd needs a special wa for tail updates */
2522 if (IS_GEN6(dev))
2523 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2524 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2525 ring->add_request = gen6_add_request;
2526 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2527 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2528 if (INTEL_INFO(dev)->gen >= 8) {
2529 ring->irq_enable_mask =
2530 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2531 ring->irq_get = gen8_ring_get_irq;
2532 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2533 ring->dispatch_execbuffer =
2534 gen8_ring_dispatch_execbuffer;
707d9cf9 2535 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2536 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2537 ring->semaphore.signal = gen8_xcs_signal;
2538 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2539 }
abd58f01
BW		 2540 } else {
2541 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2542 ring->irq_get = gen6_ring_get_irq;
2543 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2544 ring->dispatch_execbuffer =
2545 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2546 if (i915_semaphore_is_enabled(dev)) {
2547 ring->semaphore.sync_to = gen6_ring_sync;
2548 ring->semaphore.signal = gen6_signal;
2549 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2550 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2551 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2552 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2553 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2554 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2555 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2556 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2557 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2558 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2559 }
abd58f01 2560 }
58fa3835
DV		 2561 } else {
2562 ring->mmio_base = BSD_RING_BASE;
58fa3835 2563 ring->flush = bsd_ring_flush;
8620a3a9 2564 ring->add_request = i9xx_add_request;
58fa3835 2565 ring->get_seqno = ring_get_seqno;
b70ec5bf 2566 ring->set_seqno = ring_set_seqno;
e48d8634 2567 if (IS_GEN5(dev)) {
cc609d5d 2568 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2569 ring->irq_get = gen5_ring_get_irq;
2570 ring->irq_put = gen5_ring_put_irq;
2571 } else {
e3670319 2572 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2573 ring->irq_get = i9xx_ring_get_irq;
2574 ring->irq_put = i9xx_ring_put_irq;
2575 }
fb3256da 2576 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2577 }
ecfe00d8 2578 ring->init_hw = init_ring_common;
58fa3835 2579
1ec14ad3 2580 return intel_init_ring_buffer(dev, ring);
5c1143bb 2581}
549f7365 2582
845f74a7
ZY		 2583/**
2584 * Initialize the second BSD ring for Broadwell GT3.
2585 * It is noted that this only exists on Broadwell GT3.
2586 */
2587int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2588{
2589 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2590 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2591
2592 if ((INTEL_INFO(dev)->gen != 8)) {
2593 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2594 return -EINVAL;
2595 }
2596
f7b64236 2597 ring->name = "bsd2 ring";
845f74a7
ZY		 2598 ring->id = VCS2;
2599
2600 ring->write_tail = ring_write_tail;
2601 ring->mmio_base = GEN8_BSD2_RING_BASE;
2602 ring->flush = gen6_bsd_ring_flush;
2603 ring->add_request = gen6_add_request;
2604 ring->get_seqno = gen6_ring_get_seqno;
2605 ring->set_seqno = ring_set_seqno;
2606 ring->irq_enable_mask =
2607 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2608 ring->irq_get = gen8_ring_get_irq;
2609 ring->irq_put = gen8_ring_put_irq;
2610 ring->dispatch_execbuffer =
2611 gen8_ring_dispatch_execbuffer;
3e78998a 2612 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2613 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2614 ring->semaphore.signal = gen8_xcs_signal;
2615 GEN8_RING_SEMAPHORE_INIT;
2616 }
ecfe00d8 2617 ring->init_hw = init_ring_common;
845f74a7
ZY		 2618
2619 return intel_init_ring_buffer(dev, ring);
2620}
2621
549f7365
CW		 2622int intel_init_blt_ring_buffer(struct drm_device *dev)
2623{
4640c4ff 2624 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2625 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2626
3535d9dd
DV		 2627 ring->name = "blitter ring";
2628 ring->id = BCS;
2629
2630 ring->mmio_base = BLT_RING_BASE;
2631 ring->write_tail = ring_write_tail;
ea251324 2632 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2633 ring->add_request = gen6_add_request;
2634 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2635 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2636 if (INTEL_INFO(dev)->gen >= 8) {
2637 ring->irq_enable_mask =
2638 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2639 ring->irq_get = gen8_ring_get_irq;
2640 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2641 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2642 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2643 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2644 ring->semaphore.signal = gen8_xcs_signal;
2645 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2646 }
abd58f01
BW		 2647 } else {
2648 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2649 ring->irq_get = gen6_ring_get_irq;
2650 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2651 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2652 if (i915_semaphore_is_enabled(dev)) {
2653 ring->semaphore.signal = gen6_signal;
2654 ring->semaphore.sync_to = gen6_ring_sync;
2655 /*
2656 * The current semaphore is only applied on pre-gen8
2657 * platform. And there is no VCS2 ring on the pre-gen8
2658 * platform. So the semaphore between BCS and VCS2 is
2659 * initialized as INVALID. Gen8 will initialize the
2660 * sema between BCS and VCS2 later.
2661 */
2662 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2663 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2664 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2665 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2666 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2667 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2668 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2669 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2670 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2671 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2672 }
abd58f01 2673 }
ecfe00d8 2674 ring->init_hw = init_ring_common;
549f7365 2675
1ec14ad3 2676 return intel_init_ring_buffer(dev, ring);
549f7365 2677}
a7b9761d 2678
9a8a2213
BW		 2679int intel_init_vebox_ring_buffer(struct drm_device *dev)
2680{
4640c4ff 2681 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2682 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2683
2684 ring->name = "video enhancement ring";
2685 ring->id = VECS;
2686
2687 ring->mmio_base = VEBOX_RING_BASE;
2688 ring->write_tail = ring_write_tail;
2689 ring->flush = gen6_ring_flush;
2690 ring->add_request = gen6_add_request;
2691 ring->get_seqno = gen6_ring_get_seqno;
2692 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2693
2694 if (INTEL_INFO(dev)->gen >= 8) {
2695 ring->irq_enable_mask =
40c499f9 2696 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2697 ring->irq_get = gen8_ring_get_irq;
2698 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2699 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2700 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2701 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2702 ring->semaphore.signal = gen8_xcs_signal;
2703 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2704 }
abd58f01
BW		 2705 } else {
2706 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2707 ring->irq_get = hsw_vebox_get_irq;
2708 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2709 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2710 if (i915_semaphore_is_enabled(dev)) {
2711 ring->semaphore.sync_to = gen6_ring_sync;
2712 ring->semaphore.signal = gen6_signal;
2713 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2714 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2715 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2716 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2717 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2718 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2719 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2720 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2721 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2722 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2723 }
abd58f01 2724 }
ecfe00d8 2725 ring->init_hw = init_ring_common;
9a8a2213
BW		 2726
2727 return intel_init_ring_buffer(dev, ring);
2728}
2729
a7b9761d 2730int
a4872ba6 2731intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2732{
2733 int ret;
2734
2735 if (!ring->gpu_caches_dirty)
2736 return 0;
2737
2738 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2739 if (ret)
2740 return ret;
2741
2742 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2743
2744 ring->gpu_caches_dirty = false;
2745 return 0;
2746}
2747
2748int
a4872ba6 2749intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2750{
2751 uint32_t flush_domains;
2752 int ret;
2753
2754 flush_domains = 0;
2755 if (ring->gpu_caches_dirty)
2756 flush_domains = I915_GEM_GPU_DOMAINS;
2757
2758 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2759 if (ret)
2760 return ret;
2761
2762 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2763
2764 ring->gpu_caches_dirty = false;
2765 return 0;
2766}
e3efda49
CW		 2767
2768void
a4872ba6 2769intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2770{
2771 int ret;
2772
2773 if (!intel_ring_initialized(ring))
2774 return;
2775
2776 ret = intel_ring_idle(ring);
2777 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2778 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2779 ring->name, ret);
2780
2781 stop_ring(ring);
2782}
Linux kernel - Deliverables
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