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drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
a4d8a0fe 30#include <linux/log2.h>
760285e7 31#include <drm/drmP.h>
62fdfeaf 32#include "i915_drv.h"
760285e7 33#include <drm/i915_drm.h>
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
a0442461
CW		 37/* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
39 */
40#define LEGACY_REQUEST_SIZE 200
41
82e104cc 42int __intel_ring_space(int head, int tail, int size)
c7dca47b 43{
4f54741e
DG		 44 int space = head - tail;
45 if (space <= 0)
1cf0ba14 46 space += size;
4f54741e 47 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 48}
49
ebd0fd4b
DG		 50void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
51{
52 if (ringbuf->last_retired_head != -1) {
53 ringbuf->head = ringbuf->last_retired_head;
54 ringbuf->last_retired_head = -1;
55 }
56
57 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
58 ringbuf->tail, ringbuf->size);
59}
60
117897f4 61bool intel_engine_stopped(struct intel_engine_cs *engine)
09246732 62{
c033666a 63 struct drm_i915_private *dev_priv = engine->i915;
666796da 64 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
88b4aa87 65}
09246732 66
0bc40be8 67static void __intel_ring_advance(struct intel_engine_cs *engine)
88b4aa87 68{
0bc40be8 69 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 70 ringbuf->tail &= ringbuf->size - 1;
117897f4 71 if (intel_engine_stopped(engine))
09246732 72 return;
0bc40be8 73 engine->write_tail(engine, ringbuf->tail);
09246732
CW		 74}
75
b72f3acb 76static int
a84c3ae1 77gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 78 u32 invalidate_domains,
79 u32 flush_domains)
80{
4a570db5 81 struct intel_engine_cs *engine = req->engine;
46f0f8d1
CW		 82 u32 cmd;
83 int ret;
84
85 cmd = MI_FLUSH;
31b14c9f 86 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 87 cmd |= MI_NO_WRITE_FLUSH;
88
89 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
90 cmd |= MI_READ_FLUSH;
91
5fb9de1a 92 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 93 if (ret)
94 return ret;
95
e2f80391
TU		 96 intel_ring_emit(engine, cmd);
97 intel_ring_emit(engine, MI_NOOP);
98 intel_ring_advance(engine);
46f0f8d1
CW		 99
100 return 0;
101}
102
103static int
a84c3ae1 104gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 105 u32 invalidate_domains,
106 u32 flush_domains)
62fdfeaf 107{
4a570db5 108 struct intel_engine_cs *engine = req->engine;
6f392d54 109 u32 cmd;
b72f3acb 110 int ret;
6f392d54 111
36d527de
CW		 112 /*
113 * read/write caches:
114 *
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
118 *
119 * read-only caches:
120 *
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
123 *
124 * I915_GEM_DOMAIN_COMMAND may not exist?
125 *
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
128 *
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
131 *
132 * TLBs:
133 *
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
138 */
139
140 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 141 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 142 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 143 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
144 cmd |= MI_EXE_FLUSH;
62fdfeaf 145
36d527de 146 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
c033666a 147 (IS_G4X(req->i915) || IS_GEN5(req->i915)))
36d527de 148 cmd |= MI_INVALIDATE_ISP;
70eac33e 149
5fb9de1a 150 ret = intel_ring_begin(req, 2);
36d527de
CW		 151 if (ret)
152 return ret;
b72f3acb 153
e2f80391
TU		 154 intel_ring_emit(engine, cmd);
155 intel_ring_emit(engine, MI_NOOP);
156 intel_ring_advance(engine);
b72f3acb
CW		 157
158 return 0;
8187a2b7
ZN		 159}
160
8d315287
JB		 161/**
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
165 *
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
169 * 0.
170 *
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
173 *
174 * And the workaround for these two requires this workaround first:
175 *
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
178 * flushes.
179 *
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
182 * volume 2 part 1:
183 *
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
191 *
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
197 */
198static int
f2cf1fcc 199intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 200{
4a570db5 201 struct intel_engine_cs *engine = req->engine;
e2f80391 202 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 203 int ret;
204
5fb9de1a 205 ret = intel_ring_begin(req, 6);
8d315287
JB		 206 if (ret)
207 return ret;
208
e2f80391
TU		 209 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
8d315287 211 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 212 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(engine, 0); /* low dword */
214 intel_ring_emit(engine, 0); /* high dword */
215 intel_ring_emit(engine, MI_NOOP);
216 intel_ring_advance(engine);
8d315287 217
5fb9de1a 218 ret = intel_ring_begin(req, 6);
8d315287
JB		 219 if (ret)
220 return ret;
221
e2f80391
TU		 222 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
224 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
225 intel_ring_emit(engine, 0);
226 intel_ring_emit(engine, 0);
227 intel_ring_emit(engine, MI_NOOP);
228 intel_ring_advance(engine);
8d315287
JB		 229
230 return 0;
231}
232
233static int
a84c3ae1
JH		 234gen6_render_ring_flush(struct drm_i915_gem_request *req,
235 u32 invalidate_domains, u32 flush_domains)
8d315287 236{
4a570db5 237 struct intel_engine_cs *engine = req->engine;
8d315287 238 u32 flags = 0;
e2f80391 239 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 240 int ret;
241
b3111509 242 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 243 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 244 if (ret)
245 return ret;
246
8d315287
JB		 247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
249 * impact.
250 */
7d54a904
CW		 251 if (flush_domains) {
252 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
253 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
254 /*
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
257 */
97f209bc 258 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 259 }
260 if (invalidate_domains) {
261 flags |= PIPE_CONTROL_TLB_INVALIDATE;
262 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
263 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
264 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
267 /*
268 * TLB invalidate requires a post-sync write.
269 */
3ac78313 270 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 271 }
8d315287 272
5fb9de1a 273 ret = intel_ring_begin(req, 4);
8d315287
JB		 274 if (ret)
275 return ret;
276
e2f80391
TU		 277 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine, flags);
279 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
280 intel_ring_emit(engine, 0);
281 intel_ring_advance(engine);
8d315287
JB		 282
283 return 0;
284}
285
f3987631 286static int
f2cf1fcc 287gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 288{
4a570db5 289 struct intel_engine_cs *engine = req->engine;
f3987631
PZ		 290 int ret;
291
5fb9de1a 292 ret = intel_ring_begin(req, 4);
f3987631
PZ		 293 if (ret)
294 return ret;
295
e2f80391
TU		 296 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
f3987631 298 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 299 intel_ring_emit(engine, 0);
300 intel_ring_emit(engine, 0);
301 intel_ring_advance(engine);
f3987631
PZ		 302
303 return 0;
304}
305
4772eaeb 306static int
a84c3ae1 307gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 308 u32 invalidate_domains, u32 flush_domains)
309{
4a570db5 310 struct intel_engine_cs *engine = req->engine;
4772eaeb 311 u32 flags = 0;
e2f80391 312 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 313 int ret;
314
f3987631
PZ		 315 /*
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
318 *
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
322 */
323 flags |= PIPE_CONTROL_CS_STALL;
324
4772eaeb
PZ		 325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
327 * impact.
328 */
329 if (flush_domains) {
330 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
331 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 332 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 333 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4772eaeb
PZ		 334 }
335 if (invalidate_domains) {
336 flags |= PIPE_CONTROL_TLB_INVALIDATE;
337 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
338 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
339 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 342 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 343 /*
344 * TLB invalidate requires a post-sync write.
345 */
346 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 347 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 348
add284a3
CW		 349 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
350
f3987631
PZ		 351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
f2cf1fcc 354 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 355 }
356
5fb9de1a 357 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 358 if (ret)
359 return ret;
360
e2f80391
TU		 361 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine, flags);
363 intel_ring_emit(engine, scratch_addr);
364 intel_ring_emit(engine, 0);
365 intel_ring_advance(engine);
4772eaeb
PZ		 366
367 return 0;
368}
369
884ceace 370static int
f2cf1fcc 371gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 372 u32 flags, u32 scratch_addr)
373{
4a570db5 374 struct intel_engine_cs *engine = req->engine;
884ceace
KG		 375 int ret;
376
5fb9de1a 377 ret = intel_ring_begin(req, 6);
884ceace
KG		 378 if (ret)
379 return ret;
380
e2f80391
TU		 381 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine, flags);
383 intel_ring_emit(engine, scratch_addr);
384 intel_ring_emit(engine, 0);
385 intel_ring_emit(engine, 0);
386 intel_ring_emit(engine, 0);
387 intel_ring_advance(engine);
884ceace
KG		 388
389 return 0;
390}
391
a5f3d68e 392static int
a84c3ae1 393gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 394 u32 invalidate_domains, u32 flush_domains)
395{
396 u32 flags = 0;
4a570db5 397 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 398 int ret;
a5f3d68e
BW		 399
400 flags |= PIPE_CONTROL_CS_STALL;
401
402 if (flush_domains) {
403 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
404 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 405 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 406 flags |= PIPE_CONTROL_FLUSH_ENABLE;
a5f3d68e
BW		 407 }
408 if (invalidate_domains) {
409 flags |= PIPE_CONTROL_TLB_INVALIDATE;
410 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
412 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_QW_WRITE;
416 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 417
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 419 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 420 PIPE_CONTROL_CS_STALL |
421 PIPE_CONTROL_STALL_AT_SCOREBOARD,
422 0);
423 if (ret)
424 return ret;
a5f3d68e
BW		 425 }
426
f2cf1fcc 427 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 428}
429
0bc40be8 430static void ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 431 u32 value)
d46eefa2 432{
c033666a 433 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 434 I915_WRITE_TAIL(engine, value);
d46eefa2
XH		 435}
436
0bc40be8 437u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
8187a2b7 438{
c033666a 439 struct drm_i915_private *dev_priv = engine->i915;
50877445 440 u64 acthd;
8187a2b7 441
c033666a 442 if (INTEL_GEN(dev_priv) >= 8)
0bc40be8
TU		 443 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
444 RING_ACTHD_UDW(engine->mmio_base));
c033666a 445 else if (INTEL_GEN(dev_priv) >= 4)
0bc40be8 446 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
50877445
CW		 447 else
448 acthd = I915_READ(ACTHD);
449
450 return acthd;
8187a2b7
ZN		 451}
452
0bc40be8 453static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
035dc1e0 454{
c033666a 455 struct drm_i915_private *dev_priv = engine->i915;
035dc1e0
DV		 456 u32 addr;
457
458 addr = dev_priv->status_page_dmah->busaddr;
c033666a 459 if (INTEL_GEN(dev_priv) >= 4)
035dc1e0
DV		 460 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
461 I915_WRITE(HWS_PGA, addr);
462}
463
0bc40be8 464static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
af75f269 465{
c033666a 466 struct drm_i915_private *dev_priv = engine->i915;
f0f59a00 467 i915_reg_t mmio;
af75f269
DL		 468
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
471 */
c033666a 472 if (IS_GEN7(dev_priv)) {
0bc40be8 473 switch (engine->id) {
af75f269
DL		 474 case RCS:
475 mmio = RENDER_HWS_PGA_GEN7;
476 break;
477 case BCS:
478 mmio = BLT_HWS_PGA_GEN7;
479 break;
480 /*
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
483 */
484 case VCS2:
485 case VCS:
486 mmio = BSD_HWS_PGA_GEN7;
487 break;
488 case VECS:
489 mmio = VEBOX_HWS_PGA_GEN7;
490 break;
491 }
c033666a 492 } else if (IS_GEN6(dev_priv)) {
0bc40be8 493 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
af75f269
DL		 494 } else {
495 /* XXX: gen8 returns to sanity */
0bc40be8 496 mmio = RING_HWS_PGA(engine->mmio_base);
af75f269
DL		 497 }
498
0bc40be8 499 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
af75f269
DL		 500 POSTING_READ(mmio);
501
502 /*
503 * Flush the TLB for this page
504 *
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
508 */
ac657f64 509 if (IS_GEN(dev_priv, 6, 7)) {
0bc40be8 510 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
af75f269
DL		 511
512 /* ring should be idle before issuing a sync flush*/
0bc40be8 513 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
af75f269
DL		 514
515 I915_WRITE(reg,
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
517 INSTPM_SYNC_FLUSH));
518 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
519 1000))
520 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
0bc40be8 521 engine->name);
af75f269
DL		 522 }
523}
524
0bc40be8 525static bool stop_ring(struct intel_engine_cs *engine)
8187a2b7 526{
c033666a 527 struct drm_i915_private *dev_priv = engine->i915;
8187a2b7 528
c033666a 529 if (!IS_GEN2(dev_priv)) {
0bc40be8
TU		 530 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
531 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
532 DRM_ERROR("%s : timed out trying to stop ring\n",
533 engine->name);
9bec9b13
CW		 534 /* Sometimes we observe that the idle flag is not
535 * set even though the ring is empty. So double
536 * check before giving up.
537 */
0bc40be8 538 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
9bec9b13 539 return false;
9991ae78
CW		 540 }
541 }
b7884eb4 542
0bc40be8
TU		 543 I915_WRITE_CTL(engine, 0);
544 I915_WRITE_HEAD(engine, 0);
545 engine->write_tail(engine, 0);
8187a2b7 546
c033666a 547 if (!IS_GEN2(dev_priv)) {
0bc40be8
TU		 548 (void)I915_READ_CTL(engine);
549 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
9991ae78 550 }
a51435a3 551
0bc40be8 552 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
9991ae78 553}
8187a2b7 554
fc0768ce
TE		 555void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
556{
557 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
558}
559
0bc40be8 560static int init_ring_common(struct intel_engine_cs *engine)
9991ae78 561{
c033666a 562 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 563 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 564 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 565 int ret = 0;
566
59bad947 567 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78 568
0bc40be8 569 if (!stop_ring(engine)) {
9991ae78 570 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 571 DRM_DEBUG_KMS("%s head not reset to zero "
572 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 573 engine->name,
574 I915_READ_CTL(engine),
575 I915_READ_HEAD(engine),
576 I915_READ_TAIL(engine),
577 I915_READ_START(engine));
8187a2b7 578
0bc40be8 579 if (!stop_ring(engine)) {
6fd0d56e
CW		 580 DRM_ERROR("failed to set %s head to zero "
581 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 582 engine->name,
583 I915_READ_CTL(engine),
584 I915_READ_HEAD(engine),
585 I915_READ_TAIL(engine),
586 I915_READ_START(engine));
9991ae78
CW		 587 ret = -EIO;
588 goto out;
6fd0d56e 589 }
8187a2b7
ZN		 590 }
591
c033666a 592 if (I915_NEED_GFX_HWS(dev_priv))
0bc40be8 593 intel_ring_setup_status_page(engine);
9991ae78 594 else
0bc40be8 595 ring_setup_phys_status_page(engine);
9991ae78 596
ece4a17d 597 /* Enforce ordering by reading HEAD register back */
0bc40be8 598 I915_READ_HEAD(engine);
ece4a17d 599
0d8957c8
DV		 600 /* Initialize the ring. This must happen _after_ we've cleared the ring
601 * registers with the above sequence (the readback of the HEAD registers
602 * also enforces ordering), otherwise the hw might lose the new ring
603 * register values. */
0bc40be8 604 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 605
606 /* WaClearRingBufHeadRegAtInit:ctg,elk */
0bc40be8 607 if (I915_READ_HEAD(engine))
95468892 608 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
0bc40be8
TU		 609 engine->name, I915_READ_HEAD(engine));
610 I915_WRITE_HEAD(engine, 0);
611 (void)I915_READ_HEAD(engine);
95468892 612
0bc40be8 613 I915_WRITE_CTL(engine,
93b0a4e0 614 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 615 | RING_VALID);
8187a2b7 616
8187a2b7 617 /* If the head is still not zero, the ring is dead */
0bc40be8
TU		 618 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
619 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
620 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
e74cfed5 621 DRM_ERROR("%s initialization failed "
48e48a0b 622 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
0bc40be8
TU		 623 engine->name,
624 I915_READ_CTL(engine),
625 I915_READ_CTL(engine) & RING_VALID,
626 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
627 I915_READ_START(engine),
628 (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 629 ret = -EIO;
630 goto out;
8187a2b7
ZN		 631 }
632
ebd0fd4b 633 ringbuf->last_retired_head = -1;
0bc40be8
TU		 634 ringbuf->head = I915_READ_HEAD(engine);
635 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
ebd0fd4b 636 intel_ring_update_space(ringbuf);
1ec14ad3 637
fc0768ce 638 intel_engine_init_hangcheck(engine);
50f018df 639
b7884eb4 640out:
59bad947 641 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 642
643 return ret;
8187a2b7
ZN		 644}
645
9b1136d5 646void
0bc40be8 647intel_fini_pipe_control(struct intel_engine_cs *engine)
9b1136d5 648{
0bc40be8 649 if (engine->scratch.obj == NULL)
9b1136d5
OM		 650 return;
651
c033666a 652 if (INTEL_GEN(engine->i915) >= 5) {
0bc40be8
TU		 653 kunmap(sg_page(engine->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(engine->scratch.obj);
9b1136d5
OM		 655 }
656
0bc40be8
TU		 657 drm_gem_object_unreference(&engine->scratch.obj->base);
658 engine->scratch.obj = NULL;
9b1136d5
OM		 659}
660
661int
0bc40be8 662intel_init_pipe_control(struct intel_engine_cs *engine)
c6df541c 663{
c6df541c
CW		 664 int ret;
665
0bc40be8 666 WARN_ON(engine->scratch.obj);
c6df541c 667
c033666a 668 engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
fe3db79b 669 if (IS_ERR(engine->scratch.obj)) {
c6df541c 670 DRM_ERROR("Failed to allocate seqno page\n");
fe3db79b
CW		 671 ret = PTR_ERR(engine->scratch.obj);
672 engine->scratch.obj = NULL;
c6df541c
CW		 673 goto err;
674 }
e4ffd173 675
0bc40be8
TU		 676 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
677 I915_CACHE_LLC);
a9cc726c
DV		 678 if (ret)
679 goto err_unref;
c6df541c 680
0bc40be8 681 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
c6df541c
CW		 682 if (ret)
683 goto err_unref;
684
0bc40be8
TU		 685 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
686 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
687 if (engine->scratch.cpu_page == NULL) {
56b085a0 688 ret = -ENOMEM;
c6df541c 689 goto err_unpin;
56b085a0 690 }
c6df541c 691
2b1086cc 692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0bc40be8 693 engine->name, engine->scratch.gtt_offset);
c6df541c
CW		 694 return 0;
695
696err_unpin:
0bc40be8 697 i915_gem_object_ggtt_unpin(engine->scratch.obj);
c6df541c 698err_unref:
0bc40be8 699 drm_gem_object_unreference(&engine->scratch.obj->base);
c6df541c 700err:
c6df541c
CW		 701 return ret;
702}
703
e2be4faf 704static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 705{
4a570db5 706 struct intel_engine_cs *engine = req->engine;
c033666a
CW		 707 struct i915_workarounds *w = &req->i915->workarounds;
708 int ret, i;
888b5995 709
02235808 710 if (w->count == 0)
7225342a 711 return 0;
888b5995 712
e2f80391 713 engine->gpu_caches_dirty = true;
4866d729 714 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 715 if (ret)
716 return ret;
888b5995 717
5fb9de1a 718 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 719 if (ret)
720 return ret;
721
e2f80391 722 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
7225342a 723 for (i = 0; i < w->count; i++) {
e2f80391
TU		 724 intel_ring_emit_reg(engine, w->reg[i].addr);
725 intel_ring_emit(engine, w->reg[i].value);
7225342a 726 }
e2f80391 727 intel_ring_emit(engine, MI_NOOP);
7225342a 728
e2f80391 729 intel_ring_advance(engine);
7225342a 730
e2f80391 731 engine->gpu_caches_dirty = true;
4866d729 732 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 733 if (ret)
734 return ret;
888b5995 735
7225342a 736 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 737
7225342a 738 return 0;
86d7f238
AS		 739}
740
8753181e 741static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 742{
743 int ret;
744
e2be4faf 745 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 746 if (ret != 0)
747 return ret;
748
be01363f 749 ret = i915_gem_render_state_init(req);
8f0e2b9d 750 if (ret)
e26e1b97 751 return ret;
8f0e2b9d 752
e26e1b97 753 return 0;
8f0e2b9d
DV		 754}
755
7225342a 756static int wa_add(struct drm_i915_private *dev_priv,
f0f59a00
VS		 757 i915_reg_t addr,
758 const u32 mask, const u32 val)
7225342a
MK		 759{
760 const u32 idx = dev_priv->workarounds.count;
761
762 if (WARN_ON(idx >= I915_MAX_WA_REGS))
763 return -ENOSPC;
764
765 dev_priv->workarounds.reg[idx].addr = addr;
766 dev_priv->workarounds.reg[idx].value = val;
767 dev_priv->workarounds.reg[idx].mask = mask;
768
769 dev_priv->workarounds.count++;
770
771 return 0;
86d7f238
AS		 772}
773
ca5a0fbd 774#define WA_REG(addr, mask, val) do { \
cf4b0de6 775 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 776 if (r) \
777 return r; \
ca5a0fbd 778 } while (0)
7225342a
MK		 779
780#define WA_SET_BIT_MASKED(addr, mask) \
26459343 781 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 782
783#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 784 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 785
98533251 786#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 787 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 788
cf4b0de6
DL		 789#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
790#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 791
cf4b0de6 792#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 793
0bc40be8
TU		 794static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
795 i915_reg_t reg)
33136b06 796{
c033666a 797 struct drm_i915_private *dev_priv = engine->i915;
33136b06 798 struct i915_workarounds *wa = &dev_priv->workarounds;
0bc40be8 799 const uint32_t index = wa->hw_whitelist_count[engine->id];
33136b06
AS		 800
801 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
802 return -EINVAL;
803
0bc40be8 804 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
33136b06 805 i915_mmio_reg_offset(reg));
0bc40be8 806 wa->hw_whitelist_count[engine->id]++;
33136b06
AS		 807
808 return 0;
809}
810
0bc40be8 811static int gen8_init_workarounds(struct intel_engine_cs *engine)
e9a64ada 812{
c033666a 813 struct drm_i915_private *dev_priv = engine->i915;
68c6198b
AS		 814
815 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 816
717d84d6
AS		 817 /* WaDisableAsyncFlipPerfMode:bdw,chv */
818 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
819
d0581194
AS		 820 /* WaDisablePartialInstShootdown:bdw,chv */
821 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
822 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
823
a340af58
AS		 824 /* Use Force Non-Coherent whenever executing a 3D context. This is a
825 * workaround for for a possible hang in the unlikely event a TLB
826 * invalidation occurs during a PSD flush.
827 */
828 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 829 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 831 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 832 HDC_FORCE_NON_COHERENT);
833
6def8fdd
AS		 834 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
835 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
836 * polygons in the same 8x4 pixel/sample area to be processed without
837 * stalling waiting for the earlier ones to write to Hierarchical Z
838 * buffer."
839 *
840 * This optimization is off by default for BDW and CHV; turn it on.
841 */
842 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
843
48404636
AS		 844 /* Wa4x4STCOptimizationDisable:bdw,chv */
845 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
846
7eebcde6
AS		 847 /*
848 * BSpec recommends 8x4 when MSAA is used,
849 * however in practice 16x4 seems fastest.
850 *
851 * Note that PS/WM thread counts depend on the WIZ hashing
852 * disable bit, which we don't touch here, but it's good
853 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
854 */
855 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
856 GEN6_WIZ_HASHING_MASK,
857 GEN6_WIZ_HASHING_16x4);
858
e9a64ada
AS		 859 return 0;
860}
861
0bc40be8 862static int bdw_init_workarounds(struct intel_engine_cs *engine)
86d7f238 863{
c033666a 864 struct drm_i915_private *dev_priv = engine->i915;
e9a64ada 865 int ret;
86d7f238 866
0bc40be8 867 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 868 if (ret)
869 return ret;
870
101b376d 871 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 872 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 873
101b376d 874 /* WaDisableDopClockGating:bdw */
7225342a
MK		 875 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
876 DOP_CLOCK_GATING_DISABLE);
86d7f238 877
7225342a
MK		 878 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
879 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 880
7225342a 881 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 882 /* WaForceContextSaveRestoreNonCoherent:bdw */
883 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 884 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
c033666a 885 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 886
86d7f238
AS		 887 return 0;
888}
889
0bc40be8 890static int chv_init_workarounds(struct intel_engine_cs *engine)
00e1e623 891{
c033666a 892 struct drm_i915_private *dev_priv = engine->i915;
e9a64ada 893 int ret;
00e1e623 894
0bc40be8 895 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 896 if (ret)
897 return ret;
898
00e1e623 899 /* WaDisableThreadStallDopClockGating:chv */
d0581194 900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 901
d60de81d
KG		 902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
904
7225342a
MK		 905 return 0;
906}
907
0bc40be8 908static int gen9_init_workarounds(struct intel_engine_cs *engine)
3b106531 909{
c033666a 910 struct drm_i915_private *dev_priv = engine->i915;
e0f3fa09 911 int ret;
ab0dfafe 912
a8ab5ed5
TG		 913 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
914 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
915
e5f81d65 916 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
9c4cbf82
MK		 917 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
918 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
919
e5f81d65 920 /* WaDisableKillLogic:bxt,skl,kbl */
9c4cbf82
MK		 921 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
922 ECOCHK_DIS_TLB);
923
e5f81d65
MK		 924 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
925 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
ab0dfafe 926 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
950b2aae 927 FLOW_CONTROL_ENABLE |
ab0dfafe
HN		 928 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
929
e5f81d65 930 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
8424171e
NH		 931 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
932 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
933
e87a005d 934 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
c033666a
CW		 935 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
936 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
a86eb582
DL		 937 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
938 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 939
e87a005d 940 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
c033666a
CW		 941 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
942 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
183c6dac
DL		 943 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
944 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 945 /*
946 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
947 * but we do that in per ctx batchbuffer as there is an issue
948 * with this register not getting restored on ctx restore
949 */
183c6dac
DL		 950 }
951
e5f81d65
MK		 952 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
953 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
bfd8ad4e
TG		 954 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
955 GEN9_ENABLE_YV12_BUGFIX |
956 GEN9_ENABLE_GPGPU_PREEMPTION);
cac23df4 957
e5f81d65
MK		 958 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
959 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
60294683
AS		 960 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
961 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 962
e5f81d65 963 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
e2db7071
DL		 964 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
965 GEN9_CCS_TLB_PREFETCH_ENABLE);
966
5a2ae95e 967 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
c033666a
CW		 968 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
969 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
38a39a7b
BW		 970 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
971 PIXEL_MASK_CAMMING_DISABLE);
972
5b0e3659
MK		 973 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
974 WA_SET_BIT_MASKED(HDC_CHICKEN0,
975 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
976 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
8ea6f892 977
bbaefe72
MK		 978 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
979 * both tied to WaForceContextSaveRestoreNonCoherent
980 * in some hsds for skl. We keep the tie for all gen9. The
981 * documentation is a bit hazy and so we want to get common behaviour,
982 * even though there is no clear evidence we would need both on kbl/bxt.
983 * This area has been source of system hangs so we play it safe
984 * and mimic the skl regardless of what bspec says.
985 *
986 * Use Force Non-Coherent whenever executing a 3D context. This
987 * is a workaround for a possible hang in the unlikely event
988 * a TLB invalidation occurs during a PSD flush.
989 */
990
991 /* WaForceEnableNonCoherent:skl,bxt,kbl */
992 WA_SET_BIT_MASKED(HDC_CHICKEN0,
993 HDC_FORCE_NON_COHERENT);
994
995 /* WaDisableHDCInvalidation:skl,bxt,kbl */
996 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
997 BDW_DISABLE_HDC_INVALIDATION);
998
e5f81d65
MK		 999 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1000 if (IS_SKYLAKE(dev_priv) ||
1001 IS_KABYLAKE(dev_priv) ||
1002 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
8c761609
AS		 1003 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1004 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 1005
e5f81d65 1006 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
6b6d5626
RB		 1007 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1008
e5f81d65 1009 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
6ecf56ae
AS		 1010 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1011 GEN8_LQSC_FLUSH_COHERENT_LINES));
1012
6bb62855 1013 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1014 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1015 if (ret)
1016 return ret;
1017
e5f81d65 1018 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
0bc40be8 1019 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
e0f3fa09
AS		 1020 if (ret)
1021 return ret;
1022
e5f81d65 1023 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
0bc40be8 1024 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
3669ab61
AS		 1025 if (ret)
1026 return ret;
1027
3b106531
HN		 1028 return 0;
1029}
1030
0bc40be8 1031static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
b7668791 1032{
c033666a 1033 struct drm_i915_private *dev_priv = engine->i915;
b7668791
DL		 1034 u8 vals[3] = { 0, 0, 0 };
1035 unsigned int i;
1036
1037 for (i = 0; i < 3; i++) {
1038 u8 ss;
1039
1040 /*
1041 * Only consider slices where one, and only one, subslice has 7
1042 * EUs
1043 */
a4d8a0fe 1044 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
b7668791
DL		 1045 continue;
1046
1047 /*
1048 * subslice_7eu[i] != 0 (because of the check above) and
1049 * ss_max == 4 (maximum number of subslices possible per slice)
1050 *
1051 * -> 0 <= ss <= 3;
1052 */
1053 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1054 vals[i] = 3 - ss;
1055 }
1056
1057 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1058 return 0;
1059
1060 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1061 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1062 GEN9_IZ_HASHING_MASK(2) |
1063 GEN9_IZ_HASHING_MASK(1) |
1064 GEN9_IZ_HASHING_MASK(0),
1065 GEN9_IZ_HASHING(2, vals[2]) |
1066 GEN9_IZ_HASHING(1, vals[1]) |
1067 GEN9_IZ_HASHING(0, vals[0]));
1068
1069 return 0;
1070}
1071
0bc40be8 1072static int skl_init_workarounds(struct intel_engine_cs *engine)
8d205494 1073{
c033666a 1074 struct drm_i915_private *dev_priv = engine->i915;
aa0011a8 1075 int ret;
d0bbbc4f 1076
0bc40be8 1077 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1078 if (ret)
1079 return ret;
8d205494 1080
a78536e7
AS		 1081 /*
1082 * Actual WA is to disable percontext preemption granularity control
1083 * until D0 which is the default case so this is equivalent to
1084 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1085 */
c033666a 1086 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
a78536e7
AS		 1087 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1088 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1089 }
1090
71dce58c 1091 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
9c4cbf82
MK		 1092 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1093 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1094 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1095 }
1096
1097 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1098 * involving this register should also be added to WA batch as required.
1099 */
c033666a 1100 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
9c4cbf82
MK		 1101 /* WaDisableLSQCROPERFforOCL:skl */
1102 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1103 GEN8_LQSC_RO_PERF_DIS);
1104
1105 /* WaEnableGapsTsvCreditFix:skl */
c033666a 1106 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1107 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1108 GEN9_GAPS_TSV_CREDIT_DISABLE));
1109 }
1110
d0bbbc4f 1111 /* WaDisablePowerCompilerClockGating:skl */
c033666a 1112 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1113 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1114 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1115
e87a005d 1116 /* WaBarrierPerformanceFixDisable:skl */
c033666a 1117 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1118 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1119 HDC_FENCE_DEST_SLM_DISABLE |
1120 HDC_BARRIER_PERFORMANCE_DISABLE);
1121
9bd9dfb4 1122 /* WaDisableSbeCacheDispatchPortSharing:skl */
c033666a 1123 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1124 WA_SET_BIT_MASKED(
1125 GEN7_HALF_SLICE_CHICKEN1,
1126 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1127
eee8efb0
MK		 1128 /* WaDisableGafsUnitClkGating:skl */
1129 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1130
6107497e 1131 /* WaDisableLSQCROPERFforOCL:skl */
0bc40be8 1132 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
6107497e
AS		 1133 if (ret)
1134 return ret;
1135
0bc40be8 1136 return skl_tune_iz_hashing(engine);
7225342a
MK		 1137}
1138
0bc40be8 1139static int bxt_init_workarounds(struct intel_engine_cs *engine)
cae0437f 1140{
c033666a 1141 struct drm_i915_private *dev_priv = engine->i915;
aa0011a8 1142 int ret;
dfb601e6 1143
0bc40be8 1144 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1145 if (ret)
1146 return ret;
cae0437f 1147
9c4cbf82
MK		 1148 /* WaStoreMultiplePTEenable:bxt */
1149 /* This is a requirement according to Hardware specification */
c033666a 1150 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
9c4cbf82
MK		 1151 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1152
1153 /* WaSetClckGatingDisableMedia:bxt */
c033666a 1154 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
9c4cbf82
MK		 1155 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1156 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1157 }
1158
dfb601e6
NH		 1159 /* WaDisableThreadStallDopClockGating:bxt */
1160 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1161 STALL_DOP_GATING_DISABLE);
1162
780f0aeb 1163 /* WaDisablePooledEuLoadBalancingFix:bxt */
1164 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1165 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1166 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1167 }
1168
983b4b9d 1169 /* WaDisableSbeCacheDispatchPortSharing:bxt */
c033666a 1170 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1171 WA_SET_BIT_MASKED(
1172 GEN7_HALF_SLICE_CHICKEN1,
1173 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1174 }
1175
2c8580e4
AS		 1176 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1177 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1178 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
a786d53a 1179 /* WaDisableLSQCROPERFforOCL:bxt */
c033666a 1180 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
0bc40be8 1181 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
2c8580e4
AS		 1182 if (ret)
1183 return ret;
a786d53a 1184
0bc40be8 1185 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
a786d53a
AS		 1186 if (ret)
1187 return ret;
2c8580e4
AS		 1188 }
1189
050fc465 1190 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
c033666a 1191 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
36579cb6
ID		 1192 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1193 L3_HIGH_PRIO_CREDITS(2));
050fc465 1194
ad2bdb44
MK		 1195 /* WaInsertDummyPushConstPs:bxt */
1196 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1197 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1198 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1199
cae0437f
NH		 1200 return 0;
1201}
1202
e5f81d65
MK		 1203static int kbl_init_workarounds(struct intel_engine_cs *engine)
1204{
e587f6cb 1205 struct drm_i915_private *dev_priv = engine->i915;
e5f81d65
MK		 1206 int ret;
1207
1208 ret = gen9_init_workarounds(engine);
1209 if (ret)
1210 return ret;
1211
e587f6cb
MK		 1212 /* WaEnableGapsTsvCreditFix:kbl */
1213 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1214 GEN9_GAPS_TSV_CREDIT_DISABLE));
1215
c0b730d5
MK		 1216 /* WaDisableDynamicCreditSharing:kbl */
1217 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1218 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1219 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1220
8401d42f
MK		 1221 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1222 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1223 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1224 HDC_FENCE_DEST_SLM_DISABLE);
1225
fe905819
MK		 1226 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1227 * involving this register should also be added to WA batch as required.
1228 */
1229 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1230 /* WaDisableLSQCROPERFforOCL:kbl */
1231 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1232 GEN8_LQSC_RO_PERF_DIS);
1233
ad2bdb44
MK		 1234 /* WaInsertDummyPushConstPs:kbl */
1235 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1236 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1237 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1238
4de5d7cc
MK		 1239 /* WaDisableGafsUnitClkGating:kbl */
1240 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1241
954337aa
MK		 1242 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1243 WA_SET_BIT_MASKED(
1244 GEN7_HALF_SLICE_CHICKEN1,
1245 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1246
fe905819
MK		 1247 /* WaDisableLSQCROPERFforOCL:kbl */
1248 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1249 if (ret)
1250 return ret;
1251
e5f81d65
MK		 1252 return 0;
1253}
1254
0bc40be8 1255int init_workarounds_ring(struct intel_engine_cs *engine)
7225342a 1256{
c033666a 1257 struct drm_i915_private *dev_priv = engine->i915;
7225342a 1258
0bc40be8 1259 WARN_ON(engine->id != RCS);
7225342a
MK		 1260
1261 dev_priv->workarounds.count = 0;
33136b06 1262 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
7225342a 1263
c033666a 1264 if (IS_BROADWELL(dev_priv))
0bc40be8 1265 return bdw_init_workarounds(engine);
7225342a 1266
c033666a 1267 if (IS_CHERRYVIEW(dev_priv))
0bc40be8 1268 return chv_init_workarounds(engine);
00e1e623 1269
c033666a 1270 if (IS_SKYLAKE(dev_priv))
0bc40be8 1271 return skl_init_workarounds(engine);
cae0437f 1272
c033666a 1273 if (IS_BROXTON(dev_priv))
0bc40be8 1274 return bxt_init_workarounds(engine);
3b106531 1275
e5f81d65
MK		 1276 if (IS_KABYLAKE(dev_priv))
1277 return kbl_init_workarounds(engine);
1278
00e1e623
VS		 1279 return 0;
1280}
1281
0bc40be8 1282static int init_render_ring(struct intel_engine_cs *engine)
8187a2b7 1283{
c033666a 1284 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 1285 int ret = init_ring_common(engine);
9c33baa6
KZ		 1286 if (ret)
1287 return ret;
a69ffdbf 1288
61a563a2 1289 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
ac657f64 1290 if (IS_GEN(dev_priv, 4, 6))
6b26c86d 1291 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1292
1293 /* We need to disable the AsyncFlip performance optimisations in order
1294 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1295 * programmed to '1' on all products.
8693a824 1296 *
2441f877 1297 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1298 */
ac657f64 1299 if (IS_GEN(dev_priv, 6, 7))
1c8c38c5
CW		 1300 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1301
f05bb0c7 1302 /* Required for the hardware to program scanline values for waiting */
01fa0302 1303 /* WaEnableFlushTlbInvalidationMode:snb */
c033666a 1304 if (IS_GEN6(dev_priv))
f05bb0c7 1305 I915_WRITE(GFX_MODE,
aa83e30d 1306 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1307
01fa0302 1308 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
c033666a 1309 if (IS_GEN7(dev_priv))
1c8c38c5 1310 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1311 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1312 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1313
c033666a 1314 if (IS_GEN6(dev_priv)) {
3a69ddd6
KG		 1315 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1316 * "If this bit is set, STCunit will have LRA as replacement
1317 * policy. [...] This bit must be reset. LRA replacement
1318 * policy is not supported."
1319 */
1320 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1321 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1322 }
1323
ac657f64 1324 if (IS_GEN(dev_priv, 6, 7))
6b26c86d 1325 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1326
c033666a
CW		 1327 if (HAS_L3_DPF(dev_priv))
1328 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
15b9f80e 1329
0bc40be8 1330 return init_workarounds_ring(engine);
8187a2b7
ZN		 1331}
1332
0bc40be8 1333static void render_ring_cleanup(struct intel_engine_cs *engine)
c6df541c 1334{
c033666a 1335 struct drm_i915_private *dev_priv = engine->i915;
3e78998a
BW		 1336
1337 if (dev_priv->semaphore_obj) {
1338 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1339 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1340 dev_priv->semaphore_obj = NULL;
1341 }
b45305fc 1342
0bc40be8 1343 intel_fini_pipe_control(engine);
c6df541c
CW		 1344}
1345
f7169687 1346static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1347 unsigned int num_dwords)
1348{
1349#define MBOX_UPDATE_DWORDS 8
4a570db5 1350 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1351 struct drm_i915_private *dev_priv = signaller_req->i915;
3e78998a 1352 struct intel_engine_cs *waiter;
c3232b18
DG		 1353 enum intel_engine_id id;
1354 int ret, num_rings;
3e78998a 1355
c033666a 1356 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
3e78998a
BW		 1357 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1358#undef MBOX_UPDATE_DWORDS
1359
5fb9de1a 1360 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1361 if (ret)
1362 return ret;
1363
c3232b18 1364 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1365 u32 seqno;
c3232b18 1366 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1367 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1368 continue;
1369
f7169687 1370 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1371 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1372 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1373 PIPE_CONTROL_QW_WRITE |
f9a4ea35 1374 PIPE_CONTROL_CS_STALL);
3e78998a
BW		 1375 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1376 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1377 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1378 intel_ring_emit(signaller, 0);
1379 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
215a7e32 1380 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1381 intel_ring_emit(signaller, 0);
1382 }
1383
1384 return 0;
1385}
1386
f7169687 1387static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1388 unsigned int num_dwords)
1389{
1390#define MBOX_UPDATE_DWORDS 6
4a570db5 1391 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1392 struct drm_i915_private *dev_priv = signaller_req->i915;
3e78998a 1393 struct intel_engine_cs *waiter;
c3232b18
DG		 1394 enum intel_engine_id id;
1395 int ret, num_rings;
3e78998a 1396
c033666a 1397 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
3e78998a
BW		 1398 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1399#undef MBOX_UPDATE_DWORDS
1400
5fb9de1a 1401 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1402 if (ret)
1403 return ret;
1404
c3232b18 1405 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1406 u32 seqno;
c3232b18 1407 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1408 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1409 continue;
1410
f7169687 1411 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1412 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1413 MI_FLUSH_DW_OP_STOREDW);
1414 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1415 MI_FLUSH_DW_USE_GTT);
1416 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1417 intel_ring_emit(signaller, seqno);
3e78998a 1418 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
215a7e32 1419 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1420 intel_ring_emit(signaller, 0);
1421 }
1422
1423 return 0;
1424}
1425
f7169687 1426static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1427 unsigned int num_dwords)
1ec14ad3 1428{
4a570db5 1429 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1430 struct drm_i915_private *dev_priv = signaller_req->i915;
a4872ba6 1431 struct intel_engine_cs *useless;
c3232b18
DG		 1432 enum intel_engine_id id;
1433 int ret, num_rings;
78325f2d 1434
a1444b79 1435#define MBOX_UPDATE_DWORDS 3
c033666a 1436 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
a1444b79
BW		 1437 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1438#undef MBOX_UPDATE_DWORDS
024a43e1 1439
5fb9de1a 1440 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1441 if (ret)
1442 return ret;
024a43e1 1443
c3232b18
DG		 1444 for_each_engine_id(useless, dev_priv, id) {
1445 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
f0f59a00
VS		 1446
1447 if (i915_mmio_reg_valid(mbox_reg)) {
f7169687 1448 u32 seqno = i915_gem_request_get_seqno(signaller_req);
f0f59a00 1449
78325f2d 1450 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
f92a9162 1451 intel_ring_emit_reg(signaller, mbox_reg);
6259cead 1452 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1453 }
1454 }
024a43e1 1455
a1444b79
BW		 1456 /* If num_dwords was rounded, make sure the tail pointer is correct */
1457 if (num_rings % 2 == 0)
1458 intel_ring_emit(signaller, MI_NOOP);
1459
024a43e1 1460 return 0;
1ec14ad3
CW		 1461}
1462
c8c99b0f
BW		 1463/**
1464 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1465 *
1466 * @request - request to write to the ring
c8c99b0f
BW		 1467 *
1468 * Update the mailbox registers in the *other* rings with the current seqno.
1469 * This acts like a signal in the canonical semaphore.
1470 */
1ec14ad3 1471static int
ee044a88 1472gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1473{
4a570db5 1474 struct intel_engine_cs *engine = req->engine;
024a43e1 1475 int ret;
52ed2325 1476
e2f80391
TU		 1477 if (engine->semaphore.signal)
1478 ret = engine->semaphore.signal(req, 4);
707d9cf9 1479 else
5fb9de1a 1480 ret = intel_ring_begin(req, 4);
707d9cf9 1481
1ec14ad3
CW		 1482 if (ret)
1483 return ret;
1484
e2f80391
TU		 1485 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1486 intel_ring_emit(engine,
1487 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1488 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1489 intel_ring_emit(engine, MI_USER_INTERRUPT);
1490 __intel_ring_advance(engine);
1ec14ad3 1491
1ec14ad3
CW		 1492 return 0;
1493}
1494
a58c01aa
CW		 1495static int
1496gen8_render_add_request(struct drm_i915_gem_request *req)
1497{
1498 struct intel_engine_cs *engine = req->engine;
1499 int ret;
1500
1501 if (engine->semaphore.signal)
1502 ret = engine->semaphore.signal(req, 8);
1503 else
1504 ret = intel_ring_begin(req, 8);
1505 if (ret)
1506 return ret;
1507
1508 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1509 intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1510 PIPE_CONTROL_CS_STALL |
1511 PIPE_CONTROL_QW_WRITE));
1512 intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1513 intel_ring_emit(engine, 0);
1514 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1515 /* We're thrashing one dword of HWS. */
1516 intel_ring_emit(engine, 0);
1517 intel_ring_emit(engine, MI_USER_INTERRUPT);
1518 intel_ring_emit(engine, MI_NOOP);
1519 __intel_ring_advance(engine);
1520
1521 return 0;
1522}
1523
c033666a 1524static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
f72b3435
MK		 1525 u32 seqno)
1526{
f72b3435
MK		 1527 return dev_priv->last_seqno < seqno;
1528}
1529
c8c99b0f
BW		 1530/**
1531 * intel_ring_sync - sync the waiter to the signaller on seqno
1532 *
1533 * @waiter - ring that is waiting
1534 * @signaller - ring which has, or will signal
1535 * @seqno - seqno which the waiter will block on
1536 */
5ee426ca
BW		 1537
1538static int
599d924c 1539gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1540 struct intel_engine_cs *signaller,
1541 u32 seqno)
1542{
4a570db5 1543 struct intel_engine_cs *waiter = waiter_req->engine;
c033666a 1544 struct drm_i915_private *dev_priv = waiter_req->i915;
6ef48d7f 1545 struct i915_hw_ppgtt *ppgtt;
5ee426ca
BW		 1546 int ret;
1547
5fb9de1a 1548 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1549 if (ret)
1550 return ret;
1551
1552 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1553 MI_SEMAPHORE_GLOBAL_GTT |
1554 MI_SEMAPHORE_SAD_GTE_SDD);
1555 intel_ring_emit(waiter, seqno);
1556 intel_ring_emit(waiter,
1557 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1558 intel_ring_emit(waiter,
1559 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1560 intel_ring_advance(waiter);
6ef48d7f
CW		 1561
1562 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1563 * pagetables and we must reload them before executing the batch.
1564 * We do this on the i915_switch_context() following the wait and
1565 * before the dispatch.
1566 */
1567 ppgtt = waiter_req->ctx->ppgtt;
1568 if (ppgtt && waiter_req->engine->id != RCS)
1569 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
5ee426ca
BW		 1570 return 0;
1571}
1572
c8c99b0f 1573static int
599d924c 1574gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1575 struct intel_engine_cs *signaller,
686cb5f9 1576 u32 seqno)
1ec14ad3 1577{
4a570db5 1578 struct intel_engine_cs *waiter = waiter_req->engine;
c8c99b0f
BW		 1579 u32 dw1 = MI_SEMAPHORE_MBOX |
1580 MI_SEMAPHORE_COMPARE |
1581 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1582 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1583 int ret;
1ec14ad3 1584
1500f7ea
BW		 1585 /* Throughout all of the GEM code, seqno passed implies our current
1586 * seqno is >= the last seqno executed. However for hardware the
1587 * comparison is strictly greater than.
1588 */
1589 seqno -= 1;
1590
ebc348b2 1591 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1592
5fb9de1a 1593 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1594 if (ret)
1595 return ret;
1596
f72b3435 1597 /* If seqno wrap happened, omit the wait with no-ops */
c033666a 1598 if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
ebc348b2 1599 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1600 intel_ring_emit(waiter, seqno);
1601 intel_ring_emit(waiter, 0);
1602 intel_ring_emit(waiter, MI_NOOP);
1603 } else {
1604 intel_ring_emit(waiter, MI_NOOP);
1605 intel_ring_emit(waiter, MI_NOOP);
1606 intel_ring_emit(waiter, MI_NOOP);
1607 intel_ring_emit(waiter, MI_NOOP);
1608 }
c8c99b0f 1609 intel_ring_advance(waiter);
1ec14ad3
CW		 1610
1611 return 0;
1612}
1613
c6df541c
CW		 1614#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1615do { \
fcbc34e4
KG		 1616 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1617 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1618 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1619 intel_ring_emit(ring__, 0); \
1620 intel_ring_emit(ring__, 0); \
1621} while (0)
1622
1623static int
ee044a88 1624pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1625{
4a570db5 1626 struct intel_engine_cs *engine = req->engine;
e2f80391 1627 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1628 int ret;
1629
1630 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1631 * incoherent with writes to memory, i.e. completely fubar,
1632 * so we need to use PIPE_NOTIFY instead.
1633 *
1634 * However, we also need to workaround the qword write
1635 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1636 * memory before requesting an interrupt.
1637 */
5fb9de1a 1638 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1639 if (ret)
1640 return ret;
1641
e2f80391
TU		 1642 intel_ring_emit(engine,
1643 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1644 PIPE_CONTROL_WRITE_FLUSH |
1645 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
e2f80391
TU		 1646 intel_ring_emit(engine,
1647 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1648 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1649 intel_ring_emit(engine, 0);
1650 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1651 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
e2f80391 1652 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1653 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1654 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1655 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1656 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1657 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1658 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1659 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1660 PIPE_CONTROL_FLUSH(engine, scratch_addr);
a71d8d94 1661
e2f80391
TU		 1662 intel_ring_emit(engine,
1663 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1664 PIPE_CONTROL_WRITE_FLUSH |
1665 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1666 PIPE_CONTROL_NOTIFY);
e2f80391
TU		 1667 intel_ring_emit(engine,
1668 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1669 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1670 intel_ring_emit(engine, 0);
1671 __intel_ring_advance(engine);
c6df541c 1672
c6df541c
CW		 1673 return 0;
1674}
1675
c04e0f3b
CW		 1676static void
1677gen6_seqno_barrier(struct intel_engine_cs *engine)
4cd53c0c 1678{
c033666a 1679 struct drm_i915_private *dev_priv = engine->i915;
bcbdb6d0 1680
4cd53c0c
DV		 1681 /* Workaround to force correct ordering between irq and seqno writes on
1682 * ivb (and maybe also on snb) by reading from a CS register (like
9b9ed309
CW		 1683 * ACTHD) before reading the status page.
1684 *
1685 * Note that this effectively stalls the read by the time it takes to
1686 * do a memory transaction, which more or less ensures that the write
1687 * from the GPU has sufficient time to invalidate the CPU cacheline.
1688 * Alternatively we could delay the interrupt from the CS ring to give
1689 * the write time to land, but that would incur a delay after every
1690 * batch i.e. much more frequent than a delay when waiting for the
1691 * interrupt (with the same net latency).
bcbdb6d0
CW		 1692 *
1693 * Also note that to prevent whole machine hangs on gen7, we have to
1694 * take the spinlock to guard against concurrent cacheline access.
9b9ed309 1695 */
bcbdb6d0 1696 spin_lock_irq(&dev_priv->uncore.lock);
c04e0f3b 1697 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
bcbdb6d0 1698 spin_unlock_irq(&dev_priv->uncore.lock);
4cd53c0c
DV		 1699}
1700
8187a2b7 1701static u32
c04e0f3b 1702ring_get_seqno(struct intel_engine_cs *engine)
8187a2b7 1703{
0bc40be8 1704 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1ec14ad3
CW		 1705}
1706
b70ec5bf 1707static void
0bc40be8 1708ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1709{
0bc40be8 1710 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
b70ec5bf
MK		 1711}
1712
c6df541c 1713static u32
c04e0f3b 1714pc_render_get_seqno(struct intel_engine_cs *engine)
c6df541c 1715{
0bc40be8 1716 return engine->scratch.cpu_page[0];
c6df541c
CW		 1717}
1718
b70ec5bf 1719static void
0bc40be8 1720pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1721{
0bc40be8 1722 engine->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1723}
1724
e48d8634 1725static bool
0bc40be8 1726gen5_ring_get_irq(struct intel_engine_cs *engine)
e48d8634 1727{
c033666a 1728 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1729 unsigned long flags;
e48d8634 1730
7cd512f1 1731 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1732 return false;
1733
7338aefa 1734 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1735 if (engine->irq_refcount++ == 0)
1736 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1738
1739 return true;
1740}
1741
1742static void
0bc40be8 1743gen5_ring_put_irq(struct intel_engine_cs *engine)
e48d8634 1744{
c033666a 1745 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1746 unsigned long flags;
e48d8634 1747
7338aefa 1748 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1749 if (--engine->irq_refcount == 0)
1750 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1751 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1752}
1753
b13c2b96 1754static bool
0bc40be8 1755i9xx_ring_get_irq(struct intel_engine_cs *engine)
62fdfeaf 1756{
c033666a 1757 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1758 unsigned long flags;
62fdfeaf 1759
7cd512f1 1760 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1761 return false;
1762
7338aefa 1763 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1764 if (engine->irq_refcount++ == 0) {
1765 dev_priv->irq_mask &= ~engine->irq_enable_mask;
f637fde4
DV		 1766 I915_WRITE(IMR, dev_priv->irq_mask);
1767 POSTING_READ(IMR);
1768 }
7338aefa 1769 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1770
1771 return true;
62fdfeaf
EA		 1772}
1773
8187a2b7 1774static void
0bc40be8 1775i9xx_ring_put_irq(struct intel_engine_cs *engine)
62fdfeaf 1776{
c033666a 1777 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1778 unsigned long flags;
62fdfeaf 1779
7338aefa 1780 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1781 if (--engine->irq_refcount == 0) {
1782 dev_priv->irq_mask |= engine->irq_enable_mask;
f637fde4
DV		 1783 I915_WRITE(IMR, dev_priv->irq_mask);
1784 POSTING_READ(IMR);
1785 }
7338aefa 1786 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1787}
1788
c2798b19 1789static bool
0bc40be8 1790i8xx_ring_get_irq(struct intel_engine_cs *engine)
c2798b19 1791{
c033666a 1792 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1793 unsigned long flags;
c2798b19 1794
7cd512f1 1795 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1796 return false;
1797
7338aefa 1798 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1799 if (engine->irq_refcount++ == 0) {
1800 dev_priv->irq_mask &= ~engine->irq_enable_mask;
c2798b19
CW		 1801 I915_WRITE16(IMR, dev_priv->irq_mask);
1802 POSTING_READ16(IMR);
1803 }
7338aefa 1804 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1805
1806 return true;
1807}
1808
1809static void
0bc40be8 1810i8xx_ring_put_irq(struct intel_engine_cs *engine)
c2798b19 1811{
c033666a 1812 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1813 unsigned long flags;
c2798b19 1814
7338aefa 1815 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1816 if (--engine->irq_refcount == 0) {
1817 dev_priv->irq_mask |= engine->irq_enable_mask;
c2798b19
CW		 1818 I915_WRITE16(IMR, dev_priv->irq_mask);
1819 POSTING_READ16(IMR);
1820 }
7338aefa 1821 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1822}
1823
b72f3acb 1824static int
a84c3ae1 1825bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1826 u32 invalidate_domains,
1827 u32 flush_domains)
d1b851fc 1828{
4a570db5 1829 struct intel_engine_cs *engine = req->engine;
b72f3acb
CW		 1830 int ret;
1831
5fb9de1a 1832 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1833 if (ret)
1834 return ret;
1835
e2f80391
TU		 1836 intel_ring_emit(engine, MI_FLUSH);
1837 intel_ring_emit(engine, MI_NOOP);
1838 intel_ring_advance(engine);
b72f3acb 1839 return 0;
d1b851fc
ZN		 1840}
1841
3cce469c 1842static int
ee044a88 1843i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1844{
4a570db5 1845 struct intel_engine_cs *engine = req->engine;
3cce469c
CW		 1846 int ret;
1847
5fb9de1a 1848 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1849 if (ret)
1850 return ret;
6f392d54 1851
e2f80391
TU		 1852 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1853 intel_ring_emit(engine,
1854 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1855 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1856 intel_ring_emit(engine, MI_USER_INTERRUPT);
1857 __intel_ring_advance(engine);
d1b851fc 1858
3cce469c 1859 return 0;
d1b851fc
ZN		 1860}
1861
0f46832f 1862static bool
0bc40be8 1863gen6_ring_get_irq(struct intel_engine_cs *engine)
0f46832f 1864{
c033666a 1865 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1866 unsigned long flags;
0f46832f 1867
7cd512f1
DV		 1868 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1869 return false;
0f46832f 1870
7338aefa 1871 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1872 if (engine->irq_refcount++ == 0) {
c033666a 1873 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
0bc40be8
TU		 1874 I915_WRITE_IMR(engine,
1875 ~(engine->irq_enable_mask |
c033666a 1876 GT_PARITY_ERROR(dev_priv)));
15b9f80e 1877 else
0bc40be8
TU		 1878 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1879 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
0f46832f 1880 }
7338aefa 1881 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1882
1883 return true;
1884}
1885
1886static void
0bc40be8 1887gen6_ring_put_irq(struct intel_engine_cs *engine)
0f46832f 1888{
c033666a 1889 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1890 unsigned long flags;
0f46832f 1891
7338aefa 1892 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1893 if (--engine->irq_refcount == 0) {
c033666a
CW		 1894 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1895 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
15b9f80e 1896 else
0bc40be8
TU		 1897 I915_WRITE_IMR(engine, ~0);
1898 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1ec14ad3 1899 }
7338aefa 1900 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1901}
1902
a19d2933 1903static bool
0bc40be8 1904hsw_vebox_get_irq(struct intel_engine_cs *engine)
a19d2933 1905{
c033666a 1906 struct drm_i915_private *dev_priv = engine->i915;
a19d2933
BW		 1907 unsigned long flags;
1908
7cd512f1 1909 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1910 return false;
1911
59cdb63d 1912 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1913 if (engine->irq_refcount++ == 0) {
1914 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1915 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1916 }
59cdb63d 1917 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1918
1919 return true;
1920}
1921
1922static void
0bc40be8 1923hsw_vebox_put_irq(struct intel_engine_cs *engine)
a19d2933 1924{
c033666a 1925 struct drm_i915_private *dev_priv = engine->i915;
a19d2933
BW		 1926 unsigned long flags;
1927
59cdb63d 1928 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1929 if (--engine->irq_refcount == 0) {
1930 I915_WRITE_IMR(engine, ~0);
1931 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1932 }
59cdb63d 1933 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1934}
1935
abd58f01 1936static bool
0bc40be8 1937gen8_ring_get_irq(struct intel_engine_cs *engine)
abd58f01 1938{
c033666a 1939 struct drm_i915_private *dev_priv = engine->i915;
abd58f01
BW		 1940 unsigned long flags;
1941
7cd512f1 1942 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1943 return false;
1944
1945 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1946 if (engine->irq_refcount++ == 0) {
c033666a 1947 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
0bc40be8
TU		 1948 I915_WRITE_IMR(engine,
1949 ~(engine->irq_enable_mask |
abd58f01
BW		 1950 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1951 } else {
0bc40be8 1952 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
abd58f01 1953 }
0bc40be8 1954 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1955 }
1956 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1957
1958 return true;
1959}
1960
1961static void
0bc40be8 1962gen8_ring_put_irq(struct intel_engine_cs *engine)
abd58f01 1963{
c033666a 1964 struct drm_i915_private *dev_priv = engine->i915;
abd58f01
BW		 1965 unsigned long flags;
1966
1967 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1968 if (--engine->irq_refcount == 0) {
c033666a 1969 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
0bc40be8 1970 I915_WRITE_IMR(engine,
abd58f01
BW		 1971 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1972 } else {
0bc40be8 1973 I915_WRITE_IMR(engine, ~0);
abd58f01 1974 }
0bc40be8 1975 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1976 }
1977 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1978}
1979
d1b851fc 1980static int
53fddaf7 1981i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1982 u64 offset, u32 length,
8e004efc 1983 unsigned dispatch_flags)
d1b851fc 1984{
4a570db5 1985 struct intel_engine_cs *engine = req->engine;
e1f99ce6 1986 int ret;
78501eac 1987
5fb9de1a 1988 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1989 if (ret)
1990 return ret;
1991
e2f80391 1992 intel_ring_emit(engine,
65f56876
CW		 1993 MI_BATCH_BUFFER_START |
1994 MI_BATCH_GTT |
8e004efc
JH		 1995 (dispatch_flags & I915_DISPATCH_SECURE ?
1996 0 : MI_BATCH_NON_SECURE_I965));
e2f80391
TU		 1997 intel_ring_emit(engine, offset);
1998 intel_ring_advance(engine);
78501eac 1999
d1b851fc
ZN		 2000 return 0;
2001}
2002
b45305fc
DV		 2003/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
2004#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 2005#define I830_TLB_ENTRIES (2)
2006#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 2007static int
53fddaf7 2008i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2009 u64 offset, u32 len,
2010 unsigned dispatch_flags)
62fdfeaf 2011{
4a570db5 2012 struct intel_engine_cs *engine = req->engine;
e2f80391 2013 u32 cs_offset = engine->scratch.gtt_offset;
c4e7a414 2014 int ret;
62fdfeaf 2015
5fb9de1a 2016 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 2017 if (ret)
2018 return ret;
62fdfeaf 2019
c4d69da1 2020 /* Evict the invalid PTE TLBs */
e2f80391
TU		 2021 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
2022 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
2023 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
2024 intel_ring_emit(engine, cs_offset);
2025 intel_ring_emit(engine, 0xdeadbeef);
2026 intel_ring_emit(engine, MI_NOOP);
2027 intel_ring_advance(engine);
b45305fc 2028
8e004efc 2029 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 2030 if (len > I830_BATCH_LIMIT)
2031 return -ENOSPC;
2032
5fb9de1a 2033 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 2034 if (ret)
2035 return ret;
c4d69da1
CW		 2036
2037 /* Blit the batch (which has now all relocs applied) to the
2038 * stable batch scratch bo area (so that the CS never
2039 * stumbles over its tlb invalidation bug) ...
2040 */
e2f80391
TU		 2041 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
2042 intel_ring_emit(engine,
2043 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
2044 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2045 intel_ring_emit(engine, cs_offset);
2046 intel_ring_emit(engine, 4096);
2047 intel_ring_emit(engine, offset);
2048
2049 intel_ring_emit(engine, MI_FLUSH);
2050 intel_ring_emit(engine, MI_NOOP);
2051 intel_ring_advance(engine);
b45305fc
DV		 2052
2053 /* ... and execute it. */
c4d69da1 2054 offset = cs_offset;
b45305fc 2055 }
e1f99ce6 2056
9d611c03 2057 ret = intel_ring_begin(req, 2);
c4d69da1
CW		 2058 if (ret)
2059 return ret;
2060
e2f80391
TU		 2061 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2062 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2063 0 : MI_BATCH_NON_SECURE));
2064 intel_ring_advance(engine);
c4d69da1 2065
fb3256da
DV		 2066 return 0;
2067}
2068
2069static int
53fddaf7 2070i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2071 u64 offset, u32 len,
8e004efc 2072 unsigned dispatch_flags)
fb3256da 2073{
4a570db5 2074 struct intel_engine_cs *engine = req->engine;
fb3256da
DV		 2075 int ret;
2076
5fb9de1a 2077 ret = intel_ring_begin(req, 2);
fb3256da
DV		 2078 if (ret)
2079 return ret;
2080
e2f80391
TU		 2081 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2082 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2083 0 : MI_BATCH_NON_SECURE));
2084 intel_ring_advance(engine);
62fdfeaf 2085
62fdfeaf
EA		 2086 return 0;
2087}
2088
0bc40be8 2089static void cleanup_phys_status_page(struct intel_engine_cs *engine)
7d3fdfff 2090{
c033666a 2091 struct drm_i915_private *dev_priv = engine->i915;
7d3fdfff
VS		 2092
2093 if (!dev_priv->status_page_dmah)
2094 return;
2095
c033666a 2096 drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
0bc40be8 2097 engine->status_page.page_addr = NULL;
7d3fdfff
VS		 2098}
2099
0bc40be8 2100static void cleanup_status_page(struct intel_engine_cs *engine)
62fdfeaf 2101{
05394f39 2102 struct drm_i915_gem_object *obj;
62fdfeaf 2103
0bc40be8 2104 obj = engine->status_page.obj;
8187a2b7 2105 if (obj == NULL)
62fdfeaf 2106 return;
62fdfeaf 2107
9da3da66 2108 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 2109 i915_gem_object_ggtt_unpin(obj);
05394f39 2110 drm_gem_object_unreference(&obj->base);
0bc40be8 2111 engine->status_page.obj = NULL;
62fdfeaf
EA		 2112}
2113
0bc40be8 2114static int init_status_page(struct intel_engine_cs *engine)
62fdfeaf 2115{
0bc40be8 2116 struct drm_i915_gem_object *obj = engine->status_page.obj;
62fdfeaf 2117
7d3fdfff 2118 if (obj == NULL) {
1f767e02 2119 unsigned flags;
e3efda49 2120 int ret;
e4ffd173 2121
c033666a 2122 obj = i915_gem_object_create(engine->i915->dev, 4096);
fe3db79b 2123 if (IS_ERR(obj)) {
e3efda49 2124 DRM_ERROR("Failed to allocate status page\n");
fe3db79b 2125 return PTR_ERR(obj);
e3efda49 2126 }
62fdfeaf 2127
e3efda49
CW		 2128 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2129 if (ret)
2130 goto err_unref;
2131
1f767e02 2132 flags = 0;
c033666a 2133 if (!HAS_LLC(engine->i915))
1f767e02
CW		 2134 /* On g33, we cannot place HWS above 256MiB, so
2135 * restrict its pinning to the low mappable arena.
2136 * Though this restriction is not documented for
2137 * gen4, gen5, or byt, they also behave similarly
2138 * and hang if the HWS is placed at the top of the
2139 * GTT. To generalise, it appears that all !llc
2140 * platforms have issues with us placing the HWS
2141 * above the mappable region (even though we never
2142 * actualy map it).
2143 */
2144 flags |= PIN_MAPPABLE;
2145 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 2146 if (ret) {
2147err_unref:
2148 drm_gem_object_unreference(&obj->base);
2149 return ret;
2150 }
2151
0bc40be8 2152 engine->status_page.obj = obj;
e3efda49 2153 }
62fdfeaf 2154
0bc40be8
TU		 2155 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2156 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2157 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 2158
8187a2b7 2159 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
0bc40be8 2160 engine->name, engine->status_page.gfx_addr);
62fdfeaf
EA		 2161
2162 return 0;
62fdfeaf
EA		 2163}
2164
0bc40be8 2165static int init_phys_status_page(struct intel_engine_cs *engine)
6b8294a4 2166{
c033666a 2167 struct drm_i915_private *dev_priv = engine->i915;
6b8294a4
CW		 2168
2169 if (!dev_priv->status_page_dmah) {
2170 dev_priv->status_page_dmah =
c033666a 2171 drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
6b8294a4
CW		 2172 if (!dev_priv->status_page_dmah)
2173 return -ENOMEM;
2174 }
2175
0bc40be8
TU		 2176 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2177 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
6b8294a4
CW		 2178
2179 return 0;
2180}
2181
7ba717cf 2182void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 2183{
3d77e9be
CW		 2184 GEM_BUG_ON(ringbuf->vma == NULL);
2185 GEM_BUG_ON(ringbuf->virtual_start == NULL);
2186
def0c5f6 2187 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
0a798eb9 2188 i915_gem_object_unpin_map(ringbuf->obj);
def0c5f6 2189 else
3d77e9be 2190 i915_vma_unpin_iomap(ringbuf->vma);
8305216f 2191 ringbuf->virtual_start = NULL;
3d77e9be 2192
2919d291 2193 i915_gem_object_ggtt_unpin(ringbuf->obj);
3d77e9be 2194 ringbuf->vma = NULL;
7ba717cf
TD		 2195}
2196
c033666a 2197int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
7ba717cf
TD		 2198 struct intel_ringbuffer *ringbuf)
2199{
7ba717cf 2200 struct drm_i915_gem_object *obj = ringbuf->obj;
a687a43a
CW		 2201 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2202 unsigned flags = PIN_OFFSET_BIAS | 4096;
8305216f 2203 void *addr;
7ba717cf
TD		 2204 int ret;
2205
def0c5f6 2206 if (HAS_LLC(dev_priv) && !obj->stolen) {
a687a43a 2207 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
def0c5f6
CW		 2208 if (ret)
2209 return ret;
7ba717cf 2210
def0c5f6 2211 ret = i915_gem_object_set_to_cpu_domain(obj, true);
d2cad535
CW		 2212 if (ret)
2213 goto err_unpin;
def0c5f6 2214
8305216f
DG		 2215 addr = i915_gem_object_pin_map(obj);
2216 if (IS_ERR(addr)) {
2217 ret = PTR_ERR(addr);
d2cad535 2218 goto err_unpin;
def0c5f6
CW		 2219 }
2220 } else {
a687a43a
CW		 2221 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2222 flags | PIN_MAPPABLE);
def0c5f6
CW		 2223 if (ret)
2224 return ret;
7ba717cf 2225
def0c5f6 2226 ret = i915_gem_object_set_to_gtt_domain(obj, true);
d2cad535
CW		 2227 if (ret)
2228 goto err_unpin;
def0c5f6 2229
ff3dc087
DCS		 2230 /* Access through the GTT requires the device to be awake. */
2231 assert_rpm_wakelock_held(dev_priv);
2232
3d77e9be
CW		 2233 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2234 if (IS_ERR(addr)) {
2235 ret = PTR_ERR(addr);
d2cad535 2236 goto err_unpin;
def0c5f6 2237 }
7ba717cf
TD		 2238 }
2239
8305216f 2240 ringbuf->virtual_start = addr;
0eb973d3 2241 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
7ba717cf 2242 return 0;
d2cad535
CW		 2243
2244err_unpin:
2245 i915_gem_object_ggtt_unpin(obj);
2246 return ret;
7ba717cf
TD		 2247}
2248
01101fa7 2249static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2250{
2919d291
OM		 2251 drm_gem_object_unreference(&ringbuf->obj->base);
2252 ringbuf->obj = NULL;
2253}
2254
01101fa7
CW		 2255static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2256 struct intel_ringbuffer *ringbuf)
62fdfeaf 2257{
05394f39 2258 struct drm_i915_gem_object *obj;
62fdfeaf 2259
ebc052e0
CW		 2260 obj = NULL;
2261 if (!HAS_LLC(dev))
93b0a4e0 2262 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2263 if (obj == NULL)
d37cd8a8 2264 obj = i915_gem_object_create(dev, ringbuf->size);
fe3db79b
CW		 2265 if (IS_ERR(obj))
2266 return PTR_ERR(obj);
8187a2b7 2267
24f3a8cf
AG		 2268 /* mark ring buffers as read-only from GPU side by default */
2269 obj->gt_ro = 1;
2270
93b0a4e0 2271 ringbuf->obj = obj;
e3efda49 2272
7ba717cf 2273 return 0;
e3efda49
CW		 2274}
2275
01101fa7
CW		 2276struct intel_ringbuffer *
2277intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2278{
2279 struct intel_ringbuffer *ring;
2280 int ret;
2281
2282 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2283 if (ring == NULL) {
2284 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2285 engine->name);
01101fa7 2286 return ERR_PTR(-ENOMEM);
608c1a52 2287 }
01101fa7 2288
4a570db5 2289 ring->engine = engine;
608c1a52 2290 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2291
2292 ring->size = size;
2293 /* Workaround an erratum on the i830 which causes a hang if
2294 * the TAIL pointer points to within the last 2 cachelines
2295 * of the buffer.
2296 */
2297 ring->effective_size = size;
c033666a 2298 if (IS_I830(engine->i915) || IS_845G(engine->i915))
01101fa7
CW		 2299 ring->effective_size -= 2 * CACHELINE_BYTES;
2300
2301 ring->last_retired_head = -1;
2302 intel_ring_update_space(ring);
2303
c033666a 2304 ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
01101fa7 2305 if (ret) {
608c1a52
CW		 2306 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2307 engine->name, ret);
2308 list_del(&ring->link);
01101fa7
CW		 2309 kfree(ring);
2310 return ERR_PTR(ret);
2311 }
2312
2313 return ring;
2314}
2315
2316void
2317intel_ringbuffer_free(struct intel_ringbuffer *ring)
2318{
2319 intel_destroy_ringbuffer_obj(ring);
608c1a52 2320 list_del(&ring->link);
01101fa7
CW		 2321 kfree(ring);
2322}
2323
e3efda49 2324static int intel_init_ring_buffer(struct drm_device *dev,
0bc40be8 2325 struct intel_engine_cs *engine)
e3efda49 2326{
c033666a 2327 struct drm_i915_private *dev_priv = to_i915(dev);
bfc882b4 2328 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2329 int ret;
2330
0bc40be8 2331 WARN_ON(engine->buffer);
bfc882b4 2332
c033666a 2333 engine->i915 = dev_priv;
0bc40be8
TU		 2334 INIT_LIST_HEAD(&engine->active_list);
2335 INIT_LIST_HEAD(&engine->request_list);
2336 INIT_LIST_HEAD(&engine->execlist_queue);
2337 INIT_LIST_HEAD(&engine->buffers);
2338 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2339 memset(engine->semaphore.sync_seqno, 0,
2340 sizeof(engine->semaphore.sync_seqno));
e3efda49 2341
0bc40be8 2342 init_waitqueue_head(&engine->irq_queue);
e3efda49 2343
0bc40be8 2344 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
b0366a54
DG		 2345 if (IS_ERR(ringbuf)) {
2346 ret = PTR_ERR(ringbuf);
2347 goto error;
2348 }
0bc40be8 2349 engine->buffer = ringbuf;
01101fa7 2350
c033666a 2351 if (I915_NEED_GFX_HWS(dev_priv)) {
0bc40be8 2352 ret = init_status_page(engine);
e3efda49 2353 if (ret)
8ee14975 2354 goto error;
e3efda49 2355 } else {
0bc40be8
TU		 2356 WARN_ON(engine->id != RCS);
2357 ret = init_phys_status_page(engine);
e3efda49 2358 if (ret)
8ee14975 2359 goto error;
e3efda49
CW		 2360 }
2361
c033666a 2362 ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
bfc882b4
DV		 2363 if (ret) {
2364 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
0bc40be8 2365 engine->name, ret);
bfc882b4
DV		 2366 intel_destroy_ringbuffer_obj(ringbuf);
2367 goto error;
e3efda49 2368 }
62fdfeaf 2369
0bc40be8 2370 ret = i915_cmd_parser_init_ring(engine);
44e895a8 2371 if (ret)
8ee14975
OM		 2372 goto error;
2373
8ee14975 2374 return 0;
351e3db2 2375
8ee14975 2376error:
117897f4 2377 intel_cleanup_engine(engine);
8ee14975 2378 return ret;
62fdfeaf
EA		 2379}
2380
117897f4 2381void intel_cleanup_engine(struct intel_engine_cs *engine)
62fdfeaf 2382{
6402c330 2383 struct drm_i915_private *dev_priv;
33626e6a 2384
117897f4 2385 if (!intel_engine_initialized(engine))
62fdfeaf
EA		 2386 return;
2387
c033666a 2388 dev_priv = engine->i915;
6402c330 2389
0bc40be8 2390 if (engine->buffer) {
117897f4 2391 intel_stop_engine(engine);
c033666a 2392 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
33626e6a 2393
0bc40be8
TU		 2394 intel_unpin_ringbuffer_obj(engine->buffer);
2395 intel_ringbuffer_free(engine->buffer);
2396 engine->buffer = NULL;
b0366a54 2397 }
78501eac 2398
0bc40be8
TU		 2399 if (engine->cleanup)
2400 engine->cleanup(engine);
8d19215b 2401
c033666a 2402 if (I915_NEED_GFX_HWS(dev_priv)) {
0bc40be8 2403 cleanup_status_page(engine);
7d3fdfff 2404 } else {
0bc40be8
TU		 2405 WARN_ON(engine->id != RCS);
2406 cleanup_phys_status_page(engine);
7d3fdfff 2407 }
44e895a8 2408
0bc40be8
TU		 2409 i915_cmd_parser_fini_ring(engine);
2410 i915_gem_batch_pool_fini(&engine->batch_pool);
c033666a 2411 engine->i915 = NULL;
62fdfeaf
EA		 2412}
2413
666796da 2414int intel_engine_idle(struct intel_engine_cs *engine)
3e960501 2415{
a4b3a571 2416 struct drm_i915_gem_request *req;
3e960501 2417
3e960501 2418 /* Wait upon the last request to be completed */
0bc40be8 2419 if (list_empty(&engine->request_list))
3e960501
CW		 2420 return 0;
2421
0bc40be8
TU		 2422 req = list_entry(engine->request_list.prev,
2423 struct drm_i915_gem_request,
2424 list);
b4716185
CW		 2425
2426 /* Make sure we do not trigger any retires */
2427 return __i915_wait_request(req,
c19ae989 2428 req->i915->mm.interruptible,
b4716185 2429 NULL, NULL);
3e960501
CW		 2430}
2431
6689cb2b 2432int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2433{
6310346e
CW		 2434 int ret;
2435
2436 /* Flush enough space to reduce the likelihood of waiting after
2437 * we start building the request - in which case we will just
2438 * have to repeat work.
2439 */
a0442461 2440 request->reserved_space += LEGACY_REQUEST_SIZE;
6310346e 2441
4a570db5 2442 request->ringbuf = request->engine->buffer;
6310346e
CW		 2443
2444 ret = intel_ring_begin(request, 0);
2445 if (ret)
2446 return ret;
2447
a0442461 2448 request->reserved_space -= LEGACY_REQUEST_SIZE;
6310346e 2449 return 0;
9d773091
CW		 2450}
2451
987046ad
CW		 2452static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2453{
2454 struct intel_ringbuffer *ringbuf = req->ringbuf;
2455 struct intel_engine_cs *engine = req->engine;
2456 struct drm_i915_gem_request *target;
2457
2458 intel_ring_update_space(ringbuf);
2459 if (ringbuf->space >= bytes)
2460 return 0;
2461
2462 /*
2463 * Space is reserved in the ringbuffer for finalising the request,
2464 * as that cannot be allowed to fail. During request finalisation,
2465 * reserved_space is set to 0 to stop the overallocation and the
2466 * assumption is that then we never need to wait (which has the
2467 * risk of failing with EINTR).
2468 *
2469 * See also i915_gem_request_alloc() and i915_add_request().
2470 */
0251a963 2471 GEM_BUG_ON(!req->reserved_space);
987046ad
CW		 2472
2473 list_for_each_entry(target, &engine->request_list, list) {
2474 unsigned space;
2475
79bbcc29 2476 /*
987046ad
CW		 2477 * The request queue is per-engine, so can contain requests
2478 * from multiple ringbuffers. Here, we must ignore any that
2479 * aren't from the ringbuffer we're considering.
79bbcc29 2480 */
987046ad
CW		 2481 if (target->ringbuf != ringbuf)
2482 continue;
2483
2484 /* Would completion of this request free enough space? */
2485 space = __intel_ring_space(target->postfix, ringbuf->tail,
2486 ringbuf->size);
2487 if (space >= bytes)
2488 break;
79bbcc29 2489 }
29b1b415 2490
987046ad
CW		 2491 if (WARN_ON(&target->list == &engine->request_list))
2492 return -ENOSPC;
2493
2494 return i915_wait_request(target);
29b1b415
JH		 2495}
2496
987046ad 2497int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
cbcc80df 2498{
987046ad 2499 struct intel_ringbuffer *ringbuf = req->ringbuf;
79bbcc29 2500 int remain_actual = ringbuf->size - ringbuf->tail;
987046ad
CW		 2501 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2502 int bytes = num_dwords * sizeof(u32);
2503 int total_bytes, wait_bytes;
79bbcc29 2504 bool need_wrap = false;
29b1b415 2505
0251a963 2506 total_bytes = bytes + req->reserved_space;
29b1b415 2507
79bbcc29
JH		 2508 if (unlikely(bytes > remain_usable)) {
2509 /*
2510 * Not enough space for the basic request. So need to flush
2511 * out the remainder and then wait for base + reserved.
2512 */
2513 wait_bytes = remain_actual + total_bytes;
2514 need_wrap = true;
987046ad
CW		 2515 } else if (unlikely(total_bytes > remain_usable)) {
2516 /*
2517 * The base request will fit but the reserved space
2518 * falls off the end. So we don't need an immediate wrap
2519 * and only need to effectively wait for the reserved
2520 * size space from the start of ringbuffer.
2521 */
0251a963 2522 wait_bytes = remain_actual + req->reserved_space;
79bbcc29 2523 } else {
987046ad
CW		 2524 /* No wrapping required, just waiting. */
2525 wait_bytes = total_bytes;
cbcc80df
MK		 2526 }
2527
987046ad
CW		 2528 if (wait_bytes > ringbuf->space) {
2529 int ret = wait_for_space(req, wait_bytes);
cbcc80df
MK		 2530 if (unlikely(ret))
2531 return ret;
79bbcc29 2532
987046ad 2533 intel_ring_update_space(ringbuf);
e075a32f
CW		 2534 if (unlikely(ringbuf->space < wait_bytes))
2535 return -EAGAIN;
cbcc80df
MK		 2536 }
2537
987046ad
CW		 2538 if (unlikely(need_wrap)) {
2539 GEM_BUG_ON(remain_actual > ringbuf->space);
2540 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
78501eac 2541
987046ad
CW		 2542 /* Fill the tail with MI_NOOP */
2543 memset(ringbuf->virtual_start + ringbuf->tail,
2544 0, remain_actual);
2545 ringbuf->tail = 0;
2546 ringbuf->space -= remain_actual;
2547 }
304d695c 2548
987046ad
CW		 2549 ringbuf->space -= bytes;
2550 GEM_BUG_ON(ringbuf->space < 0);
304d695c 2551 return 0;
8187a2b7 2552}
78501eac 2553
753b1ad4 2554/* Align the ring tail to a cacheline boundary */
bba09b12 2555int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2556{
4a570db5 2557 struct intel_engine_cs *engine = req->engine;
e2f80391 2558 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2559 int ret;
2560
2561 if (num_dwords == 0)
2562 return 0;
2563
18393f63 2564 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2565 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2566 if (ret)
2567 return ret;
2568
2569 while (num_dwords--)
e2f80391 2570 intel_ring_emit(engine, MI_NOOP);
753b1ad4 2571
e2f80391 2572 intel_ring_advance(engine);
753b1ad4
VS		 2573
2574 return 0;
2575}
2576
0bc40be8 2577void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
498d2ac1 2578{
c033666a 2579 struct drm_i915_private *dev_priv = engine->i915;
498d2ac1 2580
29dcb570
CW		 2581 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2582 * so long as the semaphore value in the register/page is greater
2583 * than the sync value), so whenever we reset the seqno,
2584 * so long as we reset the tracking semaphore value to 0, it will
2585 * always be before the next request's seqno. If we don't reset
2586 * the semaphore value, then when the seqno moves backwards all
2587 * future waits will complete instantly (causing rendering corruption).
2588 */
7e22dbbb 2589 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
0bc40be8
TU		 2590 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2591 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
d04bce48 2592 if (HAS_VEBOX(dev_priv))
0bc40be8 2593 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
e1f99ce6 2594 }
a058d934
CW		 2595 if (dev_priv->semaphore_obj) {
2596 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2597 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2598 void *semaphores = kmap(page);
2599 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2600 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2601 kunmap(page);
2602 }
29dcb570
CW		 2603 memset(engine->semaphore.sync_seqno, 0,
2604 sizeof(engine->semaphore.sync_seqno));
d97ed339 2605
0bc40be8 2606 engine->set_seqno(engine, seqno);
01347126 2607 engine->last_submitted_seqno = seqno;
29dcb570 2608
0bc40be8 2609 engine->hangcheck.seqno = seqno;
8187a2b7 2610}
62fdfeaf 2611
0bc40be8 2612static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 2613 u32 value)
881f47b6 2614{
c033666a 2615 struct drm_i915_private *dev_priv = engine->i915;
881f47b6
XH		 2616
2617 /* Every tail move must follow the sequence below */
12f55818
CW		 2618
2619 /* Disable notification that the ring is IDLE. The GT
2620 * will then assume that it is busy and bring it out of rc6.
2621 */
0206e353 2622 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2623 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2624
2625 /* Clear the context id. Here be magic! */
2626 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2627
12f55818 2628 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2629 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2630 GEN6_BSD_SLEEP_INDICATOR) == 0,
2631 50))
2632 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2633
12f55818 2634 /* Now that the ring is fully powered up, update the tail */
0bc40be8
TU		 2635 I915_WRITE_TAIL(engine, value);
2636 POSTING_READ(RING_TAIL(engine->mmio_base));
12f55818
CW		 2637
2638 /* Let the ring send IDLE messages to the GT again,
2639 * and so let it sleep to conserve power when idle.
2640 */
0206e353 2641 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2642 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2643}
2644
a84c3ae1 2645static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2646 u32 invalidate, u32 flush)
881f47b6 2647{
4a570db5 2648 struct intel_engine_cs *engine = req->engine;
71a77e07 2649 uint32_t cmd;
b72f3acb
CW		 2650 int ret;
2651
5fb9de1a 2652 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2653 if (ret)
2654 return ret;
2655
71a77e07 2656 cmd = MI_FLUSH_DW;
c033666a 2657 if (INTEL_GEN(req->i915) >= 8)
075b3bba 2658 cmd += 1;
f0a1fb10
CW		 2659
2660 /* We always require a command barrier so that subsequent
2661 * commands, such as breadcrumb interrupts, are strictly ordered
2662 * wrt the contents of the write cache being flushed to memory
2663 * (and thus being coherent from the CPU).
2664 */
2665 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2666
9a289771
JB		 2667 /*
2668 * Bspec vol 1c.5 - video engine command streamer:
2669 * "If ENABLED, all TLBs will be invalidated once the flush
2670 * operation is complete. This bit is only valid when the
2671 * Post-Sync Operation field is a value of 1h or 3h."
2672 */
71a77e07 2673 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2674 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2675
e2f80391
TU		 2676 intel_ring_emit(engine, cmd);
2677 intel_ring_emit(engine,
2678 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
c033666a 2679 if (INTEL_GEN(req->i915) >= 8) {
e2f80391
TU		 2680 intel_ring_emit(engine, 0); /* upper addr */
2681 intel_ring_emit(engine, 0); /* value */
075b3bba 2682 } else {
e2f80391
TU		 2683 intel_ring_emit(engine, 0);
2684 intel_ring_emit(engine, MI_NOOP);
075b3bba 2685 }
e2f80391 2686 intel_ring_advance(engine);
b72f3acb 2687 return 0;
881f47b6
XH		 2688}
2689
1c7a0623 2690static int
53fddaf7 2691gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2692 u64 offset, u32 len,
8e004efc 2693 unsigned dispatch_flags)
1c7a0623 2694{
4a570db5 2695 struct intel_engine_cs *engine = req->engine;
e2f80391 2696 bool ppgtt = USES_PPGTT(engine->dev) &&
8e004efc 2697 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2698 int ret;
2699
5fb9de1a 2700 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2701 if (ret)
2702 return ret;
2703
2704 /* FIXME(BDW): Address space and security selectors. */
e2f80391 2705 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
919032ec
AJ		 2706 (dispatch_flags & I915_DISPATCH_RS ?
2707 MI_BATCH_RESOURCE_STREAMER : 0));
e2f80391
TU		 2708 intel_ring_emit(engine, lower_32_bits(offset));
2709 intel_ring_emit(engine, upper_32_bits(offset));
2710 intel_ring_emit(engine, MI_NOOP);
2711 intel_ring_advance(engine);
1c7a0623
BW		 2712
2713 return 0;
2714}
2715
d7d4eedd 2716static int
53fddaf7 2717hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2718 u64 offset, u32 len,
2719 unsigned dispatch_flags)
d7d4eedd 2720{
4a570db5 2721 struct intel_engine_cs *engine = req->engine;
d7d4eedd
CW		 2722 int ret;
2723
5fb9de1a 2724 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2725 if (ret)
2726 return ret;
2727
e2f80391 2728 intel_ring_emit(engine,
77072258 2729 MI_BATCH_BUFFER_START |
8e004efc 2730 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2731 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2732 (dispatch_flags & I915_DISPATCH_RS ?
2733 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd 2734 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2735 intel_ring_emit(engine, offset);
2736 intel_ring_advance(engine);
d7d4eedd
CW		 2737
2738 return 0;
2739}
2740
881f47b6 2741static int
53fddaf7 2742gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2743 u64 offset, u32 len,
8e004efc 2744 unsigned dispatch_flags)
881f47b6 2745{
4a570db5 2746 struct intel_engine_cs *engine = req->engine;
0206e353 2747 int ret;
ab6f8e32 2748
5fb9de1a 2749 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2750 if (ret)
2751 return ret;
e1f99ce6 2752
e2f80391 2753 intel_ring_emit(engine,
d7d4eedd 2754 MI_BATCH_BUFFER_START |
8e004efc
JH		 2755 (dispatch_flags & I915_DISPATCH_SECURE ?
2756 0 : MI_BATCH_NON_SECURE_I965));
0206e353 2757 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2758 intel_ring_emit(engine, offset);
2759 intel_ring_advance(engine);
ab6f8e32 2760
0206e353 2761 return 0;
881f47b6
XH		 2762}
2763
549f7365
CW		 2764/* Blitter support (SandyBridge+) */
2765
a84c3ae1 2766static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2767 u32 invalidate, u32 flush)
8d19215b 2768{
4a570db5 2769 struct intel_engine_cs *engine = req->engine;
71a77e07 2770 uint32_t cmd;
b72f3acb
CW		 2771 int ret;
2772
5fb9de1a 2773 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2774 if (ret)
2775 return ret;
2776
71a77e07 2777 cmd = MI_FLUSH_DW;
c033666a 2778 if (INTEL_GEN(req->i915) >= 8)
075b3bba 2779 cmd += 1;
f0a1fb10
CW		 2780
2781 /* We always require a command barrier so that subsequent
2782 * commands, such as breadcrumb interrupts, are strictly ordered
2783 * wrt the contents of the write cache being flushed to memory
2784 * (and thus being coherent from the CPU).
2785 */
2786 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2787
9a289771
JB		 2788 /*
2789 * Bspec vol 1c.3 - blitter engine command streamer:
2790 * "If ENABLED, all TLBs will be invalidated once the flush
2791 * operation is complete. This bit is only valid when the
2792 * Post-Sync Operation field is a value of 1h or 3h."
2793 */
71a77e07 2794 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2795 cmd |= MI_INVALIDATE_TLB;
e2f80391
TU		 2796 intel_ring_emit(engine, cmd);
2797 intel_ring_emit(engine,
2798 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
c033666a 2799 if (INTEL_GEN(req->i915) >= 8) {
e2f80391
TU		 2800 intel_ring_emit(engine, 0); /* upper addr */
2801 intel_ring_emit(engine, 0); /* value */
075b3bba 2802 } else {
e2f80391
TU		 2803 intel_ring_emit(engine, 0);
2804 intel_ring_emit(engine, MI_NOOP);
075b3bba 2805 }
e2f80391 2806 intel_ring_advance(engine);
fd3da6c9 2807
b72f3acb 2808 return 0;
8d19215b
ZN		 2809}
2810
5c1143bb
XH		 2811int intel_init_render_ring_buffer(struct drm_device *dev)
2812{
4640c4ff 2813 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2814 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
3e78998a
BW		 2815 struct drm_i915_gem_object *obj;
2816 int ret;
5c1143bb 2817
e2f80391
TU		 2818 engine->name = "render ring";
2819 engine->id = RCS;
2820 engine->exec_id = I915_EXEC_RENDER;
215a7e32 2821 engine->hw_id = 0;
e2f80391 2822 engine->mmio_base = RENDER_RING_BASE;
59465b5f 2823
c033666a
CW		 2824 if (INTEL_GEN(dev_priv) >= 8) {
2825 if (i915_semaphore_is_enabled(dev_priv)) {
d37cd8a8 2826 obj = i915_gem_object_create(dev, 4096);
fe3db79b 2827 if (IS_ERR(obj)) {
3e78998a
BW		 2828 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2829 i915.semaphores = 0;
2830 } else {
2831 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2832 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2833 if (ret != 0) {
2834 drm_gem_object_unreference(&obj->base);
2835 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2836 i915.semaphores = 0;
2837 } else
2838 dev_priv->semaphore_obj = obj;
2839 }
2840 }
7225342a 2841
e2f80391 2842 engine->init_context = intel_rcs_ctx_init;
a58c01aa 2843 engine->add_request = gen8_render_add_request;
e2f80391
TU		 2844 engine->flush = gen8_render_ring_flush;
2845 engine->irq_get = gen8_ring_get_irq;
2846 engine->irq_put = gen8_ring_put_irq;
2847 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b 2848 engine->get_seqno = ring_get_seqno;
e2f80391 2849 engine->set_seqno = ring_set_seqno;
c033666a 2850 if (i915_semaphore_is_enabled(dev_priv)) {
3e78998a 2851 WARN_ON(!dev_priv->semaphore_obj);
e2f80391
TU		 2852 engine->semaphore.sync_to = gen8_ring_sync;
2853 engine->semaphore.signal = gen8_rcs_signal;
2854 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2855 }
c033666a 2856 } else if (INTEL_GEN(dev_priv) >= 6) {
e2f80391
TU		 2857 engine->init_context = intel_rcs_ctx_init;
2858 engine->add_request = gen6_add_request;
2859 engine->flush = gen7_render_ring_flush;
c033666a 2860 if (IS_GEN6(dev_priv))
e2f80391
TU		 2861 engine->flush = gen6_render_ring_flush;
2862 engine->irq_get = gen6_ring_get_irq;
2863 engine->irq_put = gen6_ring_put_irq;
2864 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b
CW		 2865 engine->irq_seqno_barrier = gen6_seqno_barrier;
2866 engine->get_seqno = ring_get_seqno;
e2f80391 2867 engine->set_seqno = ring_set_seqno;
c033666a 2868 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2869 engine->semaphore.sync_to = gen6_ring_sync;
2870 engine->semaphore.signal = gen6_signal;
707d9cf9
BW		 2871 /*
2872 * The current semaphore is only applied on pre-gen8
2873 * platform. And there is no VCS2 ring on the pre-gen8
2874 * platform. So the semaphore between RCS and VCS2 is
2875 * initialized as INVALID. Gen8 will initialize the
2876 * sema between VCS2 and RCS later.
2877 */
e2f80391
TU		 2878 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2879 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2880 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2881 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2882 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2883 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2884 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2885 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2886 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2887 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2888 }
c033666a 2889 } else if (IS_GEN5(dev_priv)) {
e2f80391
TU		 2890 engine->add_request = pc_render_add_request;
2891 engine->flush = gen4_render_ring_flush;
2892 engine->get_seqno = pc_render_get_seqno;
2893 engine->set_seqno = pc_render_set_seqno;
2894 engine->irq_get = gen5_ring_get_irq;
2895 engine->irq_put = gen5_ring_put_irq;
2896 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
cc609d5d 2897 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2898 } else {
e2f80391 2899 engine->add_request = i9xx_add_request;
c033666a 2900 if (INTEL_GEN(dev_priv) < 4)
e2f80391 2901 engine->flush = gen2_render_ring_flush;
46f0f8d1 2902 else
e2f80391
TU		 2903 engine->flush = gen4_render_ring_flush;
2904 engine->get_seqno = ring_get_seqno;
2905 engine->set_seqno = ring_set_seqno;
c033666a 2906 if (IS_GEN2(dev_priv)) {
e2f80391
TU		 2907 engine->irq_get = i8xx_ring_get_irq;
2908 engine->irq_put = i8xx_ring_put_irq;
c2798b19 2909 } else {
e2f80391
TU		 2910 engine->irq_get = i9xx_ring_get_irq;
2911 engine->irq_put = i9xx_ring_put_irq;
c2798b19 2912 }
e2f80391 2913 engine->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2914 }
e2f80391 2915 engine->write_tail = ring_write_tail;
707d9cf9 2916
c033666a 2917 if (IS_HASWELL(dev_priv))
e2f80391 2918 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
c033666a 2919 else if (IS_GEN8(dev_priv))
e2f80391 2920 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 2921 else if (INTEL_GEN(dev_priv) >= 6)
e2f80391 2922 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 2923 else if (INTEL_GEN(dev_priv) >= 4)
e2f80391 2924 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
c033666a 2925 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
e2f80391 2926 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
fb3256da 2927 else
e2f80391
TU		 2928 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2929 engine->init_hw = init_render_ring;
2930 engine->cleanup = render_ring_cleanup;
59465b5f 2931
b45305fc 2932 /* Workaround batchbuffer to combat CS tlb bug. */
c033666a 2933 if (HAS_BROKEN_CS_TLB(dev_priv)) {
d37cd8a8 2934 obj = i915_gem_object_create(dev, I830_WA_SIZE);
fe3db79b 2935 if (IS_ERR(obj)) {
b45305fc 2936 DRM_ERROR("Failed to allocate batch bo\n");
fe3db79b 2937 return PTR_ERR(obj);
b45305fc
DV		 2938 }
2939
be1fa129 2940 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2941 if (ret != 0) {
2942 drm_gem_object_unreference(&obj->base);
2943 DRM_ERROR("Failed to ping batch bo\n");
2944 return ret;
2945 }
2946
e2f80391
TU		 2947 engine->scratch.obj = obj;
2948 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2949 }
2950
e2f80391 2951 ret = intel_init_ring_buffer(dev, engine);
99be1dfe
DV		 2952 if (ret)
2953 return ret;
2954
c033666a 2955 if (INTEL_GEN(dev_priv) >= 5) {
e2f80391 2956 ret = intel_init_pipe_control(engine);
99be1dfe
DV		 2957 if (ret)
2958 return ret;
2959 }
2960
2961 return 0;
5c1143bb
XH		 2962}
2963
2964int intel_init_bsd_ring_buffer(struct drm_device *dev)
2965{
4640c4ff 2966 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2967 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
5c1143bb 2968
e2f80391
TU		 2969 engine->name = "bsd ring";
2970 engine->id = VCS;
2971 engine->exec_id = I915_EXEC_BSD;
215a7e32 2972 engine->hw_id = 1;
58fa3835 2973
e2f80391 2974 engine->write_tail = ring_write_tail;
c033666a 2975 if (INTEL_GEN(dev_priv) >= 6) {
e2f80391 2976 engine->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201 2977 /* gen6 bsd needs a special wa for tail updates */
c033666a 2978 if (IS_GEN6(dev_priv))
e2f80391
TU		 2979 engine->write_tail = gen6_bsd_ring_write_tail;
2980 engine->flush = gen6_bsd_ring_flush;
2981 engine->add_request = gen6_add_request;
c04e0f3b
CW		 2982 engine->irq_seqno_barrier = gen6_seqno_barrier;
2983 engine->get_seqno = ring_get_seqno;
e2f80391 2984 engine->set_seqno = ring_set_seqno;
c033666a 2985 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 2986 engine->irq_enable_mask =
abd58f01 2987 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
e2f80391
TU		 2988 engine->irq_get = gen8_ring_get_irq;
2989 engine->irq_put = gen8_ring_put_irq;
2990 engine->dispatch_execbuffer =
1c7a0623 2991 gen8_ring_dispatch_execbuffer;
c033666a 2992 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2993 engine->semaphore.sync_to = gen8_ring_sync;
2994 engine->semaphore.signal = gen8_xcs_signal;
2995 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2996 }
abd58f01 2997 } else {
e2f80391
TU		 2998 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2999 engine->irq_get = gen6_ring_get_irq;
3000 engine->irq_put = gen6_ring_put_irq;
3001 engine->dispatch_execbuffer =
1c7a0623 3002 gen6_ring_dispatch_execbuffer;
c033666a 3003 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3004 engine->semaphore.sync_to = gen6_ring_sync;
3005 engine->semaphore.signal = gen6_signal;
3006 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
3007 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
3008 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
3009 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
3010 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3011 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
3012 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
3013 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
3014 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
3015 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3016 }
abd58f01 3017 }
58fa3835 3018 } else {
e2f80391
TU		 3019 engine->mmio_base = BSD_RING_BASE;
3020 engine->flush = bsd_ring_flush;
3021 engine->add_request = i9xx_add_request;
3022 engine->get_seqno = ring_get_seqno;
3023 engine->set_seqno = ring_set_seqno;
c033666a 3024 if (IS_GEN5(dev_priv)) {
e2f80391
TU		 3025 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3026 engine->irq_get = gen5_ring_get_irq;
3027 engine->irq_put = gen5_ring_put_irq;
e48d8634 3028 } else {
e2f80391
TU		 3029 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3030 engine->irq_get = i9xx_ring_get_irq;
3031 engine->irq_put = i9xx_ring_put_irq;
e48d8634 3032 }
e2f80391 3033 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 3034 }
e2f80391 3035 engine->init_hw = init_ring_common;
58fa3835 3036
e2f80391 3037 return intel_init_ring_buffer(dev, engine);
5c1143bb 3038}
549f7365 3039
845f74a7 3040/**
62659920 3041 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 3042 */
3043int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3044{
3045 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3046 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
e2f80391
TU		 3047
3048 engine->name = "bsd2 ring";
3049 engine->id = VCS2;
3050 engine->exec_id = I915_EXEC_BSD;
215a7e32 3051 engine->hw_id = 4;
e2f80391
TU		 3052
3053 engine->write_tail = ring_write_tail;
3054 engine->mmio_base = GEN8_BSD2_RING_BASE;
3055 engine->flush = gen6_bsd_ring_flush;
3056 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3057 engine->irq_seqno_barrier = gen6_seqno_barrier;
3058 engine->get_seqno = ring_get_seqno;
e2f80391
TU		 3059 engine->set_seqno = ring_set_seqno;
3060 engine->irq_enable_mask =
845f74a7 3061 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
e2f80391
TU		 3062 engine->irq_get = gen8_ring_get_irq;
3063 engine->irq_put = gen8_ring_put_irq;
3064 engine->dispatch_execbuffer =
845f74a7 3065 gen8_ring_dispatch_execbuffer;
c033666a 3066 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3067 engine->semaphore.sync_to = gen8_ring_sync;
3068 engine->semaphore.signal = gen8_xcs_signal;
3069 GEN8_RING_SEMAPHORE_INIT(engine);
3e78998a 3070 }
e2f80391 3071 engine->init_hw = init_ring_common;
845f74a7 3072
e2f80391 3073 return intel_init_ring_buffer(dev, engine);
845f74a7
ZY		 3074}
3075
549f7365
CW		 3076int intel_init_blt_ring_buffer(struct drm_device *dev)
3077{
4640c4ff 3078 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3079 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
e2f80391
TU		 3080
3081 engine->name = "blitter ring";
3082 engine->id = BCS;
3083 engine->exec_id = I915_EXEC_BLT;
215a7e32 3084 engine->hw_id = 2;
e2f80391
TU		 3085
3086 engine->mmio_base = BLT_RING_BASE;
3087 engine->write_tail = ring_write_tail;
3088 engine->flush = gen6_ring_flush;
3089 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3090 engine->irq_seqno_barrier = gen6_seqno_barrier;
3091 engine->get_seqno = ring_get_seqno;
e2f80391 3092 engine->set_seqno = ring_set_seqno;
c033666a 3093 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 3094 engine->irq_enable_mask =
abd58f01 3095 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
e2f80391
TU		 3096 engine->irq_get = gen8_ring_get_irq;
3097 engine->irq_put = gen8_ring_put_irq;
3098 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 3099 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3100 engine->semaphore.sync_to = gen8_ring_sync;
3101 engine->semaphore.signal = gen8_xcs_signal;
3102 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3103 }
abd58f01 3104 } else {
e2f80391
TU		 3105 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3106 engine->irq_get = gen6_ring_get_irq;
3107 engine->irq_put = gen6_ring_put_irq;
3108 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 3109 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3110 engine->semaphore.signal = gen6_signal;
3111 engine->semaphore.sync_to = gen6_ring_sync;
707d9cf9
BW		 3112 /*
3113 * The current semaphore is only applied on pre-gen8
3114 * platform. And there is no VCS2 ring on the pre-gen8
3115 * platform. So the semaphore between BCS and VCS2 is
3116 * initialized as INVALID. Gen8 will initialize the
3117 * sema between BCS and VCS2 later.
3118 */
e2f80391
TU		 3119 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3120 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3121 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3122 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3123 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3124 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3125 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3126 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3127 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3128 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3129 }
abd58f01 3130 }
e2f80391 3131 engine->init_hw = init_ring_common;
549f7365 3132
e2f80391 3133 return intel_init_ring_buffer(dev, engine);
549f7365 3134}
a7b9761d 3135
9a8a2213
BW		 3136int intel_init_vebox_ring_buffer(struct drm_device *dev)
3137{
4640c4ff 3138 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3139 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
9a8a2213 3140
e2f80391
TU		 3141 engine->name = "video enhancement ring";
3142 engine->id = VECS;
3143 engine->exec_id = I915_EXEC_VEBOX;
215a7e32 3144 engine->hw_id = 3;
9a8a2213 3145
e2f80391
TU		 3146 engine->mmio_base = VEBOX_RING_BASE;
3147 engine->write_tail = ring_write_tail;
3148 engine->flush = gen6_ring_flush;
3149 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3150 engine->irq_seqno_barrier = gen6_seqno_barrier;
3151 engine->get_seqno = ring_get_seqno;
e2f80391 3152 engine->set_seqno = ring_set_seqno;
abd58f01 3153
c033666a 3154 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 3155 engine->irq_enable_mask =
40c499f9 3156 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
e2f80391
TU		 3157 engine->irq_get = gen8_ring_get_irq;
3158 engine->irq_put = gen8_ring_put_irq;
3159 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 3160 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3161 engine->semaphore.sync_to = gen8_ring_sync;
3162 engine->semaphore.signal = gen8_xcs_signal;
3163 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3164 }
abd58f01 3165 } else {
e2f80391
TU		 3166 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3167 engine->irq_get = hsw_vebox_get_irq;
3168 engine->irq_put = hsw_vebox_put_irq;
3169 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 3170 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3171 engine->semaphore.sync_to = gen6_ring_sync;
3172 engine->semaphore.signal = gen6_signal;
3173 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3174 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3175 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3176 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3177 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3178 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3179 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3180 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3181 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3182 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3183 }
abd58f01 3184 }
e2f80391 3185 engine->init_hw = init_ring_common;
9a8a2213 3186
e2f80391 3187 return intel_init_ring_buffer(dev, engine);
9a8a2213
BW		 3188}
3189
a7b9761d 3190int
4866d729 3191intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3192{
4a570db5 3193 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3194 int ret;
3195
e2f80391 3196 if (!engine->gpu_caches_dirty)
a7b9761d
CW		 3197 return 0;
3198
e2f80391 3199 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3200 if (ret)
3201 return ret;
3202
a84c3ae1 3203 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d 3204
e2f80391 3205 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3206 return 0;
3207}
3208
3209int
2f20055d 3210intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3211{
4a570db5 3212 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3213 uint32_t flush_domains;
3214 int ret;
3215
3216 flush_domains = 0;
e2f80391 3217 if (engine->gpu_caches_dirty)
a7b9761d
CW		 3218 flush_domains = I915_GEM_GPU_DOMAINS;
3219
e2f80391 3220 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3221 if (ret)
3222 return ret;
3223
a84c3ae1 3224 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d 3225
e2f80391 3226 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3227 return 0;
3228}
e3efda49
CW		 3229
3230void
117897f4 3231intel_stop_engine(struct intel_engine_cs *engine)
e3efda49
CW		 3232{
3233 int ret;
3234
117897f4 3235 if (!intel_engine_initialized(engine))
e3efda49
CW		 3236 return;
3237
666796da 3238 ret = intel_engine_idle(engine);
f4457ae7 3239 if (ret)
e3efda49 3240 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
0bc40be8 3241 engine->name, ret);
e3efda49 3242
0bc40be8 3243 stop_ring(engine);
e3efda49 3244}
Linux kernel - Deliverables
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