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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 ZN |
51 | static void |
52 | render_ring_flush(struct drm_device *dev, | |
ab6f8e32 CW |
53 | struct intel_ring_buffer *ring, |
54 | u32 invalidate_domains, | |
55 | u32 flush_domains) | |
62fdfeaf | 56 | { |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
112 | #if WATCH_EXEC | |
113 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
114 | #endif | |
be26a10b | 115 | intel_ring_begin(dev, ring, 2); |
8187a2b7 ZN |
116 | intel_ring_emit(dev, ring, cmd); |
117 | intel_ring_emit(dev, ring, MI_NOOP); | |
118 | intel_ring_advance(dev, ring); | |
62fdfeaf | 119 | } |
8187a2b7 ZN |
120 | } |
121 | ||
870e86dd DV |
122 | static void ring_set_tail(struct drm_device *dev, |
123 | struct intel_ring_buffer *ring, | |
124 | u32 value) | |
d46eefa2 XH |
125 | { |
126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
870e86dd | 127 | I915_WRITE_TAIL(ring, ring->tail); |
d46eefa2 XH |
128 | } |
129 | ||
79f321b7 DV |
130 | u32 intel_ring_get_active_head(struct drm_device *dev, |
131 | struct intel_ring_buffer *ring) | |
8187a2b7 ZN |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3d281d8c DV |
134 | u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ? |
135 | RING_ACTHD(ring->mmio_base) : ACTHD; | |
8187a2b7 ZN |
136 | |
137 | return I915_READ(acthd_reg); | |
138 | } | |
139 | ||
8187a2b7 | 140 | static int init_ring_common(struct drm_device *dev, |
ab6f8e32 | 141 | struct intel_ring_buffer *ring) |
8187a2b7 ZN |
142 | { |
143 | u32 head; | |
144 | drm_i915_private_t *dev_priv = dev->dev_private; | |
145 | struct drm_i915_gem_object *obj_priv; | |
146 | obj_priv = to_intel_bo(ring->gem_object); | |
147 | ||
148 | /* Stop the ring if it's running. */ | |
7f2ab699 | 149 | I915_WRITE_CTL(ring, 0); |
570ef608 | 150 | I915_WRITE_HEAD(ring, 0); |
870e86dd | 151 | ring->set_tail(dev, ring, 0); |
8187a2b7 ZN |
152 | |
153 | /* Initialize the ring. */ | |
6c0e1c55 | 154 | I915_WRITE_START(ring, obj_priv->gtt_offset); |
570ef608 | 155 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
156 | |
157 | /* G45 ring initialization fails to reset head to zero */ | |
158 | if (head != 0) { | |
159 | DRM_ERROR("%s head not reset to zero " | |
160 | "ctl %08x head %08x tail %08x start %08x\n", | |
161 | ring->name, | |
7f2ab699 | 162 | I915_READ_CTL(ring), |
570ef608 | 163 | I915_READ_HEAD(ring), |
870e86dd | 164 | I915_READ_TAIL(ring), |
6c0e1c55 | 165 | I915_READ_START(ring)); |
8187a2b7 | 166 | |
570ef608 | 167 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
168 | |
169 | DRM_ERROR("%s head forced to zero " | |
170 | "ctl %08x head %08x tail %08x start %08x\n", | |
171 | ring->name, | |
7f2ab699 | 172 | I915_READ_CTL(ring), |
570ef608 | 173 | I915_READ_HEAD(ring), |
870e86dd | 174 | I915_READ_TAIL(ring), |
6c0e1c55 | 175 | I915_READ_START(ring)); |
8187a2b7 ZN |
176 | } |
177 | ||
7f2ab699 | 178 | I915_WRITE_CTL(ring, |
8187a2b7 ZN |
179 | ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES) |
180 | | RING_NO_REPORT | RING_VALID); | |
181 | ||
570ef608 | 182 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
183 | /* If the head is still not zero, the ring is dead */ |
184 | if (head != 0) { | |
185 | DRM_ERROR("%s initialization failed " | |
186 | "ctl %08x head %08x tail %08x start %08x\n", | |
187 | ring->name, | |
7f2ab699 | 188 | I915_READ_CTL(ring), |
570ef608 | 189 | I915_READ_HEAD(ring), |
870e86dd | 190 | I915_READ_TAIL(ring), |
6c0e1c55 | 191 | I915_READ_START(ring)); |
8187a2b7 ZN |
192 | return -EIO; |
193 | } | |
194 | ||
195 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
196 | i915_kernel_lost_context(dev); | |
197 | else { | |
570ef608 | 198 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 199 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
200 | ring->space = ring->head - (ring->tail + 8); |
201 | if (ring->space < 0) | |
202 | ring->space += ring->size; | |
203 | } | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static int init_render_ring(struct drm_device *dev, | |
ab6f8e32 | 208 | struct intel_ring_buffer *ring) |
8187a2b7 ZN |
209 | { |
210 | drm_i915_private_t *dev_priv = dev->dev_private; | |
211 | int ret = init_ring_common(dev, ring); | |
a69ffdbf ZW |
212 | int mode; |
213 | ||
a6c45cf0 | 214 | if (INTEL_INFO(dev)->gen > 3) { |
a69ffdbf ZW |
215 | mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
216 | if (IS_GEN6(dev)) | |
217 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
218 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 ZN |
219 | } |
220 | return ret; | |
221 | } | |
222 | ||
62fdfeaf | 223 | #define PIPE_CONTROL_FLUSH(addr) \ |
8187a2b7 | 224 | do { \ |
62fdfeaf | 225 | OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 226 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
62fdfeaf EA |
227 | OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \ |
228 | OUT_RING(0); \ | |
229 | OUT_RING(0); \ | |
8187a2b7 | 230 | } while (0) |
62fdfeaf EA |
231 | |
232 | /** | |
233 | * Creates a new sequence number, emitting a write of it to the status page | |
234 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
235 | * | |
236 | * Must be called with struct_lock held. | |
237 | * | |
238 | * Returned sequence numbers are nonzero on success. | |
239 | */ | |
8187a2b7 ZN |
240 | static u32 |
241 | render_ring_add_request(struct drm_device *dev, | |
ab6f8e32 | 242 | struct intel_ring_buffer *ring, |
ab6f8e32 | 243 | u32 flush_domains) |
62fdfeaf EA |
244 | { |
245 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6f392d54 CW |
246 | u32 seqno; |
247 | ||
248 | seqno = i915_gem_get_seqno(dev); | |
ca76482e ZW |
249 | |
250 | if (IS_GEN6(dev)) { | |
251 | BEGIN_LP_RING(6); | |
252 | OUT_RING(GFX_OP_PIPE_CONTROL | 3); | |
253 | OUT_RING(PIPE_CONTROL_QW_WRITE | | |
254 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | | |
255 | PIPE_CONTROL_NOTIFY); | |
256 | OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | OUT_RING(seqno); | |
258 | OUT_RING(0); | |
259 | OUT_RING(0); | |
260 | ADVANCE_LP_RING(); | |
261 | } else if (HAS_PIPE_CONTROL(dev)) { | |
62fdfeaf EA |
262 | u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; |
263 | ||
264 | /* | |
265 | * Workaround qword write incoherence by flushing the | |
266 | * PIPE_NOTIFY buffers out to memory before requesting | |
267 | * an interrupt. | |
268 | */ | |
269 | BEGIN_LP_RING(32); | |
270 | OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
271 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | |
272 | OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
273 | OUT_RING(seqno); | |
274 | OUT_RING(0); | |
275 | PIPE_CONTROL_FLUSH(scratch_addr); | |
276 | scratch_addr += 128; /* write to separate cachelines */ | |
277 | PIPE_CONTROL_FLUSH(scratch_addr); | |
278 | scratch_addr += 128; | |
279 | PIPE_CONTROL_FLUSH(scratch_addr); | |
280 | scratch_addr += 128; | |
281 | PIPE_CONTROL_FLUSH(scratch_addr); | |
282 | scratch_addr += 128; | |
283 | PIPE_CONTROL_FLUSH(scratch_addr); | |
284 | scratch_addr += 128; | |
285 | PIPE_CONTROL_FLUSH(scratch_addr); | |
286 | OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
287 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | |
288 | PIPE_CONTROL_NOTIFY); | |
289 | OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
290 | OUT_RING(seqno); | |
291 | OUT_RING(0); | |
292 | ADVANCE_LP_RING(); | |
293 | } else { | |
294 | BEGIN_LP_RING(4); | |
295 | OUT_RING(MI_STORE_DWORD_INDEX); | |
296 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
297 | OUT_RING(seqno); | |
298 | ||
299 | OUT_RING(MI_USER_INTERRUPT); | |
300 | ADVANCE_LP_RING(); | |
301 | } | |
302 | return seqno; | |
303 | } | |
304 | ||
8187a2b7 | 305 | static u32 |
f787a5f5 CW |
306 | render_ring_get_seqno(struct drm_device *dev, |
307 | struct intel_ring_buffer *ring) | |
8187a2b7 ZN |
308 | { |
309 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
310 | if (HAS_PIPE_CONTROL(dev)) | |
311 | return ((volatile u32 *)(dev_priv->seqno_page))[0]; | |
312 | else | |
313 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
314 | } | |
315 | ||
316 | static void | |
317 | render_ring_get_user_irq(struct drm_device *dev, | |
ab6f8e32 | 318 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
319 | { |
320 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
321 | unsigned long irqflags; | |
322 | ||
323 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 324 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
325 | if (HAS_PCH_SPLIT(dev)) |
326 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
327 | else | |
328 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
329 | } | |
330 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
331 | } | |
332 | ||
8187a2b7 ZN |
333 | static void |
334 | render_ring_put_user_irq(struct drm_device *dev, | |
ab6f8e32 | 335 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
336 | { |
337 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
338 | unsigned long irqflags; | |
339 | ||
340 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
341 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
342 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
343 | if (HAS_PCH_SPLIT(dev)) |
344 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
345 | else | |
346 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
347 | } | |
348 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
349 | } | |
350 | ||
8187a2b7 | 351 | static void render_setup_status_page(struct drm_device *dev, |
ab6f8e32 | 352 | struct intel_ring_buffer *ring) |
8187a2b7 ZN |
353 | { |
354 | drm_i915_private_t *dev_priv = dev->dev_private; | |
355 | if (IS_GEN6(dev)) { | |
3d281d8c DV |
356 | I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), |
357 | ring->status_page.gfx_addr); | |
358 | I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */ | |
8187a2b7 | 359 | } else { |
3d281d8c DV |
360 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), |
361 | ring->status_page.gfx_addr); | |
362 | I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */ | |
8187a2b7 ZN |
363 | } |
364 | ||
365 | } | |
366 | ||
ab6f8e32 | 367 | static void |
d1b851fc ZN |
368 | bsd_ring_flush(struct drm_device *dev, |
369 | struct intel_ring_buffer *ring, | |
370 | u32 invalidate_domains, | |
371 | u32 flush_domains) | |
372 | { | |
be26a10b | 373 | intel_ring_begin(dev, ring, 2); |
d1b851fc ZN |
374 | intel_ring_emit(dev, ring, MI_FLUSH); |
375 | intel_ring_emit(dev, ring, MI_NOOP); | |
376 | intel_ring_advance(dev, ring); | |
377 | } | |
378 | ||
d1b851fc | 379 | static int init_bsd_ring(struct drm_device *dev, |
ab6f8e32 | 380 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
381 | { |
382 | return init_ring_common(dev, ring); | |
383 | } | |
384 | ||
385 | static u32 | |
386 | bsd_ring_add_request(struct drm_device *dev, | |
ab6f8e32 | 387 | struct intel_ring_buffer *ring, |
ab6f8e32 | 388 | u32 flush_domains) |
d1b851fc ZN |
389 | { |
390 | u32 seqno; | |
6f392d54 CW |
391 | |
392 | seqno = i915_gem_get_seqno(dev); | |
393 | ||
d1b851fc ZN |
394 | intel_ring_begin(dev, ring, 4); |
395 | intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); | |
396 | intel_ring_emit(dev, ring, | |
397 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
398 | intel_ring_emit(dev, ring, seqno); | |
399 | intel_ring_emit(dev, ring, MI_USER_INTERRUPT); | |
400 | intel_ring_advance(dev, ring); | |
401 | ||
402 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
403 | ||
404 | return seqno; | |
405 | } | |
406 | ||
407 | static void bsd_setup_status_page(struct drm_device *dev, | |
ab6f8e32 | 408 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
409 | { |
410 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3d281d8c DV |
411 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), ring->status_page.gfx_addr); |
412 | I915_READ(RING_HWS_PGA(ring->mmio_base)); | |
d1b851fc ZN |
413 | } |
414 | ||
415 | static void | |
416 | bsd_ring_get_user_irq(struct drm_device *dev, | |
ab6f8e32 | 417 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
418 | { |
419 | /* do nothing */ | |
420 | } | |
421 | static void | |
422 | bsd_ring_put_user_irq(struct drm_device *dev, | |
ab6f8e32 | 423 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
424 | { |
425 | /* do nothing */ | |
426 | } | |
427 | ||
428 | static u32 | |
f787a5f5 CW |
429 | bsd_ring_get_seqno(struct drm_device *dev, |
430 | struct intel_ring_buffer *ring) | |
d1b851fc ZN |
431 | { |
432 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
433 | } | |
434 | ||
435 | static int | |
436 | bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev, | |
ab6f8e32 CW |
437 | struct intel_ring_buffer *ring, |
438 | struct drm_i915_gem_execbuffer2 *exec, | |
439 | struct drm_clip_rect *cliprects, | |
440 | uint64_t exec_offset) | |
d1b851fc ZN |
441 | { |
442 | uint32_t exec_start; | |
443 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
444 | intel_ring_begin(dev, ring, 2); | |
445 | intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | | |
446 | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
447 | intel_ring_emit(dev, ring, exec_start); | |
448 | intel_ring_advance(dev, ring); | |
449 | return 0; | |
450 | } | |
451 | ||
452 | ||
8187a2b7 ZN |
453 | static int |
454 | render_ring_dispatch_gem_execbuffer(struct drm_device *dev, | |
ab6f8e32 CW |
455 | struct intel_ring_buffer *ring, |
456 | struct drm_i915_gem_execbuffer2 *exec, | |
457 | struct drm_clip_rect *cliprects, | |
458 | uint64_t exec_offset) | |
62fdfeaf EA |
459 | { |
460 | drm_i915_private_t *dev_priv = dev->dev_private; | |
461 | int nbox = exec->num_cliprects; | |
462 | int i = 0, count; | |
463 | uint32_t exec_start, exec_len; | |
62fdfeaf EA |
464 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
465 | exec_len = (uint32_t) exec->batch_len; | |
466 | ||
6f392d54 | 467 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf EA |
468 | |
469 | count = nbox ? nbox : 1; | |
470 | ||
471 | for (i = 0; i < count; i++) { | |
472 | if (i < nbox) { | |
473 | int ret = i915_emit_box(dev, cliprects, i, | |
474 | exec->DR1, exec->DR4); | |
475 | if (ret) | |
476 | return ret; | |
477 | } | |
478 | ||
479 | if (IS_I830(dev) || IS_845G(dev)) { | |
8187a2b7 ZN |
480 | intel_ring_begin(dev, ring, 4); |
481 | intel_ring_emit(dev, ring, MI_BATCH_BUFFER); | |
482 | intel_ring_emit(dev, ring, | |
483 | exec_start | MI_BATCH_NON_SECURE); | |
484 | intel_ring_emit(dev, ring, exec_start + exec_len - 4); | |
485 | intel_ring_emit(dev, ring, 0); | |
62fdfeaf | 486 | } else { |
8187a2b7 | 487 | intel_ring_begin(dev, ring, 4); |
a6c45cf0 | 488 | if (INTEL_INFO(dev)->gen >= 4) { |
8187a2b7 ZN |
489 | intel_ring_emit(dev, ring, |
490 | MI_BATCH_BUFFER_START | (2 << 6) | |
491 | | MI_BATCH_NON_SECURE_I965); | |
492 | intel_ring_emit(dev, ring, exec_start); | |
62fdfeaf | 493 | } else { |
8187a2b7 ZN |
494 | intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
495 | | (2 << 6)); | |
496 | intel_ring_emit(dev, ring, exec_start | | |
497 | MI_BATCH_NON_SECURE); | |
62fdfeaf | 498 | } |
62fdfeaf | 499 | } |
8187a2b7 | 500 | intel_ring_advance(dev, ring); |
62fdfeaf EA |
501 | } |
502 | ||
1cafd347 ZN |
503 | if (IS_G4X(dev) || IS_IRONLAKE(dev)) { |
504 | intel_ring_begin(dev, ring, 2); | |
505 | intel_ring_emit(dev, ring, MI_FLUSH | | |
506 | MI_NO_WRITE_FLUSH | | |
507 | MI_INVALIDATE_ISP ); | |
508 | intel_ring_emit(dev, ring, MI_NOOP); | |
509 | intel_ring_advance(dev, ring); | |
510 | } | |
62fdfeaf | 511 | /* XXX breadcrumb */ |
1cafd347 | 512 | |
62fdfeaf EA |
513 | return 0; |
514 | } | |
515 | ||
8187a2b7 | 516 | static void cleanup_status_page(struct drm_device *dev, |
ab6f8e32 | 517 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
518 | { |
519 | drm_i915_private_t *dev_priv = dev->dev_private; | |
520 | struct drm_gem_object *obj; | |
521 | struct drm_i915_gem_object *obj_priv; | |
522 | ||
8187a2b7 ZN |
523 | obj = ring->status_page.obj; |
524 | if (obj == NULL) | |
62fdfeaf | 525 | return; |
62fdfeaf EA |
526 | obj_priv = to_intel_bo(obj); |
527 | ||
528 | kunmap(obj_priv->pages[0]); | |
529 | i915_gem_object_unpin(obj); | |
530 | drm_gem_object_unreference(obj); | |
8187a2b7 | 531 | ring->status_page.obj = NULL; |
62fdfeaf EA |
532 | |
533 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
534 | } |
535 | ||
8187a2b7 | 536 | static int init_status_page(struct drm_device *dev, |
ab6f8e32 | 537 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
538 | { |
539 | drm_i915_private_t *dev_priv = dev->dev_private; | |
540 | struct drm_gem_object *obj; | |
541 | struct drm_i915_gem_object *obj_priv; | |
542 | int ret; | |
543 | ||
62fdfeaf EA |
544 | obj = i915_gem_alloc_object(dev, 4096); |
545 | if (obj == NULL) { | |
546 | DRM_ERROR("Failed to allocate status page\n"); | |
547 | ret = -ENOMEM; | |
548 | goto err; | |
549 | } | |
550 | obj_priv = to_intel_bo(obj); | |
551 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
552 | ||
553 | ret = i915_gem_object_pin(obj, 4096); | |
554 | if (ret != 0) { | |
62fdfeaf EA |
555 | goto err_unref; |
556 | } | |
557 | ||
8187a2b7 ZN |
558 | ring->status_page.gfx_addr = obj_priv->gtt_offset; |
559 | ring->status_page.page_addr = kmap(obj_priv->pages[0]); | |
560 | if (ring->status_page.page_addr == NULL) { | |
62fdfeaf | 561 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
562 | goto err_unpin; |
563 | } | |
8187a2b7 ZN |
564 | ring->status_page.obj = obj; |
565 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 566 | |
8187a2b7 ZN |
567 | ring->setup_status_page(dev, ring); |
568 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", | |
569 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
570 | |
571 | return 0; | |
572 | ||
573 | err_unpin: | |
574 | i915_gem_object_unpin(obj); | |
575 | err_unref: | |
576 | drm_gem_object_unreference(obj); | |
577 | err: | |
8187a2b7 | 578 | return ret; |
62fdfeaf EA |
579 | } |
580 | ||
8187a2b7 | 581 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 582 | struct intel_ring_buffer *ring) |
62fdfeaf | 583 | { |
870e86dd | 584 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 ZN |
585 | struct drm_i915_gem_object *obj_priv; |
586 | struct drm_gem_object *obj; | |
dd785e35 CW |
587 | int ret; |
588 | ||
8187a2b7 | 589 | ring->dev = dev; |
62fdfeaf | 590 | |
8187a2b7 ZN |
591 | if (I915_NEED_GFX_HWS(dev)) { |
592 | ret = init_status_page(dev, ring); | |
593 | if (ret) | |
594 | return ret; | |
595 | } | |
62fdfeaf | 596 | |
8187a2b7 | 597 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
598 | if (obj == NULL) { |
599 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 600 | ret = -ENOMEM; |
dd785e35 | 601 | goto err_hws; |
62fdfeaf | 602 | } |
62fdfeaf | 603 | |
8187a2b7 ZN |
604 | ring->gem_object = obj; |
605 | ||
a9db5c8f | 606 | ret = i915_gem_object_pin(obj, PAGE_SIZE); |
dd785e35 CW |
607 | if (ret) |
608 | goto err_unref; | |
62fdfeaf | 609 | |
8187a2b7 ZN |
610 | obj_priv = to_intel_bo(obj); |
611 | ring->map.size = ring->size; | |
62fdfeaf | 612 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
62fdfeaf EA |
613 | ring->map.type = 0; |
614 | ring->map.flags = 0; | |
615 | ring->map.mtrr = 0; | |
616 | ||
617 | drm_core_ioremap_wc(&ring->map, dev); | |
618 | if (ring->map.handle == NULL) { | |
619 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 620 | ret = -EINVAL; |
dd785e35 | 621 | goto err_unpin; |
62fdfeaf EA |
622 | } |
623 | ||
8187a2b7 ZN |
624 | ring->virtual_start = ring->map.handle; |
625 | ret = ring->init(dev, ring); | |
dd785e35 CW |
626 | if (ret) |
627 | goto err_unmap; | |
62fdfeaf | 628 | |
62fdfeaf EA |
629 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
630 | i915_kernel_lost_context(dev); | |
631 | else { | |
570ef608 | 632 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 633 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
62fdfeaf EA |
634 | ring->space = ring->head - (ring->tail + 8); |
635 | if (ring->space < 0) | |
8187a2b7 | 636 | ring->space += ring->size; |
62fdfeaf | 637 | } |
8187a2b7 ZN |
638 | INIT_LIST_HEAD(&ring->active_list); |
639 | INIT_LIST_HEAD(&ring->request_list); | |
640 | return ret; | |
dd785e35 CW |
641 | |
642 | err_unmap: | |
643 | drm_core_ioremapfree(&ring->map, dev); | |
644 | err_unpin: | |
645 | i915_gem_object_unpin(obj); | |
646 | err_unref: | |
647 | drm_gem_object_unreference(obj); | |
648 | ring->gem_object = NULL; | |
649 | err_hws: | |
8187a2b7 ZN |
650 | cleanup_status_page(dev, ring); |
651 | return ret; | |
62fdfeaf EA |
652 | } |
653 | ||
8187a2b7 | 654 | void intel_cleanup_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 655 | struct intel_ring_buffer *ring) |
62fdfeaf | 656 | { |
8187a2b7 | 657 | if (ring->gem_object == NULL) |
62fdfeaf EA |
658 | return; |
659 | ||
8187a2b7 | 660 | drm_core_ioremapfree(&ring->map, dev); |
62fdfeaf | 661 | |
8187a2b7 ZN |
662 | i915_gem_object_unpin(ring->gem_object); |
663 | drm_gem_object_unreference(ring->gem_object); | |
664 | ring->gem_object = NULL; | |
665 | cleanup_status_page(dev, ring); | |
62fdfeaf EA |
666 | } |
667 | ||
ab6f8e32 CW |
668 | static int intel_wrap_ring_buffer(struct drm_device *dev, |
669 | struct intel_ring_buffer *ring) | |
62fdfeaf | 670 | { |
8187a2b7 | 671 | unsigned int *virt; |
62fdfeaf | 672 | int rem; |
8187a2b7 | 673 | rem = ring->size - ring->tail; |
62fdfeaf | 674 | |
8187a2b7 ZN |
675 | if (ring->space < rem) { |
676 | int ret = intel_wait_ring_buffer(dev, ring, rem); | |
62fdfeaf EA |
677 | if (ret) |
678 | return ret; | |
679 | } | |
62fdfeaf | 680 | |
8187a2b7 | 681 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
682 | rem /= 8; |
683 | while (rem--) { | |
62fdfeaf | 684 | *virt++ = MI_NOOP; |
1741dd4a CW |
685 | *virt++ = MI_NOOP; |
686 | } | |
62fdfeaf | 687 | |
8187a2b7 | 688 | ring->tail = 0; |
43ed340a | 689 | ring->space = ring->head - 8; |
62fdfeaf EA |
690 | |
691 | return 0; | |
692 | } | |
693 | ||
8187a2b7 | 694 | int intel_wait_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 695 | struct intel_ring_buffer *ring, int n) |
62fdfeaf | 696 | { |
8187a2b7 | 697 | unsigned long end; |
570ef608 | 698 | drm_i915_private_t *dev_priv = dev->dev_private; |
62fdfeaf EA |
699 | |
700 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
701 | end = jiffies + 3 * HZ; |
702 | do { | |
570ef608 | 703 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
704 | ring->space = ring->head - (ring->tail + 8); |
705 | if (ring->space < 0) | |
8187a2b7 | 706 | ring->space += ring->size; |
62fdfeaf EA |
707 | if (ring->space >= n) { |
708 | trace_i915_ring_wait_end (dev); | |
709 | return 0; | |
710 | } | |
711 | ||
712 | if (dev->primary->master) { | |
713 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
714 | if (master_priv->sarea_priv) | |
715 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
716 | } | |
d1b851fc | 717 | |
8187a2b7 ZN |
718 | yield(); |
719 | } while (!time_after(jiffies, end)); | |
720 | trace_i915_ring_wait_end (dev); | |
721 | return -EBUSY; | |
722 | } | |
62fdfeaf | 723 | |
8187a2b7 | 724 | void intel_ring_begin(struct drm_device *dev, |
ab6f8e32 CW |
725 | struct intel_ring_buffer *ring, |
726 | int num_dwords) | |
8187a2b7 | 727 | { |
be26a10b | 728 | int n = 4*num_dwords; |
8187a2b7 ZN |
729 | if (unlikely(ring->tail + n > ring->size)) |
730 | intel_wrap_ring_buffer(dev, ring); | |
731 | if (unlikely(ring->space < n)) | |
732 | intel_wait_ring_buffer(dev, ring, n); | |
d97ed339 CW |
733 | |
734 | ring->space -= n; | |
8187a2b7 | 735 | } |
62fdfeaf | 736 | |
8187a2b7 | 737 | void intel_ring_advance(struct drm_device *dev, |
ab6f8e32 | 738 | struct intel_ring_buffer *ring) |
8187a2b7 | 739 | { |
d97ed339 | 740 | ring->tail &= ring->size - 1; |
870e86dd | 741 | ring->set_tail(dev, ring, ring->tail); |
8187a2b7 | 742 | } |
62fdfeaf | 743 | |
8187a2b7 | 744 | void intel_fill_struct(struct drm_device *dev, |
ab6f8e32 CW |
745 | struct intel_ring_buffer *ring, |
746 | void *data, | |
747 | unsigned int len) | |
8187a2b7 ZN |
748 | { |
749 | unsigned int *virt = ring->virtual_start + ring->tail; | |
750 | BUG_ON((len&~(4-1)) != 0); | |
be26a10b | 751 | intel_ring_begin(dev, ring, len/4); |
8187a2b7 ZN |
752 | memcpy(virt, data, len); |
753 | ring->tail += len; | |
754 | ring->tail &= ring->size - 1; | |
755 | ring->space -= len; | |
756 | intel_ring_advance(dev, ring); | |
757 | } | |
62fdfeaf | 758 | |
e070868e | 759 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 760 | .name = "render ring", |
9220434a | 761 | .id = RING_RENDER, |
333e9fe9 | 762 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 763 | .size = 32 * PAGE_SIZE, |
8187a2b7 ZN |
764 | .setup_status_page = render_setup_status_page, |
765 | .init = init_render_ring, | |
870e86dd | 766 | .set_tail = ring_set_tail, |
8187a2b7 ZN |
767 | .flush = render_ring_flush, |
768 | .add_request = render_ring_add_request, | |
f787a5f5 | 769 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
770 | .user_irq_get = render_ring_get_user_irq, |
771 | .user_irq_put = render_ring_put_user_irq, | |
772 | .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer, | |
8187a2b7 | 773 | }; |
d1b851fc ZN |
774 | |
775 | /* ring buffer for bit-stream decoder */ | |
776 | ||
e070868e | 777 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 778 | .name = "bsd ring", |
9220434a | 779 | .id = RING_BSD, |
333e9fe9 | 780 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 781 | .size = 32 * PAGE_SIZE, |
d1b851fc ZN |
782 | .setup_status_page = bsd_setup_status_page, |
783 | .init = init_bsd_ring, | |
870e86dd | 784 | .set_tail = ring_set_tail, |
d1b851fc ZN |
785 | .flush = bsd_ring_flush, |
786 | .add_request = bsd_ring_add_request, | |
f787a5f5 | 787 | .get_seqno = bsd_ring_get_seqno, |
d1b851fc ZN |
788 | .user_irq_get = bsd_ring_get_user_irq, |
789 | .user_irq_put = bsd_ring_put_user_irq, | |
790 | .dispatch_gem_execbuffer = bsd_ring_dispatch_gem_execbuffer, | |
d1b851fc | 791 | }; |
5c1143bb | 792 | |
881f47b6 XH |
793 | |
794 | static void gen6_bsd_setup_status_page(struct drm_device *dev, | |
ab6f8e32 | 795 | struct intel_ring_buffer *ring) |
881f47b6 XH |
796 | { |
797 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3d281d8c DV |
798 | I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), ring->status_page.gfx_addr); |
799 | I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); | |
881f47b6 XH |
800 | } |
801 | ||
ab6f8e32 CW |
802 | static void gen6_bsd_ring_set_tail(struct drm_device *dev, |
803 | struct intel_ring_buffer *ring, | |
804 | u32 value) | |
881f47b6 XH |
805 | { |
806 | drm_i915_private_t *dev_priv = dev->dev_private; | |
807 | ||
808 | /* Every tail move must follow the sequence below */ | |
809 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
810 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
811 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
812 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
813 | ||
814 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
815 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
816 | 50)) | |
817 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
818 | ||
870e86dd | 819 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
820 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
821 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
822 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
823 | } | |
824 | ||
881f47b6 | 825 | static void gen6_bsd_ring_flush(struct drm_device *dev, |
ab6f8e32 CW |
826 | struct intel_ring_buffer *ring, |
827 | u32 invalidate_domains, | |
828 | u32 flush_domains) | |
881f47b6 XH |
829 | { |
830 | intel_ring_begin(dev, ring, 4); | |
831 | intel_ring_emit(dev, ring, MI_FLUSH_DW); | |
832 | intel_ring_emit(dev, ring, 0); | |
833 | intel_ring_emit(dev, ring, 0); | |
834 | intel_ring_emit(dev, ring, 0); | |
835 | intel_ring_advance(dev, ring); | |
836 | } | |
837 | ||
838 | static int | |
839 | gen6_bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev, | |
ab6f8e32 CW |
840 | struct intel_ring_buffer *ring, |
841 | struct drm_i915_gem_execbuffer2 *exec, | |
842 | struct drm_clip_rect *cliprects, | |
843 | uint64_t exec_offset) | |
881f47b6 XH |
844 | { |
845 | uint32_t exec_start; | |
ab6f8e32 | 846 | |
881f47b6 | 847 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
ab6f8e32 | 848 | |
881f47b6 | 849 | intel_ring_begin(dev, ring, 2); |
ab6f8e32 CW |
850 | intel_ring_emit(dev, ring, |
851 | MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); | |
852 | /* bit0-7 is the length on GEN6+ */ | |
881f47b6 XH |
853 | intel_ring_emit(dev, ring, exec_start); |
854 | intel_ring_advance(dev, ring); | |
ab6f8e32 | 855 | |
881f47b6 XH |
856 | return 0; |
857 | } | |
858 | ||
859 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 860 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
861 | .name = "gen6 bsd ring", |
862 | .id = RING_BSD, | |
333e9fe9 | 863 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 864 | .size = 32 * PAGE_SIZE, |
881f47b6 XH |
865 | .setup_status_page = gen6_bsd_setup_status_page, |
866 | .init = init_bsd_ring, | |
881f47b6 | 867 | .set_tail = gen6_bsd_ring_set_tail, |
881f47b6 XH |
868 | .flush = gen6_bsd_ring_flush, |
869 | .add_request = bsd_ring_add_request, | |
f787a5f5 | 870 | .get_seqno = bsd_ring_get_seqno, |
881f47b6 XH |
871 | .user_irq_get = bsd_ring_get_user_irq, |
872 | .user_irq_put = bsd_ring_put_user_irq, | |
873 | .dispatch_gem_execbuffer = gen6_bsd_ring_dispatch_gem_execbuffer, | |
881f47b6 XH |
874 | }; |
875 | ||
5c1143bb XH |
876 | int intel_init_render_ring_buffer(struct drm_device *dev) |
877 | { | |
878 | drm_i915_private_t *dev_priv = dev->dev_private; | |
879 | ||
880 | dev_priv->render_ring = render_ring; | |
881 | ||
882 | if (!I915_NEED_GFX_HWS(dev)) { | |
883 | dev_priv->render_ring.status_page.page_addr | |
884 | = dev_priv->status_page_dmah->vaddr; | |
885 | memset(dev_priv->render_ring.status_page.page_addr, | |
886 | 0, PAGE_SIZE); | |
887 | } | |
888 | ||
889 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
890 | } | |
891 | ||
892 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
893 | { | |
894 | drm_i915_private_t *dev_priv = dev->dev_private; | |
895 | ||
881f47b6 XH |
896 | if (IS_GEN6(dev)) |
897 | dev_priv->bsd_ring = gen6_bsd_ring; | |
898 | else | |
899 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
900 | |
901 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
902 | } |