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drm/i915: Fix irq checks in ring->irq_get/put functions
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
1cf0ba14 55 int space = head - (tail + I915_RING_FREE_SPACE);
c7dca47b 56 if (space < 0)
1cf0ba14 57 space += size;
c7dca47b
CW		 58 return space;
59}
60
82e104cc 61int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 62{
82e104cc
OM		 63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
1cf0ba14
CW		 65}
66
82e104cc 67bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 68{
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71}
09246732 72
a4872ba6 73void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 74{
93b0a4e0
OM		 75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 77 if (intel_ring_stopped(ring))
09246732 78 return;
93b0a4e0 79 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 80}
81
b72f3acb 82static int
a4872ba6 83gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 84 u32 invalidate_domains,
85 u32 flush_domains)
86{
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
31b14c9f 91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106}
107
108static int
a4872ba6 109gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 110 u32 invalidate_domains,
111 u32 flush_domains)
62fdfeaf 112{
78501eac 113 struct drm_device *dev = ring->dev;
6f392d54 114 u32 cmd;
b72f3acb 115 int ret;
6f392d54 116
36d527de
CW		 117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 147 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
62fdfeaf 150
36d527de
CW		 151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
70eac33e 154
36d527de
CW		 155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
b72f3acb 158
36d527de
CW		 159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
b72f3acb
CW		 162
163 return 0;
8187a2b7
ZN		 164}
165
8d315287
JB		 166/**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203static int
a4872ba6 204intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 205{
18393f63 206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236}
237
238static int
a4872ba6 239gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 240 u32 invalidate_domains, u32 flush_domains)
241{
242 u32 flags = 0;
18393f63 243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 244 int ret;
245
b3111509
PZ		 246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
8d315287
JB		 251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
7d54a904
CW		 255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
97f209bc 262 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
3ac78313 274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 275 }
8d315287 276
6c6cf5aa 277 ret = intel_ring_begin(ring, 4);
8d315287
JB		 278 if (ret)
279 return ret;
280
6c6cf5aa 281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 284 intel_ring_emit(ring, 0);
8d315287
JB		 285 intel_ring_advance(ring);
286
287 return 0;
288}
289
f3987631 290static int
a4872ba6 291gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 292{
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307}
308
a4872ba6 309static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 310{
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
37c1d94f 316 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 317 if (ret)
318 return ret;
fd3da6c9
RV		 319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
37c1d94f
VS		 323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330}
331
4772eaeb 332static int
a4872ba6 333gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 334 u32 invalidate_domains, u32 flush_domains)
335{
336 u32 flags = 0;
18393f63 337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 338 int ret;
339
f3987631
PZ		 340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
4772eaeb
PZ		 350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
365 /*
366 * TLB invalidate requires a post-sync write.
367 */
368 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 369 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631
PZ		 370
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 375 }
376
377 ret = intel_ring_begin(ring, 4);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring, flags);
b9e1faa7 383 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 384 intel_ring_emit(ring, 0);
385 intel_ring_advance(ring);
386
9688ecad 387 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 388 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
389
4772eaeb
PZ		 390 return 0;
391}
392
884ceace
KG		 393static int
394gen8_emit_pipe_control(struct intel_engine_cs *ring,
395 u32 flags, u32 scratch_addr)
396{
397 int ret;
398
399 ret = intel_ring_begin(ring, 6);
400 if (ret)
401 return ret;
402
403 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring, flags);
405 intel_ring_emit(ring, scratch_addr);
406 intel_ring_emit(ring, 0);
407 intel_ring_emit(ring, 0);
408 intel_ring_emit(ring, 0);
409 intel_ring_advance(ring);
410
411 return 0;
412}
413
a5f3d68e 414static int
a4872ba6 415gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 416 u32 invalidate_domains, u32 flush_domains)
417{
418 u32 flags = 0;
18393f63 419 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 420 int ret;
a5f3d68e
BW		 421
422 flags |= PIPE_CONTROL_CS_STALL;
423
424 if (flush_domains) {
425 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
426 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
427 }
428 if (invalidate_domains) {
429 flags |= PIPE_CONTROL_TLB_INVALIDATE;
430 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_QW_WRITE;
436 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 437
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret = gen8_emit_pipe_control(ring,
440 PIPE_CONTROL_CS_STALL |
441 PIPE_CONTROL_STALL_AT_SCOREBOARD,
442 0);
443 if (ret)
444 return ret;
a5f3d68e
BW		 445 }
446
c5ad011d
RV		 447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
448 if (ret)
449 return ret;
450
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
453
454 return 0;
a5f3d68e
BW		 455}
456
a4872ba6 457static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 458 u32 value)
d46eefa2 459{
4640c4ff 460 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 461 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 462}
463
a4872ba6 464u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 465{
4640c4ff 466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 467 u64 acthd;
8187a2b7 468
50877445
CW		 469 if (INTEL_INFO(ring->dev)->gen >= 8)
470 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
471 RING_ACTHD_UDW(ring->mmio_base));
472 else if (INTEL_INFO(ring->dev)->gen >= 4)
473 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
474 else
475 acthd = I915_READ(ACTHD);
476
477 return acthd;
8187a2b7
ZN		 478}
479
a4872ba6 480static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 481{
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 addr;
484
485 addr = dev_priv->status_page_dmah->busaddr;
486 if (INTEL_INFO(ring->dev)->gen >= 4)
487 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
488 I915_WRITE(HWS_PGA, addr);
489}
490
a4872ba6 491static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 492{
9991ae78 493 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 494
9991ae78
CW		 495 if (!IS_GEN2(ring->dev)) {
496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 497 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
502 */
503 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
504 return false;
9991ae78
CW		 505 }
506 }
b7884eb4 507
7f2ab699 508 I915_WRITE_CTL(ring, 0);
570ef608 509 I915_WRITE_HEAD(ring, 0);
78501eac 510 ring->write_tail(ring, 0);
8187a2b7 511
9991ae78
CW		 512 if (!IS_GEN2(ring->dev)) {
513 (void)I915_READ_CTL(ring);
514 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
515 }
a51435a3 516
9991ae78
CW		 517 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
518}
8187a2b7 519
a4872ba6 520static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 521{
522 struct drm_device *dev = ring->dev;
523 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 524 struct intel_ringbuffer *ringbuf = ring->buffer;
525 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 526 int ret = 0;
527
528 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
529
530 if (!stop_ring(ring)) {
531 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
534 ring->name,
535 I915_READ_CTL(ring),
536 I915_READ_HEAD(ring),
537 I915_READ_TAIL(ring),
538 I915_READ_START(ring));
8187a2b7 539
9991ae78 540 if (!stop_ring(ring)) {
6fd0d56e
CW		 541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
543 ring->name,
544 I915_READ_CTL(ring),
545 I915_READ_HEAD(ring),
546 I915_READ_TAIL(ring),
547 I915_READ_START(ring));
9991ae78
CW		 548 ret = -EIO;
549 goto out;
6fd0d56e 550 }
8187a2b7
ZN		 551 }
552
9991ae78
CW		 553 if (I915_NEED_GFX_HWS(dev))
554 intel_ring_setup_status_page(ring);
555 else
556 ring_setup_phys_status_page(ring);
557
ece4a17d
JK		 558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring);
560
0d8957c8
DV		 561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
f343c5f6 565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 566
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
573
7f2ab699 574 I915_WRITE_CTL(ring,
93b0a4e0 575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 576 | RING_VALID);
8187a2b7 577
8187a2b7 578 /* If the head is still not zero, the ring is dead */
f01db988 579 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 580 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 581 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 582 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
584 ring->name,
585 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
586 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
587 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 588 ret = -EIO;
589 goto out;
8187a2b7
ZN		 590 }
591
78501eac
CW		 592 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
593 i915_kernel_lost_context(ring->dev);
8187a2b7 594 else {
93b0a4e0
OM		 595 ringbuf->head = I915_READ_HEAD(ring);
596 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
82e104cc 597 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 598 ringbuf->last_retired_head = -1;
8187a2b7 599 }
1ec14ad3 600
50f018df
CW		 601 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
602
b7884eb4 603out:
c8d9a590 604 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 605
606 return ret;
8187a2b7
ZN		 607}
608
9b1136d5
OM		 609void
610intel_fini_pipe_control(struct intel_engine_cs *ring)
611{
612 struct drm_device *dev = ring->dev;
613
614 if (ring->scratch.obj == NULL)
615 return;
616
617 if (INTEL_INFO(dev)->gen >= 5) {
618 kunmap(sg_page(ring->scratch.obj->pages->sgl));
619 i915_gem_object_ggtt_unpin(ring->scratch.obj);
620 }
621
622 drm_gem_object_unreference(&ring->scratch.obj->base);
623 ring->scratch.obj = NULL;
624}
625
626int
627intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 628{
c6df541c
CW		 629 int ret;
630
0d1aacac 631 if (ring->scratch.obj)
c6df541c
CW		 632 return 0;
633
0d1aacac
CW		 634 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
635 if (ring->scratch.obj == NULL) {
c6df541c
CW		 636 DRM_ERROR("Failed to allocate seqno page\n");
637 ret = -ENOMEM;
638 goto err;
639 }
e4ffd173 640
a9cc726c
DV		 641 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
642 if (ret)
643 goto err_unref;
c6df541c 644
1ec9e26d 645 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 646 if (ret)
647 goto err_unref;
648
0d1aacac
CW		 649 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
650 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
651 if (ring->scratch.cpu_page == NULL) {
56b085a0 652 ret = -ENOMEM;
c6df541c 653 goto err_unpin;
56b085a0 654 }
c6df541c 655
2b1086cc 656 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 657 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 658 return 0;
659
660err_unpin:
d7f46fc4 661 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 662err_unref:
0d1aacac 663 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 664err:
c6df541c
CW		 665 return ret;
666}
667
86d7f238
AS		 668static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
669 u32 addr, u32 value)
670{
888b5995
AS		 671 struct drm_device *dev = ring->dev;
672 struct drm_i915_private *dev_priv = dev->dev_private;
673
04ad2dc7 674 if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
888b5995
AS		 675 return;
676
86d7f238
AS		 677 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
678 intel_ring_emit(ring, addr);
679 intel_ring_emit(ring, value);
888b5995
AS		 680
681 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
b07ba1dc 682 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
888b5995
AS		 683 /* value is updated with the status of remaining bits of this
684 * register when it is read from debugfs file
685 */
686 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
687 dev_priv->num_wa_regs++;
688
689 return;
86d7f238
AS		 690}
691
00e1e623 692static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238
AS		 693{
694 int ret;
888b5995
AS		 695 struct drm_device *dev = ring->dev;
696 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238
AS		 697
698 /*
699 * workarounds applied in this fn are part of register state context,
700 * they need to be re-initialized followed by gpu reset, suspend/resume,
701 * module reload.
702 */
888b5995
AS		 703 dev_priv->num_wa_regs = 0;
704 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
86d7f238
AS		 705
706 /*
707 * update the number of dwords required based on the
708 * actual number of workarounds applied
709 */
710 ret = intel_ring_begin(ring, 24);
711 if (ret)
712 return ret;
713
714 /* WaDisablePartialInstShootdown:bdw */
715 /* WaDisableThreadStallDopClockGating:bdw */
716 /* FIXME: Unclear whether we really need this on production bdw. */
717 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
718 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
719 | STALL_DOP_GATING_DISABLE));
720
721 /* WaDisableDopClockGating:bdw May not be needed for production */
722 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
723 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
724
725 /*
726 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
727 * pre-production hardware
728 */
729 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
730 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
731 | GEN8_SAMPLER_POWER_BYPASS_DIS));
732
733 intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
734 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
735
736 intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
737 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
738
739 /* Use Force Non-Coherent whenever executing a 3D context. This is a
740 * workaround for for a possible hang in the unlikely event a TLB
741 * invalidation occurs during a PSD flush.
742 */
743 intel_ring_emit_wa(ring, HDC_CHICKEN0,
744 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
745
746 /* Wa4x4STCOptimizationDisable:bdw */
747 intel_ring_emit_wa(ring, CACHE_MODE_1,
748 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
749
750 /*
751 * BSpec recommends 8x4 when MSAA is used,
752 * however in practice 16x4 seems fastest.
753 *
754 * Note that PS/WM thread counts depend on the WIZ hashing
755 * disable bit, which we don't touch here, but it's good
756 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
757 */
758 intel_ring_emit_wa(ring, GEN7_GT_MODE,
759 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
760
761 intel_ring_advance(ring);
762
888b5995
AS		 763 DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
764 dev_priv->num_wa_regs);
765
86d7f238
AS		 766 return 0;
767}
768
00e1e623
VS		 769static int chv_init_workarounds(struct intel_engine_cs *ring)
770{
771 int ret;
772 struct drm_device *dev = ring->dev;
773 struct drm_i915_private *dev_priv = dev->dev_private;
774
775 /*
776 * workarounds applied in this fn are part of register state context,
777 * they need to be re-initialized followed by gpu reset, suspend/resume,
778 * module reload.
779 */
780 dev_priv->num_wa_regs = 0;
781 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
782
783 ret = intel_ring_begin(ring, 12);
784 if (ret)
785 return ret;
786
787 /* WaDisablePartialInstShootdown:chv */
788 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
789 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
790
791 /* WaDisableThreadStallDopClockGating:chv */
792 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
793 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
794
795 /* WaDisableDopClockGating:chv (pre-production hw) */
796 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
797 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
798
799 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
800 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
801 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
802
803 intel_ring_advance(ring);
804
805 return 0;
806}
807
a4872ba6 808static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 809{
78501eac 810 struct drm_device *dev = ring->dev;
1ec14ad3 811 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 812 int ret = init_ring_common(ring);
9c33baa6
KZ		 813 if (ret)
814 return ret;
a69ffdbf 815
61a563a2
AG		 816 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
817 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 818 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 819
820 /* We need to disable the AsyncFlip performance optimisations in order
821 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
822 * programmed to '1' on all products.
8693a824 823 *
b3f797ac 824 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5
CW		 825 */
826 if (INTEL_INFO(dev)->gen >= 6)
827 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
828
f05bb0c7 829 /* Required for the hardware to program scanline values for waiting */
01fa0302 830 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 831 if (INTEL_INFO(dev)->gen == 6)
832 I915_WRITE(GFX_MODE,
aa83e30d 833 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 834
01fa0302 835 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 836 if (IS_GEN7(dev))
837 I915_WRITE(GFX_MODE_GEN7,
01fa0302 838 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 839 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 840
8d315287 841 if (INTEL_INFO(dev)->gen >= 5) {
9b1136d5 842 ret = intel_init_pipe_control(ring);
c6df541c
CW		 843 if (ret)
844 return ret;
845 }
846
5e13a0c5 847 if (IS_GEN6(dev)) {
3a69ddd6
KG		 848 /* From the Sandybridge PRM, volume 1 part 3, page 24:
849 * "If this bit is set, STCunit will have LRA as replacement
850 * policy. [...] This bit must be reset. LRA replacement
851 * policy is not supported."
852 */
853 I915_WRITE(CACHE_MODE_0,
5e13a0c5 854 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 855 }
856
6b26c86d
DV		 857 if (INTEL_INFO(dev)->gen >= 6)
858 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 859
040d2baa 860 if (HAS_L3_DPF(dev))
35a85ac6 861 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 862
8187a2b7
ZN		 863 return ret;
864}
865
a4872ba6 866static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 867{
b45305fc 868 struct drm_device *dev = ring->dev;
3e78998a
BW		 869 struct drm_i915_private *dev_priv = dev->dev_private;
870
871 if (dev_priv->semaphore_obj) {
872 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
873 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
874 dev_priv->semaphore_obj = NULL;
875 }
b45305fc 876
9b1136d5 877 intel_fini_pipe_control(ring);
c6df541c
CW		 878}
879
3e78998a
BW		 880static int gen8_rcs_signal(struct intel_engine_cs *signaller,
881 unsigned int num_dwords)
882{
883#define MBOX_UPDATE_DWORDS 8
884 struct drm_device *dev = signaller->dev;
885 struct drm_i915_private *dev_priv = dev->dev_private;
886 struct intel_engine_cs *waiter;
887 int i, ret, num_rings;
888
889 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
890 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
891#undef MBOX_UPDATE_DWORDS
892
893 ret = intel_ring_begin(signaller, num_dwords);
894 if (ret)
895 return ret;
896
897 for_each_ring(waiter, dev_priv, i) {
898 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
899 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
900 continue;
901
902 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
903 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
904 PIPE_CONTROL_QW_WRITE |
905 PIPE_CONTROL_FLUSH_ENABLE);
906 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
907 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
908 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
909 intel_ring_emit(signaller, 0);
910 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
911 MI_SEMAPHORE_TARGET(waiter->id));
912 intel_ring_emit(signaller, 0);
913 }
914
915 return 0;
916}
917
918static int gen8_xcs_signal(struct intel_engine_cs *signaller,
919 unsigned int num_dwords)
920{
921#define MBOX_UPDATE_DWORDS 6
922 struct drm_device *dev = signaller->dev;
923 struct drm_i915_private *dev_priv = dev->dev_private;
924 struct intel_engine_cs *waiter;
925 int i, ret, num_rings;
926
927 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
928 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
929#undef MBOX_UPDATE_DWORDS
930
931 ret = intel_ring_begin(signaller, num_dwords);
932 if (ret)
933 return ret;
934
935 for_each_ring(waiter, dev_priv, i) {
936 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
937 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
938 continue;
939
940 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
941 MI_FLUSH_DW_OP_STOREDW);
942 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
943 MI_FLUSH_DW_USE_GTT);
944 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
945 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
946 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
947 MI_SEMAPHORE_TARGET(waiter->id));
948 intel_ring_emit(signaller, 0);
949 }
950
951 return 0;
952}
953
a4872ba6 954static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 955 unsigned int num_dwords)
1ec14ad3 956{
024a43e1
BW		 957 struct drm_device *dev = signaller->dev;
958 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 959 struct intel_engine_cs *useless;
a1444b79 960 int i, ret, num_rings;
78325f2d 961
a1444b79
BW		 962#define MBOX_UPDATE_DWORDS 3
963 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
964 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
965#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 966
967 ret = intel_ring_begin(signaller, num_dwords);
968 if (ret)
969 return ret;
024a43e1 970
78325f2d
BW		 971 for_each_ring(useless, dev_priv, i) {
972 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
973 if (mbox_reg != GEN6_NOSYNC) {
974 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
975 intel_ring_emit(signaller, mbox_reg);
976 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
78325f2d
BW		 977 }
978 }
024a43e1 979
a1444b79
BW		 980 /* If num_dwords was rounded, make sure the tail pointer is correct */
981 if (num_rings % 2 == 0)
982 intel_ring_emit(signaller, MI_NOOP);
983
024a43e1 984 return 0;
1ec14ad3
CW		 985}
986
c8c99b0f
BW		 987/**
988 * gen6_add_request - Update the semaphore mailbox registers
989 *
990 * @ring - ring that is adding a request
991 * @seqno - return seqno stuck into the ring
992 *
993 * Update the mailbox registers in the *other* rings with the current seqno.
994 * This acts like a signal in the canonical semaphore.
995 */
1ec14ad3 996static int
a4872ba6 997gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 998{
024a43e1 999 int ret;
52ed2325 1000
707d9cf9
BW		 1001 if (ring->semaphore.signal)
1002 ret = ring->semaphore.signal(ring, 4);
1003 else
1004 ret = intel_ring_begin(ring, 4);
1005
1ec14ad3
CW		 1006 if (ret)
1007 return ret;
1008
1ec14ad3
CW		 1009 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1010 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1823521d 1011 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1ec14ad3 1012 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1013 __intel_ring_advance(ring);
1ec14ad3 1014
1ec14ad3
CW		 1015 return 0;
1016}
1017
f72b3435
MK		 1018static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1019 u32 seqno)
1020{
1021 struct drm_i915_private *dev_priv = dev->dev_private;
1022 return dev_priv->last_seqno < seqno;
1023}
1024
c8c99b0f
BW		 1025/**
1026 * intel_ring_sync - sync the waiter to the signaller on seqno
1027 *
1028 * @waiter - ring that is waiting
1029 * @signaller - ring which has, or will signal
1030 * @seqno - seqno which the waiter will block on
1031 */
5ee426ca
BW		 1032
1033static int
1034gen8_ring_sync(struct intel_engine_cs *waiter,
1035 struct intel_engine_cs *signaller,
1036 u32 seqno)
1037{
1038 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1039 int ret;
1040
1041 ret = intel_ring_begin(waiter, 4);
1042 if (ret)
1043 return ret;
1044
1045 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1046 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1047 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1048 MI_SEMAPHORE_SAD_GTE_SDD);
1049 intel_ring_emit(waiter, seqno);
1050 intel_ring_emit(waiter,
1051 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1052 intel_ring_emit(waiter,
1053 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1054 intel_ring_advance(waiter);
1055 return 0;
1056}
1057
c8c99b0f 1058static int
a4872ba6
OM		 1059gen6_ring_sync(struct intel_engine_cs *waiter,
1060 struct intel_engine_cs *signaller,
686cb5f9 1061 u32 seqno)
1ec14ad3 1062{
c8c99b0f
BW		 1063 u32 dw1 = MI_SEMAPHORE_MBOX |
1064 MI_SEMAPHORE_COMPARE |
1065 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1066 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1067 int ret;
1ec14ad3 1068
1500f7ea
BW		 1069 /* Throughout all of the GEM code, seqno passed implies our current
1070 * seqno is >= the last seqno executed. However for hardware the
1071 * comparison is strictly greater than.
1072 */
1073 seqno -= 1;
1074
ebc348b2 1075 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1076
c8c99b0f 1077 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1078 if (ret)
1079 return ret;
1080
f72b3435
MK		 1081 /* If seqno wrap happened, omit the wait with no-ops */
1082 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1083 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1084 intel_ring_emit(waiter, seqno);
1085 intel_ring_emit(waiter, 0);
1086 intel_ring_emit(waiter, MI_NOOP);
1087 } else {
1088 intel_ring_emit(waiter, MI_NOOP);
1089 intel_ring_emit(waiter, MI_NOOP);
1090 intel_ring_emit(waiter, MI_NOOP);
1091 intel_ring_emit(waiter, MI_NOOP);
1092 }
c8c99b0f 1093 intel_ring_advance(waiter);
1ec14ad3
CW		 1094
1095 return 0;
1096}
1097
c6df541c
CW		 1098#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1099do { \
fcbc34e4
KG		 1100 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1101 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1102 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1103 intel_ring_emit(ring__, 0); \
1104 intel_ring_emit(ring__, 0); \
1105} while (0)
1106
1107static int
a4872ba6 1108pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1109{
18393f63 1110 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1111 int ret;
1112
1113 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1114 * incoherent with writes to memory, i.e. completely fubar,
1115 * so we need to use PIPE_NOTIFY instead.
1116 *
1117 * However, we also need to workaround the qword write
1118 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1119 * memory before requesting an interrupt.
1120 */
1121 ret = intel_ring_begin(ring, 32);
1122 if (ret)
1123 return ret;
1124
fcbc34e4 1125 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1126 PIPE_CONTROL_WRITE_FLUSH |
1127 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1128 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1823521d 1129 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
c6df541c
CW		 1130 intel_ring_emit(ring, 0);
1131 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1132 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1133 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1134 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1135 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1136 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1137 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1138 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1139 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1140 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1141 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1142
fcbc34e4 1143 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1144 PIPE_CONTROL_WRITE_FLUSH |
1145 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1146 PIPE_CONTROL_NOTIFY);
0d1aacac 1147 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1823521d 1148 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
c6df541c 1149 intel_ring_emit(ring, 0);
09246732 1150 __intel_ring_advance(ring);
c6df541c 1151
c6df541c
CW		 1152 return 0;
1153}
1154
4cd53c0c 1155static u32
a4872ba6 1156gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1157{
4cd53c0c
DV		 1158 /* Workaround to force correct ordering between irq and seqno writes on
1159 * ivb (and maybe also on snb) by reading from a CS register (like
1160 * ACTHD) before reading the status page. */
50877445
CW		 1161 if (!lazy_coherency) {
1162 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1163 POSTING_READ(RING_ACTHD(ring->mmio_base));
1164 }
1165
4cd53c0c
DV		 1166 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1167}
1168
8187a2b7 1169static u32
a4872ba6 1170ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1171{
1ec14ad3
CW		 1172 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1173}
1174
b70ec5bf 1175static void
a4872ba6 1176ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1177{
1178 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1179}
1180
c6df541c 1181static u32
a4872ba6 1182pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1183{
0d1aacac 1184 return ring->scratch.cpu_page[0];
c6df541c
CW		 1185}
1186
b70ec5bf 1187static void
a4872ba6 1188pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1189{
0d1aacac 1190 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1191}
1192
e48d8634 1193static bool
a4872ba6 1194gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1195{
1196 struct drm_device *dev = ring->dev;
4640c4ff 1197 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1198 unsigned long flags;
e48d8634 1199
7cd512f1 1200 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1201 return false;
1202
7338aefa 1203 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1204 if (ring->irq_refcount++ == 0)
480c8033 1205 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1206 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1207
1208 return true;
1209}
1210
1211static void
a4872ba6 1212gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1213{
1214 struct drm_device *dev = ring->dev;
4640c4ff 1215 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1216 unsigned long flags;
e48d8634 1217
7338aefa 1218 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1219 if (--ring->irq_refcount == 0)
480c8033 1220 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1221 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1222}
1223
b13c2b96 1224static bool
a4872ba6 1225i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1226{
78501eac 1227 struct drm_device *dev = ring->dev;
4640c4ff 1228 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1229 unsigned long flags;
62fdfeaf 1230
7cd512f1 1231 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1232 return false;
1233
7338aefa 1234 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1235 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1236 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1237 I915_WRITE(IMR, dev_priv->irq_mask);
1238 POSTING_READ(IMR);
1239 }
7338aefa 1240 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1241
1242 return true;
62fdfeaf
EA		 1243}
1244
8187a2b7 1245static void
a4872ba6 1246i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1247{
78501eac 1248 struct drm_device *dev = ring->dev;
4640c4ff 1249 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1250 unsigned long flags;
62fdfeaf 1251
7338aefa 1252 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1253 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1254 dev_priv->irq_mask |= ring->irq_enable_mask;
1255 I915_WRITE(IMR, dev_priv->irq_mask);
1256 POSTING_READ(IMR);
1257 }
7338aefa 1258 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1259}
1260
c2798b19 1261static bool
a4872ba6 1262i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1263{
1264 struct drm_device *dev = ring->dev;
4640c4ff 1265 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1266 unsigned long flags;
c2798b19 1267
7cd512f1 1268 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1269 return false;
1270
7338aefa 1271 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1272 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1273 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1274 I915_WRITE16(IMR, dev_priv->irq_mask);
1275 POSTING_READ16(IMR);
1276 }
7338aefa 1277 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1278
1279 return true;
1280}
1281
1282static void
a4872ba6 1283i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1284{
1285 struct drm_device *dev = ring->dev;
4640c4ff 1286 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1287 unsigned long flags;
c2798b19 1288
7338aefa 1289 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1290 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1291 dev_priv->irq_mask |= ring->irq_enable_mask;
1292 I915_WRITE16(IMR, dev_priv->irq_mask);
1293 POSTING_READ16(IMR);
1294 }
7338aefa 1295 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1296}
1297
a4872ba6 1298void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1299{
4593010b 1300 struct drm_device *dev = ring->dev;
4640c4ff 1301 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1302 u32 mmio = 0;
1303
1304 /* The ring status page addresses are no longer next to the rest of
1305 * the ring registers as of gen7.
1306 */
1307 if (IS_GEN7(dev)) {
1308 switch (ring->id) {
96154f2f 1309 case RCS:
4593010b
EA		 1310 mmio = RENDER_HWS_PGA_GEN7;
1311 break;
96154f2f 1312 case BCS:
4593010b
EA		 1313 mmio = BLT_HWS_PGA_GEN7;
1314 break;
77fe2ff3
ZY		 1315 /*
1316 * VCS2 actually doesn't exist on Gen7. Only shut up
1317 * gcc switch check warning
1318 */
1319 case VCS2:
96154f2f 1320 case VCS:
4593010b
EA		 1321 mmio = BSD_HWS_PGA_GEN7;
1322 break;
4a3dd19d 1323 case VECS:
9a8a2213
BW		 1324 mmio = VEBOX_HWS_PGA_GEN7;
1325 break;
4593010b
EA		 1326 }
1327 } else if (IS_GEN6(ring->dev)) {
1328 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1329 } else {
eb0d4b75 1330 /* XXX: gen8 returns to sanity */
4593010b
EA		 1331 mmio = RING_HWS_PGA(ring->mmio_base);
1332 }
1333
78501eac
CW		 1334 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1335 POSTING_READ(mmio);
884020bf 1336
dc616b89
DL		 1337 /*
1338 * Flush the TLB for this page
1339 *
1340 * FIXME: These two bits have disappeared on gen8, so a question
1341 * arises: do we still need this and if so how should we go about
1342 * invalidating the TLB?
1343 */
1344 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1345 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1346
1347 /* ring should be idle before issuing a sync flush*/
1348 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1349
884020bf
CW		 1350 I915_WRITE(reg,
1351 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1352 INSTPM_SYNC_FLUSH));
1353 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1354 1000))
1355 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1356 ring->name);
1357 }
8187a2b7
ZN		 1358}
1359
b72f3acb 1360static int
a4872ba6 1361bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1362 u32 invalidate_domains,
1363 u32 flush_domains)
d1b851fc 1364{
b72f3acb
CW		 1365 int ret;
1366
b72f3acb
CW		 1367 ret = intel_ring_begin(ring, 2);
1368 if (ret)
1369 return ret;
1370
1371 intel_ring_emit(ring, MI_FLUSH);
1372 intel_ring_emit(ring, MI_NOOP);
1373 intel_ring_advance(ring);
1374 return 0;
d1b851fc
ZN		 1375}
1376
3cce469c 1377static int
a4872ba6 1378i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1379{
3cce469c
CW		 1380 int ret;
1381
1382 ret = intel_ring_begin(ring, 4);
1383 if (ret)
1384 return ret;
6f392d54 1385
3cce469c
CW		 1386 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1387 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1823521d 1388 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
3cce469c 1389 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1390 __intel_ring_advance(ring);
d1b851fc 1391
3cce469c 1392 return 0;
d1b851fc
ZN		 1393}
1394
0f46832f 1395static bool
a4872ba6 1396gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1397{
1398 struct drm_device *dev = ring->dev;
4640c4ff 1399 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1400 unsigned long flags;
0f46832f 1401
7cd512f1
DV		 1402 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1403 return false;
0f46832f 1404
7338aefa 1405 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1406 if (ring->irq_refcount++ == 0) {
040d2baa 1407 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1408 I915_WRITE_IMR(ring,
1409 ~(ring->irq_enable_mask |
35a85ac6 1410 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1411 else
1412 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1413 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1414 }
7338aefa 1415 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1416
1417 return true;
1418}
1419
1420static void
a4872ba6 1421gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1422{
1423 struct drm_device *dev = ring->dev;
4640c4ff 1424 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1425 unsigned long flags;
0f46832f 1426
7338aefa 1427 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1428 if (--ring->irq_refcount == 0) {
040d2baa 1429 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1430 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1431 else
1432 I915_WRITE_IMR(ring, ~0);
480c8033 1433 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1434 }
7338aefa 1435 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1436}
1437
a19d2933 1438static bool
a4872ba6 1439hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1440{
1441 struct drm_device *dev = ring->dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 unsigned long flags;
1444
7cd512f1 1445 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1446 return false;
1447
59cdb63d 1448 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1449 if (ring->irq_refcount++ == 0) {
a19d2933 1450 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1451 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1452 }
59cdb63d 1453 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1454
1455 return true;
1456}
1457
1458static void
a4872ba6 1459hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1460{
1461 struct drm_device *dev = ring->dev;
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 unsigned long flags;
1464
59cdb63d 1465 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1466 if (--ring->irq_refcount == 0) {
a19d2933 1467 I915_WRITE_IMR(ring, ~0);
480c8033 1468 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1469 }
59cdb63d 1470 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1471}
1472
abd58f01 1473static bool
a4872ba6 1474gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1475{
1476 struct drm_device *dev = ring->dev;
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 unsigned long flags;
1479
7cd512f1 1480 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1481 return false;
1482
1483 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1484 if (ring->irq_refcount++ == 0) {
1485 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1486 I915_WRITE_IMR(ring,
1487 ~(ring->irq_enable_mask |
1488 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1489 } else {
1490 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1491 }
1492 POSTING_READ(RING_IMR(ring->mmio_base));
1493 }
1494 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1495
1496 return true;
1497}
1498
1499static void
a4872ba6 1500gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1501{
1502 struct drm_device *dev = ring->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 unsigned long flags;
1505
1506 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1507 if (--ring->irq_refcount == 0) {
1508 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1509 I915_WRITE_IMR(ring,
1510 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1511 } else {
1512 I915_WRITE_IMR(ring, ~0);
1513 }
1514 POSTING_READ(RING_IMR(ring->mmio_base));
1515 }
1516 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1517}
1518
d1b851fc 1519static int
a4872ba6 1520i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1521 u64 offset, u32 length,
d7d4eedd 1522 unsigned flags)
d1b851fc 1523{
e1f99ce6 1524 int ret;
78501eac 1525
e1f99ce6
CW		 1526 ret = intel_ring_begin(ring, 2);
1527 if (ret)
1528 return ret;
1529
78501eac 1530 intel_ring_emit(ring,
65f56876
CW		 1531 MI_BATCH_BUFFER_START |
1532 MI_BATCH_GTT |
d7d4eedd 1533 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1534 intel_ring_emit(ring, offset);
78501eac
CW		 1535 intel_ring_advance(ring);
1536
d1b851fc
ZN		 1537 return 0;
1538}
1539
b45305fc
DV		 1540/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1541#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1542#define I830_TLB_ENTRIES (2)
1543#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1544static int
a4872ba6 1545i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1546 u64 offset, u32 len,
d7d4eedd 1547 unsigned flags)
62fdfeaf 1548{
c4d69da1 1549 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1550 int ret;
62fdfeaf 1551
c4d69da1
CW		 1552 ret = intel_ring_begin(ring, 6);
1553 if (ret)
1554 return ret;
62fdfeaf 1555
c4d69da1
CW		 1556 /* Evict the invalid PTE TLBs */
1557 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1558 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1559 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1560 intel_ring_emit(ring, cs_offset);
1561 intel_ring_emit(ring, 0xdeadbeef);
1562 intel_ring_emit(ring, MI_NOOP);
1563 intel_ring_advance(ring);
b45305fc 1564
c4d69da1 1565 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1566 if (len > I830_BATCH_LIMIT)
1567 return -ENOSPC;
1568
c4d69da1 1569 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1570 if (ret)
1571 return ret;
c4d69da1
CW		 1572
1573 /* Blit the batch (which has now all relocs applied) to the
1574 * stable batch scratch bo area (so that the CS never
1575 * stumbles over its tlb invalidation bug) ...
1576 */
1577 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1578 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1579 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024);
b45305fc 1580 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1581 intel_ring_emit(ring, 4096);
1582 intel_ring_emit(ring, offset);
c4d69da1 1583
b45305fc 1584 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1585 intel_ring_emit(ring, MI_NOOP);
1586 intel_ring_advance(ring);
b45305fc
DV		 1587
1588 /* ... and execute it. */
c4d69da1 1589 offset = cs_offset;
b45305fc 1590 }
e1f99ce6 1591
c4d69da1
CW		 1592 ret = intel_ring_begin(ring, 4);
1593 if (ret)
1594 return ret;
1595
1596 intel_ring_emit(ring, MI_BATCH_BUFFER);
1597 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1598 intel_ring_emit(ring, offset + len - 8);
1599 intel_ring_emit(ring, MI_NOOP);
1600 intel_ring_advance(ring);
1601
fb3256da
DV		 1602 return 0;
1603}
1604
1605static int
a4872ba6 1606i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1607 u64 offset, u32 len,
d7d4eedd 1608 unsigned flags)
fb3256da
DV		 1609{
1610 int ret;
1611
1612 ret = intel_ring_begin(ring, 2);
1613 if (ret)
1614 return ret;
1615
65f56876 1616 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1617 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1618 intel_ring_advance(ring);
62fdfeaf 1619
62fdfeaf
EA		 1620 return 0;
1621}
1622
a4872ba6 1623static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1624{
05394f39 1625 struct drm_i915_gem_object *obj;
62fdfeaf 1626
8187a2b7
ZN		 1627 obj = ring->status_page.obj;
1628 if (obj == NULL)
62fdfeaf 1629 return;
62fdfeaf 1630
9da3da66 1631 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1632 i915_gem_object_ggtt_unpin(obj);
05394f39 1633 drm_gem_object_unreference(&obj->base);
8187a2b7 1634 ring->status_page.obj = NULL;
62fdfeaf
EA		 1635}
1636
a4872ba6 1637static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1638{
05394f39 1639 struct drm_i915_gem_object *obj;
62fdfeaf 1640
e3efda49 1641 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1642 unsigned flags;
e3efda49 1643 int ret;
e4ffd173 1644
e3efda49
CW		 1645 obj = i915_gem_alloc_object(ring->dev, 4096);
1646 if (obj == NULL) {
1647 DRM_ERROR("Failed to allocate status page\n");
1648 return -ENOMEM;
1649 }
62fdfeaf 1650
e3efda49
CW		 1651 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1652 if (ret)
1653 goto err_unref;
1654
1f767e02
CW		 1655 flags = 0;
1656 if (!HAS_LLC(ring->dev))
1657 /* On g33, we cannot place HWS above 256MiB, so
1658 * restrict its pinning to the low mappable arena.
1659 * Though this restriction is not documented for
1660 * gen4, gen5, or byt, they also behave similarly
1661 * and hang if the HWS is placed at the top of the
1662 * GTT. To generalise, it appears that all !llc
1663 * platforms have issues with us placing the HWS
1664 * above the mappable region (even though we never
1665 * actualy map it).
1666 */
1667 flags |= PIN_MAPPABLE;
1668 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1669 if (ret) {
1670err_unref:
1671 drm_gem_object_unreference(&obj->base);
1672 return ret;
1673 }
1674
1675 ring->status_page.obj = obj;
1676 }
62fdfeaf 1677
f343c5f6 1678 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1679 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1680 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1681
8187a2b7
ZN		 1682 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1683 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1684
1685 return 0;
62fdfeaf
EA		 1686}
1687
a4872ba6 1688static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1689{
1690 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1691
1692 if (!dev_priv->status_page_dmah) {
1693 dev_priv->status_page_dmah =
1694 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1695 if (!dev_priv->status_page_dmah)
1696 return -ENOMEM;
1697 }
1698
6b8294a4
CW		 1699 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1700 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1701
1702 return 0;
1703}
1704
84c2377f 1705void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291
OM		 1706{
1707 if (!ringbuf->obj)
1708 return;
1709
1710 iounmap(ringbuf->virtual_start);
1711 i915_gem_object_ggtt_unpin(ringbuf->obj);
1712 drm_gem_object_unreference(&ringbuf->obj->base);
1713 ringbuf->obj = NULL;
1714}
1715
84c2377f
OM		 1716int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1717 struct intel_ringbuffer *ringbuf)
62fdfeaf 1718{
e3efda49 1719 struct drm_i915_private *dev_priv = to_i915(dev);
05394f39 1720 struct drm_i915_gem_object *obj;
dd785e35
CW		 1721 int ret;
1722
2919d291 1723 if (ringbuf->obj)
e3efda49 1724 return 0;
62fdfeaf 1725
ebc052e0
CW		 1726 obj = NULL;
1727 if (!HAS_LLC(dev))
93b0a4e0 1728 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1729 if (obj == NULL)
93b0a4e0 1730 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1731 if (obj == NULL)
1732 return -ENOMEM;
8187a2b7 1733
24f3a8cf
AG		 1734 /* mark ring buffers as read-only from GPU side by default */
1735 obj->gt_ro = 1;
1736
1ec9e26d 1737 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
dd785e35
CW		 1738 if (ret)
1739 goto err_unref;
62fdfeaf 1740
3eef8918
CW		 1741 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1742 if (ret)
1743 goto err_unpin;
1744
93b0a4e0 1745 ringbuf->virtual_start =
f343c5f6 1746 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
93b0a4e0
OM		 1747 ringbuf->size);
1748 if (ringbuf->virtual_start == NULL) {
8187a2b7 1749 ret = -EINVAL;
dd785e35 1750 goto err_unpin;
62fdfeaf
EA		 1751 }
1752
93b0a4e0 1753 ringbuf->obj = obj;
e3efda49
CW		 1754 return 0;
1755
1756err_unpin:
1757 i915_gem_object_ggtt_unpin(obj);
1758err_unref:
1759 drm_gem_object_unreference(&obj->base);
1760 return ret;
1761}
1762
1763static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1764 struct intel_engine_cs *ring)
e3efda49 1765{
8ee14975 1766 struct intel_ringbuffer *ringbuf = ring->buffer;
e3efda49
CW		 1767 int ret;
1768
8ee14975
OM		 1769 if (ringbuf == NULL) {
1770 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1771 if (!ringbuf)
1772 return -ENOMEM;
1773 ring->buffer = ringbuf;
1774 }
1775
e3efda49
CW		 1776 ring->dev = dev;
1777 INIT_LIST_HEAD(&ring->active_list);
1778 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1779 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1780 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1781 ringbuf->ring = ring;
ebc348b2 1782 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1783
1784 init_waitqueue_head(&ring->irq_queue);
1785
1786 if (I915_NEED_GFX_HWS(dev)) {
1787 ret = init_status_page(ring);
1788 if (ret)
8ee14975 1789 goto error;
e3efda49
CW		 1790 } else {
1791 BUG_ON(ring->id != RCS);
1792 ret = init_phys_status_page(ring);
1793 if (ret)
8ee14975 1794 goto error;
e3efda49
CW		 1795 }
1796
2919d291 1797 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
e3efda49
CW		 1798 if (ret) {
1799 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
8ee14975 1800 goto error;
e3efda49 1801 }
62fdfeaf 1802
55249baa
CW		 1803 /* Workaround an erratum on the i830 which causes a hang if
1804 * the TAIL pointer points to within the last 2 cachelines
1805 * of the buffer.
1806 */
93b0a4e0 1807 ringbuf->effective_size = ringbuf->size;
e3efda49 1808 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1809 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1810
44e895a8
BV		 1811 ret = i915_cmd_parser_init_ring(ring);
1812 if (ret)
8ee14975
OM		 1813 goto error;
1814
1815 ret = ring->init(ring);
1816 if (ret)
1817 goto error;
1818
1819 return 0;
351e3db2 1820
8ee14975
OM		 1821error:
1822 kfree(ringbuf);
1823 ring->buffer = NULL;
1824 return ret;
62fdfeaf
EA		 1825}
1826
a4872ba6 1827void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1828{
e3efda49 1829 struct drm_i915_private *dev_priv = to_i915(ring->dev);
93b0a4e0 1830 struct intel_ringbuffer *ringbuf = ring->buffer;
33626e6a 1831
93b0a4e0 1832 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1833 return;
1834
e3efda49 1835 intel_stop_ring_buffer(ring);
de8f0a50 1836 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1837
2919d291 1838 intel_destroy_ringbuffer_obj(ringbuf);
3d57e5bd
BW		 1839 ring->preallocated_lazy_request = NULL;
1840 ring->outstanding_lazy_seqno = 0;
78501eac 1841
8d19215b
ZN		 1842 if (ring->cleanup)
1843 ring->cleanup(ring);
1844
78501eac 1845 cleanup_status_page(ring);
44e895a8
BV		 1846
1847 i915_cmd_parser_fini_ring(ring);
8ee14975 1848
93b0a4e0 1849 kfree(ringbuf);
8ee14975 1850 ring->buffer = NULL;
62fdfeaf
EA		 1851}
1852
a4872ba6 1853static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1854{
93b0a4e0 1855 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1856 struct drm_i915_gem_request *request;
1cf0ba14 1857 u32 seqno = 0;
a71d8d94
CW		 1858 int ret;
1859
93b0a4e0
OM		 1860 if (ringbuf->last_retired_head != -1) {
1861 ringbuf->head = ringbuf->last_retired_head;
1862 ringbuf->last_retired_head = -1;
1f70999f 1863
82e104cc 1864 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1865 if (ringbuf->space >= n)
a71d8d94
CW		 1866 return 0;
1867 }
1868
1869 list_for_each_entry(request, &ring->request_list, list) {
82e104cc
OM		 1870 if (__intel_ring_space(request->tail, ringbuf->tail,
1871 ringbuf->size) >= n) {
a71d8d94
CW		 1872 seqno = request->seqno;
1873 break;
1874 }
a71d8d94
CW		 1875 }
1876
1877 if (seqno == 0)
1878 return -ENOSPC;
1879
1f70999f 1880 ret = i915_wait_seqno(ring, seqno);
a71d8d94
CW		 1881 if (ret)
1882 return ret;
1883
1cf0ba14 1884 i915_gem_retire_requests_ring(ring);
93b0a4e0
OM		 1885 ringbuf->head = ringbuf->last_retired_head;
1886 ringbuf->last_retired_head = -1;
a71d8d94 1887
82e104cc 1888 ringbuf->space = intel_ring_space(ringbuf);
a71d8d94
CW		 1889 return 0;
1890}
1891
a4872ba6 1892static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1893{
78501eac 1894 struct drm_device *dev = ring->dev;
cae5852d 1895 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1896 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1897 unsigned long end;
a71d8d94 1898 int ret;
c7dca47b 1899
a71d8d94
CW		 1900 ret = intel_ring_wait_request(ring, n);
1901 if (ret != -ENOSPC)
1902 return ret;
1903
09246732
CW		 1904 /* force the tail write in case we have been skipping them */
1905 __intel_ring_advance(ring);
1906
63ed2cb2
DV		 1907 /* With GEM the hangcheck timer should kick us out of the loop,
1908 * leaving it early runs the risk of corrupting GEM state (due
1909 * to running on almost untested codepaths). But on resume
1910 * timers don't work yet, so prevent a complete hang in that
1911 * case by choosing an insanely large timeout. */
1912 end = jiffies + 60 * HZ;
e6bfaf85 1913
dcfe0506 1914 trace_i915_ring_wait_begin(ring);
8187a2b7 1915 do {
93b0a4e0 1916 ringbuf->head = I915_READ_HEAD(ring);
82e104cc 1917 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1918 if (ringbuf->space >= n) {
dcfe0506
CW		 1919 ret = 0;
1920 break;
62fdfeaf
EA		 1921 }
1922
fb19e2ac
DV		 1923 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1924 dev->primary->master) {
62fdfeaf
EA		 1925 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1926 if (master_priv->sarea_priv)
1927 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1928 }
d1b851fc 1929
e60a0b10 1930 msleep(1);
d6b2c790 1931
dcfe0506
CW		 1932 if (dev_priv->mm.interruptible && signal_pending(current)) {
1933 ret = -ERESTARTSYS;
1934 break;
1935 }
1936
33196ded
DV		 1937 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1938 dev_priv->mm.interruptible);
d6b2c790 1939 if (ret)
dcfe0506
CW		 1940 break;
1941
1942 if (time_after(jiffies, end)) {
1943 ret = -EBUSY;
1944 break;
1945 }
1946 } while (1);
db53a302 1947 trace_i915_ring_wait_end(ring);
dcfe0506 1948 return ret;
8187a2b7 1949}
62fdfeaf 1950
a4872ba6 1951static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 1952{
1953 uint32_t __iomem *virt;
93b0a4e0
OM		 1954 struct intel_ringbuffer *ringbuf = ring->buffer;
1955 int rem = ringbuf->size - ringbuf->tail;
3e960501 1956
93b0a4e0 1957 if (ringbuf->space < rem) {
3e960501
CW		 1958 int ret = ring_wait_for_space(ring, rem);
1959 if (ret)
1960 return ret;
1961 }
1962
93b0a4e0 1963 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 1964 rem /= 4;
1965 while (rem--)
1966 iowrite32(MI_NOOP, virt++);
1967
93b0a4e0 1968 ringbuf->tail = 0;
82e104cc 1969 ringbuf->space = intel_ring_space(ringbuf);
3e960501
CW		 1970
1971 return 0;
1972}
1973
a4872ba6 1974int intel_ring_idle(struct intel_engine_cs *ring)
3e960501
CW		 1975{
1976 u32 seqno;
1977 int ret;
1978
1979 /* We need to add any requests required to flush the objects and ring */
1823521d 1980 if (ring->outstanding_lazy_seqno) {
0025c077 1981 ret = i915_add_request(ring, NULL);
3e960501
CW		 1982 if (ret)
1983 return ret;
1984 }
1985
1986 /* Wait upon the last request to be completed */
1987 if (list_empty(&ring->request_list))
1988 return 0;
1989
1990 seqno = list_entry(ring->request_list.prev,
1991 struct drm_i915_gem_request,
1992 list)->seqno;
1993
1994 return i915_wait_seqno(ring, seqno);
1995}
1996
9d773091 1997static int
a4872ba6 1998intel_ring_alloc_seqno(struct intel_engine_cs *ring)
9d773091 1999{
1823521d 2000 if (ring->outstanding_lazy_seqno)
9d773091
CW		 2001 return 0;
2002
3c0e234c
CW		 2003 if (ring->preallocated_lazy_request == NULL) {
2004 struct drm_i915_gem_request *request;
2005
2006 request = kmalloc(sizeof(*request), GFP_KERNEL);
2007 if (request == NULL)
2008 return -ENOMEM;
2009
2010 ring->preallocated_lazy_request = request;
2011 }
2012
1823521d 2013 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
9d773091
CW		 2014}
2015
a4872ba6 2016static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2017 int bytes)
cbcc80df 2018{
93b0a4e0 2019 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2020 int ret;
2021
93b0a4e0 2022 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2023 ret = intel_wrap_ring_buffer(ring);
2024 if (unlikely(ret))
2025 return ret;
2026 }
2027
93b0a4e0 2028 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2029 ret = ring_wait_for_space(ring, bytes);
2030 if (unlikely(ret))
2031 return ret;
2032 }
2033
cbcc80df
MK		 2034 return 0;
2035}
2036
a4872ba6 2037int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2038 int num_dwords)
8187a2b7 2039{
4640c4ff 2040 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2041 int ret;
78501eac 2042
33196ded
DV		 2043 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2044 dev_priv->mm.interruptible);
de2b9985
DV		 2045 if (ret)
2046 return ret;
21dd3734 2047
304d695c
CW		 2048 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2049 if (ret)
2050 return ret;
2051
9d773091
CW		 2052 /* Preallocate the olr before touching the ring */
2053 ret = intel_ring_alloc_seqno(ring);
2054 if (ret)
2055 return ret;
2056
ee1b1e5e 2057 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2058 return 0;
8187a2b7 2059}
78501eac 2060
753b1ad4 2061/* Align the ring tail to a cacheline boundary */
a4872ba6 2062int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2063{
ee1b1e5e 2064 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2065 int ret;
2066
2067 if (num_dwords == 0)
2068 return 0;
2069
18393f63 2070 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2071 ret = intel_ring_begin(ring, num_dwords);
2072 if (ret)
2073 return ret;
2074
2075 while (num_dwords--)
2076 intel_ring_emit(ring, MI_NOOP);
2077
2078 intel_ring_advance(ring);
2079
2080 return 0;
2081}
2082
a4872ba6 2083void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2084{
3b2cc8ab
OM		 2085 struct drm_device *dev = ring->dev;
2086 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2087
1823521d 2088 BUG_ON(ring->outstanding_lazy_seqno);
498d2ac1 2089
3b2cc8ab 2090 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2091 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2092 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2093 if (HAS_VEBOX(dev))
5020150b 2094 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2095 }
d97ed339 2096
f7e98ad4 2097 ring->set_seqno(ring, seqno);
92cab734 2098 ring->hangcheck.seqno = seqno;
8187a2b7 2099}
62fdfeaf 2100
a4872ba6 2101static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2102 u32 value)
881f47b6 2103{
4640c4ff 2104 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2105
2106 /* Every tail move must follow the sequence below */
12f55818
CW		 2107
2108 /* Disable notification that the ring is IDLE. The GT
2109 * will then assume that it is busy and bring it out of rc6.
2110 */
0206e353 2111 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2112 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2113
2114 /* Clear the context id. Here be magic! */
2115 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2116
12f55818 2117 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2118 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2119 GEN6_BSD_SLEEP_INDICATOR) == 0,
2120 50))
2121 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2122
12f55818 2123 /* Now that the ring is fully powered up, update the tail */
0206e353 2124 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2125 POSTING_READ(RING_TAIL(ring->mmio_base));
2126
2127 /* Let the ring send IDLE messages to the GT again,
2128 * and so let it sleep to conserve power when idle.
2129 */
0206e353 2130 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2131 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2132}
2133
a4872ba6 2134static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2135 u32 invalidate, u32 flush)
881f47b6 2136{
71a77e07 2137 uint32_t cmd;
b72f3acb
CW		 2138 int ret;
2139
b72f3acb
CW		 2140 ret = intel_ring_begin(ring, 4);
2141 if (ret)
2142 return ret;
2143
71a77e07 2144 cmd = MI_FLUSH_DW;
075b3bba
BW		 2145 if (INTEL_INFO(ring->dev)->gen >= 8)
2146 cmd += 1;
9a289771
JB		 2147 /*
2148 * Bspec vol 1c.5 - video engine command streamer:
2149 * "If ENABLED, all TLBs will be invalidated once the flush
2150 * operation is complete. This bit is only valid when the
2151 * Post-Sync Operation field is a value of 1h or 3h."
2152 */
71a77e07 2153 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2154 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2155 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2156 intel_ring_emit(ring, cmd);
9a289771 2157 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2158 if (INTEL_INFO(ring->dev)->gen >= 8) {
2159 intel_ring_emit(ring, 0); /* upper addr */
2160 intel_ring_emit(ring, 0); /* value */
2161 } else {
2162 intel_ring_emit(ring, 0);
2163 intel_ring_emit(ring, MI_NOOP);
2164 }
b72f3acb
CW		 2165 intel_ring_advance(ring);
2166 return 0;
881f47b6
XH		 2167}
2168
1c7a0623 2169static int
a4872ba6 2170gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2171 u64 offset, u32 len,
1c7a0623
BW		 2172 unsigned flags)
2173{
896ab1a5 2174 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2175 int ret;
2176
2177 ret = intel_ring_begin(ring, 4);
2178 if (ret)
2179 return ret;
2180
2181 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2182 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2183 intel_ring_emit(ring, lower_32_bits(offset));
2184 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2185 intel_ring_emit(ring, MI_NOOP);
2186 intel_ring_advance(ring);
2187
2188 return 0;
2189}
2190
d7d4eedd 2191static int
a4872ba6 2192hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2193 u64 offset, u32 len,
d7d4eedd
CW		 2194 unsigned flags)
2195{
2196 int ret;
2197
2198 ret = intel_ring_begin(ring, 2);
2199 if (ret)
2200 return ret;
2201
2202 intel_ring_emit(ring,
77072258
CW		 2203 MI_BATCH_BUFFER_START |
2204 (flags & I915_DISPATCH_SECURE ?
2205 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2206 /* bit0-7 is the length on GEN6+ */
2207 intel_ring_emit(ring, offset);
2208 intel_ring_advance(ring);
2209
2210 return 0;
2211}
2212
881f47b6 2213static int
a4872ba6 2214gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2215 u64 offset, u32 len,
d7d4eedd 2216 unsigned flags)
881f47b6 2217{
0206e353 2218 int ret;
ab6f8e32 2219
0206e353
AJ		 2220 ret = intel_ring_begin(ring, 2);
2221 if (ret)
2222 return ret;
e1f99ce6 2223
d7d4eedd
CW		 2224 intel_ring_emit(ring,
2225 MI_BATCH_BUFFER_START |
2226 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2227 /* bit0-7 is the length on GEN6+ */
2228 intel_ring_emit(ring, offset);
2229 intel_ring_advance(ring);
ab6f8e32 2230
0206e353 2231 return 0;
881f47b6
XH		 2232}
2233
549f7365
CW		 2234/* Blitter support (SandyBridge+) */
2235
a4872ba6 2236static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2237 u32 invalidate, u32 flush)
8d19215b 2238{
fd3da6c9 2239 struct drm_device *dev = ring->dev;
71a77e07 2240 uint32_t cmd;
b72f3acb
CW		 2241 int ret;
2242
6a233c78 2243 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2244 if (ret)
2245 return ret;
2246
71a77e07 2247 cmd = MI_FLUSH_DW;
075b3bba
BW		 2248 if (INTEL_INFO(ring->dev)->gen >= 8)
2249 cmd += 1;
9a289771
JB		 2250 /*
2251 * Bspec vol 1c.3 - blitter engine command streamer:
2252 * "If ENABLED, all TLBs will be invalidated once the flush
2253 * operation is complete. This bit is only valid when the
2254 * Post-Sync Operation field is a value of 1h or 3h."
2255 */
71a77e07 2256 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2257 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2258 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2259 intel_ring_emit(ring, cmd);
9a289771 2260 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2261 if (INTEL_INFO(ring->dev)->gen >= 8) {
2262 intel_ring_emit(ring, 0); /* upper addr */
2263 intel_ring_emit(ring, 0); /* value */
2264 } else {
2265 intel_ring_emit(ring, 0);
2266 intel_ring_emit(ring, MI_NOOP);
2267 }
b72f3acb 2268 intel_ring_advance(ring);
fd3da6c9 2269
9688ecad 2270 if (IS_GEN7(dev) && !invalidate && flush)
fd3da6c9
RV		 2271 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2272
b72f3acb 2273 return 0;
8d19215b
ZN		 2274}
2275
5c1143bb
XH		 2276int intel_init_render_ring_buffer(struct drm_device *dev)
2277{
4640c4ff 2278 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2279 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2280 struct drm_i915_gem_object *obj;
2281 int ret;
5c1143bb 2282
59465b5f
DV		 2283 ring->name = "render ring";
2284 ring->id = RCS;
2285 ring->mmio_base = RENDER_RING_BASE;
2286
707d9cf9 2287 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2288 if (i915_semaphore_is_enabled(dev)) {
2289 obj = i915_gem_alloc_object(dev, 4096);
2290 if (obj == NULL) {
2291 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2292 i915.semaphores = 0;
2293 } else {
2294 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2295 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2296 if (ret != 0) {
2297 drm_gem_object_unreference(&obj->base);
2298 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2299 i915.semaphores = 0;
2300 } else
2301 dev_priv->semaphore_obj = obj;
2302 }
2303 }
00e1e623
VS		 2304 if (IS_CHERRYVIEW(dev))
2305 ring->init_context = chv_init_workarounds;
2306 else
2307 ring->init_context = bdw_init_workarounds;
707d9cf9
BW		 2308 ring->add_request = gen6_add_request;
2309 ring->flush = gen8_render_ring_flush;
2310 ring->irq_get = gen8_ring_get_irq;
2311 ring->irq_put = gen8_ring_put_irq;
2312 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2313 ring->get_seqno = gen6_ring_get_seqno;
2314 ring->set_seqno = ring_set_seqno;
2315 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2316 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2317 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2318 ring->semaphore.signal = gen8_rcs_signal;
2319 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2320 }
2321 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2322 ring->add_request = gen6_add_request;
4772eaeb 2323 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2324 if (INTEL_INFO(dev)->gen == 6)
b3111509 2325 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2326 ring->irq_get = gen6_ring_get_irq;
2327 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2328 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2329 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2330 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2331 if (i915_semaphore_is_enabled(dev)) {
2332 ring->semaphore.sync_to = gen6_ring_sync;
2333 ring->semaphore.signal = gen6_signal;
2334 /*
2335 * The current semaphore is only applied on pre-gen8
2336 * platform. And there is no VCS2 ring on the pre-gen8
2337 * platform. So the semaphore between RCS and VCS2 is
2338 * initialized as INVALID. Gen8 will initialize the
2339 * sema between VCS2 and RCS later.
2340 */
2341 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2342 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2343 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2344 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2345 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2346 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2347 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2348 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2349 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2350 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2351 }
c6df541c
CW		 2352 } else if (IS_GEN5(dev)) {
2353 ring->add_request = pc_render_add_request;
46f0f8d1 2354 ring->flush = gen4_render_ring_flush;
c6df541c 2355 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2356 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2357 ring->irq_get = gen5_ring_get_irq;
2358 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2359 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2360 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2361 } else {
8620a3a9 2362 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2363 if (INTEL_INFO(dev)->gen < 4)
2364 ring->flush = gen2_render_ring_flush;
2365 else
2366 ring->flush = gen4_render_ring_flush;
59465b5f 2367 ring->get_seqno = ring_get_seqno;
b70ec5bf 2368 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2369 if (IS_GEN2(dev)) {
2370 ring->irq_get = i8xx_ring_get_irq;
2371 ring->irq_put = i8xx_ring_put_irq;
2372 } else {
2373 ring->irq_get = i9xx_ring_get_irq;
2374 ring->irq_put = i9xx_ring_put_irq;
2375 }
e3670319 2376 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2377 }
59465b5f 2378 ring->write_tail = ring_write_tail;
707d9cf9 2379
d7d4eedd
CW		 2380 if (IS_HASWELL(dev))
2381 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2382 else if (IS_GEN8(dev))
2383 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2384 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2385 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2386 else if (INTEL_INFO(dev)->gen >= 4)
2387 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2388 else if (IS_I830(dev) || IS_845G(dev))
2389 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2390 else
2391 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 2392 ring->init = init_render_ring;
2393 ring->cleanup = render_ring_cleanup;
2394
b45305fc
DV		 2395 /* Workaround batchbuffer to combat CS tlb bug. */
2396 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2397 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2398 if (obj == NULL) {
2399 DRM_ERROR("Failed to allocate batch bo\n");
2400 return -ENOMEM;
2401 }
2402
be1fa129 2403 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2404 if (ret != 0) {
2405 drm_gem_object_unreference(&obj->base);
2406 DRM_ERROR("Failed to ping batch bo\n");
2407 return ret;
2408 }
2409
0d1aacac
CW		 2410 ring->scratch.obj = obj;
2411 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2412 }
2413
1ec14ad3 2414 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 2415}
2416
e8616b6c
CW		 2417int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2418{
4640c4ff 2419 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2420 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
8ee14975 2421 struct intel_ringbuffer *ringbuf = ring->buffer;
6b8294a4 2422 int ret;
e8616b6c 2423
8ee14975
OM		 2424 if (ringbuf == NULL) {
2425 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2426 if (!ringbuf)
2427 return -ENOMEM;
2428 ring->buffer = ringbuf;
2429 }
2430
59465b5f
DV		 2431 ring->name = "render ring";
2432 ring->id = RCS;
2433 ring->mmio_base = RENDER_RING_BASE;
2434
e8616b6c 2435 if (INTEL_INFO(dev)->gen >= 6) {
b4178f8a 2436 /* non-kms not supported on gen6+ */
8ee14975
OM		 2437 ret = -ENODEV;
2438 goto err_ringbuf;
e8616b6c 2439 }
28f0cbf7
DV		 2440
2441 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2442 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2443 * the special gen5 functions. */
2444 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2445 if (INTEL_INFO(dev)->gen < 4)
2446 ring->flush = gen2_render_ring_flush;
2447 else
2448 ring->flush = gen4_render_ring_flush;
28f0cbf7 2449 ring->get_seqno = ring_get_seqno;
b70ec5bf 2450 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2451 if (IS_GEN2(dev)) {
2452 ring->irq_get = i8xx_ring_get_irq;
2453 ring->irq_put = i8xx_ring_put_irq;
2454 } else {
2455 ring->irq_get = i9xx_ring_get_irq;
2456 ring->irq_put = i9xx_ring_put_irq;
2457 }
28f0cbf7 2458 ring->irq_enable_mask = I915_USER_INTERRUPT;
59465b5f 2459 ring->write_tail = ring_write_tail;
fb3256da
DV		 2460 if (INTEL_INFO(dev)->gen >= 4)
2461 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2462 else if (IS_I830(dev) || IS_845G(dev))
2463 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2464 else
2465 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 2466 ring->init = init_render_ring;
2467 ring->cleanup = render_ring_cleanup;
e8616b6c
CW		 2468
2469 ring->dev = dev;
2470 INIT_LIST_HEAD(&ring->active_list);
2471 INIT_LIST_HEAD(&ring->request_list);
e8616b6c 2472
93b0a4e0
OM		 2473 ringbuf->size = size;
2474 ringbuf->effective_size = ringbuf->size;
17f10fdc 2475 if (IS_I830(ring->dev) || IS_845G(ring->dev))
93b0a4e0 2476 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
e8616b6c 2477
93b0a4e0
OM		 2478 ringbuf->virtual_start = ioremap_wc(start, size);
2479 if (ringbuf->virtual_start == NULL) {
e8616b6c
CW		 2480 DRM_ERROR("can not ioremap virtual address for"
2481 " ring buffer\n");
8ee14975
OM		 2482 ret = -ENOMEM;
2483 goto err_ringbuf;
e8616b6c
CW		 2484 }
2485
6b8294a4 2486 if (!I915_NEED_GFX_HWS(dev)) {
035dc1e0 2487 ret = init_phys_status_page(ring);
6b8294a4 2488 if (ret)
8ee14975 2489 goto err_vstart;
6b8294a4
CW		 2490 }
2491
e8616b6c 2492 return 0;
8ee14975
OM		 2493
2494err_vstart:
93b0a4e0 2495 iounmap(ringbuf->virtual_start);
8ee14975
OM		 2496err_ringbuf:
2497 kfree(ringbuf);
2498 ring->buffer = NULL;
2499 return ret;
e8616b6c
CW		 2500}
2501
5c1143bb
XH		 2502int intel_init_bsd_ring_buffer(struct drm_device *dev)
2503{
4640c4ff 2504 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2505 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2506
58fa3835
DV		 2507 ring->name = "bsd ring";
2508 ring->id = VCS;
2509
0fd2c201 2510 ring->write_tail = ring_write_tail;
780f18c8 2511 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2512 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2513 /* gen6 bsd needs a special wa for tail updates */
2514 if (IS_GEN6(dev))
2515 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2516 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2517 ring->add_request = gen6_add_request;
2518 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2519 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2520 if (INTEL_INFO(dev)->gen >= 8) {
2521 ring->irq_enable_mask =
2522 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2523 ring->irq_get = gen8_ring_get_irq;
2524 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2525 ring->dispatch_execbuffer =
2526 gen8_ring_dispatch_execbuffer;
707d9cf9 2527 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2528 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2529 ring->semaphore.signal = gen8_xcs_signal;
2530 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2531 }
abd58f01
BW		 2532 } else {
2533 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2534 ring->irq_get = gen6_ring_get_irq;
2535 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2536 ring->dispatch_execbuffer =
2537 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2538 if (i915_semaphore_is_enabled(dev)) {
2539 ring->semaphore.sync_to = gen6_ring_sync;
2540 ring->semaphore.signal = gen6_signal;
2541 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2542 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2543 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2544 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2545 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2546 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2547 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2548 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2549 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2550 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2551 }
abd58f01 2552 }
58fa3835
DV		 2553 } else {
2554 ring->mmio_base = BSD_RING_BASE;
58fa3835 2555 ring->flush = bsd_ring_flush;
8620a3a9 2556 ring->add_request = i9xx_add_request;
58fa3835 2557 ring->get_seqno = ring_get_seqno;
b70ec5bf 2558 ring->set_seqno = ring_set_seqno;
e48d8634 2559 if (IS_GEN5(dev)) {
cc609d5d 2560 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2561 ring->irq_get = gen5_ring_get_irq;
2562 ring->irq_put = gen5_ring_put_irq;
2563 } else {
e3670319 2564 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2565 ring->irq_get = i9xx_ring_get_irq;
2566 ring->irq_put = i9xx_ring_put_irq;
2567 }
fb3256da 2568 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835
DV		 2569 }
2570 ring->init = init_ring_common;
2571
1ec14ad3 2572 return intel_init_ring_buffer(dev, ring);
5c1143bb 2573}
549f7365 2574
845f74a7
ZY		 2575/**
2576 * Initialize the second BSD ring for Broadwell GT3.
2577 * It is noted that this only exists on Broadwell GT3.
2578 */
2579int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2580{
2581 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2582 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2583
2584 if ((INTEL_INFO(dev)->gen != 8)) {
2585 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2586 return -EINVAL;
2587 }
2588
f7b64236 2589 ring->name = "bsd2 ring";
845f74a7
ZY		 2590 ring->id = VCS2;
2591
2592 ring->write_tail = ring_write_tail;
2593 ring->mmio_base = GEN8_BSD2_RING_BASE;
2594 ring->flush = gen6_bsd_ring_flush;
2595 ring->add_request = gen6_add_request;
2596 ring->get_seqno = gen6_ring_get_seqno;
2597 ring->set_seqno = ring_set_seqno;
2598 ring->irq_enable_mask =
2599 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2600 ring->irq_get = gen8_ring_get_irq;
2601 ring->irq_put = gen8_ring_put_irq;
2602 ring->dispatch_execbuffer =
2603 gen8_ring_dispatch_execbuffer;
3e78998a 2604 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2605 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2606 ring->semaphore.signal = gen8_xcs_signal;
2607 GEN8_RING_SEMAPHORE_INIT;
2608 }
845f74a7
ZY		 2609 ring->init = init_ring_common;
2610
2611 return intel_init_ring_buffer(dev, ring);
2612}
2613
549f7365
CW		 2614int intel_init_blt_ring_buffer(struct drm_device *dev)
2615{
4640c4ff 2616 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2617 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2618
3535d9dd
DV		 2619 ring->name = "blitter ring";
2620 ring->id = BCS;
2621
2622 ring->mmio_base = BLT_RING_BASE;
2623 ring->write_tail = ring_write_tail;
ea251324 2624 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2625 ring->add_request = gen6_add_request;
2626 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2627 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2628 if (INTEL_INFO(dev)->gen >= 8) {
2629 ring->irq_enable_mask =
2630 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2631 ring->irq_get = gen8_ring_get_irq;
2632 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2633 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2634 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2635 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2636 ring->semaphore.signal = gen8_xcs_signal;
2637 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2638 }
abd58f01
BW		 2639 } else {
2640 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2641 ring->irq_get = gen6_ring_get_irq;
2642 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2643 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2644 if (i915_semaphore_is_enabled(dev)) {
2645 ring->semaphore.signal = gen6_signal;
2646 ring->semaphore.sync_to = gen6_ring_sync;
2647 /*
2648 * The current semaphore is only applied on pre-gen8
2649 * platform. And there is no VCS2 ring on the pre-gen8
2650 * platform. So the semaphore between BCS and VCS2 is
2651 * initialized as INVALID. Gen8 will initialize the
2652 * sema between BCS and VCS2 later.
2653 */
2654 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2655 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2656 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2657 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2658 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2659 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2660 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2661 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2662 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2663 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2664 }
abd58f01 2665 }
3535d9dd 2666 ring->init = init_ring_common;
549f7365 2667
1ec14ad3 2668 return intel_init_ring_buffer(dev, ring);
549f7365 2669}
a7b9761d 2670
9a8a2213
BW		 2671int intel_init_vebox_ring_buffer(struct drm_device *dev)
2672{
4640c4ff 2673 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2674 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2675
2676 ring->name = "video enhancement ring";
2677 ring->id = VECS;
2678
2679 ring->mmio_base = VEBOX_RING_BASE;
2680 ring->write_tail = ring_write_tail;
2681 ring->flush = gen6_ring_flush;
2682 ring->add_request = gen6_add_request;
2683 ring->get_seqno = gen6_ring_get_seqno;
2684 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2685
2686 if (INTEL_INFO(dev)->gen >= 8) {
2687 ring->irq_enable_mask =
40c499f9 2688 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2689 ring->irq_get = gen8_ring_get_irq;
2690 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2691 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2692 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2693 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2694 ring->semaphore.signal = gen8_xcs_signal;
2695 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2696 }
abd58f01
BW		 2697 } else {
2698 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2699 ring->irq_get = hsw_vebox_get_irq;
2700 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2701 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2702 if (i915_semaphore_is_enabled(dev)) {
2703 ring->semaphore.sync_to = gen6_ring_sync;
2704 ring->semaphore.signal = gen6_signal;
2705 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2706 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2707 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2708 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2709 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2710 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2711 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2712 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2713 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2714 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2715 }
abd58f01 2716 }
9a8a2213
BW		 2717 ring->init = init_ring_common;
2718
2719 return intel_init_ring_buffer(dev, ring);
2720}
2721
a7b9761d 2722int
a4872ba6 2723intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2724{
2725 int ret;
2726
2727 if (!ring->gpu_caches_dirty)
2728 return 0;
2729
2730 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2731 if (ret)
2732 return ret;
2733
2734 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2735
2736 ring->gpu_caches_dirty = false;
2737 return 0;
2738}
2739
2740int
a4872ba6 2741intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2742{
2743 uint32_t flush_domains;
2744 int ret;
2745
2746 flush_domains = 0;
2747 if (ring->gpu_caches_dirty)
2748 flush_domains = I915_GEM_GPU_DOMAINS;
2749
2750 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2751 if (ret)
2752 return ret;
2753
2754 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2755
2756 ring->gpu_caches_dirty = false;
2757 return 0;
2758}
e3efda49
CW		 2759
2760void
a4872ba6 2761intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2762{
2763 int ret;
2764
2765 if (!intel_ring_initialized(ring))
2766 return;
2767
2768 ret = intel_ring_idle(ring);
2769 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2770 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2771 ring->name, ret);
2772
2773 stop_ring(ring);
2774}
Linux kernel - Deliverables
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