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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
18393f63 CW |
36 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
37 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
38 | * to give some inclination as to some of the magic values used in the various | |
39 | * workarounds! | |
40 | */ | |
41 | #define CACHELINE_BYTES 64 | |
42 | ||
48d82387 OM |
43 | bool |
44 | intel_ring_initialized(struct intel_engine_cs *ring) | |
45 | { | |
46 | struct drm_device *dev = ring->dev; | |
47 | ||
48 | if (!dev) | |
49 | return false; | |
50 | ||
51 | if (i915.enable_execlists) { | |
52 | struct intel_context *dctx = ring->default_context; | |
53 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
54 | ||
55 | return ringbuf->obj; | |
56 | } else | |
57 | return ring->buffer && ring->buffer->obj; | |
58 | } | |
59 | ||
82e104cc | 60 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 61 | { |
1cf0ba14 | 62 | int space = head - (tail + I915_RING_FREE_SPACE); |
c7dca47b | 63 | if (space < 0) |
1cf0ba14 | 64 | space += size; |
c7dca47b CW |
65 | return space; |
66 | } | |
67 | ||
82e104cc | 68 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 69 | { |
82e104cc OM |
70 | return __intel_ring_space(ringbuf->head & HEAD_ADDR, |
71 | ringbuf->tail, ringbuf->size); | |
1cf0ba14 CW |
72 | } |
73 | ||
82e104cc | 74 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
75 | { |
76 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
77 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
78 | } | |
09246732 | 79 | |
a4872ba6 | 80 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 81 | { |
93b0a4e0 OM |
82 | struct intel_ringbuffer *ringbuf = ring->buffer; |
83 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 84 | if (intel_ring_stopped(ring)) |
09246732 | 85 | return; |
93b0a4e0 | 86 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
87 | } |
88 | ||
b72f3acb | 89 | static int |
a4872ba6 | 90 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
91 | u32 invalidate_domains, |
92 | u32 flush_domains) | |
93 | { | |
94 | u32 cmd; | |
95 | int ret; | |
96 | ||
97 | cmd = MI_FLUSH; | |
31b14c9f | 98 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
99 | cmd |= MI_NO_WRITE_FLUSH; |
100 | ||
101 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
102 | cmd |= MI_READ_FLUSH; | |
103 | ||
104 | ret = intel_ring_begin(ring, 2); | |
105 | if (ret) | |
106 | return ret; | |
107 | ||
108 | intel_ring_emit(ring, cmd); | |
109 | intel_ring_emit(ring, MI_NOOP); | |
110 | intel_ring_advance(ring); | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | static int | |
a4872ba6 | 116 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
117 | u32 invalidate_domains, |
118 | u32 flush_domains) | |
62fdfeaf | 119 | { |
78501eac | 120 | struct drm_device *dev = ring->dev; |
6f392d54 | 121 | u32 cmd; |
b72f3acb | 122 | int ret; |
6f392d54 | 123 | |
36d527de CW |
124 | /* |
125 | * read/write caches: | |
126 | * | |
127 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
128 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
129 | * also flushed at 2d versus 3d pipeline switches. | |
130 | * | |
131 | * read-only caches: | |
132 | * | |
133 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
134 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
135 | * | |
136 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
137 | * | |
138 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
139 | * invalidated when MI_EXE_FLUSH is set. | |
140 | * | |
141 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
142 | * invalidated with every MI_FLUSH. | |
143 | * | |
144 | * TLBs: | |
145 | * | |
146 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
147 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
148 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
149 | * are flushed at any MI_FLUSH. | |
150 | */ | |
151 | ||
152 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 153 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 154 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
155 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
156 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 157 | |
36d527de CW |
158 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
159 | (IS_G4X(dev) || IS_GEN5(dev))) | |
160 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 161 | |
36d527de CW |
162 | ret = intel_ring_begin(ring, 2); |
163 | if (ret) | |
164 | return ret; | |
b72f3acb | 165 | |
36d527de CW |
166 | intel_ring_emit(ring, cmd); |
167 | intel_ring_emit(ring, MI_NOOP); | |
168 | intel_ring_advance(ring); | |
b72f3acb CW |
169 | |
170 | return 0; | |
8187a2b7 ZN |
171 | } |
172 | ||
8d315287 JB |
173 | /** |
174 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
175 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
176 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
177 | * | |
178 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
179 | * produced by non-pipelined state commands), software needs to first | |
180 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
181 | * 0. | |
182 | * | |
183 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
184 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
185 | * | |
186 | * And the workaround for these two requires this workaround first: | |
187 | * | |
188 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
189 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
190 | * flushes. | |
191 | * | |
192 | * And this last workaround is tricky because of the requirements on | |
193 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
194 | * volume 2 part 1: | |
195 | * | |
196 | * "1 of the following must also be set: | |
197 | * - Render Target Cache Flush Enable ([12] of DW1) | |
198 | * - Depth Cache Flush Enable ([0] of DW1) | |
199 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
200 | * - Depth Stall ([13] of DW1) | |
201 | * - Post-Sync Operation ([13] of DW1) | |
202 | * - Notify Enable ([8] of DW1)" | |
203 | * | |
204 | * The cache flushes require the workaround flush that triggered this | |
205 | * one, so we can't use it. Depth stall would trigger the same. | |
206 | * Post-sync nonzero is what triggered this second workaround, so we | |
207 | * can't use that one either. Notify enable is IRQs, which aren't | |
208 | * really our business. That leaves only stall at scoreboard. | |
209 | */ | |
210 | static int | |
a4872ba6 | 211 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 212 | { |
18393f63 | 213 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
214 | int ret; |
215 | ||
216 | ||
217 | ret = intel_ring_begin(ring, 6); | |
218 | if (ret) | |
219 | return ret; | |
220 | ||
221 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
222 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
223 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
224 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
225 | intel_ring_emit(ring, 0); /* low dword */ | |
226 | intel_ring_emit(ring, 0); /* high dword */ | |
227 | intel_ring_emit(ring, MI_NOOP); | |
228 | intel_ring_advance(ring); | |
229 | ||
230 | ret = intel_ring_begin(ring, 6); | |
231 | if (ret) | |
232 | return ret; | |
233 | ||
234 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
235 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
236 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
237 | intel_ring_emit(ring, 0); | |
238 | intel_ring_emit(ring, 0); | |
239 | intel_ring_emit(ring, MI_NOOP); | |
240 | intel_ring_advance(ring); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int | |
a4872ba6 | 246 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
247 | u32 invalidate_domains, u32 flush_domains) |
248 | { | |
249 | u32 flags = 0; | |
18393f63 | 250 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
251 | int ret; |
252 | ||
b3111509 PZ |
253 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
254 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
255 | if (ret) | |
256 | return ret; | |
257 | ||
8d315287 JB |
258 | /* Just flush everything. Experiments have shown that reducing the |
259 | * number of bits based on the write domains has little performance | |
260 | * impact. | |
261 | */ | |
7d54a904 CW |
262 | if (flush_domains) { |
263 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
264 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
265 | /* | |
266 | * Ensure that any following seqno writes only happen | |
267 | * when the render cache is indeed flushed. | |
268 | */ | |
97f209bc | 269 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
270 | } |
271 | if (invalidate_domains) { | |
272 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
273 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
274 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
275 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
276 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
277 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
278 | /* | |
279 | * TLB invalidate requires a post-sync write. | |
280 | */ | |
3ac78313 | 281 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 282 | } |
8d315287 | 283 | |
6c6cf5aa | 284 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
285 | if (ret) |
286 | return ret; | |
287 | ||
6c6cf5aa | 288 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
289 | intel_ring_emit(ring, flags); |
290 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 291 | intel_ring_emit(ring, 0); |
8d315287 JB |
292 | intel_ring_advance(ring); |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
f3987631 | 297 | static int |
a4872ba6 | 298 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
299 | { |
300 | int ret; | |
301 | ||
302 | ret = intel_ring_begin(ring, 4); | |
303 | if (ret) | |
304 | return ret; | |
305 | ||
306 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
307 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
308 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
309 | intel_ring_emit(ring, 0); | |
310 | intel_ring_emit(ring, 0); | |
311 | intel_ring_advance(ring); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
a4872ba6 | 316 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
317 | { |
318 | int ret; | |
319 | ||
320 | if (!ring->fbc_dirty) | |
321 | return 0; | |
322 | ||
37c1d94f | 323 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
324 | if (ret) |
325 | return ret; | |
fd3da6c9 RV |
326 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
327 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
328 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
329 | intel_ring_emit(ring, value); | |
37c1d94f VS |
330 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
331 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
332 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
333 | intel_ring_advance(ring); |
334 | ||
335 | ring->fbc_dirty = false; | |
336 | return 0; | |
337 | } | |
338 | ||
4772eaeb | 339 | static int |
a4872ba6 | 340 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
341 | u32 invalidate_domains, u32 flush_domains) |
342 | { | |
343 | u32 flags = 0; | |
18393f63 | 344 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
345 | int ret; |
346 | ||
f3987631 PZ |
347 | /* |
348 | * Ensure that any following seqno writes only happen when the render | |
349 | * cache is indeed flushed. | |
350 | * | |
351 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
352 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
353 | * don't try to be clever and just set it unconditionally. | |
354 | */ | |
355 | flags |= PIPE_CONTROL_CS_STALL; | |
356 | ||
4772eaeb PZ |
357 | /* Just flush everything. Experiments have shown that reducing the |
358 | * number of bits based on the write domains has little performance | |
359 | * impact. | |
360 | */ | |
361 | if (flush_domains) { | |
362 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
363 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
364 | } |
365 | if (invalidate_domains) { | |
366 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
367 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
368 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
369 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
370 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
371 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
372 | /* | |
373 | * TLB invalidate requires a post-sync write. | |
374 | */ | |
375 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 376 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
377 | |
378 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
379 | * set before a pipe_control command that has the state cache | |
380 | * invalidate bit set. */ | |
381 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
382 | } |
383 | ||
384 | ret = intel_ring_begin(ring, 4); | |
385 | if (ret) | |
386 | return ret; | |
387 | ||
388 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
389 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 390 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
391 | intel_ring_emit(ring, 0); |
392 | intel_ring_advance(ring); | |
393 | ||
9688ecad | 394 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
395 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
396 | ||
4772eaeb PZ |
397 | return 0; |
398 | } | |
399 | ||
884ceace KG |
400 | static int |
401 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
402 | u32 flags, u32 scratch_addr) | |
403 | { | |
404 | int ret; | |
405 | ||
406 | ret = intel_ring_begin(ring, 6); | |
407 | if (ret) | |
408 | return ret; | |
409 | ||
410 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
411 | intel_ring_emit(ring, flags); | |
412 | intel_ring_emit(ring, scratch_addr); | |
413 | intel_ring_emit(ring, 0); | |
414 | intel_ring_emit(ring, 0); | |
415 | intel_ring_emit(ring, 0); | |
416 | intel_ring_advance(ring); | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
a5f3d68e | 421 | static int |
a4872ba6 | 422 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
423 | u32 invalidate_domains, u32 flush_domains) |
424 | { | |
425 | u32 flags = 0; | |
18393f63 | 426 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 427 | int ret; |
a5f3d68e BW |
428 | |
429 | flags |= PIPE_CONTROL_CS_STALL; | |
430 | ||
431 | if (flush_domains) { | |
432 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
433 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
434 | } | |
435 | if (invalidate_domains) { | |
436 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
437 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
438 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
439 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
440 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
441 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
442 | flags |= PIPE_CONTROL_QW_WRITE; | |
443 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
444 | |
445 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
446 | ret = gen8_emit_pipe_control(ring, | |
447 | PIPE_CONTROL_CS_STALL | | |
448 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
449 | 0); | |
450 | if (ret) | |
451 | return ret; | |
a5f3d68e BW |
452 | } |
453 | ||
884ceace | 454 | return gen8_emit_pipe_control(ring, flags, scratch_addr); |
a5f3d68e BW |
455 | } |
456 | ||
a4872ba6 | 457 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 458 | u32 value) |
d46eefa2 | 459 | { |
4640c4ff | 460 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 461 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
462 | } |
463 | ||
a4872ba6 | 464 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 465 | { |
4640c4ff | 466 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 467 | u64 acthd; |
8187a2b7 | 468 | |
50877445 CW |
469 | if (INTEL_INFO(ring->dev)->gen >= 8) |
470 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
471 | RING_ACTHD_UDW(ring->mmio_base)); | |
472 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
473 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
474 | else | |
475 | acthd = I915_READ(ACTHD); | |
476 | ||
477 | return acthd; | |
8187a2b7 ZN |
478 | } |
479 | ||
a4872ba6 | 480 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
481 | { |
482 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
483 | u32 addr; | |
484 | ||
485 | addr = dev_priv->status_page_dmah->busaddr; | |
486 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
487 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
488 | I915_WRITE(HWS_PGA, addr); | |
489 | } | |
490 | ||
a4872ba6 | 491 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 492 | { |
9991ae78 | 493 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 494 | |
9991ae78 CW |
495 | if (!IS_GEN2(ring->dev)) { |
496 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
497 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
498 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
499 | /* Sometimes we observe that the idle flag is not |
500 | * set even though the ring is empty. So double | |
501 | * check before giving up. | |
502 | */ | |
503 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
504 | return false; | |
9991ae78 CW |
505 | } |
506 | } | |
b7884eb4 | 507 | |
7f2ab699 | 508 | I915_WRITE_CTL(ring, 0); |
570ef608 | 509 | I915_WRITE_HEAD(ring, 0); |
78501eac | 510 | ring->write_tail(ring, 0); |
8187a2b7 | 511 | |
9991ae78 CW |
512 | if (!IS_GEN2(ring->dev)) { |
513 | (void)I915_READ_CTL(ring); | |
514 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
515 | } | |
a51435a3 | 516 | |
9991ae78 CW |
517 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
518 | } | |
8187a2b7 | 519 | |
a4872ba6 | 520 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
521 | { |
522 | struct drm_device *dev = ring->dev; | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
524 | struct intel_ringbuffer *ringbuf = ring->buffer; |
525 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
526 | int ret = 0; |
527 | ||
528 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
529 | ||
530 | if (!stop_ring(ring)) { | |
531 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
532 | DRM_DEBUG_KMS("%s head not reset to zero " |
533 | "ctl %08x head %08x tail %08x start %08x\n", | |
534 | ring->name, | |
535 | I915_READ_CTL(ring), | |
536 | I915_READ_HEAD(ring), | |
537 | I915_READ_TAIL(ring), | |
538 | I915_READ_START(ring)); | |
8187a2b7 | 539 | |
9991ae78 | 540 | if (!stop_ring(ring)) { |
6fd0d56e CW |
541 | DRM_ERROR("failed to set %s head to zero " |
542 | "ctl %08x head %08x tail %08x start %08x\n", | |
543 | ring->name, | |
544 | I915_READ_CTL(ring), | |
545 | I915_READ_HEAD(ring), | |
546 | I915_READ_TAIL(ring), | |
547 | I915_READ_START(ring)); | |
9991ae78 CW |
548 | ret = -EIO; |
549 | goto out; | |
6fd0d56e | 550 | } |
8187a2b7 ZN |
551 | } |
552 | ||
9991ae78 CW |
553 | if (I915_NEED_GFX_HWS(dev)) |
554 | intel_ring_setup_status_page(ring); | |
555 | else | |
556 | ring_setup_phys_status_page(ring); | |
557 | ||
ece4a17d JK |
558 | /* Enforce ordering by reading HEAD register back */ |
559 | I915_READ_HEAD(ring); | |
560 | ||
0d8957c8 DV |
561 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
562 | * registers with the above sequence (the readback of the HEAD registers | |
563 | * also enforces ordering), otherwise the hw might lose the new ring | |
564 | * register values. */ | |
f343c5f6 | 565 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 566 | I915_WRITE_CTL(ring, |
93b0a4e0 | 567 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 568 | | RING_VALID); |
8187a2b7 | 569 | |
8187a2b7 | 570 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 571 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 572 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 573 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 574 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
575 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
576 | ring->name, | |
577 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
578 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
579 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
580 | ret = -EIO; |
581 | goto out; | |
8187a2b7 ZN |
582 | } |
583 | ||
78501eac CW |
584 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
585 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 586 | else { |
93b0a4e0 OM |
587 | ringbuf->head = I915_READ_HEAD(ring); |
588 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
82e104cc | 589 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 590 | ringbuf->last_retired_head = -1; |
8187a2b7 | 591 | } |
1ec14ad3 | 592 | |
50f018df CW |
593 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
594 | ||
b7884eb4 | 595 | out: |
c8d9a590 | 596 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
597 | |
598 | return ret; | |
8187a2b7 ZN |
599 | } |
600 | ||
9b1136d5 OM |
601 | void |
602 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
603 | { | |
604 | struct drm_device *dev = ring->dev; | |
605 | ||
606 | if (ring->scratch.obj == NULL) | |
607 | return; | |
608 | ||
609 | if (INTEL_INFO(dev)->gen >= 5) { | |
610 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
611 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
612 | } | |
613 | ||
614 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
615 | ring->scratch.obj = NULL; | |
616 | } | |
617 | ||
618 | int | |
619 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 620 | { |
c6df541c CW |
621 | int ret; |
622 | ||
0d1aacac | 623 | if (ring->scratch.obj) |
c6df541c CW |
624 | return 0; |
625 | ||
0d1aacac CW |
626 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
627 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
628 | DRM_ERROR("Failed to allocate seqno page\n"); |
629 | ret = -ENOMEM; | |
630 | goto err; | |
631 | } | |
e4ffd173 | 632 | |
a9cc726c DV |
633 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
634 | if (ret) | |
635 | goto err_unref; | |
c6df541c | 636 | |
1ec9e26d | 637 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
638 | if (ret) |
639 | goto err_unref; | |
640 | ||
0d1aacac CW |
641 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
642 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
643 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 644 | ret = -ENOMEM; |
c6df541c | 645 | goto err_unpin; |
56b085a0 | 646 | } |
c6df541c | 647 | |
2b1086cc | 648 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 649 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
650 | return 0; |
651 | ||
652 | err_unpin: | |
d7f46fc4 | 653 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 654 | err_unref: |
0d1aacac | 655 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 656 | err: |
c6df541c CW |
657 | return ret; |
658 | } | |
659 | ||
a4872ba6 | 660 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 661 | { |
78501eac | 662 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 663 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 664 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
665 | if (ret) |
666 | return ret; | |
a69ffdbf | 667 | |
61a563a2 AG |
668 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
669 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 670 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
671 | |
672 | /* We need to disable the AsyncFlip performance optimisations in order | |
673 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
674 | * programmed to '1' on all products. | |
8693a824 | 675 | * |
b3f797ac | 676 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 CW |
677 | */ |
678 | if (INTEL_INFO(dev)->gen >= 6) | |
679 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
680 | ||
f05bb0c7 | 681 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 682 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
683 | if (INTEL_INFO(dev)->gen == 6) |
684 | I915_WRITE(GFX_MODE, | |
aa83e30d | 685 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 686 | |
01fa0302 | 687 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
688 | if (IS_GEN7(dev)) |
689 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 690 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 691 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 692 | |
8d315287 | 693 | if (INTEL_INFO(dev)->gen >= 5) { |
9b1136d5 | 694 | ret = intel_init_pipe_control(ring); |
c6df541c CW |
695 | if (ret) |
696 | return ret; | |
697 | } | |
698 | ||
5e13a0c5 | 699 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
700 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
701 | * "If this bit is set, STCunit will have LRA as replacement | |
702 | * policy. [...] This bit must be reset. LRA replacement | |
703 | * policy is not supported." | |
704 | */ | |
705 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 706 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
707 | } |
708 | ||
6b26c86d DV |
709 | if (INTEL_INFO(dev)->gen >= 6) |
710 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 711 | |
040d2baa | 712 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 713 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 714 | |
8187a2b7 ZN |
715 | return ret; |
716 | } | |
717 | ||
a4872ba6 | 718 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 719 | { |
b45305fc | 720 | struct drm_device *dev = ring->dev; |
3e78998a BW |
721 | struct drm_i915_private *dev_priv = dev->dev_private; |
722 | ||
723 | if (dev_priv->semaphore_obj) { | |
724 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
725 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
726 | dev_priv->semaphore_obj = NULL; | |
727 | } | |
b45305fc | 728 | |
9b1136d5 | 729 | intel_fini_pipe_control(ring); |
c6df541c CW |
730 | } |
731 | ||
3e78998a BW |
732 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
733 | unsigned int num_dwords) | |
734 | { | |
735 | #define MBOX_UPDATE_DWORDS 8 | |
736 | struct drm_device *dev = signaller->dev; | |
737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
738 | struct intel_engine_cs *waiter; | |
739 | int i, ret, num_rings; | |
740 | ||
741 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
742 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
743 | #undef MBOX_UPDATE_DWORDS | |
744 | ||
745 | ret = intel_ring_begin(signaller, num_dwords); | |
746 | if (ret) | |
747 | return ret; | |
748 | ||
749 | for_each_ring(waiter, dev_priv, i) { | |
750 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
751 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
752 | continue; | |
753 | ||
754 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
755 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
756 | PIPE_CONTROL_QW_WRITE | | |
757 | PIPE_CONTROL_FLUSH_ENABLE); | |
758 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
759 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
760 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
761 | intel_ring_emit(signaller, 0); | |
762 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
763 | MI_SEMAPHORE_TARGET(waiter->id)); | |
764 | intel_ring_emit(signaller, 0); | |
765 | } | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
771 | unsigned int num_dwords) | |
772 | { | |
773 | #define MBOX_UPDATE_DWORDS 6 | |
774 | struct drm_device *dev = signaller->dev; | |
775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
776 | struct intel_engine_cs *waiter; | |
777 | int i, ret, num_rings; | |
778 | ||
779 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
780 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
781 | #undef MBOX_UPDATE_DWORDS | |
782 | ||
783 | ret = intel_ring_begin(signaller, num_dwords); | |
784 | if (ret) | |
785 | return ret; | |
786 | ||
787 | for_each_ring(waiter, dev_priv, i) { | |
788 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
789 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
790 | continue; | |
791 | ||
792 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | | |
793 | MI_FLUSH_DW_OP_STOREDW); | |
794 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
795 | MI_FLUSH_DW_USE_GTT); | |
796 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
797 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
798 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
799 | MI_SEMAPHORE_TARGET(waiter->id)); | |
800 | intel_ring_emit(signaller, 0); | |
801 | } | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
a4872ba6 | 806 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 807 | unsigned int num_dwords) |
1ec14ad3 | 808 | { |
024a43e1 BW |
809 | struct drm_device *dev = signaller->dev; |
810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 811 | struct intel_engine_cs *useless; |
a1444b79 | 812 | int i, ret, num_rings; |
78325f2d | 813 | |
a1444b79 BW |
814 | #define MBOX_UPDATE_DWORDS 3 |
815 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
816 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
817 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
818 | |
819 | ret = intel_ring_begin(signaller, num_dwords); | |
820 | if (ret) | |
821 | return ret; | |
024a43e1 | 822 | |
78325f2d BW |
823 | for_each_ring(useless, dev_priv, i) { |
824 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
825 | if (mbox_reg != GEN6_NOSYNC) { | |
826 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); | |
827 | intel_ring_emit(signaller, mbox_reg); | |
828 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
78325f2d BW |
829 | } |
830 | } | |
024a43e1 | 831 | |
a1444b79 BW |
832 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
833 | if (num_rings % 2 == 0) | |
834 | intel_ring_emit(signaller, MI_NOOP); | |
835 | ||
024a43e1 | 836 | return 0; |
1ec14ad3 CW |
837 | } |
838 | ||
c8c99b0f BW |
839 | /** |
840 | * gen6_add_request - Update the semaphore mailbox registers | |
841 | * | |
842 | * @ring - ring that is adding a request | |
843 | * @seqno - return seqno stuck into the ring | |
844 | * | |
845 | * Update the mailbox registers in the *other* rings with the current seqno. | |
846 | * This acts like a signal in the canonical semaphore. | |
847 | */ | |
1ec14ad3 | 848 | static int |
a4872ba6 | 849 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 850 | { |
024a43e1 | 851 | int ret; |
52ed2325 | 852 | |
707d9cf9 BW |
853 | if (ring->semaphore.signal) |
854 | ret = ring->semaphore.signal(ring, 4); | |
855 | else | |
856 | ret = intel_ring_begin(ring, 4); | |
857 | ||
1ec14ad3 CW |
858 | if (ret) |
859 | return ret; | |
860 | ||
1ec14ad3 CW |
861 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
862 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 863 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 864 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 865 | __intel_ring_advance(ring); |
1ec14ad3 | 866 | |
1ec14ad3 CW |
867 | return 0; |
868 | } | |
869 | ||
f72b3435 MK |
870 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
871 | u32 seqno) | |
872 | { | |
873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
874 | return dev_priv->last_seqno < seqno; | |
875 | } | |
876 | ||
c8c99b0f BW |
877 | /** |
878 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
879 | * | |
880 | * @waiter - ring that is waiting | |
881 | * @signaller - ring which has, or will signal | |
882 | * @seqno - seqno which the waiter will block on | |
883 | */ | |
5ee426ca BW |
884 | |
885 | static int | |
886 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
887 | struct intel_engine_cs *signaller, | |
888 | u32 seqno) | |
889 | { | |
890 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
891 | int ret; | |
892 | ||
893 | ret = intel_ring_begin(waiter, 4); | |
894 | if (ret) | |
895 | return ret; | |
896 | ||
897 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
898 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 899 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
900 | MI_SEMAPHORE_SAD_GTE_SDD); |
901 | intel_ring_emit(waiter, seqno); | |
902 | intel_ring_emit(waiter, | |
903 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
904 | intel_ring_emit(waiter, | |
905 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
906 | intel_ring_advance(waiter); | |
907 | return 0; | |
908 | } | |
909 | ||
c8c99b0f | 910 | static int |
a4872ba6 OM |
911 | gen6_ring_sync(struct intel_engine_cs *waiter, |
912 | struct intel_engine_cs *signaller, | |
686cb5f9 | 913 | u32 seqno) |
1ec14ad3 | 914 | { |
c8c99b0f BW |
915 | u32 dw1 = MI_SEMAPHORE_MBOX | |
916 | MI_SEMAPHORE_COMPARE | | |
917 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
918 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
919 | int ret; | |
1ec14ad3 | 920 | |
1500f7ea BW |
921 | /* Throughout all of the GEM code, seqno passed implies our current |
922 | * seqno is >= the last seqno executed. However for hardware the | |
923 | * comparison is strictly greater than. | |
924 | */ | |
925 | seqno -= 1; | |
926 | ||
ebc348b2 | 927 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 928 | |
c8c99b0f | 929 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
930 | if (ret) |
931 | return ret; | |
932 | ||
f72b3435 MK |
933 | /* If seqno wrap happened, omit the wait with no-ops */ |
934 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 935 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
936 | intel_ring_emit(waiter, seqno); |
937 | intel_ring_emit(waiter, 0); | |
938 | intel_ring_emit(waiter, MI_NOOP); | |
939 | } else { | |
940 | intel_ring_emit(waiter, MI_NOOP); | |
941 | intel_ring_emit(waiter, MI_NOOP); | |
942 | intel_ring_emit(waiter, MI_NOOP); | |
943 | intel_ring_emit(waiter, MI_NOOP); | |
944 | } | |
c8c99b0f | 945 | intel_ring_advance(waiter); |
1ec14ad3 CW |
946 | |
947 | return 0; | |
948 | } | |
949 | ||
c6df541c CW |
950 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
951 | do { \ | |
fcbc34e4 KG |
952 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
953 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
954 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
955 | intel_ring_emit(ring__, 0); \ | |
956 | intel_ring_emit(ring__, 0); \ | |
957 | } while (0) | |
958 | ||
959 | static int | |
a4872ba6 | 960 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 961 | { |
18393f63 | 962 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
963 | int ret; |
964 | ||
965 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
966 | * incoherent with writes to memory, i.e. completely fubar, | |
967 | * so we need to use PIPE_NOTIFY instead. | |
968 | * | |
969 | * However, we also need to workaround the qword write | |
970 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
971 | * memory before requesting an interrupt. | |
972 | */ | |
973 | ret = intel_ring_begin(ring, 32); | |
974 | if (ret) | |
975 | return ret; | |
976 | ||
fcbc34e4 | 977 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
978 | PIPE_CONTROL_WRITE_FLUSH | |
979 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 980 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 981 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
982 | intel_ring_emit(ring, 0); |
983 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 984 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 985 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 986 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 987 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 988 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 989 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 990 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 991 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 992 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 993 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 994 | |
fcbc34e4 | 995 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
996 | PIPE_CONTROL_WRITE_FLUSH | |
997 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 998 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 999 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 1000 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 1001 | intel_ring_emit(ring, 0); |
09246732 | 1002 | __intel_ring_advance(ring); |
c6df541c | 1003 | |
c6df541c CW |
1004 | return 0; |
1005 | } | |
1006 | ||
4cd53c0c | 1007 | static u32 |
a4872ba6 | 1008 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1009 | { |
4cd53c0c DV |
1010 | /* Workaround to force correct ordering between irq and seqno writes on |
1011 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1012 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1013 | if (!lazy_coherency) { |
1014 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1015 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1016 | } | |
1017 | ||
4cd53c0c DV |
1018 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1019 | } | |
1020 | ||
8187a2b7 | 1021 | static u32 |
a4872ba6 | 1022 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1023 | { |
1ec14ad3 CW |
1024 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1025 | } | |
1026 | ||
b70ec5bf | 1027 | static void |
a4872ba6 | 1028 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1029 | { |
1030 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1031 | } | |
1032 | ||
c6df541c | 1033 | static u32 |
a4872ba6 | 1034 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1035 | { |
0d1aacac | 1036 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1037 | } |
1038 | ||
b70ec5bf | 1039 | static void |
a4872ba6 | 1040 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1041 | { |
0d1aacac | 1042 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1043 | } |
1044 | ||
e48d8634 | 1045 | static bool |
a4872ba6 | 1046 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1047 | { |
1048 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1049 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1050 | unsigned long flags; |
e48d8634 DV |
1051 | |
1052 | if (!dev->irq_enabled) | |
1053 | return false; | |
1054 | ||
7338aefa | 1055 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1056 | if (ring->irq_refcount++ == 0) |
480c8033 | 1057 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1058 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1059 | |
1060 | return true; | |
1061 | } | |
1062 | ||
1063 | static void | |
a4872ba6 | 1064 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1065 | { |
1066 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1067 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1068 | unsigned long flags; |
e48d8634 | 1069 | |
7338aefa | 1070 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1071 | if (--ring->irq_refcount == 0) |
480c8033 | 1072 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1073 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1074 | } |
1075 | ||
b13c2b96 | 1076 | static bool |
a4872ba6 | 1077 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1078 | { |
78501eac | 1079 | struct drm_device *dev = ring->dev; |
4640c4ff | 1080 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1081 | unsigned long flags; |
62fdfeaf | 1082 | |
b13c2b96 CW |
1083 | if (!dev->irq_enabled) |
1084 | return false; | |
1085 | ||
7338aefa | 1086 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1087 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1088 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1089 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1090 | POSTING_READ(IMR); | |
1091 | } | |
7338aefa | 1092 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1093 | |
1094 | return true; | |
62fdfeaf EA |
1095 | } |
1096 | ||
8187a2b7 | 1097 | static void |
a4872ba6 | 1098 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1099 | { |
78501eac | 1100 | struct drm_device *dev = ring->dev; |
4640c4ff | 1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1102 | unsigned long flags; |
62fdfeaf | 1103 | |
7338aefa | 1104 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1105 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1106 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1107 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1108 | POSTING_READ(IMR); | |
1109 | } | |
7338aefa | 1110 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1111 | } |
1112 | ||
c2798b19 | 1113 | static bool |
a4872ba6 | 1114 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1115 | { |
1116 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1117 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1118 | unsigned long flags; |
c2798b19 CW |
1119 | |
1120 | if (!dev->irq_enabled) | |
1121 | return false; | |
1122 | ||
7338aefa | 1123 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1124 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1125 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1126 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1127 | POSTING_READ16(IMR); | |
1128 | } | |
7338aefa | 1129 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1130 | |
1131 | return true; | |
1132 | } | |
1133 | ||
1134 | static void | |
a4872ba6 | 1135 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1136 | { |
1137 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1138 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1139 | unsigned long flags; |
c2798b19 | 1140 | |
7338aefa | 1141 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1142 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1143 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1144 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1145 | POSTING_READ16(IMR); | |
1146 | } | |
7338aefa | 1147 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1148 | } |
1149 | ||
a4872ba6 | 1150 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1151 | { |
4593010b | 1152 | struct drm_device *dev = ring->dev; |
4640c4ff | 1153 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1154 | u32 mmio = 0; |
1155 | ||
1156 | /* The ring status page addresses are no longer next to the rest of | |
1157 | * the ring registers as of gen7. | |
1158 | */ | |
1159 | if (IS_GEN7(dev)) { | |
1160 | switch (ring->id) { | |
96154f2f | 1161 | case RCS: |
4593010b EA |
1162 | mmio = RENDER_HWS_PGA_GEN7; |
1163 | break; | |
96154f2f | 1164 | case BCS: |
4593010b EA |
1165 | mmio = BLT_HWS_PGA_GEN7; |
1166 | break; | |
77fe2ff3 ZY |
1167 | /* |
1168 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1169 | * gcc switch check warning | |
1170 | */ | |
1171 | case VCS2: | |
96154f2f | 1172 | case VCS: |
4593010b EA |
1173 | mmio = BSD_HWS_PGA_GEN7; |
1174 | break; | |
4a3dd19d | 1175 | case VECS: |
9a8a2213 BW |
1176 | mmio = VEBOX_HWS_PGA_GEN7; |
1177 | break; | |
4593010b EA |
1178 | } |
1179 | } else if (IS_GEN6(ring->dev)) { | |
1180 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1181 | } else { | |
eb0d4b75 | 1182 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1183 | mmio = RING_HWS_PGA(ring->mmio_base); |
1184 | } | |
1185 | ||
78501eac CW |
1186 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1187 | POSTING_READ(mmio); | |
884020bf | 1188 | |
dc616b89 DL |
1189 | /* |
1190 | * Flush the TLB for this page | |
1191 | * | |
1192 | * FIXME: These two bits have disappeared on gen8, so a question | |
1193 | * arises: do we still need this and if so how should we go about | |
1194 | * invalidating the TLB? | |
1195 | */ | |
1196 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1197 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1198 | |
1199 | /* ring should be idle before issuing a sync flush*/ | |
1200 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1201 | ||
884020bf CW |
1202 | I915_WRITE(reg, |
1203 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1204 | INSTPM_SYNC_FLUSH)); | |
1205 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1206 | 1000)) | |
1207 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1208 | ring->name); | |
1209 | } | |
8187a2b7 ZN |
1210 | } |
1211 | ||
b72f3acb | 1212 | static int |
a4872ba6 | 1213 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1214 | u32 invalidate_domains, |
1215 | u32 flush_domains) | |
d1b851fc | 1216 | { |
b72f3acb CW |
1217 | int ret; |
1218 | ||
b72f3acb CW |
1219 | ret = intel_ring_begin(ring, 2); |
1220 | if (ret) | |
1221 | return ret; | |
1222 | ||
1223 | intel_ring_emit(ring, MI_FLUSH); | |
1224 | intel_ring_emit(ring, MI_NOOP); | |
1225 | intel_ring_advance(ring); | |
1226 | return 0; | |
d1b851fc ZN |
1227 | } |
1228 | ||
3cce469c | 1229 | static int |
a4872ba6 | 1230 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1231 | { |
3cce469c CW |
1232 | int ret; |
1233 | ||
1234 | ret = intel_ring_begin(ring, 4); | |
1235 | if (ret) | |
1236 | return ret; | |
6f392d54 | 1237 | |
3cce469c CW |
1238 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1239 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1240 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1241 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1242 | __intel_ring_advance(ring); |
d1b851fc | 1243 | |
3cce469c | 1244 | return 0; |
d1b851fc ZN |
1245 | } |
1246 | ||
0f46832f | 1247 | static bool |
a4872ba6 | 1248 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1249 | { |
1250 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1251 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1252 | unsigned long flags; |
0f46832f CW |
1253 | |
1254 | if (!dev->irq_enabled) | |
1255 | return false; | |
1256 | ||
7338aefa | 1257 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1258 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1259 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1260 | I915_WRITE_IMR(ring, |
1261 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1262 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1263 | else |
1264 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1265 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1266 | } |
7338aefa | 1267 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1268 | |
1269 | return true; | |
1270 | } | |
1271 | ||
1272 | static void | |
a4872ba6 | 1273 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1274 | { |
1275 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1276 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1277 | unsigned long flags; |
0f46832f | 1278 | |
7338aefa | 1279 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1280 | if (--ring->irq_refcount == 0) { |
040d2baa | 1281 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1282 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1283 | else |
1284 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1285 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1286 | } |
7338aefa | 1287 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1288 | } |
1289 | ||
a19d2933 | 1290 | static bool |
a4872ba6 | 1291 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1292 | { |
1293 | struct drm_device *dev = ring->dev; | |
1294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1295 | unsigned long flags; | |
1296 | ||
1297 | if (!dev->irq_enabled) | |
1298 | return false; | |
1299 | ||
59cdb63d | 1300 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1301 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1302 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1303 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1304 | } |
59cdb63d | 1305 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1306 | |
1307 | return true; | |
1308 | } | |
1309 | ||
1310 | static void | |
a4872ba6 | 1311 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1312 | { |
1313 | struct drm_device *dev = ring->dev; | |
1314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1315 | unsigned long flags; | |
1316 | ||
1317 | if (!dev->irq_enabled) | |
1318 | return; | |
1319 | ||
59cdb63d | 1320 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1321 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1322 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1323 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1324 | } |
59cdb63d | 1325 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1326 | } |
1327 | ||
abd58f01 | 1328 | static bool |
a4872ba6 | 1329 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1330 | { |
1331 | struct drm_device *dev = ring->dev; | |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1333 | unsigned long flags; | |
1334 | ||
1335 | if (!dev->irq_enabled) | |
1336 | return false; | |
1337 | ||
1338 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1339 | if (ring->irq_refcount++ == 0) { | |
1340 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1341 | I915_WRITE_IMR(ring, | |
1342 | ~(ring->irq_enable_mask | | |
1343 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1344 | } else { | |
1345 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1346 | } | |
1347 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1348 | } | |
1349 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1350 | ||
1351 | return true; | |
1352 | } | |
1353 | ||
1354 | static void | |
a4872ba6 | 1355 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1356 | { |
1357 | struct drm_device *dev = ring->dev; | |
1358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1359 | unsigned long flags; | |
1360 | ||
1361 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1362 | if (--ring->irq_refcount == 0) { | |
1363 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1364 | I915_WRITE_IMR(ring, | |
1365 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1366 | } else { | |
1367 | I915_WRITE_IMR(ring, ~0); | |
1368 | } | |
1369 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1370 | } | |
1371 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1372 | } | |
1373 | ||
d1b851fc | 1374 | static int |
a4872ba6 | 1375 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1376 | u64 offset, u32 length, |
d7d4eedd | 1377 | unsigned flags) |
d1b851fc | 1378 | { |
e1f99ce6 | 1379 | int ret; |
78501eac | 1380 | |
e1f99ce6 CW |
1381 | ret = intel_ring_begin(ring, 2); |
1382 | if (ret) | |
1383 | return ret; | |
1384 | ||
78501eac | 1385 | intel_ring_emit(ring, |
65f56876 CW |
1386 | MI_BATCH_BUFFER_START | |
1387 | MI_BATCH_GTT | | |
d7d4eedd | 1388 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1389 | intel_ring_emit(ring, offset); |
78501eac CW |
1390 | intel_ring_advance(ring); |
1391 | ||
d1b851fc ZN |
1392 | return 0; |
1393 | } | |
1394 | ||
b45305fc DV |
1395 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1396 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1397 | static int |
a4872ba6 | 1398 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1399 | u64 offset, u32 len, |
d7d4eedd | 1400 | unsigned flags) |
62fdfeaf | 1401 | { |
c4e7a414 | 1402 | int ret; |
62fdfeaf | 1403 | |
b45305fc DV |
1404 | if (flags & I915_DISPATCH_PINNED) { |
1405 | ret = intel_ring_begin(ring, 4); | |
1406 | if (ret) | |
1407 | return ret; | |
62fdfeaf | 1408 | |
b45305fc DV |
1409 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1410 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1411 | intel_ring_emit(ring, offset + len - 8); | |
1412 | intel_ring_emit(ring, MI_NOOP); | |
1413 | intel_ring_advance(ring); | |
1414 | } else { | |
0d1aacac | 1415 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1416 | |
1417 | if (len > I830_BATCH_LIMIT) | |
1418 | return -ENOSPC; | |
1419 | ||
1420 | ret = intel_ring_begin(ring, 9+3); | |
1421 | if (ret) | |
1422 | return ret; | |
1423 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1424 | * scratch bo area (so that the CS never stumbles over its tlb | |
1425 | * invalidation bug) ... */ | |
1426 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1427 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1428 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1429 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1430 | intel_ring_emit(ring, 0); | |
1431 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1432 | intel_ring_emit(ring, cs_offset); | |
1433 | intel_ring_emit(ring, 0); | |
1434 | intel_ring_emit(ring, 4096); | |
1435 | intel_ring_emit(ring, offset); | |
1436 | intel_ring_emit(ring, MI_FLUSH); | |
1437 | ||
1438 | /* ... and execute it. */ | |
1439 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1440 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1441 | intel_ring_emit(ring, cs_offset + len - 8); | |
1442 | intel_ring_advance(ring); | |
1443 | } | |
e1f99ce6 | 1444 | |
fb3256da DV |
1445 | return 0; |
1446 | } | |
1447 | ||
1448 | static int | |
a4872ba6 | 1449 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1450 | u64 offset, u32 len, |
d7d4eedd | 1451 | unsigned flags) |
fb3256da DV |
1452 | { |
1453 | int ret; | |
1454 | ||
1455 | ret = intel_ring_begin(ring, 2); | |
1456 | if (ret) | |
1457 | return ret; | |
1458 | ||
65f56876 | 1459 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1460 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1461 | intel_ring_advance(ring); |
62fdfeaf | 1462 | |
62fdfeaf EA |
1463 | return 0; |
1464 | } | |
1465 | ||
a4872ba6 | 1466 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1467 | { |
05394f39 | 1468 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1469 | |
8187a2b7 ZN |
1470 | obj = ring->status_page.obj; |
1471 | if (obj == NULL) | |
62fdfeaf | 1472 | return; |
62fdfeaf | 1473 | |
9da3da66 | 1474 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1475 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1476 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1477 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1478 | } |
1479 | ||
a4872ba6 | 1480 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1481 | { |
05394f39 | 1482 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1483 | |
e3efda49 | 1484 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1485 | unsigned flags; |
e3efda49 | 1486 | int ret; |
e4ffd173 | 1487 | |
e3efda49 CW |
1488 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1489 | if (obj == NULL) { | |
1490 | DRM_ERROR("Failed to allocate status page\n"); | |
1491 | return -ENOMEM; | |
1492 | } | |
62fdfeaf | 1493 | |
e3efda49 CW |
1494 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1495 | if (ret) | |
1496 | goto err_unref; | |
1497 | ||
1f767e02 CW |
1498 | flags = 0; |
1499 | if (!HAS_LLC(ring->dev)) | |
1500 | /* On g33, we cannot place HWS above 256MiB, so | |
1501 | * restrict its pinning to the low mappable arena. | |
1502 | * Though this restriction is not documented for | |
1503 | * gen4, gen5, or byt, they also behave similarly | |
1504 | * and hang if the HWS is placed at the top of the | |
1505 | * GTT. To generalise, it appears that all !llc | |
1506 | * platforms have issues with us placing the HWS | |
1507 | * above the mappable region (even though we never | |
1508 | * actualy map it). | |
1509 | */ | |
1510 | flags |= PIN_MAPPABLE; | |
1511 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1512 | if (ret) { |
1513 | err_unref: | |
1514 | drm_gem_object_unreference(&obj->base); | |
1515 | return ret; | |
1516 | } | |
1517 | ||
1518 | ring->status_page.obj = obj; | |
1519 | } | |
62fdfeaf | 1520 | |
f343c5f6 | 1521 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1522 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1523 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1524 | |
8187a2b7 ZN |
1525 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1526 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1527 | |
1528 | return 0; | |
62fdfeaf EA |
1529 | } |
1530 | ||
a4872ba6 | 1531 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1532 | { |
1533 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1534 | |
1535 | if (!dev_priv->status_page_dmah) { | |
1536 | dev_priv->status_page_dmah = | |
1537 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1538 | if (!dev_priv->status_page_dmah) | |
1539 | return -ENOMEM; | |
1540 | } | |
1541 | ||
6b8294a4 CW |
1542 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1543 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
84c2377f | 1548 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 OM |
1549 | { |
1550 | if (!ringbuf->obj) | |
1551 | return; | |
1552 | ||
1553 | iounmap(ringbuf->virtual_start); | |
1554 | i915_gem_object_ggtt_unpin(ringbuf->obj); | |
1555 | drm_gem_object_unreference(&ringbuf->obj->base); | |
1556 | ringbuf->obj = NULL; | |
1557 | } | |
1558 | ||
84c2377f OM |
1559 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1560 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1561 | { |
e3efda49 | 1562 | struct drm_i915_private *dev_priv = to_i915(dev); |
05394f39 | 1563 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
1564 | int ret; |
1565 | ||
2919d291 | 1566 | if (ringbuf->obj) |
e3efda49 | 1567 | return 0; |
62fdfeaf | 1568 | |
ebc052e0 CW |
1569 | obj = NULL; |
1570 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1571 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1572 | if (obj == NULL) |
93b0a4e0 | 1573 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1574 | if (obj == NULL) |
1575 | return -ENOMEM; | |
8187a2b7 | 1576 | |
24f3a8cf AG |
1577 | /* mark ring buffers as read-only from GPU side by default */ |
1578 | obj->gt_ro = 1; | |
1579 | ||
1ec9e26d | 1580 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1581 | if (ret) |
1582 | goto err_unref; | |
62fdfeaf | 1583 | |
3eef8918 CW |
1584 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1585 | if (ret) | |
1586 | goto err_unpin; | |
1587 | ||
93b0a4e0 | 1588 | ringbuf->virtual_start = |
f343c5f6 | 1589 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
93b0a4e0 OM |
1590 | ringbuf->size); |
1591 | if (ringbuf->virtual_start == NULL) { | |
8187a2b7 | 1592 | ret = -EINVAL; |
dd785e35 | 1593 | goto err_unpin; |
62fdfeaf EA |
1594 | } |
1595 | ||
93b0a4e0 | 1596 | ringbuf->obj = obj; |
e3efda49 CW |
1597 | return 0; |
1598 | ||
1599 | err_unpin: | |
1600 | i915_gem_object_ggtt_unpin(obj); | |
1601 | err_unref: | |
1602 | drm_gem_object_unreference(&obj->base); | |
1603 | return ret; | |
1604 | } | |
1605 | ||
1606 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1607 | struct intel_engine_cs *ring) |
e3efda49 | 1608 | { |
8ee14975 | 1609 | struct intel_ringbuffer *ringbuf = ring->buffer; |
e3efda49 CW |
1610 | int ret; |
1611 | ||
8ee14975 OM |
1612 | if (ringbuf == NULL) { |
1613 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1614 | if (!ringbuf) | |
1615 | return -ENOMEM; | |
1616 | ring->buffer = ringbuf; | |
1617 | } | |
1618 | ||
e3efda49 CW |
1619 | ring->dev = dev; |
1620 | INIT_LIST_HEAD(&ring->active_list); | |
1621 | INIT_LIST_HEAD(&ring->request_list); | |
93b0a4e0 | 1622 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1623 | ringbuf->ring = ring; |
ebc348b2 | 1624 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1625 | |
1626 | init_waitqueue_head(&ring->irq_queue); | |
1627 | ||
1628 | if (I915_NEED_GFX_HWS(dev)) { | |
1629 | ret = init_status_page(ring); | |
1630 | if (ret) | |
8ee14975 | 1631 | goto error; |
e3efda49 CW |
1632 | } else { |
1633 | BUG_ON(ring->id != RCS); | |
1634 | ret = init_phys_status_page(ring); | |
1635 | if (ret) | |
8ee14975 | 1636 | goto error; |
e3efda49 CW |
1637 | } |
1638 | ||
2919d291 | 1639 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
e3efda49 CW |
1640 | if (ret) { |
1641 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); | |
8ee14975 | 1642 | goto error; |
e3efda49 | 1643 | } |
62fdfeaf | 1644 | |
55249baa CW |
1645 | /* Workaround an erratum on the i830 which causes a hang if |
1646 | * the TAIL pointer points to within the last 2 cachelines | |
1647 | * of the buffer. | |
1648 | */ | |
93b0a4e0 | 1649 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1650 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1651 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1652 | |
44e895a8 BV |
1653 | ret = i915_cmd_parser_init_ring(ring); |
1654 | if (ret) | |
8ee14975 OM |
1655 | goto error; |
1656 | ||
1657 | ret = ring->init(ring); | |
1658 | if (ret) | |
1659 | goto error; | |
1660 | ||
1661 | return 0; | |
351e3db2 | 1662 | |
8ee14975 OM |
1663 | error: |
1664 | kfree(ringbuf); | |
1665 | ring->buffer = NULL; | |
1666 | return ret; | |
62fdfeaf EA |
1667 | } |
1668 | ||
a4872ba6 | 1669 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1670 | { |
e3efda49 | 1671 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
93b0a4e0 | 1672 | struct intel_ringbuffer *ringbuf = ring->buffer; |
33626e6a | 1673 | |
93b0a4e0 | 1674 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1675 | return; |
1676 | ||
e3efda49 | 1677 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1678 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1679 | |
2919d291 | 1680 | intel_destroy_ringbuffer_obj(ringbuf); |
3d57e5bd BW |
1681 | ring->preallocated_lazy_request = NULL; |
1682 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1683 | |
8d19215b ZN |
1684 | if (ring->cleanup) |
1685 | ring->cleanup(ring); | |
1686 | ||
78501eac | 1687 | cleanup_status_page(ring); |
44e895a8 BV |
1688 | |
1689 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1690 | |
93b0a4e0 | 1691 | kfree(ringbuf); |
8ee14975 | 1692 | ring->buffer = NULL; |
62fdfeaf EA |
1693 | } |
1694 | ||
a4872ba6 | 1695 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1696 | { |
93b0a4e0 | 1697 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1698 | struct drm_i915_gem_request *request; |
1cf0ba14 | 1699 | u32 seqno = 0; |
a71d8d94 CW |
1700 | int ret; |
1701 | ||
93b0a4e0 OM |
1702 | if (ringbuf->last_retired_head != -1) { |
1703 | ringbuf->head = ringbuf->last_retired_head; | |
1704 | ringbuf->last_retired_head = -1; | |
1f70999f | 1705 | |
82e104cc | 1706 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 1707 | if (ringbuf->space >= n) |
a71d8d94 CW |
1708 | return 0; |
1709 | } | |
1710 | ||
1711 | list_for_each_entry(request, &ring->request_list, list) { | |
82e104cc OM |
1712 | if (__intel_ring_space(request->tail, ringbuf->tail, |
1713 | ringbuf->size) >= n) { | |
a71d8d94 CW |
1714 | seqno = request->seqno; |
1715 | break; | |
1716 | } | |
a71d8d94 CW |
1717 | } |
1718 | ||
1719 | if (seqno == 0) | |
1720 | return -ENOSPC; | |
1721 | ||
1f70999f | 1722 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1723 | if (ret) |
1724 | return ret; | |
1725 | ||
1cf0ba14 | 1726 | i915_gem_retire_requests_ring(ring); |
93b0a4e0 OM |
1727 | ringbuf->head = ringbuf->last_retired_head; |
1728 | ringbuf->last_retired_head = -1; | |
a71d8d94 | 1729 | |
82e104cc | 1730 | ringbuf->space = intel_ring_space(ringbuf); |
a71d8d94 CW |
1731 | return 0; |
1732 | } | |
1733 | ||
a4872ba6 | 1734 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1735 | { |
78501eac | 1736 | struct drm_device *dev = ring->dev; |
cae5852d | 1737 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1738 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1739 | unsigned long end; |
a71d8d94 | 1740 | int ret; |
c7dca47b | 1741 | |
a71d8d94 CW |
1742 | ret = intel_ring_wait_request(ring, n); |
1743 | if (ret != -ENOSPC) | |
1744 | return ret; | |
1745 | ||
09246732 CW |
1746 | /* force the tail write in case we have been skipping them */ |
1747 | __intel_ring_advance(ring); | |
1748 | ||
63ed2cb2 DV |
1749 | /* With GEM the hangcheck timer should kick us out of the loop, |
1750 | * leaving it early runs the risk of corrupting GEM state (due | |
1751 | * to running on almost untested codepaths). But on resume | |
1752 | * timers don't work yet, so prevent a complete hang in that | |
1753 | * case by choosing an insanely large timeout. */ | |
1754 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1755 | |
dcfe0506 | 1756 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1757 | do { |
93b0a4e0 | 1758 | ringbuf->head = I915_READ_HEAD(ring); |
82e104cc | 1759 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 1760 | if (ringbuf->space >= n) { |
dcfe0506 CW |
1761 | ret = 0; |
1762 | break; | |
62fdfeaf EA |
1763 | } |
1764 | ||
fb19e2ac DV |
1765 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1766 | dev->primary->master) { | |
62fdfeaf EA |
1767 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1768 | if (master_priv->sarea_priv) | |
1769 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1770 | } | |
d1b851fc | 1771 | |
e60a0b10 | 1772 | msleep(1); |
d6b2c790 | 1773 | |
dcfe0506 CW |
1774 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1775 | ret = -ERESTARTSYS; | |
1776 | break; | |
1777 | } | |
1778 | ||
33196ded DV |
1779 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1780 | dev_priv->mm.interruptible); | |
d6b2c790 | 1781 | if (ret) |
dcfe0506 CW |
1782 | break; |
1783 | ||
1784 | if (time_after(jiffies, end)) { | |
1785 | ret = -EBUSY; | |
1786 | break; | |
1787 | } | |
1788 | } while (1); | |
db53a302 | 1789 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1790 | return ret; |
8187a2b7 | 1791 | } |
62fdfeaf | 1792 | |
a4872ba6 | 1793 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1794 | { |
1795 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1796 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1797 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1798 | |
93b0a4e0 | 1799 | if (ringbuf->space < rem) { |
3e960501 CW |
1800 | int ret = ring_wait_for_space(ring, rem); |
1801 | if (ret) | |
1802 | return ret; | |
1803 | } | |
1804 | ||
93b0a4e0 | 1805 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1806 | rem /= 4; |
1807 | while (rem--) | |
1808 | iowrite32(MI_NOOP, virt++); | |
1809 | ||
93b0a4e0 | 1810 | ringbuf->tail = 0; |
82e104cc | 1811 | ringbuf->space = intel_ring_space(ringbuf); |
3e960501 CW |
1812 | |
1813 | return 0; | |
1814 | } | |
1815 | ||
a4872ba6 | 1816 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 CW |
1817 | { |
1818 | u32 seqno; | |
1819 | int ret; | |
1820 | ||
1821 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1822 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1823 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1824 | if (ret) |
1825 | return ret; | |
1826 | } | |
1827 | ||
1828 | /* Wait upon the last request to be completed */ | |
1829 | if (list_empty(&ring->request_list)) | |
1830 | return 0; | |
1831 | ||
1832 | seqno = list_entry(ring->request_list.prev, | |
1833 | struct drm_i915_gem_request, | |
1834 | list)->seqno; | |
1835 | ||
1836 | return i915_wait_seqno(ring, seqno); | |
1837 | } | |
1838 | ||
9d773091 | 1839 | static int |
a4872ba6 | 1840 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
9d773091 | 1841 | { |
1823521d | 1842 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1843 | return 0; |
1844 | ||
3c0e234c CW |
1845 | if (ring->preallocated_lazy_request == NULL) { |
1846 | struct drm_i915_gem_request *request; | |
1847 | ||
1848 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1849 | if (request == NULL) | |
1850 | return -ENOMEM; | |
1851 | ||
1852 | ring->preallocated_lazy_request = request; | |
1853 | } | |
1854 | ||
1823521d | 1855 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1856 | } |
1857 | ||
a4872ba6 | 1858 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 1859 | int bytes) |
cbcc80df | 1860 | { |
93b0a4e0 | 1861 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
1862 | int ret; |
1863 | ||
93b0a4e0 | 1864 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
1865 | ret = intel_wrap_ring_buffer(ring); |
1866 | if (unlikely(ret)) | |
1867 | return ret; | |
1868 | } | |
1869 | ||
93b0a4e0 | 1870 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
1871 | ret = ring_wait_for_space(ring, bytes); |
1872 | if (unlikely(ret)) | |
1873 | return ret; | |
1874 | } | |
1875 | ||
cbcc80df MK |
1876 | return 0; |
1877 | } | |
1878 | ||
a4872ba6 | 1879 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 1880 | int num_dwords) |
8187a2b7 | 1881 | { |
4640c4ff | 1882 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1883 | int ret; |
78501eac | 1884 | |
33196ded DV |
1885 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1886 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1887 | if (ret) |
1888 | return ret; | |
21dd3734 | 1889 | |
304d695c CW |
1890 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1891 | if (ret) | |
1892 | return ret; | |
1893 | ||
9d773091 CW |
1894 | /* Preallocate the olr before touching the ring */ |
1895 | ret = intel_ring_alloc_seqno(ring); | |
1896 | if (ret) | |
1897 | return ret; | |
1898 | ||
ee1b1e5e | 1899 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 1900 | return 0; |
8187a2b7 | 1901 | } |
78501eac | 1902 | |
753b1ad4 | 1903 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 1904 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 1905 | { |
ee1b1e5e | 1906 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
1907 | int ret; |
1908 | ||
1909 | if (num_dwords == 0) | |
1910 | return 0; | |
1911 | ||
18393f63 | 1912 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
1913 | ret = intel_ring_begin(ring, num_dwords); |
1914 | if (ret) | |
1915 | return ret; | |
1916 | ||
1917 | while (num_dwords--) | |
1918 | intel_ring_emit(ring, MI_NOOP); | |
1919 | ||
1920 | intel_ring_advance(ring); | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
a4872ba6 | 1925 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 1926 | { |
3b2cc8ab OM |
1927 | struct drm_device *dev = ring->dev; |
1928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 1929 | |
1823521d | 1930 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1931 | |
3b2cc8ab | 1932 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
1933 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
1934 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 1935 | if (HAS_VEBOX(dev)) |
5020150b | 1936 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 1937 | } |
d97ed339 | 1938 | |
f7e98ad4 | 1939 | ring->set_seqno(ring, seqno); |
92cab734 | 1940 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1941 | } |
62fdfeaf | 1942 | |
a4872ba6 | 1943 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 1944 | u32 value) |
881f47b6 | 1945 | { |
4640c4ff | 1946 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1947 | |
1948 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1949 | |
1950 | /* Disable notification that the ring is IDLE. The GT | |
1951 | * will then assume that it is busy and bring it out of rc6. | |
1952 | */ | |
0206e353 | 1953 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1954 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1955 | ||
1956 | /* Clear the context id. Here be magic! */ | |
1957 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1958 | |
12f55818 | 1959 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1960 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1961 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1962 | 50)) | |
1963 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1964 | |
12f55818 | 1965 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1966 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1967 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1968 | ||
1969 | /* Let the ring send IDLE messages to the GT again, | |
1970 | * and so let it sleep to conserve power when idle. | |
1971 | */ | |
0206e353 | 1972 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1973 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1974 | } |
1975 | ||
a4872ba6 | 1976 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 1977 | u32 invalidate, u32 flush) |
881f47b6 | 1978 | { |
71a77e07 | 1979 | uint32_t cmd; |
b72f3acb CW |
1980 | int ret; |
1981 | ||
b72f3acb CW |
1982 | ret = intel_ring_begin(ring, 4); |
1983 | if (ret) | |
1984 | return ret; | |
1985 | ||
71a77e07 | 1986 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1987 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1988 | cmd += 1; | |
9a289771 JB |
1989 | /* |
1990 | * Bspec vol 1c.5 - video engine command streamer: | |
1991 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1992 | * operation is complete. This bit is only valid when the | |
1993 | * Post-Sync Operation field is a value of 1h or 3h." | |
1994 | */ | |
71a77e07 | 1995 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1996 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1997 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1998 | intel_ring_emit(ring, cmd); |
9a289771 | 1999 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2000 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2001 | intel_ring_emit(ring, 0); /* upper addr */ | |
2002 | intel_ring_emit(ring, 0); /* value */ | |
2003 | } else { | |
2004 | intel_ring_emit(ring, 0); | |
2005 | intel_ring_emit(ring, MI_NOOP); | |
2006 | } | |
b72f3acb CW |
2007 | intel_ring_advance(ring); |
2008 | return 0; | |
881f47b6 XH |
2009 | } |
2010 | ||
1c7a0623 | 2011 | static int |
a4872ba6 | 2012 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2013 | u64 offset, u32 len, |
1c7a0623 BW |
2014 | unsigned flags) |
2015 | { | |
28cf5415 BW |
2016 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
2017 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
2018 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
2019 | int ret; |
2020 | ||
2021 | ret = intel_ring_begin(ring, 4); | |
2022 | if (ret) | |
2023 | return ret; | |
2024 | ||
2025 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2026 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2027 | intel_ring_emit(ring, lower_32_bits(offset)); |
2028 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2029 | intel_ring_emit(ring, MI_NOOP); |
2030 | intel_ring_advance(ring); | |
2031 | ||
2032 | return 0; | |
2033 | } | |
2034 | ||
d7d4eedd | 2035 | static int |
a4872ba6 | 2036 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2037 | u64 offset, u32 len, |
d7d4eedd CW |
2038 | unsigned flags) |
2039 | { | |
2040 | int ret; | |
2041 | ||
2042 | ret = intel_ring_begin(ring, 2); | |
2043 | if (ret) | |
2044 | return ret; | |
2045 | ||
2046 | intel_ring_emit(ring, | |
2047 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
2048 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
2049 | /* bit0-7 is the length on GEN6+ */ | |
2050 | intel_ring_emit(ring, offset); | |
2051 | intel_ring_advance(ring); | |
2052 | ||
2053 | return 0; | |
2054 | } | |
2055 | ||
881f47b6 | 2056 | static int |
a4872ba6 | 2057 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2058 | u64 offset, u32 len, |
d7d4eedd | 2059 | unsigned flags) |
881f47b6 | 2060 | { |
0206e353 | 2061 | int ret; |
ab6f8e32 | 2062 | |
0206e353 AJ |
2063 | ret = intel_ring_begin(ring, 2); |
2064 | if (ret) | |
2065 | return ret; | |
e1f99ce6 | 2066 | |
d7d4eedd CW |
2067 | intel_ring_emit(ring, |
2068 | MI_BATCH_BUFFER_START | | |
2069 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2070 | /* bit0-7 is the length on GEN6+ */ |
2071 | intel_ring_emit(ring, offset); | |
2072 | intel_ring_advance(ring); | |
ab6f8e32 | 2073 | |
0206e353 | 2074 | return 0; |
881f47b6 XH |
2075 | } |
2076 | ||
549f7365 CW |
2077 | /* Blitter support (SandyBridge+) */ |
2078 | ||
a4872ba6 | 2079 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2080 | u32 invalidate, u32 flush) |
8d19215b | 2081 | { |
fd3da6c9 | 2082 | struct drm_device *dev = ring->dev; |
71a77e07 | 2083 | uint32_t cmd; |
b72f3acb CW |
2084 | int ret; |
2085 | ||
6a233c78 | 2086 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2087 | if (ret) |
2088 | return ret; | |
2089 | ||
71a77e07 | 2090 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2091 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2092 | cmd += 1; | |
9a289771 JB |
2093 | /* |
2094 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2095 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2096 | * operation is complete. This bit is only valid when the | |
2097 | * Post-Sync Operation field is a value of 1h or 3h." | |
2098 | */ | |
71a77e07 | 2099 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2100 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2101 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2102 | intel_ring_emit(ring, cmd); |
9a289771 | 2103 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2104 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2105 | intel_ring_emit(ring, 0); /* upper addr */ | |
2106 | intel_ring_emit(ring, 0); /* value */ | |
2107 | } else { | |
2108 | intel_ring_emit(ring, 0); | |
2109 | intel_ring_emit(ring, MI_NOOP); | |
2110 | } | |
b72f3acb | 2111 | intel_ring_advance(ring); |
fd3da6c9 | 2112 | |
9688ecad | 2113 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
2114 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
2115 | ||
b72f3acb | 2116 | return 0; |
8d19215b ZN |
2117 | } |
2118 | ||
5c1143bb XH |
2119 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2120 | { | |
4640c4ff | 2121 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2122 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2123 | struct drm_i915_gem_object *obj; |
2124 | int ret; | |
5c1143bb | 2125 | |
59465b5f DV |
2126 | ring->name = "render ring"; |
2127 | ring->id = RCS; | |
2128 | ring->mmio_base = RENDER_RING_BASE; | |
2129 | ||
707d9cf9 | 2130 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2131 | if (i915_semaphore_is_enabled(dev)) { |
2132 | obj = i915_gem_alloc_object(dev, 4096); | |
2133 | if (obj == NULL) { | |
2134 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2135 | i915.semaphores = 0; | |
2136 | } else { | |
2137 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2138 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2139 | if (ret != 0) { | |
2140 | drm_gem_object_unreference(&obj->base); | |
2141 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2142 | i915.semaphores = 0; | |
2143 | } else | |
2144 | dev_priv->semaphore_obj = obj; | |
2145 | } | |
2146 | } | |
707d9cf9 BW |
2147 | ring->add_request = gen6_add_request; |
2148 | ring->flush = gen8_render_ring_flush; | |
2149 | ring->irq_get = gen8_ring_get_irq; | |
2150 | ring->irq_put = gen8_ring_put_irq; | |
2151 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2152 | ring->get_seqno = gen6_ring_get_seqno; | |
2153 | ring->set_seqno = ring_set_seqno; | |
2154 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2155 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2156 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2157 | ring->semaphore.signal = gen8_rcs_signal; |
2158 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2159 | } |
2160 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2161 | ring->add_request = gen6_add_request; |
4772eaeb | 2162 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2163 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2164 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2165 | ring->irq_get = gen6_ring_get_irq; |
2166 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2167 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2168 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2169 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2170 | if (i915_semaphore_is_enabled(dev)) { |
2171 | ring->semaphore.sync_to = gen6_ring_sync; | |
2172 | ring->semaphore.signal = gen6_signal; | |
2173 | /* | |
2174 | * The current semaphore is only applied on pre-gen8 | |
2175 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2176 | * platform. So the semaphore between RCS and VCS2 is | |
2177 | * initialized as INVALID. Gen8 will initialize the | |
2178 | * sema between VCS2 and RCS later. | |
2179 | */ | |
2180 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2181 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2182 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2183 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2184 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2185 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2186 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2187 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2188 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2189 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2190 | } | |
c6df541c CW |
2191 | } else if (IS_GEN5(dev)) { |
2192 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2193 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2194 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2195 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2196 | ring->irq_get = gen5_ring_get_irq; |
2197 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2198 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2199 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2200 | } else { |
8620a3a9 | 2201 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2202 | if (INTEL_INFO(dev)->gen < 4) |
2203 | ring->flush = gen2_render_ring_flush; | |
2204 | else | |
2205 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2206 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2207 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2208 | if (IS_GEN2(dev)) { |
2209 | ring->irq_get = i8xx_ring_get_irq; | |
2210 | ring->irq_put = i8xx_ring_put_irq; | |
2211 | } else { | |
2212 | ring->irq_get = i9xx_ring_get_irq; | |
2213 | ring->irq_put = i9xx_ring_put_irq; | |
2214 | } | |
e3670319 | 2215 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2216 | } |
59465b5f | 2217 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2218 | |
d7d4eedd CW |
2219 | if (IS_HASWELL(dev)) |
2220 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2221 | else if (IS_GEN8(dev)) |
2222 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2223 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2224 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2225 | else if (INTEL_INFO(dev)->gen >= 4) | |
2226 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2227 | else if (IS_I830(dev) || IS_845G(dev)) | |
2228 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2229 | else | |
2230 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2231 | ring->init = init_render_ring; |
2232 | ring->cleanup = render_ring_cleanup; | |
2233 | ||
b45305fc DV |
2234 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2235 | if (HAS_BROKEN_CS_TLB(dev)) { | |
b45305fc DV |
2236 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
2237 | if (obj == NULL) { | |
2238 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2239 | return -ENOMEM; | |
2240 | } | |
2241 | ||
be1fa129 | 2242 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2243 | if (ret != 0) { |
2244 | drm_gem_object_unreference(&obj->base); | |
2245 | DRM_ERROR("Failed to ping batch bo\n"); | |
2246 | return ret; | |
2247 | } | |
2248 | ||
0d1aacac CW |
2249 | ring->scratch.obj = obj; |
2250 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2251 | } |
2252 | ||
1ec14ad3 | 2253 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
2254 | } |
2255 | ||
e8616b6c CW |
2256 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2257 | { | |
4640c4ff | 2258 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2259 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
8ee14975 | 2260 | struct intel_ringbuffer *ringbuf = ring->buffer; |
6b8294a4 | 2261 | int ret; |
e8616b6c | 2262 | |
8ee14975 OM |
2263 | if (ringbuf == NULL) { |
2264 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
2265 | if (!ringbuf) | |
2266 | return -ENOMEM; | |
2267 | ring->buffer = ringbuf; | |
2268 | } | |
2269 | ||
59465b5f DV |
2270 | ring->name = "render ring"; |
2271 | ring->id = RCS; | |
2272 | ring->mmio_base = RENDER_RING_BASE; | |
2273 | ||
e8616b6c | 2274 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a | 2275 | /* non-kms not supported on gen6+ */ |
8ee14975 OM |
2276 | ret = -ENODEV; |
2277 | goto err_ringbuf; | |
e8616b6c | 2278 | } |
28f0cbf7 DV |
2279 | |
2280 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2281 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2282 | * the special gen5 functions. */ | |
2283 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2284 | if (INTEL_INFO(dev)->gen < 4) |
2285 | ring->flush = gen2_render_ring_flush; | |
2286 | else | |
2287 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2288 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2289 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2290 | if (IS_GEN2(dev)) { |
2291 | ring->irq_get = i8xx_ring_get_irq; | |
2292 | ring->irq_put = i8xx_ring_put_irq; | |
2293 | } else { | |
2294 | ring->irq_get = i9xx_ring_get_irq; | |
2295 | ring->irq_put = i9xx_ring_put_irq; | |
2296 | } | |
28f0cbf7 | 2297 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2298 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2299 | if (INTEL_INFO(dev)->gen >= 4) |
2300 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2301 | else if (IS_I830(dev) || IS_845G(dev)) | |
2302 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2303 | else | |
2304 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2305 | ring->init = init_render_ring; |
2306 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2307 | |
2308 | ring->dev = dev; | |
2309 | INIT_LIST_HEAD(&ring->active_list); | |
2310 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c | 2311 | |
93b0a4e0 OM |
2312 | ringbuf->size = size; |
2313 | ringbuf->effective_size = ringbuf->size; | |
17f10fdc | 2314 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
93b0a4e0 | 2315 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
e8616b6c | 2316 | |
93b0a4e0 OM |
2317 | ringbuf->virtual_start = ioremap_wc(start, size); |
2318 | if (ringbuf->virtual_start == NULL) { | |
e8616b6c CW |
2319 | DRM_ERROR("can not ioremap virtual address for" |
2320 | " ring buffer\n"); | |
8ee14975 OM |
2321 | ret = -ENOMEM; |
2322 | goto err_ringbuf; | |
e8616b6c CW |
2323 | } |
2324 | ||
6b8294a4 | 2325 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2326 | ret = init_phys_status_page(ring); |
6b8294a4 | 2327 | if (ret) |
8ee14975 | 2328 | goto err_vstart; |
6b8294a4 CW |
2329 | } |
2330 | ||
e8616b6c | 2331 | return 0; |
8ee14975 OM |
2332 | |
2333 | err_vstart: | |
93b0a4e0 | 2334 | iounmap(ringbuf->virtual_start); |
8ee14975 OM |
2335 | err_ringbuf: |
2336 | kfree(ringbuf); | |
2337 | ring->buffer = NULL; | |
2338 | return ret; | |
e8616b6c CW |
2339 | } |
2340 | ||
5c1143bb XH |
2341 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2342 | { | |
4640c4ff | 2343 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2344 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2345 | |
58fa3835 DV |
2346 | ring->name = "bsd ring"; |
2347 | ring->id = VCS; | |
2348 | ||
0fd2c201 | 2349 | ring->write_tail = ring_write_tail; |
780f18c8 | 2350 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2351 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2352 | /* gen6 bsd needs a special wa for tail updates */ |
2353 | if (IS_GEN6(dev)) | |
2354 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2355 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2356 | ring->add_request = gen6_add_request; |
2357 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2358 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2359 | if (INTEL_INFO(dev)->gen >= 8) { |
2360 | ring->irq_enable_mask = | |
2361 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2362 | ring->irq_get = gen8_ring_get_irq; | |
2363 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2364 | ring->dispatch_execbuffer = |
2365 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2366 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2367 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2368 | ring->semaphore.signal = gen8_xcs_signal; |
2369 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2370 | } |
abd58f01 BW |
2371 | } else { |
2372 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2373 | ring->irq_get = gen6_ring_get_irq; | |
2374 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2375 | ring->dispatch_execbuffer = |
2376 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2377 | if (i915_semaphore_is_enabled(dev)) { |
2378 | ring->semaphore.sync_to = gen6_ring_sync; | |
2379 | ring->semaphore.signal = gen6_signal; | |
2380 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2381 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2382 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2383 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2384 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2385 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2386 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2387 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2388 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2389 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2390 | } | |
abd58f01 | 2391 | } |
58fa3835 DV |
2392 | } else { |
2393 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2394 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2395 | ring->add_request = i9xx_add_request; |
58fa3835 | 2396 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2397 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2398 | if (IS_GEN5(dev)) { |
cc609d5d | 2399 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2400 | ring->irq_get = gen5_ring_get_irq; |
2401 | ring->irq_put = gen5_ring_put_irq; | |
2402 | } else { | |
e3670319 | 2403 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2404 | ring->irq_get = i9xx_ring_get_irq; |
2405 | ring->irq_put = i9xx_ring_put_irq; | |
2406 | } | |
fb3256da | 2407 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2408 | } |
2409 | ring->init = init_ring_common; | |
2410 | ||
1ec14ad3 | 2411 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2412 | } |
549f7365 | 2413 | |
845f74a7 ZY |
2414 | /** |
2415 | * Initialize the second BSD ring for Broadwell GT3. | |
2416 | * It is noted that this only exists on Broadwell GT3. | |
2417 | */ | |
2418 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2419 | { | |
2420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2421 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2422 | |
2423 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2424 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2425 | return -EINVAL; | |
2426 | } | |
2427 | ||
f7b64236 | 2428 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2429 | ring->id = VCS2; |
2430 | ||
2431 | ring->write_tail = ring_write_tail; | |
2432 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2433 | ring->flush = gen6_bsd_ring_flush; | |
2434 | ring->add_request = gen6_add_request; | |
2435 | ring->get_seqno = gen6_ring_get_seqno; | |
2436 | ring->set_seqno = ring_set_seqno; | |
2437 | ring->irq_enable_mask = | |
2438 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2439 | ring->irq_get = gen8_ring_get_irq; | |
2440 | ring->irq_put = gen8_ring_put_irq; | |
2441 | ring->dispatch_execbuffer = | |
2442 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2443 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2444 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2445 | ring->semaphore.signal = gen8_xcs_signal; |
2446 | GEN8_RING_SEMAPHORE_INIT; | |
2447 | } | |
845f74a7 ZY |
2448 | ring->init = init_ring_common; |
2449 | ||
2450 | return intel_init_ring_buffer(dev, ring); | |
2451 | } | |
2452 | ||
549f7365 CW |
2453 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2454 | { | |
4640c4ff | 2455 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2456 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2457 | |
3535d9dd DV |
2458 | ring->name = "blitter ring"; |
2459 | ring->id = BCS; | |
2460 | ||
2461 | ring->mmio_base = BLT_RING_BASE; | |
2462 | ring->write_tail = ring_write_tail; | |
ea251324 | 2463 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2464 | ring->add_request = gen6_add_request; |
2465 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2466 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2467 | if (INTEL_INFO(dev)->gen >= 8) { |
2468 | ring->irq_enable_mask = | |
2469 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2470 | ring->irq_get = gen8_ring_get_irq; | |
2471 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2472 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2473 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2474 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2475 | ring->semaphore.signal = gen8_xcs_signal; |
2476 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2477 | } |
abd58f01 BW |
2478 | } else { |
2479 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2480 | ring->irq_get = gen6_ring_get_irq; | |
2481 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2482 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2483 | if (i915_semaphore_is_enabled(dev)) { |
2484 | ring->semaphore.signal = gen6_signal; | |
2485 | ring->semaphore.sync_to = gen6_ring_sync; | |
2486 | /* | |
2487 | * The current semaphore is only applied on pre-gen8 | |
2488 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2489 | * platform. So the semaphore between BCS and VCS2 is | |
2490 | * initialized as INVALID. Gen8 will initialize the | |
2491 | * sema between BCS and VCS2 later. | |
2492 | */ | |
2493 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2494 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2495 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2496 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2497 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2498 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2499 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2500 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2501 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2502 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2503 | } | |
abd58f01 | 2504 | } |
3535d9dd | 2505 | ring->init = init_ring_common; |
549f7365 | 2506 | |
1ec14ad3 | 2507 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2508 | } |
a7b9761d | 2509 | |
9a8a2213 BW |
2510 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2511 | { | |
4640c4ff | 2512 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2513 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2514 | |
2515 | ring->name = "video enhancement ring"; | |
2516 | ring->id = VECS; | |
2517 | ||
2518 | ring->mmio_base = VEBOX_RING_BASE; | |
2519 | ring->write_tail = ring_write_tail; | |
2520 | ring->flush = gen6_ring_flush; | |
2521 | ring->add_request = gen6_add_request; | |
2522 | ring->get_seqno = gen6_ring_get_seqno; | |
2523 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2524 | |
2525 | if (INTEL_INFO(dev)->gen >= 8) { | |
2526 | ring->irq_enable_mask = | |
40c499f9 | 2527 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2528 | ring->irq_get = gen8_ring_get_irq; |
2529 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2530 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2531 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2532 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2533 | ring->semaphore.signal = gen8_xcs_signal; |
2534 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2535 | } |
abd58f01 BW |
2536 | } else { |
2537 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2538 | ring->irq_get = hsw_vebox_get_irq; | |
2539 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2540 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2541 | if (i915_semaphore_is_enabled(dev)) { |
2542 | ring->semaphore.sync_to = gen6_ring_sync; | |
2543 | ring->semaphore.signal = gen6_signal; | |
2544 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2545 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2546 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2547 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2548 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2549 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2550 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2551 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2552 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2553 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2554 | } | |
abd58f01 | 2555 | } |
9a8a2213 BW |
2556 | ring->init = init_ring_common; |
2557 | ||
2558 | return intel_init_ring_buffer(dev, ring); | |
2559 | } | |
2560 | ||
a7b9761d | 2561 | int |
a4872ba6 | 2562 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2563 | { |
2564 | int ret; | |
2565 | ||
2566 | if (!ring->gpu_caches_dirty) | |
2567 | return 0; | |
2568 | ||
2569 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2570 | if (ret) | |
2571 | return ret; | |
2572 | ||
2573 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2574 | ||
2575 | ring->gpu_caches_dirty = false; | |
2576 | return 0; | |
2577 | } | |
2578 | ||
2579 | int | |
a4872ba6 | 2580 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2581 | { |
2582 | uint32_t flush_domains; | |
2583 | int ret; | |
2584 | ||
2585 | flush_domains = 0; | |
2586 | if (ring->gpu_caches_dirty) | |
2587 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2588 | ||
2589 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2590 | if (ret) | |
2591 | return ret; | |
2592 | ||
2593 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2594 | ||
2595 | ring->gpu_caches_dirty = false; | |
2596 | return 0; | |
2597 | } | |
e3efda49 CW |
2598 | |
2599 | void | |
a4872ba6 | 2600 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2601 | { |
2602 | int ret; | |
2603 | ||
2604 | if (!intel_ring_initialized(ring)) | |
2605 | return; | |
2606 | ||
2607 | ret = intel_ring_idle(ring); | |
2608 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2609 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2610 | ring->name, ret); | |
2611 | ||
2612 | stop_ring(ring); | |
2613 | } |