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drm/i915: Rename 'flags' to 'dispatch_flags' for better code reading
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 382
add284a3
CW		 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
f3987631
PZ		 385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
b9e1faa7 397 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
9688ecad 401 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
4772eaeb
PZ		 404 return 0;
405}
406
884ceace
KG		 407static int
408gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410{
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426}
427
a5f3d68e 428static int
a4872ba6 429gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 430 u32 invalidate_domains, u32 flush_domains)
431{
432 u32 flags = 0;
18393f63 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 434 int ret;
a5f3d68e
BW		 435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
a5f3d68e
BW		 459 }
460
c5ad011d
RV		 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
a5f3d68e
BW		 469}
470
a4872ba6 471static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 472 u32 value)
d46eefa2 473{
4640c4ff 474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 475 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 476}
477
a4872ba6 478u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 479{
4640c4ff 480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 481 u64 acthd;
8187a2b7 482
50877445
CW		 483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
8187a2b7
ZN		 492}
493
a4872ba6 494static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503}
504
af75f269
DL		 505static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
506{
507 struct drm_device *dev = ring->dev;
508 struct drm_i915_private *dev_priv = ring->dev->dev_private;
509 u32 mmio = 0;
510
511 /* The ring status page addresses are no longer next to the rest of
512 * the ring registers as of gen7.
513 */
514 if (IS_GEN7(dev)) {
515 switch (ring->id) {
516 case RCS:
517 mmio = RENDER_HWS_PGA_GEN7;
518 break;
519 case BCS:
520 mmio = BLT_HWS_PGA_GEN7;
521 break;
522 /*
523 * VCS2 actually doesn't exist on Gen7. Only shut up
524 * gcc switch check warning
525 */
526 case VCS2:
527 case VCS:
528 mmio = BSD_HWS_PGA_GEN7;
529 break;
530 case VECS:
531 mmio = VEBOX_HWS_PGA_GEN7;
532 break;
533 }
534 } else if (IS_GEN6(ring->dev)) {
535 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
536 } else {
537 /* XXX: gen8 returns to sanity */
538 mmio = RING_HWS_PGA(ring->mmio_base);
539 }
540
541 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
542 POSTING_READ(mmio);
543
544 /*
545 * Flush the TLB for this page
546 *
547 * FIXME: These two bits have disappeared on gen8, so a question
548 * arises: do we still need this and if so how should we go about
549 * invalidating the TLB?
550 */
551 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
552 u32 reg = RING_INSTPM(ring->mmio_base);
553
554 /* ring should be idle before issuing a sync flush*/
555 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
556
557 I915_WRITE(reg,
558 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
559 INSTPM_SYNC_FLUSH));
560 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
561 1000))
562 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
563 ring->name);
564 }
565}
566
a4872ba6 567static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 568{
9991ae78 569 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 570
9991ae78
CW		 571 if (!IS_GEN2(ring->dev)) {
572 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 573 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
574 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 575 /* Sometimes we observe that the idle flag is not
576 * set even though the ring is empty. So double
577 * check before giving up.
578 */
579 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
580 return false;
9991ae78
CW		 581 }
582 }
b7884eb4 583
7f2ab699 584 I915_WRITE_CTL(ring, 0);
570ef608 585 I915_WRITE_HEAD(ring, 0);
78501eac 586 ring->write_tail(ring, 0);
8187a2b7 587
9991ae78
CW		 588 if (!IS_GEN2(ring->dev)) {
589 (void)I915_READ_CTL(ring);
590 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
591 }
a51435a3 592
9991ae78
CW		 593 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
594}
8187a2b7 595
a4872ba6 596static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 597{
598 struct drm_device *dev = ring->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 600 struct intel_ringbuffer *ringbuf = ring->buffer;
601 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 602 int ret = 0;
603
59bad947 604 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 605
606 if (!stop_ring(ring)) {
607 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 608 DRM_DEBUG_KMS("%s head not reset to zero "
609 "ctl %08x head %08x tail %08x start %08x\n",
610 ring->name,
611 I915_READ_CTL(ring),
612 I915_READ_HEAD(ring),
613 I915_READ_TAIL(ring),
614 I915_READ_START(ring));
8187a2b7 615
9991ae78 616 if (!stop_ring(ring)) {
6fd0d56e
CW		 617 DRM_ERROR("failed to set %s head to zero "
618 "ctl %08x head %08x tail %08x start %08x\n",
619 ring->name,
620 I915_READ_CTL(ring),
621 I915_READ_HEAD(ring),
622 I915_READ_TAIL(ring),
623 I915_READ_START(ring));
9991ae78
CW		 624 ret = -EIO;
625 goto out;
6fd0d56e 626 }
8187a2b7
ZN		 627 }
628
9991ae78
CW		 629 if (I915_NEED_GFX_HWS(dev))
630 intel_ring_setup_status_page(ring);
631 else
632 ring_setup_phys_status_page(ring);
633
ece4a17d
JK		 634 /* Enforce ordering by reading HEAD register back */
635 I915_READ_HEAD(ring);
636
0d8957c8
DV		 637 /* Initialize the ring. This must happen _after_ we've cleared the ring
638 * registers with the above sequence (the readback of the HEAD registers
639 * also enforces ordering), otherwise the hw might lose the new ring
640 * register values. */
f343c5f6 641 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 642
643 /* WaClearRingBufHeadRegAtInit:ctg,elk */
644 if (I915_READ_HEAD(ring))
645 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
646 ring->name, I915_READ_HEAD(ring));
647 I915_WRITE_HEAD(ring, 0);
648 (void)I915_READ_HEAD(ring);
649
7f2ab699 650 I915_WRITE_CTL(ring,
93b0a4e0 651 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 652 | RING_VALID);
8187a2b7 653
8187a2b7 654 /* If the head is still not zero, the ring is dead */
f01db988 655 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 656 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 657 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 658 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 659 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
660 ring->name,
661 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
662 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
663 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 664 ret = -EIO;
665 goto out;
8187a2b7
ZN		 666 }
667
ebd0fd4b 668 ringbuf->last_retired_head = -1;
5c6c6003
CW		 669 ringbuf->head = I915_READ_HEAD(ring);
670 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 671 intel_ring_update_space(ringbuf);
1ec14ad3 672
50f018df
CW		 673 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
674
b7884eb4 675out:
59bad947 676 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 677
678 return ret;
8187a2b7
ZN		 679}
680
9b1136d5
OM		 681void
682intel_fini_pipe_control(struct intel_engine_cs *ring)
683{
684 struct drm_device *dev = ring->dev;
685
686 if (ring->scratch.obj == NULL)
687 return;
688
689 if (INTEL_INFO(dev)->gen >= 5) {
690 kunmap(sg_page(ring->scratch.obj->pages->sgl));
691 i915_gem_object_ggtt_unpin(ring->scratch.obj);
692 }
693
694 drm_gem_object_unreference(&ring->scratch.obj->base);
695 ring->scratch.obj = NULL;
696}
697
698int
699intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 700{
c6df541c
CW		 701 int ret;
702
bfc882b4 703 WARN_ON(ring->scratch.obj);
c6df541c 704
0d1aacac
CW		 705 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
706 if (ring->scratch.obj == NULL) {
c6df541c
CW		 707 DRM_ERROR("Failed to allocate seqno page\n");
708 ret = -ENOMEM;
709 goto err;
710 }
e4ffd173 711
a9cc726c
DV		 712 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
713 if (ret)
714 goto err_unref;
c6df541c 715
1ec9e26d 716 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 717 if (ret)
718 goto err_unref;
719
0d1aacac
CW		 720 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
721 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
722 if (ring->scratch.cpu_page == NULL) {
56b085a0 723 ret = -ENOMEM;
c6df541c 724 goto err_unpin;
56b085a0 725 }
c6df541c 726
2b1086cc 727 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 728 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 729 return 0;
730
731err_unpin:
d7f46fc4 732 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 733err_unref:
0d1aacac 734 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 735err:
c6df541c
CW		 736 return ret;
737}
738
771b9a53
MT		 739static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
740 struct intel_context *ctx)
86d7f238 741{
7225342a 742 int ret, i;
888b5995
AS		 743 struct drm_device *dev = ring->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 745 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 746
e6c1abb7 747 if (WARN_ON_ONCE(w->count == 0))
7225342a 748 return 0;
888b5995 749
7225342a
MK		 750 ring->gpu_caches_dirty = true;
751 ret = intel_ring_flush_all_caches(ring);
752 if (ret)
753 return ret;
888b5995 754
22a916aa 755 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 756 if (ret)
757 return ret;
758
22a916aa 759 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 760 for (i = 0; i < w->count; i++) {
7225342a
MK		 761 intel_ring_emit(ring, w->reg[i].addr);
762 intel_ring_emit(ring, w->reg[i].value);
763 }
22a916aa 764 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 765
766 intel_ring_advance(ring);
767
768 ring->gpu_caches_dirty = true;
769 ret = intel_ring_flush_all_caches(ring);
770 if (ret)
771 return ret;
888b5995 772
7225342a 773 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 774
7225342a 775 return 0;
86d7f238
AS		 776}
777
8f0e2b9d
DV		 778static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
779 struct intel_context *ctx)
780{
781 int ret;
782
783 ret = intel_ring_workarounds_emit(ring, ctx);
784 if (ret != 0)
785 return ret;
786
787 ret = i915_gem_render_state_init(ring);
788 if (ret)
789 DRM_ERROR("init render state: %d\n", ret);
790
791 return ret;
792}
793
7225342a 794static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 795 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 796{
797 const u32 idx = dev_priv->workarounds.count;
798
799 if (WARN_ON(idx >= I915_MAX_WA_REGS))
800 return -ENOSPC;
801
802 dev_priv->workarounds.reg[idx].addr = addr;
803 dev_priv->workarounds.reg[idx].value = val;
804 dev_priv->workarounds.reg[idx].mask = mask;
805
806 dev_priv->workarounds.count++;
807
808 return 0;
86d7f238
AS		 809}
810
cf4b0de6
DL		 811#define WA_REG(addr, mask, val) { \
812 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 813 if (r) \
814 return r; \
815 }
816
817#define WA_SET_BIT_MASKED(addr, mask) \
26459343 818 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 819
820#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 821 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 822
98533251 823#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 824 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 825
cf4b0de6
DL		 826#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
827#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 828
cf4b0de6 829#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 830
00e1e623 831static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 832{
888b5995
AS		 833 struct drm_device *dev = ring->dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 835
86d7f238 836 /* WaDisablePartialInstShootdown:bdw */
101b376d 837 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 838 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
839 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
840 STALL_DOP_GATING_DISABLE);
86d7f238 841
101b376d 842 /* WaDisableDopClockGating:bdw */
7225342a
MK		 843 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
844 DOP_CLOCK_GATING_DISABLE);
86d7f238 845
7225342a
MK		 846 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
847 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 848
849 /* Use Force Non-Coherent whenever executing a 3D context. This is a
850 * workaround for for a possible hang in the unlikely event a TLB
851 * invalidation occurs during a PSD flush.
852 */
7225342a 853 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 854 /* WaForceEnableNonCoherent:bdw */
7225342a 855 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 856 /* WaForceContextSaveRestoreNonCoherent:bdw */
857 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
858 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 859 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 860 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 861 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 862
2701fc43
KG		 863 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
864 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
865 * polygons in the same 8x4 pixel/sample area to be processed without
866 * stalling waiting for the earlier ones to write to Hierarchical Z
867 * buffer."
868 *
869 * This optimization is off by default for Broadwell; turn it on.
870 */
871 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
872
86d7f238 873 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 874 WA_SET_BIT_MASKED(CACHE_MODE_1,
875 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 876
877 /*
878 * BSpec recommends 8x4 when MSAA is used,
879 * however in practice 16x4 seems fastest.
880 *
881 * Note that PS/WM thread counts depend on the WIZ hashing
882 * disable bit, which we don't touch here, but it's good
883 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
884 */
98533251
DL		 885 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
886 GEN6_WIZ_HASHING_MASK,
887 GEN6_WIZ_HASHING_16x4);
888b5995 888
86d7f238
AS		 889 return 0;
890}
891
00e1e623
VS		 892static int chv_init_workarounds(struct intel_engine_cs *ring)
893{
00e1e623
VS		 894 struct drm_device *dev = ring->dev;
895 struct drm_i915_private *dev_priv = dev->dev_private;
896
00e1e623 897 /* WaDisablePartialInstShootdown:chv */
00e1e623 898 /* WaDisableThreadStallDopClockGating:chv */
7225342a 899 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 900 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
901 STALL_DOP_GATING_DISABLE);
00e1e623 902
95289009
AS		 903 /* Use Force Non-Coherent whenever executing a 3D context. This is a
904 * workaround for a possible hang in the unlikely event a TLB
905 * invalidation occurs during a PSD flush.
906 */
907 /* WaForceEnableNonCoherent:chv */
908 /* WaHdcDisableFetchWhenMasked:chv */
909 WA_SET_BIT_MASKED(HDC_CHICKEN0,
910 HDC_FORCE_NON_COHERENT |
911 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
912
973a5b06
KG		 913 /* According to the CACHE_MODE_0 default value documentation, some
914 * CHV platforms disable this optimization by default. Turn it on.
915 */
916 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
917
14bc16e3
VS		 918 /* Wa4x4STCOptimizationDisable:chv */
919 WA_SET_BIT_MASKED(CACHE_MODE_1,
920 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
921
d60de81d
KG		 922 /* Improve HiZ throughput on CHV. */
923 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
924
e7fc2436
VS		 925 /*
926 * BSpec recommends 8x4 when MSAA is used,
927 * however in practice 16x4 seems fastest.
928 *
929 * Note that PS/WM thread counts depend on the WIZ hashing
930 * disable bit, which we don't touch here, but it's good
931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
932 */
933 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
934 GEN6_WIZ_HASHING_MASK,
935 GEN6_WIZ_HASHING_16x4);
936
65ca7514
DL		 937 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
938 INTEL_REVID(dev) == SKL_REVID_D0)
939 /* WaBarrierPerformanceFixDisable:skl */
940 WA_SET_BIT_MASKED(HDC_CHICKEN0,
941 HDC_FENCE_DEST_SLM_DISABLE |
942 HDC_BARRIER_PERFORMANCE_DISABLE);
943
7225342a
MK		 944 return 0;
945}
946
3b106531
HN		 947static int gen9_init_workarounds(struct intel_engine_cs *ring)
948{
ab0dfafe
HN		 949 struct drm_device *dev = ring->dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
951
952 /* WaDisablePartialInstShootdown:skl */
953 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
954 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
955
8424171e
NH		 956 /* Syncing dependencies between camera and graphics */
957 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
958 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
959
35c8ce6a
DL		 960 if (INTEL_REVID(dev) == SKL_REVID_A0 ||
961 INTEL_REVID(dev) == SKL_REVID_B0) {
a86eb582
DL		 962 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
963 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
964 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 965 }
966
183c6dac
DL		 967 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
968 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
969 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
970 GEN9_RHWO_OPTIMIZATION_DISABLE);
971 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
972 DISABLE_PIXEL_MASK_CAMMING);
973 }
974
cac23df4
NH		 975 if (INTEL_REVID(dev) >= SKL_REVID_C0) {
976 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
977 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
978 GEN9_ENABLE_YV12_BUGFIX);
979 }
980
13bea49c
HN		 981 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
982 /*
983 *Use Force Non-Coherent whenever executing a 3D context. This
984 * is a workaround for a possible hang in the unlikely event
985 * a TLB invalidation occurs during a PSD flush.
986 */
987 /* WaForceEnableNonCoherent:skl */
988 WA_SET_BIT_MASKED(HDC_CHICKEN0,
989 HDC_FORCE_NON_COHERENT);
990 }
991
1840481f
HN		 992 /* Wa4x4STCOptimizationDisable:skl */
993 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
994
9370cd98
DL		 995 /* WaDisablePartialResolveInVc:skl */
996 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
997
e2db7071
DL		 998 /* WaCcsTlbPrefetchDisable:skl */
999 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
1000 GEN9_CCS_TLB_PREFETCH_ENABLE);
1001
3b106531
HN		 1002 return 0;
1003}
1004
b7668791
DL		 1005static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1006{
1007 struct drm_device *dev = ring->dev;
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 u8 vals[3] = { 0, 0, 0 };
1010 unsigned int i;
1011
1012 for (i = 0; i < 3; i++) {
1013 u8 ss;
1014
1015 /*
1016 * Only consider slices where one, and only one, subslice has 7
1017 * EUs
1018 */
1019 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1020 continue;
1021
1022 /*
1023 * subslice_7eu[i] != 0 (because of the check above) and
1024 * ss_max == 4 (maximum number of subslices possible per slice)
1025 *
1026 * -> 0 <= ss <= 3;
1027 */
1028 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1029 vals[i] = 3 - ss;
1030 }
1031
1032 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1033 return 0;
1034
1035 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1036 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1037 GEN9_IZ_HASHING_MASK(2) |
1038 GEN9_IZ_HASHING_MASK(1) |
1039 GEN9_IZ_HASHING_MASK(0),
1040 GEN9_IZ_HASHING(2, vals[2]) |
1041 GEN9_IZ_HASHING(1, vals[1]) |
1042 GEN9_IZ_HASHING(0, vals[0]));
1043
1044 return 0;
1045}
1046
1047
8d205494
DL		 1048static int skl_init_workarounds(struct intel_engine_cs *ring)
1049{
d0bbbc4f
DL		 1050 struct drm_device *dev = ring->dev;
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1052
8d205494
DL		 1053 gen9_init_workarounds(ring);
1054
d0bbbc4f
DL		 1055 /* WaDisablePowerCompilerClockGating:skl */
1056 if (INTEL_REVID(dev) == SKL_REVID_B0)
1057 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1058 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1059
b7668791 1060 return skl_tune_iz_hashing(ring);
8d205494
DL		 1061}
1062
771b9a53 1063int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1064{
1065 struct drm_device *dev = ring->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068 WARN_ON(ring->id != RCS);
1069
1070 dev_priv->workarounds.count = 0;
1071
1072 if (IS_BROADWELL(dev))
1073 return bdw_init_workarounds(ring);
1074
1075 if (IS_CHERRYVIEW(dev))
1076 return chv_init_workarounds(ring);
00e1e623 1077
8d205494
DL		 1078 if (IS_SKYLAKE(dev))
1079 return skl_init_workarounds(ring);
1080 else if (IS_GEN9(dev))
3b106531
HN		 1081 return gen9_init_workarounds(ring);
1082
00e1e623
VS		 1083 return 0;
1084}
1085
a4872ba6 1086static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1087{
78501eac 1088 struct drm_device *dev = ring->dev;
1ec14ad3 1089 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1090 int ret = init_ring_common(ring);
9c33baa6
KZ		 1091 if (ret)
1092 return ret;
a69ffdbf 1093
61a563a2
AG		 1094 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1095 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1096 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1097
1098 /* We need to disable the AsyncFlip performance optimisations in order
1099 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1100 * programmed to '1' on all products.
8693a824 1101 *
b3f797ac 1102 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 1103 */
fbdcb068 1104 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 1105 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1106
f05bb0c7 1107 /* Required for the hardware to program scanline values for waiting */
01fa0302 1108 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1109 if (INTEL_INFO(dev)->gen == 6)
1110 I915_WRITE(GFX_MODE,
aa83e30d 1111 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1112
01fa0302 1113 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1114 if (IS_GEN7(dev))
1115 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1116 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1117 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1118
5e13a0c5 1119 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1120 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1121 * "If this bit is set, STCunit will have LRA as replacement
1122 * policy. [...] This bit must be reset. LRA replacement
1123 * policy is not supported."
1124 */
1125 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1126 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1127 }
1128
6b26c86d
DV		 1129 if (INTEL_INFO(dev)->gen >= 6)
1130 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1131
040d2baa 1132 if (HAS_L3_DPF(dev))
35a85ac6 1133 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1134
7225342a 1135 return init_workarounds_ring(ring);
8187a2b7
ZN		 1136}
1137
a4872ba6 1138static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1139{
b45305fc 1140 struct drm_device *dev = ring->dev;
3e78998a
BW		 1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142
1143 if (dev_priv->semaphore_obj) {
1144 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1145 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1146 dev_priv->semaphore_obj = NULL;
1147 }
b45305fc 1148
9b1136d5 1149 intel_fini_pipe_control(ring);
c6df541c
CW		 1150}
1151
3e78998a
BW		 1152static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1153 unsigned int num_dwords)
1154{
1155#define MBOX_UPDATE_DWORDS 8
1156 struct drm_device *dev = signaller->dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 struct intel_engine_cs *waiter;
1159 int i, ret, num_rings;
1160
1161 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1162 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1163#undef MBOX_UPDATE_DWORDS
1164
1165 ret = intel_ring_begin(signaller, num_dwords);
1166 if (ret)
1167 return ret;
1168
1169 for_each_ring(waiter, dev_priv, i) {
6259cead 1170 u32 seqno;
3e78998a
BW		 1171 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1172 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1173 continue;
1174
6259cead
JH		 1175 seqno = i915_gem_request_get_seqno(
1176 signaller->outstanding_lazy_request);
3e78998a
BW		 1177 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1178 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1179 PIPE_CONTROL_QW_WRITE |
1180 PIPE_CONTROL_FLUSH_ENABLE);
1181 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1182 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1183 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1184 intel_ring_emit(signaller, 0);
1185 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1186 MI_SEMAPHORE_TARGET(waiter->id));
1187 intel_ring_emit(signaller, 0);
1188 }
1189
1190 return 0;
1191}
1192
1193static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1194 unsigned int num_dwords)
1195{
1196#define MBOX_UPDATE_DWORDS 6
1197 struct drm_device *dev = signaller->dev;
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct intel_engine_cs *waiter;
1200 int i, ret, num_rings;
1201
1202 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1203 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1204#undef MBOX_UPDATE_DWORDS
1205
1206 ret = intel_ring_begin(signaller, num_dwords);
1207 if (ret)
1208 return ret;
1209
1210 for_each_ring(waiter, dev_priv, i) {
6259cead 1211 u32 seqno;
3e78998a
BW		 1212 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1213 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1214 continue;
1215
6259cead
JH		 1216 seqno = i915_gem_request_get_seqno(
1217 signaller->outstanding_lazy_request);
3e78998a
BW		 1218 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1219 MI_FLUSH_DW_OP_STOREDW);
1220 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1221 MI_FLUSH_DW_USE_GTT);
1222 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1223 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1224 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1225 MI_SEMAPHORE_TARGET(waiter->id));
1226 intel_ring_emit(signaller, 0);
1227 }
1228
1229 return 0;
1230}
1231
a4872ba6 1232static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1233 unsigned int num_dwords)
1ec14ad3 1234{
024a43e1
BW		 1235 struct drm_device *dev = signaller->dev;
1236 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1237 struct intel_engine_cs *useless;
a1444b79 1238 int i, ret, num_rings;
78325f2d 1239
a1444b79
BW		 1240#define MBOX_UPDATE_DWORDS 3
1241 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1242 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1243#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1244
1245 ret = intel_ring_begin(signaller, num_dwords);
1246 if (ret)
1247 return ret;
024a43e1 1248
78325f2d
BW		 1249 for_each_ring(useless, dev_priv, i) {
1250 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1251 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1252 u32 seqno = i915_gem_request_get_seqno(
1253 signaller->outstanding_lazy_request);
78325f2d
BW		 1254 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1255 intel_ring_emit(signaller, mbox_reg);
6259cead 1256 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1257 }
1258 }
024a43e1 1259
a1444b79
BW		 1260 /* If num_dwords was rounded, make sure the tail pointer is correct */
1261 if (num_rings % 2 == 0)
1262 intel_ring_emit(signaller, MI_NOOP);
1263
024a43e1 1264 return 0;
1ec14ad3
CW		 1265}
1266
c8c99b0f
BW		 1267/**
1268 * gen6_add_request - Update the semaphore mailbox registers
1269 *
1270 * @ring - ring that is adding a request
1271 * @seqno - return seqno stuck into the ring
1272 *
1273 * Update the mailbox registers in the *other* rings with the current seqno.
1274 * This acts like a signal in the canonical semaphore.
1275 */
1ec14ad3 1276static int
a4872ba6 1277gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1278{
024a43e1 1279 int ret;
52ed2325 1280
707d9cf9
BW		 1281 if (ring->semaphore.signal)
1282 ret = ring->semaphore.signal(ring, 4);
1283 else
1284 ret = intel_ring_begin(ring, 4);
1285
1ec14ad3
CW		 1286 if (ret)
1287 return ret;
1288
1ec14ad3
CW		 1289 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1290 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1291 intel_ring_emit(ring,
1292 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1293 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1294 __intel_ring_advance(ring);
1ec14ad3 1295
1ec14ad3
CW		 1296 return 0;
1297}
1298
f72b3435
MK		 1299static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1300 u32 seqno)
1301{
1302 struct drm_i915_private *dev_priv = dev->dev_private;
1303 return dev_priv->last_seqno < seqno;
1304}
1305
c8c99b0f
BW		 1306/**
1307 * intel_ring_sync - sync the waiter to the signaller on seqno
1308 *
1309 * @waiter - ring that is waiting
1310 * @signaller - ring which has, or will signal
1311 * @seqno - seqno which the waiter will block on
1312 */
5ee426ca
BW		 1313
1314static int
1315gen8_ring_sync(struct intel_engine_cs *waiter,
1316 struct intel_engine_cs *signaller,
1317 u32 seqno)
1318{
1319 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1320 int ret;
1321
1322 ret = intel_ring_begin(waiter, 4);
1323 if (ret)
1324 return ret;
1325
1326 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1327 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1328 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1329 MI_SEMAPHORE_SAD_GTE_SDD);
1330 intel_ring_emit(waiter, seqno);
1331 intel_ring_emit(waiter,
1332 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1333 intel_ring_emit(waiter,
1334 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1335 intel_ring_advance(waiter);
1336 return 0;
1337}
1338
c8c99b0f 1339static int
a4872ba6
OM		 1340gen6_ring_sync(struct intel_engine_cs *waiter,
1341 struct intel_engine_cs *signaller,
686cb5f9 1342 u32 seqno)
1ec14ad3 1343{
c8c99b0f
BW		 1344 u32 dw1 = MI_SEMAPHORE_MBOX |
1345 MI_SEMAPHORE_COMPARE |
1346 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1347 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1348 int ret;
1ec14ad3 1349
1500f7ea
BW		 1350 /* Throughout all of the GEM code, seqno passed implies our current
1351 * seqno is >= the last seqno executed. However for hardware the
1352 * comparison is strictly greater than.
1353 */
1354 seqno -= 1;
1355
ebc348b2 1356 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1357
c8c99b0f 1358 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1359 if (ret)
1360 return ret;
1361
f72b3435
MK		 1362 /* If seqno wrap happened, omit the wait with no-ops */
1363 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1364 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1365 intel_ring_emit(waiter, seqno);
1366 intel_ring_emit(waiter, 0);
1367 intel_ring_emit(waiter, MI_NOOP);
1368 } else {
1369 intel_ring_emit(waiter, MI_NOOP);
1370 intel_ring_emit(waiter, MI_NOOP);
1371 intel_ring_emit(waiter, MI_NOOP);
1372 intel_ring_emit(waiter, MI_NOOP);
1373 }
c8c99b0f 1374 intel_ring_advance(waiter);
1ec14ad3
CW		 1375
1376 return 0;
1377}
1378
c6df541c
CW		 1379#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1380do { \
fcbc34e4
KG		 1381 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1382 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1383 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1384 intel_ring_emit(ring__, 0); \
1385 intel_ring_emit(ring__, 0); \
1386} while (0)
1387
1388static int
a4872ba6 1389pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1390{
18393f63 1391 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1392 int ret;
1393
1394 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1395 * incoherent with writes to memory, i.e. completely fubar,
1396 * so we need to use PIPE_NOTIFY instead.
1397 *
1398 * However, we also need to workaround the qword write
1399 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1400 * memory before requesting an interrupt.
1401 */
1402 ret = intel_ring_begin(ring, 32);
1403 if (ret)
1404 return ret;
1405
fcbc34e4 1406 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1407 PIPE_CONTROL_WRITE_FLUSH |
1408 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1409 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1410 intel_ring_emit(ring,
1411 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1412 intel_ring_emit(ring, 0);
1413 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1414 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1415 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1416 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1417 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1418 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1419 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1420 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1421 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1422 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1423 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1424
fcbc34e4 1425 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1426 PIPE_CONTROL_WRITE_FLUSH |
1427 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1428 PIPE_CONTROL_NOTIFY);
0d1aacac 1429 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1430 intel_ring_emit(ring,
1431 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1432 intel_ring_emit(ring, 0);
09246732 1433 __intel_ring_advance(ring);
c6df541c 1434
c6df541c
CW		 1435 return 0;
1436}
1437
4cd53c0c 1438static u32
a4872ba6 1439gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1440{
4cd53c0c
DV		 1441 /* Workaround to force correct ordering between irq and seqno writes on
1442 * ivb (and maybe also on snb) by reading from a CS register (like
1443 * ACTHD) before reading the status page. */
50877445
CW		 1444 if (!lazy_coherency) {
1445 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1446 POSTING_READ(RING_ACTHD(ring->mmio_base));
1447 }
1448
4cd53c0c
DV		 1449 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1450}
1451
8187a2b7 1452static u32
a4872ba6 1453ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1454{
1ec14ad3
CW		 1455 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1456}
1457
b70ec5bf 1458static void
a4872ba6 1459ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1460{
1461 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1462}
1463
c6df541c 1464static u32
a4872ba6 1465pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1466{
0d1aacac 1467 return ring->scratch.cpu_page[0];
c6df541c
CW		 1468}
1469
b70ec5bf 1470static void
a4872ba6 1471pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1472{
0d1aacac 1473 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1474}
1475
e48d8634 1476static bool
a4872ba6 1477gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1478{
1479 struct drm_device *dev = ring->dev;
4640c4ff 1480 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1481 unsigned long flags;
e48d8634 1482
7cd512f1 1483 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1484 return false;
1485
7338aefa 1486 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1487 if (ring->irq_refcount++ == 0)
480c8033 1488 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1489 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1490
1491 return true;
1492}
1493
1494static void
a4872ba6 1495gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1496{
1497 struct drm_device *dev = ring->dev;
4640c4ff 1498 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1499 unsigned long flags;
e48d8634 1500
7338aefa 1501 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1502 if (--ring->irq_refcount == 0)
480c8033 1503 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1504 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1505}
1506
b13c2b96 1507static bool
a4872ba6 1508i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1509{
78501eac 1510 struct drm_device *dev = ring->dev;
4640c4ff 1511 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1512 unsigned long flags;
62fdfeaf 1513
7cd512f1 1514 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1515 return false;
1516
7338aefa 1517 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1518 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1519 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1520 I915_WRITE(IMR, dev_priv->irq_mask);
1521 POSTING_READ(IMR);
1522 }
7338aefa 1523 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1524
1525 return true;
62fdfeaf
EA		 1526}
1527
8187a2b7 1528static void
a4872ba6 1529i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1530{
78501eac 1531 struct drm_device *dev = ring->dev;
4640c4ff 1532 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1533 unsigned long flags;
62fdfeaf 1534
7338aefa 1535 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1536 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1537 dev_priv->irq_mask |= ring->irq_enable_mask;
1538 I915_WRITE(IMR, dev_priv->irq_mask);
1539 POSTING_READ(IMR);
1540 }
7338aefa 1541 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1542}
1543
c2798b19 1544static bool
a4872ba6 1545i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1546{
1547 struct drm_device *dev = ring->dev;
4640c4ff 1548 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1549 unsigned long flags;
c2798b19 1550
7cd512f1 1551 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1552 return false;
1553
7338aefa 1554 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1555 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1556 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1557 I915_WRITE16(IMR, dev_priv->irq_mask);
1558 POSTING_READ16(IMR);
1559 }
7338aefa 1560 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1561
1562 return true;
1563}
1564
1565static void
a4872ba6 1566i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1567{
1568 struct drm_device *dev = ring->dev;
4640c4ff 1569 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1570 unsigned long flags;
c2798b19 1571
7338aefa 1572 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1573 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1574 dev_priv->irq_mask |= ring->irq_enable_mask;
1575 I915_WRITE16(IMR, dev_priv->irq_mask);
1576 POSTING_READ16(IMR);
1577 }
7338aefa 1578 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1579}
1580
b72f3acb 1581static int
a4872ba6 1582bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1583 u32 invalidate_domains,
1584 u32 flush_domains)
d1b851fc 1585{
b72f3acb
CW		 1586 int ret;
1587
b72f3acb
CW		 1588 ret = intel_ring_begin(ring, 2);
1589 if (ret)
1590 return ret;
1591
1592 intel_ring_emit(ring, MI_FLUSH);
1593 intel_ring_emit(ring, MI_NOOP);
1594 intel_ring_advance(ring);
1595 return 0;
d1b851fc
ZN		 1596}
1597
3cce469c 1598static int
a4872ba6 1599i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1600{
3cce469c
CW		 1601 int ret;
1602
1603 ret = intel_ring_begin(ring, 4);
1604 if (ret)
1605 return ret;
6f392d54 1606
3cce469c
CW		 1607 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1608 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1609 intel_ring_emit(ring,
1610 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1611 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1612 __intel_ring_advance(ring);
d1b851fc 1613
3cce469c 1614 return 0;
d1b851fc
ZN		 1615}
1616
0f46832f 1617static bool
a4872ba6 1618gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1619{
1620 struct drm_device *dev = ring->dev;
4640c4ff 1621 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1622 unsigned long flags;
0f46832f 1623
7cd512f1
DV		 1624 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1625 return false;
0f46832f 1626
7338aefa 1627 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1628 if (ring->irq_refcount++ == 0) {
040d2baa 1629 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1630 I915_WRITE_IMR(ring,
1631 ~(ring->irq_enable_mask |
35a85ac6 1632 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1633 else
1634 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1635 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1636 }
7338aefa 1637 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1638
1639 return true;
1640}
1641
1642static void
a4872ba6 1643gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1644{
1645 struct drm_device *dev = ring->dev;
4640c4ff 1646 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1647 unsigned long flags;
0f46832f 1648
7338aefa 1649 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1650 if (--ring->irq_refcount == 0) {
040d2baa 1651 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1652 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1653 else
1654 I915_WRITE_IMR(ring, ~0);
480c8033 1655 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1656 }
7338aefa 1657 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1658}
1659
a19d2933 1660static bool
a4872ba6 1661hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1662{
1663 struct drm_device *dev = ring->dev;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 unsigned long flags;
1666
7cd512f1 1667 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1668 return false;
1669
59cdb63d 1670 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1671 if (ring->irq_refcount++ == 0) {
a19d2933 1672 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1673 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1674 }
59cdb63d 1675 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1676
1677 return true;
1678}
1679
1680static void
a4872ba6 1681hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1682{
1683 struct drm_device *dev = ring->dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 unsigned long flags;
1686
59cdb63d 1687 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1688 if (--ring->irq_refcount == 0) {
a19d2933 1689 I915_WRITE_IMR(ring, ~0);
480c8033 1690 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1691 }
59cdb63d 1692 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1693}
1694
abd58f01 1695static bool
a4872ba6 1696gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1697{
1698 struct drm_device *dev = ring->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 unsigned long flags;
1701
7cd512f1 1702 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1703 return false;
1704
1705 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1706 if (ring->irq_refcount++ == 0) {
1707 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1708 I915_WRITE_IMR(ring,
1709 ~(ring->irq_enable_mask |
1710 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1711 } else {
1712 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1713 }
1714 POSTING_READ(RING_IMR(ring->mmio_base));
1715 }
1716 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1717
1718 return true;
1719}
1720
1721static void
a4872ba6 1722gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1723{
1724 struct drm_device *dev = ring->dev;
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726 unsigned long flags;
1727
1728 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1729 if (--ring->irq_refcount == 0) {
1730 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1731 I915_WRITE_IMR(ring,
1732 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1733 } else {
1734 I915_WRITE_IMR(ring, ~0);
1735 }
1736 POSTING_READ(RING_IMR(ring->mmio_base));
1737 }
1738 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1739}
1740
d1b851fc 1741static int
a4872ba6 1742i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1743 u64 offset, u32 length,
8e004efc 1744 unsigned dispatch_flags)
d1b851fc 1745{
e1f99ce6 1746 int ret;
78501eac 1747
e1f99ce6
CW		 1748 ret = intel_ring_begin(ring, 2);
1749 if (ret)
1750 return ret;
1751
78501eac 1752 intel_ring_emit(ring,
65f56876
CW		 1753 MI_BATCH_BUFFER_START |
1754 MI_BATCH_GTT |
8e004efc
JH		 1755 (dispatch_flags & I915_DISPATCH_SECURE ?
1756 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1757 intel_ring_emit(ring, offset);
78501eac
CW		 1758 intel_ring_advance(ring);
1759
d1b851fc
ZN		 1760 return 0;
1761}
1762
b45305fc
DV		 1763/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1764#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1765#define I830_TLB_ENTRIES (2)
1766#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1767static int
a4872ba6 1768i830_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 1769 u64 offset, u32 len,
1770 unsigned dispatch_flags)
62fdfeaf 1771{
c4d69da1 1772 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1773 int ret;
62fdfeaf 1774
c4d69da1
CW		 1775 ret = intel_ring_begin(ring, 6);
1776 if (ret)
1777 return ret;
62fdfeaf 1778
c4d69da1
CW		 1779 /* Evict the invalid PTE TLBs */
1780 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1781 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1782 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1783 intel_ring_emit(ring, cs_offset);
1784 intel_ring_emit(ring, 0xdeadbeef);
1785 intel_ring_emit(ring, MI_NOOP);
1786 intel_ring_advance(ring);
b45305fc 1787
8e004efc 1788 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1789 if (len > I830_BATCH_LIMIT)
1790 return -ENOSPC;
1791
c4d69da1 1792 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1793 if (ret)
1794 return ret;
c4d69da1
CW		 1795
1796 /* Blit the batch (which has now all relocs applied) to the
1797 * stable batch scratch bo area (so that the CS never
1798 * stumbles over its tlb invalidation bug) ...
1799 */
1800 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1801 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1802 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1803 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1804 intel_ring_emit(ring, 4096);
1805 intel_ring_emit(ring, offset);
c4d69da1 1806
b45305fc 1807 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1808 intel_ring_emit(ring, MI_NOOP);
1809 intel_ring_advance(ring);
b45305fc
DV		 1810
1811 /* ... and execute it. */
c4d69da1 1812 offset = cs_offset;
b45305fc 1813 }
e1f99ce6 1814
c4d69da1
CW		 1815 ret = intel_ring_begin(ring, 4);
1816 if (ret)
1817 return ret;
1818
1819 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1820 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1821 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1822 intel_ring_emit(ring, offset + len - 8);
1823 intel_ring_emit(ring, MI_NOOP);
1824 intel_ring_advance(ring);
1825
fb3256da
DV		 1826 return 0;
1827}
1828
1829static int
a4872ba6 1830i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1831 u64 offset, u32 len,
8e004efc 1832 unsigned dispatch_flags)
fb3256da
DV		 1833{
1834 int ret;
1835
1836 ret = intel_ring_begin(ring, 2);
1837 if (ret)
1838 return ret;
1839
65f56876 1840 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1841 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1842 0 : MI_BATCH_NON_SECURE));
c4e7a414 1843 intel_ring_advance(ring);
62fdfeaf 1844
62fdfeaf
EA		 1845 return 0;
1846}
1847
a4872ba6 1848static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1849{
05394f39 1850 struct drm_i915_gem_object *obj;
62fdfeaf 1851
8187a2b7
ZN		 1852 obj = ring->status_page.obj;
1853 if (obj == NULL)
62fdfeaf 1854 return;
62fdfeaf 1855
9da3da66 1856 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1857 i915_gem_object_ggtt_unpin(obj);
05394f39 1858 drm_gem_object_unreference(&obj->base);
8187a2b7 1859 ring->status_page.obj = NULL;
62fdfeaf
EA		 1860}
1861
a4872ba6 1862static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1863{
05394f39 1864 struct drm_i915_gem_object *obj;
62fdfeaf 1865
e3efda49 1866 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1867 unsigned flags;
e3efda49 1868 int ret;
e4ffd173 1869
e3efda49
CW		 1870 obj = i915_gem_alloc_object(ring->dev, 4096);
1871 if (obj == NULL) {
1872 DRM_ERROR("Failed to allocate status page\n");
1873 return -ENOMEM;
1874 }
62fdfeaf 1875
e3efda49
CW		 1876 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1877 if (ret)
1878 goto err_unref;
1879
1f767e02
CW		 1880 flags = 0;
1881 if (!HAS_LLC(ring->dev))
1882 /* On g33, we cannot place HWS above 256MiB, so
1883 * restrict its pinning to the low mappable arena.
1884 * Though this restriction is not documented for
1885 * gen4, gen5, or byt, they also behave similarly
1886 * and hang if the HWS is placed at the top of the
1887 * GTT. To generalise, it appears that all !llc
1888 * platforms have issues with us placing the HWS
1889 * above the mappable region (even though we never
1890 * actualy map it).
1891 */
1892 flags |= PIN_MAPPABLE;
1893 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1894 if (ret) {
1895err_unref:
1896 drm_gem_object_unreference(&obj->base);
1897 return ret;
1898 }
1899
1900 ring->status_page.obj = obj;
1901 }
62fdfeaf 1902
f343c5f6 1903 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1904 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1905 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1906
8187a2b7
ZN		 1907 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1908 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1909
1910 return 0;
62fdfeaf
EA		 1911}
1912
a4872ba6 1913static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1914{
1915 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1916
1917 if (!dev_priv->status_page_dmah) {
1918 dev_priv->status_page_dmah =
1919 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1920 if (!dev_priv->status_page_dmah)
1921 return -ENOMEM;
1922 }
1923
6b8294a4
CW		 1924 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1925 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1926
1927 return 0;
1928}
1929
7ba717cf 1930void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1931{
2919d291 1932 iounmap(ringbuf->virtual_start);
7ba717cf 1933 ringbuf->virtual_start = NULL;
2919d291 1934 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1935}
1936
1937int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1938 struct intel_ringbuffer *ringbuf)
1939{
1940 struct drm_i915_private *dev_priv = to_i915(dev);
1941 struct drm_i915_gem_object *obj = ringbuf->obj;
1942 int ret;
1943
1944 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1945 if (ret)
1946 return ret;
1947
1948 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1949 if (ret) {
1950 i915_gem_object_ggtt_unpin(obj);
1951 return ret;
1952 }
1953
1954 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1955 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1956 if (ringbuf->virtual_start == NULL) {
1957 i915_gem_object_ggtt_unpin(obj);
1958 return -EINVAL;
1959 }
1960
1961 return 0;
1962}
1963
1964void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1965{
2919d291
OM		 1966 drm_gem_object_unreference(&ringbuf->obj->base);
1967 ringbuf->obj = NULL;
1968}
1969
84c2377f
OM		 1970int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1971 struct intel_ringbuffer *ringbuf)
62fdfeaf 1972{
05394f39 1973 struct drm_i915_gem_object *obj;
62fdfeaf 1974
ebc052e0
CW		 1975 obj = NULL;
1976 if (!HAS_LLC(dev))
93b0a4e0 1977 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1978 if (obj == NULL)
93b0a4e0 1979 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1980 if (obj == NULL)
1981 return -ENOMEM;
8187a2b7 1982
24f3a8cf
AG		 1983 /* mark ring buffers as read-only from GPU side by default */
1984 obj->gt_ro = 1;
1985
93b0a4e0 1986 ringbuf->obj = obj;
e3efda49 1987
7ba717cf 1988 return 0;
e3efda49
CW		 1989}
1990
1991static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1992 struct intel_engine_cs *ring)
e3efda49 1993{
bfc882b4 1994 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1995 int ret;
1996
bfc882b4
DV		 1997 WARN_ON(ring->buffer);
1998
1999 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2000 if (!ringbuf)
2001 return -ENOMEM;
2002 ring->buffer = ringbuf;
8ee14975 2003
e3efda49
CW		 2004 ring->dev = dev;
2005 INIT_LIST_HEAD(&ring->active_list);
2006 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2007 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 2008 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2009 ringbuf->ring = ring;
ebc348b2 2010 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2011
2012 init_waitqueue_head(&ring->irq_queue);
2013
2014 if (I915_NEED_GFX_HWS(dev)) {
2015 ret = init_status_page(ring);
2016 if (ret)
8ee14975 2017 goto error;
e3efda49
CW		 2018 } else {
2019 BUG_ON(ring->id != RCS);
2020 ret = init_phys_status_page(ring);
2021 if (ret)
8ee14975 2022 goto error;
e3efda49
CW		 2023 }
2024
bfc882b4 2025 WARN_ON(ringbuf->obj);
7ba717cf 2026
bfc882b4
DV		 2027 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2028 if (ret) {
2029 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2030 ring->name, ret);
2031 goto error;
2032 }
2033
2034 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2035 if (ret) {
2036 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2037 ring->name, ret);
2038 intel_destroy_ringbuffer_obj(ringbuf);
2039 goto error;
e3efda49 2040 }
62fdfeaf 2041
55249baa
CW		 2042 /* Workaround an erratum on the i830 which causes a hang if
2043 * the TAIL pointer points to within the last 2 cachelines
2044 * of the buffer.
2045 */
93b0a4e0 2046 ringbuf->effective_size = ringbuf->size;
e3efda49 2047 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2048 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2049
44e895a8
BV		 2050 ret = i915_cmd_parser_init_ring(ring);
2051 if (ret)
8ee14975
OM		 2052 goto error;
2053
8ee14975 2054 return 0;
351e3db2 2055
8ee14975
OM		 2056error:
2057 kfree(ringbuf);
2058 ring->buffer = NULL;
2059 return ret;
62fdfeaf
EA		 2060}
2061
a4872ba6 2062void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2063{
6402c330
JH		 2064 struct drm_i915_private *dev_priv;
2065 struct intel_ringbuffer *ringbuf;
33626e6a 2066
93b0a4e0 2067 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2068 return;
2069
6402c330
JH		 2070 dev_priv = to_i915(ring->dev);
2071 ringbuf = ring->buffer;
2072
e3efda49 2073 intel_stop_ring_buffer(ring);
de8f0a50 2074 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2075
7ba717cf 2076 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2077 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2078 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2079
8d19215b
ZN		 2080 if (ring->cleanup)
2081 ring->cleanup(ring);
2082
78501eac 2083 cleanup_status_page(ring);
44e895a8
BV		 2084
2085 i915_cmd_parser_fini_ring(ring);
8ee14975 2086
93b0a4e0 2087 kfree(ringbuf);
8ee14975 2088 ring->buffer = NULL;
62fdfeaf
EA		 2089}
2090
a4872ba6 2091static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 2092{
93b0a4e0 2093 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2094 struct drm_i915_gem_request *request;
a71d8d94
CW		 2095 int ret;
2096
ebd0fd4b
DG		 2097 if (intel_ring_space(ringbuf) >= n)
2098 return 0;
a71d8d94
CW		 2099
2100 list_for_each_entry(request, &ring->request_list, list) {
72f95afa 2101 if (__intel_ring_space(request->postfix, ringbuf->tail,
82e104cc 2102 ringbuf->size) >= n) {
a71d8d94
CW		 2103 break;
2104 }
a71d8d94
CW		 2105 }
2106
a4b3a571 2107 if (&request->list == &ring->request_list)
a71d8d94
CW		 2108 return -ENOSPC;
2109
a4b3a571 2110 ret = i915_wait_request(request);
a71d8d94
CW		 2111 if (ret)
2112 return ret;
2113
1cf0ba14 2114 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 2115
2116 return 0;
2117}
2118
a4872ba6 2119static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 2120{
78501eac 2121 struct drm_device *dev = ring->dev;
cae5852d 2122 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 2123 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 2124 unsigned long end;
a71d8d94 2125 int ret;
c7dca47b 2126
a71d8d94
CW		 2127 ret = intel_ring_wait_request(ring, n);
2128 if (ret != -ENOSPC)
2129 return ret;
2130
09246732
CW		 2131 /* force the tail write in case we have been skipping them */
2132 __intel_ring_advance(ring);
2133
63ed2cb2
DV		 2134 /* With GEM the hangcheck timer should kick us out of the loop,
2135 * leaving it early runs the risk of corrupting GEM state (due
2136 * to running on almost untested codepaths). But on resume
2137 * timers don't work yet, so prevent a complete hang in that
2138 * case by choosing an insanely large timeout. */
2139 end = jiffies + 60 * HZ;
e6bfaf85 2140
ebd0fd4b 2141 ret = 0;
dcfe0506 2142 trace_i915_ring_wait_begin(ring);
8187a2b7 2143 do {
ebd0fd4b
DG		 2144 if (intel_ring_space(ringbuf) >= n)
2145 break;
93b0a4e0 2146 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 2147 if (intel_ring_space(ringbuf) >= n)
dcfe0506 2148 break;
62fdfeaf 2149
e60a0b10 2150 msleep(1);
d6b2c790 2151
dcfe0506
CW		 2152 if (dev_priv->mm.interruptible && signal_pending(current)) {
2153 ret = -ERESTARTSYS;
2154 break;
2155 }
2156
33196ded
DV		 2157 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2158 dev_priv->mm.interruptible);
d6b2c790 2159 if (ret)
dcfe0506
CW		 2160 break;
2161
2162 if (time_after(jiffies, end)) {
2163 ret = -EBUSY;
2164 break;
2165 }
2166 } while (1);
db53a302 2167 trace_i915_ring_wait_end(ring);
dcfe0506 2168 return ret;
8187a2b7 2169}
62fdfeaf 2170
a4872ba6 2171static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2172{
2173 uint32_t __iomem *virt;
93b0a4e0
OM		 2174 struct intel_ringbuffer *ringbuf = ring->buffer;
2175 int rem = ringbuf->size - ringbuf->tail;
3e960501 2176
93b0a4e0 2177 if (ringbuf->space < rem) {
3e960501
CW		 2178 int ret = ring_wait_for_space(ring, rem);
2179 if (ret)
2180 return ret;
2181 }
2182
93b0a4e0 2183 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2184 rem /= 4;
2185 while (rem--)
2186 iowrite32(MI_NOOP, virt++);
2187
93b0a4e0 2188 ringbuf->tail = 0;
ebd0fd4b 2189 intel_ring_update_space(ringbuf);
3e960501
CW		 2190
2191 return 0;
2192}
2193
a4872ba6 2194int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2195{
a4b3a571 2196 struct drm_i915_gem_request *req;
3e960501
CW		 2197 int ret;
2198
2199 /* We need to add any requests required to flush the objects and ring */
6259cead 2200 if (ring->outstanding_lazy_request) {
9400ae5c 2201 ret = i915_add_request(ring);
3e960501
CW		 2202 if (ret)
2203 return ret;
2204 }
2205
2206 /* Wait upon the last request to be completed */
2207 if (list_empty(&ring->request_list))
2208 return 0;
2209
a4b3a571 2210 req = list_entry(ring->request_list.prev,
3e960501 2211 struct drm_i915_gem_request,
a4b3a571 2212 list);
3e960501 2213
a4b3a571 2214 return i915_wait_request(req);
3e960501
CW		 2215}
2216
9d773091 2217static int
6259cead 2218intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2219{
9eba5d4a
JH		 2220 int ret;
2221 struct drm_i915_gem_request *request;
67e2937b 2222 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2223
6259cead 2224 if (ring->outstanding_lazy_request)
9d773091 2225 return 0;
3c0e234c 2226
aaeb1ba0 2227 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2228 if (request == NULL)
2229 return -ENOMEM;
3c0e234c 2230
abfe262a 2231 kref_init(&request->ref);
ff79e857 2232 request->ring = ring;
67e2937b 2233 request->uniq = dev_private->request_uniq++;
abfe262a 2234
6259cead 2235 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2236 if (ret) {
2237 kfree(request);
2238 return ret;
3c0e234c
CW		 2239 }
2240
6259cead 2241 ring->outstanding_lazy_request = request;
9eba5d4a 2242 return 0;
9d773091
CW		 2243}
2244
a4872ba6 2245static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2246 int bytes)
cbcc80df 2247{
93b0a4e0 2248 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2249 int ret;
2250
93b0a4e0 2251 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2252 ret = intel_wrap_ring_buffer(ring);
2253 if (unlikely(ret))
2254 return ret;
2255 }
2256
93b0a4e0 2257 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2258 ret = ring_wait_for_space(ring, bytes);
2259 if (unlikely(ret))
2260 return ret;
2261 }
2262
cbcc80df
MK		 2263 return 0;
2264}
2265
a4872ba6 2266int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2267 int num_dwords)
8187a2b7 2268{
4640c4ff 2269 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2270 int ret;
78501eac 2271
33196ded
DV		 2272 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2273 dev_priv->mm.interruptible);
de2b9985
DV		 2274 if (ret)
2275 return ret;
21dd3734 2276
304d695c
CW		 2277 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2278 if (ret)
2279 return ret;
2280
9d773091 2281 /* Preallocate the olr before touching the ring */
6259cead 2282 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2283 if (ret)
2284 return ret;
2285
ee1b1e5e 2286 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2287 return 0;
8187a2b7 2288}
78501eac 2289
753b1ad4 2290/* Align the ring tail to a cacheline boundary */
a4872ba6 2291int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2292{
ee1b1e5e 2293 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2294 int ret;
2295
2296 if (num_dwords == 0)
2297 return 0;
2298
18393f63 2299 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2300 ret = intel_ring_begin(ring, num_dwords);
2301 if (ret)
2302 return ret;
2303
2304 while (num_dwords--)
2305 intel_ring_emit(ring, MI_NOOP);
2306
2307 intel_ring_advance(ring);
2308
2309 return 0;
2310}
2311
a4872ba6 2312void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2313{
3b2cc8ab
OM		 2314 struct drm_device *dev = ring->dev;
2315 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2316
6259cead 2317 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2318
3b2cc8ab 2319 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2320 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2321 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2322 if (HAS_VEBOX(dev))
5020150b 2323 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2324 }
d97ed339 2325
f7e98ad4 2326 ring->set_seqno(ring, seqno);
92cab734 2327 ring->hangcheck.seqno = seqno;
8187a2b7 2328}
62fdfeaf 2329
a4872ba6 2330static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2331 u32 value)
881f47b6 2332{
4640c4ff 2333 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2334
2335 /* Every tail move must follow the sequence below */
12f55818
CW		 2336
2337 /* Disable notification that the ring is IDLE. The GT
2338 * will then assume that it is busy and bring it out of rc6.
2339 */
0206e353 2340 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2341 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2342
2343 /* Clear the context id. Here be magic! */
2344 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2345
12f55818 2346 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2347 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2348 GEN6_BSD_SLEEP_INDICATOR) == 0,
2349 50))
2350 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2351
12f55818 2352 /* Now that the ring is fully powered up, update the tail */
0206e353 2353 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2354 POSTING_READ(RING_TAIL(ring->mmio_base));
2355
2356 /* Let the ring send IDLE messages to the GT again,
2357 * and so let it sleep to conserve power when idle.
2358 */
0206e353 2359 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2360 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2361}
2362
a4872ba6 2363static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2364 u32 invalidate, u32 flush)
881f47b6 2365{
71a77e07 2366 uint32_t cmd;
b72f3acb
CW		 2367 int ret;
2368
b72f3acb
CW		 2369 ret = intel_ring_begin(ring, 4);
2370 if (ret)
2371 return ret;
2372
71a77e07 2373 cmd = MI_FLUSH_DW;
075b3bba
BW		 2374 if (INTEL_INFO(ring->dev)->gen >= 8)
2375 cmd += 1;
9a289771
JB		 2376 /*
2377 * Bspec vol 1c.5 - video engine command streamer:
2378 * "If ENABLED, all TLBs will be invalidated once the flush
2379 * operation is complete. This bit is only valid when the
2380 * Post-Sync Operation field is a value of 1h or 3h."
2381 */
71a77e07 2382 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2383 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2384 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2385 intel_ring_emit(ring, cmd);
9a289771 2386 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2387 if (INTEL_INFO(ring->dev)->gen >= 8) {
2388 intel_ring_emit(ring, 0); /* upper addr */
2389 intel_ring_emit(ring, 0); /* value */
2390 } else {
2391 intel_ring_emit(ring, 0);
2392 intel_ring_emit(ring, MI_NOOP);
2393 }
b72f3acb
CW		 2394 intel_ring_advance(ring);
2395 return 0;
881f47b6
XH		 2396}
2397
1c7a0623 2398static int
a4872ba6 2399gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2400 u64 offset, u32 len,
8e004efc 2401 unsigned dispatch_flags)
1c7a0623 2402{
8e004efc
JH		 2403 bool ppgtt = USES_PPGTT(ring->dev) &&
2404 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2405 int ret;
2406
2407 ret = intel_ring_begin(ring, 4);
2408 if (ret)
2409 return ret;
2410
2411 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2412 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2413 intel_ring_emit(ring, lower_32_bits(offset));
2414 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2415 intel_ring_emit(ring, MI_NOOP);
2416 intel_ring_advance(ring);
2417
2418 return 0;
2419}
2420
d7d4eedd 2421static int
a4872ba6 2422hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 2423 u64 offset, u32 len,
2424 unsigned dispatch_flags)
d7d4eedd
CW		 2425{
2426 int ret;
2427
2428 ret = intel_ring_begin(ring, 2);
2429 if (ret)
2430 return ret;
2431
2432 intel_ring_emit(ring,
77072258 2433 MI_BATCH_BUFFER_START |
8e004efc 2434 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2435 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2436 /* bit0-7 is the length on GEN6+ */
2437 intel_ring_emit(ring, offset);
2438 intel_ring_advance(ring);
2439
2440 return 0;
2441}
2442
881f47b6 2443static int
a4872ba6 2444gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2445 u64 offset, u32 len,
8e004efc 2446 unsigned dispatch_flags)
881f47b6 2447{
0206e353 2448 int ret;
ab6f8e32 2449
0206e353
AJ		 2450 ret = intel_ring_begin(ring, 2);
2451 if (ret)
2452 return ret;
e1f99ce6 2453
d7d4eedd
CW		 2454 intel_ring_emit(ring,
2455 MI_BATCH_BUFFER_START |
8e004efc
JH		 2456 (dispatch_flags & I915_DISPATCH_SECURE ?
2457 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2458 /* bit0-7 is the length on GEN6+ */
2459 intel_ring_emit(ring, offset);
2460 intel_ring_advance(ring);
ab6f8e32 2461
0206e353 2462 return 0;
881f47b6
XH		 2463}
2464
549f7365
CW		 2465/* Blitter support (SandyBridge+) */
2466
a4872ba6 2467static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2468 u32 invalidate, u32 flush)
8d19215b 2469{
fd3da6c9 2470 struct drm_device *dev = ring->dev;
1d73c2a8 2471 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2472 uint32_t cmd;
b72f3acb
CW		 2473 int ret;
2474
6a233c78 2475 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2476 if (ret)
2477 return ret;
2478
71a77e07 2479 cmd = MI_FLUSH_DW;
075b3bba
BW		 2480 if (INTEL_INFO(ring->dev)->gen >= 8)
2481 cmd += 1;
9a289771
JB		 2482 /*
2483 * Bspec vol 1c.3 - blitter engine command streamer:
2484 * "If ENABLED, all TLBs will be invalidated once the flush
2485 * operation is complete. This bit is only valid when the
2486 * Post-Sync Operation field is a value of 1h or 3h."
2487 */
71a77e07 2488 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2489 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2490 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2491 intel_ring_emit(ring, cmd);
9a289771 2492 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2493 if (INTEL_INFO(ring->dev)->gen >= 8) {
2494 intel_ring_emit(ring, 0); /* upper addr */
2495 intel_ring_emit(ring, 0); /* value */
2496 } else {
2497 intel_ring_emit(ring, 0);
2498 intel_ring_emit(ring, MI_NOOP);
2499 }
b72f3acb 2500 intel_ring_advance(ring);
fd3da6c9 2501
1d73c2a8
RV		 2502 if (!invalidate && flush) {
2503 if (IS_GEN7(dev))
2504 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2505 else if (IS_BROADWELL(dev))
2506 dev_priv->fbc.need_sw_cache_clean = true;
2507 }
fd3da6c9 2508
b72f3acb 2509 return 0;
8d19215b
ZN		 2510}
2511
5c1143bb
XH		 2512int intel_init_render_ring_buffer(struct drm_device *dev)
2513{
4640c4ff 2514 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2515 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2516 struct drm_i915_gem_object *obj;
2517 int ret;
5c1143bb 2518
59465b5f
DV		 2519 ring->name = "render ring";
2520 ring->id = RCS;
2521 ring->mmio_base = RENDER_RING_BASE;
2522
707d9cf9 2523 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2524 if (i915_semaphore_is_enabled(dev)) {
2525 obj = i915_gem_alloc_object(dev, 4096);
2526 if (obj == NULL) {
2527 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2528 i915.semaphores = 0;
2529 } else {
2530 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2531 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2532 if (ret != 0) {
2533 drm_gem_object_unreference(&obj->base);
2534 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2535 i915.semaphores = 0;
2536 } else
2537 dev_priv->semaphore_obj = obj;
2538 }
2539 }
7225342a 2540
8f0e2b9d 2541 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2542 ring->add_request = gen6_add_request;
2543 ring->flush = gen8_render_ring_flush;
2544 ring->irq_get = gen8_ring_get_irq;
2545 ring->irq_put = gen8_ring_put_irq;
2546 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2547 ring->get_seqno = gen6_ring_get_seqno;
2548 ring->set_seqno = ring_set_seqno;
2549 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2550 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2551 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2552 ring->semaphore.signal = gen8_rcs_signal;
2553 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2554 }
2555 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2556 ring->add_request = gen6_add_request;
4772eaeb 2557 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2558 if (INTEL_INFO(dev)->gen == 6)
b3111509 2559 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2560 ring->irq_get = gen6_ring_get_irq;
2561 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2562 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2563 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2564 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2565 if (i915_semaphore_is_enabled(dev)) {
2566 ring->semaphore.sync_to = gen6_ring_sync;
2567 ring->semaphore.signal = gen6_signal;
2568 /*
2569 * The current semaphore is only applied on pre-gen8
2570 * platform. And there is no VCS2 ring on the pre-gen8
2571 * platform. So the semaphore between RCS and VCS2 is
2572 * initialized as INVALID. Gen8 will initialize the
2573 * sema between VCS2 and RCS later.
2574 */
2575 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2576 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2577 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2578 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2579 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2580 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2581 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2582 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2583 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2584 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2585 }
c6df541c
CW		 2586 } else if (IS_GEN5(dev)) {
2587 ring->add_request = pc_render_add_request;
46f0f8d1 2588 ring->flush = gen4_render_ring_flush;
c6df541c 2589 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2590 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2591 ring->irq_get = gen5_ring_get_irq;
2592 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2593 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2594 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2595 } else {
8620a3a9 2596 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2597 if (INTEL_INFO(dev)->gen < 4)
2598 ring->flush = gen2_render_ring_flush;
2599 else
2600 ring->flush = gen4_render_ring_flush;
59465b5f 2601 ring->get_seqno = ring_get_seqno;
b70ec5bf 2602 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2603 if (IS_GEN2(dev)) {
2604 ring->irq_get = i8xx_ring_get_irq;
2605 ring->irq_put = i8xx_ring_put_irq;
2606 } else {
2607 ring->irq_get = i9xx_ring_get_irq;
2608 ring->irq_put = i9xx_ring_put_irq;
2609 }
e3670319 2610 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2611 }
59465b5f 2612 ring->write_tail = ring_write_tail;
707d9cf9 2613
d7d4eedd
CW		 2614 if (IS_HASWELL(dev))
2615 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2616 else if (IS_GEN8(dev))
2617 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2618 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2619 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2620 else if (INTEL_INFO(dev)->gen >= 4)
2621 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2622 else if (IS_I830(dev) || IS_845G(dev))
2623 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2624 else
2625 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2626 ring->init_hw = init_render_ring;
59465b5f
DV		 2627 ring->cleanup = render_ring_cleanup;
2628
b45305fc
DV		 2629 /* Workaround batchbuffer to combat CS tlb bug. */
2630 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2631 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2632 if (obj == NULL) {
2633 DRM_ERROR("Failed to allocate batch bo\n");
2634 return -ENOMEM;
2635 }
2636
be1fa129 2637 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2638 if (ret != 0) {
2639 drm_gem_object_unreference(&obj->base);
2640 DRM_ERROR("Failed to ping batch bo\n");
2641 return ret;
2642 }
2643
0d1aacac
CW		 2644 ring->scratch.obj = obj;
2645 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2646 }
2647
99be1dfe
DV		 2648 ret = intel_init_ring_buffer(dev, ring);
2649 if (ret)
2650 return ret;
2651
2652 if (INTEL_INFO(dev)->gen >= 5) {
2653 ret = intel_init_pipe_control(ring);
2654 if (ret)
2655 return ret;
2656 }
2657
2658 return 0;
5c1143bb
XH		 2659}
2660
2661int intel_init_bsd_ring_buffer(struct drm_device *dev)
2662{
4640c4ff 2663 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2664 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2665
58fa3835
DV		 2666 ring->name = "bsd ring";
2667 ring->id = VCS;
2668
0fd2c201 2669 ring->write_tail = ring_write_tail;
780f18c8 2670 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2671 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2672 /* gen6 bsd needs a special wa for tail updates */
2673 if (IS_GEN6(dev))
2674 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2675 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2676 ring->add_request = gen6_add_request;
2677 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2678 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2679 if (INTEL_INFO(dev)->gen >= 8) {
2680 ring->irq_enable_mask =
2681 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2682 ring->irq_get = gen8_ring_get_irq;
2683 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2684 ring->dispatch_execbuffer =
2685 gen8_ring_dispatch_execbuffer;
707d9cf9 2686 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2687 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2688 ring->semaphore.signal = gen8_xcs_signal;
2689 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2690 }
abd58f01
BW		 2691 } else {
2692 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2693 ring->irq_get = gen6_ring_get_irq;
2694 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2695 ring->dispatch_execbuffer =
2696 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2697 if (i915_semaphore_is_enabled(dev)) {
2698 ring->semaphore.sync_to = gen6_ring_sync;
2699 ring->semaphore.signal = gen6_signal;
2700 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2701 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2702 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2703 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2704 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2705 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2706 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2707 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2708 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2709 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2710 }
abd58f01 2711 }
58fa3835
DV		 2712 } else {
2713 ring->mmio_base = BSD_RING_BASE;
58fa3835 2714 ring->flush = bsd_ring_flush;
8620a3a9 2715 ring->add_request = i9xx_add_request;
58fa3835 2716 ring->get_seqno = ring_get_seqno;
b70ec5bf 2717 ring->set_seqno = ring_set_seqno;
e48d8634 2718 if (IS_GEN5(dev)) {
cc609d5d 2719 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2720 ring->irq_get = gen5_ring_get_irq;
2721 ring->irq_put = gen5_ring_put_irq;
2722 } else {
e3670319 2723 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2724 ring->irq_get = i9xx_ring_get_irq;
2725 ring->irq_put = i9xx_ring_put_irq;
2726 }
fb3256da 2727 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2728 }
ecfe00d8 2729 ring->init_hw = init_ring_common;
58fa3835 2730
1ec14ad3 2731 return intel_init_ring_buffer(dev, ring);
5c1143bb 2732}
549f7365 2733
845f74a7 2734/**
62659920 2735 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2736 */
2737int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2738{
2739 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2740 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2741
f7b64236 2742 ring->name = "bsd2 ring";
845f74a7
ZY		 2743 ring->id = VCS2;
2744
2745 ring->write_tail = ring_write_tail;
2746 ring->mmio_base = GEN8_BSD2_RING_BASE;
2747 ring->flush = gen6_bsd_ring_flush;
2748 ring->add_request = gen6_add_request;
2749 ring->get_seqno = gen6_ring_get_seqno;
2750 ring->set_seqno = ring_set_seqno;
2751 ring->irq_enable_mask =
2752 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2753 ring->irq_get = gen8_ring_get_irq;
2754 ring->irq_put = gen8_ring_put_irq;
2755 ring->dispatch_execbuffer =
2756 gen8_ring_dispatch_execbuffer;
3e78998a 2757 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2758 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2759 ring->semaphore.signal = gen8_xcs_signal;
2760 GEN8_RING_SEMAPHORE_INIT;
2761 }
ecfe00d8 2762 ring->init_hw = init_ring_common;
845f74a7
ZY		 2763
2764 return intel_init_ring_buffer(dev, ring);
2765}
2766
549f7365
CW		 2767int intel_init_blt_ring_buffer(struct drm_device *dev)
2768{
4640c4ff 2769 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2770 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2771
3535d9dd
DV		 2772 ring->name = "blitter ring";
2773 ring->id = BCS;
2774
2775 ring->mmio_base = BLT_RING_BASE;
2776 ring->write_tail = ring_write_tail;
ea251324 2777 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2778 ring->add_request = gen6_add_request;
2779 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2780 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2781 if (INTEL_INFO(dev)->gen >= 8) {
2782 ring->irq_enable_mask =
2783 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2784 ring->irq_get = gen8_ring_get_irq;
2785 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2786 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2787 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2788 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2789 ring->semaphore.signal = gen8_xcs_signal;
2790 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2791 }
abd58f01
BW		 2792 } else {
2793 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2794 ring->irq_get = gen6_ring_get_irq;
2795 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2796 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2797 if (i915_semaphore_is_enabled(dev)) {
2798 ring->semaphore.signal = gen6_signal;
2799 ring->semaphore.sync_to = gen6_ring_sync;
2800 /*
2801 * The current semaphore is only applied on pre-gen8
2802 * platform. And there is no VCS2 ring on the pre-gen8
2803 * platform. So the semaphore between BCS and VCS2 is
2804 * initialized as INVALID. Gen8 will initialize the
2805 * sema between BCS and VCS2 later.
2806 */
2807 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2808 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2809 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2810 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2811 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2812 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2813 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2814 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2815 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2816 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2817 }
abd58f01 2818 }
ecfe00d8 2819 ring->init_hw = init_ring_common;
549f7365 2820
1ec14ad3 2821 return intel_init_ring_buffer(dev, ring);
549f7365 2822}
a7b9761d 2823
9a8a2213
BW		 2824int intel_init_vebox_ring_buffer(struct drm_device *dev)
2825{
4640c4ff 2826 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2827 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2828
2829 ring->name = "video enhancement ring";
2830 ring->id = VECS;
2831
2832 ring->mmio_base = VEBOX_RING_BASE;
2833 ring->write_tail = ring_write_tail;
2834 ring->flush = gen6_ring_flush;
2835 ring->add_request = gen6_add_request;
2836 ring->get_seqno = gen6_ring_get_seqno;
2837 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2838
2839 if (INTEL_INFO(dev)->gen >= 8) {
2840 ring->irq_enable_mask =
40c499f9 2841 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2842 ring->irq_get = gen8_ring_get_irq;
2843 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2844 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2845 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2846 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2847 ring->semaphore.signal = gen8_xcs_signal;
2848 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2849 }
abd58f01
BW		 2850 } else {
2851 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2852 ring->irq_get = hsw_vebox_get_irq;
2853 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2854 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2855 if (i915_semaphore_is_enabled(dev)) {
2856 ring->semaphore.sync_to = gen6_ring_sync;
2857 ring->semaphore.signal = gen6_signal;
2858 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2859 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2860 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2861 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2862 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2863 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2864 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2865 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2866 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2867 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2868 }
abd58f01 2869 }
ecfe00d8 2870 ring->init_hw = init_ring_common;
9a8a2213
BW		 2871
2872 return intel_init_ring_buffer(dev, ring);
2873}
2874
a7b9761d 2875int
a4872ba6 2876intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2877{
2878 int ret;
2879
2880 if (!ring->gpu_caches_dirty)
2881 return 0;
2882
2883 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2884 if (ret)
2885 return ret;
2886
2887 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2888
2889 ring->gpu_caches_dirty = false;
2890 return 0;
2891}
2892
2893int
a4872ba6 2894intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2895{
2896 uint32_t flush_domains;
2897 int ret;
2898
2899 flush_domains = 0;
2900 if (ring->gpu_caches_dirty)
2901 flush_domains = I915_GEM_GPU_DOMAINS;
2902
2903 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2904 if (ret)
2905 return ret;
2906
2907 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2908
2909 ring->gpu_caches_dirty = false;
2910 return 0;
2911}
e3efda49
CW		 2912
2913void
a4872ba6 2914intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2915{
2916 int ret;
2917
2918 if (!intel_ring_initialized(ring))
2919 return;
2920
2921 ret = intel_ring_idle(ring);
2922 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2923 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2924 ring->name, ret);
2925
2926 stop_ring(ring);
2927}
Linux kernel - Deliverables
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