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drm/i915: remove redundant #ifdef CONFIG_COMPAT
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
1cf0ba14 55 int space = head - (tail + I915_RING_FREE_SPACE);
c7dca47b 56 if (space < 0)
1cf0ba14 57 space += size;
c7dca47b
CW		 58 return space;
59}
60
82e104cc 61int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 62{
82e104cc
OM		 63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
1cf0ba14
CW		 65}
66
82e104cc 67bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 68{
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71}
09246732 72
a4872ba6 73void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 74{
93b0a4e0
OM		 75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 77 if (intel_ring_stopped(ring))
09246732 78 return;
93b0a4e0 79 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 80}
81
b72f3acb 82static int
a4872ba6 83gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 84 u32 invalidate_domains,
85 u32 flush_domains)
86{
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
31b14c9f 91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106}
107
108static int
a4872ba6 109gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 110 u32 invalidate_domains,
111 u32 flush_domains)
62fdfeaf 112{
78501eac 113 struct drm_device *dev = ring->dev;
6f392d54 114 u32 cmd;
b72f3acb 115 int ret;
6f392d54 116
36d527de
CW		 117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 147 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
62fdfeaf 150
36d527de
CW		 151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
70eac33e 154
36d527de
CW		 155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
b72f3acb 158
36d527de
CW		 159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
b72f3acb
CW		 162
163 return 0;
8187a2b7
ZN		 164}
165
8d315287
JB		 166/**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203static int
a4872ba6 204intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 205{
18393f63 206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236}
237
238static int
a4872ba6 239gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 240 u32 invalidate_domains, u32 flush_domains)
241{
242 u32 flags = 0;
18393f63 243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 244 int ret;
245
b3111509
PZ		 246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
8d315287
JB		 251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
7d54a904
CW		 255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
97f209bc 262 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
3ac78313 274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 275 }
8d315287 276
6c6cf5aa 277 ret = intel_ring_begin(ring, 4);
8d315287
JB		 278 if (ret)
279 return ret;
280
6c6cf5aa 281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 284 intel_ring_emit(ring, 0);
8d315287
JB		 285 intel_ring_advance(ring);
286
287 return 0;
288}
289
f3987631 290static int
a4872ba6 291gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 292{
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307}
308
a4872ba6 309static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 310{
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
37c1d94f 316 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 317 if (ret)
318 return ret;
fd3da6c9
RV		 319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
37c1d94f
VS		 323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330}
331
4772eaeb 332static int
a4872ba6 333gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 334 u32 invalidate_domains, u32 flush_domains)
335{
336 u32 flags = 0;
18393f63 337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 338 int ret;
339
f3987631
PZ		 340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
4772eaeb
PZ		 350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
365 /*
366 * TLB invalidate requires a post-sync write.
367 */
368 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 369 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631
PZ		 370
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 375 }
376
377 ret = intel_ring_begin(ring, 4);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring, flags);
b9e1faa7 383 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 384 intel_ring_emit(ring, 0);
385 intel_ring_advance(ring);
386
9688ecad 387 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 388 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
389
4772eaeb
PZ		 390 return 0;
391}
392
884ceace
KG		 393static int
394gen8_emit_pipe_control(struct intel_engine_cs *ring,
395 u32 flags, u32 scratch_addr)
396{
397 int ret;
398
399 ret = intel_ring_begin(ring, 6);
400 if (ret)
401 return ret;
402
403 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring, flags);
405 intel_ring_emit(ring, scratch_addr);
406 intel_ring_emit(ring, 0);
407 intel_ring_emit(ring, 0);
408 intel_ring_emit(ring, 0);
409 intel_ring_advance(ring);
410
411 return 0;
412}
413
a5f3d68e 414static int
a4872ba6 415gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 416 u32 invalidate_domains, u32 flush_domains)
417{
418 u32 flags = 0;
18393f63 419 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 420 int ret;
a5f3d68e
BW		 421
422 flags |= PIPE_CONTROL_CS_STALL;
423
424 if (flush_domains) {
425 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
426 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
427 }
428 if (invalidate_domains) {
429 flags |= PIPE_CONTROL_TLB_INVALIDATE;
430 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_QW_WRITE;
436 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 437
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret = gen8_emit_pipe_control(ring,
440 PIPE_CONTROL_CS_STALL |
441 PIPE_CONTROL_STALL_AT_SCOREBOARD,
442 0);
443 if (ret)
444 return ret;
a5f3d68e
BW		 445 }
446
c5ad011d
RV		 447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
448 if (ret)
449 return ret;
450
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
453
454 return 0;
a5f3d68e
BW		 455}
456
a4872ba6 457static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 458 u32 value)
d46eefa2 459{
4640c4ff 460 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 461 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 462}
463
a4872ba6 464u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 465{
4640c4ff 466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 467 u64 acthd;
8187a2b7 468
50877445
CW		 469 if (INTEL_INFO(ring->dev)->gen >= 8)
470 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
471 RING_ACTHD_UDW(ring->mmio_base));
472 else if (INTEL_INFO(ring->dev)->gen >= 4)
473 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
474 else
475 acthd = I915_READ(ACTHD);
476
477 return acthd;
8187a2b7
ZN		 478}
479
a4872ba6 480static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 481{
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 addr;
484
485 addr = dev_priv->status_page_dmah->busaddr;
486 if (INTEL_INFO(ring->dev)->gen >= 4)
487 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
488 I915_WRITE(HWS_PGA, addr);
489}
490
a4872ba6 491static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 492{
9991ae78 493 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 494
9991ae78
CW		 495 if (!IS_GEN2(ring->dev)) {
496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 497 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
502 */
503 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
504 return false;
9991ae78
CW		 505 }
506 }
b7884eb4 507
7f2ab699 508 I915_WRITE_CTL(ring, 0);
570ef608 509 I915_WRITE_HEAD(ring, 0);
78501eac 510 ring->write_tail(ring, 0);
8187a2b7 511
9991ae78
CW		 512 if (!IS_GEN2(ring->dev)) {
513 (void)I915_READ_CTL(ring);
514 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
515 }
a51435a3 516
9991ae78
CW		 517 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
518}
8187a2b7 519
a4872ba6 520static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 521{
522 struct drm_device *dev = ring->dev;
523 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 524 struct intel_ringbuffer *ringbuf = ring->buffer;
525 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 526 int ret = 0;
527
528 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
529
530 if (!stop_ring(ring)) {
531 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
534 ring->name,
535 I915_READ_CTL(ring),
536 I915_READ_HEAD(ring),
537 I915_READ_TAIL(ring),
538 I915_READ_START(ring));
8187a2b7 539
9991ae78 540 if (!stop_ring(ring)) {
6fd0d56e
CW		 541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
543 ring->name,
544 I915_READ_CTL(ring),
545 I915_READ_HEAD(ring),
546 I915_READ_TAIL(ring),
547 I915_READ_START(ring));
9991ae78
CW		 548 ret = -EIO;
549 goto out;
6fd0d56e 550 }
8187a2b7
ZN		 551 }
552
9991ae78
CW		 553 if (I915_NEED_GFX_HWS(dev))
554 intel_ring_setup_status_page(ring);
555 else
556 ring_setup_phys_status_page(ring);
557
ece4a17d
JK		 558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring);
560
0d8957c8
DV		 561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
f343c5f6 565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 566
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
573
7f2ab699 574 I915_WRITE_CTL(ring,
93b0a4e0 575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 576 | RING_VALID);
8187a2b7 577
8187a2b7 578 /* If the head is still not zero, the ring is dead */
f01db988 579 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 580 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 581 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 582 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
584 ring->name,
585 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
586 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
587 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 588 ret = -EIO;
589 goto out;
8187a2b7
ZN		 590 }
591
78501eac
CW		 592 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
593 i915_kernel_lost_context(ring->dev);
8187a2b7 594 else {
93b0a4e0
OM		 595 ringbuf->head = I915_READ_HEAD(ring);
596 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
82e104cc 597 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 598 ringbuf->last_retired_head = -1;
8187a2b7 599 }
1ec14ad3 600
50f018df
CW		 601 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
602
b7884eb4 603out:
c8d9a590 604 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 605
606 return ret;
8187a2b7
ZN		 607}
608
9b1136d5
OM		 609void
610intel_fini_pipe_control(struct intel_engine_cs *ring)
611{
612 struct drm_device *dev = ring->dev;
613
614 if (ring->scratch.obj == NULL)
615 return;
616
617 if (INTEL_INFO(dev)->gen >= 5) {
618 kunmap(sg_page(ring->scratch.obj->pages->sgl));
619 i915_gem_object_ggtt_unpin(ring->scratch.obj);
620 }
621
622 drm_gem_object_unreference(&ring->scratch.obj->base);
623 ring->scratch.obj = NULL;
624}
625
626int
627intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 628{
c6df541c
CW		 629 int ret;
630
0d1aacac 631 if (ring->scratch.obj)
c6df541c
CW		 632 return 0;
633
0d1aacac
CW		 634 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
635 if (ring->scratch.obj == NULL) {
c6df541c
CW		 636 DRM_ERROR("Failed to allocate seqno page\n");
637 ret = -ENOMEM;
638 goto err;
639 }
e4ffd173 640
a9cc726c
DV		 641 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
642 if (ret)
643 goto err_unref;
c6df541c 644
1ec9e26d 645 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 646 if (ret)
647 goto err_unref;
648
0d1aacac
CW		 649 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
650 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
651 if (ring->scratch.cpu_page == NULL) {
56b085a0 652 ret = -ENOMEM;
c6df541c 653 goto err_unpin;
56b085a0 654 }
c6df541c 655
2b1086cc 656 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 657 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 658 return 0;
659
660err_unpin:
d7f46fc4 661 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 662err_unref:
0d1aacac 663 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 664err:
c6df541c
CW		 665 return ret;
666}
667
86d7f238
AS		 668static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
669 u32 addr, u32 value)
670{
888b5995
AS		 671 struct drm_device *dev = ring->dev;
672 struct drm_i915_private *dev_priv = dev->dev_private;
673
04ad2dc7 674 if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
888b5995
AS		 675 return;
676
86d7f238
AS		 677 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
678 intel_ring_emit(ring, addr);
679 intel_ring_emit(ring, value);
888b5995
AS		 680
681 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
b07ba1dc 682 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
888b5995
AS		 683 /* value is updated with the status of remaining bits of this
684 * register when it is read from debugfs file
685 */
686 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
687 dev_priv->num_wa_regs++;
688
689 return;
86d7f238
AS		 690}
691
00e1e623 692static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238
AS		 693{
694 int ret;
888b5995
AS		 695 struct drm_device *dev = ring->dev;
696 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238
AS		 697
698 /*
699 * workarounds applied in this fn are part of register state context,
700 * they need to be re-initialized followed by gpu reset, suspend/resume,
701 * module reload.
702 */
888b5995
AS		 703 dev_priv->num_wa_regs = 0;
704 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
86d7f238
AS		 705
706 /*
707 * update the number of dwords required based on the
708 * actual number of workarounds applied
709 */
d37cf5f7 710 ret = intel_ring_begin(ring, 18);
86d7f238
AS		 711 if (ret)
712 return ret;
713
714 /* WaDisablePartialInstShootdown:bdw */
101b376d 715 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
86d7f238
AS		 716 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
717 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
718 | STALL_DOP_GATING_DISABLE));
719
101b376d 720 /* WaDisableDopClockGating:bdw */
86d7f238
AS		 721 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
722 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
723
86d7f238 724 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
d37cf5f7 725 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
86d7f238
AS		 726
727 /* Use Force Non-Coherent whenever executing a 3D context. This is a
728 * workaround for for a possible hang in the unlikely event a TLB
729 * invalidation occurs during a PSD flush.
730 */
da09654d 731 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
86d7f238 732 intel_ring_emit_wa(ring, HDC_CHICKEN0,
da09654d
RV		 733 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT |
734 (IS_BDW_GT3(dev) ?
735 HDC_FENCE_DEST_SLM_DISABLE : 0)
736 ));
86d7f238
AS		 737
738 /* Wa4x4STCOptimizationDisable:bdw */
739 intel_ring_emit_wa(ring, CACHE_MODE_1,
740 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
741
742 /*
743 * BSpec recommends 8x4 when MSAA is used,
744 * however in practice 16x4 seems fastest.
745 *
746 * Note that PS/WM thread counts depend on the WIZ hashing
747 * disable bit, which we don't touch here, but it's good
748 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
749 */
750 intel_ring_emit_wa(ring, GEN7_GT_MODE,
751 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
752
753 intel_ring_advance(ring);
754
888b5995
AS		 755 DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
756 dev_priv->num_wa_regs);
757
86d7f238
AS		 758 return 0;
759}
760
00e1e623
VS		 761static int chv_init_workarounds(struct intel_engine_cs *ring)
762{
763 int ret;
764 struct drm_device *dev = ring->dev;
765 struct drm_i915_private *dev_priv = dev->dev_private;
766
767 /*
768 * workarounds applied in this fn are part of register state context,
769 * they need to be re-initialized followed by gpu reset, suspend/resume,
770 * module reload.
771 */
772 dev_priv->num_wa_regs = 0;
773 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
774
775 ret = intel_ring_begin(ring, 12);
776 if (ret)
777 return ret;
778
779 /* WaDisablePartialInstShootdown:chv */
780 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
781 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
782
783 /* WaDisableThreadStallDopClockGating:chv */
784 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
785 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
786
787 /* WaDisableDopClockGating:chv (pre-production hw) */
788 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
789 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
790
791 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
792 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
793 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
794
795 intel_ring_advance(ring);
796
797 return 0;
798}
799
a4872ba6 800static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 801{
78501eac 802 struct drm_device *dev = ring->dev;
1ec14ad3 803 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 804 int ret = init_ring_common(ring);
9c33baa6
KZ		 805 if (ret)
806 return ret;
a69ffdbf 807
61a563a2
AG		 808 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
809 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 810 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 811
812 /* We need to disable the AsyncFlip performance optimisations in order
813 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
814 * programmed to '1' on all products.
8693a824 815 *
b3f797ac 816 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 817 */
fbdcb068 818 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 819 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
820
f05bb0c7 821 /* Required for the hardware to program scanline values for waiting */
01fa0302 822 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 823 if (INTEL_INFO(dev)->gen == 6)
824 I915_WRITE(GFX_MODE,
aa83e30d 825 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 826
01fa0302 827 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 828 if (IS_GEN7(dev))
829 I915_WRITE(GFX_MODE_GEN7,
01fa0302 830 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 831 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 832
8d315287 833 if (INTEL_INFO(dev)->gen >= 5) {
9b1136d5 834 ret = intel_init_pipe_control(ring);
c6df541c
CW		 835 if (ret)
836 return ret;
837 }
838
5e13a0c5 839 if (IS_GEN6(dev)) {
3a69ddd6
KG		 840 /* From the Sandybridge PRM, volume 1 part 3, page 24:
841 * "If this bit is set, STCunit will have LRA as replacement
842 * policy. [...] This bit must be reset. LRA replacement
843 * policy is not supported."
844 */
845 I915_WRITE(CACHE_MODE_0,
5e13a0c5 846 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 847 }
848
6b26c86d
DV		 849 if (INTEL_INFO(dev)->gen >= 6)
850 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 851
040d2baa 852 if (HAS_L3_DPF(dev))
35a85ac6 853 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 854
8187a2b7
ZN		 855 return ret;
856}
857
a4872ba6 858static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 859{
b45305fc 860 struct drm_device *dev = ring->dev;
3e78998a
BW		 861 struct drm_i915_private *dev_priv = dev->dev_private;
862
863 if (dev_priv->semaphore_obj) {
864 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
865 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
866 dev_priv->semaphore_obj = NULL;
867 }
b45305fc 868
9b1136d5 869 intel_fini_pipe_control(ring);
c6df541c
CW		 870}
871
3e78998a
BW		 872static int gen8_rcs_signal(struct intel_engine_cs *signaller,
873 unsigned int num_dwords)
874{
875#define MBOX_UPDATE_DWORDS 8
876 struct drm_device *dev = signaller->dev;
877 struct drm_i915_private *dev_priv = dev->dev_private;
878 struct intel_engine_cs *waiter;
879 int i, ret, num_rings;
880
881 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
882 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
883#undef MBOX_UPDATE_DWORDS
884
885 ret = intel_ring_begin(signaller, num_dwords);
886 if (ret)
887 return ret;
888
889 for_each_ring(waiter, dev_priv, i) {
890 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
891 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
892 continue;
893
894 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
895 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
896 PIPE_CONTROL_QW_WRITE |
897 PIPE_CONTROL_FLUSH_ENABLE);
898 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
899 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
900 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
901 intel_ring_emit(signaller, 0);
902 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
903 MI_SEMAPHORE_TARGET(waiter->id));
904 intel_ring_emit(signaller, 0);
905 }
906
907 return 0;
908}
909
910static int gen8_xcs_signal(struct intel_engine_cs *signaller,
911 unsigned int num_dwords)
912{
913#define MBOX_UPDATE_DWORDS 6
914 struct drm_device *dev = signaller->dev;
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 struct intel_engine_cs *waiter;
917 int i, ret, num_rings;
918
919 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
920 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
921#undef MBOX_UPDATE_DWORDS
922
923 ret = intel_ring_begin(signaller, num_dwords);
924 if (ret)
925 return ret;
926
927 for_each_ring(waiter, dev_priv, i) {
928 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
929 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
930 continue;
931
932 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
933 MI_FLUSH_DW_OP_STOREDW);
934 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
935 MI_FLUSH_DW_USE_GTT);
936 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
937 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
938 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
939 MI_SEMAPHORE_TARGET(waiter->id));
940 intel_ring_emit(signaller, 0);
941 }
942
943 return 0;
944}
945
a4872ba6 946static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 947 unsigned int num_dwords)
1ec14ad3 948{
024a43e1
BW		 949 struct drm_device *dev = signaller->dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 951 struct intel_engine_cs *useless;
a1444b79 952 int i, ret, num_rings;
78325f2d 953
a1444b79
BW		 954#define MBOX_UPDATE_DWORDS 3
955 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
956 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
957#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 958
959 ret = intel_ring_begin(signaller, num_dwords);
960 if (ret)
961 return ret;
024a43e1 962
78325f2d
BW		 963 for_each_ring(useless, dev_priv, i) {
964 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
965 if (mbox_reg != GEN6_NOSYNC) {
966 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
967 intel_ring_emit(signaller, mbox_reg);
968 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
78325f2d
BW		 969 }
970 }
024a43e1 971
a1444b79
BW		 972 /* If num_dwords was rounded, make sure the tail pointer is correct */
973 if (num_rings % 2 == 0)
974 intel_ring_emit(signaller, MI_NOOP);
975
024a43e1 976 return 0;
1ec14ad3
CW		 977}
978
c8c99b0f
BW		 979/**
980 * gen6_add_request - Update the semaphore mailbox registers
981 *
982 * @ring - ring that is adding a request
983 * @seqno - return seqno stuck into the ring
984 *
985 * Update the mailbox registers in the *other* rings with the current seqno.
986 * This acts like a signal in the canonical semaphore.
987 */
1ec14ad3 988static int
a4872ba6 989gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 990{
024a43e1 991 int ret;
52ed2325 992
707d9cf9
BW		 993 if (ring->semaphore.signal)
994 ret = ring->semaphore.signal(ring, 4);
995 else
996 ret = intel_ring_begin(ring, 4);
997
1ec14ad3
CW		 998 if (ret)
999 return ret;
1000
1ec14ad3
CW		 1001 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1002 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1823521d 1003 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1ec14ad3 1004 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1005 __intel_ring_advance(ring);
1ec14ad3 1006
1ec14ad3
CW		 1007 return 0;
1008}
1009
f72b3435
MK		 1010static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1011 u32 seqno)
1012{
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 return dev_priv->last_seqno < seqno;
1015}
1016
c8c99b0f
BW		 1017/**
1018 * intel_ring_sync - sync the waiter to the signaller on seqno
1019 *
1020 * @waiter - ring that is waiting
1021 * @signaller - ring which has, or will signal
1022 * @seqno - seqno which the waiter will block on
1023 */
5ee426ca
BW		 1024
1025static int
1026gen8_ring_sync(struct intel_engine_cs *waiter,
1027 struct intel_engine_cs *signaller,
1028 u32 seqno)
1029{
1030 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1031 int ret;
1032
1033 ret = intel_ring_begin(waiter, 4);
1034 if (ret)
1035 return ret;
1036
1037 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1038 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1039 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1040 MI_SEMAPHORE_SAD_GTE_SDD);
1041 intel_ring_emit(waiter, seqno);
1042 intel_ring_emit(waiter,
1043 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1044 intel_ring_emit(waiter,
1045 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1046 intel_ring_advance(waiter);
1047 return 0;
1048}
1049
c8c99b0f 1050static int
a4872ba6
OM		 1051gen6_ring_sync(struct intel_engine_cs *waiter,
1052 struct intel_engine_cs *signaller,
686cb5f9 1053 u32 seqno)
1ec14ad3 1054{
c8c99b0f
BW		 1055 u32 dw1 = MI_SEMAPHORE_MBOX |
1056 MI_SEMAPHORE_COMPARE |
1057 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1058 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1059 int ret;
1ec14ad3 1060
1500f7ea
BW		 1061 /* Throughout all of the GEM code, seqno passed implies our current
1062 * seqno is >= the last seqno executed. However for hardware the
1063 * comparison is strictly greater than.
1064 */
1065 seqno -= 1;
1066
ebc348b2 1067 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1068
c8c99b0f 1069 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1070 if (ret)
1071 return ret;
1072
f72b3435
MK		 1073 /* If seqno wrap happened, omit the wait with no-ops */
1074 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1075 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1076 intel_ring_emit(waiter, seqno);
1077 intel_ring_emit(waiter, 0);
1078 intel_ring_emit(waiter, MI_NOOP);
1079 } else {
1080 intel_ring_emit(waiter, MI_NOOP);
1081 intel_ring_emit(waiter, MI_NOOP);
1082 intel_ring_emit(waiter, MI_NOOP);
1083 intel_ring_emit(waiter, MI_NOOP);
1084 }
c8c99b0f 1085 intel_ring_advance(waiter);
1ec14ad3
CW		 1086
1087 return 0;
1088}
1089
c6df541c
CW		 1090#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1091do { \
fcbc34e4
KG		 1092 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1093 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1094 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1095 intel_ring_emit(ring__, 0); \
1096 intel_ring_emit(ring__, 0); \
1097} while (0)
1098
1099static int
a4872ba6 1100pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1101{
18393f63 1102 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1103 int ret;
1104
1105 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1106 * incoherent with writes to memory, i.e. completely fubar,
1107 * so we need to use PIPE_NOTIFY instead.
1108 *
1109 * However, we also need to workaround the qword write
1110 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1111 * memory before requesting an interrupt.
1112 */
1113 ret = intel_ring_begin(ring, 32);
1114 if (ret)
1115 return ret;
1116
fcbc34e4 1117 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1118 PIPE_CONTROL_WRITE_FLUSH |
1119 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1120 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1823521d 1121 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
c6df541c
CW		 1122 intel_ring_emit(ring, 0);
1123 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1124 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1125 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1126 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1127 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1128 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1129 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1130 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1131 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1132 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1133 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1134
fcbc34e4 1135 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1136 PIPE_CONTROL_WRITE_FLUSH |
1137 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1138 PIPE_CONTROL_NOTIFY);
0d1aacac 1139 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1823521d 1140 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
c6df541c 1141 intel_ring_emit(ring, 0);
09246732 1142 __intel_ring_advance(ring);
c6df541c 1143
c6df541c
CW		 1144 return 0;
1145}
1146
4cd53c0c 1147static u32
a4872ba6 1148gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1149{
4cd53c0c
DV		 1150 /* Workaround to force correct ordering between irq and seqno writes on
1151 * ivb (and maybe also on snb) by reading from a CS register (like
1152 * ACTHD) before reading the status page. */
50877445
CW		 1153 if (!lazy_coherency) {
1154 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1155 POSTING_READ(RING_ACTHD(ring->mmio_base));
1156 }
1157
4cd53c0c
DV		 1158 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1159}
1160
8187a2b7 1161static u32
a4872ba6 1162ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1163{
1ec14ad3
CW		 1164 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1165}
1166
b70ec5bf 1167static void
a4872ba6 1168ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1169{
1170 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1171}
1172
c6df541c 1173static u32
a4872ba6 1174pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1175{
0d1aacac 1176 return ring->scratch.cpu_page[0];
c6df541c
CW		 1177}
1178
b70ec5bf 1179static void
a4872ba6 1180pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1181{
0d1aacac 1182 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1183}
1184
e48d8634 1185static bool
a4872ba6 1186gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1187{
1188 struct drm_device *dev = ring->dev;
4640c4ff 1189 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1190 unsigned long flags;
e48d8634 1191
7cd512f1 1192 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1193 return false;
1194
7338aefa 1195 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1196 if (ring->irq_refcount++ == 0)
480c8033 1197 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1198 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1199
1200 return true;
1201}
1202
1203static void
a4872ba6 1204gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1205{
1206 struct drm_device *dev = ring->dev;
4640c4ff 1207 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1208 unsigned long flags;
e48d8634 1209
7338aefa 1210 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1211 if (--ring->irq_refcount == 0)
480c8033 1212 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1213 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1214}
1215
b13c2b96 1216static bool
a4872ba6 1217i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1218{
78501eac 1219 struct drm_device *dev = ring->dev;
4640c4ff 1220 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1221 unsigned long flags;
62fdfeaf 1222
7cd512f1 1223 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1224 return false;
1225
7338aefa 1226 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1227 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1228 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1229 I915_WRITE(IMR, dev_priv->irq_mask);
1230 POSTING_READ(IMR);
1231 }
7338aefa 1232 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1233
1234 return true;
62fdfeaf
EA		 1235}
1236
8187a2b7 1237static void
a4872ba6 1238i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1239{
78501eac 1240 struct drm_device *dev = ring->dev;
4640c4ff 1241 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1242 unsigned long flags;
62fdfeaf 1243
7338aefa 1244 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1245 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1246 dev_priv->irq_mask |= ring->irq_enable_mask;
1247 I915_WRITE(IMR, dev_priv->irq_mask);
1248 POSTING_READ(IMR);
1249 }
7338aefa 1250 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1251}
1252
c2798b19 1253static bool
a4872ba6 1254i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1255{
1256 struct drm_device *dev = ring->dev;
4640c4ff 1257 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1258 unsigned long flags;
c2798b19 1259
7cd512f1 1260 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1261 return false;
1262
7338aefa 1263 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1264 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1265 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1266 I915_WRITE16(IMR, dev_priv->irq_mask);
1267 POSTING_READ16(IMR);
1268 }
7338aefa 1269 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1270
1271 return true;
1272}
1273
1274static void
a4872ba6 1275i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1276{
1277 struct drm_device *dev = ring->dev;
4640c4ff 1278 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1279 unsigned long flags;
c2798b19 1280
7338aefa 1281 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1282 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1283 dev_priv->irq_mask |= ring->irq_enable_mask;
1284 I915_WRITE16(IMR, dev_priv->irq_mask);
1285 POSTING_READ16(IMR);
1286 }
7338aefa 1287 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1288}
1289
a4872ba6 1290void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1291{
4593010b 1292 struct drm_device *dev = ring->dev;
4640c4ff 1293 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1294 u32 mmio = 0;
1295
1296 /* The ring status page addresses are no longer next to the rest of
1297 * the ring registers as of gen7.
1298 */
1299 if (IS_GEN7(dev)) {
1300 switch (ring->id) {
96154f2f 1301 case RCS:
4593010b
EA		 1302 mmio = RENDER_HWS_PGA_GEN7;
1303 break;
96154f2f 1304 case BCS:
4593010b
EA		 1305 mmio = BLT_HWS_PGA_GEN7;
1306 break;
77fe2ff3
ZY		 1307 /*
1308 * VCS2 actually doesn't exist on Gen7. Only shut up
1309 * gcc switch check warning
1310 */
1311 case VCS2:
96154f2f 1312 case VCS:
4593010b
EA		 1313 mmio = BSD_HWS_PGA_GEN7;
1314 break;
4a3dd19d 1315 case VECS:
9a8a2213
BW		 1316 mmio = VEBOX_HWS_PGA_GEN7;
1317 break;
4593010b
EA		 1318 }
1319 } else if (IS_GEN6(ring->dev)) {
1320 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1321 } else {
eb0d4b75 1322 /* XXX: gen8 returns to sanity */
4593010b
EA		 1323 mmio = RING_HWS_PGA(ring->mmio_base);
1324 }
1325
78501eac
CW		 1326 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1327 POSTING_READ(mmio);
884020bf 1328
dc616b89
DL		 1329 /*
1330 * Flush the TLB for this page
1331 *
1332 * FIXME: These two bits have disappeared on gen8, so a question
1333 * arises: do we still need this and if so how should we go about
1334 * invalidating the TLB?
1335 */
1336 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1337 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1338
1339 /* ring should be idle before issuing a sync flush*/
1340 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1341
884020bf
CW		 1342 I915_WRITE(reg,
1343 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1344 INSTPM_SYNC_FLUSH));
1345 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1346 1000))
1347 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1348 ring->name);
1349 }
8187a2b7
ZN		 1350}
1351
b72f3acb 1352static int
a4872ba6 1353bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1354 u32 invalidate_domains,
1355 u32 flush_domains)
d1b851fc 1356{
b72f3acb
CW		 1357 int ret;
1358
b72f3acb
CW		 1359 ret = intel_ring_begin(ring, 2);
1360 if (ret)
1361 return ret;
1362
1363 intel_ring_emit(ring, MI_FLUSH);
1364 intel_ring_emit(ring, MI_NOOP);
1365 intel_ring_advance(ring);
1366 return 0;
d1b851fc
ZN		 1367}
1368
3cce469c 1369static int
a4872ba6 1370i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1371{
3cce469c
CW		 1372 int ret;
1373
1374 ret = intel_ring_begin(ring, 4);
1375 if (ret)
1376 return ret;
6f392d54 1377
3cce469c
CW		 1378 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1379 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1823521d 1380 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
3cce469c 1381 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1382 __intel_ring_advance(ring);
d1b851fc 1383
3cce469c 1384 return 0;
d1b851fc
ZN		 1385}
1386
0f46832f 1387static bool
a4872ba6 1388gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1389{
1390 struct drm_device *dev = ring->dev;
4640c4ff 1391 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1392 unsigned long flags;
0f46832f 1393
7cd512f1
DV		 1394 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1395 return false;
0f46832f 1396
7338aefa 1397 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1398 if (ring->irq_refcount++ == 0) {
040d2baa 1399 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1400 I915_WRITE_IMR(ring,
1401 ~(ring->irq_enable_mask |
35a85ac6 1402 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1403 else
1404 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1405 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1406 }
7338aefa 1407 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1408
1409 return true;
1410}
1411
1412static void
a4872ba6 1413gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1414{
1415 struct drm_device *dev = ring->dev;
4640c4ff 1416 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1417 unsigned long flags;
0f46832f 1418
7338aefa 1419 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1420 if (--ring->irq_refcount == 0) {
040d2baa 1421 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1422 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1423 else
1424 I915_WRITE_IMR(ring, ~0);
480c8033 1425 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1426 }
7338aefa 1427 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1428}
1429
a19d2933 1430static bool
a4872ba6 1431hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1432{
1433 struct drm_device *dev = ring->dev;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 unsigned long flags;
1436
7cd512f1 1437 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1438 return false;
1439
59cdb63d 1440 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1441 if (ring->irq_refcount++ == 0) {
a19d2933 1442 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1443 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1444 }
59cdb63d 1445 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1446
1447 return true;
1448}
1449
1450static void
a4872ba6 1451hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1452{
1453 struct drm_device *dev = ring->dev;
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 unsigned long flags;
1456
59cdb63d 1457 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1458 if (--ring->irq_refcount == 0) {
a19d2933 1459 I915_WRITE_IMR(ring, ~0);
480c8033 1460 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1461 }
59cdb63d 1462 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1463}
1464
abd58f01 1465static bool
a4872ba6 1466gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1467{
1468 struct drm_device *dev = ring->dev;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1470 unsigned long flags;
1471
7cd512f1 1472 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1473 return false;
1474
1475 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1476 if (ring->irq_refcount++ == 0) {
1477 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1478 I915_WRITE_IMR(ring,
1479 ~(ring->irq_enable_mask |
1480 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1481 } else {
1482 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1483 }
1484 POSTING_READ(RING_IMR(ring->mmio_base));
1485 }
1486 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1487
1488 return true;
1489}
1490
1491static void
a4872ba6 1492gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1493{
1494 struct drm_device *dev = ring->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 unsigned long flags;
1497
1498 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1499 if (--ring->irq_refcount == 0) {
1500 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1501 I915_WRITE_IMR(ring,
1502 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1503 } else {
1504 I915_WRITE_IMR(ring, ~0);
1505 }
1506 POSTING_READ(RING_IMR(ring->mmio_base));
1507 }
1508 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1509}
1510
d1b851fc 1511static int
a4872ba6 1512i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1513 u64 offset, u32 length,
d7d4eedd 1514 unsigned flags)
d1b851fc 1515{
e1f99ce6 1516 int ret;
78501eac 1517
e1f99ce6
CW		 1518 ret = intel_ring_begin(ring, 2);
1519 if (ret)
1520 return ret;
1521
78501eac 1522 intel_ring_emit(ring,
65f56876
CW		 1523 MI_BATCH_BUFFER_START |
1524 MI_BATCH_GTT |
d7d4eedd 1525 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1526 intel_ring_emit(ring, offset);
78501eac
CW		 1527 intel_ring_advance(ring);
1528
d1b851fc
ZN		 1529 return 0;
1530}
1531
b45305fc
DV		 1532/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1533#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1534#define I830_TLB_ENTRIES (2)
1535#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1536static int
a4872ba6 1537i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1538 u64 offset, u32 len,
d7d4eedd 1539 unsigned flags)
62fdfeaf 1540{
c4d69da1 1541 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1542 int ret;
62fdfeaf 1543
c4d69da1
CW		 1544 ret = intel_ring_begin(ring, 6);
1545 if (ret)
1546 return ret;
62fdfeaf 1547
c4d69da1
CW		 1548 /* Evict the invalid PTE TLBs */
1549 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1550 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1551 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1552 intel_ring_emit(ring, cs_offset);
1553 intel_ring_emit(ring, 0xdeadbeef);
1554 intel_ring_emit(ring, MI_NOOP);
1555 intel_ring_advance(ring);
b45305fc 1556
c4d69da1 1557 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1558 if (len > I830_BATCH_LIMIT)
1559 return -ENOSPC;
1560
c4d69da1 1561 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1562 if (ret)
1563 return ret;
c4d69da1
CW		 1564
1565 /* Blit the batch (which has now all relocs applied) to the
1566 * stable batch scratch bo area (so that the CS never
1567 * stumbles over its tlb invalidation bug) ...
1568 */
1569 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1570 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1571 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024);
b45305fc 1572 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1573 intel_ring_emit(ring, 4096);
1574 intel_ring_emit(ring, offset);
c4d69da1 1575
b45305fc 1576 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1577 intel_ring_emit(ring, MI_NOOP);
1578 intel_ring_advance(ring);
b45305fc
DV		 1579
1580 /* ... and execute it. */
c4d69da1 1581 offset = cs_offset;
b45305fc 1582 }
e1f99ce6 1583
c4d69da1
CW		 1584 ret = intel_ring_begin(ring, 4);
1585 if (ret)
1586 return ret;
1587
1588 intel_ring_emit(ring, MI_BATCH_BUFFER);
1589 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1590 intel_ring_emit(ring, offset + len - 8);
1591 intel_ring_emit(ring, MI_NOOP);
1592 intel_ring_advance(ring);
1593
fb3256da
DV		 1594 return 0;
1595}
1596
1597static int
a4872ba6 1598i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1599 u64 offset, u32 len,
d7d4eedd 1600 unsigned flags)
fb3256da
DV		 1601{
1602 int ret;
1603
1604 ret = intel_ring_begin(ring, 2);
1605 if (ret)
1606 return ret;
1607
65f56876 1608 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1609 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1610 intel_ring_advance(ring);
62fdfeaf 1611
62fdfeaf
EA		 1612 return 0;
1613}
1614
a4872ba6 1615static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1616{
05394f39 1617 struct drm_i915_gem_object *obj;
62fdfeaf 1618
8187a2b7
ZN		 1619 obj = ring->status_page.obj;
1620 if (obj == NULL)
62fdfeaf 1621 return;
62fdfeaf 1622
9da3da66 1623 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1624 i915_gem_object_ggtt_unpin(obj);
05394f39 1625 drm_gem_object_unreference(&obj->base);
8187a2b7 1626 ring->status_page.obj = NULL;
62fdfeaf
EA		 1627}
1628
a4872ba6 1629static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1630{
05394f39 1631 struct drm_i915_gem_object *obj;
62fdfeaf 1632
e3efda49 1633 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1634 unsigned flags;
e3efda49 1635 int ret;
e4ffd173 1636
e3efda49
CW		 1637 obj = i915_gem_alloc_object(ring->dev, 4096);
1638 if (obj == NULL) {
1639 DRM_ERROR("Failed to allocate status page\n");
1640 return -ENOMEM;
1641 }
62fdfeaf 1642
e3efda49
CW		 1643 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1644 if (ret)
1645 goto err_unref;
1646
1f767e02
CW		 1647 flags = 0;
1648 if (!HAS_LLC(ring->dev))
1649 /* On g33, we cannot place HWS above 256MiB, so
1650 * restrict its pinning to the low mappable arena.
1651 * Though this restriction is not documented for
1652 * gen4, gen5, or byt, they also behave similarly
1653 * and hang if the HWS is placed at the top of the
1654 * GTT. To generalise, it appears that all !llc
1655 * platforms have issues with us placing the HWS
1656 * above the mappable region (even though we never
1657 * actualy map it).
1658 */
1659 flags |= PIN_MAPPABLE;
1660 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1661 if (ret) {
1662err_unref:
1663 drm_gem_object_unreference(&obj->base);
1664 return ret;
1665 }
1666
1667 ring->status_page.obj = obj;
1668 }
62fdfeaf 1669
f343c5f6 1670 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1671 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1672 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1673
8187a2b7
ZN		 1674 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1675 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1676
1677 return 0;
62fdfeaf
EA		 1678}
1679
a4872ba6 1680static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1681{
1682 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1683
1684 if (!dev_priv->status_page_dmah) {
1685 dev_priv->status_page_dmah =
1686 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1687 if (!dev_priv->status_page_dmah)
1688 return -ENOMEM;
1689 }
1690
6b8294a4
CW		 1691 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1692 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1693
1694 return 0;
1695}
1696
84c2377f 1697void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291
OM		 1698{
1699 if (!ringbuf->obj)
1700 return;
1701
1702 iounmap(ringbuf->virtual_start);
1703 i915_gem_object_ggtt_unpin(ringbuf->obj);
1704 drm_gem_object_unreference(&ringbuf->obj->base);
1705 ringbuf->obj = NULL;
1706}
1707
84c2377f
OM		 1708int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1709 struct intel_ringbuffer *ringbuf)
62fdfeaf 1710{
e3efda49 1711 struct drm_i915_private *dev_priv = to_i915(dev);
05394f39 1712 struct drm_i915_gem_object *obj;
dd785e35
CW		 1713 int ret;
1714
2919d291 1715 if (ringbuf->obj)
e3efda49 1716 return 0;
62fdfeaf 1717
ebc052e0
CW		 1718 obj = NULL;
1719 if (!HAS_LLC(dev))
93b0a4e0 1720 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1721 if (obj == NULL)
93b0a4e0 1722 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1723 if (obj == NULL)
1724 return -ENOMEM;
8187a2b7 1725
24f3a8cf
AG		 1726 /* mark ring buffers as read-only from GPU side by default */
1727 obj->gt_ro = 1;
1728
1ec9e26d 1729 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
dd785e35
CW		 1730 if (ret)
1731 goto err_unref;
62fdfeaf 1732
3eef8918
CW		 1733 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1734 if (ret)
1735 goto err_unpin;
1736
93b0a4e0 1737 ringbuf->virtual_start =
f343c5f6 1738 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
93b0a4e0
OM		 1739 ringbuf->size);
1740 if (ringbuf->virtual_start == NULL) {
8187a2b7 1741 ret = -EINVAL;
dd785e35 1742 goto err_unpin;
62fdfeaf
EA		 1743 }
1744
93b0a4e0 1745 ringbuf->obj = obj;
e3efda49
CW		 1746 return 0;
1747
1748err_unpin:
1749 i915_gem_object_ggtt_unpin(obj);
1750err_unref:
1751 drm_gem_object_unreference(&obj->base);
1752 return ret;
1753}
1754
1755static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1756 struct intel_engine_cs *ring)
e3efda49 1757{
8ee14975 1758 struct intel_ringbuffer *ringbuf = ring->buffer;
e3efda49
CW		 1759 int ret;
1760
8ee14975
OM		 1761 if (ringbuf == NULL) {
1762 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1763 if (!ringbuf)
1764 return -ENOMEM;
1765 ring->buffer = ringbuf;
1766 }
1767
e3efda49
CW		 1768 ring->dev = dev;
1769 INIT_LIST_HEAD(&ring->active_list);
1770 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1771 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1772 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1773 ringbuf->ring = ring;
ebc348b2 1774 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1775
1776 init_waitqueue_head(&ring->irq_queue);
1777
1778 if (I915_NEED_GFX_HWS(dev)) {
1779 ret = init_status_page(ring);
1780 if (ret)
8ee14975 1781 goto error;
e3efda49
CW		 1782 } else {
1783 BUG_ON(ring->id != RCS);
1784 ret = init_phys_status_page(ring);
1785 if (ret)
8ee14975 1786 goto error;
e3efda49
CW		 1787 }
1788
2919d291 1789 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
e3efda49
CW		 1790 if (ret) {
1791 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
8ee14975 1792 goto error;
e3efda49 1793 }
62fdfeaf 1794
55249baa
CW		 1795 /* Workaround an erratum on the i830 which causes a hang if
1796 * the TAIL pointer points to within the last 2 cachelines
1797 * of the buffer.
1798 */
93b0a4e0 1799 ringbuf->effective_size = ringbuf->size;
e3efda49 1800 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1801 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1802
44e895a8
BV		 1803 ret = i915_cmd_parser_init_ring(ring);
1804 if (ret)
8ee14975
OM		 1805 goto error;
1806
1807 ret = ring->init(ring);
1808 if (ret)
1809 goto error;
1810
1811 return 0;
351e3db2 1812
8ee14975
OM		 1813error:
1814 kfree(ringbuf);
1815 ring->buffer = NULL;
1816 return ret;
62fdfeaf
EA		 1817}
1818
a4872ba6 1819void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1820{
e3efda49 1821 struct drm_i915_private *dev_priv = to_i915(ring->dev);
93b0a4e0 1822 struct intel_ringbuffer *ringbuf = ring->buffer;
33626e6a 1823
93b0a4e0 1824 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1825 return;
1826
e3efda49 1827 intel_stop_ring_buffer(ring);
de8f0a50 1828 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1829
2919d291 1830 intel_destroy_ringbuffer_obj(ringbuf);
3d57e5bd
BW		 1831 ring->preallocated_lazy_request = NULL;
1832 ring->outstanding_lazy_seqno = 0;
78501eac 1833
8d19215b
ZN		 1834 if (ring->cleanup)
1835 ring->cleanup(ring);
1836
78501eac 1837 cleanup_status_page(ring);
44e895a8
BV		 1838
1839 i915_cmd_parser_fini_ring(ring);
8ee14975 1840
93b0a4e0 1841 kfree(ringbuf);
8ee14975 1842 ring->buffer = NULL;
62fdfeaf
EA		 1843}
1844
a4872ba6 1845static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1846{
93b0a4e0 1847 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1848 struct drm_i915_gem_request *request;
1cf0ba14 1849 u32 seqno = 0;
a71d8d94
CW		 1850 int ret;
1851
93b0a4e0
OM		 1852 if (ringbuf->last_retired_head != -1) {
1853 ringbuf->head = ringbuf->last_retired_head;
1854 ringbuf->last_retired_head = -1;
1f70999f 1855
82e104cc 1856 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1857 if (ringbuf->space >= n)
a71d8d94
CW		 1858 return 0;
1859 }
1860
1861 list_for_each_entry(request, &ring->request_list, list) {
82e104cc
OM		 1862 if (__intel_ring_space(request->tail, ringbuf->tail,
1863 ringbuf->size) >= n) {
a71d8d94
CW		 1864 seqno = request->seqno;
1865 break;
1866 }
a71d8d94
CW		 1867 }
1868
1869 if (seqno == 0)
1870 return -ENOSPC;
1871
1f70999f 1872 ret = i915_wait_seqno(ring, seqno);
a71d8d94
CW		 1873 if (ret)
1874 return ret;
1875
1cf0ba14 1876 i915_gem_retire_requests_ring(ring);
93b0a4e0
OM		 1877 ringbuf->head = ringbuf->last_retired_head;
1878 ringbuf->last_retired_head = -1;
a71d8d94 1879
82e104cc 1880 ringbuf->space = intel_ring_space(ringbuf);
a71d8d94
CW		 1881 return 0;
1882}
1883
a4872ba6 1884static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1885{
78501eac 1886 struct drm_device *dev = ring->dev;
cae5852d 1887 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1888 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1889 unsigned long end;
a71d8d94 1890 int ret;
c7dca47b 1891
a71d8d94
CW		 1892 ret = intel_ring_wait_request(ring, n);
1893 if (ret != -ENOSPC)
1894 return ret;
1895
09246732
CW		 1896 /* force the tail write in case we have been skipping them */
1897 __intel_ring_advance(ring);
1898
63ed2cb2
DV		 1899 /* With GEM the hangcheck timer should kick us out of the loop,
1900 * leaving it early runs the risk of corrupting GEM state (due
1901 * to running on almost untested codepaths). But on resume
1902 * timers don't work yet, so prevent a complete hang in that
1903 * case by choosing an insanely large timeout. */
1904 end = jiffies + 60 * HZ;
e6bfaf85 1905
dcfe0506 1906 trace_i915_ring_wait_begin(ring);
8187a2b7 1907 do {
93b0a4e0 1908 ringbuf->head = I915_READ_HEAD(ring);
82e104cc 1909 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1910 if (ringbuf->space >= n) {
dcfe0506
CW		 1911 ret = 0;
1912 break;
62fdfeaf
EA		 1913 }
1914
fb19e2ac
DV		 1915 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1916 dev->primary->master) {
62fdfeaf
EA		 1917 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1918 if (master_priv->sarea_priv)
1919 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1920 }
d1b851fc 1921
e60a0b10 1922 msleep(1);
d6b2c790 1923
dcfe0506
CW		 1924 if (dev_priv->mm.interruptible && signal_pending(current)) {
1925 ret = -ERESTARTSYS;
1926 break;
1927 }
1928
33196ded
DV		 1929 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1930 dev_priv->mm.interruptible);
d6b2c790 1931 if (ret)
dcfe0506
CW		 1932 break;
1933
1934 if (time_after(jiffies, end)) {
1935 ret = -EBUSY;
1936 break;
1937 }
1938 } while (1);
db53a302 1939 trace_i915_ring_wait_end(ring);
dcfe0506 1940 return ret;
8187a2b7 1941}
62fdfeaf 1942
a4872ba6 1943static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 1944{
1945 uint32_t __iomem *virt;
93b0a4e0
OM		 1946 struct intel_ringbuffer *ringbuf = ring->buffer;
1947 int rem = ringbuf->size - ringbuf->tail;
3e960501 1948
93b0a4e0 1949 if (ringbuf->space < rem) {
3e960501
CW		 1950 int ret = ring_wait_for_space(ring, rem);
1951 if (ret)
1952 return ret;
1953 }
1954
93b0a4e0 1955 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 1956 rem /= 4;
1957 while (rem--)
1958 iowrite32(MI_NOOP, virt++);
1959
93b0a4e0 1960 ringbuf->tail = 0;
82e104cc 1961 ringbuf->space = intel_ring_space(ringbuf);
3e960501
CW		 1962
1963 return 0;
1964}
1965
a4872ba6 1966int intel_ring_idle(struct intel_engine_cs *ring)
3e960501
CW		 1967{
1968 u32 seqno;
1969 int ret;
1970
1971 /* We need to add any requests required to flush the objects and ring */
1823521d 1972 if (ring->outstanding_lazy_seqno) {
0025c077 1973 ret = i915_add_request(ring, NULL);
3e960501
CW		 1974 if (ret)
1975 return ret;
1976 }
1977
1978 /* Wait upon the last request to be completed */
1979 if (list_empty(&ring->request_list))
1980 return 0;
1981
1982 seqno = list_entry(ring->request_list.prev,
1983 struct drm_i915_gem_request,
1984 list)->seqno;
1985
1986 return i915_wait_seqno(ring, seqno);
1987}
1988
9d773091 1989static int
a4872ba6 1990intel_ring_alloc_seqno(struct intel_engine_cs *ring)
9d773091 1991{
1823521d 1992 if (ring->outstanding_lazy_seqno)
9d773091
CW		 1993 return 0;
1994
3c0e234c
CW		 1995 if (ring->preallocated_lazy_request == NULL) {
1996 struct drm_i915_gem_request *request;
1997
1998 request = kmalloc(sizeof(*request), GFP_KERNEL);
1999 if (request == NULL)
2000 return -ENOMEM;
2001
2002 ring->preallocated_lazy_request = request;
2003 }
2004
1823521d 2005 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
9d773091
CW		 2006}
2007
a4872ba6 2008static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2009 int bytes)
cbcc80df 2010{
93b0a4e0 2011 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2012 int ret;
2013
93b0a4e0 2014 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2015 ret = intel_wrap_ring_buffer(ring);
2016 if (unlikely(ret))
2017 return ret;
2018 }
2019
93b0a4e0 2020 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2021 ret = ring_wait_for_space(ring, bytes);
2022 if (unlikely(ret))
2023 return ret;
2024 }
2025
cbcc80df
MK		 2026 return 0;
2027}
2028
a4872ba6 2029int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2030 int num_dwords)
8187a2b7 2031{
4640c4ff 2032 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2033 int ret;
78501eac 2034
33196ded
DV		 2035 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2036 dev_priv->mm.interruptible);
de2b9985
DV		 2037 if (ret)
2038 return ret;
21dd3734 2039
304d695c
CW		 2040 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2041 if (ret)
2042 return ret;
2043
9d773091
CW		 2044 /* Preallocate the olr before touching the ring */
2045 ret = intel_ring_alloc_seqno(ring);
2046 if (ret)
2047 return ret;
2048
ee1b1e5e 2049 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2050 return 0;
8187a2b7 2051}
78501eac 2052
753b1ad4 2053/* Align the ring tail to a cacheline boundary */
a4872ba6 2054int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2055{
ee1b1e5e 2056 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2057 int ret;
2058
2059 if (num_dwords == 0)
2060 return 0;
2061
18393f63 2062 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2063 ret = intel_ring_begin(ring, num_dwords);
2064 if (ret)
2065 return ret;
2066
2067 while (num_dwords--)
2068 intel_ring_emit(ring, MI_NOOP);
2069
2070 intel_ring_advance(ring);
2071
2072 return 0;
2073}
2074
a4872ba6 2075void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2076{
3b2cc8ab
OM		 2077 struct drm_device *dev = ring->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2079
1823521d 2080 BUG_ON(ring->outstanding_lazy_seqno);
498d2ac1 2081
3b2cc8ab 2082 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2083 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2084 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2085 if (HAS_VEBOX(dev))
5020150b 2086 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2087 }
d97ed339 2088
f7e98ad4 2089 ring->set_seqno(ring, seqno);
92cab734 2090 ring->hangcheck.seqno = seqno;
8187a2b7 2091}
62fdfeaf 2092
a4872ba6 2093static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2094 u32 value)
881f47b6 2095{
4640c4ff 2096 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2097
2098 /* Every tail move must follow the sequence below */
12f55818
CW		 2099
2100 /* Disable notification that the ring is IDLE. The GT
2101 * will then assume that it is busy and bring it out of rc6.
2102 */
0206e353 2103 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2104 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2105
2106 /* Clear the context id. Here be magic! */
2107 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2108
12f55818 2109 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2110 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2111 GEN6_BSD_SLEEP_INDICATOR) == 0,
2112 50))
2113 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2114
12f55818 2115 /* Now that the ring is fully powered up, update the tail */
0206e353 2116 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2117 POSTING_READ(RING_TAIL(ring->mmio_base));
2118
2119 /* Let the ring send IDLE messages to the GT again,
2120 * and so let it sleep to conserve power when idle.
2121 */
0206e353 2122 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2123 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2124}
2125
a4872ba6 2126static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2127 u32 invalidate, u32 flush)
881f47b6 2128{
71a77e07 2129 uint32_t cmd;
b72f3acb
CW		 2130 int ret;
2131
b72f3acb
CW		 2132 ret = intel_ring_begin(ring, 4);
2133 if (ret)
2134 return ret;
2135
71a77e07 2136 cmd = MI_FLUSH_DW;
075b3bba
BW		 2137 if (INTEL_INFO(ring->dev)->gen >= 8)
2138 cmd += 1;
9a289771
JB		 2139 /*
2140 * Bspec vol 1c.5 - video engine command streamer:
2141 * "If ENABLED, all TLBs will be invalidated once the flush
2142 * operation is complete. This bit is only valid when the
2143 * Post-Sync Operation field is a value of 1h or 3h."
2144 */
71a77e07 2145 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2146 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2147 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2148 intel_ring_emit(ring, cmd);
9a289771 2149 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2150 if (INTEL_INFO(ring->dev)->gen >= 8) {
2151 intel_ring_emit(ring, 0); /* upper addr */
2152 intel_ring_emit(ring, 0); /* value */
2153 } else {
2154 intel_ring_emit(ring, 0);
2155 intel_ring_emit(ring, MI_NOOP);
2156 }
b72f3acb
CW		 2157 intel_ring_advance(ring);
2158 return 0;
881f47b6
XH		 2159}
2160
1c7a0623 2161static int
a4872ba6 2162gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2163 u64 offset, u32 len,
1c7a0623
BW		 2164 unsigned flags)
2165{
896ab1a5 2166 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2167 int ret;
2168
2169 ret = intel_ring_begin(ring, 4);
2170 if (ret)
2171 return ret;
2172
2173 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2174 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2175 intel_ring_emit(ring, lower_32_bits(offset));
2176 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2177 intel_ring_emit(ring, MI_NOOP);
2178 intel_ring_advance(ring);
2179
2180 return 0;
2181}
2182
d7d4eedd 2183static int
a4872ba6 2184hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2185 u64 offset, u32 len,
d7d4eedd
CW		 2186 unsigned flags)
2187{
2188 int ret;
2189
2190 ret = intel_ring_begin(ring, 2);
2191 if (ret)
2192 return ret;
2193
2194 intel_ring_emit(ring,
77072258
CW		 2195 MI_BATCH_BUFFER_START |
2196 (flags & I915_DISPATCH_SECURE ?
2197 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2198 /* bit0-7 is the length on GEN6+ */
2199 intel_ring_emit(ring, offset);
2200 intel_ring_advance(ring);
2201
2202 return 0;
2203}
2204
881f47b6 2205static int
a4872ba6 2206gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2207 u64 offset, u32 len,
d7d4eedd 2208 unsigned flags)
881f47b6 2209{
0206e353 2210 int ret;
ab6f8e32 2211
0206e353
AJ		 2212 ret = intel_ring_begin(ring, 2);
2213 if (ret)
2214 return ret;
e1f99ce6 2215
d7d4eedd
CW		 2216 intel_ring_emit(ring,
2217 MI_BATCH_BUFFER_START |
2218 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2219 /* bit0-7 is the length on GEN6+ */
2220 intel_ring_emit(ring, offset);
2221 intel_ring_advance(ring);
ab6f8e32 2222
0206e353 2223 return 0;
881f47b6
XH		 2224}
2225
549f7365
CW		 2226/* Blitter support (SandyBridge+) */
2227
a4872ba6 2228static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2229 u32 invalidate, u32 flush)
8d19215b 2230{
fd3da6c9 2231 struct drm_device *dev = ring->dev;
1d73c2a8 2232 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2233 uint32_t cmd;
b72f3acb
CW		 2234 int ret;
2235
6a233c78 2236 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2237 if (ret)
2238 return ret;
2239
71a77e07 2240 cmd = MI_FLUSH_DW;
075b3bba
BW		 2241 if (INTEL_INFO(ring->dev)->gen >= 8)
2242 cmd += 1;
9a289771
JB		 2243 /*
2244 * Bspec vol 1c.3 - blitter engine command streamer:
2245 * "If ENABLED, all TLBs will be invalidated once the flush
2246 * operation is complete. This bit is only valid when the
2247 * Post-Sync Operation field is a value of 1h or 3h."
2248 */
71a77e07 2249 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2250 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2251 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2252 intel_ring_emit(ring, cmd);
9a289771 2253 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2254 if (INTEL_INFO(ring->dev)->gen >= 8) {
2255 intel_ring_emit(ring, 0); /* upper addr */
2256 intel_ring_emit(ring, 0); /* value */
2257 } else {
2258 intel_ring_emit(ring, 0);
2259 intel_ring_emit(ring, MI_NOOP);
2260 }
b72f3acb 2261 intel_ring_advance(ring);
fd3da6c9 2262
1d73c2a8
RV		 2263 if (!invalidate && flush) {
2264 if (IS_GEN7(dev))
2265 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2266 else if (IS_BROADWELL(dev))
2267 dev_priv->fbc.need_sw_cache_clean = true;
2268 }
fd3da6c9 2269
b72f3acb 2270 return 0;
8d19215b
ZN		 2271}
2272
5c1143bb
XH		 2273int intel_init_render_ring_buffer(struct drm_device *dev)
2274{
4640c4ff 2275 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2276 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2277 struct drm_i915_gem_object *obj;
2278 int ret;
5c1143bb 2279
59465b5f
DV		 2280 ring->name = "render ring";
2281 ring->id = RCS;
2282 ring->mmio_base = RENDER_RING_BASE;
2283
707d9cf9 2284 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2285 if (i915_semaphore_is_enabled(dev)) {
2286 obj = i915_gem_alloc_object(dev, 4096);
2287 if (obj == NULL) {
2288 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2289 i915.semaphores = 0;
2290 } else {
2291 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2292 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2293 if (ret != 0) {
2294 drm_gem_object_unreference(&obj->base);
2295 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2296 i915.semaphores = 0;
2297 } else
2298 dev_priv->semaphore_obj = obj;
2299 }
2300 }
00e1e623
VS		 2301 if (IS_CHERRYVIEW(dev))
2302 ring->init_context = chv_init_workarounds;
2303 else
2304 ring->init_context = bdw_init_workarounds;
707d9cf9
BW		 2305 ring->add_request = gen6_add_request;
2306 ring->flush = gen8_render_ring_flush;
2307 ring->irq_get = gen8_ring_get_irq;
2308 ring->irq_put = gen8_ring_put_irq;
2309 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2310 ring->get_seqno = gen6_ring_get_seqno;
2311 ring->set_seqno = ring_set_seqno;
2312 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2313 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2314 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2315 ring->semaphore.signal = gen8_rcs_signal;
2316 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2317 }
2318 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2319 ring->add_request = gen6_add_request;
4772eaeb 2320 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2321 if (INTEL_INFO(dev)->gen == 6)
b3111509 2322 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2323 ring->irq_get = gen6_ring_get_irq;
2324 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2325 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2326 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2327 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2328 if (i915_semaphore_is_enabled(dev)) {
2329 ring->semaphore.sync_to = gen6_ring_sync;
2330 ring->semaphore.signal = gen6_signal;
2331 /*
2332 * The current semaphore is only applied on pre-gen8
2333 * platform. And there is no VCS2 ring on the pre-gen8
2334 * platform. So the semaphore between RCS and VCS2 is
2335 * initialized as INVALID. Gen8 will initialize the
2336 * sema between VCS2 and RCS later.
2337 */
2338 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2339 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2340 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2341 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2342 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2343 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2344 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2345 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2346 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2347 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2348 }
c6df541c
CW		 2349 } else if (IS_GEN5(dev)) {
2350 ring->add_request = pc_render_add_request;
46f0f8d1 2351 ring->flush = gen4_render_ring_flush;
c6df541c 2352 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2353 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2354 ring->irq_get = gen5_ring_get_irq;
2355 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2356 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2357 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2358 } else {
8620a3a9 2359 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2360 if (INTEL_INFO(dev)->gen < 4)
2361 ring->flush = gen2_render_ring_flush;
2362 else
2363 ring->flush = gen4_render_ring_flush;
59465b5f 2364 ring->get_seqno = ring_get_seqno;
b70ec5bf 2365 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2366 if (IS_GEN2(dev)) {
2367 ring->irq_get = i8xx_ring_get_irq;
2368 ring->irq_put = i8xx_ring_put_irq;
2369 } else {
2370 ring->irq_get = i9xx_ring_get_irq;
2371 ring->irq_put = i9xx_ring_put_irq;
2372 }
e3670319 2373 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2374 }
59465b5f 2375 ring->write_tail = ring_write_tail;
707d9cf9 2376
d7d4eedd
CW		 2377 if (IS_HASWELL(dev))
2378 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2379 else if (IS_GEN8(dev))
2380 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2381 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2382 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2383 else if (INTEL_INFO(dev)->gen >= 4)
2384 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2385 else if (IS_I830(dev) || IS_845G(dev))
2386 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2387 else
2388 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 2389 ring->init = init_render_ring;
2390 ring->cleanup = render_ring_cleanup;
2391
b45305fc
DV		 2392 /* Workaround batchbuffer to combat CS tlb bug. */
2393 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2394 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2395 if (obj == NULL) {
2396 DRM_ERROR("Failed to allocate batch bo\n");
2397 return -ENOMEM;
2398 }
2399
be1fa129 2400 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2401 if (ret != 0) {
2402 drm_gem_object_unreference(&obj->base);
2403 DRM_ERROR("Failed to ping batch bo\n");
2404 return ret;
2405 }
2406
0d1aacac
CW		 2407 ring->scratch.obj = obj;
2408 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2409 }
2410
1ec14ad3 2411 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 2412}
2413
e8616b6c
CW		 2414int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2415{
4640c4ff 2416 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2417 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
8ee14975 2418 struct intel_ringbuffer *ringbuf = ring->buffer;
6b8294a4 2419 int ret;
e8616b6c 2420
8ee14975
OM		 2421 if (ringbuf == NULL) {
2422 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2423 if (!ringbuf)
2424 return -ENOMEM;
2425 ring->buffer = ringbuf;
2426 }
2427
59465b5f
DV		 2428 ring->name = "render ring";
2429 ring->id = RCS;
2430 ring->mmio_base = RENDER_RING_BASE;
2431
e8616b6c 2432 if (INTEL_INFO(dev)->gen >= 6) {
b4178f8a 2433 /* non-kms not supported on gen6+ */
8ee14975
OM		 2434 ret = -ENODEV;
2435 goto err_ringbuf;
e8616b6c 2436 }
28f0cbf7
DV		 2437
2438 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2439 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2440 * the special gen5 functions. */
2441 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2442 if (INTEL_INFO(dev)->gen < 4)
2443 ring->flush = gen2_render_ring_flush;
2444 else
2445 ring->flush = gen4_render_ring_flush;
28f0cbf7 2446 ring->get_seqno = ring_get_seqno;
b70ec5bf 2447 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2448 if (IS_GEN2(dev)) {
2449 ring->irq_get = i8xx_ring_get_irq;
2450 ring->irq_put = i8xx_ring_put_irq;
2451 } else {
2452 ring->irq_get = i9xx_ring_get_irq;
2453 ring->irq_put = i9xx_ring_put_irq;
2454 }
28f0cbf7 2455 ring->irq_enable_mask = I915_USER_INTERRUPT;
59465b5f 2456 ring->write_tail = ring_write_tail;
fb3256da
DV		 2457 if (INTEL_INFO(dev)->gen >= 4)
2458 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2459 else if (IS_I830(dev) || IS_845G(dev))
2460 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2461 else
2462 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 2463 ring->init = init_render_ring;
2464 ring->cleanup = render_ring_cleanup;
e8616b6c
CW		 2465
2466 ring->dev = dev;
2467 INIT_LIST_HEAD(&ring->active_list);
2468 INIT_LIST_HEAD(&ring->request_list);
e8616b6c 2469
93b0a4e0
OM		 2470 ringbuf->size = size;
2471 ringbuf->effective_size = ringbuf->size;
17f10fdc 2472 if (IS_I830(ring->dev) || IS_845G(ring->dev))
93b0a4e0 2473 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
e8616b6c 2474
93b0a4e0
OM		 2475 ringbuf->virtual_start = ioremap_wc(start, size);
2476 if (ringbuf->virtual_start == NULL) {
e8616b6c
CW		 2477 DRM_ERROR("can not ioremap virtual address for"
2478 " ring buffer\n");
8ee14975
OM		 2479 ret = -ENOMEM;
2480 goto err_ringbuf;
e8616b6c
CW		 2481 }
2482
6b8294a4 2483 if (!I915_NEED_GFX_HWS(dev)) {
035dc1e0 2484 ret = init_phys_status_page(ring);
6b8294a4 2485 if (ret)
8ee14975 2486 goto err_vstart;
6b8294a4
CW		 2487 }
2488
e8616b6c 2489 return 0;
8ee14975
OM		 2490
2491err_vstart:
93b0a4e0 2492 iounmap(ringbuf->virtual_start);
8ee14975
OM		 2493err_ringbuf:
2494 kfree(ringbuf);
2495 ring->buffer = NULL;
2496 return ret;
e8616b6c
CW		 2497}
2498
5c1143bb
XH		 2499int intel_init_bsd_ring_buffer(struct drm_device *dev)
2500{
4640c4ff 2501 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2502 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2503
58fa3835
DV		 2504 ring->name = "bsd ring";
2505 ring->id = VCS;
2506
0fd2c201 2507 ring->write_tail = ring_write_tail;
780f18c8 2508 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2509 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2510 /* gen6 bsd needs a special wa for tail updates */
2511 if (IS_GEN6(dev))
2512 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2513 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2514 ring->add_request = gen6_add_request;
2515 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2516 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2517 if (INTEL_INFO(dev)->gen >= 8) {
2518 ring->irq_enable_mask =
2519 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2520 ring->irq_get = gen8_ring_get_irq;
2521 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2522 ring->dispatch_execbuffer =
2523 gen8_ring_dispatch_execbuffer;
707d9cf9 2524 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2525 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2526 ring->semaphore.signal = gen8_xcs_signal;
2527 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2528 }
abd58f01
BW		 2529 } else {
2530 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2531 ring->irq_get = gen6_ring_get_irq;
2532 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2533 ring->dispatch_execbuffer =
2534 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2535 if (i915_semaphore_is_enabled(dev)) {
2536 ring->semaphore.sync_to = gen6_ring_sync;
2537 ring->semaphore.signal = gen6_signal;
2538 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2539 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2540 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2541 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2542 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2543 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2544 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2545 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2546 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2547 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2548 }
abd58f01 2549 }
58fa3835
DV		 2550 } else {
2551 ring->mmio_base = BSD_RING_BASE;
58fa3835 2552 ring->flush = bsd_ring_flush;
8620a3a9 2553 ring->add_request = i9xx_add_request;
58fa3835 2554 ring->get_seqno = ring_get_seqno;
b70ec5bf 2555 ring->set_seqno = ring_set_seqno;
e48d8634 2556 if (IS_GEN5(dev)) {
cc609d5d 2557 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2558 ring->irq_get = gen5_ring_get_irq;
2559 ring->irq_put = gen5_ring_put_irq;
2560 } else {
e3670319 2561 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2562 ring->irq_get = i9xx_ring_get_irq;
2563 ring->irq_put = i9xx_ring_put_irq;
2564 }
fb3256da 2565 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835
DV		 2566 }
2567 ring->init = init_ring_common;
2568
1ec14ad3 2569 return intel_init_ring_buffer(dev, ring);
5c1143bb 2570}
549f7365 2571
845f74a7
ZY		 2572/**
2573 * Initialize the second BSD ring for Broadwell GT3.
2574 * It is noted that this only exists on Broadwell GT3.
2575 */
2576int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2577{
2578 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2579 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2580
2581 if ((INTEL_INFO(dev)->gen != 8)) {
2582 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2583 return -EINVAL;
2584 }
2585
f7b64236 2586 ring->name = "bsd2 ring";
845f74a7
ZY		 2587 ring->id = VCS2;
2588
2589 ring->write_tail = ring_write_tail;
2590 ring->mmio_base = GEN8_BSD2_RING_BASE;
2591 ring->flush = gen6_bsd_ring_flush;
2592 ring->add_request = gen6_add_request;
2593 ring->get_seqno = gen6_ring_get_seqno;
2594 ring->set_seqno = ring_set_seqno;
2595 ring->irq_enable_mask =
2596 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2597 ring->irq_get = gen8_ring_get_irq;
2598 ring->irq_put = gen8_ring_put_irq;
2599 ring->dispatch_execbuffer =
2600 gen8_ring_dispatch_execbuffer;
3e78998a 2601 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2602 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2603 ring->semaphore.signal = gen8_xcs_signal;
2604 GEN8_RING_SEMAPHORE_INIT;
2605 }
845f74a7
ZY		 2606 ring->init = init_ring_common;
2607
2608 return intel_init_ring_buffer(dev, ring);
2609}
2610
549f7365
CW		 2611int intel_init_blt_ring_buffer(struct drm_device *dev)
2612{
4640c4ff 2613 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2614 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2615
3535d9dd
DV		 2616 ring->name = "blitter ring";
2617 ring->id = BCS;
2618
2619 ring->mmio_base = BLT_RING_BASE;
2620 ring->write_tail = ring_write_tail;
ea251324 2621 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2622 ring->add_request = gen6_add_request;
2623 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2624 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2625 if (INTEL_INFO(dev)->gen >= 8) {
2626 ring->irq_enable_mask =
2627 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2628 ring->irq_get = gen8_ring_get_irq;
2629 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2630 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2631 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2632 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2633 ring->semaphore.signal = gen8_xcs_signal;
2634 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2635 }
abd58f01
BW		 2636 } else {
2637 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2638 ring->irq_get = gen6_ring_get_irq;
2639 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2640 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2641 if (i915_semaphore_is_enabled(dev)) {
2642 ring->semaphore.signal = gen6_signal;
2643 ring->semaphore.sync_to = gen6_ring_sync;
2644 /*
2645 * The current semaphore is only applied on pre-gen8
2646 * platform. And there is no VCS2 ring on the pre-gen8
2647 * platform. So the semaphore between BCS and VCS2 is
2648 * initialized as INVALID. Gen8 will initialize the
2649 * sema between BCS and VCS2 later.
2650 */
2651 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2652 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2653 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2654 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2655 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2656 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2657 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2658 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2659 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2660 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2661 }
abd58f01 2662 }
3535d9dd 2663 ring->init = init_ring_common;
549f7365 2664
1ec14ad3 2665 return intel_init_ring_buffer(dev, ring);
549f7365 2666}
a7b9761d 2667
9a8a2213
BW		 2668int intel_init_vebox_ring_buffer(struct drm_device *dev)
2669{
4640c4ff 2670 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2671 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2672
2673 ring->name = "video enhancement ring";
2674 ring->id = VECS;
2675
2676 ring->mmio_base = VEBOX_RING_BASE;
2677 ring->write_tail = ring_write_tail;
2678 ring->flush = gen6_ring_flush;
2679 ring->add_request = gen6_add_request;
2680 ring->get_seqno = gen6_ring_get_seqno;
2681 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2682
2683 if (INTEL_INFO(dev)->gen >= 8) {
2684 ring->irq_enable_mask =
40c499f9 2685 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2686 ring->irq_get = gen8_ring_get_irq;
2687 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2688 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2689 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2690 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2691 ring->semaphore.signal = gen8_xcs_signal;
2692 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2693 }
abd58f01
BW		 2694 } else {
2695 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2696 ring->irq_get = hsw_vebox_get_irq;
2697 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2698 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2699 if (i915_semaphore_is_enabled(dev)) {
2700 ring->semaphore.sync_to = gen6_ring_sync;
2701 ring->semaphore.signal = gen6_signal;
2702 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2703 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2704 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2705 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2706 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2707 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2708 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2709 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2710 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2711 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2712 }
abd58f01 2713 }
9a8a2213
BW		 2714 ring->init = init_ring_common;
2715
2716 return intel_init_ring_buffer(dev, ring);
2717}
2718
a7b9761d 2719int
a4872ba6 2720intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2721{
2722 int ret;
2723
2724 if (!ring->gpu_caches_dirty)
2725 return 0;
2726
2727 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2728 if (ret)
2729 return ret;
2730
2731 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2732
2733 ring->gpu_caches_dirty = false;
2734 return 0;
2735}
2736
2737int
a4872ba6 2738intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2739{
2740 uint32_t flush_domains;
2741 int ret;
2742
2743 flush_domains = 0;
2744 if (ring->gpu_caches_dirty)
2745 flush_domains = I915_GEM_GPU_DOMAINS;
2746
2747 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2748 if (ret)
2749 return ret;
2750
2751 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2752
2753 ring->gpu_caches_dirty = false;
2754 return 0;
2755}
e3efda49
CW		 2756
2757void
a4872ba6 2758intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2759{
2760 int ret;
2761
2762 if (!intel_ring_initialized(ring))
2763 return;
2764
2765 ret = intel_ring_idle(ring);
2766 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2767 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2768 ring->name, ret);
2769
2770 stop_ring(ring);
2771}
Linux kernel - Deliverables
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