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drm/i915/skl: Implement WaDisablePartialResolveInVc
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 382
add284a3
CW		 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
f3987631
PZ		 385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
b9e1faa7 397 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
9688ecad 401 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
4772eaeb
PZ		 404 return 0;
405}
406
884ceace
KG		 407static int
408gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410{
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426}
427
a5f3d68e 428static int
a4872ba6 429gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 430 u32 invalidate_domains, u32 flush_domains)
431{
432 u32 flags = 0;
18393f63 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 434 int ret;
a5f3d68e
BW		 435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
a5f3d68e
BW		 459 }
460
c5ad011d
RV		 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
a5f3d68e
BW		 469}
470
a4872ba6 471static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 472 u32 value)
d46eefa2 473{
4640c4ff 474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 475 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 476}
477
a4872ba6 478u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 479{
4640c4ff 480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 481 u64 acthd;
8187a2b7 482
50877445
CW		 483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
8187a2b7
ZN		 492}
493
a4872ba6 494static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503}
504
af75f269
DL		 505static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
506{
507 struct drm_device *dev = ring->dev;
508 struct drm_i915_private *dev_priv = ring->dev->dev_private;
509 u32 mmio = 0;
510
511 /* The ring status page addresses are no longer next to the rest of
512 * the ring registers as of gen7.
513 */
514 if (IS_GEN7(dev)) {
515 switch (ring->id) {
516 case RCS:
517 mmio = RENDER_HWS_PGA_GEN7;
518 break;
519 case BCS:
520 mmio = BLT_HWS_PGA_GEN7;
521 break;
522 /*
523 * VCS2 actually doesn't exist on Gen7. Only shut up
524 * gcc switch check warning
525 */
526 case VCS2:
527 case VCS:
528 mmio = BSD_HWS_PGA_GEN7;
529 break;
530 case VECS:
531 mmio = VEBOX_HWS_PGA_GEN7;
532 break;
533 }
534 } else if (IS_GEN6(ring->dev)) {
535 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
536 } else {
537 /* XXX: gen8 returns to sanity */
538 mmio = RING_HWS_PGA(ring->mmio_base);
539 }
540
541 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
542 POSTING_READ(mmio);
543
544 /*
545 * Flush the TLB for this page
546 *
547 * FIXME: These two bits have disappeared on gen8, so a question
548 * arises: do we still need this and if so how should we go about
549 * invalidating the TLB?
550 */
551 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
552 u32 reg = RING_INSTPM(ring->mmio_base);
553
554 /* ring should be idle before issuing a sync flush*/
555 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
556
557 I915_WRITE(reg,
558 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
559 INSTPM_SYNC_FLUSH));
560 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
561 1000))
562 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
563 ring->name);
564 }
565}
566
a4872ba6 567static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 568{
9991ae78 569 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 570
9991ae78
CW		 571 if (!IS_GEN2(ring->dev)) {
572 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 573 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
574 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 575 /* Sometimes we observe that the idle flag is not
576 * set even though the ring is empty. So double
577 * check before giving up.
578 */
579 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
580 return false;
9991ae78
CW		 581 }
582 }
b7884eb4 583
7f2ab699 584 I915_WRITE_CTL(ring, 0);
570ef608 585 I915_WRITE_HEAD(ring, 0);
78501eac 586 ring->write_tail(ring, 0);
8187a2b7 587
9991ae78
CW		 588 if (!IS_GEN2(ring->dev)) {
589 (void)I915_READ_CTL(ring);
590 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
591 }
a51435a3 592
9991ae78
CW		 593 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
594}
8187a2b7 595
a4872ba6 596static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 597{
598 struct drm_device *dev = ring->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 600 struct intel_ringbuffer *ringbuf = ring->buffer;
601 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 602 int ret = 0;
603
59bad947 604 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 605
606 if (!stop_ring(ring)) {
607 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 608 DRM_DEBUG_KMS("%s head not reset to zero "
609 "ctl %08x head %08x tail %08x start %08x\n",
610 ring->name,
611 I915_READ_CTL(ring),
612 I915_READ_HEAD(ring),
613 I915_READ_TAIL(ring),
614 I915_READ_START(ring));
8187a2b7 615
9991ae78 616 if (!stop_ring(ring)) {
6fd0d56e
CW		 617 DRM_ERROR("failed to set %s head to zero "
618 "ctl %08x head %08x tail %08x start %08x\n",
619 ring->name,
620 I915_READ_CTL(ring),
621 I915_READ_HEAD(ring),
622 I915_READ_TAIL(ring),
623 I915_READ_START(ring));
9991ae78
CW		 624 ret = -EIO;
625 goto out;
6fd0d56e 626 }
8187a2b7
ZN		 627 }
628
9991ae78
CW		 629 if (I915_NEED_GFX_HWS(dev))
630 intel_ring_setup_status_page(ring);
631 else
632 ring_setup_phys_status_page(ring);
633
ece4a17d
JK		 634 /* Enforce ordering by reading HEAD register back */
635 I915_READ_HEAD(ring);
636
0d8957c8
DV		 637 /* Initialize the ring. This must happen _after_ we've cleared the ring
638 * registers with the above sequence (the readback of the HEAD registers
639 * also enforces ordering), otherwise the hw might lose the new ring
640 * register values. */
f343c5f6 641 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 642
643 /* WaClearRingBufHeadRegAtInit:ctg,elk */
644 if (I915_READ_HEAD(ring))
645 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
646 ring->name, I915_READ_HEAD(ring));
647 I915_WRITE_HEAD(ring, 0);
648 (void)I915_READ_HEAD(ring);
649
7f2ab699 650 I915_WRITE_CTL(ring,
93b0a4e0 651 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 652 | RING_VALID);
8187a2b7 653
8187a2b7 654 /* If the head is still not zero, the ring is dead */
f01db988 655 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 656 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 657 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 658 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 659 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
660 ring->name,
661 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
662 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
663 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 664 ret = -EIO;
665 goto out;
8187a2b7
ZN		 666 }
667
ebd0fd4b 668 ringbuf->last_retired_head = -1;
5c6c6003
CW		 669 ringbuf->head = I915_READ_HEAD(ring);
670 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 671 intel_ring_update_space(ringbuf);
1ec14ad3 672
50f018df
CW		 673 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
674
b7884eb4 675out:
59bad947 676 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 677
678 return ret;
8187a2b7
ZN		 679}
680
9b1136d5
OM		 681void
682intel_fini_pipe_control(struct intel_engine_cs *ring)
683{
684 struct drm_device *dev = ring->dev;
685
686 if (ring->scratch.obj == NULL)
687 return;
688
689 if (INTEL_INFO(dev)->gen >= 5) {
690 kunmap(sg_page(ring->scratch.obj->pages->sgl));
691 i915_gem_object_ggtt_unpin(ring->scratch.obj);
692 }
693
694 drm_gem_object_unreference(&ring->scratch.obj->base);
695 ring->scratch.obj = NULL;
696}
697
698int
699intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 700{
c6df541c
CW		 701 int ret;
702
bfc882b4 703 WARN_ON(ring->scratch.obj);
c6df541c 704
0d1aacac
CW		 705 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
706 if (ring->scratch.obj == NULL) {
c6df541c
CW		 707 DRM_ERROR("Failed to allocate seqno page\n");
708 ret = -ENOMEM;
709 goto err;
710 }
e4ffd173 711
a9cc726c
DV		 712 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
713 if (ret)
714 goto err_unref;
c6df541c 715
1ec9e26d 716 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 717 if (ret)
718 goto err_unref;
719
0d1aacac
CW		 720 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
721 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
722 if (ring->scratch.cpu_page == NULL) {
56b085a0 723 ret = -ENOMEM;
c6df541c 724 goto err_unpin;
56b085a0 725 }
c6df541c 726
2b1086cc 727 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 728 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 729 return 0;
730
731err_unpin:
d7f46fc4 732 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 733err_unref:
0d1aacac 734 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 735err:
c6df541c
CW		 736 return ret;
737}
738
771b9a53
MT		 739static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
740 struct intel_context *ctx)
86d7f238 741{
7225342a 742 int ret, i;
888b5995
AS		 743 struct drm_device *dev = ring->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 745 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 746
e6c1abb7 747 if (WARN_ON_ONCE(w->count == 0))
7225342a 748 return 0;
888b5995 749
7225342a
MK		 750 ring->gpu_caches_dirty = true;
751 ret = intel_ring_flush_all_caches(ring);
752 if (ret)
753 return ret;
888b5995 754
22a916aa 755 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 756 if (ret)
757 return ret;
758
22a916aa 759 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 760 for (i = 0; i < w->count; i++) {
7225342a
MK		 761 intel_ring_emit(ring, w->reg[i].addr);
762 intel_ring_emit(ring, w->reg[i].value);
763 }
22a916aa 764 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 765
766 intel_ring_advance(ring);
767
768 ring->gpu_caches_dirty = true;
769 ret = intel_ring_flush_all_caches(ring);
770 if (ret)
771 return ret;
888b5995 772
7225342a 773 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 774
7225342a 775 return 0;
86d7f238
AS		 776}
777
8f0e2b9d
DV		 778static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
779 struct intel_context *ctx)
780{
781 int ret;
782
783 ret = intel_ring_workarounds_emit(ring, ctx);
784 if (ret != 0)
785 return ret;
786
787 ret = i915_gem_render_state_init(ring);
788 if (ret)
789 DRM_ERROR("init render state: %d\n", ret);
790
791 return ret;
792}
793
7225342a 794static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 795 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 796{
797 const u32 idx = dev_priv->workarounds.count;
798
799 if (WARN_ON(idx >= I915_MAX_WA_REGS))
800 return -ENOSPC;
801
802 dev_priv->workarounds.reg[idx].addr = addr;
803 dev_priv->workarounds.reg[idx].value = val;
804 dev_priv->workarounds.reg[idx].mask = mask;
805
806 dev_priv->workarounds.count++;
807
808 return 0;
86d7f238
AS		 809}
810
cf4b0de6
DL		 811#define WA_REG(addr, mask, val) { \
812 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 813 if (r) \
814 return r; \
815 }
816
817#define WA_SET_BIT_MASKED(addr, mask) \
26459343 818 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 819
820#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 821 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 822
98533251 823#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 824 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 825
cf4b0de6
DL		 826#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
827#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 828
cf4b0de6 829#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 830
00e1e623 831static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 832{
888b5995
AS		 833 struct drm_device *dev = ring->dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 835
86d7f238 836 /* WaDisablePartialInstShootdown:bdw */
101b376d 837 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 838 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
839 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
840 STALL_DOP_GATING_DISABLE);
86d7f238 841
101b376d 842 /* WaDisableDopClockGating:bdw */
7225342a
MK		 843 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
844 DOP_CLOCK_GATING_DISABLE);
86d7f238 845
7225342a
MK		 846 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
847 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 848
849 /* Use Force Non-Coherent whenever executing a 3D context. This is a
850 * workaround for for a possible hang in the unlikely event a TLB
851 * invalidation occurs during a PSD flush.
852 */
7225342a 853 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 854 /* WaForceEnableNonCoherent:bdw */
7225342a 855 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 856 /* WaForceContextSaveRestoreNonCoherent:bdw */
857 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
858 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 859 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 860 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 861 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 862
2701fc43
KG		 863 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
864 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
865 * polygons in the same 8x4 pixel/sample area to be processed without
866 * stalling waiting for the earlier ones to write to Hierarchical Z
867 * buffer."
868 *
869 * This optimization is off by default for Broadwell; turn it on.
870 */
871 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
872
86d7f238 873 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 874 WA_SET_BIT_MASKED(CACHE_MODE_1,
875 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 876
877 /*
878 * BSpec recommends 8x4 when MSAA is used,
879 * however in practice 16x4 seems fastest.
880 *
881 * Note that PS/WM thread counts depend on the WIZ hashing
882 * disable bit, which we don't touch here, but it's good
883 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
884 */
98533251
DL		 885 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
886 GEN6_WIZ_HASHING_MASK,
887 GEN6_WIZ_HASHING_16x4);
888b5995 888
86d7f238
AS		 889 return 0;
890}
891
00e1e623
VS		 892static int chv_init_workarounds(struct intel_engine_cs *ring)
893{
00e1e623
VS		 894 struct drm_device *dev = ring->dev;
895 struct drm_i915_private *dev_priv = dev->dev_private;
896
00e1e623 897 /* WaDisablePartialInstShootdown:chv */
00e1e623 898 /* WaDisableThreadStallDopClockGating:chv */
7225342a 899 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 900 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
901 STALL_DOP_GATING_DISABLE);
00e1e623 902
95289009
AS		 903 /* Use Force Non-Coherent whenever executing a 3D context. This is a
904 * workaround for a possible hang in the unlikely event a TLB
905 * invalidation occurs during a PSD flush.
906 */
907 /* WaForceEnableNonCoherent:chv */
908 /* WaHdcDisableFetchWhenMasked:chv */
909 WA_SET_BIT_MASKED(HDC_CHICKEN0,
910 HDC_FORCE_NON_COHERENT |
911 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
912
973a5b06
KG		 913 /* According to the CACHE_MODE_0 default value documentation, some
914 * CHV platforms disable this optimization by default. Turn it on.
915 */
916 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
917
14bc16e3
VS		 918 /* Wa4x4STCOptimizationDisable:chv */
919 WA_SET_BIT_MASKED(CACHE_MODE_1,
920 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
921
d60de81d
KG		 922 /* Improve HiZ throughput on CHV. */
923 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
924
e7fc2436
VS		 925 /*
926 * BSpec recommends 8x4 when MSAA is used,
927 * however in practice 16x4 seems fastest.
928 *
929 * Note that PS/WM thread counts depend on the WIZ hashing
930 * disable bit, which we don't touch here, but it's good
931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
932 */
933 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
934 GEN6_WIZ_HASHING_MASK,
935 GEN6_WIZ_HASHING_16x4);
936
7225342a
MK		 937 return 0;
938}
939
3b106531
HN		 940static int gen9_init_workarounds(struct intel_engine_cs *ring)
941{
ab0dfafe
HN		 942 struct drm_device *dev = ring->dev;
943 struct drm_i915_private *dev_priv = dev->dev_private;
944
945 /* WaDisablePartialInstShootdown:skl */
946 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
947 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
948
8424171e
NH		 949 /* Syncing dependencies between camera and graphics */
950 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
951 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
952
e90fff15
NH		 953 if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
954 INTEL_REVID(dev) <= SKL_REVID_B0) {
1de4582f
NH		 955 /*
956 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
957 * This is a pre-production w/a.
958 */
959 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
960 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
961 ~GEN9_DG_MIRROR_FIX_ENABLE);
962 }
963
cac23df4
NH		 964 if (INTEL_REVID(dev) >= SKL_REVID_C0) {
965 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
966 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
967 GEN9_ENABLE_YV12_BUGFIX);
968 }
969
13bea49c
HN		 970 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
971 /*
972 *Use Force Non-Coherent whenever executing a 3D context. This
973 * is a workaround for a possible hang in the unlikely event
974 * a TLB invalidation occurs during a PSD flush.
975 */
976 /* WaForceEnableNonCoherent:skl */
977 WA_SET_BIT_MASKED(HDC_CHICKEN0,
978 HDC_FORCE_NON_COHERENT);
979 }
980
1840481f
HN		 981 /* Wa4x4STCOptimizationDisable:skl */
982 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
983
9370cd98
DL		 984 /* WaDisablePartialResolveInVc:skl */
985 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
986
3b106531
HN		 987 return 0;
988}
989
8d205494
DL		 990static int skl_init_workarounds(struct intel_engine_cs *ring)
991{
992 gen9_init_workarounds(ring);
993
994 return 0;
995}
996
771b9a53 997int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 998{
999 struct drm_device *dev = ring->dev;
1000 struct drm_i915_private *dev_priv = dev->dev_private;
1001
1002 WARN_ON(ring->id != RCS);
1003
1004 dev_priv->workarounds.count = 0;
1005
1006 if (IS_BROADWELL(dev))
1007 return bdw_init_workarounds(ring);
1008
1009 if (IS_CHERRYVIEW(dev))
1010 return chv_init_workarounds(ring);
00e1e623 1011
8d205494
DL		 1012 if (IS_SKYLAKE(dev))
1013 return skl_init_workarounds(ring);
1014 else if (IS_GEN9(dev))
3b106531
HN		 1015 return gen9_init_workarounds(ring);
1016
00e1e623
VS		 1017 return 0;
1018}
1019
a4872ba6 1020static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1021{
78501eac 1022 struct drm_device *dev = ring->dev;
1ec14ad3 1023 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1024 int ret = init_ring_common(ring);
9c33baa6
KZ		 1025 if (ret)
1026 return ret;
a69ffdbf 1027
61a563a2
AG		 1028 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1029 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1030 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1031
1032 /* We need to disable the AsyncFlip performance optimisations in order
1033 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1034 * programmed to '1' on all products.
8693a824 1035 *
b3f797ac 1036 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 1037 */
fbdcb068 1038 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 1039 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1040
f05bb0c7 1041 /* Required for the hardware to program scanline values for waiting */
01fa0302 1042 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1043 if (INTEL_INFO(dev)->gen == 6)
1044 I915_WRITE(GFX_MODE,
aa83e30d 1045 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1046
01fa0302 1047 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1048 if (IS_GEN7(dev))
1049 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1050 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1051 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1052
5e13a0c5 1053 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1054 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1055 * "If this bit is set, STCunit will have LRA as replacement
1056 * policy. [...] This bit must be reset. LRA replacement
1057 * policy is not supported."
1058 */
1059 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1060 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1061 }
1062
6b26c86d
DV		 1063 if (INTEL_INFO(dev)->gen >= 6)
1064 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1065
040d2baa 1066 if (HAS_L3_DPF(dev))
35a85ac6 1067 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1068
7225342a 1069 return init_workarounds_ring(ring);
8187a2b7
ZN		 1070}
1071
a4872ba6 1072static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1073{
b45305fc 1074 struct drm_device *dev = ring->dev;
3e78998a
BW		 1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076
1077 if (dev_priv->semaphore_obj) {
1078 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1079 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1080 dev_priv->semaphore_obj = NULL;
1081 }
b45305fc 1082
9b1136d5 1083 intel_fini_pipe_control(ring);
c6df541c
CW		 1084}
1085
3e78998a
BW		 1086static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1087 unsigned int num_dwords)
1088{
1089#define MBOX_UPDATE_DWORDS 8
1090 struct drm_device *dev = signaller->dev;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
1092 struct intel_engine_cs *waiter;
1093 int i, ret, num_rings;
1094
1095 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1096 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1097#undef MBOX_UPDATE_DWORDS
1098
1099 ret = intel_ring_begin(signaller, num_dwords);
1100 if (ret)
1101 return ret;
1102
1103 for_each_ring(waiter, dev_priv, i) {
6259cead 1104 u32 seqno;
3e78998a
BW		 1105 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1106 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1107 continue;
1108
6259cead
JH		 1109 seqno = i915_gem_request_get_seqno(
1110 signaller->outstanding_lazy_request);
3e78998a
BW		 1111 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1112 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1113 PIPE_CONTROL_QW_WRITE |
1114 PIPE_CONTROL_FLUSH_ENABLE);
1115 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1116 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1117 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1118 intel_ring_emit(signaller, 0);
1119 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1120 MI_SEMAPHORE_TARGET(waiter->id));
1121 intel_ring_emit(signaller, 0);
1122 }
1123
1124 return 0;
1125}
1126
1127static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1128 unsigned int num_dwords)
1129{
1130#define MBOX_UPDATE_DWORDS 6
1131 struct drm_device *dev = signaller->dev;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 struct intel_engine_cs *waiter;
1134 int i, ret, num_rings;
1135
1136 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1137 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1138#undef MBOX_UPDATE_DWORDS
1139
1140 ret = intel_ring_begin(signaller, num_dwords);
1141 if (ret)
1142 return ret;
1143
1144 for_each_ring(waiter, dev_priv, i) {
6259cead 1145 u32 seqno;
3e78998a
BW		 1146 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1147 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1148 continue;
1149
6259cead
JH		 1150 seqno = i915_gem_request_get_seqno(
1151 signaller->outstanding_lazy_request);
3e78998a
BW		 1152 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1153 MI_FLUSH_DW_OP_STOREDW);
1154 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1155 MI_FLUSH_DW_USE_GTT);
1156 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1157 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1158 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1159 MI_SEMAPHORE_TARGET(waiter->id));
1160 intel_ring_emit(signaller, 0);
1161 }
1162
1163 return 0;
1164}
1165
a4872ba6 1166static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1167 unsigned int num_dwords)
1ec14ad3 1168{
024a43e1
BW		 1169 struct drm_device *dev = signaller->dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1171 struct intel_engine_cs *useless;
a1444b79 1172 int i, ret, num_rings;
78325f2d 1173
a1444b79
BW		 1174#define MBOX_UPDATE_DWORDS 3
1175 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1176 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1177#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1178
1179 ret = intel_ring_begin(signaller, num_dwords);
1180 if (ret)
1181 return ret;
024a43e1 1182
78325f2d
BW		 1183 for_each_ring(useless, dev_priv, i) {
1184 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1185 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1186 u32 seqno = i915_gem_request_get_seqno(
1187 signaller->outstanding_lazy_request);
78325f2d
BW		 1188 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1189 intel_ring_emit(signaller, mbox_reg);
6259cead 1190 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1191 }
1192 }
024a43e1 1193
a1444b79
BW		 1194 /* If num_dwords was rounded, make sure the tail pointer is correct */
1195 if (num_rings % 2 == 0)
1196 intel_ring_emit(signaller, MI_NOOP);
1197
024a43e1 1198 return 0;
1ec14ad3
CW		 1199}
1200
c8c99b0f
BW		 1201/**
1202 * gen6_add_request - Update the semaphore mailbox registers
1203 *
1204 * @ring - ring that is adding a request
1205 * @seqno - return seqno stuck into the ring
1206 *
1207 * Update the mailbox registers in the *other* rings with the current seqno.
1208 * This acts like a signal in the canonical semaphore.
1209 */
1ec14ad3 1210static int
a4872ba6 1211gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1212{
024a43e1 1213 int ret;
52ed2325 1214
707d9cf9
BW		 1215 if (ring->semaphore.signal)
1216 ret = ring->semaphore.signal(ring, 4);
1217 else
1218 ret = intel_ring_begin(ring, 4);
1219
1ec14ad3
CW		 1220 if (ret)
1221 return ret;
1222
1ec14ad3
CW		 1223 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1224 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1225 intel_ring_emit(ring,
1226 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1227 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1228 __intel_ring_advance(ring);
1ec14ad3 1229
1ec14ad3
CW		 1230 return 0;
1231}
1232
f72b3435
MK		 1233static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1234 u32 seqno)
1235{
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 return dev_priv->last_seqno < seqno;
1238}
1239
c8c99b0f
BW		 1240/**
1241 * intel_ring_sync - sync the waiter to the signaller on seqno
1242 *
1243 * @waiter - ring that is waiting
1244 * @signaller - ring which has, or will signal
1245 * @seqno - seqno which the waiter will block on
1246 */
5ee426ca
BW		 1247
1248static int
1249gen8_ring_sync(struct intel_engine_cs *waiter,
1250 struct intel_engine_cs *signaller,
1251 u32 seqno)
1252{
1253 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1254 int ret;
1255
1256 ret = intel_ring_begin(waiter, 4);
1257 if (ret)
1258 return ret;
1259
1260 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1261 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1262 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1263 MI_SEMAPHORE_SAD_GTE_SDD);
1264 intel_ring_emit(waiter, seqno);
1265 intel_ring_emit(waiter,
1266 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1267 intel_ring_emit(waiter,
1268 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1269 intel_ring_advance(waiter);
1270 return 0;
1271}
1272
c8c99b0f 1273static int
a4872ba6
OM		 1274gen6_ring_sync(struct intel_engine_cs *waiter,
1275 struct intel_engine_cs *signaller,
686cb5f9 1276 u32 seqno)
1ec14ad3 1277{
c8c99b0f
BW		 1278 u32 dw1 = MI_SEMAPHORE_MBOX |
1279 MI_SEMAPHORE_COMPARE |
1280 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1281 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1282 int ret;
1ec14ad3 1283
1500f7ea
BW		 1284 /* Throughout all of the GEM code, seqno passed implies our current
1285 * seqno is >= the last seqno executed. However for hardware the
1286 * comparison is strictly greater than.
1287 */
1288 seqno -= 1;
1289
ebc348b2 1290 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1291
c8c99b0f 1292 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1293 if (ret)
1294 return ret;
1295
f72b3435
MK		 1296 /* If seqno wrap happened, omit the wait with no-ops */
1297 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1298 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1299 intel_ring_emit(waiter, seqno);
1300 intel_ring_emit(waiter, 0);
1301 intel_ring_emit(waiter, MI_NOOP);
1302 } else {
1303 intel_ring_emit(waiter, MI_NOOP);
1304 intel_ring_emit(waiter, MI_NOOP);
1305 intel_ring_emit(waiter, MI_NOOP);
1306 intel_ring_emit(waiter, MI_NOOP);
1307 }
c8c99b0f 1308 intel_ring_advance(waiter);
1ec14ad3
CW		 1309
1310 return 0;
1311}
1312
c6df541c
CW		 1313#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1314do { \
fcbc34e4
KG		 1315 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1316 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1317 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1318 intel_ring_emit(ring__, 0); \
1319 intel_ring_emit(ring__, 0); \
1320} while (0)
1321
1322static int
a4872ba6 1323pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1324{
18393f63 1325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1326 int ret;
1327
1328 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1329 * incoherent with writes to memory, i.e. completely fubar,
1330 * so we need to use PIPE_NOTIFY instead.
1331 *
1332 * However, we also need to workaround the qword write
1333 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1334 * memory before requesting an interrupt.
1335 */
1336 ret = intel_ring_begin(ring, 32);
1337 if (ret)
1338 return ret;
1339
fcbc34e4 1340 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1341 PIPE_CONTROL_WRITE_FLUSH |
1342 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1343 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1344 intel_ring_emit(ring,
1345 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1346 intel_ring_emit(ring, 0);
1347 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1348 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1349 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1350 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1351 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1352 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1353 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1354 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1355 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1356 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1357 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1358
fcbc34e4 1359 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1360 PIPE_CONTROL_WRITE_FLUSH |
1361 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1362 PIPE_CONTROL_NOTIFY);
0d1aacac 1363 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1364 intel_ring_emit(ring,
1365 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1366 intel_ring_emit(ring, 0);
09246732 1367 __intel_ring_advance(ring);
c6df541c 1368
c6df541c
CW		 1369 return 0;
1370}
1371
4cd53c0c 1372static u32
a4872ba6 1373gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1374{
4cd53c0c
DV		 1375 /* Workaround to force correct ordering between irq and seqno writes on
1376 * ivb (and maybe also on snb) by reading from a CS register (like
1377 * ACTHD) before reading the status page. */
50877445
CW		 1378 if (!lazy_coherency) {
1379 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1380 POSTING_READ(RING_ACTHD(ring->mmio_base));
1381 }
1382
4cd53c0c
DV		 1383 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1384}
1385
8187a2b7 1386static u32
a4872ba6 1387ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1388{
1ec14ad3
CW		 1389 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1390}
1391
b70ec5bf 1392static void
a4872ba6 1393ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1394{
1395 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1396}
1397
c6df541c 1398static u32
a4872ba6 1399pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1400{
0d1aacac 1401 return ring->scratch.cpu_page[0];
c6df541c
CW		 1402}
1403
b70ec5bf 1404static void
a4872ba6 1405pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1406{
0d1aacac 1407 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1408}
1409
e48d8634 1410static bool
a4872ba6 1411gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1412{
1413 struct drm_device *dev = ring->dev;
4640c4ff 1414 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1415 unsigned long flags;
e48d8634 1416
7cd512f1 1417 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1418 return false;
1419
7338aefa 1420 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1421 if (ring->irq_refcount++ == 0)
480c8033 1422 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1423 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1424
1425 return true;
1426}
1427
1428static void
a4872ba6 1429gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1430{
1431 struct drm_device *dev = ring->dev;
4640c4ff 1432 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1433 unsigned long flags;
e48d8634 1434
7338aefa 1435 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1436 if (--ring->irq_refcount == 0)
480c8033 1437 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1438 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1439}
1440
b13c2b96 1441static bool
a4872ba6 1442i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1443{
78501eac 1444 struct drm_device *dev = ring->dev;
4640c4ff 1445 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1446 unsigned long flags;
62fdfeaf 1447
7cd512f1 1448 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1449 return false;
1450
7338aefa 1451 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1452 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1453 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1454 I915_WRITE(IMR, dev_priv->irq_mask);
1455 POSTING_READ(IMR);
1456 }
7338aefa 1457 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1458
1459 return true;
62fdfeaf
EA		 1460}
1461
8187a2b7 1462static void
a4872ba6 1463i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1464{
78501eac 1465 struct drm_device *dev = ring->dev;
4640c4ff 1466 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1467 unsigned long flags;
62fdfeaf 1468
7338aefa 1469 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1470 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1471 dev_priv->irq_mask |= ring->irq_enable_mask;
1472 I915_WRITE(IMR, dev_priv->irq_mask);
1473 POSTING_READ(IMR);
1474 }
7338aefa 1475 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1476}
1477
c2798b19 1478static bool
a4872ba6 1479i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1480{
1481 struct drm_device *dev = ring->dev;
4640c4ff 1482 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1483 unsigned long flags;
c2798b19 1484
7cd512f1 1485 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1486 return false;
1487
7338aefa 1488 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1489 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1490 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1491 I915_WRITE16(IMR, dev_priv->irq_mask);
1492 POSTING_READ16(IMR);
1493 }
7338aefa 1494 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1495
1496 return true;
1497}
1498
1499static void
a4872ba6 1500i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1501{
1502 struct drm_device *dev = ring->dev;
4640c4ff 1503 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1504 unsigned long flags;
c2798b19 1505
7338aefa 1506 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1507 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1508 dev_priv->irq_mask |= ring->irq_enable_mask;
1509 I915_WRITE16(IMR, dev_priv->irq_mask);
1510 POSTING_READ16(IMR);
1511 }
7338aefa 1512 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1513}
1514
b72f3acb 1515static int
a4872ba6 1516bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1517 u32 invalidate_domains,
1518 u32 flush_domains)
d1b851fc 1519{
b72f3acb
CW		 1520 int ret;
1521
b72f3acb
CW		 1522 ret = intel_ring_begin(ring, 2);
1523 if (ret)
1524 return ret;
1525
1526 intel_ring_emit(ring, MI_FLUSH);
1527 intel_ring_emit(ring, MI_NOOP);
1528 intel_ring_advance(ring);
1529 return 0;
d1b851fc
ZN		 1530}
1531
3cce469c 1532static int
a4872ba6 1533i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1534{
3cce469c
CW		 1535 int ret;
1536
1537 ret = intel_ring_begin(ring, 4);
1538 if (ret)
1539 return ret;
6f392d54 1540
3cce469c
CW		 1541 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1542 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1543 intel_ring_emit(ring,
1544 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1545 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1546 __intel_ring_advance(ring);
d1b851fc 1547
3cce469c 1548 return 0;
d1b851fc
ZN		 1549}
1550
0f46832f 1551static bool
a4872ba6 1552gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1553{
1554 struct drm_device *dev = ring->dev;
4640c4ff 1555 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1556 unsigned long flags;
0f46832f 1557
7cd512f1
DV		 1558 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1559 return false;
0f46832f 1560
7338aefa 1561 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1562 if (ring->irq_refcount++ == 0) {
040d2baa 1563 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1564 I915_WRITE_IMR(ring,
1565 ~(ring->irq_enable_mask |
35a85ac6 1566 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1567 else
1568 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1569 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1570 }
7338aefa 1571 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1572
1573 return true;
1574}
1575
1576static void
a4872ba6 1577gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1578{
1579 struct drm_device *dev = ring->dev;
4640c4ff 1580 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1581 unsigned long flags;
0f46832f 1582
7338aefa 1583 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1584 if (--ring->irq_refcount == 0) {
040d2baa 1585 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1586 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1587 else
1588 I915_WRITE_IMR(ring, ~0);
480c8033 1589 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1590 }
7338aefa 1591 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1592}
1593
a19d2933 1594static bool
a4872ba6 1595hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1596{
1597 struct drm_device *dev = ring->dev;
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 unsigned long flags;
1600
7cd512f1 1601 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1602 return false;
1603
59cdb63d 1604 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1605 if (ring->irq_refcount++ == 0) {
a19d2933 1606 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1607 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1608 }
59cdb63d 1609 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1610
1611 return true;
1612}
1613
1614static void
a4872ba6 1615hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1616{
1617 struct drm_device *dev = ring->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 unsigned long flags;
1620
59cdb63d 1621 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1622 if (--ring->irq_refcount == 0) {
a19d2933 1623 I915_WRITE_IMR(ring, ~0);
480c8033 1624 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1625 }
59cdb63d 1626 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1627}
1628
abd58f01 1629static bool
a4872ba6 1630gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1631{
1632 struct drm_device *dev = ring->dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 unsigned long flags;
1635
7cd512f1 1636 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1637 return false;
1638
1639 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1640 if (ring->irq_refcount++ == 0) {
1641 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1642 I915_WRITE_IMR(ring,
1643 ~(ring->irq_enable_mask |
1644 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1645 } else {
1646 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1647 }
1648 POSTING_READ(RING_IMR(ring->mmio_base));
1649 }
1650 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1651
1652 return true;
1653}
1654
1655static void
a4872ba6 1656gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1657{
1658 struct drm_device *dev = ring->dev;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660 unsigned long flags;
1661
1662 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1663 if (--ring->irq_refcount == 0) {
1664 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1665 I915_WRITE_IMR(ring,
1666 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1667 } else {
1668 I915_WRITE_IMR(ring, ~0);
1669 }
1670 POSTING_READ(RING_IMR(ring->mmio_base));
1671 }
1672 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1673}
1674
d1b851fc 1675static int
a4872ba6 1676i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1677 u64 offset, u32 length,
d7d4eedd 1678 unsigned flags)
d1b851fc 1679{
e1f99ce6 1680 int ret;
78501eac 1681
e1f99ce6
CW		 1682 ret = intel_ring_begin(ring, 2);
1683 if (ret)
1684 return ret;
1685
78501eac 1686 intel_ring_emit(ring,
65f56876
CW		 1687 MI_BATCH_BUFFER_START |
1688 MI_BATCH_GTT |
d7d4eedd 1689 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1690 intel_ring_emit(ring, offset);
78501eac
CW		 1691 intel_ring_advance(ring);
1692
d1b851fc
ZN		 1693 return 0;
1694}
1695
b45305fc
DV		 1696/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1697#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1698#define I830_TLB_ENTRIES (2)
1699#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1700static int
a4872ba6 1701i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1702 u64 offset, u32 len,
d7d4eedd 1703 unsigned flags)
62fdfeaf 1704{
c4d69da1 1705 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1706 int ret;
62fdfeaf 1707
c4d69da1
CW		 1708 ret = intel_ring_begin(ring, 6);
1709 if (ret)
1710 return ret;
62fdfeaf 1711
c4d69da1
CW		 1712 /* Evict the invalid PTE TLBs */
1713 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1714 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1715 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1716 intel_ring_emit(ring, cs_offset);
1717 intel_ring_emit(ring, 0xdeadbeef);
1718 intel_ring_emit(ring, MI_NOOP);
1719 intel_ring_advance(ring);
b45305fc 1720
c4d69da1 1721 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1722 if (len > I830_BATCH_LIMIT)
1723 return -ENOSPC;
1724
c4d69da1 1725 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1726 if (ret)
1727 return ret;
c4d69da1
CW		 1728
1729 /* Blit the batch (which has now all relocs applied) to the
1730 * stable batch scratch bo area (so that the CS never
1731 * stumbles over its tlb invalidation bug) ...
1732 */
1733 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1734 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1735 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1736 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1737 intel_ring_emit(ring, 4096);
1738 intel_ring_emit(ring, offset);
c4d69da1 1739
b45305fc 1740 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1741 intel_ring_emit(ring, MI_NOOP);
1742 intel_ring_advance(ring);
b45305fc
DV		 1743
1744 /* ... and execute it. */
c4d69da1 1745 offset = cs_offset;
b45305fc 1746 }
e1f99ce6 1747
c4d69da1
CW		 1748 ret = intel_ring_begin(ring, 4);
1749 if (ret)
1750 return ret;
1751
1752 intel_ring_emit(ring, MI_BATCH_BUFFER);
1753 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1754 intel_ring_emit(ring, offset + len - 8);
1755 intel_ring_emit(ring, MI_NOOP);
1756 intel_ring_advance(ring);
1757
fb3256da
DV		 1758 return 0;
1759}
1760
1761static int
a4872ba6 1762i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1763 u64 offset, u32 len,
d7d4eedd 1764 unsigned flags)
fb3256da
DV		 1765{
1766 int ret;
1767
1768 ret = intel_ring_begin(ring, 2);
1769 if (ret)
1770 return ret;
1771
65f56876 1772 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1773 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1774 intel_ring_advance(ring);
62fdfeaf 1775
62fdfeaf
EA		 1776 return 0;
1777}
1778
a4872ba6 1779static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1780{
05394f39 1781 struct drm_i915_gem_object *obj;
62fdfeaf 1782
8187a2b7
ZN		 1783 obj = ring->status_page.obj;
1784 if (obj == NULL)
62fdfeaf 1785 return;
62fdfeaf 1786
9da3da66 1787 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1788 i915_gem_object_ggtt_unpin(obj);
05394f39 1789 drm_gem_object_unreference(&obj->base);
8187a2b7 1790 ring->status_page.obj = NULL;
62fdfeaf
EA		 1791}
1792
a4872ba6 1793static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1794{
05394f39 1795 struct drm_i915_gem_object *obj;
62fdfeaf 1796
e3efda49 1797 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1798 unsigned flags;
e3efda49 1799 int ret;
e4ffd173 1800
e3efda49
CW		 1801 obj = i915_gem_alloc_object(ring->dev, 4096);
1802 if (obj == NULL) {
1803 DRM_ERROR("Failed to allocate status page\n");
1804 return -ENOMEM;
1805 }
62fdfeaf 1806
e3efda49
CW		 1807 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1808 if (ret)
1809 goto err_unref;
1810
1f767e02
CW		 1811 flags = 0;
1812 if (!HAS_LLC(ring->dev))
1813 /* On g33, we cannot place HWS above 256MiB, so
1814 * restrict its pinning to the low mappable arena.
1815 * Though this restriction is not documented for
1816 * gen4, gen5, or byt, they also behave similarly
1817 * and hang if the HWS is placed at the top of the
1818 * GTT. To generalise, it appears that all !llc
1819 * platforms have issues with us placing the HWS
1820 * above the mappable region (even though we never
1821 * actualy map it).
1822 */
1823 flags |= PIN_MAPPABLE;
1824 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1825 if (ret) {
1826err_unref:
1827 drm_gem_object_unreference(&obj->base);
1828 return ret;
1829 }
1830
1831 ring->status_page.obj = obj;
1832 }
62fdfeaf 1833
f343c5f6 1834 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1835 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1836 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1837
8187a2b7
ZN		 1838 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1839 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1840
1841 return 0;
62fdfeaf
EA		 1842}
1843
a4872ba6 1844static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1845{
1846 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1847
1848 if (!dev_priv->status_page_dmah) {
1849 dev_priv->status_page_dmah =
1850 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1851 if (!dev_priv->status_page_dmah)
1852 return -ENOMEM;
1853 }
1854
6b8294a4
CW		 1855 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1856 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1857
1858 return 0;
1859}
1860
7ba717cf 1861void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1862{
2919d291 1863 iounmap(ringbuf->virtual_start);
7ba717cf 1864 ringbuf->virtual_start = NULL;
2919d291 1865 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1866}
1867
1868int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1869 struct intel_ringbuffer *ringbuf)
1870{
1871 struct drm_i915_private *dev_priv = to_i915(dev);
1872 struct drm_i915_gem_object *obj = ringbuf->obj;
1873 int ret;
1874
1875 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1876 if (ret)
1877 return ret;
1878
1879 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1880 if (ret) {
1881 i915_gem_object_ggtt_unpin(obj);
1882 return ret;
1883 }
1884
1885 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1886 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1887 if (ringbuf->virtual_start == NULL) {
1888 i915_gem_object_ggtt_unpin(obj);
1889 return -EINVAL;
1890 }
1891
1892 return 0;
1893}
1894
1895void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1896{
2919d291
OM		 1897 drm_gem_object_unreference(&ringbuf->obj->base);
1898 ringbuf->obj = NULL;
1899}
1900
84c2377f
OM		 1901int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1902 struct intel_ringbuffer *ringbuf)
62fdfeaf 1903{
05394f39 1904 struct drm_i915_gem_object *obj;
62fdfeaf 1905
ebc052e0
CW		 1906 obj = NULL;
1907 if (!HAS_LLC(dev))
93b0a4e0 1908 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1909 if (obj == NULL)
93b0a4e0 1910 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1911 if (obj == NULL)
1912 return -ENOMEM;
8187a2b7 1913
24f3a8cf
AG		 1914 /* mark ring buffers as read-only from GPU side by default */
1915 obj->gt_ro = 1;
1916
93b0a4e0 1917 ringbuf->obj = obj;
e3efda49 1918
7ba717cf 1919 return 0;
e3efda49
CW		 1920}
1921
1922static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1923 struct intel_engine_cs *ring)
e3efda49 1924{
bfc882b4 1925 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1926 int ret;
1927
bfc882b4
DV		 1928 WARN_ON(ring->buffer);
1929
1930 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1931 if (!ringbuf)
1932 return -ENOMEM;
1933 ring->buffer = ringbuf;
8ee14975 1934
e3efda49
CW		 1935 ring->dev = dev;
1936 INIT_LIST_HEAD(&ring->active_list);
1937 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1938 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1939 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1940 ringbuf->ring = ring;
ebc348b2 1941 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1942
1943 init_waitqueue_head(&ring->irq_queue);
1944
1945 if (I915_NEED_GFX_HWS(dev)) {
1946 ret = init_status_page(ring);
1947 if (ret)
8ee14975 1948 goto error;
e3efda49
CW		 1949 } else {
1950 BUG_ON(ring->id != RCS);
1951 ret = init_phys_status_page(ring);
1952 if (ret)
8ee14975 1953 goto error;
e3efda49
CW		 1954 }
1955
bfc882b4 1956 WARN_ON(ringbuf->obj);
7ba717cf 1957
bfc882b4
DV		 1958 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1959 if (ret) {
1960 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1961 ring->name, ret);
1962 goto error;
1963 }
1964
1965 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1966 if (ret) {
1967 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1968 ring->name, ret);
1969 intel_destroy_ringbuffer_obj(ringbuf);
1970 goto error;
e3efda49 1971 }
62fdfeaf 1972
55249baa
CW		 1973 /* Workaround an erratum on the i830 which causes a hang if
1974 * the TAIL pointer points to within the last 2 cachelines
1975 * of the buffer.
1976 */
93b0a4e0 1977 ringbuf->effective_size = ringbuf->size;
e3efda49 1978 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1979 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1980
44e895a8
BV		 1981 ret = i915_cmd_parser_init_ring(ring);
1982 if (ret)
8ee14975
OM		 1983 goto error;
1984
8ee14975 1985 return 0;
351e3db2 1986
8ee14975
OM		 1987error:
1988 kfree(ringbuf);
1989 ring->buffer = NULL;
1990 return ret;
62fdfeaf
EA		 1991}
1992
a4872ba6 1993void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1994{
6402c330
JH		 1995 struct drm_i915_private *dev_priv;
1996 struct intel_ringbuffer *ringbuf;
33626e6a 1997
93b0a4e0 1998 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1999 return;
2000
6402c330
JH		 2001 dev_priv = to_i915(ring->dev);
2002 ringbuf = ring->buffer;
2003
e3efda49 2004 intel_stop_ring_buffer(ring);
de8f0a50 2005 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2006
7ba717cf 2007 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2008 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2009 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2010
8d19215b
ZN		 2011 if (ring->cleanup)
2012 ring->cleanup(ring);
2013
78501eac 2014 cleanup_status_page(ring);
44e895a8
BV		 2015
2016 i915_cmd_parser_fini_ring(ring);
8ee14975 2017
93b0a4e0 2018 kfree(ringbuf);
8ee14975 2019 ring->buffer = NULL;
62fdfeaf
EA		 2020}
2021
a4872ba6 2022static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 2023{
93b0a4e0 2024 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2025 struct drm_i915_gem_request *request;
a71d8d94
CW		 2026 int ret;
2027
ebd0fd4b
DG		 2028 if (intel_ring_space(ringbuf) >= n)
2029 return 0;
a71d8d94
CW		 2030
2031 list_for_each_entry(request, &ring->request_list, list) {
72f95afa 2032 if (__intel_ring_space(request->postfix, ringbuf->tail,
82e104cc 2033 ringbuf->size) >= n) {
a71d8d94
CW		 2034 break;
2035 }
a71d8d94
CW		 2036 }
2037
a4b3a571 2038 if (&request->list == &ring->request_list)
a71d8d94
CW		 2039 return -ENOSPC;
2040
a4b3a571 2041 ret = i915_wait_request(request);
a71d8d94
CW		 2042 if (ret)
2043 return ret;
2044
1cf0ba14 2045 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 2046
2047 return 0;
2048}
2049
a4872ba6 2050static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 2051{
78501eac 2052 struct drm_device *dev = ring->dev;
cae5852d 2053 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 2054 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 2055 unsigned long end;
a71d8d94 2056 int ret;
c7dca47b 2057
a71d8d94
CW		 2058 ret = intel_ring_wait_request(ring, n);
2059 if (ret != -ENOSPC)
2060 return ret;
2061
09246732
CW		 2062 /* force the tail write in case we have been skipping them */
2063 __intel_ring_advance(ring);
2064
63ed2cb2
DV		 2065 /* With GEM the hangcheck timer should kick us out of the loop,
2066 * leaving it early runs the risk of corrupting GEM state (due
2067 * to running on almost untested codepaths). But on resume
2068 * timers don't work yet, so prevent a complete hang in that
2069 * case by choosing an insanely large timeout. */
2070 end = jiffies + 60 * HZ;
e6bfaf85 2071
ebd0fd4b 2072 ret = 0;
dcfe0506 2073 trace_i915_ring_wait_begin(ring);
8187a2b7 2074 do {
ebd0fd4b
DG		 2075 if (intel_ring_space(ringbuf) >= n)
2076 break;
93b0a4e0 2077 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 2078 if (intel_ring_space(ringbuf) >= n)
dcfe0506 2079 break;
62fdfeaf 2080
e60a0b10 2081 msleep(1);
d6b2c790 2082
dcfe0506
CW		 2083 if (dev_priv->mm.interruptible && signal_pending(current)) {
2084 ret = -ERESTARTSYS;
2085 break;
2086 }
2087
33196ded
DV		 2088 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2089 dev_priv->mm.interruptible);
d6b2c790 2090 if (ret)
dcfe0506
CW		 2091 break;
2092
2093 if (time_after(jiffies, end)) {
2094 ret = -EBUSY;
2095 break;
2096 }
2097 } while (1);
db53a302 2098 trace_i915_ring_wait_end(ring);
dcfe0506 2099 return ret;
8187a2b7 2100}
62fdfeaf 2101
a4872ba6 2102static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2103{
2104 uint32_t __iomem *virt;
93b0a4e0
OM		 2105 struct intel_ringbuffer *ringbuf = ring->buffer;
2106 int rem = ringbuf->size - ringbuf->tail;
3e960501 2107
93b0a4e0 2108 if (ringbuf->space < rem) {
3e960501
CW		 2109 int ret = ring_wait_for_space(ring, rem);
2110 if (ret)
2111 return ret;
2112 }
2113
93b0a4e0 2114 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2115 rem /= 4;
2116 while (rem--)
2117 iowrite32(MI_NOOP, virt++);
2118
93b0a4e0 2119 ringbuf->tail = 0;
ebd0fd4b 2120 intel_ring_update_space(ringbuf);
3e960501
CW		 2121
2122 return 0;
2123}
2124
a4872ba6 2125int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2126{
a4b3a571 2127 struct drm_i915_gem_request *req;
3e960501
CW		 2128 int ret;
2129
2130 /* We need to add any requests required to flush the objects and ring */
6259cead 2131 if (ring->outstanding_lazy_request) {
9400ae5c 2132 ret = i915_add_request(ring);
3e960501
CW		 2133 if (ret)
2134 return ret;
2135 }
2136
2137 /* Wait upon the last request to be completed */
2138 if (list_empty(&ring->request_list))
2139 return 0;
2140
a4b3a571 2141 req = list_entry(ring->request_list.prev,
3e960501 2142 struct drm_i915_gem_request,
a4b3a571 2143 list);
3e960501 2144
a4b3a571 2145 return i915_wait_request(req);
3e960501
CW		 2146}
2147
9d773091 2148static int
6259cead 2149intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2150{
9eba5d4a
JH		 2151 int ret;
2152 struct drm_i915_gem_request *request;
67e2937b 2153 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2154
6259cead 2155 if (ring->outstanding_lazy_request)
9d773091 2156 return 0;
3c0e234c 2157
aaeb1ba0 2158 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2159 if (request == NULL)
2160 return -ENOMEM;
3c0e234c 2161
abfe262a 2162 kref_init(&request->ref);
ff79e857 2163 request->ring = ring;
67e2937b 2164 request->uniq = dev_private->request_uniq++;
abfe262a 2165
6259cead 2166 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2167 if (ret) {
2168 kfree(request);
2169 return ret;
3c0e234c
CW		 2170 }
2171
6259cead 2172 ring->outstanding_lazy_request = request;
9eba5d4a 2173 return 0;
9d773091
CW		 2174}
2175
a4872ba6 2176static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2177 int bytes)
cbcc80df 2178{
93b0a4e0 2179 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2180 int ret;
2181
93b0a4e0 2182 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2183 ret = intel_wrap_ring_buffer(ring);
2184 if (unlikely(ret))
2185 return ret;
2186 }
2187
93b0a4e0 2188 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2189 ret = ring_wait_for_space(ring, bytes);
2190 if (unlikely(ret))
2191 return ret;
2192 }
2193
cbcc80df
MK		 2194 return 0;
2195}
2196
a4872ba6 2197int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2198 int num_dwords)
8187a2b7 2199{
4640c4ff 2200 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2201 int ret;
78501eac 2202
33196ded
DV		 2203 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2204 dev_priv->mm.interruptible);
de2b9985
DV		 2205 if (ret)
2206 return ret;
21dd3734 2207
304d695c
CW		 2208 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2209 if (ret)
2210 return ret;
2211
9d773091 2212 /* Preallocate the olr before touching the ring */
6259cead 2213 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2214 if (ret)
2215 return ret;
2216
ee1b1e5e 2217 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2218 return 0;
8187a2b7 2219}
78501eac 2220
753b1ad4 2221/* Align the ring tail to a cacheline boundary */
a4872ba6 2222int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2223{
ee1b1e5e 2224 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2225 int ret;
2226
2227 if (num_dwords == 0)
2228 return 0;
2229
18393f63 2230 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2231 ret = intel_ring_begin(ring, num_dwords);
2232 if (ret)
2233 return ret;
2234
2235 while (num_dwords--)
2236 intel_ring_emit(ring, MI_NOOP);
2237
2238 intel_ring_advance(ring);
2239
2240 return 0;
2241}
2242
a4872ba6 2243void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2244{
3b2cc8ab
OM		 2245 struct drm_device *dev = ring->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2247
6259cead 2248 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2249
3b2cc8ab 2250 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2251 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2252 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2253 if (HAS_VEBOX(dev))
5020150b 2254 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2255 }
d97ed339 2256
f7e98ad4 2257 ring->set_seqno(ring, seqno);
92cab734 2258 ring->hangcheck.seqno = seqno;
8187a2b7 2259}
62fdfeaf 2260
a4872ba6 2261static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2262 u32 value)
881f47b6 2263{
4640c4ff 2264 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2265
2266 /* Every tail move must follow the sequence below */
12f55818
CW		 2267
2268 /* Disable notification that the ring is IDLE. The GT
2269 * will then assume that it is busy and bring it out of rc6.
2270 */
0206e353 2271 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2272 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2273
2274 /* Clear the context id. Here be magic! */
2275 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2276
12f55818 2277 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2278 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2279 GEN6_BSD_SLEEP_INDICATOR) == 0,
2280 50))
2281 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2282
12f55818 2283 /* Now that the ring is fully powered up, update the tail */
0206e353 2284 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2285 POSTING_READ(RING_TAIL(ring->mmio_base));
2286
2287 /* Let the ring send IDLE messages to the GT again,
2288 * and so let it sleep to conserve power when idle.
2289 */
0206e353 2290 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2291 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2292}
2293
a4872ba6 2294static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2295 u32 invalidate, u32 flush)
881f47b6 2296{
71a77e07 2297 uint32_t cmd;
b72f3acb
CW		 2298 int ret;
2299
b72f3acb
CW		 2300 ret = intel_ring_begin(ring, 4);
2301 if (ret)
2302 return ret;
2303
71a77e07 2304 cmd = MI_FLUSH_DW;
075b3bba
BW		 2305 if (INTEL_INFO(ring->dev)->gen >= 8)
2306 cmd += 1;
9a289771
JB		 2307 /*
2308 * Bspec vol 1c.5 - video engine command streamer:
2309 * "If ENABLED, all TLBs will be invalidated once the flush
2310 * operation is complete. This bit is only valid when the
2311 * Post-Sync Operation field is a value of 1h or 3h."
2312 */
71a77e07 2313 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2314 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2315 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2316 intel_ring_emit(ring, cmd);
9a289771 2317 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2318 if (INTEL_INFO(ring->dev)->gen >= 8) {
2319 intel_ring_emit(ring, 0); /* upper addr */
2320 intel_ring_emit(ring, 0); /* value */
2321 } else {
2322 intel_ring_emit(ring, 0);
2323 intel_ring_emit(ring, MI_NOOP);
2324 }
b72f3acb
CW		 2325 intel_ring_advance(ring);
2326 return 0;
881f47b6
XH		 2327}
2328
1c7a0623 2329static int
a4872ba6 2330gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2331 u64 offset, u32 len,
1c7a0623
BW		 2332 unsigned flags)
2333{
896ab1a5 2334 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2335 int ret;
2336
2337 ret = intel_ring_begin(ring, 4);
2338 if (ret)
2339 return ret;
2340
2341 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2342 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2343 intel_ring_emit(ring, lower_32_bits(offset));
2344 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2345 intel_ring_emit(ring, MI_NOOP);
2346 intel_ring_advance(ring);
2347
2348 return 0;
2349}
2350
d7d4eedd 2351static int
a4872ba6 2352hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2353 u64 offset, u32 len,
d7d4eedd
CW		 2354 unsigned flags)
2355{
2356 int ret;
2357
2358 ret = intel_ring_begin(ring, 2);
2359 if (ret)
2360 return ret;
2361
2362 intel_ring_emit(ring,
77072258
CW		 2363 MI_BATCH_BUFFER_START |
2364 (flags & I915_DISPATCH_SECURE ?
2365 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2366 /* bit0-7 is the length on GEN6+ */
2367 intel_ring_emit(ring, offset);
2368 intel_ring_advance(ring);
2369
2370 return 0;
2371}
2372
881f47b6 2373static int
a4872ba6 2374gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2375 u64 offset, u32 len,
d7d4eedd 2376 unsigned flags)
881f47b6 2377{
0206e353 2378 int ret;
ab6f8e32 2379
0206e353
AJ		 2380 ret = intel_ring_begin(ring, 2);
2381 if (ret)
2382 return ret;
e1f99ce6 2383
d7d4eedd
CW		 2384 intel_ring_emit(ring,
2385 MI_BATCH_BUFFER_START |
2386 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2387 /* bit0-7 is the length on GEN6+ */
2388 intel_ring_emit(ring, offset);
2389 intel_ring_advance(ring);
ab6f8e32 2390
0206e353 2391 return 0;
881f47b6
XH		 2392}
2393
549f7365
CW		 2394/* Blitter support (SandyBridge+) */
2395
a4872ba6 2396static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2397 u32 invalidate, u32 flush)
8d19215b 2398{
fd3da6c9 2399 struct drm_device *dev = ring->dev;
1d73c2a8 2400 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2401 uint32_t cmd;
b72f3acb
CW		 2402 int ret;
2403
6a233c78 2404 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2405 if (ret)
2406 return ret;
2407
71a77e07 2408 cmd = MI_FLUSH_DW;
075b3bba
BW		 2409 if (INTEL_INFO(ring->dev)->gen >= 8)
2410 cmd += 1;
9a289771
JB		 2411 /*
2412 * Bspec vol 1c.3 - blitter engine command streamer:
2413 * "If ENABLED, all TLBs will be invalidated once the flush
2414 * operation is complete. This bit is only valid when the
2415 * Post-Sync Operation field is a value of 1h or 3h."
2416 */
71a77e07 2417 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2418 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2419 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2420 intel_ring_emit(ring, cmd);
9a289771 2421 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2422 if (INTEL_INFO(ring->dev)->gen >= 8) {
2423 intel_ring_emit(ring, 0); /* upper addr */
2424 intel_ring_emit(ring, 0); /* value */
2425 } else {
2426 intel_ring_emit(ring, 0);
2427 intel_ring_emit(ring, MI_NOOP);
2428 }
b72f3acb 2429 intel_ring_advance(ring);
fd3da6c9 2430
1d73c2a8
RV		 2431 if (!invalidate && flush) {
2432 if (IS_GEN7(dev))
2433 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2434 else if (IS_BROADWELL(dev))
2435 dev_priv->fbc.need_sw_cache_clean = true;
2436 }
fd3da6c9 2437
b72f3acb 2438 return 0;
8d19215b
ZN		 2439}
2440
5c1143bb
XH		 2441int intel_init_render_ring_buffer(struct drm_device *dev)
2442{
4640c4ff 2443 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2444 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2445 struct drm_i915_gem_object *obj;
2446 int ret;
5c1143bb 2447
59465b5f
DV		 2448 ring->name = "render ring";
2449 ring->id = RCS;
2450 ring->mmio_base = RENDER_RING_BASE;
2451
707d9cf9 2452 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2453 if (i915_semaphore_is_enabled(dev)) {
2454 obj = i915_gem_alloc_object(dev, 4096);
2455 if (obj == NULL) {
2456 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2457 i915.semaphores = 0;
2458 } else {
2459 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2460 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2461 if (ret != 0) {
2462 drm_gem_object_unreference(&obj->base);
2463 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2464 i915.semaphores = 0;
2465 } else
2466 dev_priv->semaphore_obj = obj;
2467 }
2468 }
7225342a 2469
8f0e2b9d 2470 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2471 ring->add_request = gen6_add_request;
2472 ring->flush = gen8_render_ring_flush;
2473 ring->irq_get = gen8_ring_get_irq;
2474 ring->irq_put = gen8_ring_put_irq;
2475 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2476 ring->get_seqno = gen6_ring_get_seqno;
2477 ring->set_seqno = ring_set_seqno;
2478 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2479 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2480 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2481 ring->semaphore.signal = gen8_rcs_signal;
2482 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2483 }
2484 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2485 ring->add_request = gen6_add_request;
4772eaeb 2486 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2487 if (INTEL_INFO(dev)->gen == 6)
b3111509 2488 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2489 ring->irq_get = gen6_ring_get_irq;
2490 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2491 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2492 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2493 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2494 if (i915_semaphore_is_enabled(dev)) {
2495 ring->semaphore.sync_to = gen6_ring_sync;
2496 ring->semaphore.signal = gen6_signal;
2497 /*
2498 * The current semaphore is only applied on pre-gen8
2499 * platform. And there is no VCS2 ring on the pre-gen8
2500 * platform. So the semaphore between RCS and VCS2 is
2501 * initialized as INVALID. Gen8 will initialize the
2502 * sema between VCS2 and RCS later.
2503 */
2504 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2505 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2506 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2507 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2508 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2509 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2510 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2511 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2512 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2513 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2514 }
c6df541c
CW		 2515 } else if (IS_GEN5(dev)) {
2516 ring->add_request = pc_render_add_request;
46f0f8d1 2517 ring->flush = gen4_render_ring_flush;
c6df541c 2518 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2519 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2520 ring->irq_get = gen5_ring_get_irq;
2521 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2522 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2523 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2524 } else {
8620a3a9 2525 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2526 if (INTEL_INFO(dev)->gen < 4)
2527 ring->flush = gen2_render_ring_flush;
2528 else
2529 ring->flush = gen4_render_ring_flush;
59465b5f 2530 ring->get_seqno = ring_get_seqno;
b70ec5bf 2531 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2532 if (IS_GEN2(dev)) {
2533 ring->irq_get = i8xx_ring_get_irq;
2534 ring->irq_put = i8xx_ring_put_irq;
2535 } else {
2536 ring->irq_get = i9xx_ring_get_irq;
2537 ring->irq_put = i9xx_ring_put_irq;
2538 }
e3670319 2539 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2540 }
59465b5f 2541 ring->write_tail = ring_write_tail;
707d9cf9 2542
d7d4eedd
CW		 2543 if (IS_HASWELL(dev))
2544 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2545 else if (IS_GEN8(dev))
2546 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2547 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2548 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2549 else if (INTEL_INFO(dev)->gen >= 4)
2550 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2551 else if (IS_I830(dev) || IS_845G(dev))
2552 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2553 else
2554 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2555 ring->init_hw = init_render_ring;
59465b5f
DV		 2556 ring->cleanup = render_ring_cleanup;
2557
b45305fc
DV		 2558 /* Workaround batchbuffer to combat CS tlb bug. */
2559 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2560 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2561 if (obj == NULL) {
2562 DRM_ERROR("Failed to allocate batch bo\n");
2563 return -ENOMEM;
2564 }
2565
be1fa129 2566 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2567 if (ret != 0) {
2568 drm_gem_object_unreference(&obj->base);
2569 DRM_ERROR("Failed to ping batch bo\n");
2570 return ret;
2571 }
2572
0d1aacac
CW		 2573 ring->scratch.obj = obj;
2574 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2575 }
2576
99be1dfe
DV		 2577 ret = intel_init_ring_buffer(dev, ring);
2578 if (ret)
2579 return ret;
2580
2581 if (INTEL_INFO(dev)->gen >= 5) {
2582 ret = intel_init_pipe_control(ring);
2583 if (ret)
2584 return ret;
2585 }
2586
2587 return 0;
5c1143bb
XH		 2588}
2589
2590int intel_init_bsd_ring_buffer(struct drm_device *dev)
2591{
4640c4ff 2592 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2593 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2594
58fa3835
DV		 2595 ring->name = "bsd ring";
2596 ring->id = VCS;
2597
0fd2c201 2598 ring->write_tail = ring_write_tail;
780f18c8 2599 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2600 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2601 /* gen6 bsd needs a special wa for tail updates */
2602 if (IS_GEN6(dev))
2603 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2604 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2605 ring->add_request = gen6_add_request;
2606 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2607 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2608 if (INTEL_INFO(dev)->gen >= 8) {
2609 ring->irq_enable_mask =
2610 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2611 ring->irq_get = gen8_ring_get_irq;
2612 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2613 ring->dispatch_execbuffer =
2614 gen8_ring_dispatch_execbuffer;
707d9cf9 2615 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2616 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2617 ring->semaphore.signal = gen8_xcs_signal;
2618 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2619 }
abd58f01
BW		 2620 } else {
2621 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2622 ring->irq_get = gen6_ring_get_irq;
2623 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2624 ring->dispatch_execbuffer =
2625 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2626 if (i915_semaphore_is_enabled(dev)) {
2627 ring->semaphore.sync_to = gen6_ring_sync;
2628 ring->semaphore.signal = gen6_signal;
2629 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2630 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2631 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2632 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2633 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2634 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2635 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2636 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2637 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2638 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2639 }
abd58f01 2640 }
58fa3835
DV		 2641 } else {
2642 ring->mmio_base = BSD_RING_BASE;
58fa3835 2643 ring->flush = bsd_ring_flush;
8620a3a9 2644 ring->add_request = i9xx_add_request;
58fa3835 2645 ring->get_seqno = ring_get_seqno;
b70ec5bf 2646 ring->set_seqno = ring_set_seqno;
e48d8634 2647 if (IS_GEN5(dev)) {
cc609d5d 2648 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2649 ring->irq_get = gen5_ring_get_irq;
2650 ring->irq_put = gen5_ring_put_irq;
2651 } else {
e3670319 2652 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2653 ring->irq_get = i9xx_ring_get_irq;
2654 ring->irq_put = i9xx_ring_put_irq;
2655 }
fb3256da 2656 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2657 }
ecfe00d8 2658 ring->init_hw = init_ring_common;
58fa3835 2659
1ec14ad3 2660 return intel_init_ring_buffer(dev, ring);
5c1143bb 2661}
549f7365 2662
845f74a7 2663/**
62659920 2664 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2665 */
2666int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2667{
2668 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2669 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2670
f7b64236 2671 ring->name = "bsd2 ring";
845f74a7
ZY		 2672 ring->id = VCS2;
2673
2674 ring->write_tail = ring_write_tail;
2675 ring->mmio_base = GEN8_BSD2_RING_BASE;
2676 ring->flush = gen6_bsd_ring_flush;
2677 ring->add_request = gen6_add_request;
2678 ring->get_seqno = gen6_ring_get_seqno;
2679 ring->set_seqno = ring_set_seqno;
2680 ring->irq_enable_mask =
2681 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2682 ring->irq_get = gen8_ring_get_irq;
2683 ring->irq_put = gen8_ring_put_irq;
2684 ring->dispatch_execbuffer =
2685 gen8_ring_dispatch_execbuffer;
3e78998a 2686 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2687 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2688 ring->semaphore.signal = gen8_xcs_signal;
2689 GEN8_RING_SEMAPHORE_INIT;
2690 }
ecfe00d8 2691 ring->init_hw = init_ring_common;
845f74a7
ZY		 2692
2693 return intel_init_ring_buffer(dev, ring);
2694}
2695
549f7365
CW		 2696int intel_init_blt_ring_buffer(struct drm_device *dev)
2697{
4640c4ff 2698 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2699 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2700
3535d9dd
DV		 2701 ring->name = "blitter ring";
2702 ring->id = BCS;
2703
2704 ring->mmio_base = BLT_RING_BASE;
2705 ring->write_tail = ring_write_tail;
ea251324 2706 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2707 ring->add_request = gen6_add_request;
2708 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2709 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2710 if (INTEL_INFO(dev)->gen >= 8) {
2711 ring->irq_enable_mask =
2712 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2713 ring->irq_get = gen8_ring_get_irq;
2714 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2715 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2716 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2717 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2718 ring->semaphore.signal = gen8_xcs_signal;
2719 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2720 }
abd58f01
BW		 2721 } else {
2722 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2723 ring->irq_get = gen6_ring_get_irq;
2724 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2725 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2726 if (i915_semaphore_is_enabled(dev)) {
2727 ring->semaphore.signal = gen6_signal;
2728 ring->semaphore.sync_to = gen6_ring_sync;
2729 /*
2730 * The current semaphore is only applied on pre-gen8
2731 * platform. And there is no VCS2 ring on the pre-gen8
2732 * platform. So the semaphore between BCS and VCS2 is
2733 * initialized as INVALID. Gen8 will initialize the
2734 * sema between BCS and VCS2 later.
2735 */
2736 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2737 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2738 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2739 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2740 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2741 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2742 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2743 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2744 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2745 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2746 }
abd58f01 2747 }
ecfe00d8 2748 ring->init_hw = init_ring_common;
549f7365 2749
1ec14ad3 2750 return intel_init_ring_buffer(dev, ring);
549f7365 2751}
a7b9761d 2752
9a8a2213
BW		 2753int intel_init_vebox_ring_buffer(struct drm_device *dev)
2754{
4640c4ff 2755 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2756 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2757
2758 ring->name = "video enhancement ring";
2759 ring->id = VECS;
2760
2761 ring->mmio_base = VEBOX_RING_BASE;
2762 ring->write_tail = ring_write_tail;
2763 ring->flush = gen6_ring_flush;
2764 ring->add_request = gen6_add_request;
2765 ring->get_seqno = gen6_ring_get_seqno;
2766 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2767
2768 if (INTEL_INFO(dev)->gen >= 8) {
2769 ring->irq_enable_mask =
40c499f9 2770 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2771 ring->irq_get = gen8_ring_get_irq;
2772 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2773 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2774 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2775 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2776 ring->semaphore.signal = gen8_xcs_signal;
2777 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2778 }
abd58f01
BW		 2779 } else {
2780 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2781 ring->irq_get = hsw_vebox_get_irq;
2782 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2783 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2784 if (i915_semaphore_is_enabled(dev)) {
2785 ring->semaphore.sync_to = gen6_ring_sync;
2786 ring->semaphore.signal = gen6_signal;
2787 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2788 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2789 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2790 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2791 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2792 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2793 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2794 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2795 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2796 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2797 }
abd58f01 2798 }
ecfe00d8 2799 ring->init_hw = init_ring_common;
9a8a2213
BW		 2800
2801 return intel_init_ring_buffer(dev, ring);
2802}
2803
a7b9761d 2804int
a4872ba6 2805intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2806{
2807 int ret;
2808
2809 if (!ring->gpu_caches_dirty)
2810 return 0;
2811
2812 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2813 if (ret)
2814 return ret;
2815
2816 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2817
2818 ring->gpu_caches_dirty = false;
2819 return 0;
2820}
2821
2822int
a4872ba6 2823intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2824{
2825 uint32_t flush_domains;
2826 int ret;
2827
2828 flush_domains = 0;
2829 if (ring->gpu_caches_dirty)
2830 flush_domains = I915_GEM_GPU_DOMAINS;
2831
2832 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2833 if (ret)
2834 return ret;
2835
2836 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2837
2838 ring->gpu_caches_dirty = false;
2839 return 0;
2840}
e3efda49
CW		 2841
2842void
a4872ba6 2843intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2844{
2845 int ret;
2846
2847 if (!intel_ring_initialized(ring))
2848 return;
2849
2850 ret = intel_ring_idle(ring);
2851 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2852 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2853 ring->name, ret);
2854
2855 stop_ring(ring);
2856}
Linux kernel - Deliverables
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