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drm/i915: Remove obsolete seqno parameter from 'i915_add_request'
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
1cf0ba14 55 int space = head - (tail + I915_RING_FREE_SPACE);
c7dca47b 56 if (space < 0)
1cf0ba14 57 space += size;
c7dca47b
CW		 58 return space;
59}
60
82e104cc 61int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 62{
82e104cc
OM		 63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
1cf0ba14
CW		 65}
66
82e104cc 67bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 68{
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71}
09246732 72
a4872ba6 73void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 74{
93b0a4e0
OM		 75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 77 if (intel_ring_stopped(ring))
09246732 78 return;
93b0a4e0 79 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 80}
81
b72f3acb 82static int
a4872ba6 83gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 84 u32 invalidate_domains,
85 u32 flush_domains)
86{
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
31b14c9f 91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106}
107
108static int
a4872ba6 109gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 110 u32 invalidate_domains,
111 u32 flush_domains)
62fdfeaf 112{
78501eac 113 struct drm_device *dev = ring->dev;
6f392d54 114 u32 cmd;
b72f3acb 115 int ret;
6f392d54 116
36d527de
CW		 117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 147 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
62fdfeaf 150
36d527de
CW		 151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
70eac33e 154
36d527de
CW		 155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
b72f3acb 158
36d527de
CW		 159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
b72f3acb
CW		 162
163 return 0;
8187a2b7
ZN		 164}
165
8d315287
JB		 166/**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203static int
a4872ba6 204intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 205{
18393f63 206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236}
237
238static int
a4872ba6 239gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 240 u32 invalidate_domains, u32 flush_domains)
241{
242 u32 flags = 0;
18393f63 243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 244 int ret;
245
b3111509
PZ		 246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
8d315287
JB		 251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
7d54a904
CW		 255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
97f209bc 262 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
3ac78313 274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 275 }
8d315287 276
6c6cf5aa 277 ret = intel_ring_begin(ring, 4);
8d315287
JB		 278 if (ret)
279 return ret;
280
6c6cf5aa 281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 284 intel_ring_emit(ring, 0);
8d315287
JB		 285 intel_ring_advance(ring);
286
287 return 0;
288}
289
f3987631 290static int
a4872ba6 291gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 292{
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307}
308
a4872ba6 309static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 310{
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
37c1d94f 316 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 317 if (ret)
318 return ret;
fd3da6c9
RV		 319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
37c1d94f
VS		 323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330}
331
4772eaeb 332static int
a4872ba6 333gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 334 u32 invalidate_domains, u32 flush_domains)
335{
336 u32 flags = 0;
18393f63 337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 338 int ret;
339
f3987631
PZ		 340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
4772eaeb
PZ		 350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
365 /*
366 * TLB invalidate requires a post-sync write.
367 */
368 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 369 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631
PZ		 370
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 375 }
376
377 ret = intel_ring_begin(ring, 4);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring, flags);
b9e1faa7 383 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 384 intel_ring_emit(ring, 0);
385 intel_ring_advance(ring);
386
9688ecad 387 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 388 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
389
4772eaeb
PZ		 390 return 0;
391}
392
884ceace
KG		 393static int
394gen8_emit_pipe_control(struct intel_engine_cs *ring,
395 u32 flags, u32 scratch_addr)
396{
397 int ret;
398
399 ret = intel_ring_begin(ring, 6);
400 if (ret)
401 return ret;
402
403 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring, flags);
405 intel_ring_emit(ring, scratch_addr);
406 intel_ring_emit(ring, 0);
407 intel_ring_emit(ring, 0);
408 intel_ring_emit(ring, 0);
409 intel_ring_advance(ring);
410
411 return 0;
412}
413
a5f3d68e 414static int
a4872ba6 415gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 416 u32 invalidate_domains, u32 flush_domains)
417{
418 u32 flags = 0;
18393f63 419 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 420 int ret;
a5f3d68e
BW		 421
422 flags |= PIPE_CONTROL_CS_STALL;
423
424 if (flush_domains) {
425 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
426 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
427 }
428 if (invalidate_domains) {
429 flags |= PIPE_CONTROL_TLB_INVALIDATE;
430 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_QW_WRITE;
436 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 437
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret = gen8_emit_pipe_control(ring,
440 PIPE_CONTROL_CS_STALL |
441 PIPE_CONTROL_STALL_AT_SCOREBOARD,
442 0);
443 if (ret)
444 return ret;
a5f3d68e
BW		 445 }
446
c5ad011d
RV		 447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
448 if (ret)
449 return ret;
450
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
453
454 return 0;
a5f3d68e
BW		 455}
456
a4872ba6 457static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 458 u32 value)
d46eefa2 459{
4640c4ff 460 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 461 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 462}
463
a4872ba6 464u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 465{
4640c4ff 466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 467 u64 acthd;
8187a2b7 468
50877445
CW		 469 if (INTEL_INFO(ring->dev)->gen >= 8)
470 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
471 RING_ACTHD_UDW(ring->mmio_base));
472 else if (INTEL_INFO(ring->dev)->gen >= 4)
473 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
474 else
475 acthd = I915_READ(ACTHD);
476
477 return acthd;
8187a2b7
ZN		 478}
479
a4872ba6 480static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 481{
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 addr;
484
485 addr = dev_priv->status_page_dmah->busaddr;
486 if (INTEL_INFO(ring->dev)->gen >= 4)
487 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
488 I915_WRITE(HWS_PGA, addr);
489}
490
a4872ba6 491static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 492{
9991ae78 493 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 494
9991ae78
CW		 495 if (!IS_GEN2(ring->dev)) {
496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 497 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
502 */
503 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
504 return false;
9991ae78
CW		 505 }
506 }
b7884eb4 507
7f2ab699 508 I915_WRITE_CTL(ring, 0);
570ef608 509 I915_WRITE_HEAD(ring, 0);
78501eac 510 ring->write_tail(ring, 0);
8187a2b7 511
9991ae78
CW		 512 if (!IS_GEN2(ring->dev)) {
513 (void)I915_READ_CTL(ring);
514 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
515 }
a51435a3 516
9991ae78
CW		 517 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
518}
8187a2b7 519
a4872ba6 520static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 521{
522 struct drm_device *dev = ring->dev;
523 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 524 struct intel_ringbuffer *ringbuf = ring->buffer;
525 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 526 int ret = 0;
527
528 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
529
530 if (!stop_ring(ring)) {
531 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
534 ring->name,
535 I915_READ_CTL(ring),
536 I915_READ_HEAD(ring),
537 I915_READ_TAIL(ring),
538 I915_READ_START(ring));
8187a2b7 539
9991ae78 540 if (!stop_ring(ring)) {
6fd0d56e
CW		 541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
543 ring->name,
544 I915_READ_CTL(ring),
545 I915_READ_HEAD(ring),
546 I915_READ_TAIL(ring),
547 I915_READ_START(ring));
9991ae78
CW		 548 ret = -EIO;
549 goto out;
6fd0d56e 550 }
8187a2b7
ZN		 551 }
552
9991ae78
CW		 553 if (I915_NEED_GFX_HWS(dev))
554 intel_ring_setup_status_page(ring);
555 else
556 ring_setup_phys_status_page(ring);
557
ece4a17d
JK		 558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring);
560
0d8957c8
DV		 561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
f343c5f6 565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 566
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
573
7f2ab699 574 I915_WRITE_CTL(ring,
93b0a4e0 575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 576 | RING_VALID);
8187a2b7 577
8187a2b7 578 /* If the head is still not zero, the ring is dead */
f01db988 579 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 580 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 581 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 582 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
584 ring->name,
585 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
586 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
587 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 588 ret = -EIO;
589 goto out;
8187a2b7
ZN		 590 }
591
5c6c6003
CW		 592 ringbuf->head = I915_READ_HEAD(ring);
593 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
594 ringbuf->space = intel_ring_space(ringbuf);
595 ringbuf->last_retired_head = -1;
1ec14ad3 596
50f018df
CW		 597 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
598
b7884eb4 599out:
c8d9a590 600 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 601
602 return ret;
8187a2b7
ZN		 603}
604
9b1136d5
OM		 605void
606intel_fini_pipe_control(struct intel_engine_cs *ring)
607{
608 struct drm_device *dev = ring->dev;
609
610 if (ring->scratch.obj == NULL)
611 return;
612
613 if (INTEL_INFO(dev)->gen >= 5) {
614 kunmap(sg_page(ring->scratch.obj->pages->sgl));
615 i915_gem_object_ggtt_unpin(ring->scratch.obj);
616 }
617
618 drm_gem_object_unreference(&ring->scratch.obj->base);
619 ring->scratch.obj = NULL;
620}
621
622int
623intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 624{
c6df541c
CW		 625 int ret;
626
0d1aacac 627 if (ring->scratch.obj)
c6df541c
CW		 628 return 0;
629
0d1aacac
CW		 630 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
631 if (ring->scratch.obj == NULL) {
c6df541c
CW		 632 DRM_ERROR("Failed to allocate seqno page\n");
633 ret = -ENOMEM;
634 goto err;
635 }
e4ffd173 636
a9cc726c
DV		 637 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
638 if (ret)
639 goto err_unref;
c6df541c 640
1ec9e26d 641 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 642 if (ret)
643 goto err_unref;
644
0d1aacac
CW		 645 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
646 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
647 if (ring->scratch.cpu_page == NULL) {
56b085a0 648 ret = -ENOMEM;
c6df541c 649 goto err_unpin;
56b085a0 650 }
c6df541c 651
2b1086cc 652 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 653 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 654 return 0;
655
656err_unpin:
d7f46fc4 657 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 658err_unref:
0d1aacac 659 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 660err:
c6df541c
CW		 661 return ret;
662}
663
771b9a53
MT		 664static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
665 struct intel_context *ctx)
86d7f238 666{
7225342a 667 int ret, i;
888b5995
AS		 668 struct drm_device *dev = ring->dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 670 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 671
7225342a
MK		 672 if (WARN_ON(w->count == 0))
673 return 0;
888b5995 674
7225342a
MK		 675 ring->gpu_caches_dirty = true;
676 ret = intel_ring_flush_all_caches(ring);
677 if (ret)
678 return ret;
888b5995 679
22a916aa 680 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 681 if (ret)
682 return ret;
683
22a916aa 684 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 685 for (i = 0; i < w->count; i++) {
7225342a
MK		 686 intel_ring_emit(ring, w->reg[i].addr);
687 intel_ring_emit(ring, w->reg[i].value);
688 }
22a916aa 689 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 690
691 intel_ring_advance(ring);
692
693 ring->gpu_caches_dirty = true;
694 ret = intel_ring_flush_all_caches(ring);
695 if (ret)
696 return ret;
888b5995 697
7225342a 698 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 699
7225342a 700 return 0;
86d7f238
AS		 701}
702
7225342a
MK		 703static int wa_add(struct drm_i915_private *dev_priv,
704 const u32 addr, const u32 val, const u32 mask)
705{
706 const u32 idx = dev_priv->workarounds.count;
707
708 if (WARN_ON(idx >= I915_MAX_WA_REGS))
709 return -ENOSPC;
710
711 dev_priv->workarounds.reg[idx].addr = addr;
712 dev_priv->workarounds.reg[idx].value = val;
713 dev_priv->workarounds.reg[idx].mask = mask;
714
715 dev_priv->workarounds.count++;
716
717 return 0;
86d7f238
AS		 718}
719
7225342a
MK		 720#define WA_REG(addr, val, mask) { \
721 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
722 if (r) \
723 return r; \
724 }
725
726#define WA_SET_BIT_MASKED(addr, mask) \
727 WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
728
729#define WA_CLR_BIT_MASKED(addr, mask) \
730 WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
731
732#define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
733#define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
734
735#define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
736
00e1e623 737static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 738{
888b5995
AS		 739 struct drm_device *dev = ring->dev;
740 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 741
86d7f238 742 /* WaDisablePartialInstShootdown:bdw */
101b376d 743 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 744 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
745 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
746 STALL_DOP_GATING_DISABLE);
86d7f238 747
101b376d 748 /* WaDisableDopClockGating:bdw */
7225342a
MK		 749 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
750 DOP_CLOCK_GATING_DISABLE);
86d7f238 751
7225342a
MK		 752 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
753 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 754
755 /* Use Force Non-Coherent whenever executing a 3D context. This is a
756 * workaround for for a possible hang in the unlikely event a TLB
757 * invalidation occurs during a PSD flush.
758 */
da09654d 759 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
7225342a
MK		 760 WA_SET_BIT_MASKED(HDC_CHICKEN0,
761 HDC_FORCE_NON_COHERENT |
762 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238
AS		 763
764 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 765 WA_SET_BIT_MASKED(CACHE_MODE_1,
766 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 767
768 /*
769 * BSpec recommends 8x4 when MSAA is used,
770 * however in practice 16x4 seems fastest.
771 *
772 * Note that PS/WM thread counts depend on the WIZ hashing
773 * disable bit, which we don't touch here, but it's good
774 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
775 */
7225342a
MK		 776 WA_SET_BIT_MASKED(GEN7_GT_MODE,
777 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
888b5995 778
86d7f238
AS		 779 return 0;
780}
781
00e1e623
VS		 782static int chv_init_workarounds(struct intel_engine_cs *ring)
783{
00e1e623
VS		 784 struct drm_device *dev = ring->dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786
00e1e623 787 /* WaDisablePartialInstShootdown:chv */
00e1e623 788 /* WaDisableThreadStallDopClockGating:chv */
7225342a 789 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 790 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
791 STALL_DOP_GATING_DISABLE);
00e1e623 792
95289009
AS		 793 /* Use Force Non-Coherent whenever executing a 3D context. This is a
794 * workaround for a possible hang in the unlikely event a TLB
795 * invalidation occurs during a PSD flush.
796 */
797 /* WaForceEnableNonCoherent:chv */
798 /* WaHdcDisableFetchWhenMasked:chv */
799 WA_SET_BIT_MASKED(HDC_CHICKEN0,
800 HDC_FORCE_NON_COHERENT |
801 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
802
7225342a
MK		 803 return 0;
804}
805
771b9a53 806int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 807{
808 struct drm_device *dev = ring->dev;
809 struct drm_i915_private *dev_priv = dev->dev_private;
810
811 WARN_ON(ring->id != RCS);
812
813 dev_priv->workarounds.count = 0;
814
815 if (IS_BROADWELL(dev))
816 return bdw_init_workarounds(ring);
817
818 if (IS_CHERRYVIEW(dev))
819 return chv_init_workarounds(ring);
00e1e623
VS		 820
821 return 0;
822}
823
a4872ba6 824static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 825{
78501eac 826 struct drm_device *dev = ring->dev;
1ec14ad3 827 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 828 int ret = init_ring_common(ring);
9c33baa6
KZ		 829 if (ret)
830 return ret;
a69ffdbf 831
61a563a2
AG		 832 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
833 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 834 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 835
836 /* We need to disable the AsyncFlip performance optimisations in order
837 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
838 * programmed to '1' on all products.
8693a824 839 *
b3f797ac 840 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 841 */
fbdcb068 842 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 843 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
844
f05bb0c7 845 /* Required for the hardware to program scanline values for waiting */
01fa0302 846 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 847 if (INTEL_INFO(dev)->gen == 6)
848 I915_WRITE(GFX_MODE,
aa83e30d 849 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 850
01fa0302 851 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 852 if (IS_GEN7(dev))
853 I915_WRITE(GFX_MODE_GEN7,
01fa0302 854 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 855 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 856
8d315287 857 if (INTEL_INFO(dev)->gen >= 5) {
9b1136d5 858 ret = intel_init_pipe_control(ring);
c6df541c
CW		 859 if (ret)
860 return ret;
861 }
862
5e13a0c5 863 if (IS_GEN6(dev)) {
3a69ddd6
KG		 864 /* From the Sandybridge PRM, volume 1 part 3, page 24:
865 * "If this bit is set, STCunit will have LRA as replacement
866 * policy. [...] This bit must be reset. LRA replacement
867 * policy is not supported."
868 */
869 I915_WRITE(CACHE_MODE_0,
5e13a0c5 870 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 871 }
872
6b26c86d
DV		 873 if (INTEL_INFO(dev)->gen >= 6)
874 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 875
040d2baa 876 if (HAS_L3_DPF(dev))
35a85ac6 877 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 878
7225342a 879 return init_workarounds_ring(ring);
8187a2b7
ZN		 880}
881
a4872ba6 882static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 883{
b45305fc 884 struct drm_device *dev = ring->dev;
3e78998a
BW		 885 struct drm_i915_private *dev_priv = dev->dev_private;
886
887 if (dev_priv->semaphore_obj) {
888 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
889 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
890 dev_priv->semaphore_obj = NULL;
891 }
b45305fc 892
9b1136d5 893 intel_fini_pipe_control(ring);
c6df541c
CW		 894}
895
3e78998a
BW		 896static int gen8_rcs_signal(struct intel_engine_cs *signaller,
897 unsigned int num_dwords)
898{
899#define MBOX_UPDATE_DWORDS 8
900 struct drm_device *dev = signaller->dev;
901 struct drm_i915_private *dev_priv = dev->dev_private;
902 struct intel_engine_cs *waiter;
903 int i, ret, num_rings;
904
905 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
906 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
907#undef MBOX_UPDATE_DWORDS
908
909 ret = intel_ring_begin(signaller, num_dwords);
910 if (ret)
911 return ret;
912
913 for_each_ring(waiter, dev_priv, i) {
6259cead 914 u32 seqno;
3e78998a
BW		 915 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
916 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
917 continue;
918
6259cead
JH		 919 seqno = i915_gem_request_get_seqno(
920 signaller->outstanding_lazy_request);
3e78998a
BW		 921 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
922 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
923 PIPE_CONTROL_QW_WRITE |
924 PIPE_CONTROL_FLUSH_ENABLE);
925 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
926 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 927 intel_ring_emit(signaller, seqno);
3e78998a
BW		 928 intel_ring_emit(signaller, 0);
929 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
930 MI_SEMAPHORE_TARGET(waiter->id));
931 intel_ring_emit(signaller, 0);
932 }
933
934 return 0;
935}
936
937static int gen8_xcs_signal(struct intel_engine_cs *signaller,
938 unsigned int num_dwords)
939{
940#define MBOX_UPDATE_DWORDS 6
941 struct drm_device *dev = signaller->dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
943 struct intel_engine_cs *waiter;
944 int i, ret, num_rings;
945
946 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
947 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
948#undef MBOX_UPDATE_DWORDS
949
950 ret = intel_ring_begin(signaller, num_dwords);
951 if (ret)
952 return ret;
953
954 for_each_ring(waiter, dev_priv, i) {
6259cead 955 u32 seqno;
3e78998a
BW		 956 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
957 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
958 continue;
959
6259cead
JH		 960 seqno = i915_gem_request_get_seqno(
961 signaller->outstanding_lazy_request);
3e78998a
BW		 962 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
963 MI_FLUSH_DW_OP_STOREDW);
964 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
965 MI_FLUSH_DW_USE_GTT);
966 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 967 intel_ring_emit(signaller, seqno);
3e78998a
BW		 968 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
969 MI_SEMAPHORE_TARGET(waiter->id));
970 intel_ring_emit(signaller, 0);
971 }
972
973 return 0;
974}
975
a4872ba6 976static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 977 unsigned int num_dwords)
1ec14ad3 978{
024a43e1
BW		 979 struct drm_device *dev = signaller->dev;
980 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 981 struct intel_engine_cs *useless;
a1444b79 982 int i, ret, num_rings;
78325f2d 983
a1444b79
BW		 984#define MBOX_UPDATE_DWORDS 3
985 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
986 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
987#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 988
989 ret = intel_ring_begin(signaller, num_dwords);
990 if (ret)
991 return ret;
024a43e1 992
78325f2d
BW		 993 for_each_ring(useless, dev_priv, i) {
994 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
995 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 996 u32 seqno = i915_gem_request_get_seqno(
997 signaller->outstanding_lazy_request);
78325f2d
BW		 998 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
999 intel_ring_emit(signaller, mbox_reg);
6259cead 1000 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1001 }
1002 }
024a43e1 1003
a1444b79
BW		 1004 /* If num_dwords was rounded, make sure the tail pointer is correct */
1005 if (num_rings % 2 == 0)
1006 intel_ring_emit(signaller, MI_NOOP);
1007
024a43e1 1008 return 0;
1ec14ad3
CW		 1009}
1010
c8c99b0f
BW		 1011/**
1012 * gen6_add_request - Update the semaphore mailbox registers
1013 *
1014 * @ring - ring that is adding a request
1015 * @seqno - return seqno stuck into the ring
1016 *
1017 * Update the mailbox registers in the *other* rings with the current seqno.
1018 * This acts like a signal in the canonical semaphore.
1019 */
1ec14ad3 1020static int
a4872ba6 1021gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1022{
024a43e1 1023 int ret;
52ed2325 1024
707d9cf9
BW		 1025 if (ring->semaphore.signal)
1026 ret = ring->semaphore.signal(ring, 4);
1027 else
1028 ret = intel_ring_begin(ring, 4);
1029
1ec14ad3
CW		 1030 if (ret)
1031 return ret;
1032
1ec14ad3
CW		 1033 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1034 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1035 intel_ring_emit(ring,
1036 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1037 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1038 __intel_ring_advance(ring);
1ec14ad3 1039
1ec14ad3
CW		 1040 return 0;
1041}
1042
f72b3435
MK		 1043static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1044 u32 seqno)
1045{
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 return dev_priv->last_seqno < seqno;
1048}
1049
c8c99b0f
BW		 1050/**
1051 * intel_ring_sync - sync the waiter to the signaller on seqno
1052 *
1053 * @waiter - ring that is waiting
1054 * @signaller - ring which has, or will signal
1055 * @seqno - seqno which the waiter will block on
1056 */
5ee426ca
BW		 1057
1058static int
1059gen8_ring_sync(struct intel_engine_cs *waiter,
1060 struct intel_engine_cs *signaller,
1061 u32 seqno)
1062{
1063 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1064 int ret;
1065
1066 ret = intel_ring_begin(waiter, 4);
1067 if (ret)
1068 return ret;
1069
1070 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1071 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1072 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1073 MI_SEMAPHORE_SAD_GTE_SDD);
1074 intel_ring_emit(waiter, seqno);
1075 intel_ring_emit(waiter,
1076 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1077 intel_ring_emit(waiter,
1078 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1079 intel_ring_advance(waiter);
1080 return 0;
1081}
1082
c8c99b0f 1083static int
a4872ba6
OM		 1084gen6_ring_sync(struct intel_engine_cs *waiter,
1085 struct intel_engine_cs *signaller,
686cb5f9 1086 u32 seqno)
1ec14ad3 1087{
c8c99b0f
BW		 1088 u32 dw1 = MI_SEMAPHORE_MBOX |
1089 MI_SEMAPHORE_COMPARE |
1090 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1091 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1092 int ret;
1ec14ad3 1093
1500f7ea
BW		 1094 /* Throughout all of the GEM code, seqno passed implies our current
1095 * seqno is >= the last seqno executed. However for hardware the
1096 * comparison is strictly greater than.
1097 */
1098 seqno -= 1;
1099
ebc348b2 1100 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1101
c8c99b0f 1102 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1103 if (ret)
1104 return ret;
1105
f72b3435
MK		 1106 /* If seqno wrap happened, omit the wait with no-ops */
1107 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1108 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1109 intel_ring_emit(waiter, seqno);
1110 intel_ring_emit(waiter, 0);
1111 intel_ring_emit(waiter, MI_NOOP);
1112 } else {
1113 intel_ring_emit(waiter, MI_NOOP);
1114 intel_ring_emit(waiter, MI_NOOP);
1115 intel_ring_emit(waiter, MI_NOOP);
1116 intel_ring_emit(waiter, MI_NOOP);
1117 }
c8c99b0f 1118 intel_ring_advance(waiter);
1ec14ad3
CW		 1119
1120 return 0;
1121}
1122
c6df541c
CW		 1123#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1124do { \
fcbc34e4
KG		 1125 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1126 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1127 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1128 intel_ring_emit(ring__, 0); \
1129 intel_ring_emit(ring__, 0); \
1130} while (0)
1131
1132static int
a4872ba6 1133pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1134{
18393f63 1135 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1136 int ret;
1137
1138 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1139 * incoherent with writes to memory, i.e. completely fubar,
1140 * so we need to use PIPE_NOTIFY instead.
1141 *
1142 * However, we also need to workaround the qword write
1143 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1144 * memory before requesting an interrupt.
1145 */
1146 ret = intel_ring_begin(ring, 32);
1147 if (ret)
1148 return ret;
1149
fcbc34e4 1150 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1151 PIPE_CONTROL_WRITE_FLUSH |
1152 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1153 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1154 intel_ring_emit(ring,
1155 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1156 intel_ring_emit(ring, 0);
1157 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1158 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1159 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1160 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1161 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1162 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1163 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1164 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1165 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1166 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1167 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1168
fcbc34e4 1169 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1170 PIPE_CONTROL_WRITE_FLUSH |
1171 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1172 PIPE_CONTROL_NOTIFY);
0d1aacac 1173 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1174 intel_ring_emit(ring,
1175 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1176 intel_ring_emit(ring, 0);
09246732 1177 __intel_ring_advance(ring);
c6df541c 1178
c6df541c
CW		 1179 return 0;
1180}
1181
4cd53c0c 1182static u32
a4872ba6 1183gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1184{
4cd53c0c
DV		 1185 /* Workaround to force correct ordering between irq and seqno writes on
1186 * ivb (and maybe also on snb) by reading from a CS register (like
1187 * ACTHD) before reading the status page. */
50877445
CW		 1188 if (!lazy_coherency) {
1189 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1190 POSTING_READ(RING_ACTHD(ring->mmio_base));
1191 }
1192
4cd53c0c
DV		 1193 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1194}
1195
8187a2b7 1196static u32
a4872ba6 1197ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1198{
1ec14ad3
CW		 1199 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1200}
1201
b70ec5bf 1202static void
a4872ba6 1203ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1204{
1205 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1206}
1207
c6df541c 1208static u32
a4872ba6 1209pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1210{
0d1aacac 1211 return ring->scratch.cpu_page[0];
c6df541c
CW		 1212}
1213
b70ec5bf 1214static void
a4872ba6 1215pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1216{
0d1aacac 1217 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1218}
1219
e48d8634 1220static bool
a4872ba6 1221gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1222{
1223 struct drm_device *dev = ring->dev;
4640c4ff 1224 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1225 unsigned long flags;
e48d8634 1226
7cd512f1 1227 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1228 return false;
1229
7338aefa 1230 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1231 if (ring->irq_refcount++ == 0)
480c8033 1232 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1233 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1234
1235 return true;
1236}
1237
1238static void
a4872ba6 1239gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1240{
1241 struct drm_device *dev = ring->dev;
4640c4ff 1242 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1243 unsigned long flags;
e48d8634 1244
7338aefa 1245 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1246 if (--ring->irq_refcount == 0)
480c8033 1247 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1248 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1249}
1250
b13c2b96 1251static bool
a4872ba6 1252i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1253{
78501eac 1254 struct drm_device *dev = ring->dev;
4640c4ff 1255 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1256 unsigned long flags;
62fdfeaf 1257
7cd512f1 1258 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1259 return false;
1260
7338aefa 1261 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1262 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1263 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1264 I915_WRITE(IMR, dev_priv->irq_mask);
1265 POSTING_READ(IMR);
1266 }
7338aefa 1267 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1268
1269 return true;
62fdfeaf
EA		 1270}
1271
8187a2b7 1272static void
a4872ba6 1273i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1274{
78501eac 1275 struct drm_device *dev = ring->dev;
4640c4ff 1276 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1277 unsigned long flags;
62fdfeaf 1278
7338aefa 1279 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1280 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1281 dev_priv->irq_mask |= ring->irq_enable_mask;
1282 I915_WRITE(IMR, dev_priv->irq_mask);
1283 POSTING_READ(IMR);
1284 }
7338aefa 1285 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1286}
1287
c2798b19 1288static bool
a4872ba6 1289i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1290{
1291 struct drm_device *dev = ring->dev;
4640c4ff 1292 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1293 unsigned long flags;
c2798b19 1294
7cd512f1 1295 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1296 return false;
1297
7338aefa 1298 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1299 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1300 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1301 I915_WRITE16(IMR, dev_priv->irq_mask);
1302 POSTING_READ16(IMR);
1303 }
7338aefa 1304 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1305
1306 return true;
1307}
1308
1309static void
a4872ba6 1310i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1311{
1312 struct drm_device *dev = ring->dev;
4640c4ff 1313 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1314 unsigned long flags;
c2798b19 1315
7338aefa 1316 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1317 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1318 dev_priv->irq_mask |= ring->irq_enable_mask;
1319 I915_WRITE16(IMR, dev_priv->irq_mask);
1320 POSTING_READ16(IMR);
1321 }
7338aefa 1322 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1323}
1324
a4872ba6 1325void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1326{
4593010b 1327 struct drm_device *dev = ring->dev;
4640c4ff 1328 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1329 u32 mmio = 0;
1330
1331 /* The ring status page addresses are no longer next to the rest of
1332 * the ring registers as of gen7.
1333 */
1334 if (IS_GEN7(dev)) {
1335 switch (ring->id) {
96154f2f 1336 case RCS:
4593010b
EA		 1337 mmio = RENDER_HWS_PGA_GEN7;
1338 break;
96154f2f 1339 case BCS:
4593010b
EA		 1340 mmio = BLT_HWS_PGA_GEN7;
1341 break;
77fe2ff3
ZY		 1342 /*
1343 * VCS2 actually doesn't exist on Gen7. Only shut up
1344 * gcc switch check warning
1345 */
1346 case VCS2:
96154f2f 1347 case VCS:
4593010b
EA		 1348 mmio = BSD_HWS_PGA_GEN7;
1349 break;
4a3dd19d 1350 case VECS:
9a8a2213
BW		 1351 mmio = VEBOX_HWS_PGA_GEN7;
1352 break;
4593010b
EA		 1353 }
1354 } else if (IS_GEN6(ring->dev)) {
1355 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1356 } else {
eb0d4b75 1357 /* XXX: gen8 returns to sanity */
4593010b
EA		 1358 mmio = RING_HWS_PGA(ring->mmio_base);
1359 }
1360
78501eac
CW		 1361 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1362 POSTING_READ(mmio);
884020bf 1363
dc616b89
DL		 1364 /*
1365 * Flush the TLB for this page
1366 *
1367 * FIXME: These two bits have disappeared on gen8, so a question
1368 * arises: do we still need this and if so how should we go about
1369 * invalidating the TLB?
1370 */
1371 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1372 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1373
1374 /* ring should be idle before issuing a sync flush*/
1375 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1376
884020bf
CW		 1377 I915_WRITE(reg,
1378 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1379 INSTPM_SYNC_FLUSH));
1380 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1381 1000))
1382 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1383 ring->name);
1384 }
8187a2b7
ZN		 1385}
1386
b72f3acb 1387static int
a4872ba6 1388bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1389 u32 invalidate_domains,
1390 u32 flush_domains)
d1b851fc 1391{
b72f3acb
CW		 1392 int ret;
1393
b72f3acb
CW		 1394 ret = intel_ring_begin(ring, 2);
1395 if (ret)
1396 return ret;
1397
1398 intel_ring_emit(ring, MI_FLUSH);
1399 intel_ring_emit(ring, MI_NOOP);
1400 intel_ring_advance(ring);
1401 return 0;
d1b851fc
ZN		 1402}
1403
3cce469c 1404static int
a4872ba6 1405i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1406{
3cce469c
CW		 1407 int ret;
1408
1409 ret = intel_ring_begin(ring, 4);
1410 if (ret)
1411 return ret;
6f392d54 1412
3cce469c
CW		 1413 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1414 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1415 intel_ring_emit(ring,
1416 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1417 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1418 __intel_ring_advance(ring);
d1b851fc 1419
3cce469c 1420 return 0;
d1b851fc
ZN		 1421}
1422
0f46832f 1423static bool
a4872ba6 1424gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1425{
1426 struct drm_device *dev = ring->dev;
4640c4ff 1427 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1428 unsigned long flags;
0f46832f 1429
7cd512f1
DV		 1430 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1431 return false;
0f46832f 1432
7338aefa 1433 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1434 if (ring->irq_refcount++ == 0) {
040d2baa 1435 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1436 I915_WRITE_IMR(ring,
1437 ~(ring->irq_enable_mask |
35a85ac6 1438 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1439 else
1440 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1441 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1442 }
7338aefa 1443 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1444
1445 return true;
1446}
1447
1448static void
a4872ba6 1449gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1450{
1451 struct drm_device *dev = ring->dev;
4640c4ff 1452 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1453 unsigned long flags;
0f46832f 1454
7338aefa 1455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1456 if (--ring->irq_refcount == 0) {
040d2baa 1457 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1458 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1459 else
1460 I915_WRITE_IMR(ring, ~0);
480c8033 1461 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1462 }
7338aefa 1463 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1464}
1465
a19d2933 1466static bool
a4872ba6 1467hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1468{
1469 struct drm_device *dev = ring->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 unsigned long flags;
1472
7cd512f1 1473 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1474 return false;
1475
59cdb63d 1476 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1477 if (ring->irq_refcount++ == 0) {
a19d2933 1478 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1479 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1480 }
59cdb63d 1481 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1482
1483 return true;
1484}
1485
1486static void
a4872ba6 1487hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1488{
1489 struct drm_device *dev = ring->dev;
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491 unsigned long flags;
1492
59cdb63d 1493 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1494 if (--ring->irq_refcount == 0) {
a19d2933 1495 I915_WRITE_IMR(ring, ~0);
480c8033 1496 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1497 }
59cdb63d 1498 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1499}
1500
abd58f01 1501static bool
a4872ba6 1502gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1503{
1504 struct drm_device *dev = ring->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 unsigned long flags;
1507
7cd512f1 1508 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1509 return false;
1510
1511 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1512 if (ring->irq_refcount++ == 0) {
1513 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1514 I915_WRITE_IMR(ring,
1515 ~(ring->irq_enable_mask |
1516 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1517 } else {
1518 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1519 }
1520 POSTING_READ(RING_IMR(ring->mmio_base));
1521 }
1522 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1523
1524 return true;
1525}
1526
1527static void
a4872ba6 1528gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1529{
1530 struct drm_device *dev = ring->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 unsigned long flags;
1533
1534 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1535 if (--ring->irq_refcount == 0) {
1536 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1537 I915_WRITE_IMR(ring,
1538 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1539 } else {
1540 I915_WRITE_IMR(ring, ~0);
1541 }
1542 POSTING_READ(RING_IMR(ring->mmio_base));
1543 }
1544 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1545}
1546
d1b851fc 1547static int
a4872ba6 1548i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1549 u64 offset, u32 length,
d7d4eedd 1550 unsigned flags)
d1b851fc 1551{
e1f99ce6 1552 int ret;
78501eac 1553
e1f99ce6
CW		 1554 ret = intel_ring_begin(ring, 2);
1555 if (ret)
1556 return ret;
1557
78501eac 1558 intel_ring_emit(ring,
65f56876
CW		 1559 MI_BATCH_BUFFER_START |
1560 MI_BATCH_GTT |
d7d4eedd 1561 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1562 intel_ring_emit(ring, offset);
78501eac
CW		 1563 intel_ring_advance(ring);
1564
d1b851fc
ZN		 1565 return 0;
1566}
1567
b45305fc
DV		 1568/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1569#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1570#define I830_TLB_ENTRIES (2)
1571#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1572static int
a4872ba6 1573i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1574 u64 offset, u32 len,
d7d4eedd 1575 unsigned flags)
62fdfeaf 1576{
c4d69da1 1577 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1578 int ret;
62fdfeaf 1579
c4d69da1
CW		 1580 ret = intel_ring_begin(ring, 6);
1581 if (ret)
1582 return ret;
62fdfeaf 1583
c4d69da1
CW		 1584 /* Evict the invalid PTE TLBs */
1585 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1586 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1587 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1588 intel_ring_emit(ring, cs_offset);
1589 intel_ring_emit(ring, 0xdeadbeef);
1590 intel_ring_emit(ring, MI_NOOP);
1591 intel_ring_advance(ring);
b45305fc 1592
c4d69da1 1593 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1594 if (len > I830_BATCH_LIMIT)
1595 return -ENOSPC;
1596
c4d69da1 1597 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1598 if (ret)
1599 return ret;
c4d69da1
CW		 1600
1601 /* Blit the batch (which has now all relocs applied) to the
1602 * stable batch scratch bo area (so that the CS never
1603 * stumbles over its tlb invalidation bug) ...
1604 */
1605 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1606 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1607 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1608 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1609 intel_ring_emit(ring, 4096);
1610 intel_ring_emit(ring, offset);
c4d69da1 1611
b45305fc 1612 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1613 intel_ring_emit(ring, MI_NOOP);
1614 intel_ring_advance(ring);
b45305fc
DV		 1615
1616 /* ... and execute it. */
c4d69da1 1617 offset = cs_offset;
b45305fc 1618 }
e1f99ce6 1619
c4d69da1
CW		 1620 ret = intel_ring_begin(ring, 4);
1621 if (ret)
1622 return ret;
1623
1624 intel_ring_emit(ring, MI_BATCH_BUFFER);
1625 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1626 intel_ring_emit(ring, offset + len - 8);
1627 intel_ring_emit(ring, MI_NOOP);
1628 intel_ring_advance(ring);
1629
fb3256da
DV		 1630 return 0;
1631}
1632
1633static int
a4872ba6 1634i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1635 u64 offset, u32 len,
d7d4eedd 1636 unsigned flags)
fb3256da
DV		 1637{
1638 int ret;
1639
1640 ret = intel_ring_begin(ring, 2);
1641 if (ret)
1642 return ret;
1643
65f56876 1644 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1645 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1646 intel_ring_advance(ring);
62fdfeaf 1647
62fdfeaf
EA		 1648 return 0;
1649}
1650
a4872ba6 1651static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1652{
05394f39 1653 struct drm_i915_gem_object *obj;
62fdfeaf 1654
8187a2b7
ZN		 1655 obj = ring->status_page.obj;
1656 if (obj == NULL)
62fdfeaf 1657 return;
62fdfeaf 1658
9da3da66 1659 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1660 i915_gem_object_ggtt_unpin(obj);
05394f39 1661 drm_gem_object_unreference(&obj->base);
8187a2b7 1662 ring->status_page.obj = NULL;
62fdfeaf
EA		 1663}
1664
a4872ba6 1665static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1666{
05394f39 1667 struct drm_i915_gem_object *obj;
62fdfeaf 1668
e3efda49 1669 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1670 unsigned flags;
e3efda49 1671 int ret;
e4ffd173 1672
e3efda49
CW		 1673 obj = i915_gem_alloc_object(ring->dev, 4096);
1674 if (obj == NULL) {
1675 DRM_ERROR("Failed to allocate status page\n");
1676 return -ENOMEM;
1677 }
62fdfeaf 1678
e3efda49
CW		 1679 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1680 if (ret)
1681 goto err_unref;
1682
1f767e02
CW		 1683 flags = 0;
1684 if (!HAS_LLC(ring->dev))
1685 /* On g33, we cannot place HWS above 256MiB, so
1686 * restrict its pinning to the low mappable arena.
1687 * Though this restriction is not documented for
1688 * gen4, gen5, or byt, they also behave similarly
1689 * and hang if the HWS is placed at the top of the
1690 * GTT. To generalise, it appears that all !llc
1691 * platforms have issues with us placing the HWS
1692 * above the mappable region (even though we never
1693 * actualy map it).
1694 */
1695 flags |= PIN_MAPPABLE;
1696 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1697 if (ret) {
1698err_unref:
1699 drm_gem_object_unreference(&obj->base);
1700 return ret;
1701 }
1702
1703 ring->status_page.obj = obj;
1704 }
62fdfeaf 1705
f343c5f6 1706 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1707 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1708 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1709
8187a2b7
ZN		 1710 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1711 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1712
1713 return 0;
62fdfeaf
EA		 1714}
1715
a4872ba6 1716static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1717{
1718 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1719
1720 if (!dev_priv->status_page_dmah) {
1721 dev_priv->status_page_dmah =
1722 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1723 if (!dev_priv->status_page_dmah)
1724 return -ENOMEM;
1725 }
1726
6b8294a4
CW		 1727 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1728 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1729
1730 return 0;
1731}
1732
7ba717cf 1733void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1734{
2919d291 1735 iounmap(ringbuf->virtual_start);
7ba717cf 1736 ringbuf->virtual_start = NULL;
2919d291 1737 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1738}
1739
1740int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1741 struct intel_ringbuffer *ringbuf)
1742{
1743 struct drm_i915_private *dev_priv = to_i915(dev);
1744 struct drm_i915_gem_object *obj = ringbuf->obj;
1745 int ret;
1746
1747 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1748 if (ret)
1749 return ret;
1750
1751 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1752 if (ret) {
1753 i915_gem_object_ggtt_unpin(obj);
1754 return ret;
1755 }
1756
1757 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1758 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1759 if (ringbuf->virtual_start == NULL) {
1760 i915_gem_object_ggtt_unpin(obj);
1761 return -EINVAL;
1762 }
1763
1764 return 0;
1765}
1766
1767void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1768{
2919d291
OM		 1769 drm_gem_object_unreference(&ringbuf->obj->base);
1770 ringbuf->obj = NULL;
1771}
1772
84c2377f
OM		 1773int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1774 struct intel_ringbuffer *ringbuf)
62fdfeaf 1775{
05394f39 1776 struct drm_i915_gem_object *obj;
62fdfeaf 1777
ebc052e0
CW		 1778 obj = NULL;
1779 if (!HAS_LLC(dev))
93b0a4e0 1780 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1781 if (obj == NULL)
93b0a4e0 1782 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1783 if (obj == NULL)
1784 return -ENOMEM;
8187a2b7 1785
24f3a8cf
AG		 1786 /* mark ring buffers as read-only from GPU side by default */
1787 obj->gt_ro = 1;
1788
93b0a4e0 1789 ringbuf->obj = obj;
e3efda49 1790
7ba717cf 1791 return 0;
e3efda49
CW		 1792}
1793
1794static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1795 struct intel_engine_cs *ring)
e3efda49 1796{
8ee14975 1797 struct intel_ringbuffer *ringbuf = ring->buffer;
e3efda49
CW		 1798 int ret;
1799
8ee14975
OM		 1800 if (ringbuf == NULL) {
1801 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1802 if (!ringbuf)
1803 return -ENOMEM;
1804 ring->buffer = ringbuf;
1805 }
1806
e3efda49
CW		 1807 ring->dev = dev;
1808 INIT_LIST_HEAD(&ring->active_list);
1809 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1810 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1811 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1812 ringbuf->ring = ring;
ebc348b2 1813 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1814
1815 init_waitqueue_head(&ring->irq_queue);
1816
1817 if (I915_NEED_GFX_HWS(dev)) {
1818 ret = init_status_page(ring);
1819 if (ret)
8ee14975 1820 goto error;
e3efda49
CW		 1821 } else {
1822 BUG_ON(ring->id != RCS);
1823 ret = init_phys_status_page(ring);
1824 if (ret)
8ee14975 1825 goto error;
e3efda49
CW		 1826 }
1827
7ba717cf
TD		 1828 if (ringbuf->obj == NULL) {
1829 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1830 if (ret) {
1831 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1832 ring->name, ret);
1833 goto error;
1834 }
1835
1836 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1837 if (ret) {
1838 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1839 ring->name, ret);
1840 intel_destroy_ringbuffer_obj(ringbuf);
1841 goto error;
1842 }
e3efda49 1843 }
62fdfeaf 1844
55249baa
CW		 1845 /* Workaround an erratum on the i830 which causes a hang if
1846 * the TAIL pointer points to within the last 2 cachelines
1847 * of the buffer.
1848 */
93b0a4e0 1849 ringbuf->effective_size = ringbuf->size;
e3efda49 1850 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1851 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1852
44e895a8
BV		 1853 ret = i915_cmd_parser_init_ring(ring);
1854 if (ret)
8ee14975
OM		 1855 goto error;
1856
1857 ret = ring->init(ring);
1858 if (ret)
1859 goto error;
1860
1861 return 0;
351e3db2 1862
8ee14975
OM		 1863error:
1864 kfree(ringbuf);
1865 ring->buffer = NULL;
1866 return ret;
62fdfeaf
EA		 1867}
1868
a4872ba6 1869void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1870{
6402c330
JH		 1871 struct drm_i915_private *dev_priv;
1872 struct intel_ringbuffer *ringbuf;
33626e6a 1873
93b0a4e0 1874 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1875 return;
1876
6402c330
JH		 1877 dev_priv = to_i915(ring->dev);
1878 ringbuf = ring->buffer;
1879
e3efda49 1880 intel_stop_ring_buffer(ring);
de8f0a50 1881 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1882
7ba717cf 1883 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 1884 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 1885 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 1886
8d19215b
ZN		 1887 if (ring->cleanup)
1888 ring->cleanup(ring);
1889
78501eac 1890 cleanup_status_page(ring);
44e895a8
BV		 1891
1892 i915_cmd_parser_fini_ring(ring);
8ee14975 1893
93b0a4e0 1894 kfree(ringbuf);
8ee14975 1895 ring->buffer = NULL;
62fdfeaf
EA		 1896}
1897
a4872ba6 1898static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1899{
93b0a4e0 1900 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1901 struct drm_i915_gem_request *request;
a71d8d94
CW		 1902 int ret;
1903
93b0a4e0
OM		 1904 if (ringbuf->last_retired_head != -1) {
1905 ringbuf->head = ringbuf->last_retired_head;
1906 ringbuf->last_retired_head = -1;
1f70999f 1907
82e104cc 1908 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1909 if (ringbuf->space >= n)
a71d8d94
CW		 1910 return 0;
1911 }
1912
1913 list_for_each_entry(request, &ring->request_list, list) {
82e104cc
OM		 1914 if (__intel_ring_space(request->tail, ringbuf->tail,
1915 ringbuf->size) >= n) {
a71d8d94
CW		 1916 break;
1917 }
a71d8d94
CW		 1918 }
1919
a4b3a571 1920 if (&request->list == &ring->request_list)
a71d8d94
CW		 1921 return -ENOSPC;
1922
a4b3a571 1923 ret = i915_wait_request(request);
a71d8d94
CW		 1924 if (ret)
1925 return ret;
1926
1cf0ba14 1927 i915_gem_retire_requests_ring(ring);
93b0a4e0
OM		 1928 ringbuf->head = ringbuf->last_retired_head;
1929 ringbuf->last_retired_head = -1;
a71d8d94 1930
82e104cc 1931 ringbuf->space = intel_ring_space(ringbuf);
a71d8d94
CW		 1932 return 0;
1933}
1934
a4872ba6 1935static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1936{
78501eac 1937 struct drm_device *dev = ring->dev;
cae5852d 1938 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1939 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1940 unsigned long end;
a71d8d94 1941 int ret;
c7dca47b 1942
a71d8d94
CW		 1943 ret = intel_ring_wait_request(ring, n);
1944 if (ret != -ENOSPC)
1945 return ret;
1946
09246732
CW		 1947 /* force the tail write in case we have been skipping them */
1948 __intel_ring_advance(ring);
1949
63ed2cb2
DV		 1950 /* With GEM the hangcheck timer should kick us out of the loop,
1951 * leaving it early runs the risk of corrupting GEM state (due
1952 * to running on almost untested codepaths). But on resume
1953 * timers don't work yet, so prevent a complete hang in that
1954 * case by choosing an insanely large timeout. */
1955 end = jiffies + 60 * HZ;
e6bfaf85 1956
dcfe0506 1957 trace_i915_ring_wait_begin(ring);
8187a2b7 1958 do {
93b0a4e0 1959 ringbuf->head = I915_READ_HEAD(ring);
82e104cc 1960 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1961 if (ringbuf->space >= n) {
dcfe0506
CW		 1962 ret = 0;
1963 break;
62fdfeaf
EA		 1964 }
1965
e60a0b10 1966 msleep(1);
d6b2c790 1967
dcfe0506
CW		 1968 if (dev_priv->mm.interruptible && signal_pending(current)) {
1969 ret = -ERESTARTSYS;
1970 break;
1971 }
1972
33196ded
DV		 1973 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1974 dev_priv->mm.interruptible);
d6b2c790 1975 if (ret)
dcfe0506
CW		 1976 break;
1977
1978 if (time_after(jiffies, end)) {
1979 ret = -EBUSY;
1980 break;
1981 }
1982 } while (1);
db53a302 1983 trace_i915_ring_wait_end(ring);
dcfe0506 1984 return ret;
8187a2b7 1985}
62fdfeaf 1986
a4872ba6 1987static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 1988{
1989 uint32_t __iomem *virt;
93b0a4e0
OM		 1990 struct intel_ringbuffer *ringbuf = ring->buffer;
1991 int rem = ringbuf->size - ringbuf->tail;
3e960501 1992
93b0a4e0 1993 if (ringbuf->space < rem) {
3e960501
CW		 1994 int ret = ring_wait_for_space(ring, rem);
1995 if (ret)
1996 return ret;
1997 }
1998
93b0a4e0 1999 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2000 rem /= 4;
2001 while (rem--)
2002 iowrite32(MI_NOOP, virt++);
2003
93b0a4e0 2004 ringbuf->tail = 0;
82e104cc 2005 ringbuf->space = intel_ring_space(ringbuf);
3e960501
CW		 2006
2007 return 0;
2008}
2009
a4872ba6 2010int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2011{
a4b3a571 2012 struct drm_i915_gem_request *req;
3e960501
CW		 2013 int ret;
2014
2015 /* We need to add any requests required to flush the objects and ring */
6259cead 2016 if (ring->outstanding_lazy_request) {
9400ae5c 2017 ret = i915_add_request(ring);
3e960501
CW		 2018 if (ret)
2019 return ret;
2020 }
2021
2022 /* Wait upon the last request to be completed */
2023 if (list_empty(&ring->request_list))
2024 return 0;
2025
a4b3a571 2026 req = list_entry(ring->request_list.prev,
3e960501 2027 struct drm_i915_gem_request,
a4b3a571 2028 list);
3e960501 2029
a4b3a571 2030 return i915_wait_request(req);
3e960501
CW		 2031}
2032
9d773091 2033static int
6259cead 2034intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2035{
9eba5d4a
JH		 2036 int ret;
2037 struct drm_i915_gem_request *request;
2038
6259cead 2039 if (ring->outstanding_lazy_request)
9d773091 2040 return 0;
3c0e234c 2041
9eba5d4a
JH		 2042 request = kmalloc(sizeof(*request), GFP_KERNEL);
2043 if (request == NULL)
2044 return -ENOMEM;
3c0e234c 2045
abfe262a
JH		 2046 kref_init(&request->ref);
2047
6259cead 2048 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2049 if (ret) {
2050 kfree(request);
2051 return ret;
3c0e234c
CW		 2052 }
2053
6259cead 2054 ring->outstanding_lazy_request = request;
9eba5d4a 2055 return 0;
9d773091
CW		 2056}
2057
a4872ba6 2058static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2059 int bytes)
cbcc80df 2060{
93b0a4e0 2061 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2062 int ret;
2063
93b0a4e0 2064 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2065 ret = intel_wrap_ring_buffer(ring);
2066 if (unlikely(ret))
2067 return ret;
2068 }
2069
93b0a4e0 2070 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2071 ret = ring_wait_for_space(ring, bytes);
2072 if (unlikely(ret))
2073 return ret;
2074 }
2075
cbcc80df
MK		 2076 return 0;
2077}
2078
a4872ba6 2079int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2080 int num_dwords)
8187a2b7 2081{
4640c4ff 2082 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2083 int ret;
78501eac 2084
33196ded
DV		 2085 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2086 dev_priv->mm.interruptible);
de2b9985
DV		 2087 if (ret)
2088 return ret;
21dd3734 2089
304d695c
CW		 2090 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2091 if (ret)
2092 return ret;
2093
9d773091 2094 /* Preallocate the olr before touching the ring */
6259cead 2095 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2096 if (ret)
2097 return ret;
2098
ee1b1e5e 2099 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2100 return 0;
8187a2b7 2101}
78501eac 2102
753b1ad4 2103/* Align the ring tail to a cacheline boundary */
a4872ba6 2104int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2105{
ee1b1e5e 2106 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2107 int ret;
2108
2109 if (num_dwords == 0)
2110 return 0;
2111
18393f63 2112 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2113 ret = intel_ring_begin(ring, num_dwords);
2114 if (ret)
2115 return ret;
2116
2117 while (num_dwords--)
2118 intel_ring_emit(ring, MI_NOOP);
2119
2120 intel_ring_advance(ring);
2121
2122 return 0;
2123}
2124
a4872ba6 2125void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2126{
3b2cc8ab
OM		 2127 struct drm_device *dev = ring->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2129
6259cead 2130 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2131
3b2cc8ab 2132 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2133 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2134 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2135 if (HAS_VEBOX(dev))
5020150b 2136 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2137 }
d97ed339 2138
f7e98ad4 2139 ring->set_seqno(ring, seqno);
92cab734 2140 ring->hangcheck.seqno = seqno;
8187a2b7 2141}
62fdfeaf 2142
a4872ba6 2143static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2144 u32 value)
881f47b6 2145{
4640c4ff 2146 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2147
2148 /* Every tail move must follow the sequence below */
12f55818
CW		 2149
2150 /* Disable notification that the ring is IDLE. The GT
2151 * will then assume that it is busy and bring it out of rc6.
2152 */
0206e353 2153 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2154 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2155
2156 /* Clear the context id. Here be magic! */
2157 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2158
12f55818 2159 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2160 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2161 GEN6_BSD_SLEEP_INDICATOR) == 0,
2162 50))
2163 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2164
12f55818 2165 /* Now that the ring is fully powered up, update the tail */
0206e353 2166 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2167 POSTING_READ(RING_TAIL(ring->mmio_base));
2168
2169 /* Let the ring send IDLE messages to the GT again,
2170 * and so let it sleep to conserve power when idle.
2171 */
0206e353 2172 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2173 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2174}
2175
a4872ba6 2176static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2177 u32 invalidate, u32 flush)
881f47b6 2178{
71a77e07 2179 uint32_t cmd;
b72f3acb
CW		 2180 int ret;
2181
b72f3acb
CW		 2182 ret = intel_ring_begin(ring, 4);
2183 if (ret)
2184 return ret;
2185
71a77e07 2186 cmd = MI_FLUSH_DW;
075b3bba
BW		 2187 if (INTEL_INFO(ring->dev)->gen >= 8)
2188 cmd += 1;
9a289771
JB		 2189 /*
2190 * Bspec vol 1c.5 - video engine command streamer:
2191 * "If ENABLED, all TLBs will be invalidated once the flush
2192 * operation is complete. This bit is only valid when the
2193 * Post-Sync Operation field is a value of 1h or 3h."
2194 */
71a77e07 2195 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2196 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2197 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2198 intel_ring_emit(ring, cmd);
9a289771 2199 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2200 if (INTEL_INFO(ring->dev)->gen >= 8) {
2201 intel_ring_emit(ring, 0); /* upper addr */
2202 intel_ring_emit(ring, 0); /* value */
2203 } else {
2204 intel_ring_emit(ring, 0);
2205 intel_ring_emit(ring, MI_NOOP);
2206 }
b72f3acb
CW		 2207 intel_ring_advance(ring);
2208 return 0;
881f47b6
XH		 2209}
2210
1c7a0623 2211static int
a4872ba6 2212gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2213 u64 offset, u32 len,
1c7a0623
BW		 2214 unsigned flags)
2215{
896ab1a5 2216 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2217 int ret;
2218
2219 ret = intel_ring_begin(ring, 4);
2220 if (ret)
2221 return ret;
2222
2223 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2224 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2225 intel_ring_emit(ring, lower_32_bits(offset));
2226 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2227 intel_ring_emit(ring, MI_NOOP);
2228 intel_ring_advance(ring);
2229
2230 return 0;
2231}
2232
d7d4eedd 2233static int
a4872ba6 2234hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2235 u64 offset, u32 len,
d7d4eedd
CW		 2236 unsigned flags)
2237{
2238 int ret;
2239
2240 ret = intel_ring_begin(ring, 2);
2241 if (ret)
2242 return ret;
2243
2244 intel_ring_emit(ring,
77072258
CW		 2245 MI_BATCH_BUFFER_START |
2246 (flags & I915_DISPATCH_SECURE ?
2247 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2248 /* bit0-7 is the length on GEN6+ */
2249 intel_ring_emit(ring, offset);
2250 intel_ring_advance(ring);
2251
2252 return 0;
2253}
2254
881f47b6 2255static int
a4872ba6 2256gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2257 u64 offset, u32 len,
d7d4eedd 2258 unsigned flags)
881f47b6 2259{
0206e353 2260 int ret;
ab6f8e32 2261
0206e353
AJ		 2262 ret = intel_ring_begin(ring, 2);
2263 if (ret)
2264 return ret;
e1f99ce6 2265
d7d4eedd
CW		 2266 intel_ring_emit(ring,
2267 MI_BATCH_BUFFER_START |
2268 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2269 /* bit0-7 is the length on GEN6+ */
2270 intel_ring_emit(ring, offset);
2271 intel_ring_advance(ring);
ab6f8e32 2272
0206e353 2273 return 0;
881f47b6
XH		 2274}
2275
549f7365
CW		 2276/* Blitter support (SandyBridge+) */
2277
a4872ba6 2278static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2279 u32 invalidate, u32 flush)
8d19215b 2280{
fd3da6c9 2281 struct drm_device *dev = ring->dev;
1d73c2a8 2282 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2283 uint32_t cmd;
b72f3acb
CW		 2284 int ret;
2285
6a233c78 2286 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2287 if (ret)
2288 return ret;
2289
71a77e07 2290 cmd = MI_FLUSH_DW;
075b3bba
BW		 2291 if (INTEL_INFO(ring->dev)->gen >= 8)
2292 cmd += 1;
9a289771
JB		 2293 /*
2294 * Bspec vol 1c.3 - blitter engine command streamer:
2295 * "If ENABLED, all TLBs will be invalidated once the flush
2296 * operation is complete. This bit is only valid when the
2297 * Post-Sync Operation field is a value of 1h or 3h."
2298 */
71a77e07 2299 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2300 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2301 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2302 intel_ring_emit(ring, cmd);
9a289771 2303 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2304 if (INTEL_INFO(ring->dev)->gen >= 8) {
2305 intel_ring_emit(ring, 0); /* upper addr */
2306 intel_ring_emit(ring, 0); /* value */
2307 } else {
2308 intel_ring_emit(ring, 0);
2309 intel_ring_emit(ring, MI_NOOP);
2310 }
b72f3acb 2311 intel_ring_advance(ring);
fd3da6c9 2312
1d73c2a8
RV		 2313 if (!invalidate && flush) {
2314 if (IS_GEN7(dev))
2315 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2316 else if (IS_BROADWELL(dev))
2317 dev_priv->fbc.need_sw_cache_clean = true;
2318 }
fd3da6c9 2319
b72f3acb 2320 return 0;
8d19215b
ZN		 2321}
2322
5c1143bb
XH		 2323int intel_init_render_ring_buffer(struct drm_device *dev)
2324{
4640c4ff 2325 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2326 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2327 struct drm_i915_gem_object *obj;
2328 int ret;
5c1143bb 2329
59465b5f
DV		 2330 ring->name = "render ring";
2331 ring->id = RCS;
2332 ring->mmio_base = RENDER_RING_BASE;
2333
707d9cf9 2334 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2335 if (i915_semaphore_is_enabled(dev)) {
2336 obj = i915_gem_alloc_object(dev, 4096);
2337 if (obj == NULL) {
2338 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2339 i915.semaphores = 0;
2340 } else {
2341 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2342 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2343 if (ret != 0) {
2344 drm_gem_object_unreference(&obj->base);
2345 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2346 i915.semaphores = 0;
2347 } else
2348 dev_priv->semaphore_obj = obj;
2349 }
2350 }
7225342a
MK		 2351
2352 ring->init_context = intel_ring_workarounds_emit;
707d9cf9
BW		 2353 ring->add_request = gen6_add_request;
2354 ring->flush = gen8_render_ring_flush;
2355 ring->irq_get = gen8_ring_get_irq;
2356 ring->irq_put = gen8_ring_put_irq;
2357 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2358 ring->get_seqno = gen6_ring_get_seqno;
2359 ring->set_seqno = ring_set_seqno;
2360 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2361 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2362 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2363 ring->semaphore.signal = gen8_rcs_signal;
2364 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2365 }
2366 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2367 ring->add_request = gen6_add_request;
4772eaeb 2368 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2369 if (INTEL_INFO(dev)->gen == 6)
b3111509 2370 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2371 ring->irq_get = gen6_ring_get_irq;
2372 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2373 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2374 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2375 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2376 if (i915_semaphore_is_enabled(dev)) {
2377 ring->semaphore.sync_to = gen6_ring_sync;
2378 ring->semaphore.signal = gen6_signal;
2379 /*
2380 * The current semaphore is only applied on pre-gen8
2381 * platform. And there is no VCS2 ring on the pre-gen8
2382 * platform. So the semaphore between RCS and VCS2 is
2383 * initialized as INVALID. Gen8 will initialize the
2384 * sema between VCS2 and RCS later.
2385 */
2386 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2387 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2388 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2389 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2390 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2391 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2392 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2393 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2394 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2395 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2396 }
c6df541c
CW		 2397 } else if (IS_GEN5(dev)) {
2398 ring->add_request = pc_render_add_request;
46f0f8d1 2399 ring->flush = gen4_render_ring_flush;
c6df541c 2400 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2401 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2402 ring->irq_get = gen5_ring_get_irq;
2403 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2404 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2405 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2406 } else {
8620a3a9 2407 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2408 if (INTEL_INFO(dev)->gen < 4)
2409 ring->flush = gen2_render_ring_flush;
2410 else
2411 ring->flush = gen4_render_ring_flush;
59465b5f 2412 ring->get_seqno = ring_get_seqno;
b70ec5bf 2413 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2414 if (IS_GEN2(dev)) {
2415 ring->irq_get = i8xx_ring_get_irq;
2416 ring->irq_put = i8xx_ring_put_irq;
2417 } else {
2418 ring->irq_get = i9xx_ring_get_irq;
2419 ring->irq_put = i9xx_ring_put_irq;
2420 }
e3670319 2421 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2422 }
59465b5f 2423 ring->write_tail = ring_write_tail;
707d9cf9 2424
d7d4eedd
CW		 2425 if (IS_HASWELL(dev))
2426 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2427 else if (IS_GEN8(dev))
2428 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2429 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2430 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2431 else if (INTEL_INFO(dev)->gen >= 4)
2432 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2433 else if (IS_I830(dev) || IS_845G(dev))
2434 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2435 else
2436 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 2437 ring->init = init_render_ring;
2438 ring->cleanup = render_ring_cleanup;
2439
b45305fc
DV		 2440 /* Workaround batchbuffer to combat CS tlb bug. */
2441 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2442 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2443 if (obj == NULL) {
2444 DRM_ERROR("Failed to allocate batch bo\n");
2445 return -ENOMEM;
2446 }
2447
be1fa129 2448 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2449 if (ret != 0) {
2450 drm_gem_object_unreference(&obj->base);
2451 DRM_ERROR("Failed to ping batch bo\n");
2452 return ret;
2453 }
2454
0d1aacac
CW		 2455 ring->scratch.obj = obj;
2456 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2457 }
2458
1ec14ad3 2459 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 2460}
2461
2462int intel_init_bsd_ring_buffer(struct drm_device *dev)
2463{
4640c4ff 2464 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2465 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2466
58fa3835
DV		 2467 ring->name = "bsd ring";
2468 ring->id = VCS;
2469
0fd2c201 2470 ring->write_tail = ring_write_tail;
780f18c8 2471 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2472 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2473 /* gen6 bsd needs a special wa for tail updates */
2474 if (IS_GEN6(dev))
2475 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2476 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2477 ring->add_request = gen6_add_request;
2478 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2479 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2480 if (INTEL_INFO(dev)->gen >= 8) {
2481 ring->irq_enable_mask =
2482 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2483 ring->irq_get = gen8_ring_get_irq;
2484 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2485 ring->dispatch_execbuffer =
2486 gen8_ring_dispatch_execbuffer;
707d9cf9 2487 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2488 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2489 ring->semaphore.signal = gen8_xcs_signal;
2490 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2491 }
abd58f01
BW		 2492 } else {
2493 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2494 ring->irq_get = gen6_ring_get_irq;
2495 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2496 ring->dispatch_execbuffer =
2497 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2498 if (i915_semaphore_is_enabled(dev)) {
2499 ring->semaphore.sync_to = gen6_ring_sync;
2500 ring->semaphore.signal = gen6_signal;
2501 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2502 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2503 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2504 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2505 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2506 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2507 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2508 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2509 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2510 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2511 }
abd58f01 2512 }
58fa3835
DV		 2513 } else {
2514 ring->mmio_base = BSD_RING_BASE;
58fa3835 2515 ring->flush = bsd_ring_flush;
8620a3a9 2516 ring->add_request = i9xx_add_request;
58fa3835 2517 ring->get_seqno = ring_get_seqno;
b70ec5bf 2518 ring->set_seqno = ring_set_seqno;
e48d8634 2519 if (IS_GEN5(dev)) {
cc609d5d 2520 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2521 ring->irq_get = gen5_ring_get_irq;
2522 ring->irq_put = gen5_ring_put_irq;
2523 } else {
e3670319 2524 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2525 ring->irq_get = i9xx_ring_get_irq;
2526 ring->irq_put = i9xx_ring_put_irq;
2527 }
fb3256da 2528 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835
DV		 2529 }
2530 ring->init = init_ring_common;
2531
1ec14ad3 2532 return intel_init_ring_buffer(dev, ring);
5c1143bb 2533}
549f7365 2534
845f74a7
ZY		 2535/**
2536 * Initialize the second BSD ring for Broadwell GT3.
2537 * It is noted that this only exists on Broadwell GT3.
2538 */
2539int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2540{
2541 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2542 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2543
2544 if ((INTEL_INFO(dev)->gen != 8)) {
2545 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2546 return -EINVAL;
2547 }
2548
f7b64236 2549 ring->name = "bsd2 ring";
845f74a7
ZY		 2550 ring->id = VCS2;
2551
2552 ring->write_tail = ring_write_tail;
2553 ring->mmio_base = GEN8_BSD2_RING_BASE;
2554 ring->flush = gen6_bsd_ring_flush;
2555 ring->add_request = gen6_add_request;
2556 ring->get_seqno = gen6_ring_get_seqno;
2557 ring->set_seqno = ring_set_seqno;
2558 ring->irq_enable_mask =
2559 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2560 ring->irq_get = gen8_ring_get_irq;
2561 ring->irq_put = gen8_ring_put_irq;
2562 ring->dispatch_execbuffer =
2563 gen8_ring_dispatch_execbuffer;
3e78998a 2564 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2565 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2566 ring->semaphore.signal = gen8_xcs_signal;
2567 GEN8_RING_SEMAPHORE_INIT;
2568 }
845f74a7
ZY		 2569 ring->init = init_ring_common;
2570
2571 return intel_init_ring_buffer(dev, ring);
2572}
2573
549f7365
CW		 2574int intel_init_blt_ring_buffer(struct drm_device *dev)
2575{
4640c4ff 2576 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2577 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2578
3535d9dd
DV		 2579 ring->name = "blitter ring";
2580 ring->id = BCS;
2581
2582 ring->mmio_base = BLT_RING_BASE;
2583 ring->write_tail = ring_write_tail;
ea251324 2584 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2585 ring->add_request = gen6_add_request;
2586 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2587 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2588 if (INTEL_INFO(dev)->gen >= 8) {
2589 ring->irq_enable_mask =
2590 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2591 ring->irq_get = gen8_ring_get_irq;
2592 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2593 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2594 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2595 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2596 ring->semaphore.signal = gen8_xcs_signal;
2597 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2598 }
abd58f01
BW		 2599 } else {
2600 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2601 ring->irq_get = gen6_ring_get_irq;
2602 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2603 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2604 if (i915_semaphore_is_enabled(dev)) {
2605 ring->semaphore.signal = gen6_signal;
2606 ring->semaphore.sync_to = gen6_ring_sync;
2607 /*
2608 * The current semaphore is only applied on pre-gen8
2609 * platform. And there is no VCS2 ring on the pre-gen8
2610 * platform. So the semaphore between BCS and VCS2 is
2611 * initialized as INVALID. Gen8 will initialize the
2612 * sema between BCS and VCS2 later.
2613 */
2614 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2615 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2616 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2617 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2618 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2619 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2620 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2621 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2622 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2623 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2624 }
abd58f01 2625 }
3535d9dd 2626 ring->init = init_ring_common;
549f7365 2627
1ec14ad3 2628 return intel_init_ring_buffer(dev, ring);
549f7365 2629}
a7b9761d 2630
9a8a2213
BW		 2631int intel_init_vebox_ring_buffer(struct drm_device *dev)
2632{
4640c4ff 2633 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2634 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2635
2636 ring->name = "video enhancement ring";
2637 ring->id = VECS;
2638
2639 ring->mmio_base = VEBOX_RING_BASE;
2640 ring->write_tail = ring_write_tail;
2641 ring->flush = gen6_ring_flush;
2642 ring->add_request = gen6_add_request;
2643 ring->get_seqno = gen6_ring_get_seqno;
2644 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2645
2646 if (INTEL_INFO(dev)->gen >= 8) {
2647 ring->irq_enable_mask =
40c499f9 2648 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2649 ring->irq_get = gen8_ring_get_irq;
2650 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2651 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2652 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2653 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2654 ring->semaphore.signal = gen8_xcs_signal;
2655 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2656 }
abd58f01
BW		 2657 } else {
2658 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2659 ring->irq_get = hsw_vebox_get_irq;
2660 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2661 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2662 if (i915_semaphore_is_enabled(dev)) {
2663 ring->semaphore.sync_to = gen6_ring_sync;
2664 ring->semaphore.signal = gen6_signal;
2665 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2666 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2667 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2668 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2669 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2670 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2671 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2672 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2673 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2674 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2675 }
abd58f01 2676 }
9a8a2213
BW		 2677 ring->init = init_ring_common;
2678
2679 return intel_init_ring_buffer(dev, ring);
2680}
2681
a7b9761d 2682int
a4872ba6 2683intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2684{
2685 int ret;
2686
2687 if (!ring->gpu_caches_dirty)
2688 return 0;
2689
2690 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2691 if (ret)
2692 return ret;
2693
2694 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2695
2696 ring->gpu_caches_dirty = false;
2697 return 0;
2698}
2699
2700int
a4872ba6 2701intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2702{
2703 uint32_t flush_domains;
2704 int ret;
2705
2706 flush_domains = 0;
2707 if (ring->gpu_caches_dirty)
2708 flush_domains = I915_GEM_GPU_DOMAINS;
2709
2710 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2711 if (ret)
2712 return ret;
2713
2714 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2715
2716 ring->gpu_caches_dirty = false;
2717 return 0;
2718}
e3efda49
CW		 2719
2720void
a4872ba6 2721intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2722{
2723 int ret;
2724
2725 if (!intel_ring_initialized(ring))
2726 return;
2727
2728 ret = intel_ring_idle(ring);
2729 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2730 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2731 ring->name, ret);
2732
2733 stop_ring(ring);
2734}
Linux kernel - Deliverables
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