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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
c7dca47b CW |
36 | static inline int ring_space(struct intel_ring_buffer *ring) |
37 | { | |
633cf8f5 | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
39 | if (space < 0) |
40 | space += ring->size; | |
41 | return space; | |
42 | } | |
43 | ||
09246732 CW |
44 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
45 | { | |
46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
47 | ||
48 | ring->tail &= ring->size - 1; | |
49 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) | |
50 | return; | |
51 | ring->write_tail(ring, ring->tail); | |
52 | } | |
53 | ||
b72f3acb | 54 | static int |
46f0f8d1 CW |
55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
56 | u32 invalidate_domains, | |
57 | u32 flush_domains) | |
58 | { | |
59 | u32 cmd; | |
60 | int ret; | |
61 | ||
62 | cmd = MI_FLUSH; | |
31b14c9f | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
64 | cmd |= MI_NO_WRITE_FLUSH; |
65 | ||
66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
67 | cmd |= MI_READ_FLUSH; | |
68 | ||
69 | ret = intel_ring_begin(ring, 2); | |
70 | if (ret) | |
71 | return ret; | |
72 | ||
73 | intel_ring_emit(ring, cmd); | |
74 | intel_ring_emit(ring, MI_NOOP); | |
75 | intel_ring_advance(ring); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int | |
81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
82 | u32 invalidate_domains, | |
83 | u32 flush_domains) | |
62fdfeaf | 84 | { |
78501eac | 85 | struct drm_device *dev = ring->dev; |
6f392d54 | 86 | u32 cmd; |
b72f3acb | 87 | int ret; |
6f392d54 | 88 | |
36d527de CW |
89 | /* |
90 | * read/write caches: | |
91 | * | |
92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
94 | * also flushed at 2d versus 3d pipeline switches. | |
95 | * | |
96 | * read-only caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
99 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
100 | * | |
101 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
102 | * | |
103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
104 | * invalidated when MI_EXE_FLUSH is set. | |
105 | * | |
106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
107 | * invalidated with every MI_FLUSH. | |
108 | * | |
109 | * TLBs: | |
110 | * | |
111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
114 | * are flushed at any MI_FLUSH. | |
115 | */ | |
116 | ||
117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
121 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 122 | |
36d527de CW |
123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
124 | (IS_G4X(dev) || IS_GEN5(dev))) | |
125 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 126 | |
36d527de CW |
127 | ret = intel_ring_begin(ring, 2); |
128 | if (ret) | |
129 | return ret; | |
b72f3acb | 130 | |
36d527de CW |
131 | intel_ring_emit(ring, cmd); |
132 | intel_ring_emit(ring, MI_NOOP); | |
133 | intel_ring_advance(ring); | |
b72f3acb CW |
134 | |
135 | return 0; | |
8187a2b7 ZN |
136 | } |
137 | ||
8d315287 JB |
138 | /** |
139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
140 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
142 | * | |
143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
144 | * produced by non-pipelined state commands), software needs to first | |
145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
146 | * 0. | |
147 | * | |
148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
150 | * | |
151 | * And the workaround for these two requires this workaround first: | |
152 | * | |
153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
154 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
155 | * flushes. | |
156 | * | |
157 | * And this last workaround is tricky because of the requirements on | |
158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
159 | * volume 2 part 1: | |
160 | * | |
161 | * "1 of the following must also be set: | |
162 | * - Render Target Cache Flush Enable ([12] of DW1) | |
163 | * - Depth Cache Flush Enable ([0] of DW1) | |
164 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
165 | * - Depth Stall ([13] of DW1) | |
166 | * - Post-Sync Operation ([13] of DW1) | |
167 | * - Notify Enable ([8] of DW1)" | |
168 | * | |
169 | * The cache flushes require the workaround flush that triggered this | |
170 | * one, so we can't use it. Depth stall would trigger the same. | |
171 | * Post-sync nonzero is what triggered this second workaround, so we | |
172 | * can't use that one either. Notify enable is IRQs, which aren't | |
173 | * really our business. That leaves only stall at scoreboard. | |
174 | */ | |
175 | static int | |
176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
177 | { | |
0d1aacac | 178 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
179 | int ret; |
180 | ||
181 | ||
182 | ret = intel_ring_begin(ring, 6); | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
194 | ||
195 | ret = intel_ring_begin(ring, 6); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
211 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
212 | u32 invalidate_domains, u32 flush_domains) | |
213 | { | |
214 | u32 flags = 0; | |
0d1aacac | 215 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
216 | int ret; |
217 | ||
b3111509 PZ |
218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
219 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
8d315287 JB |
223 | /* Just flush everything. Experiments have shown that reducing the |
224 | * number of bits based on the write domains has little performance | |
225 | * impact. | |
226 | */ | |
7d54a904 CW |
227 | if (flush_domains) { |
228 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
229 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
230 | /* | |
231 | * Ensure that any following seqno writes only happen | |
232 | * when the render cache is indeed flushed. | |
233 | */ | |
97f209bc | 234 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
235 | } |
236 | if (invalidate_domains) { | |
237 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
243 | /* | |
244 | * TLB invalidate requires a post-sync write. | |
245 | */ | |
3ac78313 | 246 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 247 | } |
8d315287 | 248 | |
6c6cf5aa | 249 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
250 | if (ret) |
251 | return ret; | |
252 | ||
6c6cf5aa | 253 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
254 | intel_ring_emit(ring, flags); |
255 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 256 | intel_ring_emit(ring, 0); |
8d315287 JB |
257 | intel_ring_advance(ring); |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
f3987631 PZ |
262 | static int |
263 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
264 | { | |
265 | int ret; | |
266 | ||
267 | ret = intel_ring_begin(ring, 4); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
272 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
273 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
274 | intel_ring_emit(ring, 0); | |
275 | intel_ring_emit(ring, 0); | |
276 | intel_ring_advance(ring); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
fd3da6c9 RV |
281 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
282 | { | |
283 | int ret; | |
284 | ||
285 | if (!ring->fbc_dirty) | |
286 | return 0; | |
287 | ||
37c1d94f | 288 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
289 | if (ret) |
290 | return ret; | |
fd3da6c9 RV |
291 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
292 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
293 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
294 | intel_ring_emit(ring, value); | |
37c1d94f VS |
295 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
296 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
297 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
298 | intel_ring_advance(ring); |
299 | ||
300 | ring->fbc_dirty = false; | |
301 | return 0; | |
302 | } | |
303 | ||
4772eaeb PZ |
304 | static int |
305 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
306 | u32 invalidate_domains, u32 flush_domains) | |
307 | { | |
308 | u32 flags = 0; | |
0d1aacac | 309 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
4772eaeb PZ |
310 | int ret; |
311 | ||
f3987631 PZ |
312 | /* |
313 | * Ensure that any following seqno writes only happen when the render | |
314 | * cache is indeed flushed. | |
315 | * | |
316 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
317 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
318 | * don't try to be clever and just set it unconditionally. | |
319 | */ | |
320 | flags |= PIPE_CONTROL_CS_STALL; | |
321 | ||
4772eaeb PZ |
322 | /* Just flush everything. Experiments have shown that reducing the |
323 | * number of bits based on the write domains has little performance | |
324 | * impact. | |
325 | */ | |
326 | if (flush_domains) { | |
327 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
328 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
329 | } |
330 | if (invalidate_domains) { | |
331 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
332 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
335 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
336 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
337 | /* | |
338 | * TLB invalidate requires a post-sync write. | |
339 | */ | |
340 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 341 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
342 | |
343 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
344 | * set before a pipe_control command that has the state cache | |
345 | * invalidate bit set. */ | |
346 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
347 | } |
348 | ||
349 | ret = intel_ring_begin(ring, 4); | |
350 | if (ret) | |
351 | return ret; | |
352 | ||
353 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
354 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 355 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
356 | intel_ring_emit(ring, 0); |
357 | intel_ring_advance(ring); | |
358 | ||
9688ecad | 359 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
360 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
361 | ||
4772eaeb PZ |
362 | return 0; |
363 | } | |
364 | ||
a5f3d68e BW |
365 | static int |
366 | gen8_render_ring_flush(struct intel_ring_buffer *ring, | |
367 | u32 invalidate_domains, u32 flush_domains) | |
368 | { | |
369 | u32 flags = 0; | |
370 | u32 scratch_addr = ring->scratch.gtt_offset + 128; | |
371 | int ret; | |
372 | ||
373 | flags |= PIPE_CONTROL_CS_STALL; | |
374 | ||
375 | if (flush_domains) { | |
376 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
377 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
378 | } | |
379 | if (invalidate_domains) { | |
380 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
381 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
382 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
383 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
384 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
385 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
386 | flags |= PIPE_CONTROL_QW_WRITE; | |
387 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
388 | } | |
389 | ||
390 | ret = intel_ring_begin(ring, 6); | |
391 | if (ret) | |
392 | return ret; | |
393 | ||
394 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
395 | intel_ring_emit(ring, flags); | |
396 | intel_ring_emit(ring, scratch_addr); | |
397 | intel_ring_emit(ring, 0); | |
398 | intel_ring_emit(ring, 0); | |
399 | intel_ring_emit(ring, 0); | |
400 | intel_ring_advance(ring); | |
401 | ||
402 | return 0; | |
403 | ||
404 | } | |
405 | ||
78501eac | 406 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 407 | u32 value) |
d46eefa2 | 408 | { |
4640c4ff | 409 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 410 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
411 | } |
412 | ||
50877445 | 413 | u64 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 414 | { |
4640c4ff | 415 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 416 | u64 acthd; |
8187a2b7 | 417 | |
50877445 CW |
418 | if (INTEL_INFO(ring->dev)->gen >= 8) |
419 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
420 | RING_ACTHD_UDW(ring->mmio_base)); | |
421 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
422 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
423 | else | |
424 | acthd = I915_READ(ACTHD); | |
425 | ||
426 | return acthd; | |
8187a2b7 ZN |
427 | } |
428 | ||
035dc1e0 DV |
429 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
430 | { | |
431 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
432 | u32 addr; | |
433 | ||
434 | addr = dev_priv->status_page_dmah->busaddr; | |
435 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
436 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
437 | I915_WRITE(HWS_PGA, addr); | |
438 | } | |
439 | ||
9991ae78 | 440 | static bool stop_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 441 | { |
9991ae78 | 442 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 443 | |
9991ae78 CW |
444 | if (!IS_GEN2(ring->dev)) { |
445 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
446 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
447 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
448 | return false; | |
449 | } | |
450 | } | |
b7884eb4 | 451 | |
7f2ab699 | 452 | I915_WRITE_CTL(ring, 0); |
570ef608 | 453 | I915_WRITE_HEAD(ring, 0); |
78501eac | 454 | ring->write_tail(ring, 0); |
8187a2b7 | 455 | |
9991ae78 CW |
456 | if (!IS_GEN2(ring->dev)) { |
457 | (void)I915_READ_CTL(ring); | |
458 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
459 | } | |
a51435a3 | 460 | |
9991ae78 CW |
461 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
462 | } | |
8187a2b7 | 463 | |
9991ae78 CW |
464 | static int init_ring_common(struct intel_ring_buffer *ring) |
465 | { | |
466 | struct drm_device *dev = ring->dev; | |
467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
468 | struct drm_i915_gem_object *obj = ring->obj; | |
469 | int ret = 0; | |
470 | ||
471 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
472 | ||
473 | if (!stop_ring(ring)) { | |
474 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
475 | DRM_DEBUG_KMS("%s head not reset to zero " |
476 | "ctl %08x head %08x tail %08x start %08x\n", | |
477 | ring->name, | |
478 | I915_READ_CTL(ring), | |
479 | I915_READ_HEAD(ring), | |
480 | I915_READ_TAIL(ring), | |
481 | I915_READ_START(ring)); | |
8187a2b7 | 482 | |
9991ae78 | 483 | if (!stop_ring(ring)) { |
6fd0d56e CW |
484 | DRM_ERROR("failed to set %s head to zero " |
485 | "ctl %08x head %08x tail %08x start %08x\n", | |
486 | ring->name, | |
487 | I915_READ_CTL(ring), | |
488 | I915_READ_HEAD(ring), | |
489 | I915_READ_TAIL(ring), | |
490 | I915_READ_START(ring)); | |
9991ae78 CW |
491 | ret = -EIO; |
492 | goto out; | |
6fd0d56e | 493 | } |
8187a2b7 ZN |
494 | } |
495 | ||
9991ae78 CW |
496 | if (I915_NEED_GFX_HWS(dev)) |
497 | intel_ring_setup_status_page(ring); | |
498 | else | |
499 | ring_setup_phys_status_page(ring); | |
500 | ||
0d8957c8 DV |
501 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
502 | * registers with the above sequence (the readback of the HEAD registers | |
503 | * also enforces ordering), otherwise the hw might lose the new ring | |
504 | * register values. */ | |
f343c5f6 | 505 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 506 | I915_WRITE_CTL(ring, |
ae69b42a | 507 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 508 | | RING_VALID); |
8187a2b7 | 509 | |
8187a2b7 | 510 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 511 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 512 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 513 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 CW |
514 | DRM_ERROR("%s initialization failed " |
515 | "ctl %08x head %08x tail %08x start %08x\n", | |
516 | ring->name, | |
517 | I915_READ_CTL(ring), | |
518 | I915_READ_HEAD(ring), | |
519 | I915_READ_TAIL(ring), | |
520 | I915_READ_START(ring)); | |
b7884eb4 DV |
521 | ret = -EIO; |
522 | goto out; | |
8187a2b7 ZN |
523 | } |
524 | ||
78501eac CW |
525 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
526 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 527 | else { |
c7dca47b | 528 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 529 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 530 | ring->space = ring_space(ring); |
c3b20037 | 531 | ring->last_retired_head = -1; |
8187a2b7 | 532 | } |
1ec14ad3 | 533 | |
50f018df CW |
534 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
535 | ||
b7884eb4 | 536 | out: |
c8d9a590 | 537 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
538 | |
539 | return ret; | |
8187a2b7 ZN |
540 | } |
541 | ||
c6df541c CW |
542 | static int |
543 | init_pipe_control(struct intel_ring_buffer *ring) | |
544 | { | |
c6df541c CW |
545 | int ret; |
546 | ||
0d1aacac | 547 | if (ring->scratch.obj) |
c6df541c CW |
548 | return 0; |
549 | ||
0d1aacac CW |
550 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
551 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
552 | DRM_ERROR("Failed to allocate seqno page\n"); |
553 | ret = -ENOMEM; | |
554 | goto err; | |
555 | } | |
e4ffd173 | 556 | |
a9cc726c DV |
557 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
558 | if (ret) | |
559 | goto err_unref; | |
c6df541c | 560 | |
1ec9e26d | 561 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
562 | if (ret) |
563 | goto err_unref; | |
564 | ||
0d1aacac CW |
565 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
566 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
567 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 568 | ret = -ENOMEM; |
c6df541c | 569 | goto err_unpin; |
56b085a0 | 570 | } |
c6df541c | 571 | |
2b1086cc | 572 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 573 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
574 | return 0; |
575 | ||
576 | err_unpin: | |
d7f46fc4 | 577 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 578 | err_unref: |
0d1aacac | 579 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 580 | err: |
c6df541c CW |
581 | return ret; |
582 | } | |
583 | ||
78501eac | 584 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 585 | { |
78501eac | 586 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 587 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 588 | int ret = init_ring_common(ring); |
a69ffdbf | 589 | |
61a563a2 AG |
590 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
591 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 592 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
593 | |
594 | /* We need to disable the AsyncFlip performance optimisations in order | |
595 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
596 | * programmed to '1' on all products. | |
8693a824 | 597 | * |
8285222c | 598 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw |
1c8c38c5 CW |
599 | */ |
600 | if (INTEL_INFO(dev)->gen >= 6) | |
601 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
602 | ||
f05bb0c7 | 603 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 604 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
605 | if (INTEL_INFO(dev)->gen == 6) |
606 | I915_WRITE(GFX_MODE, | |
aa83e30d | 607 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 608 | |
01fa0302 | 609 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
610 | if (IS_GEN7(dev)) |
611 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 612 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 613 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 614 | |
8d315287 | 615 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
616 | ret = init_pipe_control(ring); |
617 | if (ret) | |
618 | return ret; | |
619 | } | |
620 | ||
5e13a0c5 | 621 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
622 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
623 | * "If this bit is set, STCunit will have LRA as replacement | |
624 | * policy. [...] This bit must be reset. LRA replacement | |
625 | * policy is not supported." | |
626 | */ | |
627 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 628 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
629 | } |
630 | ||
6b26c86d DV |
631 | if (INTEL_INFO(dev)->gen >= 6) |
632 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 633 | |
040d2baa | 634 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 635 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 636 | |
8187a2b7 ZN |
637 | return ret; |
638 | } | |
639 | ||
c6df541c CW |
640 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
641 | { | |
b45305fc DV |
642 | struct drm_device *dev = ring->dev; |
643 | ||
0d1aacac | 644 | if (ring->scratch.obj == NULL) |
c6df541c CW |
645 | return; |
646 | ||
0d1aacac CW |
647 | if (INTEL_INFO(dev)->gen >= 5) { |
648 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
d7f46fc4 | 649 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
0d1aacac | 650 | } |
aaf8a516 | 651 | |
0d1aacac CW |
652 | drm_gem_object_unreference(&ring->scratch.obj->base); |
653 | ring->scratch.obj = NULL; | |
c6df541c CW |
654 | } |
655 | ||
1ec14ad3 | 656 | static void |
c8c99b0f | 657 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 658 | u32 mmio_offset) |
1ec14ad3 | 659 | { |
ad776f8b BW |
660 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
661 | * of rings, it's easiest if we round up each individual update to a | |
662 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
663 | * even though the actual update only requires 3 dwords. | |
664 | */ | |
665 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 666 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 667 | intel_ring_emit(ring, mmio_offset); |
1823521d | 668 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
ad776f8b | 669 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
670 | } |
671 | ||
c8c99b0f BW |
672 | /** |
673 | * gen6_add_request - Update the semaphore mailbox registers | |
674 | * | |
675 | * @ring - ring that is adding a request | |
676 | * @seqno - return seqno stuck into the ring | |
677 | * | |
678 | * Update the mailbox registers in the *other* rings with the current seqno. | |
679 | * This acts like a signal in the canonical semaphore. | |
680 | */ | |
1ec14ad3 | 681 | static int |
9d773091 | 682 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 683 | { |
ad776f8b BW |
684 | struct drm_device *dev = ring->dev; |
685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
686 | struct intel_ring_buffer *useless; | |
52ed2325 | 687 | int i, ret, num_dwords = 4; |
1ec14ad3 | 688 | |
52ed2325 BW |
689 | if (i915_semaphore_is_enabled(dev)) |
690 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); | |
691 | #undef MBOX_UPDATE_DWORDS | |
692 | ||
693 | ret = intel_ring_begin(ring, num_dwords); | |
1ec14ad3 CW |
694 | if (ret) |
695 | return ret; | |
696 | ||
f0a9f74c BW |
697 | if (i915_semaphore_is_enabled(dev)) { |
698 | for_each_ring(useless, dev_priv, i) { | |
699 | u32 mbox_reg = ring->signal_mbox[i]; | |
700 | if (mbox_reg != GEN6_NOSYNC) | |
701 | update_mboxes(ring, mbox_reg); | |
702 | } | |
ad776f8b | 703 | } |
1ec14ad3 CW |
704 | |
705 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
706 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 707 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 708 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 709 | __intel_ring_advance(ring); |
1ec14ad3 | 710 | |
1ec14ad3 CW |
711 | return 0; |
712 | } | |
713 | ||
f72b3435 MK |
714 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
715 | u32 seqno) | |
716 | { | |
717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
718 | return dev_priv->last_seqno < seqno; | |
719 | } | |
720 | ||
c8c99b0f BW |
721 | /** |
722 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
723 | * | |
724 | * @waiter - ring that is waiting | |
725 | * @signaller - ring which has, or will signal | |
726 | * @seqno - seqno which the waiter will block on | |
727 | */ | |
728 | static int | |
686cb5f9 DV |
729 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
730 | struct intel_ring_buffer *signaller, | |
731 | u32 seqno) | |
1ec14ad3 CW |
732 | { |
733 | int ret; | |
c8c99b0f BW |
734 | u32 dw1 = MI_SEMAPHORE_MBOX | |
735 | MI_SEMAPHORE_COMPARE | | |
736 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 737 | |
1500f7ea BW |
738 | /* Throughout all of the GEM code, seqno passed implies our current |
739 | * seqno is >= the last seqno executed. However for hardware the | |
740 | * comparison is strictly greater than. | |
741 | */ | |
742 | seqno -= 1; | |
743 | ||
686cb5f9 DV |
744 | WARN_ON(signaller->semaphore_register[waiter->id] == |
745 | MI_SEMAPHORE_SYNC_INVALID); | |
746 | ||
c8c99b0f | 747 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
748 | if (ret) |
749 | return ret; | |
750 | ||
f72b3435 MK |
751 | /* If seqno wrap happened, omit the wait with no-ops */ |
752 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
753 | intel_ring_emit(waiter, | |
754 | dw1 | | |
755 | signaller->semaphore_register[waiter->id]); | |
756 | intel_ring_emit(waiter, seqno); | |
757 | intel_ring_emit(waiter, 0); | |
758 | intel_ring_emit(waiter, MI_NOOP); | |
759 | } else { | |
760 | intel_ring_emit(waiter, MI_NOOP); | |
761 | intel_ring_emit(waiter, MI_NOOP); | |
762 | intel_ring_emit(waiter, MI_NOOP); | |
763 | intel_ring_emit(waiter, MI_NOOP); | |
764 | } | |
c8c99b0f | 765 | intel_ring_advance(waiter); |
1ec14ad3 CW |
766 | |
767 | return 0; | |
768 | } | |
769 | ||
c6df541c CW |
770 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
771 | do { \ | |
fcbc34e4 KG |
772 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
773 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
774 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
775 | intel_ring_emit(ring__, 0); \ | |
776 | intel_ring_emit(ring__, 0); \ | |
777 | } while (0) | |
778 | ||
779 | static int | |
9d773091 | 780 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 781 | { |
0d1aacac | 782 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
c6df541c CW |
783 | int ret; |
784 | ||
785 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
786 | * incoherent with writes to memory, i.e. completely fubar, | |
787 | * so we need to use PIPE_NOTIFY instead. | |
788 | * | |
789 | * However, we also need to workaround the qword write | |
790 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
791 | * memory before requesting an interrupt. | |
792 | */ | |
793 | ret = intel_ring_begin(ring, 32); | |
794 | if (ret) | |
795 | return ret; | |
796 | ||
fcbc34e4 | 797 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
798 | PIPE_CONTROL_WRITE_FLUSH | |
799 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 800 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 801 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
802 | intel_ring_emit(ring, 0); |
803 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
804 | scratch_addr += 128; /* write to separate cachelines */ | |
805 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
806 | scratch_addr += 128; | |
807 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
808 | scratch_addr += 128; | |
809 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
810 | scratch_addr += 128; | |
811 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
812 | scratch_addr += 128; | |
813 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 814 | |
fcbc34e4 | 815 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
816 | PIPE_CONTROL_WRITE_FLUSH | |
817 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 818 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 819 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 820 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 821 | intel_ring_emit(ring, 0); |
09246732 | 822 | __intel_ring_advance(ring); |
c6df541c | 823 | |
c6df541c CW |
824 | return 0; |
825 | } | |
826 | ||
4cd53c0c | 827 | static u32 |
b2eadbc8 | 828 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 829 | { |
4cd53c0c DV |
830 | /* Workaround to force correct ordering between irq and seqno writes on |
831 | * ivb (and maybe also on snb) by reading from a CS register (like | |
832 | * ACTHD) before reading the status page. */ | |
50877445 CW |
833 | if (!lazy_coherency) { |
834 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
835 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
836 | } | |
837 | ||
4cd53c0c DV |
838 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
839 | } | |
840 | ||
8187a2b7 | 841 | static u32 |
b2eadbc8 | 842 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 843 | { |
1ec14ad3 CW |
844 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
845 | } | |
846 | ||
b70ec5bf MK |
847 | static void |
848 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
849 | { | |
850 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
851 | } | |
852 | ||
c6df541c | 853 | static u32 |
b2eadbc8 | 854 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c | 855 | { |
0d1aacac | 856 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
857 | } |
858 | ||
b70ec5bf MK |
859 | static void |
860 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
861 | { | |
0d1aacac | 862 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
863 | } |
864 | ||
e48d8634 DV |
865 | static bool |
866 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
867 | { | |
868 | struct drm_device *dev = ring->dev; | |
4640c4ff | 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 870 | unsigned long flags; |
e48d8634 DV |
871 | |
872 | if (!dev->irq_enabled) | |
873 | return false; | |
874 | ||
7338aefa | 875 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
876 | if (ring->irq_refcount++ == 0) |
877 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 878 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
879 | |
880 | return true; | |
881 | } | |
882 | ||
883 | static void | |
884 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
885 | { | |
886 | struct drm_device *dev = ring->dev; | |
4640c4ff | 887 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 888 | unsigned long flags; |
e48d8634 | 889 | |
7338aefa | 890 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
891 | if (--ring->irq_refcount == 0) |
892 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 893 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
894 | } |
895 | ||
b13c2b96 | 896 | static bool |
e3670319 | 897 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 898 | { |
78501eac | 899 | struct drm_device *dev = ring->dev; |
4640c4ff | 900 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 901 | unsigned long flags; |
62fdfeaf | 902 | |
b13c2b96 CW |
903 | if (!dev->irq_enabled) |
904 | return false; | |
905 | ||
7338aefa | 906 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 907 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
908 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
909 | I915_WRITE(IMR, dev_priv->irq_mask); | |
910 | POSTING_READ(IMR); | |
911 | } | |
7338aefa | 912 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
913 | |
914 | return true; | |
62fdfeaf EA |
915 | } |
916 | ||
8187a2b7 | 917 | static void |
e3670319 | 918 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 919 | { |
78501eac | 920 | struct drm_device *dev = ring->dev; |
4640c4ff | 921 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 922 | unsigned long flags; |
62fdfeaf | 923 | |
7338aefa | 924 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 925 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
926 | dev_priv->irq_mask |= ring->irq_enable_mask; |
927 | I915_WRITE(IMR, dev_priv->irq_mask); | |
928 | POSTING_READ(IMR); | |
929 | } | |
7338aefa | 930 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
931 | } |
932 | ||
c2798b19 CW |
933 | static bool |
934 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
935 | { | |
936 | struct drm_device *dev = ring->dev; | |
4640c4ff | 937 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 938 | unsigned long flags; |
c2798b19 CW |
939 | |
940 | if (!dev->irq_enabled) | |
941 | return false; | |
942 | ||
7338aefa | 943 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 944 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
945 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
946 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
947 | POSTING_READ16(IMR); | |
948 | } | |
7338aefa | 949 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
950 | |
951 | return true; | |
952 | } | |
953 | ||
954 | static void | |
955 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
956 | { | |
957 | struct drm_device *dev = ring->dev; | |
4640c4ff | 958 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 959 | unsigned long flags; |
c2798b19 | 960 | |
7338aefa | 961 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 962 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
963 | dev_priv->irq_mask |= ring->irq_enable_mask; |
964 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
965 | POSTING_READ16(IMR); | |
966 | } | |
7338aefa | 967 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
968 | } |
969 | ||
78501eac | 970 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 971 | { |
4593010b | 972 | struct drm_device *dev = ring->dev; |
4640c4ff | 973 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
974 | u32 mmio = 0; |
975 | ||
976 | /* The ring status page addresses are no longer next to the rest of | |
977 | * the ring registers as of gen7. | |
978 | */ | |
979 | if (IS_GEN7(dev)) { | |
980 | switch (ring->id) { | |
96154f2f | 981 | case RCS: |
4593010b EA |
982 | mmio = RENDER_HWS_PGA_GEN7; |
983 | break; | |
96154f2f | 984 | case BCS: |
4593010b EA |
985 | mmio = BLT_HWS_PGA_GEN7; |
986 | break; | |
96154f2f | 987 | case VCS: |
4593010b EA |
988 | mmio = BSD_HWS_PGA_GEN7; |
989 | break; | |
4a3dd19d | 990 | case VECS: |
9a8a2213 BW |
991 | mmio = VEBOX_HWS_PGA_GEN7; |
992 | break; | |
4593010b EA |
993 | } |
994 | } else if (IS_GEN6(ring->dev)) { | |
995 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
996 | } else { | |
eb0d4b75 | 997 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
998 | mmio = RING_HWS_PGA(ring->mmio_base); |
999 | } | |
1000 | ||
78501eac CW |
1001 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1002 | POSTING_READ(mmio); | |
884020bf | 1003 | |
dc616b89 DL |
1004 | /* |
1005 | * Flush the TLB for this page | |
1006 | * | |
1007 | * FIXME: These two bits have disappeared on gen8, so a question | |
1008 | * arises: do we still need this and if so how should we go about | |
1009 | * invalidating the TLB? | |
1010 | */ | |
1011 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1012 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1013 | |
1014 | /* ring should be idle before issuing a sync flush*/ | |
1015 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1016 | ||
884020bf CW |
1017 | I915_WRITE(reg, |
1018 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1019 | INSTPM_SYNC_FLUSH)); | |
1020 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1021 | 1000)) | |
1022 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1023 | ring->name); | |
1024 | } | |
8187a2b7 ZN |
1025 | } |
1026 | ||
b72f3acb | 1027 | static int |
78501eac CW |
1028 | bsd_ring_flush(struct intel_ring_buffer *ring, |
1029 | u32 invalidate_domains, | |
1030 | u32 flush_domains) | |
d1b851fc | 1031 | { |
b72f3acb CW |
1032 | int ret; |
1033 | ||
b72f3acb CW |
1034 | ret = intel_ring_begin(ring, 2); |
1035 | if (ret) | |
1036 | return ret; | |
1037 | ||
1038 | intel_ring_emit(ring, MI_FLUSH); | |
1039 | intel_ring_emit(ring, MI_NOOP); | |
1040 | intel_ring_advance(ring); | |
1041 | return 0; | |
d1b851fc ZN |
1042 | } |
1043 | ||
3cce469c | 1044 | static int |
9d773091 | 1045 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 1046 | { |
3cce469c CW |
1047 | int ret; |
1048 | ||
1049 | ret = intel_ring_begin(ring, 4); | |
1050 | if (ret) | |
1051 | return ret; | |
6f392d54 | 1052 | |
3cce469c CW |
1053 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1054 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1055 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1056 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1057 | __intel_ring_advance(ring); |
d1b851fc | 1058 | |
3cce469c | 1059 | return 0; |
d1b851fc ZN |
1060 | } |
1061 | ||
0f46832f | 1062 | static bool |
25c06300 | 1063 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1064 | { |
1065 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1066 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1067 | unsigned long flags; |
0f46832f CW |
1068 | |
1069 | if (!dev->irq_enabled) | |
1070 | return false; | |
1071 | ||
7338aefa | 1072 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1073 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1074 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1075 | I915_WRITE_IMR(ring, |
1076 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1077 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1078 | else |
1079 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 1080 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1081 | } |
7338aefa | 1082 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1083 | |
1084 | return true; | |
1085 | } | |
1086 | ||
1087 | static void | |
25c06300 | 1088 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1089 | { |
1090 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1091 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1092 | unsigned long flags; |
0f46832f | 1093 | |
7338aefa | 1094 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1095 | if (--ring->irq_refcount == 0) { |
040d2baa | 1096 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1097 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1098 | else |
1099 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1100 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1101 | } |
7338aefa | 1102 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1103 | } |
1104 | ||
a19d2933 BW |
1105 | static bool |
1106 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |
1107 | { | |
1108 | struct drm_device *dev = ring->dev; | |
1109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1110 | unsigned long flags; | |
1111 | ||
1112 | if (!dev->irq_enabled) | |
1113 | return false; | |
1114 | ||
59cdb63d | 1115 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1116 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1117 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1118 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1119 | } |
59cdb63d | 1120 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1121 | |
1122 | return true; | |
1123 | } | |
1124 | ||
1125 | static void | |
1126 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |
1127 | { | |
1128 | struct drm_device *dev = ring->dev; | |
1129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1130 | unsigned long flags; | |
1131 | ||
1132 | if (!dev->irq_enabled) | |
1133 | return; | |
1134 | ||
59cdb63d | 1135 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1136 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1137 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1138 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1139 | } |
59cdb63d | 1140 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1141 | } |
1142 | ||
abd58f01 BW |
1143 | static bool |
1144 | gen8_ring_get_irq(struct intel_ring_buffer *ring) | |
1145 | { | |
1146 | struct drm_device *dev = ring->dev; | |
1147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1148 | unsigned long flags; | |
1149 | ||
1150 | if (!dev->irq_enabled) | |
1151 | return false; | |
1152 | ||
1153 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1154 | if (ring->irq_refcount++ == 0) { | |
1155 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1156 | I915_WRITE_IMR(ring, | |
1157 | ~(ring->irq_enable_mask | | |
1158 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1159 | } else { | |
1160 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1161 | } | |
1162 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1163 | } | |
1164 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1165 | ||
1166 | return true; | |
1167 | } | |
1168 | ||
1169 | static void | |
1170 | gen8_ring_put_irq(struct intel_ring_buffer *ring) | |
1171 | { | |
1172 | struct drm_device *dev = ring->dev; | |
1173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1174 | unsigned long flags; | |
1175 | ||
1176 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1177 | if (--ring->irq_refcount == 0) { | |
1178 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1179 | I915_WRITE_IMR(ring, | |
1180 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1181 | } else { | |
1182 | I915_WRITE_IMR(ring, ~0); | |
1183 | } | |
1184 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1185 | } | |
1186 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1187 | } | |
1188 | ||
d1b851fc | 1189 | static int |
d7d4eedd CW |
1190 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1191 | u32 offset, u32 length, | |
1192 | unsigned flags) | |
d1b851fc | 1193 | { |
e1f99ce6 | 1194 | int ret; |
78501eac | 1195 | |
e1f99ce6 CW |
1196 | ret = intel_ring_begin(ring, 2); |
1197 | if (ret) | |
1198 | return ret; | |
1199 | ||
78501eac | 1200 | intel_ring_emit(ring, |
65f56876 CW |
1201 | MI_BATCH_BUFFER_START | |
1202 | MI_BATCH_GTT | | |
d7d4eedd | 1203 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1204 | intel_ring_emit(ring, offset); |
78501eac CW |
1205 | intel_ring_advance(ring); |
1206 | ||
d1b851fc ZN |
1207 | return 0; |
1208 | } | |
1209 | ||
b45305fc DV |
1210 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1211 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1212 | static int |
fb3256da | 1213 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1214 | u32 offset, u32 len, |
1215 | unsigned flags) | |
62fdfeaf | 1216 | { |
c4e7a414 | 1217 | int ret; |
62fdfeaf | 1218 | |
b45305fc DV |
1219 | if (flags & I915_DISPATCH_PINNED) { |
1220 | ret = intel_ring_begin(ring, 4); | |
1221 | if (ret) | |
1222 | return ret; | |
62fdfeaf | 1223 | |
b45305fc DV |
1224 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1225 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1226 | intel_ring_emit(ring, offset + len - 8); | |
1227 | intel_ring_emit(ring, MI_NOOP); | |
1228 | intel_ring_advance(ring); | |
1229 | } else { | |
0d1aacac | 1230 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1231 | |
1232 | if (len > I830_BATCH_LIMIT) | |
1233 | return -ENOSPC; | |
1234 | ||
1235 | ret = intel_ring_begin(ring, 9+3); | |
1236 | if (ret) | |
1237 | return ret; | |
1238 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1239 | * scratch bo area (so that the CS never stumbles over its tlb | |
1240 | * invalidation bug) ... */ | |
1241 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1242 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1243 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1244 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1245 | intel_ring_emit(ring, 0); | |
1246 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1247 | intel_ring_emit(ring, cs_offset); | |
1248 | intel_ring_emit(ring, 0); | |
1249 | intel_ring_emit(ring, 4096); | |
1250 | intel_ring_emit(ring, offset); | |
1251 | intel_ring_emit(ring, MI_FLUSH); | |
1252 | ||
1253 | /* ... and execute it. */ | |
1254 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1255 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1256 | intel_ring_emit(ring, cs_offset + len - 8); | |
1257 | intel_ring_advance(ring); | |
1258 | } | |
e1f99ce6 | 1259 | |
fb3256da DV |
1260 | return 0; |
1261 | } | |
1262 | ||
1263 | static int | |
1264 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1265 | u32 offset, u32 len, |
1266 | unsigned flags) | |
fb3256da DV |
1267 | { |
1268 | int ret; | |
1269 | ||
1270 | ret = intel_ring_begin(ring, 2); | |
1271 | if (ret) | |
1272 | return ret; | |
1273 | ||
65f56876 | 1274 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1275 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1276 | intel_ring_advance(ring); |
62fdfeaf | 1277 | |
62fdfeaf EA |
1278 | return 0; |
1279 | } | |
1280 | ||
78501eac | 1281 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1282 | { |
05394f39 | 1283 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1284 | |
8187a2b7 ZN |
1285 | obj = ring->status_page.obj; |
1286 | if (obj == NULL) | |
62fdfeaf | 1287 | return; |
62fdfeaf | 1288 | |
9da3da66 | 1289 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1290 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1291 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1292 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1293 | } |
1294 | ||
78501eac | 1295 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1296 | { |
78501eac | 1297 | struct drm_device *dev = ring->dev; |
05394f39 | 1298 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1299 | int ret; |
1300 | ||
62fdfeaf EA |
1301 | obj = i915_gem_alloc_object(dev, 4096); |
1302 | if (obj == NULL) { | |
1303 | DRM_ERROR("Failed to allocate status page\n"); | |
1304 | ret = -ENOMEM; | |
1305 | goto err; | |
1306 | } | |
e4ffd173 | 1307 | |
e01f6929 DV |
1308 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1309 | if (ret) | |
1310 | goto err_unref; | |
62fdfeaf | 1311 | |
9a6bbb62 | 1312 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); |
1ec9e26d | 1313 | if (ret) |
62fdfeaf | 1314 | goto err_unref; |
62fdfeaf | 1315 | |
f343c5f6 | 1316 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1317 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1318 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1319 | ret = -ENOMEM; |
62fdfeaf EA |
1320 | goto err_unpin; |
1321 | } | |
8187a2b7 ZN |
1322 | ring->status_page.obj = obj; |
1323 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1324 | |
8187a2b7 ZN |
1325 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1326 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1327 | |
1328 | return 0; | |
1329 | ||
1330 | err_unpin: | |
d7f46fc4 | 1331 | i915_gem_object_ggtt_unpin(obj); |
62fdfeaf | 1332 | err_unref: |
05394f39 | 1333 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1334 | err: |
8187a2b7 | 1335 | return ret; |
62fdfeaf EA |
1336 | } |
1337 | ||
035dc1e0 | 1338 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
6b8294a4 CW |
1339 | { |
1340 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1341 | |
1342 | if (!dev_priv->status_page_dmah) { | |
1343 | dev_priv->status_page_dmah = | |
1344 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1345 | if (!dev_priv->status_page_dmah) | |
1346 | return -ENOMEM; | |
1347 | } | |
1348 | ||
6b8294a4 CW |
1349 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1350 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
c43b5634 BW |
1355 | static int intel_init_ring_buffer(struct drm_device *dev, |
1356 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1357 | { |
05394f39 | 1358 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1359 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1360 | int ret; |
1361 | ||
8187a2b7 | 1362 | ring->dev = dev; |
23bc5982 CW |
1363 | INIT_LIST_HEAD(&ring->active_list); |
1364 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1365 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1366 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1367 | |
b259f673 | 1368 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1369 | |
8187a2b7 | 1370 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1371 | ret = init_status_page(ring); |
8187a2b7 ZN |
1372 | if (ret) |
1373 | return ret; | |
6b8294a4 CW |
1374 | } else { |
1375 | BUG_ON(ring->id != RCS); | |
035dc1e0 | 1376 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1377 | if (ret) |
1378 | return ret; | |
8187a2b7 | 1379 | } |
62fdfeaf | 1380 | |
ebc052e0 CW |
1381 | obj = NULL; |
1382 | if (!HAS_LLC(dev)) | |
1383 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1384 | if (obj == NULL) | |
1385 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1386 | if (obj == NULL) { |
1387 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1388 | ret = -ENOMEM; |
dd785e35 | 1389 | goto err_hws; |
62fdfeaf | 1390 | } |
62fdfeaf | 1391 | |
05394f39 | 1392 | ring->obj = obj; |
8187a2b7 | 1393 | |
1ec9e26d | 1394 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1395 | if (ret) |
1396 | goto err_unref; | |
62fdfeaf | 1397 | |
3eef8918 CW |
1398 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1399 | if (ret) | |
1400 | goto err_unpin; | |
1401 | ||
dd2757f8 | 1402 | ring->virtual_start = |
f343c5f6 | 1403 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
dd2757f8 | 1404 | ring->size); |
4225d0f2 | 1405 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1406 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1407 | ret = -EINVAL; |
dd785e35 | 1408 | goto err_unpin; |
62fdfeaf EA |
1409 | } |
1410 | ||
78501eac | 1411 | ret = ring->init(ring); |
dd785e35 CW |
1412 | if (ret) |
1413 | goto err_unmap; | |
62fdfeaf | 1414 | |
55249baa CW |
1415 | /* Workaround an erratum on the i830 which causes a hang if |
1416 | * the TAIL pointer points to within the last 2 cachelines | |
1417 | * of the buffer. | |
1418 | */ | |
1419 | ring->effective_size = ring->size; | |
27c1cbd0 | 1420 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1421 | ring->effective_size -= 128; |
1422 | ||
351e3db2 BV |
1423 | i915_cmd_parser_init_ring(ring); |
1424 | ||
c584fe47 | 1425 | return 0; |
dd785e35 CW |
1426 | |
1427 | err_unmap: | |
4225d0f2 | 1428 | iounmap(ring->virtual_start); |
dd785e35 | 1429 | err_unpin: |
d7f46fc4 | 1430 | i915_gem_object_ggtt_unpin(obj); |
dd785e35 | 1431 | err_unref: |
05394f39 CW |
1432 | drm_gem_object_unreference(&obj->base); |
1433 | ring->obj = NULL; | |
dd785e35 | 1434 | err_hws: |
78501eac | 1435 | cleanup_status_page(ring); |
8187a2b7 | 1436 | return ret; |
62fdfeaf EA |
1437 | } |
1438 | ||
78501eac | 1439 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1440 | { |
33626e6a CW |
1441 | struct drm_i915_private *dev_priv; |
1442 | int ret; | |
1443 | ||
05394f39 | 1444 | if (ring->obj == NULL) |
62fdfeaf EA |
1445 | return; |
1446 | ||
33626e6a CW |
1447 | /* Disable the ring buffer. The ring must be idle at this point */ |
1448 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1449 | ret = intel_ring_idle(ring); |
3d57e5bd | 1450 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
29ee3991 CW |
1451 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
1452 | ring->name, ret); | |
1453 | ||
33626e6a CW |
1454 | I915_WRITE_CTL(ring, 0); |
1455 | ||
4225d0f2 | 1456 | iounmap(ring->virtual_start); |
62fdfeaf | 1457 | |
d7f46fc4 | 1458 | i915_gem_object_ggtt_unpin(ring->obj); |
05394f39 CW |
1459 | drm_gem_object_unreference(&ring->obj->base); |
1460 | ring->obj = NULL; | |
3d57e5bd BW |
1461 | ring->preallocated_lazy_request = NULL; |
1462 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1463 | |
8d19215b ZN |
1464 | if (ring->cleanup) |
1465 | ring->cleanup(ring); | |
1466 | ||
78501eac | 1467 | cleanup_status_page(ring); |
62fdfeaf EA |
1468 | } |
1469 | ||
a71d8d94 CW |
1470 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
1471 | { | |
1472 | struct drm_i915_gem_request *request; | |
1f70999f | 1473 | u32 seqno = 0, tail; |
a71d8d94 CW |
1474 | int ret; |
1475 | ||
a71d8d94 CW |
1476 | if (ring->last_retired_head != -1) { |
1477 | ring->head = ring->last_retired_head; | |
1478 | ring->last_retired_head = -1; | |
1f70999f | 1479 | |
a71d8d94 CW |
1480 | ring->space = ring_space(ring); |
1481 | if (ring->space >= n) | |
1482 | return 0; | |
1483 | } | |
1484 | ||
1485 | list_for_each_entry(request, &ring->request_list, list) { | |
1486 | int space; | |
1487 | ||
1488 | if (request->tail == -1) | |
1489 | continue; | |
1490 | ||
633cf8f5 | 1491 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1492 | if (space < 0) |
1493 | space += ring->size; | |
1494 | if (space >= n) { | |
1495 | seqno = request->seqno; | |
1f70999f | 1496 | tail = request->tail; |
a71d8d94 CW |
1497 | break; |
1498 | } | |
1499 | ||
1500 | /* Consume this request in case we need more space than | |
1501 | * is available and so need to prevent a race between | |
1502 | * updating last_retired_head and direct reads of | |
1503 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1504 | */ | |
1505 | request->tail = -1; | |
1506 | } | |
1507 | ||
1508 | if (seqno == 0) | |
1509 | return -ENOSPC; | |
1510 | ||
1f70999f | 1511 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1512 | if (ret) |
1513 | return ret; | |
1514 | ||
1f70999f | 1515 | ring->head = tail; |
a71d8d94 CW |
1516 | ring->space = ring_space(ring); |
1517 | if (WARN_ON(ring->space < n)) | |
1518 | return -ENOSPC; | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
3e960501 | 1523 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1524 | { |
78501eac | 1525 | struct drm_device *dev = ring->dev; |
cae5852d | 1526 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1527 | unsigned long end; |
a71d8d94 | 1528 | int ret; |
c7dca47b | 1529 | |
a71d8d94 CW |
1530 | ret = intel_ring_wait_request(ring, n); |
1531 | if (ret != -ENOSPC) | |
1532 | return ret; | |
1533 | ||
09246732 CW |
1534 | /* force the tail write in case we have been skipping them */ |
1535 | __intel_ring_advance(ring); | |
1536 | ||
db53a302 | 1537 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1538 | /* With GEM the hangcheck timer should kick us out of the loop, |
1539 | * leaving it early runs the risk of corrupting GEM state (due | |
1540 | * to running on almost untested codepaths). But on resume | |
1541 | * timers don't work yet, so prevent a complete hang in that | |
1542 | * case by choosing an insanely large timeout. */ | |
1543 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1544 | |
8187a2b7 | 1545 | do { |
c7dca47b CW |
1546 | ring->head = I915_READ_HEAD(ring); |
1547 | ring->space = ring_space(ring); | |
62fdfeaf | 1548 | if (ring->space >= n) { |
db53a302 | 1549 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1550 | return 0; |
1551 | } | |
1552 | ||
fb19e2ac DV |
1553 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1554 | dev->primary->master) { | |
62fdfeaf EA |
1555 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1556 | if (master_priv->sarea_priv) | |
1557 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1558 | } | |
d1b851fc | 1559 | |
e60a0b10 | 1560 | msleep(1); |
d6b2c790 | 1561 | |
33196ded DV |
1562 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1563 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1564 | if (ret) |
1565 | return ret; | |
8187a2b7 | 1566 | } while (!time_after(jiffies, end)); |
db53a302 | 1567 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1568 | return -EBUSY; |
1569 | } | |
62fdfeaf | 1570 | |
3e960501 CW |
1571 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1572 | { | |
1573 | uint32_t __iomem *virt; | |
1574 | int rem = ring->size - ring->tail; | |
1575 | ||
1576 | if (ring->space < rem) { | |
1577 | int ret = ring_wait_for_space(ring, rem); | |
1578 | if (ret) | |
1579 | return ret; | |
1580 | } | |
1581 | ||
1582 | virt = ring->virtual_start + ring->tail; | |
1583 | rem /= 4; | |
1584 | while (rem--) | |
1585 | iowrite32(MI_NOOP, virt++); | |
1586 | ||
1587 | ring->tail = 0; | |
1588 | ring->space = ring_space(ring); | |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1594 | { | |
1595 | u32 seqno; | |
1596 | int ret; | |
1597 | ||
1598 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1599 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1600 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1601 | if (ret) |
1602 | return ret; | |
1603 | } | |
1604 | ||
1605 | /* Wait upon the last request to be completed */ | |
1606 | if (list_empty(&ring->request_list)) | |
1607 | return 0; | |
1608 | ||
1609 | seqno = list_entry(ring->request_list.prev, | |
1610 | struct drm_i915_gem_request, | |
1611 | list)->seqno; | |
1612 | ||
1613 | return i915_wait_seqno(ring, seqno); | |
1614 | } | |
1615 | ||
9d773091 CW |
1616 | static int |
1617 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1618 | { | |
1823521d | 1619 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1620 | return 0; |
1621 | ||
3c0e234c CW |
1622 | if (ring->preallocated_lazy_request == NULL) { |
1623 | struct drm_i915_gem_request *request; | |
1624 | ||
1625 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1626 | if (request == NULL) | |
1627 | return -ENOMEM; | |
1628 | ||
1629 | ring->preallocated_lazy_request = request; | |
1630 | } | |
1631 | ||
1823521d | 1632 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1633 | } |
1634 | ||
304d695c CW |
1635 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
1636 | int bytes) | |
cbcc80df MK |
1637 | { |
1638 | int ret; | |
1639 | ||
1640 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1641 | ret = intel_wrap_ring_buffer(ring); | |
1642 | if (unlikely(ret)) | |
1643 | return ret; | |
1644 | } | |
1645 | ||
1646 | if (unlikely(ring->space < bytes)) { | |
1647 | ret = ring_wait_for_space(ring, bytes); | |
1648 | if (unlikely(ret)) | |
1649 | return ret; | |
1650 | } | |
1651 | ||
cbcc80df MK |
1652 | return 0; |
1653 | } | |
1654 | ||
e1f99ce6 CW |
1655 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1656 | int num_dwords) | |
8187a2b7 | 1657 | { |
4640c4ff | 1658 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1659 | int ret; |
78501eac | 1660 | |
33196ded DV |
1661 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1662 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1663 | if (ret) |
1664 | return ret; | |
21dd3734 | 1665 | |
304d695c CW |
1666 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1667 | if (ret) | |
1668 | return ret; | |
1669 | ||
9d773091 CW |
1670 | /* Preallocate the olr before touching the ring */ |
1671 | ret = intel_ring_alloc_seqno(ring); | |
1672 | if (ret) | |
1673 | return ret; | |
1674 | ||
304d695c CW |
1675 | ring->space -= num_dwords * sizeof(uint32_t); |
1676 | return 0; | |
8187a2b7 | 1677 | } |
78501eac | 1678 | |
753b1ad4 VS |
1679 | /* Align the ring tail to a cacheline boundary */ |
1680 | int intel_ring_cacheline_align(struct intel_ring_buffer *ring) | |
1681 | { | |
1682 | int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t); | |
1683 | int ret; | |
1684 | ||
1685 | if (num_dwords == 0) | |
1686 | return 0; | |
1687 | ||
1688 | ret = intel_ring_begin(ring, num_dwords); | |
1689 | if (ret) | |
1690 | return ret; | |
1691 | ||
1692 | while (num_dwords--) | |
1693 | intel_ring_emit(ring, MI_NOOP); | |
1694 | ||
1695 | intel_ring_advance(ring); | |
1696 | ||
1697 | return 0; | |
1698 | } | |
1699 | ||
f7e98ad4 | 1700 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1701 | { |
f7e98ad4 | 1702 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 | 1703 | |
1823521d | 1704 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1705 | |
f7e98ad4 MK |
1706 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1707 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1708 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
5020150b BW |
1709 | if (HAS_VEBOX(ring->dev)) |
1710 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); | |
e1f99ce6 | 1711 | } |
d97ed339 | 1712 | |
f7e98ad4 | 1713 | ring->set_seqno(ring, seqno); |
92cab734 | 1714 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1715 | } |
62fdfeaf | 1716 | |
78501eac | 1717 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1718 | u32 value) |
881f47b6 | 1719 | { |
4640c4ff | 1720 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1721 | |
1722 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1723 | |
1724 | /* Disable notification that the ring is IDLE. The GT | |
1725 | * will then assume that it is busy and bring it out of rc6. | |
1726 | */ | |
0206e353 | 1727 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1728 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1729 | ||
1730 | /* Clear the context id. Here be magic! */ | |
1731 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1732 | |
12f55818 | 1733 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1734 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1735 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1736 | 50)) | |
1737 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1738 | |
12f55818 | 1739 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1740 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1741 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1742 | ||
1743 | /* Let the ring send IDLE messages to the GT again, | |
1744 | * and so let it sleep to conserve power when idle. | |
1745 | */ | |
0206e353 | 1746 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1747 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1748 | } |
1749 | ||
ea251324 BW |
1750 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1751 | u32 invalidate, u32 flush) | |
881f47b6 | 1752 | { |
71a77e07 | 1753 | uint32_t cmd; |
b72f3acb CW |
1754 | int ret; |
1755 | ||
b72f3acb CW |
1756 | ret = intel_ring_begin(ring, 4); |
1757 | if (ret) | |
1758 | return ret; | |
1759 | ||
71a77e07 | 1760 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1761 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1762 | cmd += 1; | |
9a289771 JB |
1763 | /* |
1764 | * Bspec vol 1c.5 - video engine command streamer: | |
1765 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1766 | * operation is complete. This bit is only valid when the | |
1767 | * Post-Sync Operation field is a value of 1h or 3h." | |
1768 | */ | |
71a77e07 | 1769 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1770 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1771 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1772 | intel_ring_emit(ring, cmd); |
9a289771 | 1773 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1774 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1775 | intel_ring_emit(ring, 0); /* upper addr */ | |
1776 | intel_ring_emit(ring, 0); /* value */ | |
1777 | } else { | |
1778 | intel_ring_emit(ring, 0); | |
1779 | intel_ring_emit(ring, MI_NOOP); | |
1780 | } | |
b72f3acb CW |
1781 | intel_ring_advance(ring); |
1782 | return 0; | |
881f47b6 XH |
1783 | } |
1784 | ||
1c7a0623 BW |
1785 | static int |
1786 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1787 | u32 offset, u32 len, | |
1788 | unsigned flags) | |
1789 | { | |
28cf5415 BW |
1790 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1791 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
1792 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
1793 | int ret; |
1794 | ||
1795 | ret = intel_ring_begin(ring, 4); | |
1796 | if (ret) | |
1797 | return ret; | |
1798 | ||
1799 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 1800 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
1c7a0623 BW |
1801 | intel_ring_emit(ring, offset); |
1802 | intel_ring_emit(ring, 0); | |
1803 | intel_ring_emit(ring, MI_NOOP); | |
1804 | intel_ring_advance(ring); | |
1805 | ||
1806 | return 0; | |
1807 | } | |
1808 | ||
d7d4eedd CW |
1809 | static int |
1810 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1811 | u32 offset, u32 len, | |
1812 | unsigned flags) | |
1813 | { | |
1814 | int ret; | |
1815 | ||
1816 | ret = intel_ring_begin(ring, 2); | |
1817 | if (ret) | |
1818 | return ret; | |
1819 | ||
1820 | intel_ring_emit(ring, | |
1821 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1822 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1823 | /* bit0-7 is the length on GEN6+ */ | |
1824 | intel_ring_emit(ring, offset); | |
1825 | intel_ring_advance(ring); | |
1826 | ||
1827 | return 0; | |
1828 | } | |
1829 | ||
881f47b6 | 1830 | static int |
78501eac | 1831 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1832 | u32 offset, u32 len, |
1833 | unsigned flags) | |
881f47b6 | 1834 | { |
0206e353 | 1835 | int ret; |
ab6f8e32 | 1836 | |
0206e353 AJ |
1837 | ret = intel_ring_begin(ring, 2); |
1838 | if (ret) | |
1839 | return ret; | |
e1f99ce6 | 1840 | |
d7d4eedd CW |
1841 | intel_ring_emit(ring, |
1842 | MI_BATCH_BUFFER_START | | |
1843 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1844 | /* bit0-7 is the length on GEN6+ */ |
1845 | intel_ring_emit(ring, offset); | |
1846 | intel_ring_advance(ring); | |
ab6f8e32 | 1847 | |
0206e353 | 1848 | return 0; |
881f47b6 XH |
1849 | } |
1850 | ||
549f7365 CW |
1851 | /* Blitter support (SandyBridge+) */ |
1852 | ||
ea251324 BW |
1853 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1854 | u32 invalidate, u32 flush) | |
8d19215b | 1855 | { |
fd3da6c9 | 1856 | struct drm_device *dev = ring->dev; |
71a77e07 | 1857 | uint32_t cmd; |
b72f3acb CW |
1858 | int ret; |
1859 | ||
6a233c78 | 1860 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1861 | if (ret) |
1862 | return ret; | |
1863 | ||
71a77e07 | 1864 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1865 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1866 | cmd += 1; | |
9a289771 JB |
1867 | /* |
1868 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1869 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1870 | * operation is complete. This bit is only valid when the | |
1871 | * Post-Sync Operation field is a value of 1h or 3h." | |
1872 | */ | |
71a77e07 | 1873 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1874 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1875 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1876 | intel_ring_emit(ring, cmd); |
9a289771 | 1877 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1878 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1879 | intel_ring_emit(ring, 0); /* upper addr */ | |
1880 | intel_ring_emit(ring, 0); /* value */ | |
1881 | } else { | |
1882 | intel_ring_emit(ring, 0); | |
1883 | intel_ring_emit(ring, MI_NOOP); | |
1884 | } | |
b72f3acb | 1885 | intel_ring_advance(ring); |
fd3da6c9 | 1886 | |
9688ecad | 1887 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
1888 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
1889 | ||
b72f3acb | 1890 | return 0; |
8d19215b ZN |
1891 | } |
1892 | ||
5c1143bb XH |
1893 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1894 | { | |
4640c4ff | 1895 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 1896 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1897 | |
59465b5f DV |
1898 | ring->name = "render ring"; |
1899 | ring->id = RCS; | |
1900 | ring->mmio_base = RENDER_RING_BASE; | |
1901 | ||
1ec14ad3 CW |
1902 | if (INTEL_INFO(dev)->gen >= 6) { |
1903 | ring->add_request = gen6_add_request; | |
4772eaeb | 1904 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1905 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1906 | ring->flush = gen6_render_ring_flush; |
abd58f01 | 1907 | if (INTEL_INFO(dev)->gen >= 8) { |
a5f3d68e | 1908 | ring->flush = gen8_render_ring_flush; |
abd58f01 BW |
1909 | ring->irq_get = gen8_ring_get_irq; |
1910 | ring->irq_put = gen8_ring_put_irq; | |
1911 | } else { | |
1912 | ring->irq_get = gen6_ring_get_irq; | |
1913 | ring->irq_put = gen6_ring_put_irq; | |
1914 | } | |
cc609d5d | 1915 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1916 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1917 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1918 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1919 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1920 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1921 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1922 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1923 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1924 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1925 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1926 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1927 | } else if (IS_GEN5(dev)) { |
1928 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1929 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1930 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1931 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1932 | ring->irq_get = gen5_ring_get_irq; |
1933 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1934 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1935 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1936 | } else { |
8620a3a9 | 1937 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1938 | if (INTEL_INFO(dev)->gen < 4) |
1939 | ring->flush = gen2_render_ring_flush; | |
1940 | else | |
1941 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1942 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1943 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1944 | if (IS_GEN2(dev)) { |
1945 | ring->irq_get = i8xx_ring_get_irq; | |
1946 | ring->irq_put = i8xx_ring_put_irq; | |
1947 | } else { | |
1948 | ring->irq_get = i9xx_ring_get_irq; | |
1949 | ring->irq_put = i9xx_ring_put_irq; | |
1950 | } | |
e3670319 | 1951 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1952 | } |
59465b5f | 1953 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1954 | if (IS_HASWELL(dev)) |
1955 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
1956 | else if (IS_GEN8(dev)) |
1957 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 1958 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
1959 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1960 | else if (INTEL_INFO(dev)->gen >= 4) | |
1961 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1962 | else if (IS_I830(dev) || IS_845G(dev)) | |
1963 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1964 | else | |
1965 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1966 | ring->init = init_render_ring; |
1967 | ring->cleanup = render_ring_cleanup; | |
1968 | ||
b45305fc DV |
1969 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1970 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1971 | struct drm_i915_gem_object *obj; | |
1972 | int ret; | |
1973 | ||
1974 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1975 | if (obj == NULL) { | |
1976 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1977 | return -ENOMEM; | |
1978 | } | |
1979 | ||
be1fa129 | 1980 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
1981 | if (ret != 0) { |
1982 | drm_gem_object_unreference(&obj->base); | |
1983 | DRM_ERROR("Failed to ping batch bo\n"); | |
1984 | return ret; | |
1985 | } | |
1986 | ||
0d1aacac CW |
1987 | ring->scratch.obj = obj; |
1988 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
1989 | } |
1990 | ||
1ec14ad3 | 1991 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1992 | } |
1993 | ||
e8616b6c CW |
1994 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1995 | { | |
4640c4ff | 1996 | struct drm_i915_private *dev_priv = dev->dev_private; |
e8616b6c | 1997 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6b8294a4 | 1998 | int ret; |
e8616b6c | 1999 | |
59465b5f DV |
2000 | ring->name = "render ring"; |
2001 | ring->id = RCS; | |
2002 | ring->mmio_base = RENDER_RING_BASE; | |
2003 | ||
e8616b6c | 2004 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
2005 | /* non-kms not supported on gen6+ */ |
2006 | return -ENODEV; | |
e8616b6c | 2007 | } |
28f0cbf7 DV |
2008 | |
2009 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2010 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2011 | * the special gen5 functions. */ | |
2012 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2013 | if (INTEL_INFO(dev)->gen < 4) |
2014 | ring->flush = gen2_render_ring_flush; | |
2015 | else | |
2016 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2017 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2018 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2019 | if (IS_GEN2(dev)) { |
2020 | ring->irq_get = i8xx_ring_get_irq; | |
2021 | ring->irq_put = i8xx_ring_put_irq; | |
2022 | } else { | |
2023 | ring->irq_get = i9xx_ring_get_irq; | |
2024 | ring->irq_put = i9xx_ring_put_irq; | |
2025 | } | |
28f0cbf7 | 2026 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2027 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2028 | if (INTEL_INFO(dev)->gen >= 4) |
2029 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2030 | else if (IS_I830(dev) || IS_845G(dev)) | |
2031 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2032 | else | |
2033 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2034 | ring->init = init_render_ring; |
2035 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2036 | |
2037 | ring->dev = dev; | |
2038 | INIT_LIST_HEAD(&ring->active_list); | |
2039 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
2040 | |
2041 | ring->size = size; | |
2042 | ring->effective_size = ring->size; | |
17f10fdc | 2043 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
e8616b6c CW |
2044 | ring->effective_size -= 128; |
2045 | ||
4225d0f2 DV |
2046 | ring->virtual_start = ioremap_wc(start, size); |
2047 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
2048 | DRM_ERROR("can not ioremap virtual address for" |
2049 | " ring buffer\n"); | |
2050 | return -ENOMEM; | |
2051 | } | |
2052 | ||
6b8294a4 | 2053 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2054 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
2055 | if (ret) |
2056 | return ret; | |
2057 | } | |
2058 | ||
e8616b6c CW |
2059 | return 0; |
2060 | } | |
2061 | ||
5c1143bb XH |
2062 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2063 | { | |
4640c4ff | 2064 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 2065 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2066 | |
58fa3835 DV |
2067 | ring->name = "bsd ring"; |
2068 | ring->id = VCS; | |
2069 | ||
0fd2c201 | 2070 | ring->write_tail = ring_write_tail; |
780f18c8 | 2071 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2072 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2073 | /* gen6 bsd needs a special wa for tail updates */ |
2074 | if (IS_GEN6(dev)) | |
2075 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2076 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2077 | ring->add_request = gen6_add_request; |
2078 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2079 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2080 | if (INTEL_INFO(dev)->gen >= 8) { |
2081 | ring->irq_enable_mask = | |
2082 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2083 | ring->irq_get = gen8_ring_get_irq; | |
2084 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2085 | ring->dispatch_execbuffer = |
2086 | gen8_ring_dispatch_execbuffer; | |
abd58f01 BW |
2087 | } else { |
2088 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2089 | ring->irq_get = gen6_ring_get_irq; | |
2090 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2091 | ring->dispatch_execbuffer = |
2092 | gen6_ring_dispatch_execbuffer; | |
abd58f01 | 2093 | } |
686cb5f9 | 2094 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2095 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
2096 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2097 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 2098 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
2099 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
2100 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
2101 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 2102 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
2103 | } else { |
2104 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2105 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2106 | ring->add_request = i9xx_add_request; |
58fa3835 | 2107 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2108 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2109 | if (IS_GEN5(dev)) { |
cc609d5d | 2110 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2111 | ring->irq_get = gen5_ring_get_irq; |
2112 | ring->irq_put = gen5_ring_put_irq; | |
2113 | } else { | |
e3670319 | 2114 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2115 | ring->irq_get = i9xx_ring_get_irq; |
2116 | ring->irq_put = i9xx_ring_put_irq; | |
2117 | } | |
fb3256da | 2118 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2119 | } |
2120 | ring->init = init_ring_common; | |
2121 | ||
1ec14ad3 | 2122 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2123 | } |
549f7365 CW |
2124 | |
2125 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
2126 | { | |
4640c4ff | 2127 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 2128 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 2129 | |
3535d9dd DV |
2130 | ring->name = "blitter ring"; |
2131 | ring->id = BCS; | |
2132 | ||
2133 | ring->mmio_base = BLT_RING_BASE; | |
2134 | ring->write_tail = ring_write_tail; | |
ea251324 | 2135 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2136 | ring->add_request = gen6_add_request; |
2137 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2138 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2139 | if (INTEL_INFO(dev)->gen >= 8) { |
2140 | ring->irq_enable_mask = | |
2141 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2142 | ring->irq_get = gen8_ring_get_irq; | |
2143 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2144 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2145 | } else { |
2146 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2147 | ring->irq_get = gen6_ring_get_irq; | |
2148 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2149 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2150 | } |
686cb5f9 | 2151 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2152 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
2153 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2154 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 2155 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
2156 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
2157 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
2158 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 2159 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 2160 | ring->init = init_ring_common; |
549f7365 | 2161 | |
1ec14ad3 | 2162 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2163 | } |
a7b9761d | 2164 | |
9a8a2213 BW |
2165 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2166 | { | |
4640c4ff | 2167 | struct drm_i915_private *dev_priv = dev->dev_private; |
9a8a2213 BW |
2168 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
2169 | ||
2170 | ring->name = "video enhancement ring"; | |
2171 | ring->id = VECS; | |
2172 | ||
2173 | ring->mmio_base = VEBOX_RING_BASE; | |
2174 | ring->write_tail = ring_write_tail; | |
2175 | ring->flush = gen6_ring_flush; | |
2176 | ring->add_request = gen6_add_request; | |
2177 | ring->get_seqno = gen6_ring_get_seqno; | |
2178 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2179 | |
2180 | if (INTEL_INFO(dev)->gen >= 8) { | |
2181 | ring->irq_enable_mask = | |
40c499f9 | 2182 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2183 | ring->irq_get = gen8_ring_get_irq; |
2184 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2185 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2186 | } else { |
2187 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2188 | ring->irq_get = hsw_vebox_get_irq; | |
2189 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2190 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2191 | } |
9a8a2213 BW |
2192 | ring->sync_to = gen6_ring_sync; |
2193 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2194 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2195 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2196 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2197 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
2198 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
2199 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
2200 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
2201 | ring->init = init_ring_common; | |
2202 | ||
2203 | return intel_init_ring_buffer(dev, ring); | |
2204 | } | |
2205 | ||
a7b9761d CW |
2206 | int |
2207 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
2208 | { | |
2209 | int ret; | |
2210 | ||
2211 | if (!ring->gpu_caches_dirty) | |
2212 | return 0; | |
2213 | ||
2214 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2215 | if (ret) | |
2216 | return ret; | |
2217 | ||
2218 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2219 | ||
2220 | ring->gpu_caches_dirty = false; | |
2221 | return 0; | |
2222 | } | |
2223 | ||
2224 | int | |
2225 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
2226 | { | |
2227 | uint32_t flush_domains; | |
2228 | int ret; | |
2229 | ||
2230 | flush_domains = 0; | |
2231 | if (ring->gpu_caches_dirty) | |
2232 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2233 | ||
2234 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2235 | if (ret) | |
2236 | return ret; | |
2237 | ||
2238 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2239 | ||
2240 | ring->gpu_caches_dirty = false; | |
2241 | return 0; | |
2242 | } |