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Merge git://git.infradead.org/intel-iommu
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
4772eaeb 320static int
a4872ba6 321gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 322 u32 invalidate_domains, u32 flush_domains)
323{
324 u32 flags = 0;
18393f63 325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 326 int ret;
327
f3987631
PZ		 328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
4772eaeb
PZ		 338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 345 }
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 354 /*
355 * TLB invalidate requires a post-sync write.
356 */
357 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 359
add284a3
CW		 360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
361
f3987631
PZ		 362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 366 }
367
368 ret = intel_ring_begin(ring, 4);
369 if (ret)
370 return ret;
371
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
b9e1faa7 374 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
377
378 return 0;
379}
380
884ceace
KG		 381static int
382gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
384{
385 int ret;
386
387 ret = intel_ring_begin(ring, 6);
388 if (ret)
389 return ret;
390
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
398
399 return 0;
400}
401
a5f3d68e 402static int
a4872ba6 403gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 404 u32 invalidate_domains, u32 flush_domains)
405{
406 u32 flags = 0;
18393f63 407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 408 int ret;
a5f3d68e
BW		 409
410 flags |= PIPE_CONTROL_CS_STALL;
411
412 if (flush_domains) {
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
415 }
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 425
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
430 0);
431 if (ret)
432 return ret;
a5f3d68e
BW		 433 }
434
6e0b3f8d 435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
a5f3d68e
BW		 436}
437
a4872ba6 438static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 439 u32 value)
d46eefa2 440{
4640c4ff 441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 442 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 443}
444
a4872ba6 445u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 448 u64 acthd;
8187a2b7 449
50877445
CW		 450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
455 else
456 acthd = I915_READ(ACTHD);
457
458 return acthd;
8187a2b7
ZN		 459}
460
a4872ba6 461static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 462{
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
464 u32 addr;
465
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
470}
471
af75f269
DL		 472static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
473{
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
476 u32 mmio = 0;
477
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
480 */
481 if (IS_GEN7(dev)) {
482 switch (ring->id) {
483 case RCS:
484 mmio = RENDER_HWS_PGA_GEN7;
485 break;
486 case BCS:
487 mmio = BLT_HWS_PGA_GEN7;
488 break;
489 /*
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
492 */
493 case VCS2:
494 case VCS:
495 mmio = BSD_HWS_PGA_GEN7;
496 break;
497 case VECS:
498 mmio = VEBOX_HWS_PGA_GEN7;
499 break;
500 }
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
503 } else {
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
506 }
507
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
509 POSTING_READ(mmio);
510
511 /*
512 * Flush the TLB for this page
513 *
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
517 */
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
520
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
523
524 I915_WRITE(reg,
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
526 INSTPM_SYNC_FLUSH));
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
528 1000))
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
530 ring->name);
531 }
532}
533
a4872ba6 534static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 535{
9991ae78 536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 537
9991ae78
CW		 538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
545 */
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
547 return false;
9991ae78
CW		 548 }
549 }
b7884eb4 550
7f2ab699 551 I915_WRITE_CTL(ring, 0);
570ef608 552 I915_WRITE_HEAD(ring, 0);
78501eac 553 ring->write_tail(ring, 0);
8187a2b7 554
9991ae78
CW		 555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
558 }
a51435a3 559
9991ae78
CW		 560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
561}
8187a2b7 562
a4872ba6 563static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 564{
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 569 int ret = 0;
570
59bad947 571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 572
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 ring->name,
578 I915_READ_CTL(ring),
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
8187a2b7 582
9991ae78 583 if (!stop_ring(ring)) {
6fd0d56e
CW		 584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 ring->name,
587 I915_READ_CTL(ring),
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
9991ae78
CW		 591 ret = -EIO;
592 goto out;
6fd0d56e 593 }
8187a2b7
ZN		 594 }
595
9991ae78
CW		 596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
598 else
599 ring_setup_phys_status_page(ring);
600
ece4a17d
JK		 601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
603
0d8957c8
DV		 604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
f343c5f6 608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
616
7f2ab699 617 I915_WRITE_CTL(ring,
93b0a4e0 618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 619 | RING_VALID);
8187a2b7 620
8187a2b7 621 /* If the head is still not zero, the ring is dead */
f01db988 622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 625 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 ring->name,
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 631 ret = -EIO;
632 goto out;
8187a2b7
ZN		 633 }
634
ebd0fd4b 635 ringbuf->last_retired_head = -1;
5c6c6003
CW		 636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 638 intel_ring_update_space(ringbuf);
1ec14ad3 639
50f018df
CW		 640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
641
b7884eb4 642out:
59bad947 643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 644
645 return ret;
8187a2b7
ZN		 646}
647
9b1136d5
OM		 648void
649intel_fini_pipe_control(struct intel_engine_cs *ring)
650{
651 struct drm_device *dev = ring->dev;
652
653 if (ring->scratch.obj == NULL)
654 return;
655
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(sg_page(ring->scratch.obj->pages->sgl));
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
659 }
660
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
663}
664
665int
666intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 667{
c6df541c
CW		 668 int ret;
669
bfc882b4 670 WARN_ON(ring->scratch.obj);
c6df541c 671
0d1aacac
CW		 672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
c6df541c
CW		 674 DRM_ERROR("Failed to allocate seqno page\n");
675 ret = -ENOMEM;
676 goto err;
677 }
e4ffd173 678
a9cc726c
DV		 679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
680 if (ret)
681 goto err_unref;
c6df541c 682
1ec9e26d 683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 684 if (ret)
685 goto err_unref;
686
0d1aacac
CW		 687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
689 if (ring->scratch.cpu_page == NULL) {
56b085a0 690 ret = -ENOMEM;
c6df541c 691 goto err_unpin;
56b085a0 692 }
c6df541c 693
2b1086cc 694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 695 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 696 return 0;
697
698err_unpin:
d7f46fc4 699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 700err_unref:
0d1aacac 701 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 702err:
c6df541c
CW		 703 return ret;
704}
705
771b9a53
MT		 706static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
86d7f238 708{
7225342a 709 int ret, i;
888b5995
AS		 710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 712 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 713
e6c1abb7 714 if (WARN_ON_ONCE(w->count == 0))
7225342a 715 return 0;
888b5995 716
7225342a
MK		 717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
719 if (ret)
720 return ret;
888b5995 721
22a916aa 722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 723 if (ret)
724 return ret;
725
22a916aa 726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 727 for (i = 0; i < w->count; i++) {
7225342a
MK		 728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
730 }
22a916aa 731 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 732
733 intel_ring_advance(ring);
734
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
737 if (ret)
738 return ret;
888b5995 739
7225342a 740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 741
7225342a 742 return 0;
86d7f238
AS		 743}
744
8f0e2b9d
DV		 745static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
747{
748 int ret;
749
750 ret = intel_ring_workarounds_emit(ring, ctx);
751 if (ret != 0)
752 return ret;
753
754 ret = i915_gem_render_state_init(ring);
755 if (ret)
756 DRM_ERROR("init render state: %d\n", ret);
757
758 return ret;
759}
760
7225342a 761static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 762 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 763{
764 const u32 idx = dev_priv->workarounds.count;
765
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
767 return -ENOSPC;
768
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
772
773 dev_priv->workarounds.count++;
774
775 return 0;
86d7f238
AS		 776}
777
cf4b0de6
DL		 778#define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 780 if (r) \
781 return r; \
782 }
783
784#define WA_SET_BIT_MASKED(addr, mask) \
26459343 785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 786
787#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 789
98533251 790#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 792
cf4b0de6
DL		 793#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 795
cf4b0de6 796#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 797
00e1e623 798static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 799{
888b5995
AS		 800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 802
86d7f238 803 /* WaDisablePartialInstShootdown:bdw */
101b376d 804 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 805 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
806 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
807 STALL_DOP_GATING_DISABLE);
86d7f238 808
101b376d 809 /* WaDisableDopClockGating:bdw */
7225342a
MK		 810 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
811 DOP_CLOCK_GATING_DISABLE);
86d7f238 812
7225342a
MK		 813 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
814 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 815
816 /* Use Force Non-Coherent whenever executing a 3D context. This is a
817 * workaround for for a possible hang in the unlikely event a TLB
818 * invalidation occurs during a PSD flush.
819 */
7225342a 820 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 821 /* WaForceEnableNonCoherent:bdw */
7225342a 822 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 823 /* WaForceContextSaveRestoreNonCoherent:bdw */
824 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
825 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 826 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 827 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 828 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 829
2701fc43
KG		 830 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
831 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
832 * polygons in the same 8x4 pixel/sample area to be processed without
833 * stalling waiting for the earlier ones to write to Hierarchical Z
834 * buffer."
835 *
836 * This optimization is off by default for Broadwell; turn it on.
837 */
838 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
839
86d7f238 840 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 841 WA_SET_BIT_MASKED(CACHE_MODE_1,
842 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 843
844 /*
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
847 *
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
851 */
98533251
DL		 852 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
853 GEN6_WIZ_HASHING_MASK,
854 GEN6_WIZ_HASHING_16x4);
888b5995 855
86d7f238
AS		 856 return 0;
857}
858
00e1e623
VS		 859static int chv_init_workarounds(struct intel_engine_cs *ring)
860{
00e1e623
VS		 861 struct drm_device *dev = ring->dev;
862 struct drm_i915_private *dev_priv = dev->dev_private;
863
00e1e623 864 /* WaDisablePartialInstShootdown:chv */
00e1e623 865 /* WaDisableThreadStallDopClockGating:chv */
7225342a 866 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 867 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
868 STALL_DOP_GATING_DISABLE);
00e1e623 869
95289009
AS		 870 /* Use Force Non-Coherent whenever executing a 3D context. This is a
871 * workaround for a possible hang in the unlikely event a TLB
872 * invalidation occurs during a PSD flush.
873 */
874 /* WaForceEnableNonCoherent:chv */
875 /* WaHdcDisableFetchWhenMasked:chv */
876 WA_SET_BIT_MASKED(HDC_CHICKEN0,
877 HDC_FORCE_NON_COHERENT |
878 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
879
973a5b06
KG		 880 /* According to the CACHE_MODE_0 default value documentation, some
881 * CHV platforms disable this optimization by default. Turn it on.
882 */
883 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
884
14bc16e3
VS		 885 /* Wa4x4STCOptimizationDisable:chv */
886 WA_SET_BIT_MASKED(CACHE_MODE_1,
887 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
888
d60de81d
KG		 889 /* Improve HiZ throughput on CHV. */
890 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
891
e7fc2436
VS		 892 /*
893 * BSpec recommends 8x4 when MSAA is used,
894 * however in practice 16x4 seems fastest.
895 *
896 * Note that PS/WM thread counts depend on the WIZ hashing
897 * disable bit, which we don't touch here, but it's good
898 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
899 */
900 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
901 GEN6_WIZ_HASHING_MASK,
902 GEN6_WIZ_HASHING_16x4);
903
65ca7514
DL		 904 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
905 INTEL_REVID(dev) == SKL_REVID_D0)
906 /* WaBarrierPerformanceFixDisable:skl */
907 WA_SET_BIT_MASKED(HDC_CHICKEN0,
908 HDC_FENCE_DEST_SLM_DISABLE |
909 HDC_BARRIER_PERFORMANCE_DISABLE);
910
7225342a
MK		 911 return 0;
912}
913
3b106531
HN		 914static int gen9_init_workarounds(struct intel_engine_cs *ring)
915{
ab0dfafe
HN		 916 struct drm_device *dev = ring->dev;
917 struct drm_i915_private *dev_priv = dev->dev_private;
918
919 /* WaDisablePartialInstShootdown:skl */
920 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
921 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
922
8424171e
NH		 923 /* Syncing dependencies between camera and graphics */
924 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
925 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
926
35c8ce6a
DL		 927 if (INTEL_REVID(dev) == SKL_REVID_A0 ||
928 INTEL_REVID(dev) == SKL_REVID_B0) {
a86eb582
DL		 929 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
930 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
931 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 932 }
933
183c6dac
DL		 934 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
935 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
936 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
937 GEN9_RHWO_OPTIMIZATION_DISABLE);
938 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
939 DISABLE_PIXEL_MASK_CAMMING);
940 }
941
cac23df4
NH		 942 if (INTEL_REVID(dev) >= SKL_REVID_C0) {
943 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
944 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
945 GEN9_ENABLE_YV12_BUGFIX);
946 }
947
13bea49c
HN		 948 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
949 /*
950 *Use Force Non-Coherent whenever executing a 3D context. This
951 * is a workaround for a possible hang in the unlikely event
952 * a TLB invalidation occurs during a PSD flush.
953 */
954 /* WaForceEnableNonCoherent:skl */
955 WA_SET_BIT_MASKED(HDC_CHICKEN0,
956 HDC_FORCE_NON_COHERENT);
957 }
958
1840481f
HN		 959 /* Wa4x4STCOptimizationDisable:skl */
960 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
961
9370cd98
DL		 962 /* WaDisablePartialResolveInVc:skl */
963 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
964
e2db7071
DL		 965 /* WaCcsTlbPrefetchDisable:skl */
966 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
967 GEN9_CCS_TLB_PREFETCH_ENABLE);
968
3b106531
HN		 969 return 0;
970}
971
b7668791
DL		 972static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
973{
974 struct drm_device *dev = ring->dev;
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u8 vals[3] = { 0, 0, 0 };
977 unsigned int i;
978
979 for (i = 0; i < 3; i++) {
980 u8 ss;
981
982 /*
983 * Only consider slices where one, and only one, subslice has 7
984 * EUs
985 */
986 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
987 continue;
988
989 /*
990 * subslice_7eu[i] != 0 (because of the check above) and
991 * ss_max == 4 (maximum number of subslices possible per slice)
992 *
993 * -> 0 <= ss <= 3;
994 */
995 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
996 vals[i] = 3 - ss;
997 }
998
999 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1000 return 0;
1001
1002 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1003 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1004 GEN9_IZ_HASHING_MASK(2) |
1005 GEN9_IZ_HASHING_MASK(1) |
1006 GEN9_IZ_HASHING_MASK(0),
1007 GEN9_IZ_HASHING(2, vals[2]) |
1008 GEN9_IZ_HASHING(1, vals[1]) |
1009 GEN9_IZ_HASHING(0, vals[0]));
1010
1011 return 0;
1012}
1013
1014
8d205494
DL		 1015static int skl_init_workarounds(struct intel_engine_cs *ring)
1016{
d0bbbc4f
DL		 1017 struct drm_device *dev = ring->dev;
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019
8d205494
DL		 1020 gen9_init_workarounds(ring);
1021
d0bbbc4f
DL		 1022 /* WaDisablePowerCompilerClockGating:skl */
1023 if (INTEL_REVID(dev) == SKL_REVID_B0)
1024 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1025 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1026
b7668791 1027 return skl_tune_iz_hashing(ring);
7225342a
MK		 1028}
1029
771b9a53 1030int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1031{
1032 struct drm_device *dev = ring->dev;
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034
1035 WARN_ON(ring->id != RCS);
1036
1037 dev_priv->workarounds.count = 0;
1038
1039 if (IS_BROADWELL(dev))
1040 return bdw_init_workarounds(ring);
1041
1042 if (IS_CHERRYVIEW(dev))
1043 return chv_init_workarounds(ring);
00e1e623 1044
8d205494
DL		 1045 if (IS_SKYLAKE(dev))
1046 return skl_init_workarounds(ring);
1047 else if (IS_GEN9(dev))
3b106531
HN		 1048 return gen9_init_workarounds(ring);
1049
00e1e623
VS		 1050 return 0;
1051}
1052
a4872ba6 1053static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1054{
78501eac 1055 struct drm_device *dev = ring->dev;
1ec14ad3 1056 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1057 int ret = init_ring_common(ring);
9c33baa6
KZ		 1058 if (ret)
1059 return ret;
a69ffdbf 1060
61a563a2
AG		 1061 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1062 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1063 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1064
1065 /* We need to disable the AsyncFlip performance optimisations in order
1066 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1067 * programmed to '1' on all products.
8693a824 1068 *
b3f797ac 1069 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 1070 */
fbdcb068 1071 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 1072 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1073
f05bb0c7 1074 /* Required for the hardware to program scanline values for waiting */
01fa0302 1075 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1076 if (INTEL_INFO(dev)->gen == 6)
1077 I915_WRITE(GFX_MODE,
aa83e30d 1078 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1079
01fa0302 1080 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1081 if (IS_GEN7(dev))
1082 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1083 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1084 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1085
5e13a0c5 1086 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1087 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1088 * "If this bit is set, STCunit will have LRA as replacement
1089 * policy. [...] This bit must be reset. LRA replacement
1090 * policy is not supported."
1091 */
1092 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1093 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1094 }
1095
6b26c86d
DV		 1096 if (INTEL_INFO(dev)->gen >= 6)
1097 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1098
040d2baa 1099 if (HAS_L3_DPF(dev))
35a85ac6 1100 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1101
7225342a 1102 return init_workarounds_ring(ring);
8187a2b7
ZN		 1103}
1104
a4872ba6 1105static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1106{
b45305fc 1107 struct drm_device *dev = ring->dev;
3e78998a
BW		 1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109
1110 if (dev_priv->semaphore_obj) {
1111 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1112 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1113 dev_priv->semaphore_obj = NULL;
1114 }
b45305fc 1115
9b1136d5 1116 intel_fini_pipe_control(ring);
c6df541c
CW		 1117}
1118
3e78998a
BW		 1119static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1120 unsigned int num_dwords)
1121{
1122#define MBOX_UPDATE_DWORDS 8
1123 struct drm_device *dev = signaller->dev;
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125 struct intel_engine_cs *waiter;
1126 int i, ret, num_rings;
1127
1128 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1129 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1130#undef MBOX_UPDATE_DWORDS
1131
1132 ret = intel_ring_begin(signaller, num_dwords);
1133 if (ret)
1134 return ret;
1135
1136 for_each_ring(waiter, dev_priv, i) {
6259cead 1137 u32 seqno;
3e78998a
BW		 1138 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1139 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1140 continue;
1141
6259cead
JH		 1142 seqno = i915_gem_request_get_seqno(
1143 signaller->outstanding_lazy_request);
3e78998a
BW		 1144 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1145 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1146 PIPE_CONTROL_QW_WRITE |
1147 PIPE_CONTROL_FLUSH_ENABLE);
1148 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1149 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1150 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1151 intel_ring_emit(signaller, 0);
1152 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1153 MI_SEMAPHORE_TARGET(waiter->id));
1154 intel_ring_emit(signaller, 0);
1155 }
1156
1157 return 0;
1158}
1159
1160static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1161 unsigned int num_dwords)
1162{
1163#define MBOX_UPDATE_DWORDS 6
1164 struct drm_device *dev = signaller->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 struct intel_engine_cs *waiter;
1167 int i, ret, num_rings;
1168
1169 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1170 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1171#undef MBOX_UPDATE_DWORDS
1172
1173 ret = intel_ring_begin(signaller, num_dwords);
1174 if (ret)
1175 return ret;
1176
1177 for_each_ring(waiter, dev_priv, i) {
6259cead 1178 u32 seqno;
3e78998a
BW		 1179 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1180 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1181 continue;
1182
6259cead
JH		 1183 seqno = i915_gem_request_get_seqno(
1184 signaller->outstanding_lazy_request);
3e78998a
BW		 1185 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1186 MI_FLUSH_DW_OP_STOREDW);
1187 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1188 MI_FLUSH_DW_USE_GTT);
1189 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1190 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1191 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1192 MI_SEMAPHORE_TARGET(waiter->id));
1193 intel_ring_emit(signaller, 0);
1194 }
1195
1196 return 0;
1197}
1198
a4872ba6 1199static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1200 unsigned int num_dwords)
1ec14ad3 1201{
024a43e1
BW		 1202 struct drm_device *dev = signaller->dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1204 struct intel_engine_cs *useless;
a1444b79 1205 int i, ret, num_rings;
78325f2d 1206
a1444b79
BW		 1207#define MBOX_UPDATE_DWORDS 3
1208 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1209 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1210#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1211
1212 ret = intel_ring_begin(signaller, num_dwords);
1213 if (ret)
1214 return ret;
024a43e1 1215
78325f2d
BW		 1216 for_each_ring(useless, dev_priv, i) {
1217 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1218 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1219 u32 seqno = i915_gem_request_get_seqno(
1220 signaller->outstanding_lazy_request);
78325f2d
BW		 1221 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1222 intel_ring_emit(signaller, mbox_reg);
6259cead 1223 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1224 }
1225 }
024a43e1 1226
a1444b79
BW		 1227 /* If num_dwords was rounded, make sure the tail pointer is correct */
1228 if (num_rings % 2 == 0)
1229 intel_ring_emit(signaller, MI_NOOP);
1230
024a43e1 1231 return 0;
1ec14ad3
CW		 1232}
1233
c8c99b0f
BW		 1234/**
1235 * gen6_add_request - Update the semaphore mailbox registers
1236 *
1237 * @ring - ring that is adding a request
1238 * @seqno - return seqno stuck into the ring
1239 *
1240 * Update the mailbox registers in the *other* rings with the current seqno.
1241 * This acts like a signal in the canonical semaphore.
1242 */
1ec14ad3 1243static int
a4872ba6 1244gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1245{
024a43e1 1246 int ret;
52ed2325 1247
707d9cf9
BW		 1248 if (ring->semaphore.signal)
1249 ret = ring->semaphore.signal(ring, 4);
1250 else
1251 ret = intel_ring_begin(ring, 4);
1252
1ec14ad3
CW		 1253 if (ret)
1254 return ret;
1255
1ec14ad3
CW		 1256 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1257 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1258 intel_ring_emit(ring,
1259 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1260 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1261 __intel_ring_advance(ring);
1ec14ad3 1262
1ec14ad3
CW		 1263 return 0;
1264}
1265
f72b3435
MK		 1266static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1267 u32 seqno)
1268{
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 return dev_priv->last_seqno < seqno;
1271}
1272
c8c99b0f
BW		 1273/**
1274 * intel_ring_sync - sync the waiter to the signaller on seqno
1275 *
1276 * @waiter - ring that is waiting
1277 * @signaller - ring which has, or will signal
1278 * @seqno - seqno which the waiter will block on
1279 */
5ee426ca
BW		 1280
1281static int
1282gen8_ring_sync(struct intel_engine_cs *waiter,
1283 struct intel_engine_cs *signaller,
1284 u32 seqno)
1285{
1286 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1287 int ret;
1288
1289 ret = intel_ring_begin(waiter, 4);
1290 if (ret)
1291 return ret;
1292
1293 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1294 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1295 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1296 MI_SEMAPHORE_SAD_GTE_SDD);
1297 intel_ring_emit(waiter, seqno);
1298 intel_ring_emit(waiter,
1299 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1300 intel_ring_emit(waiter,
1301 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1302 intel_ring_advance(waiter);
1303 return 0;
1304}
1305
c8c99b0f 1306static int
a4872ba6
OM		 1307gen6_ring_sync(struct intel_engine_cs *waiter,
1308 struct intel_engine_cs *signaller,
686cb5f9 1309 u32 seqno)
1ec14ad3 1310{
c8c99b0f
BW		 1311 u32 dw1 = MI_SEMAPHORE_MBOX |
1312 MI_SEMAPHORE_COMPARE |
1313 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1314 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1315 int ret;
1ec14ad3 1316
1500f7ea
BW		 1317 /* Throughout all of the GEM code, seqno passed implies our current
1318 * seqno is >= the last seqno executed. However for hardware the
1319 * comparison is strictly greater than.
1320 */
1321 seqno -= 1;
1322
ebc348b2 1323 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1324
c8c99b0f 1325 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1326 if (ret)
1327 return ret;
1328
f72b3435
MK		 1329 /* If seqno wrap happened, omit the wait with no-ops */
1330 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1331 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1332 intel_ring_emit(waiter, seqno);
1333 intel_ring_emit(waiter, 0);
1334 intel_ring_emit(waiter, MI_NOOP);
1335 } else {
1336 intel_ring_emit(waiter, MI_NOOP);
1337 intel_ring_emit(waiter, MI_NOOP);
1338 intel_ring_emit(waiter, MI_NOOP);
1339 intel_ring_emit(waiter, MI_NOOP);
1340 }
c8c99b0f 1341 intel_ring_advance(waiter);
1ec14ad3
CW		 1342
1343 return 0;
1344}
1345
c6df541c
CW		 1346#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1347do { \
fcbc34e4
KG		 1348 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1349 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1350 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1351 intel_ring_emit(ring__, 0); \
1352 intel_ring_emit(ring__, 0); \
1353} while (0)
1354
1355static int
a4872ba6 1356pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1357{
18393f63 1358 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1359 int ret;
1360
1361 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1362 * incoherent with writes to memory, i.e. completely fubar,
1363 * so we need to use PIPE_NOTIFY instead.
1364 *
1365 * However, we also need to workaround the qword write
1366 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1367 * memory before requesting an interrupt.
1368 */
1369 ret = intel_ring_begin(ring, 32);
1370 if (ret)
1371 return ret;
1372
fcbc34e4 1373 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1374 PIPE_CONTROL_WRITE_FLUSH |
1375 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1376 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1377 intel_ring_emit(ring,
1378 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1379 intel_ring_emit(ring, 0);
1380 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1381 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1382 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1383 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1384 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1385 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1386 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1387 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1388 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1389 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1390 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1391
fcbc34e4 1392 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1393 PIPE_CONTROL_WRITE_FLUSH |
1394 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1395 PIPE_CONTROL_NOTIFY);
0d1aacac 1396 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1397 intel_ring_emit(ring,
1398 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1399 intel_ring_emit(ring, 0);
09246732 1400 __intel_ring_advance(ring);
c6df541c 1401
c6df541c
CW		 1402 return 0;
1403}
1404
4cd53c0c 1405static u32
a4872ba6 1406gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1407{
4cd53c0c
DV		 1408 /* Workaround to force correct ordering between irq and seqno writes on
1409 * ivb (and maybe also on snb) by reading from a CS register (like
1410 * ACTHD) before reading the status page. */
50877445
CW		 1411 if (!lazy_coherency) {
1412 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1413 POSTING_READ(RING_ACTHD(ring->mmio_base));
1414 }
1415
4cd53c0c
DV		 1416 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1417}
1418
8187a2b7 1419static u32
a4872ba6 1420ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1421{
1ec14ad3
CW		 1422 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1423}
1424
b70ec5bf 1425static void
a4872ba6 1426ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1427{
1428 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1429}
1430
c6df541c 1431static u32
a4872ba6 1432pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1433{
0d1aacac 1434 return ring->scratch.cpu_page[0];
c6df541c
CW		 1435}
1436
b70ec5bf 1437static void
a4872ba6 1438pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1439{
0d1aacac 1440 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1441}
1442
e48d8634 1443static bool
a4872ba6 1444gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1445{
1446 struct drm_device *dev = ring->dev;
4640c4ff 1447 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1448 unsigned long flags;
e48d8634 1449
7cd512f1 1450 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1451 return false;
1452
7338aefa 1453 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1454 if (ring->irq_refcount++ == 0)
480c8033 1455 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1456 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1457
1458 return true;
1459}
1460
1461static void
a4872ba6 1462gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1463{
1464 struct drm_device *dev = ring->dev;
4640c4ff 1465 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1466 unsigned long flags;
e48d8634 1467
7338aefa 1468 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1469 if (--ring->irq_refcount == 0)
480c8033 1470 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1471 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1472}
1473
b13c2b96 1474static bool
a4872ba6 1475i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1476{
78501eac 1477 struct drm_device *dev = ring->dev;
4640c4ff 1478 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1479 unsigned long flags;
62fdfeaf 1480
7cd512f1 1481 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1482 return false;
1483
7338aefa 1484 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1485 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1486 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1487 I915_WRITE(IMR, dev_priv->irq_mask);
1488 POSTING_READ(IMR);
1489 }
7338aefa 1490 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1491
1492 return true;
62fdfeaf
EA		 1493}
1494
8187a2b7 1495static void
a4872ba6 1496i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1497{
78501eac 1498 struct drm_device *dev = ring->dev;
4640c4ff 1499 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1500 unsigned long flags;
62fdfeaf 1501
7338aefa 1502 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1503 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1504 dev_priv->irq_mask |= ring->irq_enable_mask;
1505 I915_WRITE(IMR, dev_priv->irq_mask);
1506 POSTING_READ(IMR);
1507 }
7338aefa 1508 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1509}
1510
c2798b19 1511static bool
a4872ba6 1512i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1513{
1514 struct drm_device *dev = ring->dev;
4640c4ff 1515 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1516 unsigned long flags;
c2798b19 1517
7cd512f1 1518 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1519 return false;
1520
7338aefa 1521 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1522 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1523 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1524 I915_WRITE16(IMR, dev_priv->irq_mask);
1525 POSTING_READ16(IMR);
1526 }
7338aefa 1527 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1528
1529 return true;
1530}
1531
1532static void
a4872ba6 1533i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1534{
1535 struct drm_device *dev = ring->dev;
4640c4ff 1536 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1537 unsigned long flags;
c2798b19 1538
7338aefa 1539 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1540 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1541 dev_priv->irq_mask |= ring->irq_enable_mask;
1542 I915_WRITE16(IMR, dev_priv->irq_mask);
1543 POSTING_READ16(IMR);
1544 }
7338aefa 1545 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1546}
1547
b72f3acb 1548static int
a4872ba6 1549bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1550 u32 invalidate_domains,
1551 u32 flush_domains)
d1b851fc 1552{
b72f3acb
CW		 1553 int ret;
1554
b72f3acb
CW		 1555 ret = intel_ring_begin(ring, 2);
1556 if (ret)
1557 return ret;
1558
1559 intel_ring_emit(ring, MI_FLUSH);
1560 intel_ring_emit(ring, MI_NOOP);
1561 intel_ring_advance(ring);
1562 return 0;
d1b851fc
ZN		 1563}
1564
3cce469c 1565static int
a4872ba6 1566i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1567{
3cce469c
CW		 1568 int ret;
1569
1570 ret = intel_ring_begin(ring, 4);
1571 if (ret)
1572 return ret;
6f392d54 1573
3cce469c
CW		 1574 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1575 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1576 intel_ring_emit(ring,
1577 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1578 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1579 __intel_ring_advance(ring);
d1b851fc 1580
3cce469c 1581 return 0;
d1b851fc
ZN		 1582}
1583
0f46832f 1584static bool
a4872ba6 1585gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1586{
1587 struct drm_device *dev = ring->dev;
4640c4ff 1588 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1589 unsigned long flags;
0f46832f 1590
7cd512f1
DV		 1591 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1592 return false;
0f46832f 1593
7338aefa 1594 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1595 if (ring->irq_refcount++ == 0) {
040d2baa 1596 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1597 I915_WRITE_IMR(ring,
1598 ~(ring->irq_enable_mask |
35a85ac6 1599 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1600 else
1601 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1602 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1603 }
7338aefa 1604 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1605
1606 return true;
1607}
1608
1609static void
a4872ba6 1610gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1611{
1612 struct drm_device *dev = ring->dev;
4640c4ff 1613 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1614 unsigned long flags;
0f46832f 1615
7338aefa 1616 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1617 if (--ring->irq_refcount == 0) {
040d2baa 1618 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1619 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1620 else
1621 I915_WRITE_IMR(ring, ~0);
480c8033 1622 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1623 }
7338aefa 1624 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1625}
1626
a19d2933 1627static bool
a4872ba6 1628hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1629{
1630 struct drm_device *dev = ring->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 unsigned long flags;
1633
7cd512f1 1634 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1635 return false;
1636
59cdb63d 1637 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1638 if (ring->irq_refcount++ == 0) {
a19d2933 1639 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1640 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1641 }
59cdb63d 1642 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1643
1644 return true;
1645}
1646
1647static void
a4872ba6 1648hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1649{
1650 struct drm_device *dev = ring->dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 unsigned long flags;
1653
59cdb63d 1654 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1655 if (--ring->irq_refcount == 0) {
a19d2933 1656 I915_WRITE_IMR(ring, ~0);
480c8033 1657 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1658 }
59cdb63d 1659 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1660}
1661
abd58f01 1662static bool
a4872ba6 1663gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1664{
1665 struct drm_device *dev = ring->dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 unsigned long flags;
1668
7cd512f1 1669 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1670 return false;
1671
1672 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1673 if (ring->irq_refcount++ == 0) {
1674 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1675 I915_WRITE_IMR(ring,
1676 ~(ring->irq_enable_mask |
1677 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1678 } else {
1679 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1680 }
1681 POSTING_READ(RING_IMR(ring->mmio_base));
1682 }
1683 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1684
1685 return true;
1686}
1687
1688static void
a4872ba6 1689gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1690{
1691 struct drm_device *dev = ring->dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 unsigned long flags;
1694
1695 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1696 if (--ring->irq_refcount == 0) {
1697 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1698 I915_WRITE_IMR(ring,
1699 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1700 } else {
1701 I915_WRITE_IMR(ring, ~0);
1702 }
1703 POSTING_READ(RING_IMR(ring->mmio_base));
1704 }
1705 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1706}
1707
d1b851fc 1708static int
a4872ba6 1709i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1710 u64 offset, u32 length,
8e004efc 1711 unsigned dispatch_flags)
d1b851fc 1712{
e1f99ce6 1713 int ret;
78501eac 1714
e1f99ce6
CW		 1715 ret = intel_ring_begin(ring, 2);
1716 if (ret)
1717 return ret;
1718
78501eac 1719 intel_ring_emit(ring,
65f56876
CW		 1720 MI_BATCH_BUFFER_START |
1721 MI_BATCH_GTT |
8e004efc
JH		 1722 (dispatch_flags & I915_DISPATCH_SECURE ?
1723 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1724 intel_ring_emit(ring, offset);
78501eac
CW		 1725 intel_ring_advance(ring);
1726
d1b851fc
ZN		 1727 return 0;
1728}
1729
b45305fc
DV		 1730/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1731#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1732#define I830_TLB_ENTRIES (2)
1733#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1734static int
a4872ba6 1735i830_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 1736 u64 offset, u32 len,
1737 unsigned dispatch_flags)
62fdfeaf 1738{
c4d69da1 1739 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1740 int ret;
62fdfeaf 1741
c4d69da1
CW		 1742 ret = intel_ring_begin(ring, 6);
1743 if (ret)
1744 return ret;
62fdfeaf 1745
c4d69da1
CW		 1746 /* Evict the invalid PTE TLBs */
1747 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1748 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1749 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1750 intel_ring_emit(ring, cs_offset);
1751 intel_ring_emit(ring, 0xdeadbeef);
1752 intel_ring_emit(ring, MI_NOOP);
1753 intel_ring_advance(ring);
b45305fc 1754
8e004efc 1755 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1756 if (len > I830_BATCH_LIMIT)
1757 return -ENOSPC;
1758
c4d69da1 1759 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1760 if (ret)
1761 return ret;
c4d69da1
CW		 1762
1763 /* Blit the batch (which has now all relocs applied) to the
1764 * stable batch scratch bo area (so that the CS never
1765 * stumbles over its tlb invalidation bug) ...
1766 */
1767 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1768 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1769 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1770 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1771 intel_ring_emit(ring, 4096);
1772 intel_ring_emit(ring, offset);
c4d69da1 1773
b45305fc 1774 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1775 intel_ring_emit(ring, MI_NOOP);
1776 intel_ring_advance(ring);
b45305fc
DV		 1777
1778 /* ... and execute it. */
c4d69da1 1779 offset = cs_offset;
b45305fc 1780 }
e1f99ce6 1781
c4d69da1
CW		 1782 ret = intel_ring_begin(ring, 4);
1783 if (ret)
1784 return ret;
1785
1786 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1787 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1788 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1789 intel_ring_emit(ring, offset + len - 8);
1790 intel_ring_emit(ring, MI_NOOP);
1791 intel_ring_advance(ring);
1792
fb3256da
DV		 1793 return 0;
1794}
1795
1796static int
a4872ba6 1797i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1798 u64 offset, u32 len,
8e004efc 1799 unsigned dispatch_flags)
fb3256da
DV		 1800{
1801 int ret;
1802
1803 ret = intel_ring_begin(ring, 2);
1804 if (ret)
1805 return ret;
1806
65f56876 1807 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1808 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1809 0 : MI_BATCH_NON_SECURE));
c4e7a414 1810 intel_ring_advance(ring);
62fdfeaf 1811
62fdfeaf
EA		 1812 return 0;
1813}
1814
a4872ba6 1815static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1816{
05394f39 1817 struct drm_i915_gem_object *obj;
62fdfeaf 1818
8187a2b7
ZN		 1819 obj = ring->status_page.obj;
1820 if (obj == NULL)
62fdfeaf 1821 return;
62fdfeaf 1822
9da3da66 1823 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1824 i915_gem_object_ggtt_unpin(obj);
05394f39 1825 drm_gem_object_unreference(&obj->base);
8187a2b7 1826 ring->status_page.obj = NULL;
62fdfeaf
EA		 1827}
1828
a4872ba6 1829static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1830{
05394f39 1831 struct drm_i915_gem_object *obj;
62fdfeaf 1832
e3efda49 1833 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1834 unsigned flags;
e3efda49 1835 int ret;
e4ffd173 1836
e3efda49
CW		 1837 obj = i915_gem_alloc_object(ring->dev, 4096);
1838 if (obj == NULL) {
1839 DRM_ERROR("Failed to allocate status page\n");
1840 return -ENOMEM;
1841 }
62fdfeaf 1842
e3efda49
CW		 1843 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1844 if (ret)
1845 goto err_unref;
1846
1f767e02
CW		 1847 flags = 0;
1848 if (!HAS_LLC(ring->dev))
1849 /* On g33, we cannot place HWS above 256MiB, so
1850 * restrict its pinning to the low mappable arena.
1851 * Though this restriction is not documented for
1852 * gen4, gen5, or byt, they also behave similarly
1853 * and hang if the HWS is placed at the top of the
1854 * GTT. To generalise, it appears that all !llc
1855 * platforms have issues with us placing the HWS
1856 * above the mappable region (even though we never
1857 * actualy map it).
1858 */
1859 flags |= PIN_MAPPABLE;
1860 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1861 if (ret) {
1862err_unref:
1863 drm_gem_object_unreference(&obj->base);
1864 return ret;
1865 }
1866
1867 ring->status_page.obj = obj;
1868 }
62fdfeaf 1869
f343c5f6 1870 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1871 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1872 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1873
8187a2b7
ZN		 1874 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1875 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1876
1877 return 0;
62fdfeaf
EA		 1878}
1879
a4872ba6 1880static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1881{
1882 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1883
1884 if (!dev_priv->status_page_dmah) {
1885 dev_priv->status_page_dmah =
1886 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1887 if (!dev_priv->status_page_dmah)
1888 return -ENOMEM;
1889 }
1890
6b8294a4
CW		 1891 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1892 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1893
1894 return 0;
1895}
1896
7ba717cf 1897void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1898{
2919d291 1899 iounmap(ringbuf->virtual_start);
7ba717cf 1900 ringbuf->virtual_start = NULL;
2919d291 1901 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1902}
1903
1904int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1905 struct intel_ringbuffer *ringbuf)
1906{
1907 struct drm_i915_private *dev_priv = to_i915(dev);
1908 struct drm_i915_gem_object *obj = ringbuf->obj;
1909 int ret;
1910
1911 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1912 if (ret)
1913 return ret;
1914
1915 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1916 if (ret) {
1917 i915_gem_object_ggtt_unpin(obj);
1918 return ret;
1919 }
1920
1921 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1922 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1923 if (ringbuf->virtual_start == NULL) {
1924 i915_gem_object_ggtt_unpin(obj);
1925 return -EINVAL;
1926 }
1927
1928 return 0;
1929}
1930
1931void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1932{
2919d291
OM		 1933 drm_gem_object_unreference(&ringbuf->obj->base);
1934 ringbuf->obj = NULL;
1935}
1936
84c2377f
OM		 1937int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1938 struct intel_ringbuffer *ringbuf)
62fdfeaf 1939{
05394f39 1940 struct drm_i915_gem_object *obj;
62fdfeaf 1941
ebc052e0
CW		 1942 obj = NULL;
1943 if (!HAS_LLC(dev))
93b0a4e0 1944 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1945 if (obj == NULL)
93b0a4e0 1946 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1947 if (obj == NULL)
1948 return -ENOMEM;
8187a2b7 1949
24f3a8cf
AG		 1950 /* mark ring buffers as read-only from GPU side by default */
1951 obj->gt_ro = 1;
1952
93b0a4e0 1953 ringbuf->obj = obj;
e3efda49 1954
7ba717cf 1955 return 0;
e3efda49
CW		 1956}
1957
1958static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1959 struct intel_engine_cs *ring)
e3efda49 1960{
bfc882b4 1961 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1962 int ret;
1963
bfc882b4
DV		 1964 WARN_ON(ring->buffer);
1965
1966 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1967 if (!ringbuf)
1968 return -ENOMEM;
1969 ring->buffer = ringbuf;
8ee14975 1970
e3efda49
CW		 1971 ring->dev = dev;
1972 INIT_LIST_HEAD(&ring->active_list);
1973 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1974 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1975 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1976 ringbuf->ring = ring;
ebc348b2 1977 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1978
1979 init_waitqueue_head(&ring->irq_queue);
1980
1981 if (I915_NEED_GFX_HWS(dev)) {
1982 ret = init_status_page(ring);
1983 if (ret)
8ee14975 1984 goto error;
e3efda49
CW		 1985 } else {
1986 BUG_ON(ring->id != RCS);
1987 ret = init_phys_status_page(ring);
1988 if (ret)
8ee14975 1989 goto error;
e3efda49
CW		 1990 }
1991
bfc882b4 1992 WARN_ON(ringbuf->obj);
7ba717cf 1993
bfc882b4
DV		 1994 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1995 if (ret) {
1996 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1997 ring->name, ret);
1998 goto error;
1999 }
2000
2001 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2002 if (ret) {
2003 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2004 ring->name, ret);
2005 intel_destroy_ringbuffer_obj(ringbuf);
2006 goto error;
e3efda49 2007 }
62fdfeaf 2008
55249baa
CW		 2009 /* Workaround an erratum on the i830 which causes a hang if
2010 * the TAIL pointer points to within the last 2 cachelines
2011 * of the buffer.
2012 */
93b0a4e0 2013 ringbuf->effective_size = ringbuf->size;
e3efda49 2014 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2015 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2016
44e895a8
BV		 2017 ret = i915_cmd_parser_init_ring(ring);
2018 if (ret)
8ee14975
OM		 2019 goto error;
2020
8ee14975 2021 return 0;
351e3db2 2022
8ee14975
OM		 2023error:
2024 kfree(ringbuf);
2025 ring->buffer = NULL;
2026 return ret;
62fdfeaf
EA		 2027}
2028
a4872ba6 2029void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2030{
6402c330
JH		 2031 struct drm_i915_private *dev_priv;
2032 struct intel_ringbuffer *ringbuf;
33626e6a 2033
93b0a4e0 2034 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2035 return;
2036
6402c330
JH		 2037 dev_priv = to_i915(ring->dev);
2038 ringbuf = ring->buffer;
2039
e3efda49 2040 intel_stop_ring_buffer(ring);
de8f0a50 2041 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2042
7ba717cf 2043 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2044 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2045 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2046
8d19215b
ZN		 2047 if (ring->cleanup)
2048 ring->cleanup(ring);
2049
78501eac 2050 cleanup_status_page(ring);
44e895a8
BV		 2051
2052 i915_cmd_parser_fini_ring(ring);
8ee14975 2053
93b0a4e0 2054 kfree(ringbuf);
8ee14975 2055 ring->buffer = NULL;
62fdfeaf
EA		 2056}
2057
a4872ba6 2058static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 2059{
93b0a4e0 2060 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2061 struct drm_i915_gem_request *request;
a71d8d94
CW		 2062 int ret;
2063
ebd0fd4b
DG		 2064 if (intel_ring_space(ringbuf) >= n)
2065 return 0;
a71d8d94
CW		 2066
2067 list_for_each_entry(request, &ring->request_list, list) {
72f95afa 2068 if (__intel_ring_space(request->postfix, ringbuf->tail,
82e104cc 2069 ringbuf->size) >= n) {
a71d8d94
CW		 2070 break;
2071 }
a71d8d94
CW		 2072 }
2073
a4b3a571 2074 if (&request->list == &ring->request_list)
a71d8d94
CW		 2075 return -ENOSPC;
2076
a4b3a571 2077 ret = i915_wait_request(request);
a71d8d94
CW		 2078 if (ret)
2079 return ret;
2080
1cf0ba14 2081 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 2082
2083 return 0;
2084}
2085
a4872ba6 2086static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 2087{
78501eac 2088 struct drm_device *dev = ring->dev;
cae5852d 2089 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 2090 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 2091 unsigned long end;
a71d8d94 2092 int ret;
c7dca47b 2093
a71d8d94
CW		 2094 ret = intel_ring_wait_request(ring, n);
2095 if (ret != -ENOSPC)
2096 return ret;
2097
09246732
CW		 2098 /* force the tail write in case we have been skipping them */
2099 __intel_ring_advance(ring);
2100
63ed2cb2
DV		 2101 /* With GEM the hangcheck timer should kick us out of the loop,
2102 * leaving it early runs the risk of corrupting GEM state (due
2103 * to running on almost untested codepaths). But on resume
2104 * timers don't work yet, so prevent a complete hang in that
2105 * case by choosing an insanely large timeout. */
2106 end = jiffies + 60 * HZ;
e6bfaf85 2107
ebd0fd4b 2108 ret = 0;
dcfe0506 2109 trace_i915_ring_wait_begin(ring);
8187a2b7 2110 do {
ebd0fd4b
DG		 2111 if (intel_ring_space(ringbuf) >= n)
2112 break;
93b0a4e0 2113 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 2114 if (intel_ring_space(ringbuf) >= n)
dcfe0506 2115 break;
62fdfeaf 2116
e60a0b10 2117 msleep(1);
d6b2c790 2118
dcfe0506
CW		 2119 if (dev_priv->mm.interruptible && signal_pending(current)) {
2120 ret = -ERESTARTSYS;
2121 break;
2122 }
2123
33196ded
DV		 2124 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2125 dev_priv->mm.interruptible);
d6b2c790 2126 if (ret)
dcfe0506
CW		 2127 break;
2128
2129 if (time_after(jiffies, end)) {
2130 ret = -EBUSY;
2131 break;
2132 }
2133 } while (1);
db53a302 2134 trace_i915_ring_wait_end(ring);
dcfe0506 2135 return ret;
8187a2b7 2136}
62fdfeaf 2137
a4872ba6 2138static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2139{
2140 uint32_t __iomem *virt;
93b0a4e0
OM		 2141 struct intel_ringbuffer *ringbuf = ring->buffer;
2142 int rem = ringbuf->size - ringbuf->tail;
3e960501 2143
93b0a4e0 2144 if (ringbuf->space < rem) {
3e960501
CW		 2145 int ret = ring_wait_for_space(ring, rem);
2146 if (ret)
2147 return ret;
2148 }
2149
93b0a4e0 2150 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2151 rem /= 4;
2152 while (rem--)
2153 iowrite32(MI_NOOP, virt++);
2154
93b0a4e0 2155 ringbuf->tail = 0;
ebd0fd4b 2156 intel_ring_update_space(ringbuf);
3e960501
CW		 2157
2158 return 0;
2159}
2160
a4872ba6 2161int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2162{
a4b3a571 2163 struct drm_i915_gem_request *req;
3e960501
CW		 2164 int ret;
2165
2166 /* We need to add any requests required to flush the objects and ring */
6259cead 2167 if (ring->outstanding_lazy_request) {
9400ae5c 2168 ret = i915_add_request(ring);
3e960501
CW		 2169 if (ret)
2170 return ret;
2171 }
2172
2173 /* Wait upon the last request to be completed */
2174 if (list_empty(&ring->request_list))
2175 return 0;
2176
a4b3a571 2177 req = list_entry(ring->request_list.prev,
3e960501 2178 struct drm_i915_gem_request,
a4b3a571 2179 list);
3e960501 2180
a4b3a571 2181 return i915_wait_request(req);
3e960501
CW		 2182}
2183
9d773091 2184static int
6259cead 2185intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2186{
9eba5d4a
JH		 2187 int ret;
2188 struct drm_i915_gem_request *request;
67e2937b 2189 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2190
6259cead 2191 if (ring->outstanding_lazy_request)
9d773091 2192 return 0;
3c0e234c 2193
aaeb1ba0 2194 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2195 if (request == NULL)
2196 return -ENOMEM;
3c0e234c 2197
abfe262a 2198 kref_init(&request->ref);
ff79e857 2199 request->ring = ring;
98e1bd4a 2200 request->ringbuf = ring->buffer;
67e2937b 2201 request->uniq = dev_private->request_uniq++;
abfe262a 2202
6259cead 2203 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2204 if (ret) {
2205 kfree(request);
2206 return ret;
3c0e234c
CW		 2207 }
2208
6259cead 2209 ring->outstanding_lazy_request = request;
9eba5d4a 2210 return 0;
9d773091
CW		 2211}
2212
a4872ba6 2213static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2214 int bytes)
cbcc80df 2215{
93b0a4e0 2216 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2217 int ret;
2218
93b0a4e0 2219 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2220 ret = intel_wrap_ring_buffer(ring);
2221 if (unlikely(ret))
2222 return ret;
2223 }
2224
93b0a4e0 2225 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2226 ret = ring_wait_for_space(ring, bytes);
2227 if (unlikely(ret))
2228 return ret;
2229 }
2230
cbcc80df
MK		 2231 return 0;
2232}
2233
a4872ba6 2234int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2235 int num_dwords)
8187a2b7 2236{
4640c4ff 2237 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2238 int ret;
78501eac 2239
33196ded
DV		 2240 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2241 dev_priv->mm.interruptible);
de2b9985
DV		 2242 if (ret)
2243 return ret;
21dd3734 2244
304d695c
CW		 2245 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2246 if (ret)
2247 return ret;
2248
9d773091 2249 /* Preallocate the olr before touching the ring */
6259cead 2250 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2251 if (ret)
2252 return ret;
2253
ee1b1e5e 2254 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2255 return 0;
8187a2b7 2256}
78501eac 2257
753b1ad4 2258/* Align the ring tail to a cacheline boundary */
a4872ba6 2259int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2260{
ee1b1e5e 2261 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2262 int ret;
2263
2264 if (num_dwords == 0)
2265 return 0;
2266
18393f63 2267 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2268 ret = intel_ring_begin(ring, num_dwords);
2269 if (ret)
2270 return ret;
2271
2272 while (num_dwords--)
2273 intel_ring_emit(ring, MI_NOOP);
2274
2275 intel_ring_advance(ring);
2276
2277 return 0;
2278}
2279
a4872ba6 2280void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2281{
3b2cc8ab
OM		 2282 struct drm_device *dev = ring->dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2284
6259cead 2285 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2286
3b2cc8ab 2287 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2288 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2289 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2290 if (HAS_VEBOX(dev))
5020150b 2291 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2292 }
d97ed339 2293
f7e98ad4 2294 ring->set_seqno(ring, seqno);
92cab734 2295 ring->hangcheck.seqno = seqno;
8187a2b7 2296}
62fdfeaf 2297
a4872ba6 2298static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2299 u32 value)
881f47b6 2300{
4640c4ff 2301 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2302
2303 /* Every tail move must follow the sequence below */
12f55818
CW		 2304
2305 /* Disable notification that the ring is IDLE. The GT
2306 * will then assume that it is busy and bring it out of rc6.
2307 */
0206e353 2308 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2309 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2310
2311 /* Clear the context id. Here be magic! */
2312 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2313
12f55818 2314 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2315 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2316 GEN6_BSD_SLEEP_INDICATOR) == 0,
2317 50))
2318 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2319
12f55818 2320 /* Now that the ring is fully powered up, update the tail */
0206e353 2321 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2322 POSTING_READ(RING_TAIL(ring->mmio_base));
2323
2324 /* Let the ring send IDLE messages to the GT again,
2325 * and so let it sleep to conserve power when idle.
2326 */
0206e353 2327 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2328 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2329}
2330
a4872ba6 2331static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2332 u32 invalidate, u32 flush)
881f47b6 2333{
71a77e07 2334 uint32_t cmd;
b72f3acb
CW		 2335 int ret;
2336
b72f3acb
CW		 2337 ret = intel_ring_begin(ring, 4);
2338 if (ret)
2339 return ret;
2340
71a77e07 2341 cmd = MI_FLUSH_DW;
075b3bba
BW		 2342 if (INTEL_INFO(ring->dev)->gen >= 8)
2343 cmd += 1;
f0a1fb10
CW		 2344
2345 /* We always require a command barrier so that subsequent
2346 * commands, such as breadcrumb interrupts, are strictly ordered
2347 * wrt the contents of the write cache being flushed to memory
2348 * (and thus being coherent from the CPU).
2349 */
2350 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2351
9a289771
JB		 2352 /*
2353 * Bspec vol 1c.5 - video engine command streamer:
2354 * "If ENABLED, all TLBs will be invalidated once the flush
2355 * operation is complete. This bit is only valid when the
2356 * Post-Sync Operation field is a value of 1h or 3h."
2357 */
71a77e07 2358 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2359 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2360
71a77e07 2361 intel_ring_emit(ring, cmd);
9a289771 2362 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2363 if (INTEL_INFO(ring->dev)->gen >= 8) {
2364 intel_ring_emit(ring, 0); /* upper addr */
2365 intel_ring_emit(ring, 0); /* value */
2366 } else {
2367 intel_ring_emit(ring, 0);
2368 intel_ring_emit(ring, MI_NOOP);
2369 }
b72f3acb
CW		 2370 intel_ring_advance(ring);
2371 return 0;
881f47b6
XH		 2372}
2373
1c7a0623 2374static int
a4872ba6 2375gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2376 u64 offset, u32 len,
8e004efc 2377 unsigned dispatch_flags)
1c7a0623 2378{
8e004efc
JH		 2379 bool ppgtt = USES_PPGTT(ring->dev) &&
2380 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2381 int ret;
2382
2383 ret = intel_ring_begin(ring, 4);
2384 if (ret)
2385 return ret;
2386
2387 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2388 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2389 intel_ring_emit(ring, lower_32_bits(offset));
2390 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2391 intel_ring_emit(ring, MI_NOOP);
2392 intel_ring_advance(ring);
2393
2394 return 0;
2395}
2396
d7d4eedd 2397static int
a4872ba6 2398hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 2399 u64 offset, u32 len,
2400 unsigned dispatch_flags)
d7d4eedd
CW		 2401{
2402 int ret;
2403
2404 ret = intel_ring_begin(ring, 2);
2405 if (ret)
2406 return ret;
2407
2408 intel_ring_emit(ring,
77072258 2409 MI_BATCH_BUFFER_START |
8e004efc 2410 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2411 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2412 /* bit0-7 is the length on GEN6+ */
2413 intel_ring_emit(ring, offset);
2414 intel_ring_advance(ring);
2415
2416 return 0;
2417}
2418
881f47b6 2419static int
a4872ba6 2420gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2421 u64 offset, u32 len,
8e004efc 2422 unsigned dispatch_flags)
881f47b6 2423{
0206e353 2424 int ret;
ab6f8e32 2425
0206e353
AJ		 2426 ret = intel_ring_begin(ring, 2);
2427 if (ret)
2428 return ret;
e1f99ce6 2429
d7d4eedd
CW		 2430 intel_ring_emit(ring,
2431 MI_BATCH_BUFFER_START |
8e004efc
JH		 2432 (dispatch_flags & I915_DISPATCH_SECURE ?
2433 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2434 /* bit0-7 is the length on GEN6+ */
2435 intel_ring_emit(ring, offset);
2436 intel_ring_advance(ring);
ab6f8e32 2437
0206e353 2438 return 0;
881f47b6
XH		 2439}
2440
549f7365
CW		 2441/* Blitter support (SandyBridge+) */
2442
a4872ba6 2443static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2444 u32 invalidate, u32 flush)
8d19215b 2445{
fd3da6c9 2446 struct drm_device *dev = ring->dev;
71a77e07 2447 uint32_t cmd;
b72f3acb
CW		 2448 int ret;
2449
6a233c78 2450 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2451 if (ret)
2452 return ret;
2453
71a77e07 2454 cmd = MI_FLUSH_DW;
dbef0f15 2455 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2456 cmd += 1;
f0a1fb10
CW		 2457
2458 /* We always require a command barrier so that subsequent
2459 * commands, such as breadcrumb interrupts, are strictly ordered
2460 * wrt the contents of the write cache being flushed to memory
2461 * (and thus being coherent from the CPU).
2462 */
2463 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2464
9a289771
JB		 2465 /*
2466 * Bspec vol 1c.3 - blitter engine command streamer:
2467 * "If ENABLED, all TLBs will be invalidated once the flush
2468 * operation is complete. This bit is only valid when the
2469 * Post-Sync Operation field is a value of 1h or 3h."
2470 */
71a77e07 2471 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2472 cmd |= MI_INVALIDATE_TLB;
71a77e07 2473 intel_ring_emit(ring, cmd);
9a289771 2474 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2475 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2476 intel_ring_emit(ring, 0); /* upper addr */
2477 intel_ring_emit(ring, 0); /* value */
2478 } else {
2479 intel_ring_emit(ring, 0);
2480 intel_ring_emit(ring, MI_NOOP);
2481 }
b72f3acb 2482 intel_ring_advance(ring);
fd3da6c9 2483
b72f3acb 2484 return 0;
8d19215b
ZN		 2485}
2486
5c1143bb
XH		 2487int intel_init_render_ring_buffer(struct drm_device *dev)
2488{
4640c4ff 2489 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2490 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2491 struct drm_i915_gem_object *obj;
2492 int ret;
5c1143bb 2493
59465b5f
DV		 2494 ring->name = "render ring";
2495 ring->id = RCS;
2496 ring->mmio_base = RENDER_RING_BASE;
2497
707d9cf9 2498 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2499 if (i915_semaphore_is_enabled(dev)) {
2500 obj = i915_gem_alloc_object(dev, 4096);
2501 if (obj == NULL) {
2502 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2503 i915.semaphores = 0;
2504 } else {
2505 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2506 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2507 if (ret != 0) {
2508 drm_gem_object_unreference(&obj->base);
2509 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2510 i915.semaphores = 0;
2511 } else
2512 dev_priv->semaphore_obj = obj;
2513 }
2514 }
7225342a 2515
8f0e2b9d 2516 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2517 ring->add_request = gen6_add_request;
2518 ring->flush = gen8_render_ring_flush;
2519 ring->irq_get = gen8_ring_get_irq;
2520 ring->irq_put = gen8_ring_put_irq;
2521 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2522 ring->get_seqno = gen6_ring_get_seqno;
2523 ring->set_seqno = ring_set_seqno;
2524 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2525 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2526 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2527 ring->semaphore.signal = gen8_rcs_signal;
2528 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2529 }
2530 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2531 ring->add_request = gen6_add_request;
4772eaeb 2532 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2533 if (INTEL_INFO(dev)->gen == 6)
b3111509 2534 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2535 ring->irq_get = gen6_ring_get_irq;
2536 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2537 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2538 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2539 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2540 if (i915_semaphore_is_enabled(dev)) {
2541 ring->semaphore.sync_to = gen6_ring_sync;
2542 ring->semaphore.signal = gen6_signal;
2543 /*
2544 * The current semaphore is only applied on pre-gen8
2545 * platform. And there is no VCS2 ring on the pre-gen8
2546 * platform. So the semaphore between RCS and VCS2 is
2547 * initialized as INVALID. Gen8 will initialize the
2548 * sema between VCS2 and RCS later.
2549 */
2550 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2551 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2552 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2553 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2554 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2555 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2556 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2557 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2558 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2559 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2560 }
c6df541c
CW		 2561 } else if (IS_GEN5(dev)) {
2562 ring->add_request = pc_render_add_request;
46f0f8d1 2563 ring->flush = gen4_render_ring_flush;
c6df541c 2564 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2565 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2566 ring->irq_get = gen5_ring_get_irq;
2567 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2568 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2569 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2570 } else {
8620a3a9 2571 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2572 if (INTEL_INFO(dev)->gen < 4)
2573 ring->flush = gen2_render_ring_flush;
2574 else
2575 ring->flush = gen4_render_ring_flush;
59465b5f 2576 ring->get_seqno = ring_get_seqno;
b70ec5bf 2577 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2578 if (IS_GEN2(dev)) {
2579 ring->irq_get = i8xx_ring_get_irq;
2580 ring->irq_put = i8xx_ring_put_irq;
2581 } else {
2582 ring->irq_get = i9xx_ring_get_irq;
2583 ring->irq_put = i9xx_ring_put_irq;
2584 }
e3670319 2585 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2586 }
59465b5f 2587 ring->write_tail = ring_write_tail;
707d9cf9 2588
d7d4eedd
CW		 2589 if (IS_HASWELL(dev))
2590 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2591 else if (IS_GEN8(dev))
2592 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2593 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2594 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2595 else if (INTEL_INFO(dev)->gen >= 4)
2596 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2597 else if (IS_I830(dev) || IS_845G(dev))
2598 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2599 else
2600 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2601 ring->init_hw = init_render_ring;
59465b5f
DV		 2602 ring->cleanup = render_ring_cleanup;
2603
b45305fc
DV		 2604 /* Workaround batchbuffer to combat CS tlb bug. */
2605 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2606 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2607 if (obj == NULL) {
2608 DRM_ERROR("Failed to allocate batch bo\n");
2609 return -ENOMEM;
2610 }
2611
be1fa129 2612 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2613 if (ret != 0) {
2614 drm_gem_object_unreference(&obj->base);
2615 DRM_ERROR("Failed to ping batch bo\n");
2616 return ret;
2617 }
2618
0d1aacac
CW		 2619 ring->scratch.obj = obj;
2620 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2621 }
2622
99be1dfe
DV		 2623 ret = intel_init_ring_buffer(dev, ring);
2624 if (ret)
2625 return ret;
2626
2627 if (INTEL_INFO(dev)->gen >= 5) {
2628 ret = intel_init_pipe_control(ring);
2629 if (ret)
2630 return ret;
2631 }
2632
2633 return 0;
5c1143bb
XH		 2634}
2635
2636int intel_init_bsd_ring_buffer(struct drm_device *dev)
2637{
4640c4ff 2638 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2639 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2640
58fa3835
DV		 2641 ring->name = "bsd ring";
2642 ring->id = VCS;
2643
0fd2c201 2644 ring->write_tail = ring_write_tail;
780f18c8 2645 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2646 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2647 /* gen6 bsd needs a special wa for tail updates */
2648 if (IS_GEN6(dev))
2649 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2650 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2651 ring->add_request = gen6_add_request;
2652 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2653 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2654 if (INTEL_INFO(dev)->gen >= 8) {
2655 ring->irq_enable_mask =
2656 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2657 ring->irq_get = gen8_ring_get_irq;
2658 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2659 ring->dispatch_execbuffer =
2660 gen8_ring_dispatch_execbuffer;
707d9cf9 2661 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2662 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2663 ring->semaphore.signal = gen8_xcs_signal;
2664 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2665 }
abd58f01
BW		 2666 } else {
2667 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2668 ring->irq_get = gen6_ring_get_irq;
2669 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2670 ring->dispatch_execbuffer =
2671 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2672 if (i915_semaphore_is_enabled(dev)) {
2673 ring->semaphore.sync_to = gen6_ring_sync;
2674 ring->semaphore.signal = gen6_signal;
2675 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2676 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2677 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2678 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2679 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2680 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2681 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2682 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2683 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2684 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2685 }
abd58f01 2686 }
58fa3835
DV		 2687 } else {
2688 ring->mmio_base = BSD_RING_BASE;
58fa3835 2689 ring->flush = bsd_ring_flush;
8620a3a9 2690 ring->add_request = i9xx_add_request;
58fa3835 2691 ring->get_seqno = ring_get_seqno;
b70ec5bf 2692 ring->set_seqno = ring_set_seqno;
e48d8634 2693 if (IS_GEN5(dev)) {
cc609d5d 2694 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2695 ring->irq_get = gen5_ring_get_irq;
2696 ring->irq_put = gen5_ring_put_irq;
2697 } else {
e3670319 2698 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2699 ring->irq_get = i9xx_ring_get_irq;
2700 ring->irq_put = i9xx_ring_put_irq;
2701 }
fb3256da 2702 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2703 }
ecfe00d8 2704 ring->init_hw = init_ring_common;
58fa3835 2705
1ec14ad3 2706 return intel_init_ring_buffer(dev, ring);
5c1143bb 2707}
549f7365 2708
845f74a7 2709/**
62659920 2710 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2711 */
2712int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2713{
2714 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2715 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2716
f7b64236 2717 ring->name = "bsd2 ring";
845f74a7
ZY		 2718 ring->id = VCS2;
2719
2720 ring->write_tail = ring_write_tail;
2721 ring->mmio_base = GEN8_BSD2_RING_BASE;
2722 ring->flush = gen6_bsd_ring_flush;
2723 ring->add_request = gen6_add_request;
2724 ring->get_seqno = gen6_ring_get_seqno;
2725 ring->set_seqno = ring_set_seqno;
2726 ring->irq_enable_mask =
2727 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2728 ring->irq_get = gen8_ring_get_irq;
2729 ring->irq_put = gen8_ring_put_irq;
2730 ring->dispatch_execbuffer =
2731 gen8_ring_dispatch_execbuffer;
3e78998a 2732 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2733 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2734 ring->semaphore.signal = gen8_xcs_signal;
2735 GEN8_RING_SEMAPHORE_INIT;
2736 }
ecfe00d8 2737 ring->init_hw = init_ring_common;
845f74a7
ZY		 2738
2739 return intel_init_ring_buffer(dev, ring);
2740}
2741
549f7365
CW		 2742int intel_init_blt_ring_buffer(struct drm_device *dev)
2743{
4640c4ff 2744 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2745 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2746
3535d9dd
DV		 2747 ring->name = "blitter ring";
2748 ring->id = BCS;
2749
2750 ring->mmio_base = BLT_RING_BASE;
2751 ring->write_tail = ring_write_tail;
ea251324 2752 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2753 ring->add_request = gen6_add_request;
2754 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2755 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2756 if (INTEL_INFO(dev)->gen >= 8) {
2757 ring->irq_enable_mask =
2758 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2759 ring->irq_get = gen8_ring_get_irq;
2760 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2761 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2762 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2763 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2764 ring->semaphore.signal = gen8_xcs_signal;
2765 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2766 }
abd58f01
BW		 2767 } else {
2768 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2769 ring->irq_get = gen6_ring_get_irq;
2770 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2771 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2772 if (i915_semaphore_is_enabled(dev)) {
2773 ring->semaphore.signal = gen6_signal;
2774 ring->semaphore.sync_to = gen6_ring_sync;
2775 /*
2776 * The current semaphore is only applied on pre-gen8
2777 * platform. And there is no VCS2 ring on the pre-gen8
2778 * platform. So the semaphore between BCS and VCS2 is
2779 * initialized as INVALID. Gen8 will initialize the
2780 * sema between BCS and VCS2 later.
2781 */
2782 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2783 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2784 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2785 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2786 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2787 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2788 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2789 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2790 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2791 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2792 }
abd58f01 2793 }
ecfe00d8 2794 ring->init_hw = init_ring_common;
549f7365 2795
1ec14ad3 2796 return intel_init_ring_buffer(dev, ring);
549f7365 2797}
a7b9761d 2798
9a8a2213
BW		 2799int intel_init_vebox_ring_buffer(struct drm_device *dev)
2800{
4640c4ff 2801 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2802 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2803
2804 ring->name = "video enhancement ring";
2805 ring->id = VECS;
2806
2807 ring->mmio_base = VEBOX_RING_BASE;
2808 ring->write_tail = ring_write_tail;
2809 ring->flush = gen6_ring_flush;
2810 ring->add_request = gen6_add_request;
2811 ring->get_seqno = gen6_ring_get_seqno;
2812 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2813
2814 if (INTEL_INFO(dev)->gen >= 8) {
2815 ring->irq_enable_mask =
40c499f9 2816 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2817 ring->irq_get = gen8_ring_get_irq;
2818 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2819 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2820 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2821 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2822 ring->semaphore.signal = gen8_xcs_signal;
2823 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2824 }
abd58f01
BW		 2825 } else {
2826 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2827 ring->irq_get = hsw_vebox_get_irq;
2828 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2829 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2830 if (i915_semaphore_is_enabled(dev)) {
2831 ring->semaphore.sync_to = gen6_ring_sync;
2832 ring->semaphore.signal = gen6_signal;
2833 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2834 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2835 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2836 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2837 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2838 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2839 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2840 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2841 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2842 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2843 }
abd58f01 2844 }
ecfe00d8 2845 ring->init_hw = init_ring_common;
9a8a2213
BW		 2846
2847 return intel_init_ring_buffer(dev, ring);
2848}
2849
a7b9761d 2850int
a4872ba6 2851intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2852{
2853 int ret;
2854
2855 if (!ring->gpu_caches_dirty)
2856 return 0;
2857
2858 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2859 if (ret)
2860 return ret;
2861
2862 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2863
2864 ring->gpu_caches_dirty = false;
2865 return 0;
2866}
2867
2868int
a4872ba6 2869intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2870{
2871 uint32_t flush_domains;
2872 int ret;
2873
2874 flush_domains = 0;
2875 if (ring->gpu_caches_dirty)
2876 flush_domains = I915_GEM_GPU_DOMAINS;
2877
2878 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2879 if (ret)
2880 return ret;
2881
2882 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2883
2884 ring->gpu_caches_dirty = false;
2885 return 0;
2886}
e3efda49
CW		 2887
2888void
a4872ba6 2889intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2890{
2891 int ret;
2892
2893 if (!intel_ring_initialized(ring))
2894 return;
2895
2896 ret = intel_ring_idle(ring);
2897 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2898 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2899 ring->name, ret);
2900
2901 stop_ring(ring);
2902}
Linux kernel - Deliverables
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