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drm/i915: only disable memory self-refresh on GMCH
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
a4d8a0fe 30#include <linux/log2.h>
760285e7 31#include <drm/drmP.h>
62fdfeaf 32#include "i915_drv.h"
760285e7 33#include <drm/i915_drm.h>
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
a0442461
CW		 37/* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
39 */
40#define LEGACY_REQUEST_SIZE 200
41
82e104cc 42int __intel_ring_space(int head, int tail, int size)
c7dca47b 43{
4f54741e
DG		 44 int space = head - tail;
45 if (space <= 0)
1cf0ba14 46 space += size;
4f54741e 47 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 48}
49
ebd0fd4b
DG		 50void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
51{
52 if (ringbuf->last_retired_head != -1) {
53 ringbuf->head = ringbuf->last_retired_head;
54 ringbuf->last_retired_head = -1;
55 }
56
57 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
58 ringbuf->tail, ringbuf->size);
59}
60
117897f4 61bool intel_engine_stopped(struct intel_engine_cs *engine)
09246732 62{
c033666a 63 struct drm_i915_private *dev_priv = engine->i915;
666796da 64 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
88b4aa87 65}
09246732 66
0bc40be8 67static void __intel_ring_advance(struct intel_engine_cs *engine)
88b4aa87 68{
0bc40be8 69 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 70 ringbuf->tail &= ringbuf->size - 1;
117897f4 71 if (intel_engine_stopped(engine))
09246732 72 return;
0bc40be8 73 engine->write_tail(engine, ringbuf->tail);
09246732
CW		 74}
75
b72f3acb 76static int
a84c3ae1 77gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 78 u32 invalidate_domains,
79 u32 flush_domains)
80{
4a570db5 81 struct intel_engine_cs *engine = req->engine;
46f0f8d1
CW		 82 u32 cmd;
83 int ret;
84
85 cmd = MI_FLUSH;
31b14c9f 86 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 87 cmd |= MI_NO_WRITE_FLUSH;
88
89 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
90 cmd |= MI_READ_FLUSH;
91
5fb9de1a 92 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 93 if (ret)
94 return ret;
95
e2f80391
TU		 96 intel_ring_emit(engine, cmd);
97 intel_ring_emit(engine, MI_NOOP);
98 intel_ring_advance(engine);
46f0f8d1
CW		 99
100 return 0;
101}
102
103static int
a84c3ae1 104gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 105 u32 invalidate_domains,
106 u32 flush_domains)
62fdfeaf 107{
4a570db5 108 struct intel_engine_cs *engine = req->engine;
6f392d54 109 u32 cmd;
b72f3acb 110 int ret;
6f392d54 111
36d527de
CW		 112 /*
113 * read/write caches:
114 *
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
118 *
119 * read-only caches:
120 *
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
123 *
124 * I915_GEM_DOMAIN_COMMAND may not exist?
125 *
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
128 *
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
131 *
132 * TLBs:
133 *
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
138 */
139
140 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 141 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 142 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 143 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
144 cmd |= MI_EXE_FLUSH;
62fdfeaf 145
36d527de 146 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
c033666a 147 (IS_G4X(req->i915) || IS_GEN5(req->i915)))
36d527de 148 cmd |= MI_INVALIDATE_ISP;
70eac33e 149
5fb9de1a 150 ret = intel_ring_begin(req, 2);
36d527de
CW		 151 if (ret)
152 return ret;
b72f3acb 153
e2f80391
TU		 154 intel_ring_emit(engine, cmd);
155 intel_ring_emit(engine, MI_NOOP);
156 intel_ring_advance(engine);
b72f3acb
CW		 157
158 return 0;
8187a2b7
ZN		 159}
160
8d315287
JB		 161/**
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
165 *
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
169 * 0.
170 *
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
173 *
174 * And the workaround for these two requires this workaround first:
175 *
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
178 * flushes.
179 *
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
182 * volume 2 part 1:
183 *
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
191 *
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
197 */
198static int
f2cf1fcc 199intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 200{
4a570db5 201 struct intel_engine_cs *engine = req->engine;
e2f80391 202 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 203 int ret;
204
5fb9de1a 205 ret = intel_ring_begin(req, 6);
8d315287
JB		 206 if (ret)
207 return ret;
208
e2f80391
TU		 209 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
8d315287 211 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 212 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(engine, 0); /* low dword */
214 intel_ring_emit(engine, 0); /* high dword */
215 intel_ring_emit(engine, MI_NOOP);
216 intel_ring_advance(engine);
8d315287 217
5fb9de1a 218 ret = intel_ring_begin(req, 6);
8d315287
JB		 219 if (ret)
220 return ret;
221
e2f80391
TU		 222 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
224 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
225 intel_ring_emit(engine, 0);
226 intel_ring_emit(engine, 0);
227 intel_ring_emit(engine, MI_NOOP);
228 intel_ring_advance(engine);
8d315287
JB		 229
230 return 0;
231}
232
233static int
a84c3ae1
JH		 234gen6_render_ring_flush(struct drm_i915_gem_request *req,
235 u32 invalidate_domains, u32 flush_domains)
8d315287 236{
4a570db5 237 struct intel_engine_cs *engine = req->engine;
8d315287 238 u32 flags = 0;
e2f80391 239 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 240 int ret;
241
b3111509 242 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 243 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 244 if (ret)
245 return ret;
246
8d315287
JB		 247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
249 * impact.
250 */
7d54a904
CW		 251 if (flush_domains) {
252 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
253 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
254 /*
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
257 */
97f209bc 258 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 259 }
260 if (invalidate_domains) {
261 flags |= PIPE_CONTROL_TLB_INVALIDATE;
262 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
263 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
264 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
267 /*
268 * TLB invalidate requires a post-sync write.
269 */
3ac78313 270 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 271 }
8d315287 272
5fb9de1a 273 ret = intel_ring_begin(req, 4);
8d315287
JB		 274 if (ret)
275 return ret;
276
e2f80391
TU		 277 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine, flags);
279 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
280 intel_ring_emit(engine, 0);
281 intel_ring_advance(engine);
8d315287
JB		 282
283 return 0;
284}
285
f3987631 286static int
f2cf1fcc 287gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 288{
4a570db5 289 struct intel_engine_cs *engine = req->engine;
f3987631
PZ		 290 int ret;
291
5fb9de1a 292 ret = intel_ring_begin(req, 4);
f3987631
PZ		 293 if (ret)
294 return ret;
295
e2f80391
TU		 296 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
f3987631 298 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 299 intel_ring_emit(engine, 0);
300 intel_ring_emit(engine, 0);
301 intel_ring_advance(engine);
f3987631
PZ		 302
303 return 0;
304}
305
4772eaeb 306static int
a84c3ae1 307gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 308 u32 invalidate_domains, u32 flush_domains)
309{
4a570db5 310 struct intel_engine_cs *engine = req->engine;
4772eaeb 311 u32 flags = 0;
e2f80391 312 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 313 int ret;
314
f3987631
PZ		 315 /*
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
318 *
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
322 */
323 flags |= PIPE_CONTROL_CS_STALL;
324
4772eaeb
PZ		 325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
327 * impact.
328 */
329 if (flush_domains) {
330 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
331 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 332 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 333 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4772eaeb
PZ		 334 }
335 if (invalidate_domains) {
336 flags |= PIPE_CONTROL_TLB_INVALIDATE;
337 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
338 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
339 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 342 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 343 /*
344 * TLB invalidate requires a post-sync write.
345 */
346 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 347 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 348
add284a3
CW		 349 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
350
f3987631
PZ		 351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
f2cf1fcc 354 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 355 }
356
5fb9de1a 357 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 358 if (ret)
359 return ret;
360
e2f80391
TU		 361 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine, flags);
363 intel_ring_emit(engine, scratch_addr);
364 intel_ring_emit(engine, 0);
365 intel_ring_advance(engine);
4772eaeb
PZ		 366
367 return 0;
368}
369
884ceace 370static int
f2cf1fcc 371gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 372 u32 flags, u32 scratch_addr)
373{
4a570db5 374 struct intel_engine_cs *engine = req->engine;
884ceace
KG		 375 int ret;
376
5fb9de1a 377 ret = intel_ring_begin(req, 6);
884ceace
KG		 378 if (ret)
379 return ret;
380
e2f80391
TU		 381 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine, flags);
383 intel_ring_emit(engine, scratch_addr);
384 intel_ring_emit(engine, 0);
385 intel_ring_emit(engine, 0);
386 intel_ring_emit(engine, 0);
387 intel_ring_advance(engine);
884ceace
KG		 388
389 return 0;
390}
391
a5f3d68e 392static int
a84c3ae1 393gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 394 u32 invalidate_domains, u32 flush_domains)
395{
396 u32 flags = 0;
4a570db5 397 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 398 int ret;
a5f3d68e
BW		 399
400 flags |= PIPE_CONTROL_CS_STALL;
401
402 if (flush_domains) {
403 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
404 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 405 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 406 flags |= PIPE_CONTROL_FLUSH_ENABLE;
a5f3d68e
BW		 407 }
408 if (invalidate_domains) {
409 flags |= PIPE_CONTROL_TLB_INVALIDATE;
410 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
412 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_QW_WRITE;
416 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 417
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 419 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 420 PIPE_CONTROL_CS_STALL |
421 PIPE_CONTROL_STALL_AT_SCOREBOARD,
422 0);
423 if (ret)
424 return ret;
a5f3d68e
BW		 425 }
426
f2cf1fcc 427 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 428}
429
0bc40be8 430static void ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 431 u32 value)
d46eefa2 432{
c033666a 433 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 434 I915_WRITE_TAIL(engine, value);
d46eefa2
XH		 435}
436
0bc40be8 437u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
8187a2b7 438{
c033666a 439 struct drm_i915_private *dev_priv = engine->i915;
50877445 440 u64 acthd;
8187a2b7 441
c033666a 442 if (INTEL_GEN(dev_priv) >= 8)
0bc40be8
TU		 443 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
444 RING_ACTHD_UDW(engine->mmio_base));
c033666a 445 else if (INTEL_GEN(dev_priv) >= 4)
0bc40be8 446 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
50877445
CW		 447 else
448 acthd = I915_READ(ACTHD);
449
450 return acthd;
8187a2b7
ZN		 451}
452
0bc40be8 453static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
035dc1e0 454{
c033666a 455 struct drm_i915_private *dev_priv = engine->i915;
035dc1e0
DV		 456 u32 addr;
457
458 addr = dev_priv->status_page_dmah->busaddr;
c033666a 459 if (INTEL_GEN(dev_priv) >= 4)
035dc1e0
DV		 460 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
461 I915_WRITE(HWS_PGA, addr);
462}
463
0bc40be8 464static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
af75f269 465{
c033666a 466 struct drm_i915_private *dev_priv = engine->i915;
f0f59a00 467 i915_reg_t mmio;
af75f269
DL		 468
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
471 */
c033666a 472 if (IS_GEN7(dev_priv)) {
0bc40be8 473 switch (engine->id) {
af75f269
DL		 474 case RCS:
475 mmio = RENDER_HWS_PGA_GEN7;
476 break;
477 case BCS:
478 mmio = BLT_HWS_PGA_GEN7;
479 break;
480 /*
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
483 */
484 case VCS2:
485 case VCS:
486 mmio = BSD_HWS_PGA_GEN7;
487 break;
488 case VECS:
489 mmio = VEBOX_HWS_PGA_GEN7;
490 break;
491 }
c033666a 492 } else if (IS_GEN6(dev_priv)) {
0bc40be8 493 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
af75f269
DL		 494 } else {
495 /* XXX: gen8 returns to sanity */
0bc40be8 496 mmio = RING_HWS_PGA(engine->mmio_base);
af75f269
DL		 497 }
498
0bc40be8 499 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
af75f269
DL		 500 POSTING_READ(mmio);
501
502 /*
503 * Flush the TLB for this page
504 *
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
508 */
ac657f64 509 if (IS_GEN(dev_priv, 6, 7)) {
0bc40be8 510 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
af75f269
DL		 511
512 /* ring should be idle before issuing a sync flush*/
0bc40be8 513 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
af75f269
DL		 514
515 I915_WRITE(reg,
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
517 INSTPM_SYNC_FLUSH));
518 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
519 1000))
520 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
0bc40be8 521 engine->name);
af75f269
DL		 522 }
523}
524
0bc40be8 525static bool stop_ring(struct intel_engine_cs *engine)
8187a2b7 526{
c033666a 527 struct drm_i915_private *dev_priv = engine->i915;
8187a2b7 528
c033666a 529 if (!IS_GEN2(dev_priv)) {
0bc40be8
TU		 530 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
531 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
532 DRM_ERROR("%s : timed out trying to stop ring\n",
533 engine->name);
9bec9b13
CW		 534 /* Sometimes we observe that the idle flag is not
535 * set even though the ring is empty. So double
536 * check before giving up.
537 */
0bc40be8 538 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
9bec9b13 539 return false;
9991ae78
CW		 540 }
541 }
b7884eb4 542
0bc40be8
TU		 543 I915_WRITE_CTL(engine, 0);
544 I915_WRITE_HEAD(engine, 0);
545 engine->write_tail(engine, 0);
8187a2b7 546
c033666a 547 if (!IS_GEN2(dev_priv)) {
0bc40be8
TU		 548 (void)I915_READ_CTL(engine);
549 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
9991ae78 550 }
a51435a3 551
0bc40be8 552 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
9991ae78 553}
8187a2b7 554
fc0768ce
TE		 555void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
556{
557 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
558}
559
0bc40be8 560static int init_ring_common(struct intel_engine_cs *engine)
9991ae78 561{
c033666a 562 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 563 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 564 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 565 int ret = 0;
566
59bad947 567 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78 568
0bc40be8 569 if (!stop_ring(engine)) {
9991ae78 570 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 571 DRM_DEBUG_KMS("%s head not reset to zero "
572 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 573 engine->name,
574 I915_READ_CTL(engine),
575 I915_READ_HEAD(engine),
576 I915_READ_TAIL(engine),
577 I915_READ_START(engine));
8187a2b7 578
0bc40be8 579 if (!stop_ring(engine)) {
6fd0d56e
CW		 580 DRM_ERROR("failed to set %s head to zero "
581 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 582 engine->name,
583 I915_READ_CTL(engine),
584 I915_READ_HEAD(engine),
585 I915_READ_TAIL(engine),
586 I915_READ_START(engine));
9991ae78
CW		 587 ret = -EIO;
588 goto out;
6fd0d56e 589 }
8187a2b7
ZN		 590 }
591
c033666a 592 if (I915_NEED_GFX_HWS(dev_priv))
0bc40be8 593 intel_ring_setup_status_page(engine);
9991ae78 594 else
0bc40be8 595 ring_setup_phys_status_page(engine);
9991ae78 596
ece4a17d 597 /* Enforce ordering by reading HEAD register back */
0bc40be8 598 I915_READ_HEAD(engine);
ece4a17d 599
0d8957c8
DV		 600 /* Initialize the ring. This must happen _after_ we've cleared the ring
601 * registers with the above sequence (the readback of the HEAD registers
602 * also enforces ordering), otherwise the hw might lose the new ring
603 * register values. */
0bc40be8 604 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 605
606 /* WaClearRingBufHeadRegAtInit:ctg,elk */
0bc40be8 607 if (I915_READ_HEAD(engine))
95468892 608 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
0bc40be8
TU		 609 engine->name, I915_READ_HEAD(engine));
610 I915_WRITE_HEAD(engine, 0);
611 (void)I915_READ_HEAD(engine);
95468892 612
0bc40be8 613 I915_WRITE_CTL(engine,
93b0a4e0 614 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 615 | RING_VALID);
8187a2b7 616
8187a2b7 617 /* If the head is still not zero, the ring is dead */
0bc40be8
TU		 618 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
619 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
620 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
e74cfed5 621 DRM_ERROR("%s initialization failed "
48e48a0b 622 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
0bc40be8
TU		 623 engine->name,
624 I915_READ_CTL(engine),
625 I915_READ_CTL(engine) & RING_VALID,
626 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
627 I915_READ_START(engine),
628 (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 629 ret = -EIO;
630 goto out;
8187a2b7
ZN		 631 }
632
ebd0fd4b 633 ringbuf->last_retired_head = -1;
0bc40be8
TU		 634 ringbuf->head = I915_READ_HEAD(engine);
635 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
ebd0fd4b 636 intel_ring_update_space(ringbuf);
1ec14ad3 637
fc0768ce 638 intel_engine_init_hangcheck(engine);
50f018df 639
b7884eb4 640out:
59bad947 641 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 642
643 return ret;
8187a2b7
ZN		 644}
645
9b1136d5 646void
0bc40be8 647intel_fini_pipe_control(struct intel_engine_cs *engine)
9b1136d5 648{
0bc40be8 649 if (engine->scratch.obj == NULL)
9b1136d5
OM		 650 return;
651
c033666a 652 if (INTEL_GEN(engine->i915) >= 5) {
0bc40be8
TU		 653 kunmap(sg_page(engine->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(engine->scratch.obj);
9b1136d5
OM		 655 }
656
0bc40be8
TU		 657 drm_gem_object_unreference(&engine->scratch.obj->base);
658 engine->scratch.obj = NULL;
9b1136d5
OM		 659}
660
661int
0bc40be8 662intel_init_pipe_control(struct intel_engine_cs *engine)
c6df541c 663{
c6df541c
CW		 664 int ret;
665
0bc40be8 666 WARN_ON(engine->scratch.obj);
c6df541c 667
c033666a 668 engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
fe3db79b 669 if (IS_ERR(engine->scratch.obj)) {
c6df541c 670 DRM_ERROR("Failed to allocate seqno page\n");
fe3db79b
CW		 671 ret = PTR_ERR(engine->scratch.obj);
672 engine->scratch.obj = NULL;
c6df541c
CW		 673 goto err;
674 }
e4ffd173 675
0bc40be8
TU		 676 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
677 I915_CACHE_LLC);
a9cc726c
DV		 678 if (ret)
679 goto err_unref;
c6df541c 680
0bc40be8 681 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
c6df541c
CW		 682 if (ret)
683 goto err_unref;
684
0bc40be8
TU		 685 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
686 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
687 if (engine->scratch.cpu_page == NULL) {
56b085a0 688 ret = -ENOMEM;
c6df541c 689 goto err_unpin;
56b085a0 690 }
c6df541c 691
2b1086cc 692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0bc40be8 693 engine->name, engine->scratch.gtt_offset);
c6df541c
CW		 694 return 0;
695
696err_unpin:
0bc40be8 697 i915_gem_object_ggtt_unpin(engine->scratch.obj);
c6df541c 698err_unref:
0bc40be8 699 drm_gem_object_unreference(&engine->scratch.obj->base);
c6df541c 700err:
c6df541c
CW		 701 return ret;
702}
703
e2be4faf 704static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 705{
4a570db5 706 struct intel_engine_cs *engine = req->engine;
c033666a
CW		 707 struct i915_workarounds *w = &req->i915->workarounds;
708 int ret, i;
888b5995 709
02235808 710 if (w->count == 0)
7225342a 711 return 0;
888b5995 712
e2f80391 713 engine->gpu_caches_dirty = true;
4866d729 714 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 715 if (ret)
716 return ret;
888b5995 717
5fb9de1a 718 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 719 if (ret)
720 return ret;
721
e2f80391 722 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
7225342a 723 for (i = 0; i < w->count; i++) {
e2f80391
TU		 724 intel_ring_emit_reg(engine, w->reg[i].addr);
725 intel_ring_emit(engine, w->reg[i].value);
7225342a 726 }
e2f80391 727 intel_ring_emit(engine, MI_NOOP);
7225342a 728
e2f80391 729 intel_ring_advance(engine);
7225342a 730
e2f80391 731 engine->gpu_caches_dirty = true;
4866d729 732 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 733 if (ret)
734 return ret;
888b5995 735
7225342a 736 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 737
7225342a 738 return 0;
86d7f238
AS		 739}
740
8753181e 741static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 742{
743 int ret;
744
e2be4faf 745 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 746 if (ret != 0)
747 return ret;
748
be01363f 749 ret = i915_gem_render_state_init(req);
8f0e2b9d 750 if (ret)
e26e1b97 751 return ret;
8f0e2b9d 752
e26e1b97 753 return 0;
8f0e2b9d
DV		 754}
755
7225342a 756static int wa_add(struct drm_i915_private *dev_priv,
f0f59a00
VS		 757 i915_reg_t addr,
758 const u32 mask, const u32 val)
7225342a
MK		 759{
760 const u32 idx = dev_priv->workarounds.count;
761
762 if (WARN_ON(idx >= I915_MAX_WA_REGS))
763 return -ENOSPC;
764
765 dev_priv->workarounds.reg[idx].addr = addr;
766 dev_priv->workarounds.reg[idx].value = val;
767 dev_priv->workarounds.reg[idx].mask = mask;
768
769 dev_priv->workarounds.count++;
770
771 return 0;
86d7f238
AS		 772}
773
ca5a0fbd 774#define WA_REG(addr, mask, val) do { \
cf4b0de6 775 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 776 if (r) \
777 return r; \
ca5a0fbd 778 } while (0)
7225342a
MK		 779
780#define WA_SET_BIT_MASKED(addr, mask) \
26459343 781 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 782
783#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 784 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 785
98533251 786#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 787 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 788
cf4b0de6
DL		 789#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
790#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 791
cf4b0de6 792#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 793
0bc40be8
TU		 794static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
795 i915_reg_t reg)
33136b06 796{
c033666a 797 struct drm_i915_private *dev_priv = engine->i915;
33136b06 798 struct i915_workarounds *wa = &dev_priv->workarounds;
0bc40be8 799 const uint32_t index = wa->hw_whitelist_count[engine->id];
33136b06
AS		 800
801 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
802 return -EINVAL;
803
0bc40be8 804 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
33136b06 805 i915_mmio_reg_offset(reg));
0bc40be8 806 wa->hw_whitelist_count[engine->id]++;
33136b06
AS		 807
808 return 0;
809}
810
0bc40be8 811static int gen8_init_workarounds(struct intel_engine_cs *engine)
e9a64ada 812{
c033666a 813 struct drm_i915_private *dev_priv = engine->i915;
68c6198b
AS		 814
815 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 816
717d84d6
AS		 817 /* WaDisableAsyncFlipPerfMode:bdw,chv */
818 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
819
d0581194
AS		 820 /* WaDisablePartialInstShootdown:bdw,chv */
821 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
822 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
823
a340af58
AS		 824 /* Use Force Non-Coherent whenever executing a 3D context. This is a
825 * workaround for for a possible hang in the unlikely event a TLB
826 * invalidation occurs during a PSD flush.
827 */
828 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 829 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 831 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 832 HDC_FORCE_NON_COHERENT);
833
6def8fdd
AS		 834 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
835 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
836 * polygons in the same 8x4 pixel/sample area to be processed without
837 * stalling waiting for the earlier ones to write to Hierarchical Z
838 * buffer."
839 *
840 * This optimization is off by default for BDW and CHV; turn it on.
841 */
842 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
843
48404636
AS		 844 /* Wa4x4STCOptimizationDisable:bdw,chv */
845 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
846
7eebcde6
AS		 847 /*
848 * BSpec recommends 8x4 when MSAA is used,
849 * however in practice 16x4 seems fastest.
850 *
851 * Note that PS/WM thread counts depend on the WIZ hashing
852 * disable bit, which we don't touch here, but it's good
853 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
854 */
855 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
856 GEN6_WIZ_HASHING_MASK,
857 GEN6_WIZ_HASHING_16x4);
858
e9a64ada
AS		 859 return 0;
860}
861
0bc40be8 862static int bdw_init_workarounds(struct intel_engine_cs *engine)
86d7f238 863{
c033666a 864 struct drm_i915_private *dev_priv = engine->i915;
e9a64ada 865 int ret;
86d7f238 866
0bc40be8 867 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 868 if (ret)
869 return ret;
870
101b376d 871 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 872 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 873
101b376d 874 /* WaDisableDopClockGating:bdw */
7225342a
MK		 875 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
876 DOP_CLOCK_GATING_DISABLE);
86d7f238 877
7225342a
MK		 878 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
879 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 880
7225342a 881 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 882 /* WaForceContextSaveRestoreNonCoherent:bdw */
883 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 884 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
c033666a 885 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 886
86d7f238
AS		 887 return 0;
888}
889
0bc40be8 890static int chv_init_workarounds(struct intel_engine_cs *engine)
00e1e623 891{
c033666a 892 struct drm_i915_private *dev_priv = engine->i915;
e9a64ada 893 int ret;
00e1e623 894
0bc40be8 895 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 896 if (ret)
897 return ret;
898
00e1e623 899 /* WaDisableThreadStallDopClockGating:chv */
d0581194 900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 901
d60de81d
KG		 902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
904
7225342a
MK		 905 return 0;
906}
907
0bc40be8 908static int gen9_init_workarounds(struct intel_engine_cs *engine)
3b106531 909{
c033666a 910 struct drm_i915_private *dev_priv = engine->i915;
8ea6f892 911 uint32_t tmp;
e0f3fa09 912 int ret;
ab0dfafe 913
9c4cbf82
MK		 914 /* WaEnableLbsSlaRetryTimerDecrement:skl */
915 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
916 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
917
918 /* WaDisableKillLogic:bxt,skl */
919 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
920 ECOCHK_DIS_TLB);
921
950b2aae 922 /* WaClearFlowControlGpgpuContextSave:skl,bxt */
b0e6f6d4 923 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe 924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
950b2aae 925 FLOW_CONTROL_ENABLE |
ab0dfafe
HN		 926 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
927
a119a6e6 928 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 929 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
930 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
931
e87a005d 932 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
c033666a
CW		 933 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
934 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
a86eb582
DL		 935 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
936 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 937
e87a005d 938 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
c033666a
CW		 939 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
940 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
183c6dac
DL		 941 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
942 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 943 /*
944 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
945 * but we do that in per ctx batchbuffer as there is an issue
946 * with this register not getting restored on ctx restore
947 */
183c6dac
DL		 948 }
949
e87a005d 950 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
bfd8ad4e
TG		 951 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
952 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
953 GEN9_ENABLE_YV12_BUGFIX |
954 GEN9_ENABLE_GPGPU_PREEMPTION);
cac23df4 955
5068368c 956 /* Wa4x4STCOptimizationDisable:skl,bxt */
27160c96 957 /* WaDisablePartialResolveInVc:skl,bxt */
60294683
AS		 958 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
959 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 960
16be17af 961 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 962 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
963 GEN9_CCS_TLB_PREFETCH_ENABLE);
964
5a2ae95e 965 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
c033666a
CW		 966 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
967 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
38a39a7b
BW		 968 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
969 PIXEL_MASK_CAMMING_DISABLE);
970
8ea6f892
ID		 971 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
972 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
c033666a
CW		 973 if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
974 IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
8ea6f892
ID		 975 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
976 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
977
8c761609 978 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
c033666a 979 if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
8c761609
AS		 980 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
981 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 982
6b6d5626
RB		 983 /* WaDisableSTUnitPowerOptimization:skl,bxt */
984 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
985
6ecf56ae
AS		 986 /* WaOCLCoherentLineFlush:skl,bxt */
987 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
988 GEN8_LQSC_FLUSH_COHERENT_LINES));
989
6bb62855 990 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
991 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
992 if (ret)
993 return ret;
994
e0f3fa09 995 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
0bc40be8 996 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
e0f3fa09
AS		 997 if (ret)
998 return ret;
999
3669ab61 1000 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
0bc40be8 1001 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
3669ab61
AS		 1002 if (ret)
1003 return ret;
1004
3b106531
HN		 1005 return 0;
1006}
1007
0bc40be8 1008static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
b7668791 1009{
c033666a 1010 struct drm_i915_private *dev_priv = engine->i915;
b7668791
DL		 1011 u8 vals[3] = { 0, 0, 0 };
1012 unsigned int i;
1013
1014 for (i = 0; i < 3; i++) {
1015 u8 ss;
1016
1017 /*
1018 * Only consider slices where one, and only one, subslice has 7
1019 * EUs
1020 */
a4d8a0fe 1021 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
b7668791
DL		 1022 continue;
1023
1024 /*
1025 * subslice_7eu[i] != 0 (because of the check above) and
1026 * ss_max == 4 (maximum number of subslices possible per slice)
1027 *
1028 * -> 0 <= ss <= 3;
1029 */
1030 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1031 vals[i] = 3 - ss;
1032 }
1033
1034 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1035 return 0;
1036
1037 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1038 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1039 GEN9_IZ_HASHING_MASK(2) |
1040 GEN9_IZ_HASHING_MASK(1) |
1041 GEN9_IZ_HASHING_MASK(0),
1042 GEN9_IZ_HASHING(2, vals[2]) |
1043 GEN9_IZ_HASHING(1, vals[1]) |
1044 GEN9_IZ_HASHING(0, vals[0]));
1045
1046 return 0;
1047}
1048
0bc40be8 1049static int skl_init_workarounds(struct intel_engine_cs *engine)
8d205494 1050{
c033666a 1051 struct drm_i915_private *dev_priv = engine->i915;
aa0011a8 1052 int ret;
d0bbbc4f 1053
0bc40be8 1054 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1055 if (ret)
1056 return ret;
8d205494 1057
a78536e7
AS		 1058 /*
1059 * Actual WA is to disable percontext preemption granularity control
1060 * until D0 which is the default case so this is equivalent to
1061 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1062 */
c033666a 1063 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
a78536e7
AS		 1064 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1065 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1066 }
1067
c033666a 1068 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
9c4cbf82
MK		 1069 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1070 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1071 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1072 }
1073
1074 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1075 * involving this register should also be added to WA batch as required.
1076 */
c033666a 1077 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
9c4cbf82
MK		 1078 /* WaDisableLSQCROPERFforOCL:skl */
1079 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1080 GEN8_LQSC_RO_PERF_DIS);
1081
1082 /* WaEnableGapsTsvCreditFix:skl */
c033666a 1083 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1084 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1085 GEN9_GAPS_TSV_CREDIT_DISABLE));
1086 }
1087
d0bbbc4f 1088 /* WaDisablePowerCompilerClockGating:skl */
c033666a 1089 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1090 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1091 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1092
97ea6be1 1093 /* This is tied to WaForceContextSaveRestoreNonCoherent */
c033666a 1094 if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
b62adbd1
NH		 1095 /*
1096 *Use Force Non-Coherent whenever executing a 3D context. This
1097 * is a workaround for a possible hang in the unlikely event
1098 * a TLB invalidation occurs during a PSD flush.
1099 */
1100 /* WaForceEnableNonCoherent:skl */
1101 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1102 HDC_FORCE_NON_COHERENT);
e238659d
MK		 1103
1104 /* WaDisableHDCInvalidation:skl */
1105 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1106 BDW_DISABLE_HDC_INVALIDATION);
b62adbd1
NH		 1107 }
1108
e87a005d 1109 /* WaBarrierPerformanceFixDisable:skl */
c033666a 1110 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1111 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1112 HDC_FENCE_DEST_SLM_DISABLE |
1113 HDC_BARRIER_PERFORMANCE_DISABLE);
1114
9bd9dfb4 1115 /* WaDisableSbeCacheDispatchPortSharing:skl */
c033666a 1116 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1117 WA_SET_BIT_MASKED(
1118 GEN7_HALF_SLICE_CHICKEN1,
1119 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1120
6107497e 1121 /* WaDisableLSQCROPERFforOCL:skl */
0bc40be8 1122 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
6107497e
AS		 1123 if (ret)
1124 return ret;
1125
0bc40be8 1126 return skl_tune_iz_hashing(engine);
7225342a
MK		 1127}
1128
0bc40be8 1129static int bxt_init_workarounds(struct intel_engine_cs *engine)
cae0437f 1130{
c033666a 1131 struct drm_i915_private *dev_priv = engine->i915;
aa0011a8 1132 int ret;
dfb601e6 1133
0bc40be8 1134 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1135 if (ret)
1136 return ret;
cae0437f 1137
9c4cbf82
MK		 1138 /* WaStoreMultiplePTEenable:bxt */
1139 /* This is a requirement according to Hardware specification */
c033666a 1140 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
9c4cbf82
MK		 1141 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1142
1143 /* WaSetClckGatingDisableMedia:bxt */
c033666a 1144 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
9c4cbf82
MK		 1145 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1146 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1147 }
1148
dfb601e6
NH		 1149 /* WaDisableThreadStallDopClockGating:bxt */
1150 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1151 STALL_DOP_GATING_DISABLE);
1152
983b4b9d 1153 /* WaDisableSbeCacheDispatchPortSharing:bxt */
c033666a 1154 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1155 WA_SET_BIT_MASKED(
1156 GEN7_HALF_SLICE_CHICKEN1,
1157 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1158 }
1159
2c8580e4
AS		 1160 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1161 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1162 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
a786d53a 1163 /* WaDisableLSQCROPERFforOCL:bxt */
c033666a 1164 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
0bc40be8 1165 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
2c8580e4
AS		 1166 if (ret)
1167 return ret;
a786d53a 1168
0bc40be8 1169 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
a786d53a
AS		 1170 if (ret)
1171 return ret;
2c8580e4
AS		 1172 }
1173
050fc465 1174 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
c033666a 1175 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
36579cb6
ID		 1176 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1177 L3_HIGH_PRIO_CREDITS(2));
050fc465 1178
cae0437f
NH		 1179 return 0;
1180}
1181
0bc40be8 1182int init_workarounds_ring(struct intel_engine_cs *engine)
7225342a 1183{
c033666a 1184 struct drm_i915_private *dev_priv = engine->i915;
7225342a 1185
0bc40be8 1186 WARN_ON(engine->id != RCS);
7225342a
MK		 1187
1188 dev_priv->workarounds.count = 0;
33136b06 1189 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
7225342a 1190
c033666a 1191 if (IS_BROADWELL(dev_priv))
0bc40be8 1192 return bdw_init_workarounds(engine);
7225342a 1193
c033666a 1194 if (IS_CHERRYVIEW(dev_priv))
0bc40be8 1195 return chv_init_workarounds(engine);
00e1e623 1196
c033666a 1197 if (IS_SKYLAKE(dev_priv))
0bc40be8 1198 return skl_init_workarounds(engine);
cae0437f 1199
c033666a 1200 if (IS_BROXTON(dev_priv))
0bc40be8 1201 return bxt_init_workarounds(engine);
3b106531 1202
00e1e623
VS		 1203 return 0;
1204}
1205
0bc40be8 1206static int init_render_ring(struct intel_engine_cs *engine)
8187a2b7 1207{
c033666a 1208 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 1209 int ret = init_ring_common(engine);
9c33baa6
KZ		 1210 if (ret)
1211 return ret;
a69ffdbf 1212
61a563a2 1213 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
ac657f64 1214 if (IS_GEN(dev_priv, 4, 6))
6b26c86d 1215 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1216
1217 /* We need to disable the AsyncFlip performance optimisations in order
1218 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1219 * programmed to '1' on all products.
8693a824 1220 *
2441f877 1221 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1222 */
ac657f64 1223 if (IS_GEN(dev_priv, 6, 7))
1c8c38c5
CW		 1224 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1225
f05bb0c7 1226 /* Required for the hardware to program scanline values for waiting */
01fa0302 1227 /* WaEnableFlushTlbInvalidationMode:snb */
c033666a 1228 if (IS_GEN6(dev_priv))
f05bb0c7 1229 I915_WRITE(GFX_MODE,
aa83e30d 1230 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1231
01fa0302 1232 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
c033666a 1233 if (IS_GEN7(dev_priv))
1c8c38c5 1234 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1235 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1236 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1237
c033666a 1238 if (IS_GEN6(dev_priv)) {
3a69ddd6
KG		 1239 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1240 * "If this bit is set, STCunit will have LRA as replacement
1241 * policy. [...] This bit must be reset. LRA replacement
1242 * policy is not supported."
1243 */
1244 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1245 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1246 }
1247
ac657f64 1248 if (IS_GEN(dev_priv, 6, 7))
6b26c86d 1249 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1250
c033666a
CW		 1251 if (HAS_L3_DPF(dev_priv))
1252 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
15b9f80e 1253
0bc40be8 1254 return init_workarounds_ring(engine);
8187a2b7
ZN		 1255}
1256
0bc40be8 1257static void render_ring_cleanup(struct intel_engine_cs *engine)
c6df541c 1258{
c033666a 1259 struct drm_i915_private *dev_priv = engine->i915;
3e78998a
BW		 1260
1261 if (dev_priv->semaphore_obj) {
1262 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1263 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1264 dev_priv->semaphore_obj = NULL;
1265 }
b45305fc 1266
0bc40be8 1267 intel_fini_pipe_control(engine);
c6df541c
CW		 1268}
1269
f7169687 1270static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1271 unsigned int num_dwords)
1272{
1273#define MBOX_UPDATE_DWORDS 8
4a570db5 1274 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1275 struct drm_i915_private *dev_priv = signaller_req->i915;
3e78998a 1276 struct intel_engine_cs *waiter;
c3232b18
DG		 1277 enum intel_engine_id id;
1278 int ret, num_rings;
3e78998a 1279
c033666a 1280 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
3e78998a
BW		 1281 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1282#undef MBOX_UPDATE_DWORDS
1283
5fb9de1a 1284 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1285 if (ret)
1286 return ret;
1287
c3232b18 1288 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1289 u32 seqno;
c3232b18 1290 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1291 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1292 continue;
1293
f7169687 1294 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1295 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1296 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1297 PIPE_CONTROL_QW_WRITE |
f9a4ea35 1298 PIPE_CONTROL_CS_STALL);
3e78998a
BW		 1299 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1300 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1301 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1302 intel_ring_emit(signaller, 0);
1303 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
215a7e32 1304 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1305 intel_ring_emit(signaller, 0);
1306 }
1307
1308 return 0;
1309}
1310
f7169687 1311static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1312 unsigned int num_dwords)
1313{
1314#define MBOX_UPDATE_DWORDS 6
4a570db5 1315 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1316 struct drm_i915_private *dev_priv = signaller_req->i915;
3e78998a 1317 struct intel_engine_cs *waiter;
c3232b18
DG		 1318 enum intel_engine_id id;
1319 int ret, num_rings;
3e78998a 1320
c033666a 1321 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
3e78998a
BW		 1322 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1323#undef MBOX_UPDATE_DWORDS
1324
5fb9de1a 1325 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1326 if (ret)
1327 return ret;
1328
c3232b18 1329 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1330 u32 seqno;
c3232b18 1331 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1332 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1333 continue;
1334
f7169687 1335 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1336 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1337 MI_FLUSH_DW_OP_STOREDW);
1338 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1339 MI_FLUSH_DW_USE_GTT);
1340 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1341 intel_ring_emit(signaller, seqno);
3e78998a 1342 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
215a7e32 1343 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1344 intel_ring_emit(signaller, 0);
1345 }
1346
1347 return 0;
1348}
1349
f7169687 1350static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1351 unsigned int num_dwords)
1ec14ad3 1352{
4a570db5 1353 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1354 struct drm_i915_private *dev_priv = signaller_req->i915;
a4872ba6 1355 struct intel_engine_cs *useless;
c3232b18
DG		 1356 enum intel_engine_id id;
1357 int ret, num_rings;
78325f2d 1358
a1444b79 1359#define MBOX_UPDATE_DWORDS 3
c033666a 1360 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
a1444b79
BW		 1361 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1362#undef MBOX_UPDATE_DWORDS
024a43e1 1363
5fb9de1a 1364 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1365 if (ret)
1366 return ret;
024a43e1 1367
c3232b18
DG		 1368 for_each_engine_id(useless, dev_priv, id) {
1369 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
f0f59a00
VS		 1370
1371 if (i915_mmio_reg_valid(mbox_reg)) {
f7169687 1372 u32 seqno = i915_gem_request_get_seqno(signaller_req);
f0f59a00 1373
78325f2d 1374 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
f92a9162 1375 intel_ring_emit_reg(signaller, mbox_reg);
6259cead 1376 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1377 }
1378 }
024a43e1 1379
a1444b79
BW		 1380 /* If num_dwords was rounded, make sure the tail pointer is correct */
1381 if (num_rings % 2 == 0)
1382 intel_ring_emit(signaller, MI_NOOP);
1383
024a43e1 1384 return 0;
1ec14ad3
CW		 1385}
1386
c8c99b0f
BW		 1387/**
1388 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1389 *
1390 * @request - request to write to the ring
c8c99b0f
BW		 1391 *
1392 * Update the mailbox registers in the *other* rings with the current seqno.
1393 * This acts like a signal in the canonical semaphore.
1394 */
1ec14ad3 1395static int
ee044a88 1396gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1397{
4a570db5 1398 struct intel_engine_cs *engine = req->engine;
024a43e1 1399 int ret;
52ed2325 1400
e2f80391
TU		 1401 if (engine->semaphore.signal)
1402 ret = engine->semaphore.signal(req, 4);
707d9cf9 1403 else
5fb9de1a 1404 ret = intel_ring_begin(req, 4);
707d9cf9 1405
1ec14ad3
CW		 1406 if (ret)
1407 return ret;
1408
e2f80391
TU		 1409 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1410 intel_ring_emit(engine,
1411 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1412 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1413 intel_ring_emit(engine, MI_USER_INTERRUPT);
1414 __intel_ring_advance(engine);
1ec14ad3 1415
1ec14ad3
CW		 1416 return 0;
1417}
1418
a58c01aa
CW		 1419static int
1420gen8_render_add_request(struct drm_i915_gem_request *req)
1421{
1422 struct intel_engine_cs *engine = req->engine;
1423 int ret;
1424
1425 if (engine->semaphore.signal)
1426 ret = engine->semaphore.signal(req, 8);
1427 else
1428 ret = intel_ring_begin(req, 8);
1429 if (ret)
1430 return ret;
1431
1432 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1433 intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1434 PIPE_CONTROL_CS_STALL |
1435 PIPE_CONTROL_QW_WRITE));
1436 intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1437 intel_ring_emit(engine, 0);
1438 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1439 /* We're thrashing one dword of HWS. */
1440 intel_ring_emit(engine, 0);
1441 intel_ring_emit(engine, MI_USER_INTERRUPT);
1442 intel_ring_emit(engine, MI_NOOP);
1443 __intel_ring_advance(engine);
1444
1445 return 0;
1446}
1447
c033666a 1448static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
f72b3435
MK		 1449 u32 seqno)
1450{
f72b3435
MK		 1451 return dev_priv->last_seqno < seqno;
1452}
1453
c8c99b0f
BW		 1454/**
1455 * intel_ring_sync - sync the waiter to the signaller on seqno
1456 *
1457 * @waiter - ring that is waiting
1458 * @signaller - ring which has, or will signal
1459 * @seqno - seqno which the waiter will block on
1460 */
5ee426ca
BW		 1461
1462static int
599d924c 1463gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1464 struct intel_engine_cs *signaller,
1465 u32 seqno)
1466{
4a570db5 1467 struct intel_engine_cs *waiter = waiter_req->engine;
c033666a 1468 struct drm_i915_private *dev_priv = waiter_req->i915;
6ef48d7f 1469 struct i915_hw_ppgtt *ppgtt;
5ee426ca
BW		 1470 int ret;
1471
5fb9de1a 1472 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1473 if (ret)
1474 return ret;
1475
1476 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1477 MI_SEMAPHORE_GLOBAL_GTT |
1478 MI_SEMAPHORE_SAD_GTE_SDD);
1479 intel_ring_emit(waiter, seqno);
1480 intel_ring_emit(waiter,
1481 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1482 intel_ring_emit(waiter,
1483 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1484 intel_ring_advance(waiter);
6ef48d7f
CW		 1485
1486 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1487 * pagetables and we must reload them before executing the batch.
1488 * We do this on the i915_switch_context() following the wait and
1489 * before the dispatch.
1490 */
1491 ppgtt = waiter_req->ctx->ppgtt;
1492 if (ppgtt && waiter_req->engine->id != RCS)
1493 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
5ee426ca
BW		 1494 return 0;
1495}
1496
c8c99b0f 1497static int
599d924c 1498gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1499 struct intel_engine_cs *signaller,
686cb5f9 1500 u32 seqno)
1ec14ad3 1501{
4a570db5 1502 struct intel_engine_cs *waiter = waiter_req->engine;
c8c99b0f
BW		 1503 u32 dw1 = MI_SEMAPHORE_MBOX |
1504 MI_SEMAPHORE_COMPARE |
1505 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1506 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1507 int ret;
1ec14ad3 1508
1500f7ea
BW		 1509 /* Throughout all of the GEM code, seqno passed implies our current
1510 * seqno is >= the last seqno executed. However for hardware the
1511 * comparison is strictly greater than.
1512 */
1513 seqno -= 1;
1514
ebc348b2 1515 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1516
5fb9de1a 1517 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1518 if (ret)
1519 return ret;
1520
f72b3435 1521 /* If seqno wrap happened, omit the wait with no-ops */
c033666a 1522 if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
ebc348b2 1523 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1524 intel_ring_emit(waiter, seqno);
1525 intel_ring_emit(waiter, 0);
1526 intel_ring_emit(waiter, MI_NOOP);
1527 } else {
1528 intel_ring_emit(waiter, MI_NOOP);
1529 intel_ring_emit(waiter, MI_NOOP);
1530 intel_ring_emit(waiter, MI_NOOP);
1531 intel_ring_emit(waiter, MI_NOOP);
1532 }
c8c99b0f 1533 intel_ring_advance(waiter);
1ec14ad3
CW		 1534
1535 return 0;
1536}
1537
c6df541c
CW		 1538#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1539do { \
fcbc34e4
KG		 1540 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1541 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1542 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1543 intel_ring_emit(ring__, 0); \
1544 intel_ring_emit(ring__, 0); \
1545} while (0)
1546
1547static int
ee044a88 1548pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1549{
4a570db5 1550 struct intel_engine_cs *engine = req->engine;
e2f80391 1551 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1552 int ret;
1553
1554 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1555 * incoherent with writes to memory, i.e. completely fubar,
1556 * so we need to use PIPE_NOTIFY instead.
1557 *
1558 * However, we also need to workaround the qword write
1559 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1560 * memory before requesting an interrupt.
1561 */
5fb9de1a 1562 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1563 if (ret)
1564 return ret;
1565
e2f80391
TU		 1566 intel_ring_emit(engine,
1567 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1568 PIPE_CONTROL_WRITE_FLUSH |
1569 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
e2f80391
TU		 1570 intel_ring_emit(engine,
1571 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1572 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1573 intel_ring_emit(engine, 0);
1574 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1575 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
e2f80391 1576 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1577 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1578 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1579 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1580 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1581 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1582 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1583 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1584 PIPE_CONTROL_FLUSH(engine, scratch_addr);
a71d8d94 1585
e2f80391
TU		 1586 intel_ring_emit(engine,
1587 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1588 PIPE_CONTROL_WRITE_FLUSH |
1589 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1590 PIPE_CONTROL_NOTIFY);
e2f80391
TU		 1591 intel_ring_emit(engine,
1592 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1593 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1594 intel_ring_emit(engine, 0);
1595 __intel_ring_advance(engine);
c6df541c 1596
c6df541c
CW		 1597 return 0;
1598}
1599
c04e0f3b
CW		 1600static void
1601gen6_seqno_barrier(struct intel_engine_cs *engine)
4cd53c0c 1602{
c033666a 1603 struct drm_i915_private *dev_priv = engine->i915;
bcbdb6d0 1604
4cd53c0c
DV		 1605 /* Workaround to force correct ordering between irq and seqno writes on
1606 * ivb (and maybe also on snb) by reading from a CS register (like
9b9ed309
CW		 1607 * ACTHD) before reading the status page.
1608 *
1609 * Note that this effectively stalls the read by the time it takes to
1610 * do a memory transaction, which more or less ensures that the write
1611 * from the GPU has sufficient time to invalidate the CPU cacheline.
1612 * Alternatively we could delay the interrupt from the CS ring to give
1613 * the write time to land, but that would incur a delay after every
1614 * batch i.e. much more frequent than a delay when waiting for the
1615 * interrupt (with the same net latency).
bcbdb6d0
CW		 1616 *
1617 * Also note that to prevent whole machine hangs on gen7, we have to
1618 * take the spinlock to guard against concurrent cacheline access.
9b9ed309 1619 */
bcbdb6d0 1620 spin_lock_irq(&dev_priv->uncore.lock);
c04e0f3b 1621 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
bcbdb6d0 1622 spin_unlock_irq(&dev_priv->uncore.lock);
4cd53c0c
DV		 1623}
1624
8187a2b7 1625static u32
c04e0f3b 1626ring_get_seqno(struct intel_engine_cs *engine)
8187a2b7 1627{
0bc40be8 1628 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1ec14ad3
CW		 1629}
1630
b70ec5bf 1631static void
0bc40be8 1632ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1633{
0bc40be8 1634 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
b70ec5bf
MK		 1635}
1636
c6df541c 1637static u32
c04e0f3b 1638pc_render_get_seqno(struct intel_engine_cs *engine)
c6df541c 1639{
0bc40be8 1640 return engine->scratch.cpu_page[0];
c6df541c
CW		 1641}
1642
b70ec5bf 1643static void
0bc40be8 1644pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1645{
0bc40be8 1646 engine->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1647}
1648
e48d8634 1649static bool
0bc40be8 1650gen5_ring_get_irq(struct intel_engine_cs *engine)
e48d8634 1651{
c033666a 1652 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1653 unsigned long flags;
e48d8634 1654
7cd512f1 1655 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1656 return false;
1657
7338aefa 1658 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1659 if (engine->irq_refcount++ == 0)
1660 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1661 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1662
1663 return true;
1664}
1665
1666static void
0bc40be8 1667gen5_ring_put_irq(struct intel_engine_cs *engine)
e48d8634 1668{
c033666a 1669 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1670 unsigned long flags;
e48d8634 1671
7338aefa 1672 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1673 if (--engine->irq_refcount == 0)
1674 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1675 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1676}
1677
b13c2b96 1678static bool
0bc40be8 1679i9xx_ring_get_irq(struct intel_engine_cs *engine)
62fdfeaf 1680{
c033666a 1681 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1682 unsigned long flags;
62fdfeaf 1683
7cd512f1 1684 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1685 return false;
1686
7338aefa 1687 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1688 if (engine->irq_refcount++ == 0) {
1689 dev_priv->irq_mask &= ~engine->irq_enable_mask;
f637fde4
DV		 1690 I915_WRITE(IMR, dev_priv->irq_mask);
1691 POSTING_READ(IMR);
1692 }
7338aefa 1693 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1694
1695 return true;
62fdfeaf
EA		 1696}
1697
8187a2b7 1698static void
0bc40be8 1699i9xx_ring_put_irq(struct intel_engine_cs *engine)
62fdfeaf 1700{
c033666a 1701 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1702 unsigned long flags;
62fdfeaf 1703
7338aefa 1704 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1705 if (--engine->irq_refcount == 0) {
1706 dev_priv->irq_mask |= engine->irq_enable_mask;
f637fde4
DV		 1707 I915_WRITE(IMR, dev_priv->irq_mask);
1708 POSTING_READ(IMR);
1709 }
7338aefa 1710 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1711}
1712
c2798b19 1713static bool
0bc40be8 1714i8xx_ring_get_irq(struct intel_engine_cs *engine)
c2798b19 1715{
c033666a 1716 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1717 unsigned long flags;
c2798b19 1718
7cd512f1 1719 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1720 return false;
1721
7338aefa 1722 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1723 if (engine->irq_refcount++ == 0) {
1724 dev_priv->irq_mask &= ~engine->irq_enable_mask;
c2798b19
CW		 1725 I915_WRITE16(IMR, dev_priv->irq_mask);
1726 POSTING_READ16(IMR);
1727 }
7338aefa 1728 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1729
1730 return true;
1731}
1732
1733static void
0bc40be8 1734i8xx_ring_put_irq(struct intel_engine_cs *engine)
c2798b19 1735{
c033666a 1736 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1737 unsigned long flags;
c2798b19 1738
7338aefa 1739 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1740 if (--engine->irq_refcount == 0) {
1741 dev_priv->irq_mask |= engine->irq_enable_mask;
c2798b19
CW		 1742 I915_WRITE16(IMR, dev_priv->irq_mask);
1743 POSTING_READ16(IMR);
1744 }
7338aefa 1745 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1746}
1747
b72f3acb 1748static int
a84c3ae1 1749bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1750 u32 invalidate_domains,
1751 u32 flush_domains)
d1b851fc 1752{
4a570db5 1753 struct intel_engine_cs *engine = req->engine;
b72f3acb
CW		 1754 int ret;
1755
5fb9de1a 1756 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1757 if (ret)
1758 return ret;
1759
e2f80391
TU		 1760 intel_ring_emit(engine, MI_FLUSH);
1761 intel_ring_emit(engine, MI_NOOP);
1762 intel_ring_advance(engine);
b72f3acb 1763 return 0;
d1b851fc
ZN		 1764}
1765
3cce469c 1766static int
ee044a88 1767i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1768{
4a570db5 1769 struct intel_engine_cs *engine = req->engine;
3cce469c
CW		 1770 int ret;
1771
5fb9de1a 1772 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1773 if (ret)
1774 return ret;
6f392d54 1775
e2f80391
TU		 1776 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1777 intel_ring_emit(engine,
1778 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1779 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1780 intel_ring_emit(engine, MI_USER_INTERRUPT);
1781 __intel_ring_advance(engine);
d1b851fc 1782
3cce469c 1783 return 0;
d1b851fc
ZN		 1784}
1785
0f46832f 1786static bool
0bc40be8 1787gen6_ring_get_irq(struct intel_engine_cs *engine)
0f46832f 1788{
c033666a 1789 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1790 unsigned long flags;
0f46832f 1791
7cd512f1
DV		 1792 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1793 return false;
0f46832f 1794
7338aefa 1795 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1796 if (engine->irq_refcount++ == 0) {
c033666a 1797 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
0bc40be8
TU		 1798 I915_WRITE_IMR(engine,
1799 ~(engine->irq_enable_mask |
c033666a 1800 GT_PARITY_ERROR(dev_priv)));
15b9f80e 1801 else
0bc40be8
TU		 1802 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1803 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
0f46832f 1804 }
7338aefa 1805 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1806
1807 return true;
1808}
1809
1810static void
0bc40be8 1811gen6_ring_put_irq(struct intel_engine_cs *engine)
0f46832f 1812{
c033666a 1813 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1814 unsigned long flags;
0f46832f 1815
7338aefa 1816 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1817 if (--engine->irq_refcount == 0) {
c033666a
CW		 1818 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1819 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
15b9f80e 1820 else
0bc40be8
TU		 1821 I915_WRITE_IMR(engine, ~0);
1822 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1ec14ad3 1823 }
7338aefa 1824 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1825}
1826
a19d2933 1827static bool
0bc40be8 1828hsw_vebox_get_irq(struct intel_engine_cs *engine)
a19d2933 1829{
c033666a 1830 struct drm_i915_private *dev_priv = engine->i915;
a19d2933
BW		 1831 unsigned long flags;
1832
7cd512f1 1833 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1834 return false;
1835
59cdb63d 1836 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1837 if (engine->irq_refcount++ == 0) {
1838 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1839 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1840 }
59cdb63d 1841 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1842
1843 return true;
1844}
1845
1846static void
0bc40be8 1847hsw_vebox_put_irq(struct intel_engine_cs *engine)
a19d2933 1848{
c033666a 1849 struct drm_i915_private *dev_priv = engine->i915;
a19d2933
BW		 1850 unsigned long flags;
1851
59cdb63d 1852 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1853 if (--engine->irq_refcount == 0) {
1854 I915_WRITE_IMR(engine, ~0);
1855 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1856 }
59cdb63d 1857 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1858}
1859
abd58f01 1860static bool
0bc40be8 1861gen8_ring_get_irq(struct intel_engine_cs *engine)
abd58f01 1862{
c033666a 1863 struct drm_i915_private *dev_priv = engine->i915;
abd58f01
BW		 1864 unsigned long flags;
1865
7cd512f1 1866 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1867 return false;
1868
1869 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1870 if (engine->irq_refcount++ == 0) {
c033666a 1871 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
0bc40be8
TU		 1872 I915_WRITE_IMR(engine,
1873 ~(engine->irq_enable_mask |
abd58f01
BW		 1874 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1875 } else {
0bc40be8 1876 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
abd58f01 1877 }
0bc40be8 1878 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1879 }
1880 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1881
1882 return true;
1883}
1884
1885static void
0bc40be8 1886gen8_ring_put_irq(struct intel_engine_cs *engine)
abd58f01 1887{
c033666a 1888 struct drm_i915_private *dev_priv = engine->i915;
abd58f01
BW		 1889 unsigned long flags;
1890
1891 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1892 if (--engine->irq_refcount == 0) {
c033666a 1893 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
0bc40be8 1894 I915_WRITE_IMR(engine,
abd58f01
BW		 1895 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1896 } else {
0bc40be8 1897 I915_WRITE_IMR(engine, ~0);
abd58f01 1898 }
0bc40be8 1899 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1900 }
1901 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1902}
1903
d1b851fc 1904static int
53fddaf7 1905i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1906 u64 offset, u32 length,
8e004efc 1907 unsigned dispatch_flags)
d1b851fc 1908{
4a570db5 1909 struct intel_engine_cs *engine = req->engine;
e1f99ce6 1910 int ret;
78501eac 1911
5fb9de1a 1912 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1913 if (ret)
1914 return ret;
1915
e2f80391 1916 intel_ring_emit(engine,
65f56876
CW		 1917 MI_BATCH_BUFFER_START |
1918 MI_BATCH_GTT |
8e004efc
JH		 1919 (dispatch_flags & I915_DISPATCH_SECURE ?
1920 0 : MI_BATCH_NON_SECURE_I965));
e2f80391
TU		 1921 intel_ring_emit(engine, offset);
1922 intel_ring_advance(engine);
78501eac 1923
d1b851fc
ZN		 1924 return 0;
1925}
1926
b45305fc
DV		 1927/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1928#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1929#define I830_TLB_ENTRIES (2)
1930#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1931static int
53fddaf7 1932i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1933 u64 offset, u32 len,
1934 unsigned dispatch_flags)
62fdfeaf 1935{
4a570db5 1936 struct intel_engine_cs *engine = req->engine;
e2f80391 1937 u32 cs_offset = engine->scratch.gtt_offset;
c4e7a414 1938 int ret;
62fdfeaf 1939
5fb9de1a 1940 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1941 if (ret)
1942 return ret;
62fdfeaf 1943
c4d69da1 1944 /* Evict the invalid PTE TLBs */
e2f80391
TU		 1945 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1946 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1947 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1948 intel_ring_emit(engine, cs_offset);
1949 intel_ring_emit(engine, 0xdeadbeef);
1950 intel_ring_emit(engine, MI_NOOP);
1951 intel_ring_advance(engine);
b45305fc 1952
8e004efc 1953 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1954 if (len > I830_BATCH_LIMIT)
1955 return -ENOSPC;
1956
5fb9de1a 1957 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1958 if (ret)
1959 return ret;
c4d69da1
CW		 1960
1961 /* Blit the batch (which has now all relocs applied) to the
1962 * stable batch scratch bo area (so that the CS never
1963 * stumbles over its tlb invalidation bug) ...
1964 */
e2f80391
TU		 1965 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1966 intel_ring_emit(engine,
1967 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1968 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1969 intel_ring_emit(engine, cs_offset);
1970 intel_ring_emit(engine, 4096);
1971 intel_ring_emit(engine, offset);
1972
1973 intel_ring_emit(engine, MI_FLUSH);
1974 intel_ring_emit(engine, MI_NOOP);
1975 intel_ring_advance(engine);
b45305fc
DV		 1976
1977 /* ... and execute it. */
c4d69da1 1978 offset = cs_offset;
b45305fc 1979 }
e1f99ce6 1980
9d611c03 1981 ret = intel_ring_begin(req, 2);
c4d69da1
CW		 1982 if (ret)
1983 return ret;
1984
e2f80391
TU		 1985 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1986 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1987 0 : MI_BATCH_NON_SECURE));
1988 intel_ring_advance(engine);
c4d69da1 1989
fb3256da
DV		 1990 return 0;
1991}
1992
1993static int
53fddaf7 1994i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1995 u64 offset, u32 len,
8e004efc 1996 unsigned dispatch_flags)
fb3256da 1997{
4a570db5 1998 struct intel_engine_cs *engine = req->engine;
fb3256da
DV		 1999 int ret;
2000
5fb9de1a 2001 ret = intel_ring_begin(req, 2);
fb3256da
DV		 2002 if (ret)
2003 return ret;
2004
e2f80391
TU		 2005 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2006 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2007 0 : MI_BATCH_NON_SECURE));
2008 intel_ring_advance(engine);
62fdfeaf 2009
62fdfeaf
EA		 2010 return 0;
2011}
2012
0bc40be8 2013static void cleanup_phys_status_page(struct intel_engine_cs *engine)
7d3fdfff 2014{
c033666a 2015 struct drm_i915_private *dev_priv = engine->i915;
7d3fdfff
VS		 2016
2017 if (!dev_priv->status_page_dmah)
2018 return;
2019
c033666a 2020 drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
0bc40be8 2021 engine->status_page.page_addr = NULL;
7d3fdfff
VS		 2022}
2023
0bc40be8 2024static void cleanup_status_page(struct intel_engine_cs *engine)
62fdfeaf 2025{
05394f39 2026 struct drm_i915_gem_object *obj;
62fdfeaf 2027
0bc40be8 2028 obj = engine->status_page.obj;
8187a2b7 2029 if (obj == NULL)
62fdfeaf 2030 return;
62fdfeaf 2031
9da3da66 2032 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 2033 i915_gem_object_ggtt_unpin(obj);
05394f39 2034 drm_gem_object_unreference(&obj->base);
0bc40be8 2035 engine->status_page.obj = NULL;
62fdfeaf
EA		 2036}
2037
0bc40be8 2038static int init_status_page(struct intel_engine_cs *engine)
62fdfeaf 2039{
0bc40be8 2040 struct drm_i915_gem_object *obj = engine->status_page.obj;
62fdfeaf 2041
7d3fdfff 2042 if (obj == NULL) {
1f767e02 2043 unsigned flags;
e3efda49 2044 int ret;
e4ffd173 2045
c033666a 2046 obj = i915_gem_object_create(engine->i915->dev, 4096);
fe3db79b 2047 if (IS_ERR(obj)) {
e3efda49 2048 DRM_ERROR("Failed to allocate status page\n");
fe3db79b 2049 return PTR_ERR(obj);
e3efda49 2050 }
62fdfeaf 2051
e3efda49
CW		 2052 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2053 if (ret)
2054 goto err_unref;
2055
1f767e02 2056 flags = 0;
c033666a 2057 if (!HAS_LLC(engine->i915))
1f767e02
CW		 2058 /* On g33, we cannot place HWS above 256MiB, so
2059 * restrict its pinning to the low mappable arena.
2060 * Though this restriction is not documented for
2061 * gen4, gen5, or byt, they also behave similarly
2062 * and hang if the HWS is placed at the top of the
2063 * GTT. To generalise, it appears that all !llc
2064 * platforms have issues with us placing the HWS
2065 * above the mappable region (even though we never
2066 * actualy map it).
2067 */
2068 flags |= PIN_MAPPABLE;
2069 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 2070 if (ret) {
2071err_unref:
2072 drm_gem_object_unreference(&obj->base);
2073 return ret;
2074 }
2075
0bc40be8 2076 engine->status_page.obj = obj;
e3efda49 2077 }
62fdfeaf 2078
0bc40be8
TU		 2079 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2080 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2081 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 2082
8187a2b7 2083 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
0bc40be8 2084 engine->name, engine->status_page.gfx_addr);
62fdfeaf
EA		 2085
2086 return 0;
62fdfeaf
EA		 2087}
2088
0bc40be8 2089static int init_phys_status_page(struct intel_engine_cs *engine)
6b8294a4 2090{
c033666a 2091 struct drm_i915_private *dev_priv = engine->i915;
6b8294a4
CW		 2092
2093 if (!dev_priv->status_page_dmah) {
2094 dev_priv->status_page_dmah =
c033666a 2095 drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
6b8294a4
CW		 2096 if (!dev_priv->status_page_dmah)
2097 return -ENOMEM;
2098 }
2099
0bc40be8
TU		 2100 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2101 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
6b8294a4
CW		 2102
2103 return 0;
2104}
2105
7ba717cf 2106void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 2107{
3d77e9be
CW		 2108 GEM_BUG_ON(ringbuf->vma == NULL);
2109 GEM_BUG_ON(ringbuf->virtual_start == NULL);
2110
def0c5f6 2111 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
0a798eb9 2112 i915_gem_object_unpin_map(ringbuf->obj);
def0c5f6 2113 else
3d77e9be 2114 i915_vma_unpin_iomap(ringbuf->vma);
8305216f 2115 ringbuf->virtual_start = NULL;
3d77e9be 2116
2919d291 2117 i915_gem_object_ggtt_unpin(ringbuf->obj);
3d77e9be 2118 ringbuf->vma = NULL;
7ba717cf
TD		 2119}
2120
c033666a 2121int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
7ba717cf
TD		 2122 struct intel_ringbuffer *ringbuf)
2123{
7ba717cf 2124 struct drm_i915_gem_object *obj = ringbuf->obj;
a687a43a
CW		 2125 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2126 unsigned flags = PIN_OFFSET_BIAS | 4096;
8305216f 2127 void *addr;
7ba717cf
TD		 2128 int ret;
2129
def0c5f6 2130 if (HAS_LLC(dev_priv) && !obj->stolen) {
a687a43a 2131 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
def0c5f6
CW		 2132 if (ret)
2133 return ret;
7ba717cf 2134
def0c5f6 2135 ret = i915_gem_object_set_to_cpu_domain(obj, true);
d2cad535
CW		 2136 if (ret)
2137 goto err_unpin;
def0c5f6 2138
8305216f
DG		 2139 addr = i915_gem_object_pin_map(obj);
2140 if (IS_ERR(addr)) {
2141 ret = PTR_ERR(addr);
d2cad535 2142 goto err_unpin;
def0c5f6
CW		 2143 }
2144 } else {
a687a43a
CW		 2145 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2146 flags | PIN_MAPPABLE);
def0c5f6
CW		 2147 if (ret)
2148 return ret;
7ba717cf 2149
def0c5f6 2150 ret = i915_gem_object_set_to_gtt_domain(obj, true);
d2cad535
CW		 2151 if (ret)
2152 goto err_unpin;
def0c5f6 2153
ff3dc087
DCS		 2154 /* Access through the GTT requires the device to be awake. */
2155 assert_rpm_wakelock_held(dev_priv);
2156
3d77e9be
CW		 2157 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2158 if (IS_ERR(addr)) {
2159 ret = PTR_ERR(addr);
d2cad535 2160 goto err_unpin;
def0c5f6 2161 }
7ba717cf
TD		 2162 }
2163
8305216f 2164 ringbuf->virtual_start = addr;
0eb973d3 2165 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
7ba717cf 2166 return 0;
d2cad535
CW		 2167
2168err_unpin:
2169 i915_gem_object_ggtt_unpin(obj);
2170 return ret;
7ba717cf
TD		 2171}
2172
01101fa7 2173static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2174{
2919d291
OM		 2175 drm_gem_object_unreference(&ringbuf->obj->base);
2176 ringbuf->obj = NULL;
2177}
2178
01101fa7
CW		 2179static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2180 struct intel_ringbuffer *ringbuf)
62fdfeaf 2181{
05394f39 2182 struct drm_i915_gem_object *obj;
62fdfeaf 2183
ebc052e0
CW		 2184 obj = NULL;
2185 if (!HAS_LLC(dev))
93b0a4e0 2186 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2187 if (obj == NULL)
d37cd8a8 2188 obj = i915_gem_object_create(dev, ringbuf->size);
fe3db79b
CW		 2189 if (IS_ERR(obj))
2190 return PTR_ERR(obj);
8187a2b7 2191
24f3a8cf
AG		 2192 /* mark ring buffers as read-only from GPU side by default */
2193 obj->gt_ro = 1;
2194
93b0a4e0 2195 ringbuf->obj = obj;
e3efda49 2196
7ba717cf 2197 return 0;
e3efda49
CW		 2198}
2199
01101fa7
CW		 2200struct intel_ringbuffer *
2201intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2202{
2203 struct intel_ringbuffer *ring;
2204 int ret;
2205
2206 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2207 if (ring == NULL) {
2208 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2209 engine->name);
01101fa7 2210 return ERR_PTR(-ENOMEM);
608c1a52 2211 }
01101fa7 2212
4a570db5 2213 ring->engine = engine;
608c1a52 2214 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2215
2216 ring->size = size;
2217 /* Workaround an erratum on the i830 which causes a hang if
2218 * the TAIL pointer points to within the last 2 cachelines
2219 * of the buffer.
2220 */
2221 ring->effective_size = size;
c033666a 2222 if (IS_I830(engine->i915) || IS_845G(engine->i915))
01101fa7
CW		 2223 ring->effective_size -= 2 * CACHELINE_BYTES;
2224
2225 ring->last_retired_head = -1;
2226 intel_ring_update_space(ring);
2227
c033666a 2228 ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
01101fa7 2229 if (ret) {
608c1a52
CW		 2230 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2231 engine->name, ret);
2232 list_del(&ring->link);
01101fa7
CW		 2233 kfree(ring);
2234 return ERR_PTR(ret);
2235 }
2236
2237 return ring;
2238}
2239
2240void
2241intel_ringbuffer_free(struct intel_ringbuffer *ring)
2242{
2243 intel_destroy_ringbuffer_obj(ring);
608c1a52 2244 list_del(&ring->link);
01101fa7
CW		 2245 kfree(ring);
2246}
2247
e3efda49 2248static int intel_init_ring_buffer(struct drm_device *dev,
0bc40be8 2249 struct intel_engine_cs *engine)
e3efda49 2250{
c033666a 2251 struct drm_i915_private *dev_priv = to_i915(dev);
bfc882b4 2252 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2253 int ret;
2254
0bc40be8 2255 WARN_ON(engine->buffer);
bfc882b4 2256
c033666a 2257 engine->i915 = dev_priv;
0bc40be8
TU		 2258 INIT_LIST_HEAD(&engine->active_list);
2259 INIT_LIST_HEAD(&engine->request_list);
2260 INIT_LIST_HEAD(&engine->execlist_queue);
2261 INIT_LIST_HEAD(&engine->buffers);
2262 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2263 memset(engine->semaphore.sync_seqno, 0,
2264 sizeof(engine->semaphore.sync_seqno));
e3efda49 2265
0bc40be8 2266 init_waitqueue_head(&engine->irq_queue);
e3efda49 2267
0bc40be8 2268 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
b0366a54
DG		 2269 if (IS_ERR(ringbuf)) {
2270 ret = PTR_ERR(ringbuf);
2271 goto error;
2272 }
0bc40be8 2273 engine->buffer = ringbuf;
01101fa7 2274
c033666a 2275 if (I915_NEED_GFX_HWS(dev_priv)) {
0bc40be8 2276 ret = init_status_page(engine);
e3efda49 2277 if (ret)
8ee14975 2278 goto error;
e3efda49 2279 } else {
0bc40be8
TU		 2280 WARN_ON(engine->id != RCS);
2281 ret = init_phys_status_page(engine);
e3efda49 2282 if (ret)
8ee14975 2283 goto error;
e3efda49
CW		 2284 }
2285
c033666a 2286 ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
bfc882b4
DV		 2287 if (ret) {
2288 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
0bc40be8 2289 engine->name, ret);
bfc882b4
DV		 2290 intel_destroy_ringbuffer_obj(ringbuf);
2291 goto error;
e3efda49 2292 }
62fdfeaf 2293
0bc40be8 2294 ret = i915_cmd_parser_init_ring(engine);
44e895a8 2295 if (ret)
8ee14975
OM		 2296 goto error;
2297
8ee14975 2298 return 0;
351e3db2 2299
8ee14975 2300error:
117897f4 2301 intel_cleanup_engine(engine);
8ee14975 2302 return ret;
62fdfeaf
EA		 2303}
2304
117897f4 2305void intel_cleanup_engine(struct intel_engine_cs *engine)
62fdfeaf 2306{
6402c330 2307 struct drm_i915_private *dev_priv;
33626e6a 2308
117897f4 2309 if (!intel_engine_initialized(engine))
62fdfeaf
EA		 2310 return;
2311
c033666a 2312 dev_priv = engine->i915;
6402c330 2313
0bc40be8 2314 if (engine->buffer) {
117897f4 2315 intel_stop_engine(engine);
c033666a 2316 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
33626e6a 2317
0bc40be8
TU		 2318 intel_unpin_ringbuffer_obj(engine->buffer);
2319 intel_ringbuffer_free(engine->buffer);
2320 engine->buffer = NULL;
b0366a54 2321 }
78501eac 2322
0bc40be8
TU		 2323 if (engine->cleanup)
2324 engine->cleanup(engine);
8d19215b 2325
c033666a 2326 if (I915_NEED_GFX_HWS(dev_priv)) {
0bc40be8 2327 cleanup_status_page(engine);
7d3fdfff 2328 } else {
0bc40be8
TU		 2329 WARN_ON(engine->id != RCS);
2330 cleanup_phys_status_page(engine);
7d3fdfff 2331 }
44e895a8 2332
0bc40be8
TU		 2333 i915_cmd_parser_fini_ring(engine);
2334 i915_gem_batch_pool_fini(&engine->batch_pool);
c033666a 2335 engine->i915 = NULL;
62fdfeaf
EA		 2336}
2337
666796da 2338int intel_engine_idle(struct intel_engine_cs *engine)
3e960501 2339{
a4b3a571 2340 struct drm_i915_gem_request *req;
3e960501 2341
3e960501 2342 /* Wait upon the last request to be completed */
0bc40be8 2343 if (list_empty(&engine->request_list))
3e960501
CW		 2344 return 0;
2345
0bc40be8
TU		 2346 req = list_entry(engine->request_list.prev,
2347 struct drm_i915_gem_request,
2348 list);
b4716185
CW		 2349
2350 /* Make sure we do not trigger any retires */
2351 return __i915_wait_request(req,
c19ae989 2352 req->i915->mm.interruptible,
b4716185 2353 NULL, NULL);
3e960501
CW		 2354}
2355
6689cb2b 2356int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2357{
6310346e
CW		 2358 int ret;
2359
2360 /* Flush enough space to reduce the likelihood of waiting after
2361 * we start building the request - in which case we will just
2362 * have to repeat work.
2363 */
a0442461 2364 request->reserved_space += LEGACY_REQUEST_SIZE;
6310346e 2365
4a570db5 2366 request->ringbuf = request->engine->buffer;
6310346e
CW		 2367
2368 ret = intel_ring_begin(request, 0);
2369 if (ret)
2370 return ret;
2371
a0442461 2372 request->reserved_space -= LEGACY_REQUEST_SIZE;
6310346e 2373 return 0;
9d773091
CW		 2374}
2375
987046ad
CW		 2376static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2377{
2378 struct intel_ringbuffer *ringbuf = req->ringbuf;
2379 struct intel_engine_cs *engine = req->engine;
2380 struct drm_i915_gem_request *target;
2381
2382 intel_ring_update_space(ringbuf);
2383 if (ringbuf->space >= bytes)
2384 return 0;
2385
2386 /*
2387 * Space is reserved in the ringbuffer for finalising the request,
2388 * as that cannot be allowed to fail. During request finalisation,
2389 * reserved_space is set to 0 to stop the overallocation and the
2390 * assumption is that then we never need to wait (which has the
2391 * risk of failing with EINTR).
2392 *
2393 * See also i915_gem_request_alloc() and i915_add_request().
2394 */
0251a963 2395 GEM_BUG_ON(!req->reserved_space);
987046ad
CW		 2396
2397 list_for_each_entry(target, &engine->request_list, list) {
2398 unsigned space;
2399
79bbcc29 2400 /*
987046ad
CW		 2401 * The request queue is per-engine, so can contain requests
2402 * from multiple ringbuffers. Here, we must ignore any that
2403 * aren't from the ringbuffer we're considering.
79bbcc29 2404 */
987046ad
CW		 2405 if (target->ringbuf != ringbuf)
2406 continue;
2407
2408 /* Would completion of this request free enough space? */
2409 space = __intel_ring_space(target->postfix, ringbuf->tail,
2410 ringbuf->size);
2411 if (space >= bytes)
2412 break;
79bbcc29 2413 }
29b1b415 2414
987046ad
CW		 2415 if (WARN_ON(&target->list == &engine->request_list))
2416 return -ENOSPC;
2417
2418 return i915_wait_request(target);
29b1b415
JH		 2419}
2420
987046ad 2421int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
cbcc80df 2422{
987046ad 2423 struct intel_ringbuffer *ringbuf = req->ringbuf;
79bbcc29 2424 int remain_actual = ringbuf->size - ringbuf->tail;
987046ad
CW		 2425 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2426 int bytes = num_dwords * sizeof(u32);
2427 int total_bytes, wait_bytes;
79bbcc29 2428 bool need_wrap = false;
29b1b415 2429
0251a963 2430 total_bytes = bytes + req->reserved_space;
29b1b415 2431
79bbcc29
JH		 2432 if (unlikely(bytes > remain_usable)) {
2433 /*
2434 * Not enough space for the basic request. So need to flush
2435 * out the remainder and then wait for base + reserved.
2436 */
2437 wait_bytes = remain_actual + total_bytes;
2438 need_wrap = true;
987046ad
CW		 2439 } else if (unlikely(total_bytes > remain_usable)) {
2440 /*
2441 * The base request will fit but the reserved space
2442 * falls off the end. So we don't need an immediate wrap
2443 * and only need to effectively wait for the reserved
2444 * size space from the start of ringbuffer.
2445 */
0251a963 2446 wait_bytes = remain_actual + req->reserved_space;
79bbcc29 2447 } else {
987046ad
CW		 2448 /* No wrapping required, just waiting. */
2449 wait_bytes = total_bytes;
cbcc80df
MK		 2450 }
2451
987046ad
CW		 2452 if (wait_bytes > ringbuf->space) {
2453 int ret = wait_for_space(req, wait_bytes);
cbcc80df
MK		 2454 if (unlikely(ret))
2455 return ret;
79bbcc29 2456
987046ad 2457 intel_ring_update_space(ringbuf);
e075a32f
CW		 2458 if (unlikely(ringbuf->space < wait_bytes))
2459 return -EAGAIN;
cbcc80df
MK		 2460 }
2461
987046ad
CW		 2462 if (unlikely(need_wrap)) {
2463 GEM_BUG_ON(remain_actual > ringbuf->space);
2464 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
78501eac 2465
987046ad
CW		 2466 /* Fill the tail with MI_NOOP */
2467 memset(ringbuf->virtual_start + ringbuf->tail,
2468 0, remain_actual);
2469 ringbuf->tail = 0;
2470 ringbuf->space -= remain_actual;
2471 }
304d695c 2472
987046ad
CW		 2473 ringbuf->space -= bytes;
2474 GEM_BUG_ON(ringbuf->space < 0);
304d695c 2475 return 0;
8187a2b7 2476}
78501eac 2477
753b1ad4 2478/* Align the ring tail to a cacheline boundary */
bba09b12 2479int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2480{
4a570db5 2481 struct intel_engine_cs *engine = req->engine;
e2f80391 2482 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2483 int ret;
2484
2485 if (num_dwords == 0)
2486 return 0;
2487
18393f63 2488 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2489 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2490 if (ret)
2491 return ret;
2492
2493 while (num_dwords--)
e2f80391 2494 intel_ring_emit(engine, MI_NOOP);
753b1ad4 2495
e2f80391 2496 intel_ring_advance(engine);
753b1ad4
VS		 2497
2498 return 0;
2499}
2500
0bc40be8 2501void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
498d2ac1 2502{
c033666a 2503 struct drm_i915_private *dev_priv = engine->i915;
498d2ac1 2504
29dcb570
CW		 2505 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2506 * so long as the semaphore value in the register/page is greater
2507 * than the sync value), so whenever we reset the seqno,
2508 * so long as we reset the tracking semaphore value to 0, it will
2509 * always be before the next request's seqno. If we don't reset
2510 * the semaphore value, then when the seqno moves backwards all
2511 * future waits will complete instantly (causing rendering corruption).
2512 */
7e22dbbb 2513 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
0bc40be8
TU		 2514 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2515 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
d04bce48 2516 if (HAS_VEBOX(dev_priv))
0bc40be8 2517 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
e1f99ce6 2518 }
a058d934
CW		 2519 if (dev_priv->semaphore_obj) {
2520 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2521 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2522 void *semaphores = kmap(page);
2523 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2524 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2525 kunmap(page);
2526 }
29dcb570
CW		 2527 memset(engine->semaphore.sync_seqno, 0,
2528 sizeof(engine->semaphore.sync_seqno));
d97ed339 2529
0bc40be8 2530 engine->set_seqno(engine, seqno);
01347126 2531 engine->last_submitted_seqno = seqno;
29dcb570 2532
0bc40be8 2533 engine->hangcheck.seqno = seqno;
8187a2b7 2534}
62fdfeaf 2535
0bc40be8 2536static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 2537 u32 value)
881f47b6 2538{
c033666a 2539 struct drm_i915_private *dev_priv = engine->i915;
881f47b6
XH		 2540
2541 /* Every tail move must follow the sequence below */
12f55818
CW		 2542
2543 /* Disable notification that the ring is IDLE. The GT
2544 * will then assume that it is busy and bring it out of rc6.
2545 */
0206e353 2546 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2547 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2548
2549 /* Clear the context id. Here be magic! */
2550 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2551
12f55818 2552 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2553 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2554 GEN6_BSD_SLEEP_INDICATOR) == 0,
2555 50))
2556 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2557
12f55818 2558 /* Now that the ring is fully powered up, update the tail */
0bc40be8
TU		 2559 I915_WRITE_TAIL(engine, value);
2560 POSTING_READ(RING_TAIL(engine->mmio_base));
12f55818
CW		 2561
2562 /* Let the ring send IDLE messages to the GT again,
2563 * and so let it sleep to conserve power when idle.
2564 */
0206e353 2565 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2566 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2567}
2568
a84c3ae1 2569static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2570 u32 invalidate, u32 flush)
881f47b6 2571{
4a570db5 2572 struct intel_engine_cs *engine = req->engine;
71a77e07 2573 uint32_t cmd;
b72f3acb
CW		 2574 int ret;
2575
5fb9de1a 2576 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2577 if (ret)
2578 return ret;
2579
71a77e07 2580 cmd = MI_FLUSH_DW;
c033666a 2581 if (INTEL_GEN(req->i915) >= 8)
075b3bba 2582 cmd += 1;
f0a1fb10
CW		 2583
2584 /* We always require a command barrier so that subsequent
2585 * commands, such as breadcrumb interrupts, are strictly ordered
2586 * wrt the contents of the write cache being flushed to memory
2587 * (and thus being coherent from the CPU).
2588 */
2589 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2590
9a289771
JB		 2591 /*
2592 * Bspec vol 1c.5 - video engine command streamer:
2593 * "If ENABLED, all TLBs will be invalidated once the flush
2594 * operation is complete. This bit is only valid when the
2595 * Post-Sync Operation field is a value of 1h or 3h."
2596 */
71a77e07 2597 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2598 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2599
e2f80391
TU		 2600 intel_ring_emit(engine, cmd);
2601 intel_ring_emit(engine,
2602 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
c033666a 2603 if (INTEL_GEN(req->i915) >= 8) {
e2f80391
TU		 2604 intel_ring_emit(engine, 0); /* upper addr */
2605 intel_ring_emit(engine, 0); /* value */
075b3bba 2606 } else {
e2f80391
TU		 2607 intel_ring_emit(engine, 0);
2608 intel_ring_emit(engine, MI_NOOP);
075b3bba 2609 }
e2f80391 2610 intel_ring_advance(engine);
b72f3acb 2611 return 0;
881f47b6
XH		 2612}
2613
1c7a0623 2614static int
53fddaf7 2615gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2616 u64 offset, u32 len,
8e004efc 2617 unsigned dispatch_flags)
1c7a0623 2618{
4a570db5 2619 struct intel_engine_cs *engine = req->engine;
e2f80391 2620 bool ppgtt = USES_PPGTT(engine->dev) &&
8e004efc 2621 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2622 int ret;
2623
5fb9de1a 2624 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2625 if (ret)
2626 return ret;
2627
2628 /* FIXME(BDW): Address space and security selectors. */
e2f80391 2629 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
919032ec
AJ		 2630 (dispatch_flags & I915_DISPATCH_RS ?
2631 MI_BATCH_RESOURCE_STREAMER : 0));
e2f80391
TU		 2632 intel_ring_emit(engine, lower_32_bits(offset));
2633 intel_ring_emit(engine, upper_32_bits(offset));
2634 intel_ring_emit(engine, MI_NOOP);
2635 intel_ring_advance(engine);
1c7a0623
BW		 2636
2637 return 0;
2638}
2639
d7d4eedd 2640static int
53fddaf7 2641hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2642 u64 offset, u32 len,
2643 unsigned dispatch_flags)
d7d4eedd 2644{
4a570db5 2645 struct intel_engine_cs *engine = req->engine;
d7d4eedd
CW		 2646 int ret;
2647
5fb9de1a 2648 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2649 if (ret)
2650 return ret;
2651
e2f80391 2652 intel_ring_emit(engine,
77072258 2653 MI_BATCH_BUFFER_START |
8e004efc 2654 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2655 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2656 (dispatch_flags & I915_DISPATCH_RS ?
2657 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd 2658 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2659 intel_ring_emit(engine, offset);
2660 intel_ring_advance(engine);
d7d4eedd
CW		 2661
2662 return 0;
2663}
2664
881f47b6 2665static int
53fddaf7 2666gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2667 u64 offset, u32 len,
8e004efc 2668 unsigned dispatch_flags)
881f47b6 2669{
4a570db5 2670 struct intel_engine_cs *engine = req->engine;
0206e353 2671 int ret;
ab6f8e32 2672
5fb9de1a 2673 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2674 if (ret)
2675 return ret;
e1f99ce6 2676
e2f80391 2677 intel_ring_emit(engine,
d7d4eedd 2678 MI_BATCH_BUFFER_START |
8e004efc
JH		 2679 (dispatch_flags & I915_DISPATCH_SECURE ?
2680 0 : MI_BATCH_NON_SECURE_I965));
0206e353 2681 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2682 intel_ring_emit(engine, offset);
2683 intel_ring_advance(engine);
ab6f8e32 2684
0206e353 2685 return 0;
881f47b6
XH		 2686}
2687
549f7365
CW		 2688/* Blitter support (SandyBridge+) */
2689
a84c3ae1 2690static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2691 u32 invalidate, u32 flush)
8d19215b 2692{
4a570db5 2693 struct intel_engine_cs *engine = req->engine;
71a77e07 2694 uint32_t cmd;
b72f3acb
CW		 2695 int ret;
2696
5fb9de1a 2697 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2698 if (ret)
2699 return ret;
2700
71a77e07 2701 cmd = MI_FLUSH_DW;
c033666a 2702 if (INTEL_GEN(req->i915) >= 8)
075b3bba 2703 cmd += 1;
f0a1fb10
CW		 2704
2705 /* We always require a command barrier so that subsequent
2706 * commands, such as breadcrumb interrupts, are strictly ordered
2707 * wrt the contents of the write cache being flushed to memory
2708 * (and thus being coherent from the CPU).
2709 */
2710 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2711
9a289771
JB		 2712 /*
2713 * Bspec vol 1c.3 - blitter engine command streamer:
2714 * "If ENABLED, all TLBs will be invalidated once the flush
2715 * operation is complete. This bit is only valid when the
2716 * Post-Sync Operation field is a value of 1h or 3h."
2717 */
71a77e07 2718 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2719 cmd |= MI_INVALIDATE_TLB;
e2f80391
TU		 2720 intel_ring_emit(engine, cmd);
2721 intel_ring_emit(engine,
2722 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
c033666a 2723 if (INTEL_GEN(req->i915) >= 8) {
e2f80391
TU		 2724 intel_ring_emit(engine, 0); /* upper addr */
2725 intel_ring_emit(engine, 0); /* value */
075b3bba 2726 } else {
e2f80391
TU		 2727 intel_ring_emit(engine, 0);
2728 intel_ring_emit(engine, MI_NOOP);
075b3bba 2729 }
e2f80391 2730 intel_ring_advance(engine);
fd3da6c9 2731
b72f3acb 2732 return 0;
8d19215b
ZN		 2733}
2734
5c1143bb
XH		 2735int intel_init_render_ring_buffer(struct drm_device *dev)
2736{
4640c4ff 2737 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2738 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
3e78998a
BW		 2739 struct drm_i915_gem_object *obj;
2740 int ret;
5c1143bb 2741
e2f80391
TU		 2742 engine->name = "render ring";
2743 engine->id = RCS;
2744 engine->exec_id = I915_EXEC_RENDER;
215a7e32 2745 engine->hw_id = 0;
e2f80391 2746 engine->mmio_base = RENDER_RING_BASE;
59465b5f 2747
c033666a
CW		 2748 if (INTEL_GEN(dev_priv) >= 8) {
2749 if (i915_semaphore_is_enabled(dev_priv)) {
d37cd8a8 2750 obj = i915_gem_object_create(dev, 4096);
fe3db79b 2751 if (IS_ERR(obj)) {
3e78998a
BW		 2752 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2753 i915.semaphores = 0;
2754 } else {
2755 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2756 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2757 if (ret != 0) {
2758 drm_gem_object_unreference(&obj->base);
2759 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2760 i915.semaphores = 0;
2761 } else
2762 dev_priv->semaphore_obj = obj;
2763 }
2764 }
7225342a 2765
e2f80391 2766 engine->init_context = intel_rcs_ctx_init;
a58c01aa 2767 engine->add_request = gen8_render_add_request;
e2f80391
TU		 2768 engine->flush = gen8_render_ring_flush;
2769 engine->irq_get = gen8_ring_get_irq;
2770 engine->irq_put = gen8_ring_put_irq;
2771 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b 2772 engine->get_seqno = ring_get_seqno;
e2f80391 2773 engine->set_seqno = ring_set_seqno;
c033666a 2774 if (i915_semaphore_is_enabled(dev_priv)) {
3e78998a 2775 WARN_ON(!dev_priv->semaphore_obj);
e2f80391
TU		 2776 engine->semaphore.sync_to = gen8_ring_sync;
2777 engine->semaphore.signal = gen8_rcs_signal;
2778 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2779 }
c033666a 2780 } else if (INTEL_GEN(dev_priv) >= 6) {
e2f80391
TU		 2781 engine->init_context = intel_rcs_ctx_init;
2782 engine->add_request = gen6_add_request;
2783 engine->flush = gen7_render_ring_flush;
c033666a 2784 if (IS_GEN6(dev_priv))
e2f80391
TU		 2785 engine->flush = gen6_render_ring_flush;
2786 engine->irq_get = gen6_ring_get_irq;
2787 engine->irq_put = gen6_ring_put_irq;
2788 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b
CW		 2789 engine->irq_seqno_barrier = gen6_seqno_barrier;
2790 engine->get_seqno = ring_get_seqno;
e2f80391 2791 engine->set_seqno = ring_set_seqno;
c033666a 2792 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2793 engine->semaphore.sync_to = gen6_ring_sync;
2794 engine->semaphore.signal = gen6_signal;
707d9cf9
BW		 2795 /*
2796 * The current semaphore is only applied on pre-gen8
2797 * platform. And there is no VCS2 ring on the pre-gen8
2798 * platform. So the semaphore between RCS and VCS2 is
2799 * initialized as INVALID. Gen8 will initialize the
2800 * sema between VCS2 and RCS later.
2801 */
e2f80391
TU		 2802 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2803 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2804 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2805 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2806 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2807 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2808 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2809 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2810 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2811 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2812 }
c033666a 2813 } else if (IS_GEN5(dev_priv)) {
e2f80391
TU		 2814 engine->add_request = pc_render_add_request;
2815 engine->flush = gen4_render_ring_flush;
2816 engine->get_seqno = pc_render_get_seqno;
2817 engine->set_seqno = pc_render_set_seqno;
2818 engine->irq_get = gen5_ring_get_irq;
2819 engine->irq_put = gen5_ring_put_irq;
2820 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
cc609d5d 2821 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2822 } else {
e2f80391 2823 engine->add_request = i9xx_add_request;
c033666a 2824 if (INTEL_GEN(dev_priv) < 4)
e2f80391 2825 engine->flush = gen2_render_ring_flush;
46f0f8d1 2826 else
e2f80391
TU		 2827 engine->flush = gen4_render_ring_flush;
2828 engine->get_seqno = ring_get_seqno;
2829 engine->set_seqno = ring_set_seqno;
c033666a 2830 if (IS_GEN2(dev_priv)) {
e2f80391
TU		 2831 engine->irq_get = i8xx_ring_get_irq;
2832 engine->irq_put = i8xx_ring_put_irq;
c2798b19 2833 } else {
e2f80391
TU		 2834 engine->irq_get = i9xx_ring_get_irq;
2835 engine->irq_put = i9xx_ring_put_irq;
c2798b19 2836 }
e2f80391 2837 engine->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2838 }
e2f80391 2839 engine->write_tail = ring_write_tail;
707d9cf9 2840
c033666a 2841 if (IS_HASWELL(dev_priv))
e2f80391 2842 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
c033666a 2843 else if (IS_GEN8(dev_priv))
e2f80391 2844 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 2845 else if (INTEL_GEN(dev_priv) >= 6)
e2f80391 2846 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 2847 else if (INTEL_GEN(dev_priv) >= 4)
e2f80391 2848 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
c033666a 2849 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
e2f80391 2850 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
fb3256da 2851 else
e2f80391
TU		 2852 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2853 engine->init_hw = init_render_ring;
2854 engine->cleanup = render_ring_cleanup;
59465b5f 2855
b45305fc 2856 /* Workaround batchbuffer to combat CS tlb bug. */
c033666a 2857 if (HAS_BROKEN_CS_TLB(dev_priv)) {
d37cd8a8 2858 obj = i915_gem_object_create(dev, I830_WA_SIZE);
fe3db79b 2859 if (IS_ERR(obj)) {
b45305fc 2860 DRM_ERROR("Failed to allocate batch bo\n");
fe3db79b 2861 return PTR_ERR(obj);
b45305fc
DV		 2862 }
2863
be1fa129 2864 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2865 if (ret != 0) {
2866 drm_gem_object_unreference(&obj->base);
2867 DRM_ERROR("Failed to ping batch bo\n");
2868 return ret;
2869 }
2870
e2f80391
TU		 2871 engine->scratch.obj = obj;
2872 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2873 }
2874
e2f80391 2875 ret = intel_init_ring_buffer(dev, engine);
99be1dfe
DV		 2876 if (ret)
2877 return ret;
2878
c033666a 2879 if (INTEL_GEN(dev_priv) >= 5) {
e2f80391 2880 ret = intel_init_pipe_control(engine);
99be1dfe
DV		 2881 if (ret)
2882 return ret;
2883 }
2884
2885 return 0;
5c1143bb
XH		 2886}
2887
2888int intel_init_bsd_ring_buffer(struct drm_device *dev)
2889{
4640c4ff 2890 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2891 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
5c1143bb 2892
e2f80391
TU		 2893 engine->name = "bsd ring";
2894 engine->id = VCS;
2895 engine->exec_id = I915_EXEC_BSD;
215a7e32 2896 engine->hw_id = 1;
58fa3835 2897
e2f80391 2898 engine->write_tail = ring_write_tail;
c033666a 2899 if (INTEL_GEN(dev_priv) >= 6) {
e2f80391 2900 engine->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201 2901 /* gen6 bsd needs a special wa for tail updates */
c033666a 2902 if (IS_GEN6(dev_priv))
e2f80391
TU		 2903 engine->write_tail = gen6_bsd_ring_write_tail;
2904 engine->flush = gen6_bsd_ring_flush;
2905 engine->add_request = gen6_add_request;
c04e0f3b
CW		 2906 engine->irq_seqno_barrier = gen6_seqno_barrier;
2907 engine->get_seqno = ring_get_seqno;
e2f80391 2908 engine->set_seqno = ring_set_seqno;
c033666a 2909 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 2910 engine->irq_enable_mask =
abd58f01 2911 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
e2f80391
TU		 2912 engine->irq_get = gen8_ring_get_irq;
2913 engine->irq_put = gen8_ring_put_irq;
2914 engine->dispatch_execbuffer =
1c7a0623 2915 gen8_ring_dispatch_execbuffer;
c033666a 2916 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2917 engine->semaphore.sync_to = gen8_ring_sync;
2918 engine->semaphore.signal = gen8_xcs_signal;
2919 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2920 }
abd58f01 2921 } else {
e2f80391
TU		 2922 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2923 engine->irq_get = gen6_ring_get_irq;
2924 engine->irq_put = gen6_ring_put_irq;
2925 engine->dispatch_execbuffer =
1c7a0623 2926 gen6_ring_dispatch_execbuffer;
c033666a 2927 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2928 engine->semaphore.sync_to = gen6_ring_sync;
2929 engine->semaphore.signal = gen6_signal;
2930 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2931 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2932 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2933 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2934 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2935 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2936 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2937 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2938 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2939 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2940 }
abd58f01 2941 }
58fa3835 2942 } else {
e2f80391
TU		 2943 engine->mmio_base = BSD_RING_BASE;
2944 engine->flush = bsd_ring_flush;
2945 engine->add_request = i9xx_add_request;
2946 engine->get_seqno = ring_get_seqno;
2947 engine->set_seqno = ring_set_seqno;
c033666a 2948 if (IS_GEN5(dev_priv)) {
e2f80391
TU		 2949 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2950 engine->irq_get = gen5_ring_get_irq;
2951 engine->irq_put = gen5_ring_put_irq;
e48d8634 2952 } else {
e2f80391
TU		 2953 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2954 engine->irq_get = i9xx_ring_get_irq;
2955 engine->irq_put = i9xx_ring_put_irq;
e48d8634 2956 }
e2f80391 2957 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2958 }
e2f80391 2959 engine->init_hw = init_ring_common;
58fa3835 2960
e2f80391 2961 return intel_init_ring_buffer(dev, engine);
5c1143bb 2962}
549f7365 2963
845f74a7 2964/**
62659920 2965 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2966 */
2967int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2968{
2969 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2970 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
e2f80391
TU		 2971
2972 engine->name = "bsd2 ring";
2973 engine->id = VCS2;
2974 engine->exec_id = I915_EXEC_BSD;
215a7e32 2975 engine->hw_id = 4;
e2f80391
TU		 2976
2977 engine->write_tail = ring_write_tail;
2978 engine->mmio_base = GEN8_BSD2_RING_BASE;
2979 engine->flush = gen6_bsd_ring_flush;
2980 engine->add_request = gen6_add_request;
c04e0f3b
CW		 2981 engine->irq_seqno_barrier = gen6_seqno_barrier;
2982 engine->get_seqno = ring_get_seqno;
e2f80391
TU		 2983 engine->set_seqno = ring_set_seqno;
2984 engine->irq_enable_mask =
845f74a7 2985 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
e2f80391
TU		 2986 engine->irq_get = gen8_ring_get_irq;
2987 engine->irq_put = gen8_ring_put_irq;
2988 engine->dispatch_execbuffer =
845f74a7 2989 gen8_ring_dispatch_execbuffer;
c033666a 2990 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2991 engine->semaphore.sync_to = gen8_ring_sync;
2992 engine->semaphore.signal = gen8_xcs_signal;
2993 GEN8_RING_SEMAPHORE_INIT(engine);
3e78998a 2994 }
e2f80391 2995 engine->init_hw = init_ring_common;
845f74a7 2996
e2f80391 2997 return intel_init_ring_buffer(dev, engine);
845f74a7
ZY		 2998}
2999
549f7365
CW		 3000int intel_init_blt_ring_buffer(struct drm_device *dev)
3001{
4640c4ff 3002 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3003 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
e2f80391
TU		 3004
3005 engine->name = "blitter ring";
3006 engine->id = BCS;
3007 engine->exec_id = I915_EXEC_BLT;
215a7e32 3008 engine->hw_id = 2;
e2f80391
TU		 3009
3010 engine->mmio_base = BLT_RING_BASE;
3011 engine->write_tail = ring_write_tail;
3012 engine->flush = gen6_ring_flush;
3013 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3014 engine->irq_seqno_barrier = gen6_seqno_barrier;
3015 engine->get_seqno = ring_get_seqno;
e2f80391 3016 engine->set_seqno = ring_set_seqno;
c033666a 3017 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 3018 engine->irq_enable_mask =
abd58f01 3019 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
e2f80391
TU		 3020 engine->irq_get = gen8_ring_get_irq;
3021 engine->irq_put = gen8_ring_put_irq;
3022 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 3023 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3024 engine->semaphore.sync_to = gen8_ring_sync;
3025 engine->semaphore.signal = gen8_xcs_signal;
3026 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3027 }
abd58f01 3028 } else {
e2f80391
TU		 3029 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3030 engine->irq_get = gen6_ring_get_irq;
3031 engine->irq_put = gen6_ring_put_irq;
3032 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 3033 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3034 engine->semaphore.signal = gen6_signal;
3035 engine->semaphore.sync_to = gen6_ring_sync;
707d9cf9
BW		 3036 /*
3037 * The current semaphore is only applied on pre-gen8
3038 * platform. And there is no VCS2 ring on the pre-gen8
3039 * platform. So the semaphore between BCS and VCS2 is
3040 * initialized as INVALID. Gen8 will initialize the
3041 * sema between BCS and VCS2 later.
3042 */
e2f80391
TU		 3043 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3044 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3045 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3046 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3047 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3048 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3049 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3050 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3051 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3052 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3053 }
abd58f01 3054 }
e2f80391 3055 engine->init_hw = init_ring_common;
549f7365 3056
e2f80391 3057 return intel_init_ring_buffer(dev, engine);
549f7365 3058}
a7b9761d 3059
9a8a2213
BW		 3060int intel_init_vebox_ring_buffer(struct drm_device *dev)
3061{
4640c4ff 3062 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3063 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
9a8a2213 3064
e2f80391
TU		 3065 engine->name = "video enhancement ring";
3066 engine->id = VECS;
3067 engine->exec_id = I915_EXEC_VEBOX;
215a7e32 3068 engine->hw_id = 3;
9a8a2213 3069
e2f80391
TU		 3070 engine->mmio_base = VEBOX_RING_BASE;
3071 engine->write_tail = ring_write_tail;
3072 engine->flush = gen6_ring_flush;
3073 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3074 engine->irq_seqno_barrier = gen6_seqno_barrier;
3075 engine->get_seqno = ring_get_seqno;
e2f80391 3076 engine->set_seqno = ring_set_seqno;
abd58f01 3077
c033666a 3078 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 3079 engine->irq_enable_mask =
40c499f9 3080 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
e2f80391
TU		 3081 engine->irq_get = gen8_ring_get_irq;
3082 engine->irq_put = gen8_ring_put_irq;
3083 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 3084 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3085 engine->semaphore.sync_to = gen8_ring_sync;
3086 engine->semaphore.signal = gen8_xcs_signal;
3087 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3088 }
abd58f01 3089 } else {
e2f80391
TU		 3090 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3091 engine->irq_get = hsw_vebox_get_irq;
3092 engine->irq_put = hsw_vebox_put_irq;
3093 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 3094 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3095 engine->semaphore.sync_to = gen6_ring_sync;
3096 engine->semaphore.signal = gen6_signal;
3097 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3098 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3099 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3100 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3101 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3102 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3103 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3104 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3105 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3106 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3107 }
abd58f01 3108 }
e2f80391 3109 engine->init_hw = init_ring_common;
9a8a2213 3110
e2f80391 3111 return intel_init_ring_buffer(dev, engine);
9a8a2213
BW		 3112}
3113
a7b9761d 3114int
4866d729 3115intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3116{
4a570db5 3117 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3118 int ret;
3119
e2f80391 3120 if (!engine->gpu_caches_dirty)
a7b9761d
CW		 3121 return 0;
3122
e2f80391 3123 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3124 if (ret)
3125 return ret;
3126
a84c3ae1 3127 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d 3128
e2f80391 3129 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3130 return 0;
3131}
3132
3133int
2f20055d 3134intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3135{
4a570db5 3136 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3137 uint32_t flush_domains;
3138 int ret;
3139
3140 flush_domains = 0;
e2f80391 3141 if (engine->gpu_caches_dirty)
a7b9761d
CW		 3142 flush_domains = I915_GEM_GPU_DOMAINS;
3143
e2f80391 3144 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3145 if (ret)
3146 return ret;
3147
a84c3ae1 3148 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d 3149
e2f80391 3150 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3151 return 0;
3152}
e3efda49
CW		 3153
3154void
117897f4 3155intel_stop_engine(struct intel_engine_cs *engine)
e3efda49
CW		 3156{
3157 int ret;
3158
117897f4 3159 if (!intel_engine_initialized(engine))
e3efda49
CW		 3160 return;
3161
666796da 3162 ret = intel_engine_idle(engine);
f4457ae7 3163 if (ret)
e3efda49 3164 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
0bc40be8 3165 engine->name, ret);
e3efda49 3166
0bc40be8 3167 stop_ring(engine);
e3efda49 3168}
Linux kernel - Deliverables
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