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drm/i915: remove do_retire from i915_wait_request
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
62fdfeaf 32#include "i915_drv.h"
8187a2b7 33#include "i915_drm.h"
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
8d315287
JB		 37/*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45};
46
c7dca47b
CW		 47static inline int ring_space(struct intel_ring_buffer *ring)
48{
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53}
54
b72f3acb 55static int
46f0f8d1
CW		 56gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59{
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
31b14c9f 64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79}
80
81static int
82gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
62fdfeaf 85{
78501eac 86 struct drm_device *dev = ring->dev;
6f392d54 87 u32 cmd;
b72f3acb 88 int ret;
6f392d54 89
36d527de
CW		 90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 120 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
62fdfeaf 123
36d527de
CW		 124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
70eac33e 127
36d527de
CW		 128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
b72f3acb 131
36d527de
CW		 132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
b72f3acb
CW		 135
136 return 0;
8187a2b7
ZN		 137}
138
8d315287
JB		 139/**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176static int
177intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178{
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210}
211
212static int
213gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215{
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
235
236 ret = intel_ring_begin(ring, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, flags);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
243 intel_ring_emit(ring, 0); /* lower dword */
244 intel_ring_emit(ring, 0); /* uppwer dword */
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
78501eac 251static void ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 252 u32 value)
d46eefa2 253{
78501eac 254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
297b0c5b 255 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 256}
257
78501eac 258u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
8187a2b7 259{
78501eac
CW		 260 drm_i915_private_t *dev_priv = ring->dev->dev_private;
261 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
3d281d8c 262 RING_ACTHD(ring->mmio_base) : ACTHD;
8187a2b7
ZN		 263
264 return I915_READ(acthd_reg);
265}
266
78501eac 267static int init_ring_common(struct intel_ring_buffer *ring)
8187a2b7 268{
78501eac 269 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 270 struct drm_i915_gem_object *obj = ring->obj;
8187a2b7 271 u32 head;
8187a2b7
ZN		 272
273 /* Stop the ring if it's running. */
7f2ab699 274 I915_WRITE_CTL(ring, 0);
570ef608 275 I915_WRITE_HEAD(ring, 0);
78501eac 276 ring->write_tail(ring, 0);
8187a2b7
ZN		 277
278 /* Initialize the ring. */
05394f39 279 I915_WRITE_START(ring, obj->gtt_offset);
570ef608 280 head = I915_READ_HEAD(ring) & HEAD_ADDR;
8187a2b7
ZN		 281
282 /* G45 ring initialization fails to reset head to zero */
283 if (head != 0) {
6fd0d56e
CW		 284 DRM_DEBUG_KMS("%s head not reset to zero "
285 "ctl %08x head %08x tail %08x start %08x\n",
286 ring->name,
287 I915_READ_CTL(ring),
288 I915_READ_HEAD(ring),
289 I915_READ_TAIL(ring),
290 I915_READ_START(ring));
8187a2b7 291
570ef608 292 I915_WRITE_HEAD(ring, 0);
8187a2b7 293
6fd0d56e
CW		 294 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
295 DRM_ERROR("failed to set %s head to zero "
296 "ctl %08x head %08x tail %08x start %08x\n",
297 ring->name,
298 I915_READ_CTL(ring),
299 I915_READ_HEAD(ring),
300 I915_READ_TAIL(ring),
301 I915_READ_START(ring));
302 }
8187a2b7
ZN		 303 }
304
7f2ab699 305 I915_WRITE_CTL(ring,
ae69b42a 306 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 307 | RING_VALID);
8187a2b7 308
8187a2b7 309 /* If the head is still not zero, the ring is dead */
f01db988
SP		 310 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
311 I915_READ_START(ring) == obj->gtt_offset &&
312 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5
CW		 313 DRM_ERROR("%s initialization failed "
314 "ctl %08x head %08x tail %08x start %08x\n",
315 ring->name,
316 I915_READ_CTL(ring),
317 I915_READ_HEAD(ring),
318 I915_READ_TAIL(ring),
319 I915_READ_START(ring));
320 return -EIO;
8187a2b7
ZN		 321 }
322
78501eac
CW		 323 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
324 i915_kernel_lost_context(ring->dev);
8187a2b7 325 else {
c7dca47b 326 ring->head = I915_READ_HEAD(ring);
870e86dd 327 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
c7dca47b 328 ring->space = ring_space(ring);
8187a2b7 329 }
1ec14ad3 330
8187a2b7
ZN		 331 return 0;
332}
333
c6df541c
CW		 334static int
335init_pipe_control(struct intel_ring_buffer *ring)
336{
337 struct pipe_control *pc;
338 struct drm_i915_gem_object *obj;
339 int ret;
340
341 if (ring->private)
342 return 0;
343
344 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
345 if (!pc)
346 return -ENOMEM;
347
348 obj = i915_gem_alloc_object(ring->dev, 4096);
349 if (obj == NULL) {
350 DRM_ERROR("Failed to allocate seqno page\n");
351 ret = -ENOMEM;
352 goto err;
353 }
e4ffd173
CW		 354
355 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
c6df541c
CW		 356
357 ret = i915_gem_object_pin(obj, 4096, true);
358 if (ret)
359 goto err_unref;
360
361 pc->gtt_offset = obj->gtt_offset;
362 pc->cpu_page = kmap(obj->pages[0]);
363 if (pc->cpu_page == NULL)
364 goto err_unpin;
365
366 pc->obj = obj;
367 ring->private = pc;
368 return 0;
369
370err_unpin:
371 i915_gem_object_unpin(obj);
372err_unref:
373 drm_gem_object_unreference(&obj->base);
374err:
375 kfree(pc);
376 return ret;
377}
378
379static void
380cleanup_pipe_control(struct intel_ring_buffer *ring)
381{
382 struct pipe_control *pc = ring->private;
383 struct drm_i915_gem_object *obj;
384
385 if (!ring->private)
386 return;
387
388 obj = pc->obj;
389 kunmap(obj->pages[0]);
390 i915_gem_object_unpin(obj);
391 drm_gem_object_unreference(&obj->base);
392
393 kfree(pc);
394 ring->private = NULL;
395}
396
78501eac 397static int init_render_ring(struct intel_ring_buffer *ring)
8187a2b7 398{
78501eac 399 struct drm_device *dev = ring->dev;
1ec14ad3 400 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 401 int ret = init_ring_common(ring);
a69ffdbf 402
a6c45cf0 403 if (INTEL_INFO(dev)->gen > 3) {
6b26c86d 404 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
b095cd0a
JB		 405 if (IS_GEN7(dev))
406 I915_WRITE(GFX_MODE_GEN7,
6b26c86d
DV		 407 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
408 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
8187a2b7 409 }
78501eac 410
8d315287 411 if (INTEL_INFO(dev)->gen >= 5) {
c6df541c
CW		 412 ret = init_pipe_control(ring);
413 if (ret)
414 return ret;
415 }
416
6b26c86d
DV		 417 if (INTEL_INFO(dev)->gen >= 6)
418 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 419
8187a2b7
ZN		 420 return ret;
421}
422
c6df541c
CW		 423static void render_ring_cleanup(struct intel_ring_buffer *ring)
424{
425 if (!ring->private)
426 return;
427
428 cleanup_pipe_control(ring);
429}
430
1ec14ad3 431static void
c8c99b0f
BW		 432update_mboxes(struct intel_ring_buffer *ring,
433 u32 seqno,
434 u32 mmio_offset)
1ec14ad3 435{
c8c99b0f
BW		 436 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
437 MI_SEMAPHORE_GLOBAL_GTT |
438 MI_SEMAPHORE_REGISTER |
439 MI_SEMAPHORE_UPDATE);
1ec14ad3 440 intel_ring_emit(ring, seqno);
c8c99b0f 441 intel_ring_emit(ring, mmio_offset);
1ec14ad3
CW		 442}
443
c8c99b0f
BW		 444/**
445 * gen6_add_request - Update the semaphore mailbox registers
446 *
447 * @ring - ring that is adding a request
448 * @seqno - return seqno stuck into the ring
449 *
450 * Update the mailbox registers in the *other* rings with the current seqno.
451 * This acts like a signal in the canonical semaphore.
452 */
1ec14ad3
CW		 453static int
454gen6_add_request(struct intel_ring_buffer *ring,
c8c99b0f 455 u32 *seqno)
1ec14ad3 456{
c8c99b0f
BW		 457 u32 mbox1_reg;
458 u32 mbox2_reg;
1ec14ad3
CW		 459 int ret;
460
461 ret = intel_ring_begin(ring, 10);
462 if (ret)
463 return ret;
464
c8c99b0f
BW		 465 mbox1_reg = ring->signal_mbox[0];
466 mbox2_reg = ring->signal_mbox[1];
1ec14ad3 467
53d227f2 468 *seqno = i915_gem_next_request_seqno(ring);
c8c99b0f
BW		 469
470 update_mboxes(ring, *seqno, mbox1_reg);
471 update_mboxes(ring, *seqno, mbox2_reg);
1ec14ad3
CW		 472 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
473 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
c8c99b0f 474 intel_ring_emit(ring, *seqno);
1ec14ad3
CW		 475 intel_ring_emit(ring, MI_USER_INTERRUPT);
476 intel_ring_advance(ring);
477
1ec14ad3
CW		 478 return 0;
479}
480
c8c99b0f
BW		 481/**
482 * intel_ring_sync - sync the waiter to the signaller on seqno
483 *
484 * @waiter - ring that is waiting
485 * @signaller - ring which has, or will signal
486 * @seqno - seqno which the waiter will block on
487 */
488static int
686cb5f9
DV		 489gen6_ring_sync(struct intel_ring_buffer *waiter,
490 struct intel_ring_buffer *signaller,
491 u32 seqno)
1ec14ad3
CW		 492{
493 int ret;
c8c99b0f
BW		 494 u32 dw1 = MI_SEMAPHORE_MBOX |
495 MI_SEMAPHORE_COMPARE |
496 MI_SEMAPHORE_REGISTER;
1ec14ad3 497
1500f7ea
BW		 498 /* Throughout all of the GEM code, seqno passed implies our current
499 * seqno is >= the last seqno executed. However for hardware the
500 * comparison is strictly greater than.
501 */
502 seqno -= 1;
503
686cb5f9
DV		 504 WARN_ON(signaller->semaphore_register[waiter->id] ==
505 MI_SEMAPHORE_SYNC_INVALID);
506
c8c99b0f 507 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 508 if (ret)
509 return ret;
510
686cb5f9
DV		 511 intel_ring_emit(waiter,
512 dw1 | signaller->semaphore_register[waiter->id]);
c8c99b0f
BW		 513 intel_ring_emit(waiter, seqno);
514 intel_ring_emit(waiter, 0);
515 intel_ring_emit(waiter, MI_NOOP);
516 intel_ring_advance(waiter);
1ec14ad3
CW		 517
518 return 0;
519}
520
c6df541c
CW		 521#define PIPE_CONTROL_FLUSH(ring__, addr__) \
522do { \
fcbc34e4
KG		 523 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
524 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 525 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
526 intel_ring_emit(ring__, 0); \
527 intel_ring_emit(ring__, 0); \
528} while (0)
529
530static int
531pc_render_add_request(struct intel_ring_buffer *ring,
532 u32 *result)
533{
53d227f2 534 u32 seqno = i915_gem_next_request_seqno(ring);
c6df541c
CW		 535 struct pipe_control *pc = ring->private;
536 u32 scratch_addr = pc->gtt_offset + 128;
537 int ret;
538
539 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
540 * incoherent with writes to memory, i.e. completely fubar,
541 * so we need to use PIPE_NOTIFY instead.
542 *
543 * However, we also need to workaround the qword write
544 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
545 * memory before requesting an interrupt.
546 */
547 ret = intel_ring_begin(ring, 32);
548 if (ret)
549 return ret;
550
fcbc34e4 551 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 552 PIPE_CONTROL_WRITE_FLUSH |
553 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
c6df541c
CW		 554 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
555 intel_ring_emit(ring, seqno);
556 intel_ring_emit(ring, 0);
557 PIPE_CONTROL_FLUSH(ring, scratch_addr);
558 scratch_addr += 128; /* write to separate cachelines */
559 PIPE_CONTROL_FLUSH(ring, scratch_addr);
560 scratch_addr += 128;
561 PIPE_CONTROL_FLUSH(ring, scratch_addr);
562 scratch_addr += 128;
563 PIPE_CONTROL_FLUSH(ring, scratch_addr);
564 scratch_addr += 128;
565 PIPE_CONTROL_FLUSH(ring, scratch_addr);
566 scratch_addr += 128;
567 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 568
fcbc34e4 569 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 570 PIPE_CONTROL_WRITE_FLUSH |
571 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c
CW		 572 PIPE_CONTROL_NOTIFY);
573 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
574 intel_ring_emit(ring, seqno);
575 intel_ring_emit(ring, 0);
576 intel_ring_advance(ring);
577
578 *result = seqno;
579 return 0;
580}
581
4cd53c0c
DV		 582static u32
583gen6_ring_get_seqno(struct intel_ring_buffer *ring)
584{
585 struct drm_device *dev = ring->dev;
586
587 /* Workaround to force correct ordering between irq and seqno writes on
588 * ivb (and maybe also on snb) by reading from a CS register (like
589 * ACTHD) before reading the status page. */
1c7eaac7 590 if (IS_GEN6(dev) || IS_GEN7(dev))
4cd53c0c
DV		 591 intel_ring_get_active_head(ring);
592 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
593}
594
8187a2b7 595static u32
1ec14ad3 596ring_get_seqno(struct intel_ring_buffer *ring)
8187a2b7 597{
1ec14ad3
CW		 598 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
599}
600
c6df541c
CW		 601static u32
602pc_render_get_seqno(struct intel_ring_buffer *ring)
603{
604 struct pipe_control *pc = ring->private;
605 return pc->cpu_page[0];
606}
607
e48d8634
DV		 608static bool
609gen5_ring_get_irq(struct intel_ring_buffer *ring)
610{
611 struct drm_device *dev = ring->dev;
612 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 613 unsigned long flags;
e48d8634
DV		 614
615 if (!dev->irq_enabled)
616 return false;
617
7338aefa 618 spin_lock_irqsave(&dev_priv->irq_lock, flags);
f637fde4
DV		 619 if (ring->irq_refcount++ == 0) {
620 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
621 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
622 POSTING_READ(GTIMR);
623 }
7338aefa 624 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 625
626 return true;
627}
628
629static void
630gen5_ring_put_irq(struct intel_ring_buffer *ring)
631{
632 struct drm_device *dev = ring->dev;
633 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 634 unsigned long flags;
e48d8634 635
7338aefa 636 spin_lock_irqsave(&dev_priv->irq_lock, flags);
f637fde4
DV		 637 if (--ring->irq_refcount == 0) {
638 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
639 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
640 POSTING_READ(GTIMR);
641 }
7338aefa 642 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 643}
644
b13c2b96 645static bool
e3670319 646i9xx_ring_get_irq(struct intel_ring_buffer *ring)
62fdfeaf 647{
78501eac 648 struct drm_device *dev = ring->dev;
01a03331 649 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 650 unsigned long flags;
62fdfeaf 651
b13c2b96
CW		 652 if (!dev->irq_enabled)
653 return false;
654
7338aefa 655 spin_lock_irqsave(&dev_priv->irq_lock, flags);
f637fde4
DV		 656 if (ring->irq_refcount++ == 0) {
657 dev_priv->irq_mask &= ~ring->irq_enable_mask;
658 I915_WRITE(IMR, dev_priv->irq_mask);
659 POSTING_READ(IMR);
660 }
7338aefa 661 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 662
663 return true;
62fdfeaf
EA		 664}
665
8187a2b7 666static void
e3670319 667i9xx_ring_put_irq(struct intel_ring_buffer *ring)
62fdfeaf 668{
78501eac 669 struct drm_device *dev = ring->dev;
01a03331 670 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 671 unsigned long flags;
62fdfeaf 672
7338aefa 673 spin_lock_irqsave(&dev_priv->irq_lock, flags);
f637fde4
DV		 674 if (--ring->irq_refcount == 0) {
675 dev_priv->irq_mask |= ring->irq_enable_mask;
676 I915_WRITE(IMR, dev_priv->irq_mask);
677 POSTING_READ(IMR);
678 }
7338aefa 679 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 680}
681
c2798b19
CW		 682static bool
683i8xx_ring_get_irq(struct intel_ring_buffer *ring)
684{
685 struct drm_device *dev = ring->dev;
686 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 687 unsigned long flags;
c2798b19
CW		 688
689 if (!dev->irq_enabled)
690 return false;
691
7338aefa 692 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c2798b19
CW		 693 if (ring->irq_refcount++ == 0) {
694 dev_priv->irq_mask &= ~ring->irq_enable_mask;
695 I915_WRITE16(IMR, dev_priv->irq_mask);
696 POSTING_READ16(IMR);
697 }
7338aefa 698 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 699
700 return true;
701}
702
703static void
704i8xx_ring_put_irq(struct intel_ring_buffer *ring)
705{
706 struct drm_device *dev = ring->dev;
707 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 708 unsigned long flags;
c2798b19 709
7338aefa 710 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c2798b19
CW		 711 if (--ring->irq_refcount == 0) {
712 dev_priv->irq_mask |= ring->irq_enable_mask;
713 I915_WRITE16(IMR, dev_priv->irq_mask);
714 POSTING_READ16(IMR);
715 }
7338aefa 716 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 717}
718
78501eac 719void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
8187a2b7 720{
4593010b 721 struct drm_device *dev = ring->dev;
78501eac 722 drm_i915_private_t *dev_priv = ring->dev->dev_private;
4593010b
EA		 723 u32 mmio = 0;
724
725 /* The ring status page addresses are no longer next to the rest of
726 * the ring registers as of gen7.
727 */
728 if (IS_GEN7(dev)) {
729 switch (ring->id) {
96154f2f 730 case RCS:
4593010b
EA		 731 mmio = RENDER_HWS_PGA_GEN7;
732 break;
96154f2f 733 case BCS:
4593010b
EA		 734 mmio = BLT_HWS_PGA_GEN7;
735 break;
96154f2f 736 case VCS:
4593010b
EA		 737 mmio = BSD_HWS_PGA_GEN7;
738 break;
739 }
740 } else if (IS_GEN6(ring->dev)) {
741 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
742 } else {
743 mmio = RING_HWS_PGA(ring->mmio_base);
744 }
745
78501eac
CW		 746 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
747 POSTING_READ(mmio);
8187a2b7
ZN		 748}
749
b72f3acb 750static int
78501eac
CW		 751bsd_ring_flush(struct intel_ring_buffer *ring,
752 u32 invalidate_domains,
753 u32 flush_domains)
d1b851fc 754{
b72f3acb
CW		 755 int ret;
756
b72f3acb
CW		 757 ret = intel_ring_begin(ring, 2);
758 if (ret)
759 return ret;
760
761 intel_ring_emit(ring, MI_FLUSH);
762 intel_ring_emit(ring, MI_NOOP);
763 intel_ring_advance(ring);
764 return 0;
d1b851fc
ZN		 765}
766
3cce469c 767static int
8620a3a9 768i9xx_add_request(struct intel_ring_buffer *ring,
3cce469c 769 u32 *result)
d1b851fc
ZN		 770{
771 u32 seqno;
3cce469c
CW		 772 int ret;
773
774 ret = intel_ring_begin(ring, 4);
775 if (ret)
776 return ret;
6f392d54 777
53d227f2 778 seqno = i915_gem_next_request_seqno(ring);
6f392d54 779
3cce469c
CW		 780 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
781 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
782 intel_ring_emit(ring, seqno);
783 intel_ring_emit(ring, MI_USER_INTERRUPT);
784 intel_ring_advance(ring);
d1b851fc 785
3cce469c
CW		 786 *result = seqno;
787 return 0;
d1b851fc
ZN		 788}
789
0f46832f 790static bool
25c06300 791gen6_ring_get_irq(struct intel_ring_buffer *ring)
0f46832f
CW		 792{
793 struct drm_device *dev = ring->dev;
01a03331 794 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 795 unsigned long flags;
0f46832f
CW		 796
797 if (!dev->irq_enabled)
798 return false;
799
4cd53c0c
DV		 800 /* It looks like we need to prevent the gt from suspending while waiting
801 * for an notifiy irq, otherwise irqs seem to get lost on at least the
802 * blt/bsd rings on ivb. */
99ffa162 803 gen6_gt_force_wake_get(dev_priv);
4cd53c0c 804
7338aefa 805 spin_lock_irqsave(&dev_priv->irq_lock, flags);
01a03331 806 if (ring->irq_refcount++ == 0) {
6a848ccb 807 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
f637fde4
DV		 808 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
809 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
810 POSTING_READ(GTIMR);
0f46832f 811 }
7338aefa 812 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 813
814 return true;
815}
816
817static void
25c06300 818gen6_ring_put_irq(struct intel_ring_buffer *ring)
0f46832f
CW		 819{
820 struct drm_device *dev = ring->dev;
01a03331 821 drm_i915_private_t *dev_priv = dev->dev_private;
7338aefa 822 unsigned long flags;
0f46832f 823
7338aefa 824 spin_lock_irqsave(&dev_priv->irq_lock, flags);
01a03331 825 if (--ring->irq_refcount == 0) {
6a848ccb 826 I915_WRITE_IMR(ring, ~0);
f637fde4
DV		 827 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
828 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
829 POSTING_READ(GTIMR);
1ec14ad3 830 }
7338aefa 831 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
4cd53c0c 832
99ffa162 833 gen6_gt_force_wake_put(dev_priv);
d1b851fc
ZN		 834}
835
d1b851fc 836static int
fb3256da 837i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
d1b851fc 838{
e1f99ce6 839 int ret;
78501eac 840
e1f99ce6
CW		 841 ret = intel_ring_begin(ring, 2);
842 if (ret)
843 return ret;
844
78501eac 845 intel_ring_emit(ring,
65f56876
CW		 846 MI_BATCH_BUFFER_START |
847 MI_BATCH_GTT |
78501eac 848 MI_BATCH_NON_SECURE_I965);
c4e7a414 849 intel_ring_emit(ring, offset);
78501eac
CW		 850 intel_ring_advance(ring);
851
d1b851fc
ZN		 852 return 0;
853}
854
8187a2b7 855static int
fb3256da 856i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 857 u32 offset, u32 len)
62fdfeaf 858{
c4e7a414 859 int ret;
62fdfeaf 860
fb3256da
DV		 861 ret = intel_ring_begin(ring, 4);
862 if (ret)
863 return ret;
62fdfeaf 864
fb3256da
DV		 865 intel_ring_emit(ring, MI_BATCH_BUFFER);
866 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
867 intel_ring_emit(ring, offset + len - 8);
868 intel_ring_emit(ring, 0);
869 intel_ring_advance(ring);
e1f99ce6 870
fb3256da
DV		 871 return 0;
872}
873
874static int
875i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
876 u32 offset, u32 len)
877{
878 int ret;
879
880 ret = intel_ring_begin(ring, 2);
881 if (ret)
882 return ret;
883
65f56876 884 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
fb3256da 885 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
c4e7a414 886 intel_ring_advance(ring);
62fdfeaf 887
62fdfeaf
EA		 888 return 0;
889}
890
78501eac 891static void cleanup_status_page(struct intel_ring_buffer *ring)
62fdfeaf 892{
78501eac 893 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 894 struct drm_i915_gem_object *obj;
62fdfeaf 895
8187a2b7
ZN		 896 obj = ring->status_page.obj;
897 if (obj == NULL)
62fdfeaf 898 return;
62fdfeaf 899
05394f39 900 kunmap(obj->pages[0]);
62fdfeaf 901 i915_gem_object_unpin(obj);
05394f39 902 drm_gem_object_unreference(&obj->base);
8187a2b7 903 ring->status_page.obj = NULL;
62fdfeaf
EA		 904
905 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 906}
907
78501eac 908static int init_status_page(struct intel_ring_buffer *ring)
62fdfeaf 909{
78501eac 910 struct drm_device *dev = ring->dev;
62fdfeaf 911 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 912 struct drm_i915_gem_object *obj;
62fdfeaf
EA		 913 int ret;
914
62fdfeaf
EA		 915 obj = i915_gem_alloc_object(dev, 4096);
916 if (obj == NULL) {
917 DRM_ERROR("Failed to allocate status page\n");
918 ret = -ENOMEM;
919 goto err;
920 }
e4ffd173
CW		 921
922 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
62fdfeaf 923
75e9e915 924 ret = i915_gem_object_pin(obj, 4096, true);
62fdfeaf 925 if (ret != 0) {
62fdfeaf
EA		 926 goto err_unref;
927 }
928
05394f39
CW		 929 ring->status_page.gfx_addr = obj->gtt_offset;
930 ring->status_page.page_addr = kmap(obj->pages[0]);
8187a2b7 931 if (ring->status_page.page_addr == NULL) {
62fdfeaf 932 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 933 goto err_unpin;
934 }
8187a2b7
ZN		 935 ring->status_page.obj = obj;
936 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 937
78501eac 938 intel_ring_setup_status_page(ring);
8187a2b7
ZN		 939 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
940 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 941
942 return 0;
943
944err_unpin:
945 i915_gem_object_unpin(obj);
946err_unref:
05394f39 947 drm_gem_object_unreference(&obj->base);
62fdfeaf 948err:
8187a2b7 949 return ret;
62fdfeaf
EA		 950}
951
c43b5634
BW		 952static int intel_init_ring_buffer(struct drm_device *dev,
953 struct intel_ring_buffer *ring)
62fdfeaf 954{
05394f39 955 struct drm_i915_gem_object *obj;
dd785e35
CW		 956 int ret;
957
8187a2b7 958 ring->dev = dev;
23bc5982
CW		 959 INIT_LIST_HEAD(&ring->active_list);
960 INIT_LIST_HEAD(&ring->request_list);
64193406 961 INIT_LIST_HEAD(&ring->gpu_write_list);
dfc9ef2f 962 ring->size = 32 * PAGE_SIZE;
0dc79fb2 963
b259f673 964 init_waitqueue_head(&ring->irq_queue);
62fdfeaf 965
8187a2b7 966 if (I915_NEED_GFX_HWS(dev)) {
78501eac 967 ret = init_status_page(ring);
8187a2b7
ZN		 968 if (ret)
969 return ret;
970 }
62fdfeaf 971
8187a2b7 972 obj = i915_gem_alloc_object(dev, ring->size);
62fdfeaf
EA		 973 if (obj == NULL) {
974 DRM_ERROR("Failed to allocate ringbuffer\n");
8187a2b7 975 ret = -ENOMEM;
dd785e35 976 goto err_hws;
62fdfeaf 977 }
62fdfeaf 978
05394f39 979 ring->obj = obj;
8187a2b7 980
75e9e915 981 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
dd785e35
CW		 982 if (ret)
983 goto err_unref;
62fdfeaf 984
8187a2b7 985 ring->map.size = ring->size;
05394f39 986 ring->map.offset = dev->agp->base + obj->gtt_offset;
62fdfeaf
EA		 987 ring->map.type = 0;
988 ring->map.flags = 0;
989 ring->map.mtrr = 0;
990
991 drm_core_ioremap_wc(&ring->map, dev);
992 if (ring->map.handle == NULL) {
993 DRM_ERROR("Failed to map ringbuffer.\n");
8187a2b7 994 ret = -EINVAL;
dd785e35 995 goto err_unpin;
62fdfeaf
EA		 996 }
997
8187a2b7 998 ring->virtual_start = ring->map.handle;
78501eac 999 ret = ring->init(ring);
dd785e35
CW		 1000 if (ret)
1001 goto err_unmap;
62fdfeaf 1002
55249baa
CW		 1003 /* Workaround an erratum on the i830 which causes a hang if
1004 * the TAIL pointer points to within the last 2 cachelines
1005 * of the buffer.
1006 */
1007 ring->effective_size = ring->size;
27c1cbd0 1008 if (IS_I830(ring->dev) || IS_845G(ring->dev))
55249baa
CW		 1009 ring->effective_size -= 128;
1010
c584fe47 1011 return 0;
dd785e35
CW		 1012
1013err_unmap:
1014 drm_core_ioremapfree(&ring->map, dev);
1015err_unpin:
1016 i915_gem_object_unpin(obj);
1017err_unref:
05394f39
CW		 1018 drm_gem_object_unreference(&obj->base);
1019 ring->obj = NULL;
dd785e35 1020err_hws:
78501eac 1021 cleanup_status_page(ring);
8187a2b7 1022 return ret;
62fdfeaf
EA		 1023}
1024
78501eac 1025void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 1026{
33626e6a
CW		 1027 struct drm_i915_private *dev_priv;
1028 int ret;
1029
05394f39 1030 if (ring->obj == NULL)
62fdfeaf
EA		 1031 return;
1032
33626e6a
CW		 1033 /* Disable the ring buffer. The ring must be idle at this point */
1034 dev_priv = ring->dev->dev_private;
96f298aa 1035 ret = intel_wait_ring_idle(ring);
29ee3991
CW		 1036 if (ret)
1037 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1038 ring->name, ret);
1039
33626e6a
CW		 1040 I915_WRITE_CTL(ring, 0);
1041
78501eac 1042 drm_core_ioremapfree(&ring->map, ring->dev);
62fdfeaf 1043
05394f39
CW		 1044 i915_gem_object_unpin(ring->obj);
1045 drm_gem_object_unreference(&ring->obj->base);
1046 ring->obj = NULL;
78501eac 1047
8d19215b
ZN		 1048 if (ring->cleanup)
1049 ring->cleanup(ring);
1050
78501eac 1051 cleanup_status_page(ring);
62fdfeaf
EA		 1052}
1053
78501eac 1054static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 1055{
8187a2b7 1056 unsigned int *virt;
55249baa 1057 int rem = ring->size - ring->tail;
62fdfeaf 1058
8187a2b7 1059 if (ring->space < rem) {
78501eac 1060 int ret = intel_wait_ring_buffer(ring, rem);
62fdfeaf
EA		 1061 if (ret)
1062 return ret;
1063 }
62fdfeaf 1064
8187a2b7 1065 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1741dd4a
CW		 1066 rem /= 8;
1067 while (rem--) {
62fdfeaf 1068 *virt++ = MI_NOOP;
1741dd4a
CW		 1069 *virt++ = MI_NOOP;
1070 }
62fdfeaf 1071
8187a2b7 1072 ring->tail = 0;
c7dca47b 1073 ring->space = ring_space(ring);
62fdfeaf
EA		 1074
1075 return 0;
1076}
1077
a71d8d94
CW		 1078static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1079{
1080 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1081 bool was_interruptible;
1082 int ret;
1083
1084 /* XXX As we have not yet audited all the paths to check that
1085 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1086 * allow us to be interruptible by a signal.
1087 */
1088 was_interruptible = dev_priv->mm.interruptible;
1089 dev_priv->mm.interruptible = false;
1090
b2da9fe5 1091 ret = i915_wait_request(ring, seqno);
a71d8d94
CW		 1092
1093 dev_priv->mm.interruptible = was_interruptible;
b2da9fe5
BW		 1094 if (!ret)
1095 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 1096
1097 return ret;
1098}
1099
1100static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1101{
1102 struct drm_i915_gem_request *request;
1103 u32 seqno = 0;
1104 int ret;
1105
1106 i915_gem_retire_requests_ring(ring);
1107
1108 if (ring->last_retired_head != -1) {
1109 ring->head = ring->last_retired_head;
1110 ring->last_retired_head = -1;
1111 ring->space = ring_space(ring);
1112 if (ring->space >= n)
1113 return 0;
1114 }
1115
1116 list_for_each_entry(request, &ring->request_list, list) {
1117 int space;
1118
1119 if (request->tail == -1)
1120 continue;
1121
1122 space = request->tail - (ring->tail + 8);
1123 if (space < 0)
1124 space += ring->size;
1125 if (space >= n) {
1126 seqno = request->seqno;
1127 break;
1128 }
1129
1130 /* Consume this request in case we need more space than
1131 * is available and so need to prevent a race between
1132 * updating last_retired_head and direct reads of
1133 * I915_RING_HEAD. It also provides a nice sanity check.
1134 */
1135 request->tail = -1;
1136 }
1137
1138 if (seqno == 0)
1139 return -ENOSPC;
1140
1141 ret = intel_ring_wait_seqno(ring, seqno);
1142 if (ret)
1143 return ret;
1144
1145 if (WARN_ON(ring->last_retired_head == -1))
1146 return -ENOSPC;
1147
1148 ring->head = ring->last_retired_head;
1149 ring->last_retired_head = -1;
1150 ring->space = ring_space(ring);
1151 if (WARN_ON(ring->space < n))
1152 return -ENOSPC;
1153
1154 return 0;
1155}
1156
78501eac 1157int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
62fdfeaf 1158{
78501eac 1159 struct drm_device *dev = ring->dev;
cae5852d 1160 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1161 unsigned long end;
a71d8d94 1162 int ret;
c7dca47b 1163
a71d8d94
CW		 1164 ret = intel_ring_wait_request(ring, n);
1165 if (ret != -ENOSPC)
1166 return ret;
1167
db53a302 1168 trace_i915_ring_wait_begin(ring);
63ed2cb2
DV		 1169 /* With GEM the hangcheck timer should kick us out of the loop,
1170 * leaving it early runs the risk of corrupting GEM state (due
1171 * to running on almost untested codepaths). But on resume
1172 * timers don't work yet, so prevent a complete hang in that
1173 * case by choosing an insanely large timeout. */
1174 end = jiffies + 60 * HZ;
e6bfaf85 1175
8187a2b7 1176 do {
c7dca47b
CW		 1177 ring->head = I915_READ_HEAD(ring);
1178 ring->space = ring_space(ring);
62fdfeaf 1179 if (ring->space >= n) {
db53a302 1180 trace_i915_ring_wait_end(ring);
62fdfeaf
EA		 1181 return 0;
1182 }
1183
1184 if (dev->primary->master) {
1185 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1186 if (master_priv->sarea_priv)
1187 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1188 }
d1b851fc 1189
e60a0b10 1190 msleep(1);
f4e0b29b
CW		 1191 if (atomic_read(&dev_priv->mm.wedged))
1192 return -EAGAIN;
8187a2b7 1193 } while (!time_after(jiffies, end));
db53a302 1194 trace_i915_ring_wait_end(ring);
8187a2b7
ZN		 1195 return -EBUSY;
1196}
62fdfeaf 1197
e1f99ce6
CW		 1198int intel_ring_begin(struct intel_ring_buffer *ring,
1199 int num_dwords)
8187a2b7 1200{
21dd3734 1201 struct drm_i915_private *dev_priv = ring->dev->dev_private;
be26a10b 1202 int n = 4*num_dwords;
e1f99ce6 1203 int ret;
78501eac 1204
21dd3734
CW		 1205 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1206 return -EIO;
1207
55249baa 1208 if (unlikely(ring->tail + n > ring->effective_size)) {
e1f99ce6
CW		 1209 ret = intel_wrap_ring_buffer(ring);
1210 if (unlikely(ret))
1211 return ret;
1212 }
78501eac 1213
e1f99ce6
CW		 1214 if (unlikely(ring->space < n)) {
1215 ret = intel_wait_ring_buffer(ring, n);
1216 if (unlikely(ret))
1217 return ret;
1218 }
d97ed339
CW		 1219
1220 ring->space -= n;
e1f99ce6 1221 return 0;
8187a2b7 1222}
62fdfeaf 1223
78501eac 1224void intel_ring_advance(struct intel_ring_buffer *ring)
8187a2b7 1225{
d97ed339 1226 ring->tail &= ring->size - 1;
78501eac 1227 ring->write_tail(ring, ring->tail);
8187a2b7 1228}
62fdfeaf 1229
881f47b6 1230
78501eac 1231static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 1232 u32 value)
881f47b6 1233{
0206e353 1234 drm_i915_private_t *dev_priv = ring->dev->dev_private;
881f47b6
XH		 1235
1236 /* Every tail move must follow the sequence below */
0206e353
AJ		 1237 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1238 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1239 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1240 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1241
1242 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1243 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1244 50))
1245 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1246
1247 I915_WRITE_TAIL(ring, value);
1248 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1249 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1250 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
881f47b6
XH		 1251}
1252
b72f3acb 1253static int gen6_ring_flush(struct intel_ring_buffer *ring,
71a77e07 1254 u32 invalidate, u32 flush)
881f47b6 1255{
71a77e07 1256 uint32_t cmd;
b72f3acb
CW		 1257 int ret;
1258
b72f3acb
CW		 1259 ret = intel_ring_begin(ring, 4);
1260 if (ret)
1261 return ret;
1262
71a77e07
CW		 1263 cmd = MI_FLUSH_DW;
1264 if (invalidate & I915_GEM_GPU_DOMAINS)
1265 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1266 intel_ring_emit(ring, cmd);
b72f3acb
CW		 1267 intel_ring_emit(ring, 0);
1268 intel_ring_emit(ring, 0);
71a77e07 1269 intel_ring_emit(ring, MI_NOOP);
b72f3acb
CW		 1270 intel_ring_advance(ring);
1271 return 0;
881f47b6
XH		 1272}
1273
1274static int
78501eac 1275gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 1276 u32 offset, u32 len)
881f47b6 1277{
0206e353 1278 int ret;
ab6f8e32 1279
0206e353
AJ		 1280 ret = intel_ring_begin(ring, 2);
1281 if (ret)
1282 return ret;
e1f99ce6 1283
0206e353
AJ		 1284 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1285 /* bit0-7 is the length on GEN6+ */
1286 intel_ring_emit(ring, offset);
1287 intel_ring_advance(ring);
ab6f8e32 1288
0206e353 1289 return 0;
881f47b6
XH		 1290}
1291
549f7365
CW		 1292/* Blitter support (SandyBridge+) */
1293
b72f3acb 1294static int blt_ring_flush(struct intel_ring_buffer *ring,
71a77e07 1295 u32 invalidate, u32 flush)
8d19215b 1296{
71a77e07 1297 uint32_t cmd;
b72f3acb
CW		 1298 int ret;
1299
6a233c78 1300 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 1301 if (ret)
1302 return ret;
1303
71a77e07
CW		 1304 cmd = MI_FLUSH_DW;
1305 if (invalidate & I915_GEM_DOMAIN_RENDER)
1306 cmd |= MI_INVALIDATE_TLB;
1307 intel_ring_emit(ring, cmd);
b72f3acb
CW		 1308 intel_ring_emit(ring, 0);
1309 intel_ring_emit(ring, 0);
71a77e07 1310 intel_ring_emit(ring, MI_NOOP);
b72f3acb
CW		 1311 intel_ring_advance(ring);
1312 return 0;
8d19215b
ZN		 1313}
1314
5c1143bb
XH		 1315int intel_init_render_ring_buffer(struct drm_device *dev)
1316{
1317 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1318 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5c1143bb 1319
59465b5f
DV		 1320 ring->name = "render ring";
1321 ring->id = RCS;
1322 ring->mmio_base = RENDER_RING_BASE;
1323
1ec14ad3
CW		 1324 if (INTEL_INFO(dev)->gen >= 6) {
1325 ring->add_request = gen6_add_request;
8d315287 1326 ring->flush = gen6_render_ring_flush;
25c06300
BW		 1327 ring->irq_get = gen6_ring_get_irq;
1328 ring->irq_put = gen6_ring_put_irq;
6a848ccb 1329 ring->irq_enable_mask = GT_USER_INTERRUPT;
4cd53c0c 1330 ring->get_seqno = gen6_ring_get_seqno;
686cb5f9 1331 ring->sync_to = gen6_ring_sync;
59465b5f
DV		 1332 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1333 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1334 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1335 ring->signal_mbox[0] = GEN6_VRSYNC;
1336 ring->signal_mbox[1] = GEN6_BRSYNC;
c6df541c
CW		 1337 } else if (IS_GEN5(dev)) {
1338 ring->add_request = pc_render_add_request;
46f0f8d1 1339 ring->flush = gen4_render_ring_flush;
c6df541c 1340 ring->get_seqno = pc_render_get_seqno;
e48d8634
DV		 1341 ring->irq_get = gen5_ring_get_irq;
1342 ring->irq_put = gen5_ring_put_irq;
e3670319 1343 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
59465b5f 1344 } else {
8620a3a9 1345 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 1346 if (INTEL_INFO(dev)->gen < 4)
1347 ring->flush = gen2_render_ring_flush;
1348 else
1349 ring->flush = gen4_render_ring_flush;
59465b5f 1350 ring->get_seqno = ring_get_seqno;
c2798b19
CW		 1351 if (IS_GEN2(dev)) {
1352 ring->irq_get = i8xx_ring_get_irq;
1353 ring->irq_put = i8xx_ring_put_irq;
1354 } else {
1355 ring->irq_get = i9xx_ring_get_irq;
1356 ring->irq_put = i9xx_ring_put_irq;
1357 }
e3670319 1358 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 1359 }
59465b5f 1360 ring->write_tail = ring_write_tail;
fb3256da
DV		 1361 if (INTEL_INFO(dev)->gen >= 6)
1362 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1363 else if (INTEL_INFO(dev)->gen >= 4)
1364 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1365 else if (IS_I830(dev) || IS_845G(dev))
1366 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1367 else
1368 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 1369 ring->init = init_render_ring;
1370 ring->cleanup = render_ring_cleanup;
1371
5c1143bb
XH		 1372
1373 if (!I915_NEED_GFX_HWS(dev)) {
1ec14ad3
CW		 1374 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1375 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
5c1143bb
XH		 1376 }
1377
1ec14ad3 1378 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 1379}
1380
e8616b6c
CW		 1381int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1382{
1383 drm_i915_private_t *dev_priv = dev->dev_private;
1384 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1385
59465b5f
DV		 1386 ring->name = "render ring";
1387 ring->id = RCS;
1388 ring->mmio_base = RENDER_RING_BASE;
1389
e8616b6c 1390 if (INTEL_INFO(dev)->gen >= 6) {
b4178f8a
DV		 1391 /* non-kms not supported on gen6+ */
1392 return -ENODEV;
e8616b6c 1393 }
28f0cbf7
DV		 1394
1395 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1396 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1397 * the special gen5 functions. */
1398 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 1399 if (INTEL_INFO(dev)->gen < 4)
1400 ring->flush = gen2_render_ring_flush;
1401 else
1402 ring->flush = gen4_render_ring_flush;
28f0cbf7 1403 ring->get_seqno = ring_get_seqno;
c2798b19
CW		 1404 if (IS_GEN2(dev)) {
1405 ring->irq_get = i8xx_ring_get_irq;
1406 ring->irq_put = i8xx_ring_put_irq;
1407 } else {
1408 ring->irq_get = i9xx_ring_get_irq;
1409 ring->irq_put = i9xx_ring_put_irq;
1410 }
28f0cbf7 1411 ring->irq_enable_mask = I915_USER_INTERRUPT;
59465b5f 1412 ring->write_tail = ring_write_tail;
fb3256da
DV		 1413 if (INTEL_INFO(dev)->gen >= 4)
1414 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1415 else if (IS_I830(dev) || IS_845G(dev))
1416 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1417 else
1418 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 1419 ring->init = init_render_ring;
1420 ring->cleanup = render_ring_cleanup;
e8616b6c 1421
f3234706
KP		 1422 if (!I915_NEED_GFX_HWS(dev))
1423 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1424
e8616b6c
CW		 1425 ring->dev = dev;
1426 INIT_LIST_HEAD(&ring->active_list);
1427 INIT_LIST_HEAD(&ring->request_list);
1428 INIT_LIST_HEAD(&ring->gpu_write_list);
1429
1430 ring->size = size;
1431 ring->effective_size = ring->size;
1432 if (IS_I830(ring->dev))
1433 ring->effective_size -= 128;
1434
1435 ring->map.offset = start;
1436 ring->map.size = size;
1437 ring->map.type = 0;
1438 ring->map.flags = 0;
1439 ring->map.mtrr = 0;
1440
1441 drm_core_ioremap_wc(&ring->map, dev);
1442 if (ring->map.handle == NULL) {
1443 DRM_ERROR("can not ioremap virtual address for"
1444 " ring buffer\n");
1445 return -ENOMEM;
1446 }
1447
1448 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1449 return 0;
1450}
1451
5c1143bb
XH		 1452int intel_init_bsd_ring_buffer(struct drm_device *dev)
1453{
1454 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1455 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
5c1143bb 1456
58fa3835
DV		 1457 ring->name = "bsd ring";
1458 ring->id = VCS;
1459
0fd2c201 1460 ring->write_tail = ring_write_tail;
58fa3835
DV		 1461 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1462 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 1463 /* gen6 bsd needs a special wa for tail updates */
1464 if (IS_GEN6(dev))
1465 ring->write_tail = gen6_bsd_ring_write_tail;
58fa3835
DV		 1466 ring->flush = gen6_ring_flush;
1467 ring->add_request = gen6_add_request;
1468 ring->get_seqno = gen6_ring_get_seqno;
1469 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1470 ring->irq_get = gen6_ring_get_irq;
1471 ring->irq_put = gen6_ring_put_irq;
1472 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
686cb5f9 1473 ring->sync_to = gen6_ring_sync;
58fa3835
DV		 1474 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1475 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1476 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1477 ring->signal_mbox[0] = GEN6_RVSYNC;
1478 ring->signal_mbox[1] = GEN6_BVSYNC;
1479 } else {
1480 ring->mmio_base = BSD_RING_BASE;
58fa3835 1481 ring->flush = bsd_ring_flush;
8620a3a9 1482 ring->add_request = i9xx_add_request;
58fa3835 1483 ring->get_seqno = ring_get_seqno;
e48d8634 1484 if (IS_GEN5(dev)) {
e3670319 1485 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
e48d8634
DV		 1486 ring->irq_get = gen5_ring_get_irq;
1487 ring->irq_put = gen5_ring_put_irq;
1488 } else {
e3670319 1489 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 1490 ring->irq_get = i9xx_ring_get_irq;
1491 ring->irq_put = i9xx_ring_put_irq;
1492 }
fb3256da 1493 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835
DV		 1494 }
1495 ring->init = init_ring_common;
1496
5c1143bb 1497
1ec14ad3 1498 return intel_init_ring_buffer(dev, ring);
5c1143bb 1499}
549f7365
CW		 1500
1501int intel_init_blt_ring_buffer(struct drm_device *dev)
1502{
1503 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1504 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
549f7365 1505
3535d9dd
DV		 1506 ring->name = "blitter ring";
1507 ring->id = BCS;
1508
1509 ring->mmio_base = BLT_RING_BASE;
1510 ring->write_tail = ring_write_tail;
1511 ring->flush = blt_ring_flush;
1512 ring->add_request = gen6_add_request;
1513 ring->get_seqno = gen6_ring_get_seqno;
1514 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1515 ring->irq_get = gen6_ring_get_irq;
1516 ring->irq_put = gen6_ring_put_irq;
1517 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
686cb5f9 1518 ring->sync_to = gen6_ring_sync;
3535d9dd
DV		 1519 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1520 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1521 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1522 ring->signal_mbox[0] = GEN6_RBSYNC;
1523 ring->signal_mbox[1] = GEN6_VBSYNC;
1524 ring->init = init_ring_common;
549f7365 1525
1ec14ad3 1526 return intel_init_ring_buffer(dev, ring);
549f7365 1527}
Linux kernel - Deliverables
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