Commit | Line | Data |
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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 | 51 | static void |
78501eac | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
53 | u32 invalidate_domains, |
54 | u32 flush_domains) | |
62fdfeaf | 55 | { |
78501eac | 56 | struct drm_device *dev = ring->dev; |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
112 | #if WATCH_EXEC | |
113 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
114 | #endif | |
e1f99ce6 CW |
115 | if (intel_ring_begin(ring, 2) == 0) { |
116 | intel_ring_emit(ring, cmd); | |
117 | intel_ring_emit(ring, MI_NOOP); | |
118 | intel_ring_advance(ring); | |
119 | } | |
62fdfeaf | 120 | } |
8187a2b7 ZN |
121 | } |
122 | ||
78501eac | 123 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 124 | u32 value) |
d46eefa2 | 125 | { |
78501eac | 126 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 127 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
128 | } |
129 | ||
78501eac | 130 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 131 | { |
78501eac CW |
132 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
133 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 134 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
135 | |
136 | return I915_READ(acthd_reg); | |
137 | } | |
138 | ||
78501eac | 139 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 140 | { |
78501eac CW |
141 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
142 | struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object); | |
8187a2b7 | 143 | u32 head; |
8187a2b7 ZN |
144 | |
145 | /* Stop the ring if it's running. */ | |
7f2ab699 | 146 | I915_WRITE_CTL(ring, 0); |
570ef608 | 147 | I915_WRITE_HEAD(ring, 0); |
78501eac | 148 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
149 | |
150 | /* Initialize the ring. */ | |
6c0e1c55 | 151 | I915_WRITE_START(ring, obj_priv->gtt_offset); |
570ef608 | 152 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
153 | |
154 | /* G45 ring initialization fails to reset head to zero */ | |
155 | if (head != 0) { | |
156 | DRM_ERROR("%s head not reset to zero " | |
157 | "ctl %08x head %08x tail %08x start %08x\n", | |
158 | ring->name, | |
7f2ab699 | 159 | I915_READ_CTL(ring), |
570ef608 | 160 | I915_READ_HEAD(ring), |
870e86dd | 161 | I915_READ_TAIL(ring), |
6c0e1c55 | 162 | I915_READ_START(ring)); |
8187a2b7 | 163 | |
570ef608 | 164 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
165 | |
166 | DRM_ERROR("%s head forced to zero " | |
167 | "ctl %08x head %08x tail %08x start %08x\n", | |
168 | ring->name, | |
7f2ab699 | 169 | I915_READ_CTL(ring), |
570ef608 | 170 | I915_READ_HEAD(ring), |
870e86dd | 171 | I915_READ_TAIL(ring), |
6c0e1c55 | 172 | I915_READ_START(ring)); |
8187a2b7 ZN |
173 | } |
174 | ||
7f2ab699 | 175 | I915_WRITE_CTL(ring, |
8187a2b7 ZN |
176 | ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES) |
177 | | RING_NO_REPORT | RING_VALID); | |
178 | ||
570ef608 | 179 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
180 | /* If the head is still not zero, the ring is dead */ |
181 | if (head != 0) { | |
182 | DRM_ERROR("%s initialization failed " | |
183 | "ctl %08x head %08x tail %08x start %08x\n", | |
184 | ring->name, | |
7f2ab699 | 185 | I915_READ_CTL(ring), |
570ef608 | 186 | I915_READ_HEAD(ring), |
870e86dd | 187 | I915_READ_TAIL(ring), |
6c0e1c55 | 188 | I915_READ_START(ring)); |
8187a2b7 ZN |
189 | return -EIO; |
190 | } | |
191 | ||
78501eac CW |
192 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
193 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 194 | else { |
570ef608 | 195 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 196 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
197 | ring->space = ring->head - (ring->tail + 8); |
198 | if (ring->space < 0) | |
199 | ring->space += ring->size; | |
200 | } | |
201 | return 0; | |
202 | } | |
203 | ||
78501eac | 204 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 205 | { |
78501eac CW |
206 | struct drm_device *dev = ring->dev; |
207 | int ret = init_ring_common(ring); | |
a69ffdbf | 208 | |
a6c45cf0 | 209 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac CW |
210 | drm_i915_private_t *dev_priv = dev->dev_private; |
211 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; | |
a69ffdbf ZW |
212 | if (IS_GEN6(dev)) |
213 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
214 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 | 215 | } |
78501eac | 216 | |
8187a2b7 ZN |
217 | return ret; |
218 | } | |
219 | ||
78501eac | 220 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
8187a2b7 | 221 | do { \ |
78501eac | 222 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 223 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
78501eac CW |
224 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
225 | intel_ring_emit(ring__, 0); \ | |
226 | intel_ring_emit(ring__, 0); \ | |
8187a2b7 | 227 | } while (0) |
62fdfeaf EA |
228 | |
229 | /** | |
230 | * Creates a new sequence number, emitting a write of it to the status page | |
231 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
232 | * | |
233 | * Must be called with struct_lock held. | |
234 | * | |
235 | * Returned sequence numbers are nonzero on success. | |
236 | */ | |
3cce469c | 237 | static int |
78501eac | 238 | render_ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 239 | u32 *result) |
62fdfeaf | 240 | { |
78501eac | 241 | struct drm_device *dev = ring->dev; |
62fdfeaf | 242 | drm_i915_private_t *dev_priv = dev->dev_private; |
3cce469c CW |
243 | u32 seqno = i915_gem_get_seqno(dev); |
244 | int ret; | |
ca76482e ZW |
245 | |
246 | if (IS_GEN6(dev)) { | |
3cce469c CW |
247 | ret = intel_ring_begin(ring, 6); |
248 | if (ret) | |
249 | return ret; | |
250 | ||
251 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3); | |
252 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE | | |
253 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | | |
254 | PIPE_CONTROL_NOTIFY); | |
255 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
256 | intel_ring_emit(ring, seqno); | |
257 | intel_ring_emit(ring, 0); | |
258 | intel_ring_emit(ring, 0); | |
ca76482e | 259 | } else if (HAS_PIPE_CONTROL(dev)) { |
62fdfeaf EA |
260 | u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; |
261 | ||
262 | /* | |
263 | * Workaround qword write incoherence by flushing the | |
264 | * PIPE_NOTIFY buffers out to memory before requesting | |
265 | * an interrupt. | |
266 | */ | |
3cce469c CW |
267 | ret = intel_ring_begin(ring, 32); |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
272 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | |
273 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
274 | intel_ring_emit(ring, seqno); | |
275 | intel_ring_emit(ring, 0); | |
276 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
277 | scratch_addr += 128; /* write to separate cachelines */ | |
278 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
279 | scratch_addr += 128; | |
280 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
281 | scratch_addr += 128; | |
282 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
283 | scratch_addr += 128; | |
284 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
285 | scratch_addr += 128; | |
286 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
287 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
288 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | |
289 | PIPE_CONTROL_NOTIFY); | |
290 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
291 | intel_ring_emit(ring, seqno); | |
292 | intel_ring_emit(ring, 0); | |
62fdfeaf | 293 | } else { |
3cce469c CW |
294 | ret = intel_ring_begin(ring, 4); |
295 | if (ret) | |
296 | return ret; | |
62fdfeaf | 297 | |
3cce469c CW |
298 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
299 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
300 | intel_ring_emit(ring, seqno); | |
301 | ||
302 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
62fdfeaf | 303 | } |
3cce469c CW |
304 | |
305 | intel_ring_advance(ring); | |
306 | *result = seqno; | |
307 | return 0; | |
62fdfeaf EA |
308 | } |
309 | ||
8187a2b7 | 310 | static u32 |
78501eac | 311 | render_ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 312 | { |
78501eac | 313 | struct drm_device *dev = ring->dev; |
8187a2b7 ZN |
314 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
315 | if (HAS_PIPE_CONTROL(dev)) | |
316 | return ((volatile u32 *)(dev_priv->seqno_page))[0]; | |
317 | else | |
318 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
319 | } | |
320 | ||
321 | static void | |
78501eac | 322 | render_ring_get_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 323 | { |
78501eac | 324 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
325 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
326 | unsigned long irqflags; | |
327 | ||
328 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 329 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
330 | if (HAS_PCH_SPLIT(dev)) |
331 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
332 | else | |
333 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
334 | } | |
335 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
336 | } | |
337 | ||
8187a2b7 | 338 | static void |
78501eac | 339 | render_ring_put_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 340 | { |
78501eac | 341 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
342 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
343 | unsigned long irqflags; | |
344 | ||
345 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
346 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
347 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
348 | if (HAS_PCH_SPLIT(dev)) |
349 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
350 | else | |
351 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
352 | } | |
353 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
354 | } | |
355 | ||
78501eac | 356 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 357 | { |
78501eac CW |
358 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
359 | u32 mmio = IS_GEN6(ring->dev) ? | |
360 | RING_HWS_PGA_GEN6(ring->mmio_base) : | |
361 | RING_HWS_PGA(ring->mmio_base); | |
362 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
363 | POSTING_READ(mmio); | |
8187a2b7 ZN |
364 | } |
365 | ||
ab6f8e32 | 366 | static void |
78501eac CW |
367 | bsd_ring_flush(struct intel_ring_buffer *ring, |
368 | u32 invalidate_domains, | |
369 | u32 flush_domains) | |
d1b851fc | 370 | { |
e1f99ce6 CW |
371 | if (intel_ring_begin(ring, 2) == 0) { |
372 | intel_ring_emit(ring, MI_FLUSH); | |
373 | intel_ring_emit(ring, MI_NOOP); | |
374 | intel_ring_advance(ring); | |
375 | } | |
d1b851fc ZN |
376 | } |
377 | ||
3cce469c | 378 | static int |
78501eac | 379 | ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 380 | u32 *result) |
d1b851fc ZN |
381 | { |
382 | u32 seqno; | |
3cce469c CW |
383 | int ret; |
384 | ||
385 | ret = intel_ring_begin(ring, 4); | |
386 | if (ret) | |
387 | return ret; | |
6f392d54 | 388 | |
78501eac | 389 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 390 | |
3cce469c CW |
391 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
392 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
393 | intel_ring_emit(ring, seqno); | |
394 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
395 | intel_ring_advance(ring); | |
d1b851fc ZN |
396 | |
397 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
3cce469c CW |
398 | *result = seqno; |
399 | return 0; | |
d1b851fc ZN |
400 | } |
401 | ||
d1b851fc | 402 | static void |
78501eac | 403 | bsd_ring_get_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
404 | { |
405 | /* do nothing */ | |
406 | } | |
407 | static void | |
78501eac | 408 | bsd_ring_put_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
409 | { |
410 | /* do nothing */ | |
411 | } | |
412 | ||
413 | static u32 | |
78501eac | 414 | ring_status_page_get_seqno(struct intel_ring_buffer *ring) |
d1b851fc ZN |
415 | { |
416 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
417 | } | |
418 | ||
419 | static int | |
78501eac CW |
420 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
421 | struct drm_i915_gem_execbuffer2 *exec, | |
422 | struct drm_clip_rect *cliprects, | |
423 | uint64_t exec_offset) | |
d1b851fc ZN |
424 | { |
425 | uint32_t exec_start; | |
e1f99ce6 | 426 | int ret; |
78501eac | 427 | |
d1b851fc | 428 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
78501eac | 429 | |
e1f99ce6 CW |
430 | ret = intel_ring_begin(ring, 2); |
431 | if (ret) | |
432 | return ret; | |
433 | ||
78501eac CW |
434 | intel_ring_emit(ring, |
435 | MI_BATCH_BUFFER_START | | |
436 | (2 << 6) | | |
437 | MI_BATCH_NON_SECURE_I965); | |
438 | intel_ring_emit(ring, exec_start); | |
439 | intel_ring_advance(ring); | |
440 | ||
d1b851fc ZN |
441 | return 0; |
442 | } | |
443 | ||
8187a2b7 | 444 | static int |
78501eac CW |
445 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
446 | struct drm_i915_gem_execbuffer2 *exec, | |
447 | struct drm_clip_rect *cliprects, | |
448 | uint64_t exec_offset) | |
62fdfeaf | 449 | { |
78501eac | 450 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
451 | drm_i915_private_t *dev_priv = dev->dev_private; |
452 | int nbox = exec->num_cliprects; | |
62fdfeaf | 453 | uint32_t exec_start, exec_len; |
e1f99ce6 | 454 | int i, count, ret; |
78501eac | 455 | |
62fdfeaf EA |
456 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
457 | exec_len = (uint32_t) exec->batch_len; | |
458 | ||
6f392d54 | 459 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf EA |
460 | |
461 | count = nbox ? nbox : 1; | |
62fdfeaf EA |
462 | for (i = 0; i < count; i++) { |
463 | if (i < nbox) { | |
e1f99ce6 CW |
464 | ret = i915_emit_box(dev, cliprects, i, |
465 | exec->DR1, exec->DR4); | |
62fdfeaf EA |
466 | if (ret) |
467 | return ret; | |
468 | } | |
469 | ||
470 | if (IS_I830(dev) || IS_845G(dev)) { | |
e1f99ce6 CW |
471 | ret = intel_ring_begin(ring, 4); |
472 | if (ret) | |
473 | return ret; | |
474 | ||
78501eac CW |
475 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
476 | intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE); | |
477 | intel_ring_emit(ring, exec_start + exec_len - 4); | |
478 | intel_ring_emit(ring, 0); | |
62fdfeaf | 479 | } else { |
e1f99ce6 CW |
480 | ret = intel_ring_begin(ring, 2); |
481 | if (ret) | |
482 | return ret; | |
483 | ||
a6c45cf0 | 484 | if (INTEL_INFO(dev)->gen >= 4) { |
78501eac | 485 | intel_ring_emit(ring, |
8187a2b7 ZN |
486 | MI_BATCH_BUFFER_START | (2 << 6) |
487 | | MI_BATCH_NON_SECURE_I965); | |
78501eac | 488 | intel_ring_emit(ring, exec_start); |
62fdfeaf | 489 | } else { |
78501eac | 490 | intel_ring_emit(ring, MI_BATCH_BUFFER_START |
8187a2b7 | 491 | | (2 << 6)); |
78501eac | 492 | intel_ring_emit(ring, exec_start | |
8187a2b7 | 493 | MI_BATCH_NON_SECURE); |
62fdfeaf | 494 | } |
62fdfeaf | 495 | } |
78501eac | 496 | intel_ring_advance(ring); |
62fdfeaf EA |
497 | } |
498 | ||
f00a3ddf | 499 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
500 | if (intel_ring_begin(ring, 2) == 0) { |
501 | intel_ring_emit(ring, MI_FLUSH | | |
502 | MI_NO_WRITE_FLUSH | | |
503 | MI_INVALIDATE_ISP ); | |
504 | intel_ring_emit(ring, MI_NOOP); | |
505 | intel_ring_advance(ring); | |
506 | } | |
1cafd347 | 507 | } |
62fdfeaf | 508 | /* XXX breadcrumb */ |
1cafd347 | 509 | |
62fdfeaf EA |
510 | return 0; |
511 | } | |
512 | ||
78501eac | 513 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 514 | { |
78501eac | 515 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
62fdfeaf EA |
516 | struct drm_gem_object *obj; |
517 | struct drm_i915_gem_object *obj_priv; | |
518 | ||
8187a2b7 ZN |
519 | obj = ring->status_page.obj; |
520 | if (obj == NULL) | |
62fdfeaf | 521 | return; |
62fdfeaf EA |
522 | obj_priv = to_intel_bo(obj); |
523 | ||
524 | kunmap(obj_priv->pages[0]); | |
525 | i915_gem_object_unpin(obj); | |
526 | drm_gem_object_unreference(obj); | |
8187a2b7 | 527 | ring->status_page.obj = NULL; |
62fdfeaf EA |
528 | |
529 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
530 | } |
531 | ||
78501eac | 532 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 533 | { |
78501eac | 534 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
535 | drm_i915_private_t *dev_priv = dev->dev_private; |
536 | struct drm_gem_object *obj; | |
537 | struct drm_i915_gem_object *obj_priv; | |
538 | int ret; | |
539 | ||
62fdfeaf EA |
540 | obj = i915_gem_alloc_object(dev, 4096); |
541 | if (obj == NULL) { | |
542 | DRM_ERROR("Failed to allocate status page\n"); | |
543 | ret = -ENOMEM; | |
544 | goto err; | |
545 | } | |
546 | obj_priv = to_intel_bo(obj); | |
547 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
548 | ||
920afa77 | 549 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 550 | if (ret != 0) { |
62fdfeaf EA |
551 | goto err_unref; |
552 | } | |
553 | ||
8187a2b7 ZN |
554 | ring->status_page.gfx_addr = obj_priv->gtt_offset; |
555 | ring->status_page.page_addr = kmap(obj_priv->pages[0]); | |
556 | if (ring->status_page.page_addr == NULL) { | |
62fdfeaf | 557 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
558 | goto err_unpin; |
559 | } | |
8187a2b7 ZN |
560 | ring->status_page.obj = obj; |
561 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 562 | |
78501eac | 563 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
564 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
565 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
566 | |
567 | return 0; | |
568 | ||
569 | err_unpin: | |
570 | i915_gem_object_unpin(obj); | |
571 | err_unref: | |
572 | drm_gem_object_unreference(obj); | |
573 | err: | |
8187a2b7 | 574 | return ret; |
62fdfeaf EA |
575 | } |
576 | ||
8187a2b7 | 577 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 578 | struct intel_ring_buffer *ring) |
62fdfeaf | 579 | { |
870e86dd | 580 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 ZN |
581 | struct drm_i915_gem_object *obj_priv; |
582 | struct drm_gem_object *obj; | |
dd785e35 CW |
583 | int ret; |
584 | ||
8187a2b7 | 585 | ring->dev = dev; |
23bc5982 CW |
586 | INIT_LIST_HEAD(&ring->active_list); |
587 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 588 | INIT_LIST_HEAD(&ring->gpu_write_list); |
62fdfeaf | 589 | |
8187a2b7 | 590 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 591 | ret = init_status_page(ring); |
8187a2b7 ZN |
592 | if (ret) |
593 | return ret; | |
594 | } | |
62fdfeaf | 595 | |
8187a2b7 | 596 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
597 | if (obj == NULL) { |
598 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 599 | ret = -ENOMEM; |
dd785e35 | 600 | goto err_hws; |
62fdfeaf | 601 | } |
62fdfeaf | 602 | |
8187a2b7 ZN |
603 | ring->gem_object = obj; |
604 | ||
920afa77 | 605 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
606 | if (ret) |
607 | goto err_unref; | |
62fdfeaf | 608 | |
8187a2b7 ZN |
609 | obj_priv = to_intel_bo(obj); |
610 | ring->map.size = ring->size; | |
62fdfeaf | 611 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
62fdfeaf EA |
612 | ring->map.type = 0; |
613 | ring->map.flags = 0; | |
614 | ring->map.mtrr = 0; | |
615 | ||
616 | drm_core_ioremap_wc(&ring->map, dev); | |
617 | if (ring->map.handle == NULL) { | |
618 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 619 | ret = -EINVAL; |
dd785e35 | 620 | goto err_unpin; |
62fdfeaf EA |
621 | } |
622 | ||
8187a2b7 | 623 | ring->virtual_start = ring->map.handle; |
78501eac | 624 | ret = ring->init(ring); |
dd785e35 CW |
625 | if (ret) |
626 | goto err_unmap; | |
62fdfeaf | 627 | |
62fdfeaf EA |
628 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
629 | i915_kernel_lost_context(dev); | |
630 | else { | |
570ef608 | 631 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 632 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
62fdfeaf EA |
633 | ring->space = ring->head - (ring->tail + 8); |
634 | if (ring->space < 0) | |
8187a2b7 | 635 | ring->space += ring->size; |
62fdfeaf | 636 | } |
8187a2b7 | 637 | return ret; |
dd785e35 CW |
638 | |
639 | err_unmap: | |
640 | drm_core_ioremapfree(&ring->map, dev); | |
641 | err_unpin: | |
642 | i915_gem_object_unpin(obj); | |
643 | err_unref: | |
644 | drm_gem_object_unreference(obj); | |
645 | ring->gem_object = NULL; | |
646 | err_hws: | |
78501eac | 647 | cleanup_status_page(ring); |
8187a2b7 | 648 | return ret; |
62fdfeaf EA |
649 | } |
650 | ||
78501eac | 651 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 652 | { |
8187a2b7 | 653 | if (ring->gem_object == NULL) |
62fdfeaf EA |
654 | return; |
655 | ||
78501eac | 656 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 657 | |
8187a2b7 ZN |
658 | i915_gem_object_unpin(ring->gem_object); |
659 | drm_gem_object_unreference(ring->gem_object); | |
660 | ring->gem_object = NULL; | |
78501eac CW |
661 | |
662 | cleanup_status_page(ring); | |
62fdfeaf EA |
663 | } |
664 | ||
78501eac | 665 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 666 | { |
8187a2b7 | 667 | unsigned int *virt; |
62fdfeaf | 668 | int rem; |
8187a2b7 | 669 | rem = ring->size - ring->tail; |
62fdfeaf | 670 | |
8187a2b7 | 671 | if (ring->space < rem) { |
78501eac | 672 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
673 | if (ret) |
674 | return ret; | |
675 | } | |
62fdfeaf | 676 | |
8187a2b7 | 677 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
678 | rem /= 8; |
679 | while (rem--) { | |
62fdfeaf | 680 | *virt++ = MI_NOOP; |
1741dd4a CW |
681 | *virt++ = MI_NOOP; |
682 | } | |
62fdfeaf | 683 | |
8187a2b7 | 684 | ring->tail = 0; |
43ed340a | 685 | ring->space = ring->head - 8; |
62fdfeaf EA |
686 | |
687 | return 0; | |
688 | } | |
689 | ||
78501eac | 690 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 691 | { |
78501eac | 692 | struct drm_device *dev = ring->dev; |
570ef608 | 693 | drm_i915_private_t *dev_priv = dev->dev_private; |
78501eac | 694 | unsigned long end; |
62fdfeaf EA |
695 | |
696 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
697 | end = jiffies + 3 * HZ; |
698 | do { | |
570ef608 | 699 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
700 | ring->space = ring->head - (ring->tail + 8); |
701 | if (ring->space < 0) | |
8187a2b7 | 702 | ring->space += ring->size; |
62fdfeaf | 703 | if (ring->space >= n) { |
78501eac | 704 | trace_i915_ring_wait_end(dev); |
62fdfeaf EA |
705 | return 0; |
706 | } | |
707 | ||
708 | if (dev->primary->master) { | |
709 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
710 | if (master_priv->sarea_priv) | |
711 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
712 | } | |
d1b851fc | 713 | |
e60a0b10 | 714 | msleep(1); |
8187a2b7 ZN |
715 | } while (!time_after(jiffies, end)); |
716 | trace_i915_ring_wait_end (dev); | |
717 | return -EBUSY; | |
718 | } | |
62fdfeaf | 719 | |
e1f99ce6 CW |
720 | int intel_ring_begin(struct intel_ring_buffer *ring, |
721 | int num_dwords) | |
8187a2b7 | 722 | { |
be26a10b | 723 | int n = 4*num_dwords; |
e1f99ce6 | 724 | int ret; |
78501eac | 725 | |
e1f99ce6 CW |
726 | if (unlikely(ring->tail + n > ring->size)) { |
727 | ret = intel_wrap_ring_buffer(ring); | |
728 | if (unlikely(ret)) | |
729 | return ret; | |
730 | } | |
78501eac | 731 | |
e1f99ce6 CW |
732 | if (unlikely(ring->space < n)) { |
733 | ret = intel_wait_ring_buffer(ring, n); | |
734 | if (unlikely(ret)) | |
735 | return ret; | |
736 | } | |
d97ed339 CW |
737 | |
738 | ring->space -= n; | |
e1f99ce6 | 739 | return 0; |
8187a2b7 | 740 | } |
62fdfeaf | 741 | |
78501eac | 742 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 743 | { |
d97ed339 | 744 | ring->tail &= ring->size - 1; |
78501eac | 745 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 746 | } |
62fdfeaf | 747 | |
e070868e | 748 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 749 | .name = "render ring", |
9220434a | 750 | .id = RING_RENDER, |
333e9fe9 | 751 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 752 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 753 | .init = init_render_ring, |
297b0c5b | 754 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
755 | .flush = render_ring_flush, |
756 | .add_request = render_ring_add_request, | |
f787a5f5 | 757 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
758 | .user_irq_get = render_ring_get_user_irq, |
759 | .user_irq_put = render_ring_put_user_irq, | |
78501eac | 760 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
8187a2b7 | 761 | }; |
d1b851fc ZN |
762 | |
763 | /* ring buffer for bit-stream decoder */ | |
764 | ||
e070868e | 765 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 766 | .name = "bsd ring", |
9220434a | 767 | .id = RING_BSD, |
333e9fe9 | 768 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 769 | .size = 32 * PAGE_SIZE, |
78501eac | 770 | .init = init_ring_common, |
297b0c5b | 771 | .write_tail = ring_write_tail, |
d1b851fc | 772 | .flush = bsd_ring_flush, |
549f7365 CW |
773 | .add_request = ring_add_request, |
774 | .get_seqno = ring_status_page_get_seqno, | |
d1b851fc ZN |
775 | .user_irq_get = bsd_ring_get_user_irq, |
776 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 777 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 778 | }; |
5c1143bb | 779 | |
881f47b6 | 780 | |
78501eac | 781 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 782 | u32 value) |
881f47b6 | 783 | { |
78501eac | 784 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
785 | |
786 | /* Every tail move must follow the sequence below */ | |
787 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
788 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
789 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
790 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
791 | ||
792 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
793 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
794 | 50)) | |
795 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
796 | ||
870e86dd | 797 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
798 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
799 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
800 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
801 | } | |
802 | ||
78501eac | 803 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
549f7365 CW |
804 | u32 invalidate_domains, |
805 | u32 flush_domains) | |
881f47b6 | 806 | { |
e1f99ce6 CW |
807 | if (intel_ring_begin(ring, 4) == 0) { |
808 | intel_ring_emit(ring, MI_FLUSH_DW); | |
809 | intel_ring_emit(ring, 0); | |
810 | intel_ring_emit(ring, 0); | |
811 | intel_ring_emit(ring, 0); | |
812 | intel_ring_advance(ring); | |
813 | } | |
881f47b6 XH |
814 | } |
815 | ||
816 | static int | |
78501eac CW |
817 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
818 | struct drm_i915_gem_execbuffer2 *exec, | |
819 | struct drm_clip_rect *cliprects, | |
820 | uint64_t exec_offset) | |
881f47b6 XH |
821 | { |
822 | uint32_t exec_start; | |
e1f99ce6 | 823 | int ret; |
ab6f8e32 | 824 | |
881f47b6 | 825 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
ab6f8e32 | 826 | |
e1f99ce6 CW |
827 | ret = intel_ring_begin(ring, 2); |
828 | if (ret) | |
829 | return ret; | |
830 | ||
78501eac | 831 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
ab6f8e32 | 832 | /* bit0-7 is the length on GEN6+ */ |
78501eac CW |
833 | intel_ring_emit(ring, exec_start); |
834 | intel_ring_advance(ring); | |
ab6f8e32 | 835 | |
881f47b6 XH |
836 | return 0; |
837 | } | |
838 | ||
839 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 840 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
841 | .name = "gen6 bsd ring", |
842 | .id = RING_BSD, | |
333e9fe9 | 843 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 844 | .size = 32 * PAGE_SIZE, |
78501eac | 845 | .init = init_ring_common, |
297b0c5b | 846 | .write_tail = gen6_bsd_ring_write_tail, |
549f7365 CW |
847 | .flush = gen6_ring_flush, |
848 | .add_request = ring_add_request, | |
849 | .get_seqno = ring_status_page_get_seqno, | |
881f47b6 XH |
850 | .user_irq_get = bsd_ring_get_user_irq, |
851 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 852 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
549f7365 CW |
853 | }; |
854 | ||
855 | /* Blitter support (SandyBridge+) */ | |
856 | ||
857 | static void | |
78501eac | 858 | blt_ring_get_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
859 | { |
860 | /* do nothing */ | |
861 | } | |
862 | static void | |
78501eac | 863 | blt_ring_put_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
864 | { |
865 | /* do nothing */ | |
866 | } | |
867 | ||
868 | static const struct intel_ring_buffer gen6_blt_ring = { | |
869 | .name = "blt ring", | |
870 | .id = RING_BLT, | |
871 | .mmio_base = BLT_RING_BASE, | |
872 | .size = 32 * PAGE_SIZE, | |
873 | .init = init_ring_common, | |
297b0c5b | 874 | .write_tail = ring_write_tail, |
549f7365 CW |
875 | .flush = gen6_ring_flush, |
876 | .add_request = ring_add_request, | |
877 | .get_seqno = ring_status_page_get_seqno, | |
878 | .user_irq_get = blt_ring_get_user_irq, | |
879 | .user_irq_put = blt_ring_put_user_irq, | |
78501eac | 880 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
881f47b6 XH |
881 | }; |
882 | ||
5c1143bb XH |
883 | int intel_init_render_ring_buffer(struct drm_device *dev) |
884 | { | |
885 | drm_i915_private_t *dev_priv = dev->dev_private; | |
886 | ||
887 | dev_priv->render_ring = render_ring; | |
888 | ||
889 | if (!I915_NEED_GFX_HWS(dev)) { | |
890 | dev_priv->render_ring.status_page.page_addr | |
891 | = dev_priv->status_page_dmah->vaddr; | |
892 | memset(dev_priv->render_ring.status_page.page_addr, | |
893 | 0, PAGE_SIZE); | |
894 | } | |
895 | ||
896 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
897 | } | |
898 | ||
899 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
900 | { | |
901 | drm_i915_private_t *dev_priv = dev->dev_private; | |
902 | ||
881f47b6 XH |
903 | if (IS_GEN6(dev)) |
904 | dev_priv->bsd_ring = gen6_bsd_ring; | |
905 | else | |
906 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
907 | |
908 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
909 | } | |
549f7365 CW |
910 | |
911 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
912 | { | |
913 | drm_i915_private_t *dev_priv = dev->dev_private; | |
914 | ||
915 | dev_priv->blt_ring = gen6_blt_ring; | |
916 | ||
917 | return intel_init_ring_buffer(dev, &dev_priv->blt_ring); | |
918 | } |