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drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
4772eaeb 320static int
a4872ba6 321gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 322 u32 invalidate_domains, u32 flush_domains)
323{
324 u32 flags = 0;
18393f63 325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 326 int ret;
327
f3987631
PZ		 328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
4772eaeb
PZ		 338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 345 }
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 354 /*
355 * TLB invalidate requires a post-sync write.
356 */
357 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 359
add284a3
CW		 360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
361
f3987631
PZ		 362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 366 }
367
368 ret = intel_ring_begin(ring, 4);
369 if (ret)
370 return ret;
371
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
b9e1faa7 374 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
377
378 return 0;
379}
380
884ceace
KG		 381static int
382gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
384{
385 int ret;
386
387 ret = intel_ring_begin(ring, 6);
388 if (ret)
389 return ret;
390
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
398
399 return 0;
400}
401
a5f3d68e 402static int
a4872ba6 403gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 404 u32 invalidate_domains, u32 flush_domains)
405{
406 u32 flags = 0;
18393f63 407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 408 int ret;
a5f3d68e
BW		 409
410 flags |= PIPE_CONTROL_CS_STALL;
411
412 if (flush_domains) {
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
415 }
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 425
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
430 0);
431 if (ret)
432 return ret;
a5f3d68e
BW		 433 }
434
6e0b3f8d 435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
a5f3d68e
BW		 436}
437
a4872ba6 438static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 439 u32 value)
d46eefa2 440{
4640c4ff 441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 442 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 443}
444
a4872ba6 445u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 448 u64 acthd;
8187a2b7 449
50877445
CW		 450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
455 else
456 acthd = I915_READ(ACTHD);
457
458 return acthd;
8187a2b7
ZN		 459}
460
a4872ba6 461static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 462{
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
464 u32 addr;
465
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
470}
471
af75f269
DL		 472static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
473{
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
476 u32 mmio = 0;
477
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
480 */
481 if (IS_GEN7(dev)) {
482 switch (ring->id) {
483 case RCS:
484 mmio = RENDER_HWS_PGA_GEN7;
485 break;
486 case BCS:
487 mmio = BLT_HWS_PGA_GEN7;
488 break;
489 /*
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
492 */
493 case VCS2:
494 case VCS:
495 mmio = BSD_HWS_PGA_GEN7;
496 break;
497 case VECS:
498 mmio = VEBOX_HWS_PGA_GEN7;
499 break;
500 }
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
503 } else {
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
506 }
507
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
509 POSTING_READ(mmio);
510
511 /*
512 * Flush the TLB for this page
513 *
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
517 */
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
520
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
523
524 I915_WRITE(reg,
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
526 INSTPM_SYNC_FLUSH));
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
528 1000))
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
530 ring->name);
531 }
532}
533
a4872ba6 534static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 535{
9991ae78 536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 537
9991ae78
CW		 538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
545 */
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
547 return false;
9991ae78
CW		 548 }
549 }
b7884eb4 550
7f2ab699 551 I915_WRITE_CTL(ring, 0);
570ef608 552 I915_WRITE_HEAD(ring, 0);
78501eac 553 ring->write_tail(ring, 0);
8187a2b7 554
9991ae78
CW		 555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
558 }
a51435a3 559
9991ae78
CW		 560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
561}
8187a2b7 562
a4872ba6 563static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 564{
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 569 int ret = 0;
570
59bad947 571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 572
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 ring->name,
578 I915_READ_CTL(ring),
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
8187a2b7 582
9991ae78 583 if (!stop_ring(ring)) {
6fd0d56e
CW		 584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 ring->name,
587 I915_READ_CTL(ring),
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
9991ae78
CW		 591 ret = -EIO;
592 goto out;
6fd0d56e 593 }
8187a2b7
ZN		 594 }
595
9991ae78
CW		 596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
598 else
599 ring_setup_phys_status_page(ring);
600
ece4a17d
JK		 601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
603
0d8957c8
DV		 604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
f343c5f6 608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
616
7f2ab699 617 I915_WRITE_CTL(ring,
93b0a4e0 618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 619 | RING_VALID);
8187a2b7 620
8187a2b7 621 /* If the head is still not zero, the ring is dead */
f01db988 622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 625 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 ring->name,
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 631 ret = -EIO;
632 goto out;
8187a2b7
ZN		 633 }
634
ebd0fd4b 635 ringbuf->last_retired_head = -1;
5c6c6003
CW		 636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 638 intel_ring_update_space(ringbuf);
1ec14ad3 639
50f018df
CW		 640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
641
b7884eb4 642out:
59bad947 643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 644
645 return ret;
8187a2b7
ZN		 646}
647
9b1136d5
OM		 648void
649intel_fini_pipe_control(struct intel_engine_cs *ring)
650{
651 struct drm_device *dev = ring->dev;
652
653 if (ring->scratch.obj == NULL)
654 return;
655
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(sg_page(ring->scratch.obj->pages->sgl));
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
659 }
660
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
663}
664
665int
666intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 667{
c6df541c
CW		 668 int ret;
669
bfc882b4 670 WARN_ON(ring->scratch.obj);
c6df541c 671
0d1aacac
CW		 672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
c6df541c
CW		 674 DRM_ERROR("Failed to allocate seqno page\n");
675 ret = -ENOMEM;
676 goto err;
677 }
e4ffd173 678
a9cc726c
DV		 679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
680 if (ret)
681 goto err_unref;
c6df541c 682
1ec9e26d 683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 684 if (ret)
685 goto err_unref;
686
0d1aacac
CW		 687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
689 if (ring->scratch.cpu_page == NULL) {
56b085a0 690 ret = -ENOMEM;
c6df541c 691 goto err_unpin;
56b085a0 692 }
c6df541c 693
2b1086cc 694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 695 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 696 return 0;
697
698err_unpin:
d7f46fc4 699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 700err_unref:
0d1aacac 701 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 702err:
c6df541c
CW		 703 return ret;
704}
705
771b9a53
MT		 706static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
86d7f238 708{
7225342a 709 int ret, i;
888b5995
AS		 710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 712 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 713
e6c1abb7 714 if (WARN_ON_ONCE(w->count == 0))
7225342a 715 return 0;
888b5995 716
7225342a
MK		 717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
719 if (ret)
720 return ret;
888b5995 721
22a916aa 722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 723 if (ret)
724 return ret;
725
22a916aa 726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 727 for (i = 0; i < w->count; i++) {
7225342a
MK		 728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
730 }
22a916aa 731 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 732
733 intel_ring_advance(ring);
734
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
737 if (ret)
738 return ret;
888b5995 739
7225342a 740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 741
7225342a 742 return 0;
86d7f238
AS		 743}
744
8f0e2b9d
DV		 745static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
747{
748 int ret;
749
750 ret = intel_ring_workarounds_emit(ring, ctx);
751 if (ret != 0)
752 return ret;
753
754 ret = i915_gem_render_state_init(ring);
755 if (ret)
756 DRM_ERROR("init render state: %d\n", ret);
757
758 return ret;
759}
760
7225342a 761static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 762 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 763{
764 const u32 idx = dev_priv->workarounds.count;
765
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
767 return -ENOSPC;
768
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
772
773 dev_priv->workarounds.count++;
774
775 return 0;
86d7f238
AS		 776}
777
cf4b0de6
DL		 778#define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 780 if (r) \
781 return r; \
782 }
783
784#define WA_SET_BIT_MASKED(addr, mask) \
26459343 785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 786
787#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 789
98533251 790#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 792
cf4b0de6
DL		 793#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 795
cf4b0de6 796#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 797
00e1e623 798static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 799{
888b5995
AS		 800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 802
86d7f238 803 /* WaDisablePartialInstShootdown:bdw */
101b376d 804 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 805 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
806 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
807 STALL_DOP_GATING_DISABLE);
86d7f238 808
101b376d 809 /* WaDisableDopClockGating:bdw */
7225342a
MK		 810 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
811 DOP_CLOCK_GATING_DISABLE);
86d7f238 812
7225342a
MK		 813 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
814 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 815
816 /* Use Force Non-Coherent whenever executing a 3D context. This is a
817 * workaround for for a possible hang in the unlikely event a TLB
818 * invalidation occurs during a PSD flush.
819 */
7225342a 820 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 821 /* WaForceEnableNonCoherent:bdw */
7225342a 822 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 823 /* WaForceContextSaveRestoreNonCoherent:bdw */
824 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
825 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 826 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 827 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 828 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 829
2701fc43
KG		 830 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
831 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
832 * polygons in the same 8x4 pixel/sample area to be processed without
833 * stalling waiting for the earlier ones to write to Hierarchical Z
834 * buffer."
835 *
836 * This optimization is off by default for Broadwell; turn it on.
837 */
838 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
839
86d7f238 840 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 841 WA_SET_BIT_MASKED(CACHE_MODE_1,
842 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 843
844 /*
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
847 *
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
851 */
98533251
DL		 852 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
853 GEN6_WIZ_HASHING_MASK,
854 GEN6_WIZ_HASHING_16x4);
888b5995 855
51ce4db1
RV		 856 /* WaProgramL3SqcReg1Default:bdw */
857 WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
858
86d7f238
AS		 859 return 0;
860}
861
00e1e623
VS		 862static int chv_init_workarounds(struct intel_engine_cs *ring)
863{
00e1e623
VS		 864 struct drm_device *dev = ring->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866
00e1e623 867 /* WaDisablePartialInstShootdown:chv */
00e1e623 868 /* WaDisableThreadStallDopClockGating:chv */
7225342a 869 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 870 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
871 STALL_DOP_GATING_DISABLE);
00e1e623 872
95289009
AS		 873 /* Use Force Non-Coherent whenever executing a 3D context. This is a
874 * workaround for a possible hang in the unlikely event a TLB
875 * invalidation occurs during a PSD flush.
876 */
877 /* WaForceEnableNonCoherent:chv */
878 /* WaHdcDisableFetchWhenMasked:chv */
879 WA_SET_BIT_MASKED(HDC_CHICKEN0,
880 HDC_FORCE_NON_COHERENT |
881 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
882
973a5b06
KG		 883 /* According to the CACHE_MODE_0 default value documentation, some
884 * CHV platforms disable this optimization by default. Turn it on.
885 */
886 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
887
14bc16e3
VS		 888 /* Wa4x4STCOptimizationDisable:chv */
889 WA_SET_BIT_MASKED(CACHE_MODE_1,
890 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
891
d60de81d
KG		 892 /* Improve HiZ throughput on CHV. */
893 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
894
e7fc2436
VS		 895 /*
896 * BSpec recommends 8x4 when MSAA is used,
897 * however in practice 16x4 seems fastest.
898 *
899 * Note that PS/WM thread counts depend on the WIZ hashing
900 * disable bit, which we don't touch here, but it's good
901 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
902 */
903 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
904 GEN6_WIZ_HASHING_MASK,
905 GEN6_WIZ_HASHING_16x4);
906
65ca7514
DL		 907 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
908 INTEL_REVID(dev) == SKL_REVID_D0)
909 /* WaBarrierPerformanceFixDisable:skl */
910 WA_SET_BIT_MASKED(HDC_CHICKEN0,
911 HDC_FENCE_DEST_SLM_DISABLE |
912 HDC_BARRIER_PERFORMANCE_DISABLE);
913
7225342a
MK		 914 return 0;
915}
916
3b106531
HN		 917static int gen9_init_workarounds(struct intel_engine_cs *ring)
918{
ab0dfafe
HN		 919 struct drm_device *dev = ring->dev;
920 struct drm_i915_private *dev_priv = dev->dev_private;
921
b0e6f6d4 922 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 923 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
924 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
925
a119a6e6 926 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 927 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
928 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
929
d2a31dbd
NH		 930 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
931 INTEL_REVID(dev) == SKL_REVID_B0)) ||
932 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
933 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
935 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 936 }
937
a13d215f
NH		 938 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
939 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
940 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 941 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
942 GEN9_RHWO_OPTIMIZATION_DISABLE);
943 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
944 DISABLE_PIXEL_MASK_CAMMING);
945 }
946
27a1b688
NH		 947 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
948 IS_BROXTON(dev)) {
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 950 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
951 GEN9_ENABLE_YV12_BUGFIX);
952 }
953
1840481f
HN		 954 /* Wa4x4STCOptimizationDisable:skl */
955 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
956
9370cd98
DL		 957 /* WaDisablePartialResolveInVc:skl */
958 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
959
e2db7071
DL		 960 /* WaCcsTlbPrefetchDisable:skl */
961 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
962 GEN9_CCS_TLB_PREFETCH_ENABLE);
963
38a39a7b
BW		 964 /*
965 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
966 * the flag reads back as 0.
967 */
8d09c812
BW		 968 /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
969 if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
38a39a7b
BW		 970 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
971 PIXEL_MASK_CAMMING_DISABLE);
972
3b106531
HN		 973 return 0;
974}
975
b7668791
DL		 976static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
977{
978 struct drm_device *dev = ring->dev;
979 struct drm_i915_private *dev_priv = dev->dev_private;
980 u8 vals[3] = { 0, 0, 0 };
981 unsigned int i;
982
983 for (i = 0; i < 3; i++) {
984 u8 ss;
985
986 /*
987 * Only consider slices where one, and only one, subslice has 7
988 * EUs
989 */
990 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
991 continue;
992
993 /*
994 * subslice_7eu[i] != 0 (because of the check above) and
995 * ss_max == 4 (maximum number of subslices possible per slice)
996 *
997 * -> 0 <= ss <= 3;
998 */
999 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1000 vals[i] = 3 - ss;
1001 }
1002
1003 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1004 return 0;
1005
1006 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1007 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1008 GEN9_IZ_HASHING_MASK(2) |
1009 GEN9_IZ_HASHING_MASK(1) |
1010 GEN9_IZ_HASHING_MASK(0),
1011 GEN9_IZ_HASHING(2, vals[2]) |
1012 GEN9_IZ_HASHING(1, vals[1]) |
1013 GEN9_IZ_HASHING(0, vals[0]));
1014
1015 return 0;
1016}
1017
1018
8d205494
DL		 1019static int skl_init_workarounds(struct intel_engine_cs *ring)
1020{
d0bbbc4f
DL		 1021 struct drm_device *dev = ring->dev;
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023
8d205494
DL		 1024 gen9_init_workarounds(ring);
1025
d0bbbc4f
DL		 1026 /* WaDisablePowerCompilerClockGating:skl */
1027 if (INTEL_REVID(dev) == SKL_REVID_B0)
1028 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1029 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1030
b62adbd1
NH		 1031 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1032 /*
1033 *Use Force Non-Coherent whenever executing a 3D context. This
1034 * is a workaround for a possible hang in the unlikely event
1035 * a TLB invalidation occurs during a PSD flush.
1036 */
1037 /* WaForceEnableNonCoherent:skl */
1038 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1039 HDC_FORCE_NON_COHERENT);
1040 }
1041
b7668791 1042 return skl_tune_iz_hashing(ring);
7225342a
MK		 1043}
1044
cae0437f
NH		 1045static int bxt_init_workarounds(struct intel_engine_cs *ring)
1046{
dfb601e6
NH		 1047 struct drm_device *dev = ring->dev;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049
cae0437f
NH		 1050 gen9_init_workarounds(ring);
1051
dfb601e6
NH		 1052 /* WaDisableThreadStallDopClockGating:bxt */
1053 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1054 STALL_DOP_GATING_DISABLE);
1055
983b4b9d
NH		 1056 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1057 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1058 WA_SET_BIT_MASKED(
1059 GEN7_HALF_SLICE_CHICKEN1,
1060 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1061 }
1062
83a24979
NH		 1063 /* WaForceContextSaveRestoreNonCoherent:bxt */
1064 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1065 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
1066
cae0437f
NH		 1067 return 0;
1068}
1069
771b9a53 1070int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1071{
1072 struct drm_device *dev = ring->dev;
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074
1075 WARN_ON(ring->id != RCS);
1076
1077 dev_priv->workarounds.count = 0;
1078
1079 if (IS_BROADWELL(dev))
1080 return bdw_init_workarounds(ring);
1081
1082 if (IS_CHERRYVIEW(dev))
1083 return chv_init_workarounds(ring);
00e1e623 1084
8d205494
DL		 1085 if (IS_SKYLAKE(dev))
1086 return skl_init_workarounds(ring);
cae0437f
NH		 1087
1088 if (IS_BROXTON(dev))
1089 return bxt_init_workarounds(ring);
3b106531 1090
00e1e623
VS		 1091 return 0;
1092}
1093
a4872ba6 1094static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1095{
78501eac 1096 struct drm_device *dev = ring->dev;
1ec14ad3 1097 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1098 int ret = init_ring_common(ring);
9c33baa6
KZ		 1099 if (ret)
1100 return ret;
a69ffdbf 1101
61a563a2
AG		 1102 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1103 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1104 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1105
1106 /* We need to disable the AsyncFlip performance optimisations in order
1107 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1108 * programmed to '1' on all products.
8693a824 1109 *
b3f797ac 1110 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 1111 */
fbdcb068 1112 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 1113 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1114
f05bb0c7 1115 /* Required for the hardware to program scanline values for waiting */
01fa0302 1116 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1117 if (INTEL_INFO(dev)->gen == 6)
1118 I915_WRITE(GFX_MODE,
aa83e30d 1119 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1120
01fa0302 1121 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1122 if (IS_GEN7(dev))
1123 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1124 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1125 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1126
5e13a0c5 1127 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1128 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1129 * "If this bit is set, STCunit will have LRA as replacement
1130 * policy. [...] This bit must be reset. LRA replacement
1131 * policy is not supported."
1132 */
1133 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1134 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1135 }
1136
6b26c86d
DV		 1137 if (INTEL_INFO(dev)->gen >= 6)
1138 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1139
040d2baa 1140 if (HAS_L3_DPF(dev))
35a85ac6 1141 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1142
7225342a 1143 return init_workarounds_ring(ring);
8187a2b7
ZN		 1144}
1145
a4872ba6 1146static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1147{
b45305fc 1148 struct drm_device *dev = ring->dev;
3e78998a
BW		 1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150
1151 if (dev_priv->semaphore_obj) {
1152 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1153 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1154 dev_priv->semaphore_obj = NULL;
1155 }
b45305fc 1156
9b1136d5 1157 intel_fini_pipe_control(ring);
c6df541c
CW		 1158}
1159
3e78998a
BW		 1160static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1161 unsigned int num_dwords)
1162{
1163#define MBOX_UPDATE_DWORDS 8
1164 struct drm_device *dev = signaller->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 struct intel_engine_cs *waiter;
1167 int i, ret, num_rings;
1168
1169 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1170 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1171#undef MBOX_UPDATE_DWORDS
1172
1173 ret = intel_ring_begin(signaller, num_dwords);
1174 if (ret)
1175 return ret;
1176
1177 for_each_ring(waiter, dev_priv, i) {
6259cead 1178 u32 seqno;
3e78998a
BW		 1179 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1180 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1181 continue;
1182
6259cead
JH		 1183 seqno = i915_gem_request_get_seqno(
1184 signaller->outstanding_lazy_request);
3e78998a
BW		 1185 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1186 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1187 PIPE_CONTROL_QW_WRITE |
1188 PIPE_CONTROL_FLUSH_ENABLE);
1189 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1190 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1191 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1192 intel_ring_emit(signaller, 0);
1193 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1194 MI_SEMAPHORE_TARGET(waiter->id));
1195 intel_ring_emit(signaller, 0);
1196 }
1197
1198 return 0;
1199}
1200
1201static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1202 unsigned int num_dwords)
1203{
1204#define MBOX_UPDATE_DWORDS 6
1205 struct drm_device *dev = signaller->dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 struct intel_engine_cs *waiter;
1208 int i, ret, num_rings;
1209
1210 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1211 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1212#undef MBOX_UPDATE_DWORDS
1213
1214 ret = intel_ring_begin(signaller, num_dwords);
1215 if (ret)
1216 return ret;
1217
1218 for_each_ring(waiter, dev_priv, i) {
6259cead 1219 u32 seqno;
3e78998a
BW		 1220 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1221 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1222 continue;
1223
6259cead
JH		 1224 seqno = i915_gem_request_get_seqno(
1225 signaller->outstanding_lazy_request);
3e78998a
BW		 1226 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1227 MI_FLUSH_DW_OP_STOREDW);
1228 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1229 MI_FLUSH_DW_USE_GTT);
1230 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1231 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1232 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1233 MI_SEMAPHORE_TARGET(waiter->id));
1234 intel_ring_emit(signaller, 0);
1235 }
1236
1237 return 0;
1238}
1239
a4872ba6 1240static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1241 unsigned int num_dwords)
1ec14ad3 1242{
024a43e1
BW		 1243 struct drm_device *dev = signaller->dev;
1244 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1245 struct intel_engine_cs *useless;
a1444b79 1246 int i, ret, num_rings;
78325f2d 1247
a1444b79
BW		 1248#define MBOX_UPDATE_DWORDS 3
1249 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1250 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1251#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1252
1253 ret = intel_ring_begin(signaller, num_dwords);
1254 if (ret)
1255 return ret;
024a43e1 1256
78325f2d
BW		 1257 for_each_ring(useless, dev_priv, i) {
1258 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1259 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1260 u32 seqno = i915_gem_request_get_seqno(
1261 signaller->outstanding_lazy_request);
78325f2d
BW		 1262 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1263 intel_ring_emit(signaller, mbox_reg);
6259cead 1264 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1265 }
1266 }
024a43e1 1267
a1444b79
BW		 1268 /* If num_dwords was rounded, make sure the tail pointer is correct */
1269 if (num_rings % 2 == 0)
1270 intel_ring_emit(signaller, MI_NOOP);
1271
024a43e1 1272 return 0;
1ec14ad3
CW		 1273}
1274
c8c99b0f
BW		 1275/**
1276 * gen6_add_request - Update the semaphore mailbox registers
1277 *
1278 * @ring - ring that is adding a request
1279 * @seqno - return seqno stuck into the ring
1280 *
1281 * Update the mailbox registers in the *other* rings with the current seqno.
1282 * This acts like a signal in the canonical semaphore.
1283 */
1ec14ad3 1284static int
a4872ba6 1285gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1286{
024a43e1 1287 int ret;
52ed2325 1288
707d9cf9
BW		 1289 if (ring->semaphore.signal)
1290 ret = ring->semaphore.signal(ring, 4);
1291 else
1292 ret = intel_ring_begin(ring, 4);
1293
1ec14ad3
CW		 1294 if (ret)
1295 return ret;
1296
1ec14ad3
CW		 1297 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1298 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1299 intel_ring_emit(ring,
1300 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1301 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1302 __intel_ring_advance(ring);
1ec14ad3 1303
1ec14ad3
CW		 1304 return 0;
1305}
1306
f72b3435
MK		 1307static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1308 u32 seqno)
1309{
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 return dev_priv->last_seqno < seqno;
1312}
1313
c8c99b0f
BW		 1314/**
1315 * intel_ring_sync - sync the waiter to the signaller on seqno
1316 *
1317 * @waiter - ring that is waiting
1318 * @signaller - ring which has, or will signal
1319 * @seqno - seqno which the waiter will block on
1320 */
5ee426ca
BW		 1321
1322static int
1323gen8_ring_sync(struct intel_engine_cs *waiter,
1324 struct intel_engine_cs *signaller,
1325 u32 seqno)
1326{
1327 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1328 int ret;
1329
1330 ret = intel_ring_begin(waiter, 4);
1331 if (ret)
1332 return ret;
1333
1334 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1335 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1336 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1337 MI_SEMAPHORE_SAD_GTE_SDD);
1338 intel_ring_emit(waiter, seqno);
1339 intel_ring_emit(waiter,
1340 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1341 intel_ring_emit(waiter,
1342 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1343 intel_ring_advance(waiter);
1344 return 0;
1345}
1346
c8c99b0f 1347static int
a4872ba6
OM		 1348gen6_ring_sync(struct intel_engine_cs *waiter,
1349 struct intel_engine_cs *signaller,
686cb5f9 1350 u32 seqno)
1ec14ad3 1351{
c8c99b0f
BW		 1352 u32 dw1 = MI_SEMAPHORE_MBOX |
1353 MI_SEMAPHORE_COMPARE |
1354 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1355 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1356 int ret;
1ec14ad3 1357
1500f7ea
BW		 1358 /* Throughout all of the GEM code, seqno passed implies our current
1359 * seqno is >= the last seqno executed. However for hardware the
1360 * comparison is strictly greater than.
1361 */
1362 seqno -= 1;
1363
ebc348b2 1364 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1365
c8c99b0f 1366 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1367 if (ret)
1368 return ret;
1369
f72b3435
MK		 1370 /* If seqno wrap happened, omit the wait with no-ops */
1371 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1372 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1373 intel_ring_emit(waiter, seqno);
1374 intel_ring_emit(waiter, 0);
1375 intel_ring_emit(waiter, MI_NOOP);
1376 } else {
1377 intel_ring_emit(waiter, MI_NOOP);
1378 intel_ring_emit(waiter, MI_NOOP);
1379 intel_ring_emit(waiter, MI_NOOP);
1380 intel_ring_emit(waiter, MI_NOOP);
1381 }
c8c99b0f 1382 intel_ring_advance(waiter);
1ec14ad3
CW		 1383
1384 return 0;
1385}
1386
c6df541c
CW		 1387#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1388do { \
fcbc34e4
KG		 1389 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1390 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1391 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1392 intel_ring_emit(ring__, 0); \
1393 intel_ring_emit(ring__, 0); \
1394} while (0)
1395
1396static int
a4872ba6 1397pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1398{
18393f63 1399 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1400 int ret;
1401
1402 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1403 * incoherent with writes to memory, i.e. completely fubar,
1404 * so we need to use PIPE_NOTIFY instead.
1405 *
1406 * However, we also need to workaround the qword write
1407 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1408 * memory before requesting an interrupt.
1409 */
1410 ret = intel_ring_begin(ring, 32);
1411 if (ret)
1412 return ret;
1413
fcbc34e4 1414 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1415 PIPE_CONTROL_WRITE_FLUSH |
1416 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1417 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1418 intel_ring_emit(ring,
1419 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1420 intel_ring_emit(ring, 0);
1421 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1422 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1423 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1424 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1425 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1426 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1427 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1428 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1430 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1431 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1432
fcbc34e4 1433 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1434 PIPE_CONTROL_WRITE_FLUSH |
1435 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1436 PIPE_CONTROL_NOTIFY);
0d1aacac 1437 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1438 intel_ring_emit(ring,
1439 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1440 intel_ring_emit(ring, 0);
09246732 1441 __intel_ring_advance(ring);
c6df541c 1442
c6df541c
CW		 1443 return 0;
1444}
1445
4cd53c0c 1446static u32
a4872ba6 1447gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1448{
4cd53c0c
DV		 1449 /* Workaround to force correct ordering between irq and seqno writes on
1450 * ivb (and maybe also on snb) by reading from a CS register (like
1451 * ACTHD) before reading the status page. */
50877445
CW		 1452 if (!lazy_coherency) {
1453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1454 POSTING_READ(RING_ACTHD(ring->mmio_base));
1455 }
1456
4cd53c0c
DV		 1457 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1458}
1459
8187a2b7 1460static u32
a4872ba6 1461ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1462{
1ec14ad3
CW		 1463 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1464}
1465
b70ec5bf 1466static void
a4872ba6 1467ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1468{
1469 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1470}
1471
c6df541c 1472static u32
a4872ba6 1473pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1474{
0d1aacac 1475 return ring->scratch.cpu_page[0];
c6df541c
CW		 1476}
1477
b70ec5bf 1478static void
a4872ba6 1479pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1480{
0d1aacac 1481 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1482}
1483
e48d8634 1484static bool
a4872ba6 1485gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1486{
1487 struct drm_device *dev = ring->dev;
4640c4ff 1488 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1489 unsigned long flags;
e48d8634 1490
7cd512f1 1491 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1492 return false;
1493
7338aefa 1494 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1495 if (ring->irq_refcount++ == 0)
480c8033 1496 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1497 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1498
1499 return true;
1500}
1501
1502static void
a4872ba6 1503gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1504{
1505 struct drm_device *dev = ring->dev;
4640c4ff 1506 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1507 unsigned long flags;
e48d8634 1508
7338aefa 1509 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1510 if (--ring->irq_refcount == 0)
480c8033 1511 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1512 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1513}
1514
b13c2b96 1515static bool
a4872ba6 1516i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1517{
78501eac 1518 struct drm_device *dev = ring->dev;
4640c4ff 1519 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1520 unsigned long flags;
62fdfeaf 1521
7cd512f1 1522 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1523 return false;
1524
7338aefa 1525 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1526 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1527 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1528 I915_WRITE(IMR, dev_priv->irq_mask);
1529 POSTING_READ(IMR);
1530 }
7338aefa 1531 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1532
1533 return true;
62fdfeaf
EA		 1534}
1535
8187a2b7 1536static void
a4872ba6 1537i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1538{
78501eac 1539 struct drm_device *dev = ring->dev;
4640c4ff 1540 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1541 unsigned long flags;
62fdfeaf 1542
7338aefa 1543 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1544 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1545 dev_priv->irq_mask |= ring->irq_enable_mask;
1546 I915_WRITE(IMR, dev_priv->irq_mask);
1547 POSTING_READ(IMR);
1548 }
7338aefa 1549 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1550}
1551
c2798b19 1552static bool
a4872ba6 1553i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1554{
1555 struct drm_device *dev = ring->dev;
4640c4ff 1556 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1557 unsigned long flags;
c2798b19 1558
7cd512f1 1559 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1560 return false;
1561
7338aefa 1562 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1563 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1564 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1565 I915_WRITE16(IMR, dev_priv->irq_mask);
1566 POSTING_READ16(IMR);
1567 }
7338aefa 1568 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1569
1570 return true;
1571}
1572
1573static void
a4872ba6 1574i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1575{
1576 struct drm_device *dev = ring->dev;
4640c4ff 1577 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1578 unsigned long flags;
c2798b19 1579
7338aefa 1580 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1581 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1582 dev_priv->irq_mask |= ring->irq_enable_mask;
1583 I915_WRITE16(IMR, dev_priv->irq_mask);
1584 POSTING_READ16(IMR);
1585 }
7338aefa 1586 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1587}
1588
b72f3acb 1589static int
a4872ba6 1590bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1591 u32 invalidate_domains,
1592 u32 flush_domains)
d1b851fc 1593{
b72f3acb
CW		 1594 int ret;
1595
b72f3acb
CW		 1596 ret = intel_ring_begin(ring, 2);
1597 if (ret)
1598 return ret;
1599
1600 intel_ring_emit(ring, MI_FLUSH);
1601 intel_ring_emit(ring, MI_NOOP);
1602 intel_ring_advance(ring);
1603 return 0;
d1b851fc
ZN		 1604}
1605
3cce469c 1606static int
a4872ba6 1607i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1608{
3cce469c
CW		 1609 int ret;
1610
1611 ret = intel_ring_begin(ring, 4);
1612 if (ret)
1613 return ret;
6f392d54 1614
3cce469c
CW		 1615 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1616 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1617 intel_ring_emit(ring,
1618 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1619 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1620 __intel_ring_advance(ring);
d1b851fc 1621
3cce469c 1622 return 0;
d1b851fc
ZN		 1623}
1624
0f46832f 1625static bool
a4872ba6 1626gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1627{
1628 struct drm_device *dev = ring->dev;
4640c4ff 1629 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1630 unsigned long flags;
0f46832f 1631
7cd512f1
DV		 1632 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1633 return false;
0f46832f 1634
7338aefa 1635 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1636 if (ring->irq_refcount++ == 0) {
040d2baa 1637 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1638 I915_WRITE_IMR(ring,
1639 ~(ring->irq_enable_mask |
35a85ac6 1640 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1641 else
1642 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1643 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1644 }
7338aefa 1645 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1646
1647 return true;
1648}
1649
1650static void
a4872ba6 1651gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1652{
1653 struct drm_device *dev = ring->dev;
4640c4ff 1654 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1655 unsigned long flags;
0f46832f 1656
7338aefa 1657 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1658 if (--ring->irq_refcount == 0) {
040d2baa 1659 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1660 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1661 else
1662 I915_WRITE_IMR(ring, ~0);
480c8033 1663 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1664 }
7338aefa 1665 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1666}
1667
a19d2933 1668static bool
a4872ba6 1669hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1670{
1671 struct drm_device *dev = ring->dev;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 unsigned long flags;
1674
7cd512f1 1675 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1676 return false;
1677
59cdb63d 1678 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1679 if (ring->irq_refcount++ == 0) {
a19d2933 1680 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1681 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1682 }
59cdb63d 1683 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1684
1685 return true;
1686}
1687
1688static void
a4872ba6 1689hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1690{
1691 struct drm_device *dev = ring->dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 unsigned long flags;
1694
59cdb63d 1695 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1696 if (--ring->irq_refcount == 0) {
a19d2933 1697 I915_WRITE_IMR(ring, ~0);
480c8033 1698 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1699 }
59cdb63d 1700 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1701}
1702
abd58f01 1703static bool
a4872ba6 1704gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1705{
1706 struct drm_device *dev = ring->dev;
1707 struct drm_i915_private *dev_priv = dev->dev_private;
1708 unsigned long flags;
1709
7cd512f1 1710 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1711 return false;
1712
1713 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1714 if (ring->irq_refcount++ == 0) {
1715 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1716 I915_WRITE_IMR(ring,
1717 ~(ring->irq_enable_mask |
1718 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1719 } else {
1720 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1721 }
1722 POSTING_READ(RING_IMR(ring->mmio_base));
1723 }
1724 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1725
1726 return true;
1727}
1728
1729static void
a4872ba6 1730gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1731{
1732 struct drm_device *dev = ring->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734 unsigned long flags;
1735
1736 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1737 if (--ring->irq_refcount == 0) {
1738 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1739 I915_WRITE_IMR(ring,
1740 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1741 } else {
1742 I915_WRITE_IMR(ring, ~0);
1743 }
1744 POSTING_READ(RING_IMR(ring->mmio_base));
1745 }
1746 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1747}
1748
d1b851fc 1749static int
a4872ba6 1750i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1751 u64 offset, u32 length,
8e004efc 1752 unsigned dispatch_flags)
d1b851fc 1753{
e1f99ce6 1754 int ret;
78501eac 1755
e1f99ce6
CW		 1756 ret = intel_ring_begin(ring, 2);
1757 if (ret)
1758 return ret;
1759
78501eac 1760 intel_ring_emit(ring,
65f56876
CW		 1761 MI_BATCH_BUFFER_START |
1762 MI_BATCH_GTT |
8e004efc
JH		 1763 (dispatch_flags & I915_DISPATCH_SECURE ?
1764 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1765 intel_ring_emit(ring, offset);
78501eac
CW		 1766 intel_ring_advance(ring);
1767
d1b851fc
ZN		 1768 return 0;
1769}
1770
b45305fc
DV		 1771/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1772#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1773#define I830_TLB_ENTRIES (2)
1774#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1775static int
a4872ba6 1776i830_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 1777 u64 offset, u32 len,
1778 unsigned dispatch_flags)
62fdfeaf 1779{
c4d69da1 1780 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1781 int ret;
62fdfeaf 1782
c4d69da1
CW		 1783 ret = intel_ring_begin(ring, 6);
1784 if (ret)
1785 return ret;
62fdfeaf 1786
c4d69da1
CW		 1787 /* Evict the invalid PTE TLBs */
1788 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1789 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1790 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1791 intel_ring_emit(ring, cs_offset);
1792 intel_ring_emit(ring, 0xdeadbeef);
1793 intel_ring_emit(ring, MI_NOOP);
1794 intel_ring_advance(ring);
b45305fc 1795
8e004efc 1796 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1797 if (len > I830_BATCH_LIMIT)
1798 return -ENOSPC;
1799
c4d69da1 1800 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1801 if (ret)
1802 return ret;
c4d69da1
CW		 1803
1804 /* Blit the batch (which has now all relocs applied) to the
1805 * stable batch scratch bo area (so that the CS never
1806 * stumbles over its tlb invalidation bug) ...
1807 */
1808 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1809 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1810 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1811 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1812 intel_ring_emit(ring, 4096);
1813 intel_ring_emit(ring, offset);
c4d69da1 1814
b45305fc 1815 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1816 intel_ring_emit(ring, MI_NOOP);
1817 intel_ring_advance(ring);
b45305fc
DV		 1818
1819 /* ... and execute it. */
c4d69da1 1820 offset = cs_offset;
b45305fc 1821 }
e1f99ce6 1822
c4d69da1
CW		 1823 ret = intel_ring_begin(ring, 4);
1824 if (ret)
1825 return ret;
1826
1827 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1828 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1829 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1830 intel_ring_emit(ring, offset + len - 8);
1831 intel_ring_emit(ring, MI_NOOP);
1832 intel_ring_advance(ring);
1833
fb3256da
DV		 1834 return 0;
1835}
1836
1837static int
a4872ba6 1838i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1839 u64 offset, u32 len,
8e004efc 1840 unsigned dispatch_flags)
fb3256da
DV		 1841{
1842 int ret;
1843
1844 ret = intel_ring_begin(ring, 2);
1845 if (ret)
1846 return ret;
1847
65f56876 1848 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1849 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1850 0 : MI_BATCH_NON_SECURE));
c4e7a414 1851 intel_ring_advance(ring);
62fdfeaf 1852
62fdfeaf
EA		 1853 return 0;
1854}
1855
a4872ba6 1856static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1857{
05394f39 1858 struct drm_i915_gem_object *obj;
62fdfeaf 1859
8187a2b7
ZN		 1860 obj = ring->status_page.obj;
1861 if (obj == NULL)
62fdfeaf 1862 return;
62fdfeaf 1863
9da3da66 1864 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1865 i915_gem_object_ggtt_unpin(obj);
05394f39 1866 drm_gem_object_unreference(&obj->base);
8187a2b7 1867 ring->status_page.obj = NULL;
62fdfeaf
EA		 1868}
1869
a4872ba6 1870static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1871{
05394f39 1872 struct drm_i915_gem_object *obj;
62fdfeaf 1873
e3efda49 1874 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1875 unsigned flags;
e3efda49 1876 int ret;
e4ffd173 1877
e3efda49
CW		 1878 obj = i915_gem_alloc_object(ring->dev, 4096);
1879 if (obj == NULL) {
1880 DRM_ERROR("Failed to allocate status page\n");
1881 return -ENOMEM;
1882 }
62fdfeaf 1883
e3efda49
CW		 1884 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1885 if (ret)
1886 goto err_unref;
1887
1f767e02
CW		 1888 flags = 0;
1889 if (!HAS_LLC(ring->dev))
1890 /* On g33, we cannot place HWS above 256MiB, so
1891 * restrict its pinning to the low mappable arena.
1892 * Though this restriction is not documented for
1893 * gen4, gen5, or byt, they also behave similarly
1894 * and hang if the HWS is placed at the top of the
1895 * GTT. To generalise, it appears that all !llc
1896 * platforms have issues with us placing the HWS
1897 * above the mappable region (even though we never
1898 * actualy map it).
1899 */
1900 flags |= PIN_MAPPABLE;
1901 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1902 if (ret) {
1903err_unref:
1904 drm_gem_object_unreference(&obj->base);
1905 return ret;
1906 }
1907
1908 ring->status_page.obj = obj;
1909 }
62fdfeaf 1910
f343c5f6 1911 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1912 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1913 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1914
8187a2b7
ZN		 1915 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1916 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1917
1918 return 0;
62fdfeaf
EA		 1919}
1920
a4872ba6 1921static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1922{
1923 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1924
1925 if (!dev_priv->status_page_dmah) {
1926 dev_priv->status_page_dmah =
1927 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1928 if (!dev_priv->status_page_dmah)
1929 return -ENOMEM;
1930 }
1931
6b8294a4
CW		 1932 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1933 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1934
1935 return 0;
1936}
1937
7ba717cf 1938void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1939{
2919d291 1940 iounmap(ringbuf->virtual_start);
7ba717cf 1941 ringbuf->virtual_start = NULL;
2919d291 1942 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1943}
1944
1945int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1946 struct intel_ringbuffer *ringbuf)
1947{
1948 struct drm_i915_private *dev_priv = to_i915(dev);
1949 struct drm_i915_gem_object *obj = ringbuf->obj;
1950 int ret;
1951
1952 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1953 if (ret)
1954 return ret;
1955
1956 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1957 if (ret) {
1958 i915_gem_object_ggtt_unpin(obj);
1959 return ret;
1960 }
1961
1962 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1963 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1964 if (ringbuf->virtual_start == NULL) {
1965 i915_gem_object_ggtt_unpin(obj);
1966 return -EINVAL;
1967 }
1968
1969 return 0;
1970}
1971
1972void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1973{
2919d291
OM		 1974 drm_gem_object_unreference(&ringbuf->obj->base);
1975 ringbuf->obj = NULL;
1976}
1977
84c2377f
OM		 1978int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1979 struct intel_ringbuffer *ringbuf)
62fdfeaf 1980{
05394f39 1981 struct drm_i915_gem_object *obj;
62fdfeaf 1982
ebc052e0
CW		 1983 obj = NULL;
1984 if (!HAS_LLC(dev))
93b0a4e0 1985 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1986 if (obj == NULL)
93b0a4e0 1987 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1988 if (obj == NULL)
1989 return -ENOMEM;
8187a2b7 1990
24f3a8cf
AG		 1991 /* mark ring buffers as read-only from GPU side by default */
1992 obj->gt_ro = 1;
1993
93b0a4e0 1994 ringbuf->obj = obj;
e3efda49 1995
7ba717cf 1996 return 0;
e3efda49
CW		 1997}
1998
1999static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2000 struct intel_engine_cs *ring)
e3efda49 2001{
bfc882b4 2002 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2003 int ret;
2004
bfc882b4
DV		 2005 WARN_ON(ring->buffer);
2006
2007 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2008 if (!ringbuf)
2009 return -ENOMEM;
2010 ring->buffer = ringbuf;
8ee14975 2011
e3efda49
CW		 2012 ring->dev = dev;
2013 INIT_LIST_HEAD(&ring->active_list);
2014 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2015 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2016 i915_gem_batch_pool_init(dev, &ring->batch_pool);
93b0a4e0 2017 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2018 ringbuf->ring = ring;
ebc348b2 2019 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2020
2021 init_waitqueue_head(&ring->irq_queue);
2022
2023 if (I915_NEED_GFX_HWS(dev)) {
2024 ret = init_status_page(ring);
2025 if (ret)
8ee14975 2026 goto error;
e3efda49
CW		 2027 } else {
2028 BUG_ON(ring->id != RCS);
2029 ret = init_phys_status_page(ring);
2030 if (ret)
8ee14975 2031 goto error;
e3efda49
CW		 2032 }
2033
bfc882b4 2034 WARN_ON(ringbuf->obj);
7ba717cf 2035
bfc882b4
DV		 2036 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2037 if (ret) {
2038 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2039 ring->name, ret);
2040 goto error;
2041 }
2042
2043 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2044 if (ret) {
2045 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2046 ring->name, ret);
2047 intel_destroy_ringbuffer_obj(ringbuf);
2048 goto error;
e3efda49 2049 }
62fdfeaf 2050
55249baa
CW		 2051 /* Workaround an erratum on the i830 which causes a hang if
2052 * the TAIL pointer points to within the last 2 cachelines
2053 * of the buffer.
2054 */
93b0a4e0 2055 ringbuf->effective_size = ringbuf->size;
e3efda49 2056 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2057 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2058
44e895a8
BV		 2059 ret = i915_cmd_parser_init_ring(ring);
2060 if (ret)
8ee14975
OM		 2061 goto error;
2062
8ee14975 2063 return 0;
351e3db2 2064
8ee14975
OM		 2065error:
2066 kfree(ringbuf);
2067 ring->buffer = NULL;
2068 return ret;
62fdfeaf
EA		 2069}
2070
a4872ba6 2071void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2072{
6402c330
JH		 2073 struct drm_i915_private *dev_priv;
2074 struct intel_ringbuffer *ringbuf;
33626e6a 2075
93b0a4e0 2076 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2077 return;
2078
6402c330
JH		 2079 dev_priv = to_i915(ring->dev);
2080 ringbuf = ring->buffer;
2081
e3efda49 2082 intel_stop_ring_buffer(ring);
de8f0a50 2083 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2084
7ba717cf 2085 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2086 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2087 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2088
8d19215b
ZN		 2089 if (ring->cleanup)
2090 ring->cleanup(ring);
2091
78501eac 2092 cleanup_status_page(ring);
44e895a8
BV		 2093
2094 i915_cmd_parser_fini_ring(ring);
06fbca71 2095 i915_gem_batch_pool_fini(&ring->batch_pool);
8ee14975 2096
93b0a4e0 2097 kfree(ringbuf);
8ee14975 2098 ring->buffer = NULL;
62fdfeaf
EA		 2099}
2100
595e1eeb 2101static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2102{
93b0a4e0 2103 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2104 struct drm_i915_gem_request *request;
dbe4646d 2105 int ret, new_space;
a71d8d94 2106
ebd0fd4b
DG		 2107 if (intel_ring_space(ringbuf) >= n)
2108 return 0;
a71d8d94
CW		 2109
2110 list_for_each_entry(request, &ring->request_list, list) {
dbe4646d
JH		 2111 new_space = __intel_ring_space(request->postfix, ringbuf->tail,
2112 ringbuf->size);
2113 if (new_space >= n)
a71d8d94 2114 break;
a71d8d94
CW		 2115 }
2116
595e1eeb 2117 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2118 return -ENOSPC;
2119
a4b3a571 2120 ret = i915_wait_request(request);
a71d8d94
CW		 2121 if (ret)
2122 return ret;
2123
1cf0ba14 2124 i915_gem_retire_requests_ring(ring);
a71d8d94 2125
dbe4646d
JH		 2126 WARN_ON(intel_ring_space(ringbuf) < new_space);
2127
a71d8d94
CW		 2128 return 0;
2129}
2130
a4872ba6 2131static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2132{
2133 uint32_t __iomem *virt;
93b0a4e0
OM		 2134 struct intel_ringbuffer *ringbuf = ring->buffer;
2135 int rem = ringbuf->size - ringbuf->tail;
3e960501 2136
93b0a4e0 2137 if (ringbuf->space < rem) {
3e960501
CW		 2138 int ret = ring_wait_for_space(ring, rem);
2139 if (ret)
2140 return ret;
2141 }
2142
93b0a4e0 2143 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2144 rem /= 4;
2145 while (rem--)
2146 iowrite32(MI_NOOP, virt++);
2147
93b0a4e0 2148 ringbuf->tail = 0;
ebd0fd4b 2149 intel_ring_update_space(ringbuf);
3e960501
CW		 2150
2151 return 0;
2152}
2153
a4872ba6 2154int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2155{
a4b3a571 2156 struct drm_i915_gem_request *req;
3e960501
CW		 2157 int ret;
2158
2159 /* We need to add any requests required to flush the objects and ring */
6259cead 2160 if (ring->outstanding_lazy_request) {
9400ae5c 2161 ret = i915_add_request(ring);
3e960501
CW		 2162 if (ret)
2163 return ret;
2164 }
2165
2166 /* Wait upon the last request to be completed */
2167 if (list_empty(&ring->request_list))
2168 return 0;
2169
a4b3a571 2170 req = list_entry(ring->request_list.prev,
3e960501 2171 struct drm_i915_gem_request,
a4b3a571 2172 list);
3e960501 2173
a4b3a571 2174 return i915_wait_request(req);
3e960501
CW		 2175}
2176
6689cb2b 2177int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2178{
6689cb2b 2179 request->ringbuf = request->ring->buffer;
9eba5d4a 2180 return 0;
9d773091
CW		 2181}
2182
a4872ba6 2183static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2184 int bytes)
cbcc80df 2185{
93b0a4e0 2186 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2187 int ret;
2188
93b0a4e0 2189 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2190 ret = intel_wrap_ring_buffer(ring);
2191 if (unlikely(ret))
2192 return ret;
2193 }
2194
93b0a4e0 2195 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2196 ret = ring_wait_for_space(ring, bytes);
2197 if (unlikely(ret))
2198 return ret;
2199 }
2200
cbcc80df
MK		 2201 return 0;
2202}
2203
a4872ba6 2204int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2205 int num_dwords)
8187a2b7 2206{
4640c4ff 2207 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2208 int ret;
78501eac 2209
33196ded
DV		 2210 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2211 dev_priv->mm.interruptible);
de2b9985
DV		 2212 if (ret)
2213 return ret;
21dd3734 2214
304d695c
CW		 2215 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2216 if (ret)
2217 return ret;
2218
9d773091 2219 /* Preallocate the olr before touching the ring */
6689cb2b 2220 ret = i915_gem_request_alloc(ring, ring->default_context);
9d773091
CW		 2221 if (ret)
2222 return ret;
2223
ee1b1e5e 2224 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2225 return 0;
8187a2b7 2226}
78501eac 2227
753b1ad4 2228/* Align the ring tail to a cacheline boundary */
a4872ba6 2229int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2230{
ee1b1e5e 2231 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2232 int ret;
2233
2234 if (num_dwords == 0)
2235 return 0;
2236
18393f63 2237 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2238 ret = intel_ring_begin(ring, num_dwords);
2239 if (ret)
2240 return ret;
2241
2242 while (num_dwords--)
2243 intel_ring_emit(ring, MI_NOOP);
2244
2245 intel_ring_advance(ring);
2246
2247 return 0;
2248}
2249
a4872ba6 2250void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2251{
3b2cc8ab
OM		 2252 struct drm_device *dev = ring->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2254
6259cead 2255 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2256
3b2cc8ab 2257 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2258 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2259 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2260 if (HAS_VEBOX(dev))
5020150b 2261 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2262 }
d97ed339 2263
f7e98ad4 2264 ring->set_seqno(ring, seqno);
92cab734 2265 ring->hangcheck.seqno = seqno;
8187a2b7 2266}
62fdfeaf 2267
a4872ba6 2268static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2269 u32 value)
881f47b6 2270{
4640c4ff 2271 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2272
2273 /* Every tail move must follow the sequence below */
12f55818
CW		 2274
2275 /* Disable notification that the ring is IDLE. The GT
2276 * will then assume that it is busy and bring it out of rc6.
2277 */
0206e353 2278 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2279 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2280
2281 /* Clear the context id. Here be magic! */
2282 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2283
12f55818 2284 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2285 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2286 GEN6_BSD_SLEEP_INDICATOR) == 0,
2287 50))
2288 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2289
12f55818 2290 /* Now that the ring is fully powered up, update the tail */
0206e353 2291 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2292 POSTING_READ(RING_TAIL(ring->mmio_base));
2293
2294 /* Let the ring send IDLE messages to the GT again,
2295 * and so let it sleep to conserve power when idle.
2296 */
0206e353 2297 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2298 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2299}
2300
a4872ba6 2301static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2302 u32 invalidate, u32 flush)
881f47b6 2303{
71a77e07 2304 uint32_t cmd;
b72f3acb
CW		 2305 int ret;
2306
b72f3acb
CW		 2307 ret = intel_ring_begin(ring, 4);
2308 if (ret)
2309 return ret;
2310
71a77e07 2311 cmd = MI_FLUSH_DW;
075b3bba
BW		 2312 if (INTEL_INFO(ring->dev)->gen >= 8)
2313 cmd += 1;
f0a1fb10
CW		 2314
2315 /* We always require a command barrier so that subsequent
2316 * commands, such as breadcrumb interrupts, are strictly ordered
2317 * wrt the contents of the write cache being flushed to memory
2318 * (and thus being coherent from the CPU).
2319 */
2320 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2321
9a289771
JB		 2322 /*
2323 * Bspec vol 1c.5 - video engine command streamer:
2324 * "If ENABLED, all TLBs will be invalidated once the flush
2325 * operation is complete. This bit is only valid when the
2326 * Post-Sync Operation field is a value of 1h or 3h."
2327 */
71a77e07 2328 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2329 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2330
71a77e07 2331 intel_ring_emit(ring, cmd);
9a289771 2332 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2333 if (INTEL_INFO(ring->dev)->gen >= 8) {
2334 intel_ring_emit(ring, 0); /* upper addr */
2335 intel_ring_emit(ring, 0); /* value */
2336 } else {
2337 intel_ring_emit(ring, 0);
2338 intel_ring_emit(ring, MI_NOOP);
2339 }
b72f3acb
CW		 2340 intel_ring_advance(ring);
2341 return 0;
881f47b6
XH		 2342}
2343
1c7a0623 2344static int
a4872ba6 2345gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2346 u64 offset, u32 len,
8e004efc 2347 unsigned dispatch_flags)
1c7a0623 2348{
8e004efc
JH		 2349 bool ppgtt = USES_PPGTT(ring->dev) &&
2350 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2351 int ret;
2352
2353 ret = intel_ring_begin(ring, 4);
2354 if (ret)
2355 return ret;
2356
2357 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2358 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2359 intel_ring_emit(ring, lower_32_bits(offset));
2360 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2361 intel_ring_emit(ring, MI_NOOP);
2362 intel_ring_advance(ring);
2363
2364 return 0;
2365}
2366
d7d4eedd 2367static int
a4872ba6 2368hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 2369 u64 offset, u32 len,
2370 unsigned dispatch_flags)
d7d4eedd
CW		 2371{
2372 int ret;
2373
2374 ret = intel_ring_begin(ring, 2);
2375 if (ret)
2376 return ret;
2377
2378 intel_ring_emit(ring,
77072258 2379 MI_BATCH_BUFFER_START |
8e004efc 2380 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2381 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2382 /* bit0-7 is the length on GEN6+ */
2383 intel_ring_emit(ring, offset);
2384 intel_ring_advance(ring);
2385
2386 return 0;
2387}
2388
881f47b6 2389static int
a4872ba6 2390gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2391 u64 offset, u32 len,
8e004efc 2392 unsigned dispatch_flags)
881f47b6 2393{
0206e353 2394 int ret;
ab6f8e32 2395
0206e353
AJ		 2396 ret = intel_ring_begin(ring, 2);
2397 if (ret)
2398 return ret;
e1f99ce6 2399
d7d4eedd
CW		 2400 intel_ring_emit(ring,
2401 MI_BATCH_BUFFER_START |
8e004efc
JH		 2402 (dispatch_flags & I915_DISPATCH_SECURE ?
2403 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2404 /* bit0-7 is the length on GEN6+ */
2405 intel_ring_emit(ring, offset);
2406 intel_ring_advance(ring);
ab6f8e32 2407
0206e353 2408 return 0;
881f47b6
XH		 2409}
2410
549f7365
CW		 2411/* Blitter support (SandyBridge+) */
2412
a4872ba6 2413static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2414 u32 invalidate, u32 flush)
8d19215b 2415{
fd3da6c9 2416 struct drm_device *dev = ring->dev;
71a77e07 2417 uint32_t cmd;
b72f3acb
CW		 2418 int ret;
2419
6a233c78 2420 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2421 if (ret)
2422 return ret;
2423
71a77e07 2424 cmd = MI_FLUSH_DW;
dbef0f15 2425 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2426 cmd += 1;
f0a1fb10
CW		 2427
2428 /* We always require a command barrier so that subsequent
2429 * commands, such as breadcrumb interrupts, are strictly ordered
2430 * wrt the contents of the write cache being flushed to memory
2431 * (and thus being coherent from the CPU).
2432 */
2433 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2434
9a289771
JB		 2435 /*
2436 * Bspec vol 1c.3 - blitter engine command streamer:
2437 * "If ENABLED, all TLBs will be invalidated once the flush
2438 * operation is complete. This bit is only valid when the
2439 * Post-Sync Operation field is a value of 1h or 3h."
2440 */
71a77e07 2441 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2442 cmd |= MI_INVALIDATE_TLB;
71a77e07 2443 intel_ring_emit(ring, cmd);
9a289771 2444 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2445 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2446 intel_ring_emit(ring, 0); /* upper addr */
2447 intel_ring_emit(ring, 0); /* value */
2448 } else {
2449 intel_ring_emit(ring, 0);
2450 intel_ring_emit(ring, MI_NOOP);
2451 }
b72f3acb 2452 intel_ring_advance(ring);
fd3da6c9 2453
b72f3acb 2454 return 0;
8d19215b
ZN		 2455}
2456
5c1143bb
XH		 2457int intel_init_render_ring_buffer(struct drm_device *dev)
2458{
4640c4ff 2459 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2460 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2461 struct drm_i915_gem_object *obj;
2462 int ret;
5c1143bb 2463
59465b5f
DV		 2464 ring->name = "render ring";
2465 ring->id = RCS;
2466 ring->mmio_base = RENDER_RING_BASE;
2467
707d9cf9 2468 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2469 if (i915_semaphore_is_enabled(dev)) {
2470 obj = i915_gem_alloc_object(dev, 4096);
2471 if (obj == NULL) {
2472 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2473 i915.semaphores = 0;
2474 } else {
2475 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2476 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2477 if (ret != 0) {
2478 drm_gem_object_unreference(&obj->base);
2479 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2480 i915.semaphores = 0;
2481 } else
2482 dev_priv->semaphore_obj = obj;
2483 }
2484 }
7225342a 2485
8f0e2b9d 2486 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2487 ring->add_request = gen6_add_request;
2488 ring->flush = gen8_render_ring_flush;
2489 ring->irq_get = gen8_ring_get_irq;
2490 ring->irq_put = gen8_ring_put_irq;
2491 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2492 ring->get_seqno = gen6_ring_get_seqno;
2493 ring->set_seqno = ring_set_seqno;
2494 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2495 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2496 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2497 ring->semaphore.signal = gen8_rcs_signal;
2498 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2499 }
2500 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2501 ring->add_request = gen6_add_request;
4772eaeb 2502 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2503 if (INTEL_INFO(dev)->gen == 6)
b3111509 2504 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2505 ring->irq_get = gen6_ring_get_irq;
2506 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2507 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2508 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2509 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2510 if (i915_semaphore_is_enabled(dev)) {
2511 ring->semaphore.sync_to = gen6_ring_sync;
2512 ring->semaphore.signal = gen6_signal;
2513 /*
2514 * The current semaphore is only applied on pre-gen8
2515 * platform. And there is no VCS2 ring on the pre-gen8
2516 * platform. So the semaphore between RCS and VCS2 is
2517 * initialized as INVALID. Gen8 will initialize the
2518 * sema between VCS2 and RCS later.
2519 */
2520 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2521 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2522 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2523 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2524 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2525 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2526 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2527 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2528 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2529 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2530 }
c6df541c
CW		 2531 } else if (IS_GEN5(dev)) {
2532 ring->add_request = pc_render_add_request;
46f0f8d1 2533 ring->flush = gen4_render_ring_flush;
c6df541c 2534 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2535 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2536 ring->irq_get = gen5_ring_get_irq;
2537 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2538 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2539 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2540 } else {
8620a3a9 2541 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2542 if (INTEL_INFO(dev)->gen < 4)
2543 ring->flush = gen2_render_ring_flush;
2544 else
2545 ring->flush = gen4_render_ring_flush;
59465b5f 2546 ring->get_seqno = ring_get_seqno;
b70ec5bf 2547 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2548 if (IS_GEN2(dev)) {
2549 ring->irq_get = i8xx_ring_get_irq;
2550 ring->irq_put = i8xx_ring_put_irq;
2551 } else {
2552 ring->irq_get = i9xx_ring_get_irq;
2553 ring->irq_put = i9xx_ring_put_irq;
2554 }
e3670319 2555 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2556 }
59465b5f 2557 ring->write_tail = ring_write_tail;
707d9cf9 2558
d7d4eedd
CW		 2559 if (IS_HASWELL(dev))
2560 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2561 else if (IS_GEN8(dev))
2562 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2563 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2564 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2565 else if (INTEL_INFO(dev)->gen >= 4)
2566 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2567 else if (IS_I830(dev) || IS_845G(dev))
2568 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2569 else
2570 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2571 ring->init_hw = init_render_ring;
59465b5f
DV		 2572 ring->cleanup = render_ring_cleanup;
2573
b45305fc
DV		 2574 /* Workaround batchbuffer to combat CS tlb bug. */
2575 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2576 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2577 if (obj == NULL) {
2578 DRM_ERROR("Failed to allocate batch bo\n");
2579 return -ENOMEM;
2580 }
2581
be1fa129 2582 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2583 if (ret != 0) {
2584 drm_gem_object_unreference(&obj->base);
2585 DRM_ERROR("Failed to ping batch bo\n");
2586 return ret;
2587 }
2588
0d1aacac
CW		 2589 ring->scratch.obj = obj;
2590 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2591 }
2592
99be1dfe
DV		 2593 ret = intel_init_ring_buffer(dev, ring);
2594 if (ret)
2595 return ret;
2596
2597 if (INTEL_INFO(dev)->gen >= 5) {
2598 ret = intel_init_pipe_control(ring);
2599 if (ret)
2600 return ret;
2601 }
2602
2603 return 0;
5c1143bb
XH		 2604}
2605
2606int intel_init_bsd_ring_buffer(struct drm_device *dev)
2607{
4640c4ff 2608 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2609 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2610
58fa3835
DV		 2611 ring->name = "bsd ring";
2612 ring->id = VCS;
2613
0fd2c201 2614 ring->write_tail = ring_write_tail;
780f18c8 2615 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2616 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2617 /* gen6 bsd needs a special wa for tail updates */
2618 if (IS_GEN6(dev))
2619 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2620 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2621 ring->add_request = gen6_add_request;
2622 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2623 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2624 if (INTEL_INFO(dev)->gen >= 8) {
2625 ring->irq_enable_mask =
2626 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2627 ring->irq_get = gen8_ring_get_irq;
2628 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2629 ring->dispatch_execbuffer =
2630 gen8_ring_dispatch_execbuffer;
707d9cf9 2631 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2632 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2633 ring->semaphore.signal = gen8_xcs_signal;
2634 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2635 }
abd58f01
BW		 2636 } else {
2637 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2638 ring->irq_get = gen6_ring_get_irq;
2639 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2640 ring->dispatch_execbuffer =
2641 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2642 if (i915_semaphore_is_enabled(dev)) {
2643 ring->semaphore.sync_to = gen6_ring_sync;
2644 ring->semaphore.signal = gen6_signal;
2645 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2646 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2647 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2648 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2649 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2650 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2651 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2652 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2653 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2654 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2655 }
abd58f01 2656 }
58fa3835
DV		 2657 } else {
2658 ring->mmio_base = BSD_RING_BASE;
58fa3835 2659 ring->flush = bsd_ring_flush;
8620a3a9 2660 ring->add_request = i9xx_add_request;
58fa3835 2661 ring->get_seqno = ring_get_seqno;
b70ec5bf 2662 ring->set_seqno = ring_set_seqno;
e48d8634 2663 if (IS_GEN5(dev)) {
cc609d5d 2664 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2665 ring->irq_get = gen5_ring_get_irq;
2666 ring->irq_put = gen5_ring_put_irq;
2667 } else {
e3670319 2668 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2669 ring->irq_get = i9xx_ring_get_irq;
2670 ring->irq_put = i9xx_ring_put_irq;
2671 }
fb3256da 2672 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2673 }
ecfe00d8 2674 ring->init_hw = init_ring_common;
58fa3835 2675
1ec14ad3 2676 return intel_init_ring_buffer(dev, ring);
5c1143bb 2677}
549f7365 2678
845f74a7 2679/**
62659920 2680 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2681 */
2682int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2683{
2684 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2685 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2686
f7b64236 2687 ring->name = "bsd2 ring";
845f74a7
ZY		 2688 ring->id = VCS2;
2689
2690 ring->write_tail = ring_write_tail;
2691 ring->mmio_base = GEN8_BSD2_RING_BASE;
2692 ring->flush = gen6_bsd_ring_flush;
2693 ring->add_request = gen6_add_request;
2694 ring->get_seqno = gen6_ring_get_seqno;
2695 ring->set_seqno = ring_set_seqno;
2696 ring->irq_enable_mask =
2697 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2698 ring->irq_get = gen8_ring_get_irq;
2699 ring->irq_put = gen8_ring_put_irq;
2700 ring->dispatch_execbuffer =
2701 gen8_ring_dispatch_execbuffer;
3e78998a 2702 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2703 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2704 ring->semaphore.signal = gen8_xcs_signal;
2705 GEN8_RING_SEMAPHORE_INIT;
2706 }
ecfe00d8 2707 ring->init_hw = init_ring_common;
845f74a7
ZY		 2708
2709 return intel_init_ring_buffer(dev, ring);
2710}
2711
549f7365
CW		 2712int intel_init_blt_ring_buffer(struct drm_device *dev)
2713{
4640c4ff 2714 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2715 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2716
3535d9dd
DV		 2717 ring->name = "blitter ring";
2718 ring->id = BCS;
2719
2720 ring->mmio_base = BLT_RING_BASE;
2721 ring->write_tail = ring_write_tail;
ea251324 2722 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2723 ring->add_request = gen6_add_request;
2724 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2725 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2726 if (INTEL_INFO(dev)->gen >= 8) {
2727 ring->irq_enable_mask =
2728 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2729 ring->irq_get = gen8_ring_get_irq;
2730 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2731 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2732 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2733 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2734 ring->semaphore.signal = gen8_xcs_signal;
2735 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2736 }
abd58f01
BW		 2737 } else {
2738 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2739 ring->irq_get = gen6_ring_get_irq;
2740 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2741 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2742 if (i915_semaphore_is_enabled(dev)) {
2743 ring->semaphore.signal = gen6_signal;
2744 ring->semaphore.sync_to = gen6_ring_sync;
2745 /*
2746 * The current semaphore is only applied on pre-gen8
2747 * platform. And there is no VCS2 ring on the pre-gen8
2748 * platform. So the semaphore between BCS and VCS2 is
2749 * initialized as INVALID. Gen8 will initialize the
2750 * sema between BCS and VCS2 later.
2751 */
2752 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2753 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2754 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2755 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2756 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2757 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2758 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2759 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2760 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2761 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2762 }
abd58f01 2763 }
ecfe00d8 2764 ring->init_hw = init_ring_common;
549f7365 2765
1ec14ad3 2766 return intel_init_ring_buffer(dev, ring);
549f7365 2767}
a7b9761d 2768
9a8a2213
BW		 2769int intel_init_vebox_ring_buffer(struct drm_device *dev)
2770{
4640c4ff 2771 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2772 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2773
2774 ring->name = "video enhancement ring";
2775 ring->id = VECS;
2776
2777 ring->mmio_base = VEBOX_RING_BASE;
2778 ring->write_tail = ring_write_tail;
2779 ring->flush = gen6_ring_flush;
2780 ring->add_request = gen6_add_request;
2781 ring->get_seqno = gen6_ring_get_seqno;
2782 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2783
2784 if (INTEL_INFO(dev)->gen >= 8) {
2785 ring->irq_enable_mask =
40c499f9 2786 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2787 ring->irq_get = gen8_ring_get_irq;
2788 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2789 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2790 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2791 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2792 ring->semaphore.signal = gen8_xcs_signal;
2793 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2794 }
abd58f01
BW		 2795 } else {
2796 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2797 ring->irq_get = hsw_vebox_get_irq;
2798 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2799 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2800 if (i915_semaphore_is_enabled(dev)) {
2801 ring->semaphore.sync_to = gen6_ring_sync;
2802 ring->semaphore.signal = gen6_signal;
2803 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2804 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2805 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2806 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2807 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2808 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2809 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2810 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2811 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2812 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2813 }
abd58f01 2814 }
ecfe00d8 2815 ring->init_hw = init_ring_common;
9a8a2213
BW		 2816
2817 return intel_init_ring_buffer(dev, ring);
2818}
2819
a7b9761d 2820int
a4872ba6 2821intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2822{
2823 int ret;
2824
2825 if (!ring->gpu_caches_dirty)
2826 return 0;
2827
2828 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2829 if (ret)
2830 return ret;
2831
2832 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2833
2834 ring->gpu_caches_dirty = false;
2835 return 0;
2836}
2837
2838int
a4872ba6 2839intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2840{
2841 uint32_t flush_domains;
2842 int ret;
2843
2844 flush_domains = 0;
2845 if (ring->gpu_caches_dirty)
2846 flush_domains = I915_GEM_GPU_DOMAINS;
2847
2848 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2849 if (ret)
2850 return ret;
2851
2852 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2853
2854 ring->gpu_caches_dirty = false;
2855 return 0;
2856}
e3efda49
CW		 2857
2858void
a4872ba6 2859intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2860{
2861 int ret;
2862
2863 if (!intel_ring_initialized(ring))
2864 return;
2865
2866 ret = intel_ring_idle(ring);
2867 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2868 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2869 ring->name, ret);
2870
2871 stop_ring(ring);
2872}
Linux kernel - Deliverables
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