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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b72f3acb | 61 | static int |
7c9cf4e3 | 62 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 63 | { |
7e37f889 | 64 | struct intel_ring *ring = req->ring; |
46f0f8d1 CW |
65 | u32 cmd; |
66 | int ret; | |
67 | ||
68 | cmd = MI_FLUSH; | |
46f0f8d1 | 69 | |
7c9cf4e3 | 70 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
71 | cmd |= MI_READ_FLUSH; |
72 | ||
5fb9de1a | 73 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
74 | if (ret) |
75 | return ret; | |
76 | ||
b5321f30 CW |
77 | intel_ring_emit(ring, cmd); |
78 | intel_ring_emit(ring, MI_NOOP); | |
79 | intel_ring_advance(ring); | |
46f0f8d1 CW |
80 | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static int | |
7c9cf4e3 | 85 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 86 | { |
7e37f889 | 87 | struct intel_ring *ring = req->ring; |
6f392d54 | 88 | u32 cmd; |
b72f3acb | 89 | int ret; |
6f392d54 | 90 | |
36d527de CW |
91 | /* |
92 | * read/write caches: | |
93 | * | |
94 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
95 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
96 | * also flushed at 2d versus 3d pipeline switches. | |
97 | * | |
98 | * read-only caches: | |
99 | * | |
100 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
101 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
102 | * | |
103 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
104 | * | |
105 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
106 | * invalidated when MI_EXE_FLUSH is set. | |
107 | * | |
108 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
109 | * invalidated with every MI_FLUSH. | |
110 | * | |
111 | * TLBs: | |
112 | * | |
113 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
114 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
115 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
116 | * are flushed at any MI_FLUSH. | |
117 | */ | |
118 | ||
b5321f30 | 119 | cmd = MI_FLUSH; |
7c9cf4e3 | 120 | if (mode & EMIT_INVALIDATE) { |
36d527de | 121 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
122 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
123 | cmd |= MI_INVALIDATE_ISP; | |
124 | } | |
70eac33e | 125 | |
5fb9de1a | 126 | ret = intel_ring_begin(req, 2); |
36d527de CW |
127 | if (ret) |
128 | return ret; | |
b72f3acb | 129 | |
b5321f30 CW |
130 | intel_ring_emit(ring, cmd); |
131 | intel_ring_emit(ring, MI_NOOP); | |
132 | intel_ring_advance(ring); | |
b72f3acb CW |
133 | |
134 | return 0; | |
8187a2b7 ZN |
135 | } |
136 | ||
8d315287 JB |
137 | /** |
138 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
139 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
140 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
141 | * | |
142 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
143 | * produced by non-pipelined state commands), software needs to first | |
144 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
145 | * 0. | |
146 | * | |
147 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
148 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
149 | * | |
150 | * And the workaround for these two requires this workaround first: | |
151 | * | |
152 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
153 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
154 | * flushes. | |
155 | * | |
156 | * And this last workaround is tricky because of the requirements on | |
157 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
158 | * volume 2 part 1: | |
159 | * | |
160 | * "1 of the following must also be set: | |
161 | * - Render Target Cache Flush Enable ([12] of DW1) | |
162 | * - Depth Cache Flush Enable ([0] of DW1) | |
163 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
164 | * - Depth Stall ([13] of DW1) | |
165 | * - Post-Sync Operation ([13] of DW1) | |
166 | * - Notify Enable ([8] of DW1)" | |
167 | * | |
168 | * The cache flushes require the workaround flush that triggered this | |
169 | * one, so we can't use it. Depth stall would trigger the same. | |
170 | * Post-sync nonzero is what triggered this second workaround, so we | |
171 | * can't use that one either. Notify enable is IRQs, which aren't | |
172 | * really our business. That leaves only stall at scoreboard. | |
173 | */ | |
174 | static int | |
f2cf1fcc | 175 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 176 | { |
7e37f889 | 177 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
178 | u32 scratch_addr = |
179 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
8d315287 JB |
180 | int ret; |
181 | ||
5fb9de1a | 182 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
183 | if (ret) |
184 | return ret; | |
185 | ||
b5321f30 CW |
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
8d315287 | 188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
b5321f30 CW |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
8d315287 | 194 | |
5fb9de1a | 195 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
196 | if (ret) |
197 | return ret; | |
198 | ||
b5321f30 CW |
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
8d315287 JB |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
7c9cf4e3 | 211 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 212 | { |
7e37f889 | 213 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
214 | u32 scratch_addr = |
215 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
8d315287 | 216 | u32 flags = 0; |
8d315287 JB |
217 | int ret; |
218 | ||
b3111509 | 219 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 220 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
221 | if (ret) |
222 | return ret; | |
223 | ||
8d315287 JB |
224 | /* Just flush everything. Experiments have shown that reducing the |
225 | * number of bits based on the write domains has little performance | |
226 | * impact. | |
227 | */ | |
7c9cf4e3 | 228 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
229 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
231 | /* | |
232 | * Ensure that any following seqno writes only happen | |
233 | * when the render cache is indeed flushed. | |
234 | */ | |
97f209bc | 235 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 236 | } |
7c9cf4e3 | 237 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
238 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
239 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
244 | /* | |
245 | * TLB invalidate requires a post-sync write. | |
246 | */ | |
3ac78313 | 247 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 248 | } |
8d315287 | 249 | |
5fb9de1a | 250 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
251 | if (ret) |
252 | return ret; | |
253 | ||
b5321f30 CW |
254 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
255 | intel_ring_emit(ring, flags); | |
256 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | intel_ring_emit(ring, 0); | |
258 | intel_ring_advance(ring); | |
8d315287 JB |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
f3987631 | 263 | static int |
f2cf1fcc | 264 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 265 | { |
7e37f889 | 266 | struct intel_ring *ring = req->ring; |
f3987631 PZ |
267 | int ret; |
268 | ||
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
270 | if (ret) |
271 | return ret; | |
272 | ||
b5321f30 CW |
273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(ring, | |
275 | PIPE_CONTROL_CS_STALL | | |
276 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
277 | intel_ring_emit(ring, 0); | |
278 | intel_ring_emit(ring, 0); | |
279 | intel_ring_advance(ring); | |
f3987631 PZ |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
4772eaeb | 284 | static int |
7c9cf4e3 | 285 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 286 | { |
7e37f889 | 287 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
288 | u32 scratch_addr = |
289 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
4772eaeb | 290 | u32 flags = 0; |
4772eaeb PZ |
291 | int ret; |
292 | ||
f3987631 PZ |
293 | /* |
294 | * Ensure that any following seqno writes only happen when the render | |
295 | * cache is indeed flushed. | |
296 | * | |
297 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
298 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
299 | * don't try to be clever and just set it unconditionally. | |
300 | */ | |
301 | flags |= PIPE_CONTROL_CS_STALL; | |
302 | ||
4772eaeb PZ |
303 | /* Just flush everything. Experiments have shown that reducing the |
304 | * number of bits based on the write domains has little performance | |
305 | * impact. | |
306 | */ | |
7c9cf4e3 | 307 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
308 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
309 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 310 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 311 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 312 | } |
7c9cf4e3 | 313 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
314 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
315 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
316 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
317 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
318 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
319 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 320 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
321 | /* |
322 | * TLB invalidate requires a post-sync write. | |
323 | */ | |
324 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 325 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 326 | |
add284a3 CW |
327 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
328 | ||
f3987631 PZ |
329 | /* Workaround: we must issue a pipe_control with CS-stall bit |
330 | * set before a pipe_control command that has the state cache | |
331 | * invalidate bit set. */ | |
f2cf1fcc | 332 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
333 | } |
334 | ||
5fb9de1a | 335 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
336 | if (ret) |
337 | return ret; | |
338 | ||
b5321f30 CW |
339 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
340 | intel_ring_emit(ring, flags); | |
341 | intel_ring_emit(ring, scratch_addr); | |
342 | intel_ring_emit(ring, 0); | |
343 | intel_ring_advance(ring); | |
4772eaeb PZ |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
884ceace | 348 | static int |
f2cf1fcc | 349 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
350 | u32 flags, u32 scratch_addr) |
351 | { | |
7e37f889 | 352 | struct intel_ring *ring = req->ring; |
884ceace KG |
353 | int ret; |
354 | ||
5fb9de1a | 355 | ret = intel_ring_begin(req, 6); |
884ceace KG |
356 | if (ret) |
357 | return ret; | |
358 | ||
b5321f30 CW |
359 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
360 | intel_ring_emit(ring, flags); | |
361 | intel_ring_emit(ring, scratch_addr); | |
362 | intel_ring_emit(ring, 0); | |
363 | intel_ring_emit(ring, 0); | |
364 | intel_ring_emit(ring, 0); | |
365 | intel_ring_advance(ring); | |
884ceace KG |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
a5f3d68e | 370 | static int |
7c9cf4e3 | 371 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
a5f3d68e | 372 | { |
4a570db5 | 373 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
b5321f30 | 374 | u32 flags = 0; |
02c9f7e3 | 375 | int ret; |
a5f3d68e BW |
376 | |
377 | flags |= PIPE_CONTROL_CS_STALL; | |
378 | ||
7c9cf4e3 | 379 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
380 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
381 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 382 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 383 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 384 | } |
7c9cf4e3 | 385 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
386 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
387 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
388 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
389 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
390 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
391 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
392 | flags |= PIPE_CONTROL_QW_WRITE; | |
393 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
394 | |
395 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 396 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
397 | PIPE_CONTROL_CS_STALL | |
398 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
399 | 0); | |
400 | if (ret) | |
401 | return ret; | |
a5f3d68e BW |
402 | } |
403 | ||
f2cf1fcc | 404 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
405 | } |
406 | ||
7e37f889 | 407 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 408 | { |
c033666a | 409 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 410 | u64 acthd; |
8187a2b7 | 411 | |
c033666a | 412 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
413 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
414 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 415 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 416 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
417 | else |
418 | acthd = I915_READ(ACTHD); | |
419 | ||
420 | return acthd; | |
8187a2b7 ZN |
421 | } |
422 | ||
0bc40be8 | 423 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 424 | { |
c033666a | 425 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
426 | u32 addr; |
427 | ||
428 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 429 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
430 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
431 | I915_WRITE(HWS_PGA, addr); | |
432 | } | |
433 | ||
0bc40be8 | 434 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 435 | { |
c033666a | 436 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 437 | i915_reg_t mmio; |
af75f269 DL |
438 | |
439 | /* The ring status page addresses are no longer next to the rest of | |
440 | * the ring registers as of gen7. | |
441 | */ | |
c033666a | 442 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 443 | switch (engine->id) { |
af75f269 DL |
444 | case RCS: |
445 | mmio = RENDER_HWS_PGA_GEN7; | |
446 | break; | |
447 | case BCS: | |
448 | mmio = BLT_HWS_PGA_GEN7; | |
449 | break; | |
450 | /* | |
451 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
452 | * gcc switch check warning | |
453 | */ | |
454 | case VCS2: | |
455 | case VCS: | |
456 | mmio = BSD_HWS_PGA_GEN7; | |
457 | break; | |
458 | case VECS: | |
459 | mmio = VEBOX_HWS_PGA_GEN7; | |
460 | break; | |
461 | } | |
c033666a | 462 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 463 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
464 | } else { |
465 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 466 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
467 | } |
468 | ||
0bc40be8 | 469 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
470 | POSTING_READ(mmio); |
471 | ||
472 | /* | |
473 | * Flush the TLB for this page | |
474 | * | |
475 | * FIXME: These two bits have disappeared on gen8, so a question | |
476 | * arises: do we still need this and if so how should we go about | |
477 | * invalidating the TLB? | |
478 | */ | |
ac657f64 | 479 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 480 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
481 | |
482 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 483 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
484 | |
485 | I915_WRITE(reg, | |
486 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
487 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
488 | if (intel_wait_for_register(dev_priv, |
489 | reg, INSTPM_SYNC_FLUSH, 0, | |
490 | 1000)) | |
af75f269 | 491 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 492 | engine->name); |
af75f269 DL |
493 | } |
494 | } | |
495 | ||
0bc40be8 | 496 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 497 | { |
c033666a | 498 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 499 | |
c033666a | 500 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 | 501 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
502 | if (intel_wait_for_register(dev_priv, |
503 | RING_MI_MODE(engine->mmio_base), | |
504 | MODE_IDLE, | |
505 | MODE_IDLE, | |
506 | 1000)) { | |
0bc40be8 TU |
507 | DRM_ERROR("%s : timed out trying to stop ring\n", |
508 | engine->name); | |
9bec9b13 CW |
509 | /* Sometimes we observe that the idle flag is not |
510 | * set even though the ring is empty. So double | |
511 | * check before giving up. | |
512 | */ | |
0bc40be8 | 513 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 514 | return false; |
9991ae78 CW |
515 | } |
516 | } | |
b7884eb4 | 517 | |
0bc40be8 TU |
518 | I915_WRITE_CTL(engine, 0); |
519 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 520 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 521 | |
c033666a | 522 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 TU |
523 | (void)I915_READ_CTL(engine); |
524 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 525 | } |
a51435a3 | 526 | |
0bc40be8 | 527 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 528 | } |
8187a2b7 | 529 | |
0bc40be8 | 530 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 531 | { |
c033666a | 532 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 CW |
533 | struct intel_ring *ring = engine->buffer; |
534 | struct drm_i915_gem_object *obj = ring->obj; | |
9991ae78 CW |
535 | int ret = 0; |
536 | ||
59bad947 | 537 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 538 | |
0bc40be8 | 539 | if (!stop_ring(engine)) { |
9991ae78 | 540 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
541 | DRM_DEBUG_KMS("%s head not reset to zero " |
542 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
543 | engine->name, |
544 | I915_READ_CTL(engine), | |
545 | I915_READ_HEAD(engine), | |
546 | I915_READ_TAIL(engine), | |
547 | I915_READ_START(engine)); | |
8187a2b7 | 548 | |
0bc40be8 | 549 | if (!stop_ring(engine)) { |
6fd0d56e CW |
550 | DRM_ERROR("failed to set %s head to zero " |
551 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
552 | engine->name, |
553 | I915_READ_CTL(engine), | |
554 | I915_READ_HEAD(engine), | |
555 | I915_READ_TAIL(engine), | |
556 | I915_READ_START(engine)); | |
9991ae78 CW |
557 | ret = -EIO; |
558 | goto out; | |
6fd0d56e | 559 | } |
8187a2b7 ZN |
560 | } |
561 | ||
c033666a | 562 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 563 | intel_ring_setup_status_page(engine); |
9991ae78 | 564 | else |
0bc40be8 | 565 | ring_setup_phys_status_page(engine); |
9991ae78 | 566 | |
ece4a17d | 567 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 568 | I915_READ_HEAD(engine); |
ece4a17d | 569 | |
0d8957c8 DV |
570 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
571 | * registers with the above sequence (the readback of the HEAD registers | |
572 | * also enforces ordering), otherwise the hw might lose the new ring | |
573 | * register values. */ | |
0bc40be8 | 574 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
575 | |
576 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 577 | if (I915_READ_HEAD(engine)) |
95468892 | 578 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
579 | engine->name, I915_READ_HEAD(engine)); |
580 | I915_WRITE_HEAD(engine, 0); | |
581 | (void)I915_READ_HEAD(engine); | |
95468892 | 582 | |
0bc40be8 | 583 | I915_WRITE_CTL(engine, |
7e37f889 | 584 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 585 | | RING_VALID); |
8187a2b7 | 586 | |
8187a2b7 | 587 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
588 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
589 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
590 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 591 | DRM_ERROR("%s initialization failed " |
48e48a0b | 592 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
593 | engine->name, |
594 | I915_READ_CTL(engine), | |
595 | I915_READ_CTL(engine) & RING_VALID, | |
596 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
597 | I915_READ_START(engine), | |
598 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
599 | ret = -EIO; |
600 | goto out; | |
8187a2b7 ZN |
601 | } |
602 | ||
7e37f889 CW |
603 | ring->last_retired_head = -1; |
604 | ring->head = I915_READ_HEAD(engine); | |
605 | ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
606 | intel_ring_update_space(ring); | |
1ec14ad3 | 607 | |
fc0768ce | 608 | intel_engine_init_hangcheck(engine); |
50f018df | 609 | |
b7884eb4 | 610 | out: |
59bad947 | 611 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
612 | |
613 | return ret; | |
8187a2b7 ZN |
614 | } |
615 | ||
f8291952 | 616 | void intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 617 | { |
0bc40be8 | 618 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
619 | return; |
620 | ||
f8291952 | 621 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
f8c417cd | 622 | i915_gem_object_put(engine->scratch.obj); |
0bc40be8 | 623 | engine->scratch.obj = NULL; |
9b1136d5 OM |
624 | } |
625 | ||
7d5ea807 | 626 | int intel_init_pipe_control(struct intel_engine_cs *engine, int size) |
c6df541c | 627 | { |
f8291952 | 628 | struct drm_i915_gem_object *obj; |
c6df541c CW |
629 | int ret; |
630 | ||
0bc40be8 | 631 | WARN_ON(engine->scratch.obj); |
c6df541c | 632 | |
91c8a326 | 633 | obj = i915_gem_object_create_stolen(&engine->i915->drm, size); |
de8fe166 | 634 | if (!obj) |
91c8a326 | 635 | obj = i915_gem_object_create(&engine->i915->drm, size); |
f8291952 CW |
636 | if (IS_ERR(obj)) { |
637 | DRM_ERROR("Failed to allocate scratch page\n"); | |
638 | ret = PTR_ERR(obj); | |
c6df541c CW |
639 | goto err; |
640 | } | |
e4ffd173 | 641 | |
de895082 | 642 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, PIN_HIGH); |
a9cc726c DV |
643 | if (ret) |
644 | goto err_unref; | |
c6df541c | 645 | |
f8291952 CW |
646 | engine->scratch.obj = obj; |
647 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
2b1086cc | 648 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 649 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
650 | return 0; |
651 | ||
c6df541c | 652 | err_unref: |
f8c417cd | 653 | i915_gem_object_put(engine->scratch.obj); |
c6df541c | 654 | err: |
c6df541c CW |
655 | return ret; |
656 | } | |
657 | ||
e2be4faf | 658 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 659 | { |
7e37f889 | 660 | struct intel_ring *ring = req->ring; |
c033666a CW |
661 | struct i915_workarounds *w = &req->i915->workarounds; |
662 | int ret, i; | |
888b5995 | 663 | |
02235808 | 664 | if (w->count == 0) |
7225342a | 665 | return 0; |
888b5995 | 666 | |
7c9cf4e3 | 667 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
668 | if (ret) |
669 | return ret; | |
888b5995 | 670 | |
5fb9de1a | 671 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
672 | if (ret) |
673 | return ret; | |
674 | ||
b5321f30 | 675 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 676 | for (i = 0; i < w->count; i++) { |
b5321f30 CW |
677 | intel_ring_emit_reg(ring, w->reg[i].addr); |
678 | intel_ring_emit(ring, w->reg[i].value); | |
7225342a | 679 | } |
b5321f30 | 680 | intel_ring_emit(ring, MI_NOOP); |
7225342a | 681 | |
b5321f30 | 682 | intel_ring_advance(ring); |
7225342a | 683 | |
7c9cf4e3 | 684 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
685 | if (ret) |
686 | return ret; | |
888b5995 | 687 | |
7225342a | 688 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 689 | |
7225342a | 690 | return 0; |
86d7f238 AS |
691 | } |
692 | ||
8753181e | 693 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
694 | { |
695 | int ret; | |
696 | ||
e2be4faf | 697 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
698 | if (ret != 0) |
699 | return ret; | |
700 | ||
be01363f | 701 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 702 | if (ret) |
e26e1b97 | 703 | return ret; |
8f0e2b9d | 704 | |
e26e1b97 | 705 | return 0; |
8f0e2b9d DV |
706 | } |
707 | ||
7225342a | 708 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
709 | i915_reg_t addr, |
710 | const u32 mask, const u32 val) | |
7225342a MK |
711 | { |
712 | const u32 idx = dev_priv->workarounds.count; | |
713 | ||
714 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
715 | return -ENOSPC; | |
716 | ||
717 | dev_priv->workarounds.reg[idx].addr = addr; | |
718 | dev_priv->workarounds.reg[idx].value = val; | |
719 | dev_priv->workarounds.reg[idx].mask = mask; | |
720 | ||
721 | dev_priv->workarounds.count++; | |
722 | ||
723 | return 0; | |
86d7f238 AS |
724 | } |
725 | ||
ca5a0fbd | 726 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 727 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
728 | if (r) \ |
729 | return r; \ | |
ca5a0fbd | 730 | } while (0) |
7225342a MK |
731 | |
732 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 733 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
734 | |
735 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 736 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 737 | |
98533251 | 738 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 739 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 740 | |
cf4b0de6 DL |
741 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
742 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 743 | |
cf4b0de6 | 744 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 745 | |
0bc40be8 TU |
746 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
747 | i915_reg_t reg) | |
33136b06 | 748 | { |
c033666a | 749 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 750 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 751 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
752 | |
753 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
754 | return -EINVAL; | |
755 | ||
0bc40be8 | 756 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 757 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 758 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
759 | |
760 | return 0; | |
761 | } | |
762 | ||
0bc40be8 | 763 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 764 | { |
c033666a | 765 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
766 | |
767 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 768 | |
717d84d6 AS |
769 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
770 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
771 | ||
d0581194 AS |
772 | /* WaDisablePartialInstShootdown:bdw,chv */ |
773 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
774 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
775 | ||
a340af58 AS |
776 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
777 | * workaround for for a possible hang in the unlikely event a TLB | |
778 | * invalidation occurs during a PSD flush. | |
779 | */ | |
780 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 781 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 782 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 783 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
784 | HDC_FORCE_NON_COHERENT); |
785 | ||
6def8fdd AS |
786 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
787 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
788 | * polygons in the same 8x4 pixel/sample area to be processed without | |
789 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
790 | * buffer." | |
791 | * | |
792 | * This optimization is off by default for BDW and CHV; turn it on. | |
793 | */ | |
794 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
795 | ||
48404636 AS |
796 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
797 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
798 | ||
7eebcde6 AS |
799 | /* |
800 | * BSpec recommends 8x4 when MSAA is used, | |
801 | * however in practice 16x4 seems fastest. | |
802 | * | |
803 | * Note that PS/WM thread counts depend on the WIZ hashing | |
804 | * disable bit, which we don't touch here, but it's good | |
805 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
806 | */ | |
807 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
808 | GEN6_WIZ_HASHING_MASK, | |
809 | GEN6_WIZ_HASHING_16x4); | |
810 | ||
e9a64ada AS |
811 | return 0; |
812 | } | |
813 | ||
0bc40be8 | 814 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 815 | { |
c033666a | 816 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 817 | int ret; |
86d7f238 | 818 | |
0bc40be8 | 819 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
820 | if (ret) |
821 | return ret; | |
822 | ||
101b376d | 823 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 824 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 825 | |
101b376d | 826 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
827 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
828 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 829 | |
7225342a MK |
830 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
831 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 832 | |
7225342a | 833 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
834 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
835 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 836 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 837 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 838 | |
86d7f238 AS |
839 | return 0; |
840 | } | |
841 | ||
0bc40be8 | 842 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 843 | { |
c033666a | 844 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 845 | int ret; |
00e1e623 | 846 | |
0bc40be8 | 847 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
848 | if (ret) |
849 | return ret; | |
850 | ||
00e1e623 | 851 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 852 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 853 | |
d60de81d KG |
854 | /* Improve HiZ throughput on CHV. */ |
855 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
856 | ||
7225342a MK |
857 | return 0; |
858 | } | |
859 | ||
0bc40be8 | 860 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 861 | { |
c033666a | 862 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 863 | int ret; |
ab0dfafe | 864 | |
a8ab5ed5 TG |
865 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
866 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
867 | ||
e5f81d65 | 868 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
869 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
870 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
871 | ||
e5f81d65 | 872 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
873 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
874 | ECOCHK_DIS_TLB); | |
875 | ||
e5f81d65 MK |
876 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
877 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 878 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 879 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
880 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
881 | ||
e5f81d65 | 882 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
883 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
884 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
885 | ||
e87a005d | 886 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
887 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
888 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
889 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
890 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 891 | |
e87a005d | 892 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
893 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
894 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
895 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
896 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
897 | /* |
898 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
899 | * but we do that in per ctx batchbuffer as there is an issue | |
900 | * with this register not getting restored on ctx restore | |
901 | */ | |
183c6dac DL |
902 | } |
903 | ||
e5f81d65 MK |
904 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
905 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
906 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
907 | GEN9_ENABLE_YV12_BUGFIX | | |
908 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 909 | |
e5f81d65 MK |
910 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
911 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
912 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
913 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 914 | |
e5f81d65 | 915 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
916 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
917 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
918 | ||
5a2ae95e | 919 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
920 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
921 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
922 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
923 | PIXEL_MASK_CAMMING_DISABLE); | |
924 | ||
5b0e3659 MK |
925 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
926 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
927 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
928 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 929 | |
bbaefe72 MK |
930 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
931 | * both tied to WaForceContextSaveRestoreNonCoherent | |
932 | * in some hsds for skl. We keep the tie for all gen9. The | |
933 | * documentation is a bit hazy and so we want to get common behaviour, | |
934 | * even though there is no clear evidence we would need both on kbl/bxt. | |
935 | * This area has been source of system hangs so we play it safe | |
936 | * and mimic the skl regardless of what bspec says. | |
937 | * | |
938 | * Use Force Non-Coherent whenever executing a 3D context. This | |
939 | * is a workaround for a possible hang in the unlikely event | |
940 | * a TLB invalidation occurs during a PSD flush. | |
941 | */ | |
942 | ||
943 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
944 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
945 | HDC_FORCE_NON_COHERENT); | |
946 | ||
947 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
948 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
949 | BDW_DISABLE_HDC_INVALIDATION); | |
950 | ||
e5f81d65 MK |
951 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
952 | if (IS_SKYLAKE(dev_priv) || | |
953 | IS_KABYLAKE(dev_priv) || | |
954 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
955 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
956 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 957 | |
e5f81d65 | 958 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
959 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
960 | ||
e5f81d65 | 961 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
962 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
963 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
964 | ||
6bb62855 | 965 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
966 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
967 | if (ret) | |
968 | return ret; | |
969 | ||
e5f81d65 | 970 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 971 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
972 | if (ret) |
973 | return ret; | |
974 | ||
e5f81d65 | 975 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 976 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
977 | if (ret) |
978 | return ret; | |
979 | ||
3b106531 HN |
980 | return 0; |
981 | } | |
982 | ||
0bc40be8 | 983 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 984 | { |
c033666a | 985 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
986 | u8 vals[3] = { 0, 0, 0 }; |
987 | unsigned int i; | |
988 | ||
989 | for (i = 0; i < 3; i++) { | |
990 | u8 ss; | |
991 | ||
992 | /* | |
993 | * Only consider slices where one, and only one, subslice has 7 | |
994 | * EUs | |
995 | */ | |
a4d8a0fe | 996 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
997 | continue; |
998 | ||
999 | /* | |
1000 | * subslice_7eu[i] != 0 (because of the check above) and | |
1001 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1002 | * | |
1003 | * -> 0 <= ss <= 3; | |
1004 | */ | |
1005 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1006 | vals[i] = 3 - ss; | |
1007 | } | |
1008 | ||
1009 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1010 | return 0; | |
1011 | ||
1012 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1013 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1014 | GEN9_IZ_HASHING_MASK(2) | | |
1015 | GEN9_IZ_HASHING_MASK(1) | | |
1016 | GEN9_IZ_HASHING_MASK(0), | |
1017 | GEN9_IZ_HASHING(2, vals[2]) | | |
1018 | GEN9_IZ_HASHING(1, vals[1]) | | |
1019 | GEN9_IZ_HASHING(0, vals[0])); | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
0bc40be8 | 1024 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1025 | { |
c033666a | 1026 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1027 | int ret; |
d0bbbc4f | 1028 | |
0bc40be8 | 1029 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1030 | if (ret) |
1031 | return ret; | |
8d205494 | 1032 | |
a78536e7 AS |
1033 | /* |
1034 | * Actual WA is to disable percontext preemption granularity control | |
1035 | * until D0 which is the default case so this is equivalent to | |
1036 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1037 | */ | |
c033666a | 1038 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
1039 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1040 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1041 | } | |
1042 | ||
71dce58c | 1043 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1044 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1045 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1046 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1047 | } | |
1048 | ||
1049 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1050 | * involving this register should also be added to WA batch as required. | |
1051 | */ | |
c033666a | 1052 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1053 | /* WaDisableLSQCROPERFforOCL:skl */ |
1054 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1055 | GEN8_LQSC_RO_PERF_DIS); | |
1056 | ||
1057 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1058 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1059 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1060 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1061 | } | |
1062 | ||
d0bbbc4f | 1063 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1064 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1065 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1066 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1067 | ||
e87a005d | 1068 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1069 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1070 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1071 | HDC_FENCE_DEST_SLM_DISABLE | | |
1072 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1073 | ||
9bd9dfb4 | 1074 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1075 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1076 | WA_SET_BIT_MASKED( |
1077 | GEN7_HALF_SLICE_CHICKEN1, | |
1078 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1079 | |
eee8efb0 MK |
1080 | /* WaDisableGafsUnitClkGating:skl */ |
1081 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1082 | ||
4ba9c1f7 MK |
1083 | /* WaInPlaceDecompressionHang:skl */ |
1084 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
1085 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1086 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1087 | ||
6107497e | 1088 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1089 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1090 | if (ret) |
1091 | return ret; | |
1092 | ||
0bc40be8 | 1093 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1094 | } |
1095 | ||
0bc40be8 | 1096 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1097 | { |
c033666a | 1098 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1099 | int ret; |
dfb601e6 | 1100 | |
0bc40be8 | 1101 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1102 | if (ret) |
1103 | return ret; | |
cae0437f | 1104 | |
9c4cbf82 MK |
1105 | /* WaStoreMultiplePTEenable:bxt */ |
1106 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1107 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1108 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1109 | ||
1110 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1111 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1112 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1113 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1114 | } | |
1115 | ||
dfb601e6 NH |
1116 | /* WaDisableThreadStallDopClockGating:bxt */ |
1117 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1118 | STALL_DOP_GATING_DISABLE); | |
1119 | ||
780f0aeb | 1120 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1121 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1122 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1123 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1124 | } | |
1125 | ||
983b4b9d | 1126 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1127 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1128 | WA_SET_BIT_MASKED( |
1129 | GEN7_HALF_SLICE_CHICKEN1, | |
1130 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1131 | } | |
1132 | ||
2c8580e4 AS |
1133 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1134 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1135 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1136 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1137 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1138 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1139 | if (ret) |
1140 | return ret; | |
a786d53a | 1141 | |
0bc40be8 | 1142 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1143 | if (ret) |
1144 | return ret; | |
2c8580e4 AS |
1145 | } |
1146 | ||
050fc465 | 1147 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1148 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1149 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1150 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1151 | |
575e3ccb MA |
1152 | /* WaToEnableHwFixForPushConstHWBug:bxt */ |
1153 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1154 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1155 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1156 | ||
4ba9c1f7 MK |
1157 | /* WaInPlaceDecompressionHang:bxt */ |
1158 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1159 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1160 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1161 | ||
cae0437f NH |
1162 | return 0; |
1163 | } | |
1164 | ||
e5f81d65 MK |
1165 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1166 | { | |
e587f6cb | 1167 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1168 | int ret; |
1169 | ||
1170 | ret = gen9_init_workarounds(engine); | |
1171 | if (ret) | |
1172 | return ret; | |
1173 | ||
e587f6cb MK |
1174 | /* WaEnableGapsTsvCreditFix:kbl */ |
1175 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1176 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1177 | ||
c0b730d5 MK |
1178 | /* WaDisableDynamicCreditSharing:kbl */ |
1179 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1180 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1181 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1182 | ||
8401d42f MK |
1183 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1184 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1185 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1186 | HDC_FENCE_DEST_SLM_DISABLE); | |
1187 | ||
fe905819 MK |
1188 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1189 | * involving this register should also be added to WA batch as required. | |
1190 | */ | |
1191 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1192 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1193 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1194 | GEN8_LQSC_RO_PERF_DIS); | |
1195 | ||
575e3ccb MA |
1196 | /* WaToEnableHwFixForPushConstHWBug:kbl */ |
1197 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1198 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1199 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1200 | ||
4de5d7cc MK |
1201 | /* WaDisableGafsUnitClkGating:kbl */ |
1202 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1203 | ||
954337aa MK |
1204 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1205 | WA_SET_BIT_MASKED( | |
1206 | GEN7_HALF_SLICE_CHICKEN1, | |
1207 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1208 | ||
4ba9c1f7 MK |
1209 | /* WaInPlaceDecompressionHang:kbl */ |
1210 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1211 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1212 | ||
fe905819 MK |
1213 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1214 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1215 | if (ret) | |
1216 | return ret; | |
1217 | ||
e5f81d65 MK |
1218 | return 0; |
1219 | } | |
1220 | ||
0bc40be8 | 1221 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1222 | { |
c033666a | 1223 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1224 | |
0bc40be8 | 1225 | WARN_ON(engine->id != RCS); |
7225342a MK |
1226 | |
1227 | dev_priv->workarounds.count = 0; | |
33136b06 | 1228 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1229 | |
c033666a | 1230 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1231 | return bdw_init_workarounds(engine); |
7225342a | 1232 | |
c033666a | 1233 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1234 | return chv_init_workarounds(engine); |
00e1e623 | 1235 | |
c033666a | 1236 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1237 | return skl_init_workarounds(engine); |
cae0437f | 1238 | |
c033666a | 1239 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1240 | return bxt_init_workarounds(engine); |
3b106531 | 1241 | |
e5f81d65 MK |
1242 | if (IS_KABYLAKE(dev_priv)) |
1243 | return kbl_init_workarounds(engine); | |
1244 | ||
00e1e623 VS |
1245 | return 0; |
1246 | } | |
1247 | ||
0bc40be8 | 1248 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1249 | { |
c033666a | 1250 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1251 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1252 | if (ret) |
1253 | return ret; | |
a69ffdbf | 1254 | |
61a563a2 | 1255 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1256 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1257 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1258 | |
1259 | /* We need to disable the AsyncFlip performance optimisations in order | |
1260 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1261 | * programmed to '1' on all products. | |
8693a824 | 1262 | * |
2441f877 | 1263 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1264 | */ |
ac657f64 | 1265 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1266 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1267 | ||
f05bb0c7 | 1268 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1269 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1270 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1271 | I915_WRITE(GFX_MODE, |
aa83e30d | 1272 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1273 | |
01fa0302 | 1274 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1275 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1276 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1277 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1278 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1279 | |
c033666a | 1280 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1281 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1282 | * "If this bit is set, STCunit will have LRA as replacement | |
1283 | * policy. [...] This bit must be reset. LRA replacement | |
1284 | * policy is not supported." | |
1285 | */ | |
1286 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1287 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1288 | } |
1289 | ||
ac657f64 | 1290 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1291 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1292 | |
035ea405 VS |
1293 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1294 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1295 | |
0bc40be8 | 1296 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1297 | } |
1298 | ||
0bc40be8 | 1299 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1300 | { |
c033666a | 1301 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a BW |
1302 | |
1303 | if (dev_priv->semaphore_obj) { | |
1304 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
f8c417cd | 1305 | i915_gem_object_put(dev_priv->semaphore_obj); |
3e78998a BW |
1306 | dev_priv->semaphore_obj = NULL; |
1307 | } | |
b45305fc | 1308 | |
0bc40be8 | 1309 | intel_fini_pipe_control(engine); |
c6df541c CW |
1310 | } |
1311 | ||
ad7bdb2b | 1312 | static int gen8_rcs_signal(struct drm_i915_gem_request *req) |
3e78998a | 1313 | { |
ad7bdb2b CW |
1314 | struct intel_ring *ring = req->ring; |
1315 | struct drm_i915_private *dev_priv = req->i915; | |
3e78998a | 1316 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1317 | enum intel_engine_id id; |
1318 | int ret, num_rings; | |
3e78998a | 1319 | |
c1bb1145 | 1320 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1321 | ret = intel_ring_begin(req, (num_rings-1) * 8); |
3e78998a BW |
1322 | if (ret) |
1323 | return ret; | |
1324 | ||
c3232b18 | 1325 | for_each_engine_id(waiter, dev_priv, id) { |
ad7bdb2b | 1326 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1327 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1328 | continue; | |
1329 | ||
ad7bdb2b CW |
1330 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1331 | intel_ring_emit(ring, | |
b5321f30 CW |
1332 | PIPE_CONTROL_GLOBAL_GTT_IVB | |
1333 | PIPE_CONTROL_QW_WRITE | | |
1334 | PIPE_CONTROL_CS_STALL); | |
ad7bdb2b CW |
1335 | intel_ring_emit(ring, lower_32_bits(gtt_offset)); |
1336 | intel_ring_emit(ring, upper_32_bits(gtt_offset)); | |
1337 | intel_ring_emit(ring, req->fence.seqno); | |
1338 | intel_ring_emit(ring, 0); | |
1339 | intel_ring_emit(ring, | |
b5321f30 CW |
1340 | MI_SEMAPHORE_SIGNAL | |
1341 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
ad7bdb2b | 1342 | intel_ring_emit(ring, 0); |
3e78998a | 1343 | } |
ad7bdb2b | 1344 | intel_ring_advance(ring); |
3e78998a BW |
1345 | |
1346 | return 0; | |
1347 | } | |
1348 | ||
ad7bdb2b | 1349 | static int gen8_xcs_signal(struct drm_i915_gem_request *req) |
3e78998a | 1350 | { |
ad7bdb2b CW |
1351 | struct intel_ring *ring = req->ring; |
1352 | struct drm_i915_private *dev_priv = req->i915; | |
3e78998a | 1353 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1354 | enum intel_engine_id id; |
1355 | int ret, num_rings; | |
3e78998a | 1356 | |
c1bb1145 | 1357 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1358 | ret = intel_ring_begin(req, (num_rings-1) * 6); |
3e78998a BW |
1359 | if (ret) |
1360 | return ret; | |
1361 | ||
c3232b18 | 1362 | for_each_engine_id(waiter, dev_priv, id) { |
ad7bdb2b | 1363 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1364 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1365 | continue; | |
1366 | ||
ad7bdb2b | 1367 | intel_ring_emit(ring, |
b5321f30 | 1368 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
ad7bdb2b | 1369 | intel_ring_emit(ring, |
b5321f30 CW |
1370 | lower_32_bits(gtt_offset) | |
1371 | MI_FLUSH_DW_USE_GTT); | |
ad7bdb2b CW |
1372 | intel_ring_emit(ring, upper_32_bits(gtt_offset)); |
1373 | intel_ring_emit(ring, req->fence.seqno); | |
1374 | intel_ring_emit(ring, | |
b5321f30 CW |
1375 | MI_SEMAPHORE_SIGNAL | |
1376 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
ad7bdb2b | 1377 | intel_ring_emit(ring, 0); |
3e78998a | 1378 | } |
ad7bdb2b | 1379 | intel_ring_advance(ring); |
3e78998a BW |
1380 | |
1381 | return 0; | |
1382 | } | |
1383 | ||
ad7bdb2b | 1384 | static int gen6_signal(struct drm_i915_gem_request *req) |
1ec14ad3 | 1385 | { |
ad7bdb2b CW |
1386 | struct intel_ring *ring = req->ring; |
1387 | struct drm_i915_private *dev_priv = req->i915; | |
a4872ba6 | 1388 | struct intel_engine_cs *useless; |
c3232b18 DG |
1389 | enum intel_engine_id id; |
1390 | int ret, num_rings; | |
78325f2d | 1391 | |
c1bb1145 | 1392 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1393 | ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2)); |
024a43e1 BW |
1394 | if (ret) |
1395 | return ret; | |
024a43e1 | 1396 | |
c3232b18 | 1397 | for_each_engine_id(useless, dev_priv, id) { |
ad7bdb2b | 1398 | i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; |
f0f59a00 VS |
1399 | |
1400 | if (i915_mmio_reg_valid(mbox_reg)) { | |
ad7bdb2b CW |
1401 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
1402 | intel_ring_emit_reg(ring, mbox_reg); | |
1403 | intel_ring_emit(ring, req->fence.seqno); | |
78325f2d BW |
1404 | } |
1405 | } | |
024a43e1 | 1406 | |
a1444b79 BW |
1407 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1408 | if (num_rings % 2 == 0) | |
ad7bdb2b CW |
1409 | intel_ring_emit(ring, MI_NOOP); |
1410 | intel_ring_advance(ring); | |
a1444b79 | 1411 | |
024a43e1 | 1412 | return 0; |
1ec14ad3 CW |
1413 | } |
1414 | ||
b0411e7d CW |
1415 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
1416 | { | |
1417 | struct drm_i915_private *dev_priv = request->i915; | |
1418 | ||
1419 | I915_WRITE_TAIL(request->engine, | |
1420 | intel_ring_offset(request->ring, request->tail)); | |
1421 | } | |
1422 | ||
1423 | static int i9xx_emit_request(struct drm_i915_gem_request *req) | |
1ec14ad3 | 1424 | { |
7e37f889 | 1425 | struct intel_ring *ring = req->ring; |
024a43e1 | 1426 | int ret; |
52ed2325 | 1427 | |
9242f974 | 1428 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1429 | if (ret) |
1430 | return ret; | |
1431 | ||
b5321f30 CW |
1432 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1433 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1434 | intel_ring_emit(ring, req->fence.seqno); | |
1435 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
c5efa1ad CW |
1436 | intel_ring_advance(ring); |
1437 | ||
1438 | req->tail = ring->tail; | |
1ec14ad3 | 1439 | |
1ec14ad3 CW |
1440 | return 0; |
1441 | } | |
1442 | ||
b0411e7d | 1443 | /** |
618e4ca7 | 1444 | * gen6_sema_emit_request - Update the semaphore mailbox registers |
b0411e7d CW |
1445 | * |
1446 | * @request - request to write to the ring | |
1447 | * | |
1448 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1449 | * This acts like a signal in the canonical semaphore. | |
1450 | */ | |
618e4ca7 | 1451 | static int gen6_sema_emit_request(struct drm_i915_gem_request *req) |
b0411e7d | 1452 | { |
618e4ca7 | 1453 | int ret; |
b0411e7d | 1454 | |
618e4ca7 CW |
1455 | ret = req->engine->semaphore.signal(req); |
1456 | if (ret) | |
1457 | return ret; | |
b0411e7d CW |
1458 | |
1459 | return i9xx_emit_request(req); | |
1460 | } | |
1461 | ||
ddd66c51 | 1462 | static int gen8_render_emit_request(struct drm_i915_gem_request *req) |
a58c01aa CW |
1463 | { |
1464 | struct intel_engine_cs *engine = req->engine; | |
7e37f889 | 1465 | struct intel_ring *ring = req->ring; |
a58c01aa CW |
1466 | int ret; |
1467 | ||
9242f974 CW |
1468 | if (engine->semaphore.signal) { |
1469 | ret = engine->semaphore.signal(req); | |
1470 | if (ret) | |
1471 | return ret; | |
1472 | } | |
1473 | ||
1474 | ret = intel_ring_begin(req, 8); | |
a58c01aa CW |
1475 | if (ret) |
1476 | return ret; | |
1477 | ||
b5321f30 CW |
1478 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1479 | intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1480 | PIPE_CONTROL_CS_STALL | | |
1481 | PIPE_CONTROL_QW_WRITE)); | |
1482 | intel_ring_emit(ring, intel_hws_seqno_address(engine)); | |
1483 | intel_ring_emit(ring, 0); | |
1484 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); | |
a58c01aa | 1485 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1486 | intel_ring_emit(ring, 0); |
1487 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1488 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1489 | intel_ring_advance(ring); |
c5efa1ad CW |
1490 | |
1491 | req->tail = ring->tail; | |
a58c01aa CW |
1492 | |
1493 | return 0; | |
1494 | } | |
1495 | ||
c8c99b0f BW |
1496 | /** |
1497 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1498 | * | |
1499 | * @waiter - ring that is waiting | |
1500 | * @signaller - ring which has, or will signal | |
1501 | * @seqno - seqno which the waiter will block on | |
1502 | */ | |
5ee426ca BW |
1503 | |
1504 | static int | |
ad7bdb2b CW |
1505 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
1506 | struct drm_i915_gem_request *signal) | |
5ee426ca | 1507 | { |
ad7bdb2b CW |
1508 | struct intel_ring *ring = req->ring; |
1509 | struct drm_i915_private *dev_priv = req->i915; | |
1510 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 1511 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1512 | int ret; |
1513 | ||
ad7bdb2b | 1514 | ret = intel_ring_begin(req, 4); |
5ee426ca BW |
1515 | if (ret) |
1516 | return ret; | |
1517 | ||
ad7bdb2b CW |
1518 | intel_ring_emit(ring, |
1519 | MI_SEMAPHORE_WAIT | | |
1520 | MI_SEMAPHORE_GLOBAL_GTT | | |
1521 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1522 | intel_ring_emit(ring, signal->fence.seqno); | |
1523 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1524 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1525 | intel_ring_advance(ring); | |
6ef48d7f CW |
1526 | |
1527 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1528 | * pagetables and we must reload them before executing the batch. | |
1529 | * We do this on the i915_switch_context() following the wait and | |
1530 | * before the dispatch. | |
1531 | */ | |
ad7bdb2b CW |
1532 | ppgtt = req->ctx->ppgtt; |
1533 | if (ppgtt && req->engine->id != RCS) | |
1534 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
1535 | return 0; |
1536 | } | |
1537 | ||
c8c99b0f | 1538 | static int |
ad7bdb2b CW |
1539 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
1540 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 1541 | { |
ad7bdb2b | 1542 | struct intel_ring *ring = req->ring; |
c8c99b0f BW |
1543 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1544 | MI_SEMAPHORE_COMPARE | | |
1545 | MI_SEMAPHORE_REGISTER; | |
ad7bdb2b | 1546 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id]; |
ebc348b2 | 1547 | int ret; |
1ec14ad3 | 1548 | |
ebc348b2 | 1549 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1550 | |
ad7bdb2b | 1551 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1552 | if (ret) |
1553 | return ret; | |
1554 | ||
ad7bdb2b | 1555 | intel_ring_emit(ring, dw1 | wait_mbox); |
ddf07be7 CW |
1556 | /* Throughout all of the GEM code, seqno passed implies our current |
1557 | * seqno is >= the last seqno executed. However for hardware the | |
1558 | * comparison is strictly greater than. | |
1559 | */ | |
ad7bdb2b CW |
1560 | intel_ring_emit(ring, signal->fence.seqno - 1); |
1561 | intel_ring_emit(ring, 0); | |
1562 | intel_ring_emit(ring, MI_NOOP); | |
1563 | intel_ring_advance(ring); | |
1ec14ad3 CW |
1564 | |
1565 | return 0; | |
1566 | } | |
1567 | ||
f8973c21 | 1568 | static void |
38a0f2db | 1569 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 1570 | { |
f8973c21 CW |
1571 | /* MI_STORE are internally buffered by the GPU and not flushed |
1572 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1573 | * MI commands. | |
c6df541c | 1574 | * |
f8973c21 CW |
1575 | * "Only the submission of the store operation is guaranteed. |
1576 | * The write result will be complete (coherent) some time later | |
1577 | * (this is practically a finite period but there is no guaranteed | |
1578 | * latency)." | |
1579 | * | |
1580 | * Empirically, we observe that we need a delay of at least 75us to | |
1581 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1582 | */ |
f8973c21 | 1583 | usleep_range(125, 250); |
c6df541c CW |
1584 | } |
1585 | ||
c04e0f3b CW |
1586 | static void |
1587 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1588 | { |
c033666a | 1589 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1590 | |
4cd53c0c DV |
1591 | /* Workaround to force correct ordering between irq and seqno writes on |
1592 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1593 | * ACTHD) before reading the status page. |
1594 | * | |
1595 | * Note that this effectively stalls the read by the time it takes to | |
1596 | * do a memory transaction, which more or less ensures that the write | |
1597 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1598 | * Alternatively we could delay the interrupt from the CS ring to give | |
1599 | * the write time to land, but that would incur a delay after every | |
1600 | * batch i.e. much more frequent than a delay when waiting for the | |
1601 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1602 | * |
1603 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1604 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1605 | */ |
bcbdb6d0 | 1606 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1607 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1608 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1609 | } |
1610 | ||
31bb59cc CW |
1611 | static void |
1612 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1613 | { |
31bb59cc | 1614 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1615 | } |
1616 | ||
1617 | static void | |
31bb59cc | 1618 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1619 | { |
31bb59cc | 1620 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1621 | } |
1622 | ||
31bb59cc CW |
1623 | static void |
1624 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1625 | { |
c033666a | 1626 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1627 | |
31bb59cc CW |
1628 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1629 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1630 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1631 | } |
1632 | ||
8187a2b7 | 1633 | static void |
31bb59cc | 1634 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1635 | { |
c033666a | 1636 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1637 | |
31bb59cc CW |
1638 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1639 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1640 | } |
1641 | ||
31bb59cc CW |
1642 | static void |
1643 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1644 | { |
c033666a | 1645 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1646 | |
31bb59cc CW |
1647 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1648 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1649 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1650 | } |
1651 | ||
1652 | static void | |
31bb59cc | 1653 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1654 | { |
c033666a | 1655 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1656 | |
31bb59cc CW |
1657 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1658 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1659 | } |
1660 | ||
b72f3acb | 1661 | static int |
7c9cf4e3 | 1662 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1663 | { |
7e37f889 | 1664 | struct intel_ring *ring = req->ring; |
b72f3acb CW |
1665 | int ret; |
1666 | ||
5fb9de1a | 1667 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1668 | if (ret) |
1669 | return ret; | |
1670 | ||
b5321f30 CW |
1671 | intel_ring_emit(ring, MI_FLUSH); |
1672 | intel_ring_emit(ring, MI_NOOP); | |
1673 | intel_ring_advance(ring); | |
b72f3acb | 1674 | return 0; |
d1b851fc ZN |
1675 | } |
1676 | ||
31bb59cc CW |
1677 | static void |
1678 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1679 | { |
c033666a | 1680 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1681 | |
61ff75ac CW |
1682 | I915_WRITE_IMR(engine, |
1683 | ~(engine->irq_enable_mask | | |
1684 | engine->irq_keep_mask)); | |
31bb59cc | 1685 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1686 | } |
1687 | ||
1688 | static void | |
31bb59cc | 1689 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1690 | { |
c033666a | 1691 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1692 | |
61ff75ac | 1693 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1694 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1695 | } |
1696 | ||
31bb59cc CW |
1697 | static void |
1698 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1699 | { |
c033666a | 1700 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1701 | |
31bb59cc CW |
1702 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1703 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1704 | } |
1705 | ||
1706 | static void | |
31bb59cc | 1707 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1708 | { |
c033666a | 1709 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1710 | |
31bb59cc CW |
1711 | I915_WRITE_IMR(engine, ~0); |
1712 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1713 | } |
1714 | ||
31bb59cc CW |
1715 | static void |
1716 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1717 | { |
c033666a | 1718 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1719 | |
61ff75ac CW |
1720 | I915_WRITE_IMR(engine, |
1721 | ~(engine->irq_enable_mask | | |
1722 | engine->irq_keep_mask)); | |
31bb59cc | 1723 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1724 | } |
1725 | ||
1726 | static void | |
31bb59cc | 1727 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1728 | { |
c033666a | 1729 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1730 | |
61ff75ac | 1731 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1732 | } |
1733 | ||
d1b851fc | 1734 | static int |
803688ba CW |
1735 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1736 | u64 offset, u32 length, | |
1737 | unsigned int dispatch_flags) | |
d1b851fc | 1738 | { |
7e37f889 | 1739 | struct intel_ring *ring = req->ring; |
e1f99ce6 | 1740 | int ret; |
78501eac | 1741 | |
5fb9de1a | 1742 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1743 | if (ret) |
1744 | return ret; | |
1745 | ||
b5321f30 | 1746 | intel_ring_emit(ring, |
65f56876 CW |
1747 | MI_BATCH_BUFFER_START | |
1748 | MI_BATCH_GTT | | |
8e004efc JH |
1749 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1750 | 0 : MI_BATCH_NON_SECURE_I965)); | |
b5321f30 CW |
1751 | intel_ring_emit(ring, offset); |
1752 | intel_ring_advance(ring); | |
78501eac | 1753 | |
d1b851fc ZN |
1754 | return 0; |
1755 | } | |
1756 | ||
b45305fc DV |
1757 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1758 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1759 | #define I830_TLB_ENTRIES (2) |
1760 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1761 | static int |
803688ba CW |
1762 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1763 | u64 offset, u32 len, | |
1764 | unsigned int dispatch_flags) | |
62fdfeaf | 1765 | { |
7e37f889 | 1766 | struct intel_ring *ring = req->ring; |
b5321f30 | 1767 | u32 cs_offset = req->engine->scratch.gtt_offset; |
c4e7a414 | 1768 | int ret; |
62fdfeaf | 1769 | |
5fb9de1a | 1770 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1771 | if (ret) |
1772 | return ret; | |
62fdfeaf | 1773 | |
c4d69da1 | 1774 | /* Evict the invalid PTE TLBs */ |
b5321f30 CW |
1775 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1776 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1777 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1778 | intel_ring_emit(ring, cs_offset); | |
1779 | intel_ring_emit(ring, 0xdeadbeef); | |
1780 | intel_ring_emit(ring, MI_NOOP); | |
1781 | intel_ring_advance(ring); | |
b45305fc | 1782 | |
8e004efc | 1783 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1784 | if (len > I830_BATCH_LIMIT) |
1785 | return -ENOSPC; | |
1786 | ||
5fb9de1a | 1787 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1788 | if (ret) |
1789 | return ret; | |
c4d69da1 CW |
1790 | |
1791 | /* Blit the batch (which has now all relocs applied) to the | |
1792 | * stable batch scratch bo area (so that the CS never | |
1793 | * stumbles over its tlb invalidation bug) ... | |
1794 | */ | |
b5321f30 CW |
1795 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1796 | intel_ring_emit(ring, | |
e2f80391 | 1797 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
b5321f30 CW |
1798 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
1799 | intel_ring_emit(ring, cs_offset); | |
1800 | intel_ring_emit(ring, 4096); | |
1801 | intel_ring_emit(ring, offset); | |
e2f80391 | 1802 | |
b5321f30 CW |
1803 | intel_ring_emit(ring, MI_FLUSH); |
1804 | intel_ring_emit(ring, MI_NOOP); | |
1805 | intel_ring_advance(ring); | |
b45305fc DV |
1806 | |
1807 | /* ... and execute it. */ | |
c4d69da1 | 1808 | offset = cs_offset; |
b45305fc | 1809 | } |
e1f99ce6 | 1810 | |
9d611c03 | 1811 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1812 | if (ret) |
1813 | return ret; | |
1814 | ||
b5321f30 CW |
1815 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1816 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1817 | 0 : MI_BATCH_NON_SECURE)); | |
1818 | intel_ring_advance(ring); | |
c4d69da1 | 1819 | |
fb3256da DV |
1820 | return 0; |
1821 | } | |
1822 | ||
1823 | static int | |
803688ba CW |
1824 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1825 | u64 offset, u32 len, | |
1826 | unsigned int dispatch_flags) | |
fb3256da | 1827 | { |
7e37f889 | 1828 | struct intel_ring *ring = req->ring; |
fb3256da DV |
1829 | int ret; |
1830 | ||
5fb9de1a | 1831 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1832 | if (ret) |
1833 | return ret; | |
1834 | ||
b5321f30 CW |
1835 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1836 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1837 | 0 : MI_BATCH_NON_SECURE)); | |
1838 | intel_ring_advance(ring); | |
62fdfeaf | 1839 | |
62fdfeaf EA |
1840 | return 0; |
1841 | } | |
1842 | ||
0bc40be8 | 1843 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1844 | { |
c033666a | 1845 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1846 | |
1847 | if (!dev_priv->status_page_dmah) | |
1848 | return; | |
1849 | ||
91c8a326 | 1850 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1851 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1852 | } |
1853 | ||
0bc40be8 | 1854 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1855 | { |
05394f39 | 1856 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1857 | |
0bc40be8 | 1858 | obj = engine->status_page.obj; |
8187a2b7 | 1859 | if (obj == NULL) |
62fdfeaf | 1860 | return; |
62fdfeaf | 1861 | |
9da3da66 | 1862 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1863 | i915_gem_object_ggtt_unpin(obj); |
f8c417cd | 1864 | i915_gem_object_put(obj); |
0bc40be8 | 1865 | engine->status_page.obj = NULL; |
62fdfeaf EA |
1866 | } |
1867 | ||
0bc40be8 | 1868 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1869 | { |
0bc40be8 | 1870 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 1871 | |
7d3fdfff | 1872 | if (obj == NULL) { |
1f767e02 | 1873 | unsigned flags; |
e3efda49 | 1874 | int ret; |
e4ffd173 | 1875 | |
91c8a326 | 1876 | obj = i915_gem_object_create(&engine->i915->drm, 4096); |
fe3db79b | 1877 | if (IS_ERR(obj)) { |
e3efda49 | 1878 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 1879 | return PTR_ERR(obj); |
e3efda49 | 1880 | } |
62fdfeaf | 1881 | |
e3efda49 CW |
1882 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1883 | if (ret) | |
1884 | goto err_unref; | |
1885 | ||
1f767e02 | 1886 | flags = 0; |
c033666a | 1887 | if (!HAS_LLC(engine->i915)) |
1f767e02 CW |
1888 | /* On g33, we cannot place HWS above 256MiB, so |
1889 | * restrict its pinning to the low mappable arena. | |
1890 | * Though this restriction is not documented for | |
1891 | * gen4, gen5, or byt, they also behave similarly | |
1892 | * and hang if the HWS is placed at the top of the | |
1893 | * GTT. To generalise, it appears that all !llc | |
1894 | * platforms have issues with us placing the HWS | |
1895 | * above the mappable region (even though we never | |
1896 | * actualy map it). | |
1897 | */ | |
1898 | flags |= PIN_MAPPABLE; | |
de895082 | 1899 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, flags); |
e3efda49 CW |
1900 | if (ret) { |
1901 | err_unref: | |
f8c417cd | 1902 | i915_gem_object_put(obj); |
e3efda49 CW |
1903 | return ret; |
1904 | } | |
1905 | ||
0bc40be8 | 1906 | engine->status_page.obj = obj; |
e3efda49 | 1907 | } |
62fdfeaf | 1908 | |
0bc40be8 TU |
1909 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
1910 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
1911 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1912 | |
8187a2b7 | 1913 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 1914 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
1915 | |
1916 | return 0; | |
62fdfeaf EA |
1917 | } |
1918 | ||
0bc40be8 | 1919 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1920 | { |
c033666a | 1921 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 CW |
1922 | |
1923 | if (!dev_priv->status_page_dmah) { | |
1924 | dev_priv->status_page_dmah = | |
91c8a326 | 1925 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
1926 | if (!dev_priv->status_page_dmah) |
1927 | return -ENOMEM; | |
1928 | } | |
1929 | ||
0bc40be8 TU |
1930 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1931 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1932 | |
1933 | return 0; | |
1934 | } | |
1935 | ||
aad29fbb | 1936 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1937 | { |
aad29fbb | 1938 | struct drm_i915_private *dev_priv = ring->engine->i915; |
32c04f16 | 1939 | struct drm_i915_gem_object *obj = ring->obj; |
a687a43a CW |
1940 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1941 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 1942 | void *addr; |
7ba717cf TD |
1943 | int ret; |
1944 | ||
def0c5f6 | 1945 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
de895082 | 1946 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, flags); |
def0c5f6 CW |
1947 | if (ret) |
1948 | return ret; | |
7ba717cf | 1949 | |
def0c5f6 | 1950 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
1951 | if (ret) |
1952 | goto err_unpin; | |
def0c5f6 | 1953 | |
8305216f DG |
1954 | addr = i915_gem_object_pin_map(obj); |
1955 | if (IS_ERR(addr)) { | |
1956 | ret = PTR_ERR(addr); | |
d2cad535 | 1957 | goto err_unpin; |
def0c5f6 CW |
1958 | } |
1959 | } else { | |
de895082 CW |
1960 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, |
1961 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
1962 | if (ret) |
1963 | return ret; | |
7ba717cf | 1964 | |
def0c5f6 | 1965 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
1966 | if (ret) |
1967 | goto err_unpin; | |
def0c5f6 | 1968 | |
ff3dc087 DCS |
1969 | /* Access through the GTT requires the device to be awake. */ |
1970 | assert_rpm_wakelock_held(dev_priv); | |
1971 | ||
406ea8d2 CW |
1972 | addr = (void __force *) |
1973 | i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); | |
3d77e9be CW |
1974 | if (IS_ERR(addr)) { |
1975 | ret = PTR_ERR(addr); | |
d2cad535 | 1976 | goto err_unpin; |
def0c5f6 | 1977 | } |
7ba717cf TD |
1978 | } |
1979 | ||
32c04f16 CW |
1980 | ring->vaddr = addr; |
1981 | ring->vma = i915_gem_obj_to_ggtt(obj); | |
7ba717cf | 1982 | return 0; |
d2cad535 CW |
1983 | |
1984 | err_unpin: | |
1985 | i915_gem_object_ggtt_unpin(obj); | |
1986 | return ret; | |
7ba717cf TD |
1987 | } |
1988 | ||
aad29fbb CW |
1989 | void intel_ring_unpin(struct intel_ring *ring) |
1990 | { | |
1991 | GEM_BUG_ON(!ring->vma); | |
1992 | GEM_BUG_ON(!ring->vaddr); | |
1993 | ||
1994 | if (HAS_LLC(ring->engine->i915) && !ring->obj->stolen) | |
1995 | i915_gem_object_unpin_map(ring->obj); | |
1996 | else | |
1997 | i915_vma_unpin_iomap(ring->vma); | |
1998 | ring->vaddr = NULL; | |
1999 | ||
2000 | i915_gem_object_ggtt_unpin(ring->obj); | |
2001 | ring->vma = NULL; | |
2002 | } | |
2003 | ||
32c04f16 | 2004 | static void intel_destroy_ringbuffer_obj(struct intel_ring *ring) |
7ba717cf | 2005 | { |
32c04f16 CW |
2006 | i915_gem_object_put(ring->obj); |
2007 | ring->obj = NULL; | |
2919d291 OM |
2008 | } |
2009 | ||
01101fa7 | 2010 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
32c04f16 | 2011 | struct intel_ring *ring) |
62fdfeaf | 2012 | { |
05394f39 | 2013 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2014 | |
ebc052e0 CW |
2015 | obj = NULL; |
2016 | if (!HAS_LLC(dev)) | |
32c04f16 | 2017 | obj = i915_gem_object_create_stolen(dev, ring->size); |
ebc052e0 | 2018 | if (obj == NULL) |
32c04f16 | 2019 | obj = i915_gem_object_create(dev, ring->size); |
fe3db79b CW |
2020 | if (IS_ERR(obj)) |
2021 | return PTR_ERR(obj); | |
8187a2b7 | 2022 | |
24f3a8cf AG |
2023 | /* mark ring buffers as read-only from GPU side by default */ |
2024 | obj->gt_ro = 1; | |
2025 | ||
32c04f16 | 2026 | ring->obj = obj; |
e3efda49 | 2027 | |
7ba717cf | 2028 | return 0; |
e3efda49 CW |
2029 | } |
2030 | ||
7e37f889 CW |
2031 | struct intel_ring * |
2032 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 2033 | { |
7e37f889 | 2034 | struct intel_ring *ring; |
01101fa7 CW |
2035 | int ret; |
2036 | ||
8f942018 CW |
2037 | GEM_BUG_ON(!is_power_of_2(size)); |
2038 | ||
01101fa7 | 2039 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
608c1a52 CW |
2040 | if (ring == NULL) { |
2041 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2042 | engine->name); | |
01101fa7 | 2043 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2044 | } |
01101fa7 | 2045 | |
4a570db5 | 2046 | ring->engine = engine; |
608c1a52 | 2047 | list_add(&ring->link, &engine->buffers); |
01101fa7 | 2048 | |
675d9ad7 CW |
2049 | INIT_LIST_HEAD(&ring->request_list); |
2050 | ||
01101fa7 CW |
2051 | ring->size = size; |
2052 | /* Workaround an erratum on the i830 which causes a hang if | |
2053 | * the TAIL pointer points to within the last 2 cachelines | |
2054 | * of the buffer. | |
2055 | */ | |
2056 | ring->effective_size = size; | |
c033666a | 2057 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
2058 | ring->effective_size -= 2 * CACHELINE_BYTES; |
2059 | ||
2060 | ring->last_retired_head = -1; | |
2061 | intel_ring_update_space(ring); | |
2062 | ||
91c8a326 | 2063 | ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring); |
01101fa7 | 2064 | if (ret) { |
608c1a52 CW |
2065 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2066 | engine->name, ret); | |
2067 | list_del(&ring->link); | |
01101fa7 CW |
2068 | kfree(ring); |
2069 | return ERR_PTR(ret); | |
2070 | } | |
2071 | ||
2072 | return ring; | |
2073 | } | |
2074 | ||
2075 | void | |
7e37f889 | 2076 | intel_ring_free(struct intel_ring *ring) |
01101fa7 CW |
2077 | { |
2078 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2079 | list_del(&ring->link); |
01101fa7 CW |
2080 | kfree(ring); |
2081 | } | |
2082 | ||
0cb26a8e CW |
2083 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2084 | struct intel_engine_cs *engine) | |
2085 | { | |
2086 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2087 | int ret; | |
2088 | ||
91c8a326 | 2089 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2090 | |
2091 | if (ce->pin_count++) | |
2092 | return 0; | |
2093 | ||
2094 | if (ce->state) { | |
de895082 | 2095 | ret = i915_gem_object_ggtt_pin(ce->state, NULL, 0, |
737aac24 | 2096 | ctx->ggtt_alignment, PIN_HIGH); |
0cb26a8e CW |
2097 | if (ret) |
2098 | goto error; | |
2099 | } | |
2100 | ||
c7c3c07d CW |
2101 | /* The kernel context is only used as a placeholder for flushing the |
2102 | * active context. It is never used for submitting user rendering and | |
2103 | * as such never requires the golden render context, and so we can skip | |
2104 | * emitting it when we switch to the kernel context. This is required | |
2105 | * as during eviction we cannot allocate and pin the renderstate in | |
2106 | * order to initialise the context. | |
2107 | */ | |
2108 | if (ctx == ctx->i915->kernel_context) | |
2109 | ce->initialised = true; | |
2110 | ||
9a6feaf0 | 2111 | i915_gem_context_get(ctx); |
0cb26a8e CW |
2112 | return 0; |
2113 | ||
2114 | error: | |
2115 | ce->pin_count = 0; | |
2116 | return ret; | |
2117 | } | |
2118 | ||
2119 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2120 | struct intel_engine_cs *engine) | |
2121 | { | |
2122 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2123 | ||
91c8a326 | 2124 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2125 | |
2126 | if (--ce->pin_count) | |
2127 | return; | |
2128 | ||
2129 | if (ce->state) | |
2130 | i915_gem_object_ggtt_unpin(ce->state); | |
2131 | ||
9a6feaf0 | 2132 | i915_gem_context_put(ctx); |
0cb26a8e CW |
2133 | } |
2134 | ||
acd27845 | 2135 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 2136 | { |
acd27845 | 2137 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 2138 | struct intel_ring *ring; |
e3efda49 CW |
2139 | int ret; |
2140 | ||
0bc40be8 | 2141 | WARN_ON(engine->buffer); |
bfc882b4 | 2142 | |
019bf277 TU |
2143 | intel_engine_setup_common(engine); |
2144 | ||
0bc40be8 TU |
2145 | memset(engine->semaphore.sync_seqno, 0, |
2146 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2147 | |
019bf277 | 2148 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
2149 | if (ret) |
2150 | goto error; | |
e3efda49 | 2151 | |
0cb26a8e CW |
2152 | /* We may need to do things with the shrinker which |
2153 | * require us to immediately switch back to the default | |
2154 | * context. This can cause a problem as pinning the | |
2155 | * default context also requires GTT space which may not | |
2156 | * be available. To avoid this we always pin the default | |
2157 | * context. | |
2158 | */ | |
2159 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2160 | if (ret) | |
2161 | goto error; | |
2162 | ||
32c04f16 CW |
2163 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
2164 | if (IS_ERR(ring)) { | |
2165 | ret = PTR_ERR(ring); | |
b0366a54 DG |
2166 | goto error; |
2167 | } | |
32c04f16 | 2168 | engine->buffer = ring; |
01101fa7 | 2169 | |
c033666a | 2170 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2171 | ret = init_status_page(engine); |
e3efda49 | 2172 | if (ret) |
8ee14975 | 2173 | goto error; |
e3efda49 | 2174 | } else { |
0bc40be8 TU |
2175 | WARN_ON(engine->id != RCS); |
2176 | ret = init_phys_status_page(engine); | |
e3efda49 | 2177 | if (ret) |
8ee14975 | 2178 | goto error; |
e3efda49 CW |
2179 | } |
2180 | ||
aad29fbb | 2181 | ret = intel_ring_pin(ring); |
bfc882b4 DV |
2182 | if (ret) { |
2183 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2184 | engine->name, ret); |
32c04f16 | 2185 | intel_destroy_ringbuffer_obj(ring); |
bfc882b4 | 2186 | goto error; |
e3efda49 | 2187 | } |
62fdfeaf | 2188 | |
8ee14975 | 2189 | return 0; |
351e3db2 | 2190 | |
8ee14975 | 2191 | error: |
7e37f889 | 2192 | intel_engine_cleanup(engine); |
8ee14975 | 2193 | return ret; |
62fdfeaf EA |
2194 | } |
2195 | ||
7e37f889 | 2196 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 2197 | { |
6402c330 | 2198 | struct drm_i915_private *dev_priv; |
33626e6a | 2199 | |
117897f4 | 2200 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2201 | return; |
2202 | ||
c033666a | 2203 | dev_priv = engine->i915; |
6402c330 | 2204 | |
0bc40be8 | 2205 | if (engine->buffer) { |
c033666a | 2206 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2207 | |
aad29fbb | 2208 | intel_ring_unpin(engine->buffer); |
7e37f889 | 2209 | intel_ring_free(engine->buffer); |
0bc40be8 | 2210 | engine->buffer = NULL; |
b0366a54 | 2211 | } |
78501eac | 2212 | |
0bc40be8 TU |
2213 | if (engine->cleanup) |
2214 | engine->cleanup(engine); | |
8d19215b | 2215 | |
c033666a | 2216 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2217 | cleanup_status_page(engine); |
7d3fdfff | 2218 | } else { |
0bc40be8 TU |
2219 | WARN_ON(engine->id != RCS); |
2220 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2221 | } |
44e895a8 | 2222 | |
96a945aa | 2223 | intel_engine_cleanup_common(engine); |
0cb26a8e CW |
2224 | |
2225 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2226 | ||
c033666a | 2227 | engine->i915 = NULL; |
62fdfeaf EA |
2228 | } |
2229 | ||
6689cb2b | 2230 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2231 | { |
6310346e CW |
2232 | int ret; |
2233 | ||
2234 | /* Flush enough space to reduce the likelihood of waiting after | |
2235 | * we start building the request - in which case we will just | |
2236 | * have to repeat work. | |
2237 | */ | |
a0442461 | 2238 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2239 | |
1dae2dfb | 2240 | request->ring = request->engine->buffer; |
6310346e CW |
2241 | |
2242 | ret = intel_ring_begin(request, 0); | |
2243 | if (ret) | |
2244 | return ret; | |
2245 | ||
a0442461 | 2246 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2247 | return 0; |
9d773091 CW |
2248 | } |
2249 | ||
987046ad CW |
2250 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2251 | { | |
7e37f889 | 2252 | struct intel_ring *ring = req->ring; |
987046ad | 2253 | struct drm_i915_gem_request *target; |
7da844c5 | 2254 | int ret; |
987046ad | 2255 | |
1dae2dfb CW |
2256 | intel_ring_update_space(ring); |
2257 | if (ring->space >= bytes) | |
987046ad CW |
2258 | return 0; |
2259 | ||
2260 | /* | |
2261 | * Space is reserved in the ringbuffer for finalising the request, | |
2262 | * as that cannot be allowed to fail. During request finalisation, | |
2263 | * reserved_space is set to 0 to stop the overallocation and the | |
2264 | * assumption is that then we never need to wait (which has the | |
2265 | * risk of failing with EINTR). | |
2266 | * | |
2267 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2268 | */ | |
0251a963 | 2269 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 2270 | |
675d9ad7 | 2271 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad CW |
2272 | unsigned space; |
2273 | ||
987046ad | 2274 | /* Would completion of this request free enough space? */ |
1dae2dfb CW |
2275 | space = __intel_ring_space(target->postfix, ring->tail, |
2276 | ring->size); | |
987046ad CW |
2277 | if (space >= bytes) |
2278 | break; | |
79bbcc29 | 2279 | } |
29b1b415 | 2280 | |
675d9ad7 | 2281 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
2282 | return -ENOSPC; |
2283 | ||
776f3236 | 2284 | ret = i915_wait_request(target, true, NULL, NO_WAITBOOST); |
7da844c5 CW |
2285 | if (ret) |
2286 | return ret; | |
2287 | ||
2288 | if (i915_reset_in_progress(&target->i915->gpu_error)) | |
2289 | return -EAGAIN; | |
2290 | ||
2291 | i915_gem_request_retire_upto(target); | |
2292 | ||
2293 | intel_ring_update_space(ring); | |
2294 | GEM_BUG_ON(ring->space < bytes); | |
2295 | return 0; | |
29b1b415 JH |
2296 | } |
2297 | ||
987046ad | 2298 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2299 | { |
7e37f889 | 2300 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
2301 | int remain_actual = ring->size - ring->tail; |
2302 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
2303 | int bytes = num_dwords * sizeof(u32); |
2304 | int total_bytes, wait_bytes; | |
79bbcc29 | 2305 | bool need_wrap = false; |
29b1b415 | 2306 | |
0251a963 | 2307 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2308 | |
79bbcc29 JH |
2309 | if (unlikely(bytes > remain_usable)) { |
2310 | /* | |
2311 | * Not enough space for the basic request. So need to flush | |
2312 | * out the remainder and then wait for base + reserved. | |
2313 | */ | |
2314 | wait_bytes = remain_actual + total_bytes; | |
2315 | need_wrap = true; | |
987046ad CW |
2316 | } else if (unlikely(total_bytes > remain_usable)) { |
2317 | /* | |
2318 | * The base request will fit but the reserved space | |
2319 | * falls off the end. So we don't need an immediate wrap | |
2320 | * and only need to effectively wait for the reserved | |
2321 | * size space from the start of ringbuffer. | |
2322 | */ | |
0251a963 | 2323 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2324 | } else { |
987046ad CW |
2325 | /* No wrapping required, just waiting. */ |
2326 | wait_bytes = total_bytes; | |
cbcc80df MK |
2327 | } |
2328 | ||
1dae2dfb | 2329 | if (wait_bytes > ring->space) { |
987046ad | 2330 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df MK |
2331 | if (unlikely(ret)) |
2332 | return ret; | |
2333 | } | |
2334 | ||
987046ad | 2335 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
2336 | GEM_BUG_ON(remain_actual > ring->space); |
2337 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 2338 | |
987046ad | 2339 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
2340 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
2341 | ring->tail = 0; | |
2342 | ring->space -= remain_actual; | |
987046ad | 2343 | } |
304d695c | 2344 | |
1dae2dfb CW |
2345 | ring->space -= bytes; |
2346 | GEM_BUG_ON(ring->space < 0); | |
304d695c | 2347 | return 0; |
8187a2b7 | 2348 | } |
78501eac | 2349 | |
753b1ad4 | 2350 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2351 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2352 | { |
7e37f889 | 2353 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
2354 | int num_dwords = |
2355 | (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); | |
753b1ad4 VS |
2356 | int ret; |
2357 | ||
2358 | if (num_dwords == 0) | |
2359 | return 0; | |
2360 | ||
18393f63 | 2361 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2362 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2363 | if (ret) |
2364 | return ret; | |
2365 | ||
2366 | while (num_dwords--) | |
b5321f30 | 2367 | intel_ring_emit(ring, MI_NOOP); |
753b1ad4 | 2368 | |
b5321f30 | 2369 | intel_ring_advance(ring); |
753b1ad4 VS |
2370 | |
2371 | return 0; | |
2372 | } | |
2373 | ||
7e37f889 | 2374 | void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2375 | { |
c033666a | 2376 | struct drm_i915_private *dev_priv = engine->i915; |
498d2ac1 | 2377 | |
29dcb570 CW |
2378 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2379 | * so long as the semaphore value in the register/page is greater | |
2380 | * than the sync value), so whenever we reset the seqno, | |
2381 | * so long as we reset the tracking semaphore value to 0, it will | |
2382 | * always be before the next request's seqno. If we don't reset | |
2383 | * the semaphore value, then when the seqno moves backwards all | |
2384 | * future waits will complete instantly (causing rendering corruption). | |
2385 | */ | |
7e22dbbb | 2386 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
0bc40be8 TU |
2387 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2388 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2389 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2390 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2391 | } |
a058d934 CW |
2392 | if (dev_priv->semaphore_obj) { |
2393 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2394 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2395 | void *semaphores = kmap(page); | |
2396 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2397 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2398 | kunmap(page); | |
2399 | } | |
29dcb570 CW |
2400 | memset(engine->semaphore.sync_seqno, 0, |
2401 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2402 | |
1b7744e7 CW |
2403 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
2404 | if (engine->irq_seqno_barrier) | |
2405 | engine->irq_seqno_barrier(engine); | |
01347126 | 2406 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2407 | |
0bc40be8 | 2408 | engine->hangcheck.seqno = seqno; |
688e6c72 CW |
2409 | |
2410 | /* After manually advancing the seqno, fake the interrupt in case | |
2411 | * there are any waiters for that seqno. | |
2412 | */ | |
688e6c72 | 2413 | intel_engine_wakeup(engine); |
8187a2b7 | 2414 | } |
62fdfeaf | 2415 | |
c5efa1ad | 2416 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 2417 | { |
c5efa1ad | 2418 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2419 | |
76f8421f CW |
2420 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2421 | ||
881f47b6 | 2422 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2423 | |
2424 | /* Disable notification that the ring is IDLE. The GT | |
2425 | * will then assume that it is busy and bring it out of rc6. | |
2426 | */ | |
76f8421f CW |
2427 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2428 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2429 | |
2430 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2431 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2432 | |
12f55818 | 2433 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2434 | if (intel_wait_for_register_fw(dev_priv, |
2435 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2436 | GEN6_BSD_SLEEP_INDICATOR, | |
2437 | 0, | |
2438 | 50)) | |
12f55818 | 2439 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2440 | |
12f55818 | 2441 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2442 | i9xx_submit_request(request); |
12f55818 CW |
2443 | |
2444 | /* Let the ring send IDLE messages to the GT again, | |
2445 | * and so let it sleep to conserve power when idle. | |
2446 | */ | |
76f8421f CW |
2447 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2448 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2449 | ||
2450 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2451 | } |
2452 | ||
7c9cf4e3 | 2453 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 2454 | { |
7e37f889 | 2455 | struct intel_ring *ring = req->ring; |
71a77e07 | 2456 | uint32_t cmd; |
b72f3acb CW |
2457 | int ret; |
2458 | ||
5fb9de1a | 2459 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2460 | if (ret) |
2461 | return ret; | |
2462 | ||
71a77e07 | 2463 | cmd = MI_FLUSH_DW; |
c033666a | 2464 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2465 | cmd += 1; |
f0a1fb10 CW |
2466 | |
2467 | /* We always require a command barrier so that subsequent | |
2468 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2469 | * wrt the contents of the write cache being flushed to memory | |
2470 | * (and thus being coherent from the CPU). | |
2471 | */ | |
2472 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2473 | ||
9a289771 JB |
2474 | /* |
2475 | * Bspec vol 1c.5 - video engine command streamer: | |
2476 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2477 | * operation is complete. This bit is only valid when the | |
2478 | * Post-Sync Operation field is a value of 1h or 3h." | |
2479 | */ | |
7c9cf4e3 | 2480 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
2481 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2482 | ||
b5321f30 CW |
2483 | intel_ring_emit(ring, cmd); |
2484 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2485 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2486 | intel_ring_emit(ring, 0); /* upper addr */ |
2487 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2488 | } else { |
b5321f30 CW |
2489 | intel_ring_emit(ring, 0); |
2490 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2491 | } |
b5321f30 | 2492 | intel_ring_advance(ring); |
b72f3acb | 2493 | return 0; |
881f47b6 XH |
2494 | } |
2495 | ||
1c7a0623 | 2496 | static int |
803688ba CW |
2497 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
2498 | u64 offset, u32 len, | |
2499 | unsigned int dispatch_flags) | |
1c7a0623 | 2500 | { |
7e37f889 | 2501 | struct intel_ring *ring = req->ring; |
b5321f30 | 2502 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 2503 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2504 | int ret; |
2505 | ||
5fb9de1a | 2506 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2507 | if (ret) |
2508 | return ret; | |
2509 | ||
2510 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 | 2511 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2512 | (dispatch_flags & I915_DISPATCH_RS ? |
2513 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
b5321f30 CW |
2514 | intel_ring_emit(ring, lower_32_bits(offset)); |
2515 | intel_ring_emit(ring, upper_32_bits(offset)); | |
2516 | intel_ring_emit(ring, MI_NOOP); | |
2517 | intel_ring_advance(ring); | |
1c7a0623 BW |
2518 | |
2519 | return 0; | |
2520 | } | |
2521 | ||
d7d4eedd | 2522 | static int |
803688ba CW |
2523 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
2524 | u64 offset, u32 len, | |
2525 | unsigned int dispatch_flags) | |
d7d4eedd | 2526 | { |
7e37f889 | 2527 | struct intel_ring *ring = req->ring; |
d7d4eedd CW |
2528 | int ret; |
2529 | ||
5fb9de1a | 2530 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2531 | if (ret) |
2532 | return ret; | |
2533 | ||
b5321f30 | 2534 | intel_ring_emit(ring, |
77072258 | 2535 | MI_BATCH_BUFFER_START | |
8e004efc | 2536 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2537 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2538 | (dispatch_flags & I915_DISPATCH_RS ? | |
2539 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2540 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2541 | intel_ring_emit(ring, offset); |
2542 | intel_ring_advance(ring); | |
d7d4eedd CW |
2543 | |
2544 | return 0; | |
2545 | } | |
2546 | ||
881f47b6 | 2547 | static int |
803688ba CW |
2548 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
2549 | u64 offset, u32 len, | |
2550 | unsigned int dispatch_flags) | |
881f47b6 | 2551 | { |
7e37f889 | 2552 | struct intel_ring *ring = req->ring; |
0206e353 | 2553 | int ret; |
ab6f8e32 | 2554 | |
5fb9de1a | 2555 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2556 | if (ret) |
2557 | return ret; | |
e1f99ce6 | 2558 | |
b5321f30 | 2559 | intel_ring_emit(ring, |
d7d4eedd | 2560 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2561 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2562 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2563 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2564 | intel_ring_emit(ring, offset); |
2565 | intel_ring_advance(ring); | |
ab6f8e32 | 2566 | |
0206e353 | 2567 | return 0; |
881f47b6 XH |
2568 | } |
2569 | ||
549f7365 CW |
2570 | /* Blitter support (SandyBridge+) */ |
2571 | ||
7c9cf4e3 | 2572 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 2573 | { |
7e37f889 | 2574 | struct intel_ring *ring = req->ring; |
71a77e07 | 2575 | uint32_t cmd; |
b72f3acb CW |
2576 | int ret; |
2577 | ||
5fb9de1a | 2578 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2579 | if (ret) |
2580 | return ret; | |
2581 | ||
71a77e07 | 2582 | cmd = MI_FLUSH_DW; |
c033666a | 2583 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2584 | cmd += 1; |
f0a1fb10 CW |
2585 | |
2586 | /* We always require a command barrier so that subsequent | |
2587 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2588 | * wrt the contents of the write cache being flushed to memory | |
2589 | * (and thus being coherent from the CPU). | |
2590 | */ | |
2591 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2592 | ||
9a289771 JB |
2593 | /* |
2594 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2595 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2596 | * operation is complete. This bit is only valid when the | |
2597 | * Post-Sync Operation field is a value of 1h or 3h." | |
2598 | */ | |
7c9cf4e3 | 2599 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 2600 | cmd |= MI_INVALIDATE_TLB; |
b5321f30 CW |
2601 | intel_ring_emit(ring, cmd); |
2602 | intel_ring_emit(ring, | |
e2f80391 | 2603 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
c033666a | 2604 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2605 | intel_ring_emit(ring, 0); /* upper addr */ |
2606 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2607 | } else { |
b5321f30 CW |
2608 | intel_ring_emit(ring, 0); |
2609 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2610 | } |
b5321f30 | 2611 | intel_ring_advance(ring); |
fd3da6c9 | 2612 | |
b72f3acb | 2613 | return 0; |
8d19215b ZN |
2614 | } |
2615 | ||
d9a64610 TU |
2616 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2617 | struct intel_engine_cs *engine) | |
2618 | { | |
db3d4019 | 2619 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2620 | int ret, i; |
db3d4019 | 2621 | |
39df9190 | 2622 | if (!i915.semaphores) |
db3d4019 TU |
2623 | return; |
2624 | ||
2625 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { | |
91c8a326 | 2626 | obj = i915_gem_object_create(&dev_priv->drm, 4096); |
db3d4019 TU |
2627 | if (IS_ERR(obj)) { |
2628 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2629 | i915.semaphores = 0; | |
2630 | } else { | |
2631 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
737aac24 CW |
2632 | ret = i915_gem_object_ggtt_pin(obj, NULL, |
2633 | 0, 0, PIN_HIGH); | |
db3d4019 | 2634 | if (ret != 0) { |
f8c417cd | 2635 | i915_gem_object_put(obj); |
db3d4019 TU |
2636 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
2637 | i915.semaphores = 0; | |
2638 | } else { | |
2639 | dev_priv->semaphore_obj = obj; | |
2640 | } | |
2641 | } | |
2642 | } | |
2643 | ||
39df9190 | 2644 | if (!i915.semaphores) |
d9a64610 TU |
2645 | return; |
2646 | ||
2647 | if (INTEL_GEN(dev_priv) >= 8) { | |
1b9e6650 TU |
2648 | u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj); |
2649 | ||
ad7bdb2b | 2650 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 2651 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
2652 | |
2653 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2654 | u64 ring_offset; | |
2655 | ||
2656 | if (i != engine->id) | |
2657 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2658 | else | |
2659 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2660 | ||
2661 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2662 | } | |
d9a64610 | 2663 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 2664 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 2665 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
2666 | |
2667 | /* | |
2668 | * The current semaphore is only applied on pre-gen8 | |
2669 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2670 | * platform. So the semaphore between RCS and VCS2 is | |
2671 | * initialized as INVALID. Gen8 will initialize the | |
2672 | * sema between VCS2 and RCS later. | |
2673 | */ | |
2674 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2675 | static const struct { | |
2676 | u32 wait_mbox; | |
2677 | i915_reg_t mbox_reg; | |
2678 | } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { | |
2679 | [RCS] = { | |
2680 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2681 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2682 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
2683 | }, | |
2684 | [VCS] = { | |
2685 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2686 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2687 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
2688 | }, | |
2689 | [BCS] = { | |
2690 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2691 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2692 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
2693 | }, | |
2694 | [VECS] = { | |
2695 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2696 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2697 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
2698 | }, | |
2699 | }; | |
2700 | u32 wait_mbox; | |
2701 | i915_reg_t mbox_reg; | |
2702 | ||
2703 | if (i == engine->id || i == VCS2) { | |
2704 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
2705 | mbox_reg = GEN6_NOSYNC; | |
2706 | } else { | |
2707 | wait_mbox = sem_data[engine->id][i].wait_mbox; | |
2708 | mbox_reg = sem_data[engine->id][i].mbox_reg; | |
2709 | } | |
2710 | ||
2711 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2712 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2713 | } | |
d9a64610 TU |
2714 | } |
2715 | } | |
2716 | ||
ed003078 CW |
2717 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2718 | struct intel_engine_cs *engine) | |
2719 | { | |
c78d6061 TU |
2720 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2721 | ||
ed003078 | 2722 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2723 | engine->irq_enable = gen8_irq_enable; |
2724 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2725 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2726 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2727 | engine->irq_enable = gen6_irq_enable; |
2728 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2729 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2730 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2731 | engine->irq_enable = gen5_irq_enable; |
2732 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2733 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2734 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2735 | engine->irq_enable = i9xx_irq_enable; |
2736 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2737 | } else { |
31bb59cc CW |
2738 | engine->irq_enable = i8xx_irq_enable; |
2739 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2740 | } |
2741 | } | |
2742 | ||
06a2fe22 TU |
2743 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2744 | struct intel_engine_cs *engine) | |
2745 | { | |
618e4ca7 CW |
2746 | intel_ring_init_irq(dev_priv, engine); |
2747 | intel_ring_init_semaphores(dev_priv, engine); | |
2748 | ||
1d8a1337 | 2749 | engine->init_hw = init_ring_common; |
7445a2a4 | 2750 | |
ddd66c51 | 2751 | engine->emit_request = i9xx_emit_request; |
618e4ca7 CW |
2752 | if (i915.semaphores) |
2753 | engine->emit_request = gen6_sema_emit_request; | |
ddd66c51 | 2754 | engine->submit_request = i9xx_submit_request; |
6f7bef75 CW |
2755 | |
2756 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2757 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2758 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2759 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2760 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2761 | engine->emit_bb_start = i965_emit_bb_start; |
6f7bef75 | 2762 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
803688ba | 2763 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2764 | else |
803688ba | 2765 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2766 | } |
2767 | ||
8b3e2d36 | 2768 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2769 | { |
8b3e2d36 | 2770 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2771 | int ret; |
5c1143bb | 2772 | |
06a2fe22 TU |
2773 | intel_ring_default_vfuncs(dev_priv, engine); |
2774 | ||
61ff75ac CW |
2775 | if (HAS_L3_DPF(dev_priv)) |
2776 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2777 | |
c033666a | 2778 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2779 | engine->init_context = intel_rcs_ctx_init; |
ddd66c51 | 2780 | engine->emit_request = gen8_render_emit_request; |
c7fe7d25 | 2781 | engine->emit_flush = gen8_render_ring_flush; |
39df9190 | 2782 | if (i915.semaphores) |
e2f80391 | 2783 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2784 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2785 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2786 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2787 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2788 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2789 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2790 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2791 | } else { |
c033666a | 2792 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2793 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2794 | else |
c7fe7d25 | 2795 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2796 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2797 | } |
707d9cf9 | 2798 | |
c033666a | 2799 | if (IS_HASWELL(dev_priv)) |
803688ba | 2800 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2801 | |
e2f80391 TU |
2802 | engine->init_hw = init_render_ring; |
2803 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2804 | |
acd27845 | 2805 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2806 | if (ret) |
2807 | return ret; | |
2808 | ||
f8973c21 | 2809 | if (INTEL_GEN(dev_priv) >= 6) { |
7d5ea807 CW |
2810 | ret = intel_init_pipe_control(engine, 4096); |
2811 | if (ret) | |
2812 | return ret; | |
2813 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
2814 | ret = intel_init_pipe_control(engine, I830_WA_SIZE); | |
99be1dfe DV |
2815 | if (ret) |
2816 | return ret; | |
2817 | } | |
2818 | ||
2819 | return 0; | |
5c1143bb XH |
2820 | } |
2821 | ||
8b3e2d36 | 2822 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2823 | { |
8b3e2d36 | 2824 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2825 | |
06a2fe22 TU |
2826 | intel_ring_default_vfuncs(dev_priv, engine); |
2827 | ||
c033666a | 2828 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2829 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2830 | if (IS_GEN6(dev_priv)) |
c5efa1ad | 2831 | engine->submit_request = gen6_bsd_submit_request; |
c7fe7d25 | 2832 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2833 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2834 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2835 | } else { |
e2f80391 | 2836 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2837 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2838 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2839 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2840 | else |
e2f80391 | 2841 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2842 | } |
58fa3835 | 2843 | |
acd27845 | 2844 | return intel_init_ring_buffer(engine); |
5c1143bb | 2845 | } |
549f7365 | 2846 | |
845f74a7 | 2847 | /** |
62659920 | 2848 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2849 | */ |
8b3e2d36 | 2850 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2851 | { |
8b3e2d36 | 2852 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2853 | |
2854 | intel_ring_default_vfuncs(dev_priv, engine); | |
2855 | ||
c7fe7d25 | 2856 | engine->emit_flush = gen6_bsd_ring_flush; |
845f74a7 | 2857 | |
acd27845 | 2858 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2859 | } |
2860 | ||
8b3e2d36 | 2861 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2862 | { |
8b3e2d36 | 2863 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2864 | |
2865 | intel_ring_default_vfuncs(dev_priv, engine); | |
2866 | ||
c7fe7d25 | 2867 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2868 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2869 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2870 | |
acd27845 | 2871 | return intel_init_ring_buffer(engine); |
549f7365 | 2872 | } |
a7b9761d | 2873 | |
8b3e2d36 | 2874 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2875 | { |
8b3e2d36 | 2876 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2877 | |
2878 | intel_ring_default_vfuncs(dev_priv, engine); | |
2879 | ||
c7fe7d25 | 2880 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2881 | |
c78d6061 | 2882 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2883 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2884 | engine->irq_enable = hsw_vebox_irq_enable; |
2885 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2886 | } |
9a8a2213 | 2887 | |
acd27845 | 2888 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2889 | } |