projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: don't reallocate the compressed FB at every frame
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 382
add284a3
CW		 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
f3987631
PZ		 385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
b9e1faa7 397 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
9688ecad 401 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
4772eaeb
PZ		 404 return 0;
405}
406
884ceace
KG		 407static int
408gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410{
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426}
427
a5f3d68e 428static int
a4872ba6 429gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 430 u32 invalidate_domains, u32 flush_domains)
431{
432 u32 flags = 0;
18393f63 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 434 int ret;
a5f3d68e
BW		 435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
a5f3d68e
BW		 459 }
460
c5ad011d
RV		 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
a5f3d68e
BW		 469}
470
a4872ba6 471static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 472 u32 value)
d46eefa2 473{
4640c4ff 474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 475 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 476}
477
a4872ba6 478u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 479{
4640c4ff 480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 481 u64 acthd;
8187a2b7 482
50877445
CW		 483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
8187a2b7
ZN		 492}
493
a4872ba6 494static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503}
504
af75f269
DL		 505static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
506{
507 struct drm_device *dev = ring->dev;
508 struct drm_i915_private *dev_priv = ring->dev->dev_private;
509 u32 mmio = 0;
510
511 /* The ring status page addresses are no longer next to the rest of
512 * the ring registers as of gen7.
513 */
514 if (IS_GEN7(dev)) {
515 switch (ring->id) {
516 case RCS:
517 mmio = RENDER_HWS_PGA_GEN7;
518 break;
519 case BCS:
520 mmio = BLT_HWS_PGA_GEN7;
521 break;
522 /*
523 * VCS2 actually doesn't exist on Gen7. Only shut up
524 * gcc switch check warning
525 */
526 case VCS2:
527 case VCS:
528 mmio = BSD_HWS_PGA_GEN7;
529 break;
530 case VECS:
531 mmio = VEBOX_HWS_PGA_GEN7;
532 break;
533 }
534 } else if (IS_GEN6(ring->dev)) {
535 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
536 } else {
537 /* XXX: gen8 returns to sanity */
538 mmio = RING_HWS_PGA(ring->mmio_base);
539 }
540
541 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
542 POSTING_READ(mmio);
543
544 /*
545 * Flush the TLB for this page
546 *
547 * FIXME: These two bits have disappeared on gen8, so a question
548 * arises: do we still need this and if so how should we go about
549 * invalidating the TLB?
550 */
551 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
552 u32 reg = RING_INSTPM(ring->mmio_base);
553
554 /* ring should be idle before issuing a sync flush*/
555 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
556
557 I915_WRITE(reg,
558 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
559 INSTPM_SYNC_FLUSH));
560 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
561 1000))
562 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
563 ring->name);
564 }
565}
566
a4872ba6 567static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 568{
9991ae78 569 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 570
9991ae78
CW		 571 if (!IS_GEN2(ring->dev)) {
572 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 573 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
574 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 575 /* Sometimes we observe that the idle flag is not
576 * set even though the ring is empty. So double
577 * check before giving up.
578 */
579 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
580 return false;
9991ae78
CW		 581 }
582 }
b7884eb4 583
7f2ab699 584 I915_WRITE_CTL(ring, 0);
570ef608 585 I915_WRITE_HEAD(ring, 0);
78501eac 586 ring->write_tail(ring, 0);
8187a2b7 587
9991ae78
CW		 588 if (!IS_GEN2(ring->dev)) {
589 (void)I915_READ_CTL(ring);
590 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
591 }
a51435a3 592
9991ae78
CW		 593 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
594}
8187a2b7 595
a4872ba6 596static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 597{
598 struct drm_device *dev = ring->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 600 struct intel_ringbuffer *ringbuf = ring->buffer;
601 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 602 int ret = 0;
603
59bad947 604 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 605
606 if (!stop_ring(ring)) {
607 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 608 DRM_DEBUG_KMS("%s head not reset to zero "
609 "ctl %08x head %08x tail %08x start %08x\n",
610 ring->name,
611 I915_READ_CTL(ring),
612 I915_READ_HEAD(ring),
613 I915_READ_TAIL(ring),
614 I915_READ_START(ring));
8187a2b7 615
9991ae78 616 if (!stop_ring(ring)) {
6fd0d56e
CW		 617 DRM_ERROR("failed to set %s head to zero "
618 "ctl %08x head %08x tail %08x start %08x\n",
619 ring->name,
620 I915_READ_CTL(ring),
621 I915_READ_HEAD(ring),
622 I915_READ_TAIL(ring),
623 I915_READ_START(ring));
9991ae78
CW		 624 ret = -EIO;
625 goto out;
6fd0d56e 626 }
8187a2b7
ZN		 627 }
628
9991ae78
CW		 629 if (I915_NEED_GFX_HWS(dev))
630 intel_ring_setup_status_page(ring);
631 else
632 ring_setup_phys_status_page(ring);
633
ece4a17d
JK		 634 /* Enforce ordering by reading HEAD register back */
635 I915_READ_HEAD(ring);
636
0d8957c8
DV		 637 /* Initialize the ring. This must happen _after_ we've cleared the ring
638 * registers with the above sequence (the readback of the HEAD registers
639 * also enforces ordering), otherwise the hw might lose the new ring
640 * register values. */
f343c5f6 641 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 642
643 /* WaClearRingBufHeadRegAtInit:ctg,elk */
644 if (I915_READ_HEAD(ring))
645 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
646 ring->name, I915_READ_HEAD(ring));
647 I915_WRITE_HEAD(ring, 0);
648 (void)I915_READ_HEAD(ring);
649
7f2ab699 650 I915_WRITE_CTL(ring,
93b0a4e0 651 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 652 | RING_VALID);
8187a2b7 653
8187a2b7 654 /* If the head is still not zero, the ring is dead */
f01db988 655 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 656 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 657 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 658 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 659 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
660 ring->name,
661 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
662 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
663 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 664 ret = -EIO;
665 goto out;
8187a2b7
ZN		 666 }
667
ebd0fd4b 668 ringbuf->last_retired_head = -1;
5c6c6003
CW		 669 ringbuf->head = I915_READ_HEAD(ring);
670 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 671 intel_ring_update_space(ringbuf);
1ec14ad3 672
50f018df
CW		 673 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
674
b7884eb4 675out:
59bad947 676 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 677
678 return ret;
8187a2b7
ZN		 679}
680
9b1136d5
OM		 681void
682intel_fini_pipe_control(struct intel_engine_cs *ring)
683{
684 struct drm_device *dev = ring->dev;
685
686 if (ring->scratch.obj == NULL)
687 return;
688
689 if (INTEL_INFO(dev)->gen >= 5) {
690 kunmap(sg_page(ring->scratch.obj->pages->sgl));
691 i915_gem_object_ggtt_unpin(ring->scratch.obj);
692 }
693
694 drm_gem_object_unreference(&ring->scratch.obj->base);
695 ring->scratch.obj = NULL;
696}
697
698int
699intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 700{
c6df541c
CW		 701 int ret;
702
bfc882b4 703 WARN_ON(ring->scratch.obj);
c6df541c 704
0d1aacac
CW		 705 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
706 if (ring->scratch.obj == NULL) {
c6df541c
CW		 707 DRM_ERROR("Failed to allocate seqno page\n");
708 ret = -ENOMEM;
709 goto err;
710 }
e4ffd173 711
a9cc726c
DV		 712 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
713 if (ret)
714 goto err_unref;
c6df541c 715
1ec9e26d 716 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 717 if (ret)
718 goto err_unref;
719
0d1aacac
CW		 720 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
721 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
722 if (ring->scratch.cpu_page == NULL) {
56b085a0 723 ret = -ENOMEM;
c6df541c 724 goto err_unpin;
56b085a0 725 }
c6df541c 726
2b1086cc 727 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 728 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 729 return 0;
730
731err_unpin:
d7f46fc4 732 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 733err_unref:
0d1aacac 734 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 735err:
c6df541c
CW		 736 return ret;
737}
738
771b9a53
MT		 739static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
740 struct intel_context *ctx)
86d7f238 741{
7225342a 742 int ret, i;
888b5995
AS		 743 struct drm_device *dev = ring->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 745 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 746
e6c1abb7 747 if (WARN_ON_ONCE(w->count == 0))
7225342a 748 return 0;
888b5995 749
7225342a
MK		 750 ring->gpu_caches_dirty = true;
751 ret = intel_ring_flush_all_caches(ring);
752 if (ret)
753 return ret;
888b5995 754
22a916aa 755 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 756 if (ret)
757 return ret;
758
22a916aa 759 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 760 for (i = 0; i < w->count; i++) {
7225342a
MK		 761 intel_ring_emit(ring, w->reg[i].addr);
762 intel_ring_emit(ring, w->reg[i].value);
763 }
22a916aa 764 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 765
766 intel_ring_advance(ring);
767
768 ring->gpu_caches_dirty = true;
769 ret = intel_ring_flush_all_caches(ring);
770 if (ret)
771 return ret;
888b5995 772
7225342a 773 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 774
7225342a 775 return 0;
86d7f238
AS		 776}
777
8f0e2b9d
DV		 778static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
779 struct intel_context *ctx)
780{
781 int ret;
782
783 ret = intel_ring_workarounds_emit(ring, ctx);
784 if (ret != 0)
785 return ret;
786
787 ret = i915_gem_render_state_init(ring);
788 if (ret)
789 DRM_ERROR("init render state: %d\n", ret);
790
791 return ret;
792}
793
7225342a 794static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 795 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 796{
797 const u32 idx = dev_priv->workarounds.count;
798
799 if (WARN_ON(idx >= I915_MAX_WA_REGS))
800 return -ENOSPC;
801
802 dev_priv->workarounds.reg[idx].addr = addr;
803 dev_priv->workarounds.reg[idx].value = val;
804 dev_priv->workarounds.reg[idx].mask = mask;
805
806 dev_priv->workarounds.count++;
807
808 return 0;
86d7f238
AS		 809}
810
cf4b0de6
DL		 811#define WA_REG(addr, mask, val) { \
812 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 813 if (r) \
814 return r; \
815 }
816
817#define WA_SET_BIT_MASKED(addr, mask) \
26459343 818 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 819
820#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 821 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 822
98533251 823#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 824 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 825
cf4b0de6
DL		 826#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
827#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 828
cf4b0de6 829#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 830
00e1e623 831static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 832{
888b5995
AS		 833 struct drm_device *dev = ring->dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 835
86d7f238 836 /* WaDisablePartialInstShootdown:bdw */
101b376d 837 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 838 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
839 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
840 STALL_DOP_GATING_DISABLE);
86d7f238 841
101b376d 842 /* WaDisableDopClockGating:bdw */
7225342a
MK		 843 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
844 DOP_CLOCK_GATING_DISABLE);
86d7f238 845
7225342a
MK		 846 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
847 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 848
849 /* Use Force Non-Coherent whenever executing a 3D context. This is a
850 * workaround for for a possible hang in the unlikely event a TLB
851 * invalidation occurs during a PSD flush.
852 */
7225342a 853 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 854 /* WaForceEnableNonCoherent:bdw */
7225342a 855 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 856 /* WaForceContextSaveRestoreNonCoherent:bdw */
857 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
858 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 859 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 860 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 861 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 862
2701fc43
KG		 863 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
864 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
865 * polygons in the same 8x4 pixel/sample area to be processed without
866 * stalling waiting for the earlier ones to write to Hierarchical Z
867 * buffer."
868 *
869 * This optimization is off by default for Broadwell; turn it on.
870 */
871 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
872
86d7f238 873 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 874 WA_SET_BIT_MASKED(CACHE_MODE_1,
875 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 876
877 /*
878 * BSpec recommends 8x4 when MSAA is used,
879 * however in practice 16x4 seems fastest.
880 *
881 * Note that PS/WM thread counts depend on the WIZ hashing
882 * disable bit, which we don't touch here, but it's good
883 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
884 */
98533251
DL		 885 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
886 GEN6_WIZ_HASHING_MASK,
887 GEN6_WIZ_HASHING_16x4);
888b5995 888
86d7f238
AS		 889 return 0;
890}
891
00e1e623
VS		 892static int chv_init_workarounds(struct intel_engine_cs *ring)
893{
00e1e623
VS		 894 struct drm_device *dev = ring->dev;
895 struct drm_i915_private *dev_priv = dev->dev_private;
896
00e1e623 897 /* WaDisablePartialInstShootdown:chv */
00e1e623 898 /* WaDisableThreadStallDopClockGating:chv */
7225342a 899 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 900 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
901 STALL_DOP_GATING_DISABLE);
00e1e623 902
95289009
AS		 903 /* Use Force Non-Coherent whenever executing a 3D context. This is a
904 * workaround for a possible hang in the unlikely event a TLB
905 * invalidation occurs during a PSD flush.
906 */
907 /* WaForceEnableNonCoherent:chv */
908 /* WaHdcDisableFetchWhenMasked:chv */
909 WA_SET_BIT_MASKED(HDC_CHICKEN0,
910 HDC_FORCE_NON_COHERENT |
911 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
912
973a5b06
KG		 913 /* According to the CACHE_MODE_0 default value documentation, some
914 * CHV platforms disable this optimization by default. Turn it on.
915 */
916 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
917
14bc16e3
VS		 918 /* Wa4x4STCOptimizationDisable:chv */
919 WA_SET_BIT_MASKED(CACHE_MODE_1,
920 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
921
d60de81d
KG		 922 /* Improve HiZ throughput on CHV. */
923 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
924
e7fc2436
VS		 925 /*
926 * BSpec recommends 8x4 when MSAA is used,
927 * however in practice 16x4 seems fastest.
928 *
929 * Note that PS/WM thread counts depend on the WIZ hashing
930 * disable bit, which we don't touch here, but it's good
931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
932 */
933 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
934 GEN6_WIZ_HASHING_MASK,
935 GEN6_WIZ_HASHING_16x4);
936
65ca7514
DL		 937 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
938 INTEL_REVID(dev) == SKL_REVID_D0)
939 /* WaBarrierPerformanceFixDisable:skl */
940 WA_SET_BIT_MASKED(HDC_CHICKEN0,
941 HDC_FENCE_DEST_SLM_DISABLE |
942 HDC_BARRIER_PERFORMANCE_DISABLE);
943
7225342a
MK		 944 return 0;
945}
946
3b106531
HN		 947static int gen9_init_workarounds(struct intel_engine_cs *ring)
948{
ab0dfafe
HN		 949 struct drm_device *dev = ring->dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
951
952 /* WaDisablePartialInstShootdown:skl */
953 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
954 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
955
8424171e
NH		 956 /* Syncing dependencies between camera and graphics */
957 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
958 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
959
35c8ce6a
DL		 960 if (INTEL_REVID(dev) == SKL_REVID_A0 ||
961 INTEL_REVID(dev) == SKL_REVID_B0) {
a86eb582
DL		 962 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
963 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
964 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 965 }
966
183c6dac
DL		 967 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
968 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
969 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
970 GEN9_RHWO_OPTIMIZATION_DISABLE);
971 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
972 DISABLE_PIXEL_MASK_CAMMING);
973 }
974
cac23df4
NH		 975 if (INTEL_REVID(dev) >= SKL_REVID_C0) {
976 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
977 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
978 GEN9_ENABLE_YV12_BUGFIX);
979 }
980
13bea49c
HN		 981 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
982 /*
983 *Use Force Non-Coherent whenever executing a 3D context. This
984 * is a workaround for a possible hang in the unlikely event
985 * a TLB invalidation occurs during a PSD flush.
986 */
987 /* WaForceEnableNonCoherent:skl */
988 WA_SET_BIT_MASKED(HDC_CHICKEN0,
989 HDC_FORCE_NON_COHERENT);
990 }
991
1840481f
HN		 992 /* Wa4x4STCOptimizationDisable:skl */
993 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
994
9370cd98
DL		 995 /* WaDisablePartialResolveInVc:skl */
996 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
997
e2db7071
DL		 998 /* WaCcsTlbPrefetchDisable:skl */
999 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
1000 GEN9_CCS_TLB_PREFETCH_ENABLE);
1001
3b106531
HN		 1002 return 0;
1003}
1004
8d205494
DL		 1005static int skl_init_workarounds(struct intel_engine_cs *ring)
1006{
d0bbbc4f
DL		 1007 struct drm_device *dev = ring->dev;
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009
8d205494
DL		 1010 gen9_init_workarounds(ring);
1011
d0bbbc4f
DL		 1012 /* WaDisablePowerCompilerClockGating:skl */
1013 if (INTEL_REVID(dev) == SKL_REVID_B0)
1014 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1015 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1016
8d205494
DL		 1017 return 0;
1018}
1019
771b9a53 1020int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1021{
1022 struct drm_device *dev = ring->dev;
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024
1025 WARN_ON(ring->id != RCS);
1026
1027 dev_priv->workarounds.count = 0;
1028
1029 if (IS_BROADWELL(dev))
1030 return bdw_init_workarounds(ring);
1031
1032 if (IS_CHERRYVIEW(dev))
1033 return chv_init_workarounds(ring);
00e1e623 1034
8d205494
DL		 1035 if (IS_SKYLAKE(dev))
1036 return skl_init_workarounds(ring);
1037 else if (IS_GEN9(dev))
3b106531
HN		 1038 return gen9_init_workarounds(ring);
1039
00e1e623
VS		 1040 return 0;
1041}
1042
a4872ba6 1043static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1044{
78501eac 1045 struct drm_device *dev = ring->dev;
1ec14ad3 1046 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1047 int ret = init_ring_common(ring);
9c33baa6
KZ		 1048 if (ret)
1049 return ret;
a69ffdbf 1050
61a563a2
AG		 1051 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1052 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1053 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1054
1055 /* We need to disable the AsyncFlip performance optimisations in order
1056 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1057 * programmed to '1' on all products.
8693a824 1058 *
b3f797ac 1059 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 1060 */
fbdcb068 1061 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 1062 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1063
f05bb0c7 1064 /* Required for the hardware to program scanline values for waiting */
01fa0302 1065 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1066 if (INTEL_INFO(dev)->gen == 6)
1067 I915_WRITE(GFX_MODE,
aa83e30d 1068 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1069
01fa0302 1070 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1071 if (IS_GEN7(dev))
1072 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1073 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1074 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1075
5e13a0c5 1076 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1077 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1078 * "If this bit is set, STCunit will have LRA as replacement
1079 * policy. [...] This bit must be reset. LRA replacement
1080 * policy is not supported."
1081 */
1082 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1083 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1084 }
1085
6b26c86d
DV		 1086 if (INTEL_INFO(dev)->gen >= 6)
1087 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1088
040d2baa 1089 if (HAS_L3_DPF(dev))
35a85ac6 1090 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1091
7225342a 1092 return init_workarounds_ring(ring);
8187a2b7
ZN		 1093}
1094
a4872ba6 1095static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1096{
b45305fc 1097 struct drm_device *dev = ring->dev;
3e78998a
BW		 1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099
1100 if (dev_priv->semaphore_obj) {
1101 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1102 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1103 dev_priv->semaphore_obj = NULL;
1104 }
b45305fc 1105
9b1136d5 1106 intel_fini_pipe_control(ring);
c6df541c
CW		 1107}
1108
3e78998a
BW		 1109static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1110 unsigned int num_dwords)
1111{
1112#define MBOX_UPDATE_DWORDS 8
1113 struct drm_device *dev = signaller->dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 struct intel_engine_cs *waiter;
1116 int i, ret, num_rings;
1117
1118 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1119 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1120#undef MBOX_UPDATE_DWORDS
1121
1122 ret = intel_ring_begin(signaller, num_dwords);
1123 if (ret)
1124 return ret;
1125
1126 for_each_ring(waiter, dev_priv, i) {
6259cead 1127 u32 seqno;
3e78998a
BW		 1128 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1129 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1130 continue;
1131
6259cead
JH		 1132 seqno = i915_gem_request_get_seqno(
1133 signaller->outstanding_lazy_request);
3e78998a
BW		 1134 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1135 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1136 PIPE_CONTROL_QW_WRITE |
1137 PIPE_CONTROL_FLUSH_ENABLE);
1138 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1139 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1140 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1141 intel_ring_emit(signaller, 0);
1142 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1143 MI_SEMAPHORE_TARGET(waiter->id));
1144 intel_ring_emit(signaller, 0);
1145 }
1146
1147 return 0;
1148}
1149
1150static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1151 unsigned int num_dwords)
1152{
1153#define MBOX_UPDATE_DWORDS 6
1154 struct drm_device *dev = signaller->dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 struct intel_engine_cs *waiter;
1157 int i, ret, num_rings;
1158
1159 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1160 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1161#undef MBOX_UPDATE_DWORDS
1162
1163 ret = intel_ring_begin(signaller, num_dwords);
1164 if (ret)
1165 return ret;
1166
1167 for_each_ring(waiter, dev_priv, i) {
6259cead 1168 u32 seqno;
3e78998a
BW		 1169 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1170 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1171 continue;
1172
6259cead
JH		 1173 seqno = i915_gem_request_get_seqno(
1174 signaller->outstanding_lazy_request);
3e78998a
BW		 1175 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1176 MI_FLUSH_DW_OP_STOREDW);
1177 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1178 MI_FLUSH_DW_USE_GTT);
1179 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1180 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1181 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1182 MI_SEMAPHORE_TARGET(waiter->id));
1183 intel_ring_emit(signaller, 0);
1184 }
1185
1186 return 0;
1187}
1188
a4872ba6 1189static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1190 unsigned int num_dwords)
1ec14ad3 1191{
024a43e1
BW		 1192 struct drm_device *dev = signaller->dev;
1193 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1194 struct intel_engine_cs *useless;
a1444b79 1195 int i, ret, num_rings;
78325f2d 1196
a1444b79
BW		 1197#define MBOX_UPDATE_DWORDS 3
1198 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1199 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1200#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1201
1202 ret = intel_ring_begin(signaller, num_dwords);
1203 if (ret)
1204 return ret;
024a43e1 1205
78325f2d
BW		 1206 for_each_ring(useless, dev_priv, i) {
1207 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1208 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1209 u32 seqno = i915_gem_request_get_seqno(
1210 signaller->outstanding_lazy_request);
78325f2d
BW		 1211 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1212 intel_ring_emit(signaller, mbox_reg);
6259cead 1213 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1214 }
1215 }
024a43e1 1216
a1444b79
BW		 1217 /* If num_dwords was rounded, make sure the tail pointer is correct */
1218 if (num_rings % 2 == 0)
1219 intel_ring_emit(signaller, MI_NOOP);
1220
024a43e1 1221 return 0;
1ec14ad3
CW		 1222}
1223
c8c99b0f
BW		 1224/**
1225 * gen6_add_request - Update the semaphore mailbox registers
1226 *
1227 * @ring - ring that is adding a request
1228 * @seqno - return seqno stuck into the ring
1229 *
1230 * Update the mailbox registers in the *other* rings with the current seqno.
1231 * This acts like a signal in the canonical semaphore.
1232 */
1ec14ad3 1233static int
a4872ba6 1234gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1235{
024a43e1 1236 int ret;
52ed2325 1237
707d9cf9
BW		 1238 if (ring->semaphore.signal)
1239 ret = ring->semaphore.signal(ring, 4);
1240 else
1241 ret = intel_ring_begin(ring, 4);
1242
1ec14ad3
CW		 1243 if (ret)
1244 return ret;
1245
1ec14ad3
CW		 1246 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1247 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1248 intel_ring_emit(ring,
1249 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1250 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1251 __intel_ring_advance(ring);
1ec14ad3 1252
1ec14ad3
CW		 1253 return 0;
1254}
1255
f72b3435
MK		 1256static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1257 u32 seqno)
1258{
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 return dev_priv->last_seqno < seqno;
1261}
1262
c8c99b0f
BW		 1263/**
1264 * intel_ring_sync - sync the waiter to the signaller on seqno
1265 *
1266 * @waiter - ring that is waiting
1267 * @signaller - ring which has, or will signal
1268 * @seqno - seqno which the waiter will block on
1269 */
5ee426ca
BW		 1270
1271static int
1272gen8_ring_sync(struct intel_engine_cs *waiter,
1273 struct intel_engine_cs *signaller,
1274 u32 seqno)
1275{
1276 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1277 int ret;
1278
1279 ret = intel_ring_begin(waiter, 4);
1280 if (ret)
1281 return ret;
1282
1283 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1284 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1285 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1286 MI_SEMAPHORE_SAD_GTE_SDD);
1287 intel_ring_emit(waiter, seqno);
1288 intel_ring_emit(waiter,
1289 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1290 intel_ring_emit(waiter,
1291 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1292 intel_ring_advance(waiter);
1293 return 0;
1294}
1295
c8c99b0f 1296static int
a4872ba6
OM		 1297gen6_ring_sync(struct intel_engine_cs *waiter,
1298 struct intel_engine_cs *signaller,
686cb5f9 1299 u32 seqno)
1ec14ad3 1300{
c8c99b0f
BW		 1301 u32 dw1 = MI_SEMAPHORE_MBOX |
1302 MI_SEMAPHORE_COMPARE |
1303 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1304 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1305 int ret;
1ec14ad3 1306
1500f7ea
BW		 1307 /* Throughout all of the GEM code, seqno passed implies our current
1308 * seqno is >= the last seqno executed. However for hardware the
1309 * comparison is strictly greater than.
1310 */
1311 seqno -= 1;
1312
ebc348b2 1313 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1314
c8c99b0f 1315 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1316 if (ret)
1317 return ret;
1318
f72b3435
MK		 1319 /* If seqno wrap happened, omit the wait with no-ops */
1320 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1321 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1322 intel_ring_emit(waiter, seqno);
1323 intel_ring_emit(waiter, 0);
1324 intel_ring_emit(waiter, MI_NOOP);
1325 } else {
1326 intel_ring_emit(waiter, MI_NOOP);
1327 intel_ring_emit(waiter, MI_NOOP);
1328 intel_ring_emit(waiter, MI_NOOP);
1329 intel_ring_emit(waiter, MI_NOOP);
1330 }
c8c99b0f 1331 intel_ring_advance(waiter);
1ec14ad3
CW		 1332
1333 return 0;
1334}
1335
c6df541c
CW		 1336#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1337do { \
fcbc34e4
KG		 1338 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1339 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1340 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1341 intel_ring_emit(ring__, 0); \
1342 intel_ring_emit(ring__, 0); \
1343} while (0)
1344
1345static int
a4872ba6 1346pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1347{
18393f63 1348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1349 int ret;
1350
1351 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1352 * incoherent with writes to memory, i.e. completely fubar,
1353 * so we need to use PIPE_NOTIFY instead.
1354 *
1355 * However, we also need to workaround the qword write
1356 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1357 * memory before requesting an interrupt.
1358 */
1359 ret = intel_ring_begin(ring, 32);
1360 if (ret)
1361 return ret;
1362
fcbc34e4 1363 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1364 PIPE_CONTROL_WRITE_FLUSH |
1365 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1366 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1367 intel_ring_emit(ring,
1368 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1369 intel_ring_emit(ring, 0);
1370 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1371 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1372 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1373 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1374 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1375 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1376 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1377 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1378 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1379 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1380 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1381
fcbc34e4 1382 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1383 PIPE_CONTROL_WRITE_FLUSH |
1384 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1385 PIPE_CONTROL_NOTIFY);
0d1aacac 1386 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1387 intel_ring_emit(ring,
1388 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1389 intel_ring_emit(ring, 0);
09246732 1390 __intel_ring_advance(ring);
c6df541c 1391
c6df541c
CW		 1392 return 0;
1393}
1394
4cd53c0c 1395static u32
a4872ba6 1396gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1397{
4cd53c0c
DV		 1398 /* Workaround to force correct ordering between irq and seqno writes on
1399 * ivb (and maybe also on snb) by reading from a CS register (like
1400 * ACTHD) before reading the status page. */
50877445
CW		 1401 if (!lazy_coherency) {
1402 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1403 POSTING_READ(RING_ACTHD(ring->mmio_base));
1404 }
1405
4cd53c0c
DV		 1406 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1407}
1408
8187a2b7 1409static u32
a4872ba6 1410ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1411{
1ec14ad3
CW		 1412 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1413}
1414
b70ec5bf 1415static void
a4872ba6 1416ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1417{
1418 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1419}
1420
c6df541c 1421static u32
a4872ba6 1422pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1423{
0d1aacac 1424 return ring->scratch.cpu_page[0];
c6df541c
CW		 1425}
1426
b70ec5bf 1427static void
a4872ba6 1428pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1429{
0d1aacac 1430 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1431}
1432
e48d8634 1433static bool
a4872ba6 1434gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1435{
1436 struct drm_device *dev = ring->dev;
4640c4ff 1437 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1438 unsigned long flags;
e48d8634 1439
7cd512f1 1440 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1441 return false;
1442
7338aefa 1443 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1444 if (ring->irq_refcount++ == 0)
480c8033 1445 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1446 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1447
1448 return true;
1449}
1450
1451static void
a4872ba6 1452gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1453{
1454 struct drm_device *dev = ring->dev;
4640c4ff 1455 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1456 unsigned long flags;
e48d8634 1457
7338aefa 1458 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1459 if (--ring->irq_refcount == 0)
480c8033 1460 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1461 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1462}
1463
b13c2b96 1464static bool
a4872ba6 1465i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1466{
78501eac 1467 struct drm_device *dev = ring->dev;
4640c4ff 1468 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1469 unsigned long flags;
62fdfeaf 1470
7cd512f1 1471 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1472 return false;
1473
7338aefa 1474 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1475 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1476 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1477 I915_WRITE(IMR, dev_priv->irq_mask);
1478 POSTING_READ(IMR);
1479 }
7338aefa 1480 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1481
1482 return true;
62fdfeaf
EA		 1483}
1484
8187a2b7 1485static void
a4872ba6 1486i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1487{
78501eac 1488 struct drm_device *dev = ring->dev;
4640c4ff 1489 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1490 unsigned long flags;
62fdfeaf 1491
7338aefa 1492 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1493 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1494 dev_priv->irq_mask |= ring->irq_enable_mask;
1495 I915_WRITE(IMR, dev_priv->irq_mask);
1496 POSTING_READ(IMR);
1497 }
7338aefa 1498 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1499}
1500
c2798b19 1501static bool
a4872ba6 1502i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1503{
1504 struct drm_device *dev = ring->dev;
4640c4ff 1505 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1506 unsigned long flags;
c2798b19 1507
7cd512f1 1508 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1509 return false;
1510
7338aefa 1511 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1512 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1513 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1514 I915_WRITE16(IMR, dev_priv->irq_mask);
1515 POSTING_READ16(IMR);
1516 }
7338aefa 1517 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1518
1519 return true;
1520}
1521
1522static void
a4872ba6 1523i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1524{
1525 struct drm_device *dev = ring->dev;
4640c4ff 1526 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1527 unsigned long flags;
c2798b19 1528
7338aefa 1529 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1530 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1531 dev_priv->irq_mask |= ring->irq_enable_mask;
1532 I915_WRITE16(IMR, dev_priv->irq_mask);
1533 POSTING_READ16(IMR);
1534 }
7338aefa 1535 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1536}
1537
b72f3acb 1538static int
a4872ba6 1539bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1540 u32 invalidate_domains,
1541 u32 flush_domains)
d1b851fc 1542{
b72f3acb
CW		 1543 int ret;
1544
b72f3acb
CW		 1545 ret = intel_ring_begin(ring, 2);
1546 if (ret)
1547 return ret;
1548
1549 intel_ring_emit(ring, MI_FLUSH);
1550 intel_ring_emit(ring, MI_NOOP);
1551 intel_ring_advance(ring);
1552 return 0;
d1b851fc
ZN		 1553}
1554
3cce469c 1555static int
a4872ba6 1556i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1557{
3cce469c
CW		 1558 int ret;
1559
1560 ret = intel_ring_begin(ring, 4);
1561 if (ret)
1562 return ret;
6f392d54 1563
3cce469c
CW		 1564 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1565 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1566 intel_ring_emit(ring,
1567 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1568 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1569 __intel_ring_advance(ring);
d1b851fc 1570
3cce469c 1571 return 0;
d1b851fc
ZN		 1572}
1573
0f46832f 1574static bool
a4872ba6 1575gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1576{
1577 struct drm_device *dev = ring->dev;
4640c4ff 1578 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1579 unsigned long flags;
0f46832f 1580
7cd512f1
DV		 1581 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1582 return false;
0f46832f 1583
7338aefa 1584 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1585 if (ring->irq_refcount++ == 0) {
040d2baa 1586 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1587 I915_WRITE_IMR(ring,
1588 ~(ring->irq_enable_mask |
35a85ac6 1589 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1590 else
1591 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1592 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1593 }
7338aefa 1594 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1595
1596 return true;
1597}
1598
1599static void
a4872ba6 1600gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1601{
1602 struct drm_device *dev = ring->dev;
4640c4ff 1603 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1604 unsigned long flags;
0f46832f 1605
7338aefa 1606 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1607 if (--ring->irq_refcount == 0) {
040d2baa 1608 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1609 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1610 else
1611 I915_WRITE_IMR(ring, ~0);
480c8033 1612 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1613 }
7338aefa 1614 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1615}
1616
a19d2933 1617static bool
a4872ba6 1618hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1619{
1620 struct drm_device *dev = ring->dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 unsigned long flags;
1623
7cd512f1 1624 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1625 return false;
1626
59cdb63d 1627 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1628 if (ring->irq_refcount++ == 0) {
a19d2933 1629 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1630 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1631 }
59cdb63d 1632 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1633
1634 return true;
1635}
1636
1637static void
a4872ba6 1638hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1639{
1640 struct drm_device *dev = ring->dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 unsigned long flags;
1643
59cdb63d 1644 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1645 if (--ring->irq_refcount == 0) {
a19d2933 1646 I915_WRITE_IMR(ring, ~0);
480c8033 1647 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1648 }
59cdb63d 1649 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1650}
1651
abd58f01 1652static bool
a4872ba6 1653gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1654{
1655 struct drm_device *dev = ring->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 unsigned long flags;
1658
7cd512f1 1659 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1660 return false;
1661
1662 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1663 if (ring->irq_refcount++ == 0) {
1664 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1665 I915_WRITE_IMR(ring,
1666 ~(ring->irq_enable_mask |
1667 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1668 } else {
1669 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1670 }
1671 POSTING_READ(RING_IMR(ring->mmio_base));
1672 }
1673 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1674
1675 return true;
1676}
1677
1678static void
a4872ba6 1679gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1680{
1681 struct drm_device *dev = ring->dev;
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 unsigned long flags;
1684
1685 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1686 if (--ring->irq_refcount == 0) {
1687 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1688 I915_WRITE_IMR(ring,
1689 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1690 } else {
1691 I915_WRITE_IMR(ring, ~0);
1692 }
1693 POSTING_READ(RING_IMR(ring->mmio_base));
1694 }
1695 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1696}
1697
d1b851fc 1698static int
a4872ba6 1699i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1700 u64 offset, u32 length,
d7d4eedd 1701 unsigned flags)
d1b851fc 1702{
e1f99ce6 1703 int ret;
78501eac 1704
e1f99ce6
CW		 1705 ret = intel_ring_begin(ring, 2);
1706 if (ret)
1707 return ret;
1708
78501eac 1709 intel_ring_emit(ring,
65f56876
CW		 1710 MI_BATCH_BUFFER_START |
1711 MI_BATCH_GTT |
d7d4eedd 1712 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1713 intel_ring_emit(ring, offset);
78501eac
CW		 1714 intel_ring_advance(ring);
1715
d1b851fc
ZN		 1716 return 0;
1717}
1718
b45305fc
DV		 1719/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1720#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1721#define I830_TLB_ENTRIES (2)
1722#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1723static int
a4872ba6 1724i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1725 u64 offset, u32 len,
d7d4eedd 1726 unsigned flags)
62fdfeaf 1727{
c4d69da1 1728 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1729 int ret;
62fdfeaf 1730
c4d69da1
CW		 1731 ret = intel_ring_begin(ring, 6);
1732 if (ret)
1733 return ret;
62fdfeaf 1734
c4d69da1
CW		 1735 /* Evict the invalid PTE TLBs */
1736 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1737 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1738 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1739 intel_ring_emit(ring, cs_offset);
1740 intel_ring_emit(ring, 0xdeadbeef);
1741 intel_ring_emit(ring, MI_NOOP);
1742 intel_ring_advance(ring);
b45305fc 1743
c4d69da1 1744 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1745 if (len > I830_BATCH_LIMIT)
1746 return -ENOSPC;
1747
c4d69da1 1748 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1749 if (ret)
1750 return ret;
c4d69da1
CW		 1751
1752 /* Blit the batch (which has now all relocs applied) to the
1753 * stable batch scratch bo area (so that the CS never
1754 * stumbles over its tlb invalidation bug) ...
1755 */
1756 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1757 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1758 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1759 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1760 intel_ring_emit(ring, 4096);
1761 intel_ring_emit(ring, offset);
c4d69da1 1762
b45305fc 1763 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1764 intel_ring_emit(ring, MI_NOOP);
1765 intel_ring_advance(ring);
b45305fc
DV		 1766
1767 /* ... and execute it. */
c4d69da1 1768 offset = cs_offset;
b45305fc 1769 }
e1f99ce6 1770
c4d69da1
CW		 1771 ret = intel_ring_begin(ring, 4);
1772 if (ret)
1773 return ret;
1774
1775 intel_ring_emit(ring, MI_BATCH_BUFFER);
1776 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1777 intel_ring_emit(ring, offset + len - 8);
1778 intel_ring_emit(ring, MI_NOOP);
1779 intel_ring_advance(ring);
1780
fb3256da
DV		 1781 return 0;
1782}
1783
1784static int
a4872ba6 1785i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1786 u64 offset, u32 len,
d7d4eedd 1787 unsigned flags)
fb3256da
DV		 1788{
1789 int ret;
1790
1791 ret = intel_ring_begin(ring, 2);
1792 if (ret)
1793 return ret;
1794
65f56876 1795 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1796 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1797 intel_ring_advance(ring);
62fdfeaf 1798
62fdfeaf
EA		 1799 return 0;
1800}
1801
a4872ba6 1802static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1803{
05394f39 1804 struct drm_i915_gem_object *obj;
62fdfeaf 1805
8187a2b7
ZN		 1806 obj = ring->status_page.obj;
1807 if (obj == NULL)
62fdfeaf 1808 return;
62fdfeaf 1809
9da3da66 1810 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1811 i915_gem_object_ggtt_unpin(obj);
05394f39 1812 drm_gem_object_unreference(&obj->base);
8187a2b7 1813 ring->status_page.obj = NULL;
62fdfeaf
EA		 1814}
1815
a4872ba6 1816static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1817{
05394f39 1818 struct drm_i915_gem_object *obj;
62fdfeaf 1819
e3efda49 1820 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1821 unsigned flags;
e3efda49 1822 int ret;
e4ffd173 1823
e3efda49
CW		 1824 obj = i915_gem_alloc_object(ring->dev, 4096);
1825 if (obj == NULL) {
1826 DRM_ERROR("Failed to allocate status page\n");
1827 return -ENOMEM;
1828 }
62fdfeaf 1829
e3efda49
CW		 1830 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1831 if (ret)
1832 goto err_unref;
1833
1f767e02
CW		 1834 flags = 0;
1835 if (!HAS_LLC(ring->dev))
1836 /* On g33, we cannot place HWS above 256MiB, so
1837 * restrict its pinning to the low mappable arena.
1838 * Though this restriction is not documented for
1839 * gen4, gen5, or byt, they also behave similarly
1840 * and hang if the HWS is placed at the top of the
1841 * GTT. To generalise, it appears that all !llc
1842 * platforms have issues with us placing the HWS
1843 * above the mappable region (even though we never
1844 * actualy map it).
1845 */
1846 flags |= PIN_MAPPABLE;
1847 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1848 if (ret) {
1849err_unref:
1850 drm_gem_object_unreference(&obj->base);
1851 return ret;
1852 }
1853
1854 ring->status_page.obj = obj;
1855 }
62fdfeaf 1856
f343c5f6 1857 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1858 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1859 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1860
8187a2b7
ZN		 1861 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1862 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1863
1864 return 0;
62fdfeaf
EA		 1865}
1866
a4872ba6 1867static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1868{
1869 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1870
1871 if (!dev_priv->status_page_dmah) {
1872 dev_priv->status_page_dmah =
1873 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1874 if (!dev_priv->status_page_dmah)
1875 return -ENOMEM;
1876 }
1877
6b8294a4
CW		 1878 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1879 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1880
1881 return 0;
1882}
1883
7ba717cf 1884void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1885{
2919d291 1886 iounmap(ringbuf->virtual_start);
7ba717cf 1887 ringbuf->virtual_start = NULL;
2919d291 1888 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1889}
1890
1891int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1892 struct intel_ringbuffer *ringbuf)
1893{
1894 struct drm_i915_private *dev_priv = to_i915(dev);
1895 struct drm_i915_gem_object *obj = ringbuf->obj;
1896 int ret;
1897
1898 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1899 if (ret)
1900 return ret;
1901
1902 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1903 if (ret) {
1904 i915_gem_object_ggtt_unpin(obj);
1905 return ret;
1906 }
1907
1908 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1909 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1910 if (ringbuf->virtual_start == NULL) {
1911 i915_gem_object_ggtt_unpin(obj);
1912 return -EINVAL;
1913 }
1914
1915 return 0;
1916}
1917
1918void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1919{
2919d291
OM		 1920 drm_gem_object_unreference(&ringbuf->obj->base);
1921 ringbuf->obj = NULL;
1922}
1923
84c2377f
OM		 1924int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1925 struct intel_ringbuffer *ringbuf)
62fdfeaf 1926{
05394f39 1927 struct drm_i915_gem_object *obj;
62fdfeaf 1928
ebc052e0
CW		 1929 obj = NULL;
1930 if (!HAS_LLC(dev))
93b0a4e0 1931 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1932 if (obj == NULL)
93b0a4e0 1933 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1934 if (obj == NULL)
1935 return -ENOMEM;
8187a2b7 1936
24f3a8cf
AG		 1937 /* mark ring buffers as read-only from GPU side by default */
1938 obj->gt_ro = 1;
1939
93b0a4e0 1940 ringbuf->obj = obj;
e3efda49 1941
7ba717cf 1942 return 0;
e3efda49
CW		 1943}
1944
1945static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1946 struct intel_engine_cs *ring)
e3efda49 1947{
bfc882b4 1948 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1949 int ret;
1950
bfc882b4
DV		 1951 WARN_ON(ring->buffer);
1952
1953 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1954 if (!ringbuf)
1955 return -ENOMEM;
1956 ring->buffer = ringbuf;
8ee14975 1957
e3efda49
CW		 1958 ring->dev = dev;
1959 INIT_LIST_HEAD(&ring->active_list);
1960 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1961 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1962 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1963 ringbuf->ring = ring;
ebc348b2 1964 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1965
1966 init_waitqueue_head(&ring->irq_queue);
1967
1968 if (I915_NEED_GFX_HWS(dev)) {
1969 ret = init_status_page(ring);
1970 if (ret)
8ee14975 1971 goto error;
e3efda49
CW		 1972 } else {
1973 BUG_ON(ring->id != RCS);
1974 ret = init_phys_status_page(ring);
1975 if (ret)
8ee14975 1976 goto error;
e3efda49
CW		 1977 }
1978
bfc882b4 1979 WARN_ON(ringbuf->obj);
7ba717cf 1980
bfc882b4
DV		 1981 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1982 if (ret) {
1983 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1984 ring->name, ret);
1985 goto error;
1986 }
1987
1988 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1989 if (ret) {
1990 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1991 ring->name, ret);
1992 intel_destroy_ringbuffer_obj(ringbuf);
1993 goto error;
e3efda49 1994 }
62fdfeaf 1995
55249baa
CW		 1996 /* Workaround an erratum on the i830 which causes a hang if
1997 * the TAIL pointer points to within the last 2 cachelines
1998 * of the buffer.
1999 */
93b0a4e0 2000 ringbuf->effective_size = ringbuf->size;
e3efda49 2001 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2002 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2003
44e895a8
BV		 2004 ret = i915_cmd_parser_init_ring(ring);
2005 if (ret)
8ee14975
OM		 2006 goto error;
2007
8ee14975 2008 return 0;
351e3db2 2009
8ee14975
OM		 2010error:
2011 kfree(ringbuf);
2012 ring->buffer = NULL;
2013 return ret;
62fdfeaf
EA		 2014}
2015
a4872ba6 2016void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2017{
6402c330
JH		 2018 struct drm_i915_private *dev_priv;
2019 struct intel_ringbuffer *ringbuf;
33626e6a 2020
93b0a4e0 2021 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2022 return;
2023
6402c330
JH		 2024 dev_priv = to_i915(ring->dev);
2025 ringbuf = ring->buffer;
2026
e3efda49 2027 intel_stop_ring_buffer(ring);
de8f0a50 2028 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2029
7ba717cf 2030 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2031 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2032 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2033
8d19215b
ZN		 2034 if (ring->cleanup)
2035 ring->cleanup(ring);
2036
78501eac 2037 cleanup_status_page(ring);
44e895a8
BV		 2038
2039 i915_cmd_parser_fini_ring(ring);
8ee14975 2040
93b0a4e0 2041 kfree(ringbuf);
8ee14975 2042 ring->buffer = NULL;
62fdfeaf
EA		 2043}
2044
a4872ba6 2045static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 2046{
93b0a4e0 2047 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2048 struct drm_i915_gem_request *request;
a71d8d94
CW		 2049 int ret;
2050
ebd0fd4b
DG		 2051 if (intel_ring_space(ringbuf) >= n)
2052 return 0;
a71d8d94
CW		 2053
2054 list_for_each_entry(request, &ring->request_list, list) {
72f95afa 2055 if (__intel_ring_space(request->postfix, ringbuf->tail,
82e104cc 2056 ringbuf->size) >= n) {
a71d8d94
CW		 2057 break;
2058 }
a71d8d94
CW		 2059 }
2060
a4b3a571 2061 if (&request->list == &ring->request_list)
a71d8d94
CW		 2062 return -ENOSPC;
2063
a4b3a571 2064 ret = i915_wait_request(request);
a71d8d94
CW		 2065 if (ret)
2066 return ret;
2067
1cf0ba14 2068 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 2069
2070 return 0;
2071}
2072
a4872ba6 2073static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 2074{
78501eac 2075 struct drm_device *dev = ring->dev;
cae5852d 2076 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 2077 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 2078 unsigned long end;
a71d8d94 2079 int ret;
c7dca47b 2080
a71d8d94
CW		 2081 ret = intel_ring_wait_request(ring, n);
2082 if (ret != -ENOSPC)
2083 return ret;
2084
09246732
CW		 2085 /* force the tail write in case we have been skipping them */
2086 __intel_ring_advance(ring);
2087
63ed2cb2
DV		 2088 /* With GEM the hangcheck timer should kick us out of the loop,
2089 * leaving it early runs the risk of corrupting GEM state (due
2090 * to running on almost untested codepaths). But on resume
2091 * timers don't work yet, so prevent a complete hang in that
2092 * case by choosing an insanely large timeout. */
2093 end = jiffies + 60 * HZ;
e6bfaf85 2094
ebd0fd4b 2095 ret = 0;
dcfe0506 2096 trace_i915_ring_wait_begin(ring);
8187a2b7 2097 do {
ebd0fd4b
DG		 2098 if (intel_ring_space(ringbuf) >= n)
2099 break;
93b0a4e0 2100 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 2101 if (intel_ring_space(ringbuf) >= n)
dcfe0506 2102 break;
62fdfeaf 2103
e60a0b10 2104 msleep(1);
d6b2c790 2105
dcfe0506
CW		 2106 if (dev_priv->mm.interruptible && signal_pending(current)) {
2107 ret = -ERESTARTSYS;
2108 break;
2109 }
2110
33196ded
DV		 2111 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2112 dev_priv->mm.interruptible);
d6b2c790 2113 if (ret)
dcfe0506
CW		 2114 break;
2115
2116 if (time_after(jiffies, end)) {
2117 ret = -EBUSY;
2118 break;
2119 }
2120 } while (1);
db53a302 2121 trace_i915_ring_wait_end(ring);
dcfe0506 2122 return ret;
8187a2b7 2123}
62fdfeaf 2124
a4872ba6 2125static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2126{
2127 uint32_t __iomem *virt;
93b0a4e0
OM		 2128 struct intel_ringbuffer *ringbuf = ring->buffer;
2129 int rem = ringbuf->size - ringbuf->tail;
3e960501 2130
93b0a4e0 2131 if (ringbuf->space < rem) {
3e960501
CW		 2132 int ret = ring_wait_for_space(ring, rem);
2133 if (ret)
2134 return ret;
2135 }
2136
93b0a4e0 2137 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2138 rem /= 4;
2139 while (rem--)
2140 iowrite32(MI_NOOP, virt++);
2141
93b0a4e0 2142 ringbuf->tail = 0;
ebd0fd4b 2143 intel_ring_update_space(ringbuf);
3e960501
CW		 2144
2145 return 0;
2146}
2147
a4872ba6 2148int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2149{
a4b3a571 2150 struct drm_i915_gem_request *req;
3e960501
CW		 2151 int ret;
2152
2153 /* We need to add any requests required to flush the objects and ring */
6259cead 2154 if (ring->outstanding_lazy_request) {
9400ae5c 2155 ret = i915_add_request(ring);
3e960501
CW		 2156 if (ret)
2157 return ret;
2158 }
2159
2160 /* Wait upon the last request to be completed */
2161 if (list_empty(&ring->request_list))
2162 return 0;
2163
a4b3a571 2164 req = list_entry(ring->request_list.prev,
3e960501 2165 struct drm_i915_gem_request,
a4b3a571 2166 list);
3e960501 2167
a4b3a571 2168 return i915_wait_request(req);
3e960501
CW		 2169}
2170
9d773091 2171static int
6259cead 2172intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2173{
9eba5d4a
JH		 2174 int ret;
2175 struct drm_i915_gem_request *request;
67e2937b 2176 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2177
6259cead 2178 if (ring->outstanding_lazy_request)
9d773091 2179 return 0;
3c0e234c 2180
aaeb1ba0 2181 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2182 if (request == NULL)
2183 return -ENOMEM;
3c0e234c 2184
abfe262a 2185 kref_init(&request->ref);
ff79e857 2186 request->ring = ring;
67e2937b 2187 request->uniq = dev_private->request_uniq++;
abfe262a 2188
6259cead 2189 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2190 if (ret) {
2191 kfree(request);
2192 return ret;
3c0e234c
CW		 2193 }
2194
6259cead 2195 ring->outstanding_lazy_request = request;
9eba5d4a 2196 return 0;
9d773091
CW		 2197}
2198
a4872ba6 2199static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2200 int bytes)
cbcc80df 2201{
93b0a4e0 2202 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2203 int ret;
2204
93b0a4e0 2205 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2206 ret = intel_wrap_ring_buffer(ring);
2207 if (unlikely(ret))
2208 return ret;
2209 }
2210
93b0a4e0 2211 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2212 ret = ring_wait_for_space(ring, bytes);
2213 if (unlikely(ret))
2214 return ret;
2215 }
2216
cbcc80df
MK		 2217 return 0;
2218}
2219
a4872ba6 2220int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2221 int num_dwords)
8187a2b7 2222{
4640c4ff 2223 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2224 int ret;
78501eac 2225
33196ded
DV		 2226 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2227 dev_priv->mm.interruptible);
de2b9985
DV		 2228 if (ret)
2229 return ret;
21dd3734 2230
304d695c
CW		 2231 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2232 if (ret)
2233 return ret;
2234
9d773091 2235 /* Preallocate the olr before touching the ring */
6259cead 2236 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2237 if (ret)
2238 return ret;
2239
ee1b1e5e 2240 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2241 return 0;
8187a2b7 2242}
78501eac 2243
753b1ad4 2244/* Align the ring tail to a cacheline boundary */
a4872ba6 2245int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2246{
ee1b1e5e 2247 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2248 int ret;
2249
2250 if (num_dwords == 0)
2251 return 0;
2252
18393f63 2253 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2254 ret = intel_ring_begin(ring, num_dwords);
2255 if (ret)
2256 return ret;
2257
2258 while (num_dwords--)
2259 intel_ring_emit(ring, MI_NOOP);
2260
2261 intel_ring_advance(ring);
2262
2263 return 0;
2264}
2265
a4872ba6 2266void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2267{
3b2cc8ab
OM		 2268 struct drm_device *dev = ring->dev;
2269 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2270
6259cead 2271 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2272
3b2cc8ab 2273 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2274 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2275 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2276 if (HAS_VEBOX(dev))
5020150b 2277 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2278 }
d97ed339 2279
f7e98ad4 2280 ring->set_seqno(ring, seqno);
92cab734 2281 ring->hangcheck.seqno = seqno;
8187a2b7 2282}
62fdfeaf 2283
a4872ba6 2284static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2285 u32 value)
881f47b6 2286{
4640c4ff 2287 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2288
2289 /* Every tail move must follow the sequence below */
12f55818
CW		 2290
2291 /* Disable notification that the ring is IDLE. The GT
2292 * will then assume that it is busy and bring it out of rc6.
2293 */
0206e353 2294 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2295 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2296
2297 /* Clear the context id. Here be magic! */
2298 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2299
12f55818 2300 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2301 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2302 GEN6_BSD_SLEEP_INDICATOR) == 0,
2303 50))
2304 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2305
12f55818 2306 /* Now that the ring is fully powered up, update the tail */
0206e353 2307 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2308 POSTING_READ(RING_TAIL(ring->mmio_base));
2309
2310 /* Let the ring send IDLE messages to the GT again,
2311 * and so let it sleep to conserve power when idle.
2312 */
0206e353 2313 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2314 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2315}
2316
a4872ba6 2317static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2318 u32 invalidate, u32 flush)
881f47b6 2319{
71a77e07 2320 uint32_t cmd;
b72f3acb
CW		 2321 int ret;
2322
b72f3acb
CW		 2323 ret = intel_ring_begin(ring, 4);
2324 if (ret)
2325 return ret;
2326
71a77e07 2327 cmd = MI_FLUSH_DW;
075b3bba
BW		 2328 if (INTEL_INFO(ring->dev)->gen >= 8)
2329 cmd += 1;
9a289771
JB		 2330 /*
2331 * Bspec vol 1c.5 - video engine command streamer:
2332 * "If ENABLED, all TLBs will be invalidated once the flush
2333 * operation is complete. This bit is only valid when the
2334 * Post-Sync Operation field is a value of 1h or 3h."
2335 */
71a77e07 2336 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2337 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2338 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2339 intel_ring_emit(ring, cmd);
9a289771 2340 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2341 if (INTEL_INFO(ring->dev)->gen >= 8) {
2342 intel_ring_emit(ring, 0); /* upper addr */
2343 intel_ring_emit(ring, 0); /* value */
2344 } else {
2345 intel_ring_emit(ring, 0);
2346 intel_ring_emit(ring, MI_NOOP);
2347 }
b72f3acb
CW		 2348 intel_ring_advance(ring);
2349 return 0;
881f47b6
XH		 2350}
2351
1c7a0623 2352static int
a4872ba6 2353gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2354 u64 offset, u32 len,
1c7a0623
BW		 2355 unsigned flags)
2356{
896ab1a5 2357 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2358 int ret;
2359
2360 ret = intel_ring_begin(ring, 4);
2361 if (ret)
2362 return ret;
2363
2364 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2365 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2366 intel_ring_emit(ring, lower_32_bits(offset));
2367 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2368 intel_ring_emit(ring, MI_NOOP);
2369 intel_ring_advance(ring);
2370
2371 return 0;
2372}
2373
d7d4eedd 2374static int
a4872ba6 2375hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2376 u64 offset, u32 len,
d7d4eedd
CW		 2377 unsigned flags)
2378{
2379 int ret;
2380
2381 ret = intel_ring_begin(ring, 2);
2382 if (ret)
2383 return ret;
2384
2385 intel_ring_emit(ring,
77072258
CW		 2386 MI_BATCH_BUFFER_START |
2387 (flags & I915_DISPATCH_SECURE ?
2388 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2389 /* bit0-7 is the length on GEN6+ */
2390 intel_ring_emit(ring, offset);
2391 intel_ring_advance(ring);
2392
2393 return 0;
2394}
2395
881f47b6 2396static int
a4872ba6 2397gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2398 u64 offset, u32 len,
d7d4eedd 2399 unsigned flags)
881f47b6 2400{
0206e353 2401 int ret;
ab6f8e32 2402
0206e353
AJ		 2403 ret = intel_ring_begin(ring, 2);
2404 if (ret)
2405 return ret;
e1f99ce6 2406
d7d4eedd
CW		 2407 intel_ring_emit(ring,
2408 MI_BATCH_BUFFER_START |
2409 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2410 /* bit0-7 is the length on GEN6+ */
2411 intel_ring_emit(ring, offset);
2412 intel_ring_advance(ring);
ab6f8e32 2413
0206e353 2414 return 0;
881f47b6
XH		 2415}
2416
549f7365
CW		 2417/* Blitter support (SandyBridge+) */
2418
a4872ba6 2419static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2420 u32 invalidate, u32 flush)
8d19215b 2421{
fd3da6c9 2422 struct drm_device *dev = ring->dev;
1d73c2a8 2423 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2424 uint32_t cmd;
b72f3acb
CW		 2425 int ret;
2426
6a233c78 2427 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2428 if (ret)
2429 return ret;
2430
71a77e07 2431 cmd = MI_FLUSH_DW;
075b3bba
BW		 2432 if (INTEL_INFO(ring->dev)->gen >= 8)
2433 cmd += 1;
9a289771
JB		 2434 /*
2435 * Bspec vol 1c.3 - blitter engine command streamer:
2436 * "If ENABLED, all TLBs will be invalidated once the flush
2437 * operation is complete. This bit is only valid when the
2438 * Post-Sync Operation field is a value of 1h or 3h."
2439 */
71a77e07 2440 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2441 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2442 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2443 intel_ring_emit(ring, cmd);
9a289771 2444 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2445 if (INTEL_INFO(ring->dev)->gen >= 8) {
2446 intel_ring_emit(ring, 0); /* upper addr */
2447 intel_ring_emit(ring, 0); /* value */
2448 } else {
2449 intel_ring_emit(ring, 0);
2450 intel_ring_emit(ring, MI_NOOP);
2451 }
b72f3acb 2452 intel_ring_advance(ring);
fd3da6c9 2453
1d73c2a8
RV		 2454 if (!invalidate && flush) {
2455 if (IS_GEN7(dev))
2456 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2457 else if (IS_BROADWELL(dev))
2458 dev_priv->fbc.need_sw_cache_clean = true;
2459 }
fd3da6c9 2460
b72f3acb 2461 return 0;
8d19215b
ZN		 2462}
2463
5c1143bb
XH		 2464int intel_init_render_ring_buffer(struct drm_device *dev)
2465{
4640c4ff 2466 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2467 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2468 struct drm_i915_gem_object *obj;
2469 int ret;
5c1143bb 2470
59465b5f
DV		 2471 ring->name = "render ring";
2472 ring->id = RCS;
2473 ring->mmio_base = RENDER_RING_BASE;
2474
707d9cf9 2475 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2476 if (i915_semaphore_is_enabled(dev)) {
2477 obj = i915_gem_alloc_object(dev, 4096);
2478 if (obj == NULL) {
2479 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2480 i915.semaphores = 0;
2481 } else {
2482 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2483 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2484 if (ret != 0) {
2485 drm_gem_object_unreference(&obj->base);
2486 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2487 i915.semaphores = 0;
2488 } else
2489 dev_priv->semaphore_obj = obj;
2490 }
2491 }
7225342a 2492
8f0e2b9d 2493 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2494 ring->add_request = gen6_add_request;
2495 ring->flush = gen8_render_ring_flush;
2496 ring->irq_get = gen8_ring_get_irq;
2497 ring->irq_put = gen8_ring_put_irq;
2498 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2499 ring->get_seqno = gen6_ring_get_seqno;
2500 ring->set_seqno = ring_set_seqno;
2501 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2502 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2503 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2504 ring->semaphore.signal = gen8_rcs_signal;
2505 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2506 }
2507 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2508 ring->add_request = gen6_add_request;
4772eaeb 2509 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2510 if (INTEL_INFO(dev)->gen == 6)
b3111509 2511 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2512 ring->irq_get = gen6_ring_get_irq;
2513 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2514 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2515 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2516 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2517 if (i915_semaphore_is_enabled(dev)) {
2518 ring->semaphore.sync_to = gen6_ring_sync;
2519 ring->semaphore.signal = gen6_signal;
2520 /*
2521 * The current semaphore is only applied on pre-gen8
2522 * platform. And there is no VCS2 ring on the pre-gen8
2523 * platform. So the semaphore between RCS and VCS2 is
2524 * initialized as INVALID. Gen8 will initialize the
2525 * sema between VCS2 and RCS later.
2526 */
2527 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2528 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2529 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2530 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2531 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2532 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2533 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2534 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2535 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2536 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2537 }
c6df541c
CW		 2538 } else if (IS_GEN5(dev)) {
2539 ring->add_request = pc_render_add_request;
46f0f8d1 2540 ring->flush = gen4_render_ring_flush;
c6df541c 2541 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2542 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2543 ring->irq_get = gen5_ring_get_irq;
2544 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2545 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2546 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2547 } else {
8620a3a9 2548 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2549 if (INTEL_INFO(dev)->gen < 4)
2550 ring->flush = gen2_render_ring_flush;
2551 else
2552 ring->flush = gen4_render_ring_flush;
59465b5f 2553 ring->get_seqno = ring_get_seqno;
b70ec5bf 2554 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2555 if (IS_GEN2(dev)) {
2556 ring->irq_get = i8xx_ring_get_irq;
2557 ring->irq_put = i8xx_ring_put_irq;
2558 } else {
2559 ring->irq_get = i9xx_ring_get_irq;
2560 ring->irq_put = i9xx_ring_put_irq;
2561 }
e3670319 2562 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2563 }
59465b5f 2564 ring->write_tail = ring_write_tail;
707d9cf9 2565
d7d4eedd
CW		 2566 if (IS_HASWELL(dev))
2567 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2568 else if (IS_GEN8(dev))
2569 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2570 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2571 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2572 else if (INTEL_INFO(dev)->gen >= 4)
2573 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2574 else if (IS_I830(dev) || IS_845G(dev))
2575 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2576 else
2577 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2578 ring->init_hw = init_render_ring;
59465b5f
DV		 2579 ring->cleanup = render_ring_cleanup;
2580
b45305fc
DV		 2581 /* Workaround batchbuffer to combat CS tlb bug. */
2582 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2583 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2584 if (obj == NULL) {
2585 DRM_ERROR("Failed to allocate batch bo\n");
2586 return -ENOMEM;
2587 }
2588
be1fa129 2589 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2590 if (ret != 0) {
2591 drm_gem_object_unreference(&obj->base);
2592 DRM_ERROR("Failed to ping batch bo\n");
2593 return ret;
2594 }
2595
0d1aacac
CW		 2596 ring->scratch.obj = obj;
2597 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2598 }
2599
99be1dfe
DV		 2600 ret = intel_init_ring_buffer(dev, ring);
2601 if (ret)
2602 return ret;
2603
2604 if (INTEL_INFO(dev)->gen >= 5) {
2605 ret = intel_init_pipe_control(ring);
2606 if (ret)
2607 return ret;
2608 }
2609
2610 return 0;
5c1143bb
XH		 2611}
2612
2613int intel_init_bsd_ring_buffer(struct drm_device *dev)
2614{
4640c4ff 2615 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2616 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2617
58fa3835
DV		 2618 ring->name = "bsd ring";
2619 ring->id = VCS;
2620
0fd2c201 2621 ring->write_tail = ring_write_tail;
780f18c8 2622 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2623 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2624 /* gen6 bsd needs a special wa for tail updates */
2625 if (IS_GEN6(dev))
2626 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2627 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2628 ring->add_request = gen6_add_request;
2629 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2630 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2631 if (INTEL_INFO(dev)->gen >= 8) {
2632 ring->irq_enable_mask =
2633 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2634 ring->irq_get = gen8_ring_get_irq;
2635 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2636 ring->dispatch_execbuffer =
2637 gen8_ring_dispatch_execbuffer;
707d9cf9 2638 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2639 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2640 ring->semaphore.signal = gen8_xcs_signal;
2641 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2642 }
abd58f01
BW		 2643 } else {
2644 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2645 ring->irq_get = gen6_ring_get_irq;
2646 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2647 ring->dispatch_execbuffer =
2648 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2649 if (i915_semaphore_is_enabled(dev)) {
2650 ring->semaphore.sync_to = gen6_ring_sync;
2651 ring->semaphore.signal = gen6_signal;
2652 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2653 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2654 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2655 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2656 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2657 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2658 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2659 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2660 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2661 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2662 }
abd58f01 2663 }
58fa3835
DV		 2664 } else {
2665 ring->mmio_base = BSD_RING_BASE;
58fa3835 2666 ring->flush = bsd_ring_flush;
8620a3a9 2667 ring->add_request = i9xx_add_request;
58fa3835 2668 ring->get_seqno = ring_get_seqno;
b70ec5bf 2669 ring->set_seqno = ring_set_seqno;
e48d8634 2670 if (IS_GEN5(dev)) {
cc609d5d 2671 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2672 ring->irq_get = gen5_ring_get_irq;
2673 ring->irq_put = gen5_ring_put_irq;
2674 } else {
e3670319 2675 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2676 ring->irq_get = i9xx_ring_get_irq;
2677 ring->irq_put = i9xx_ring_put_irq;
2678 }
fb3256da 2679 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2680 }
ecfe00d8 2681 ring->init_hw = init_ring_common;
58fa3835 2682
1ec14ad3 2683 return intel_init_ring_buffer(dev, ring);
5c1143bb 2684}
549f7365 2685
845f74a7 2686/**
62659920 2687 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2688 */
2689int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2690{
2691 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2692 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2693
f7b64236 2694 ring->name = "bsd2 ring";
845f74a7
ZY		 2695 ring->id = VCS2;
2696
2697 ring->write_tail = ring_write_tail;
2698 ring->mmio_base = GEN8_BSD2_RING_BASE;
2699 ring->flush = gen6_bsd_ring_flush;
2700 ring->add_request = gen6_add_request;
2701 ring->get_seqno = gen6_ring_get_seqno;
2702 ring->set_seqno = ring_set_seqno;
2703 ring->irq_enable_mask =
2704 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2705 ring->irq_get = gen8_ring_get_irq;
2706 ring->irq_put = gen8_ring_put_irq;
2707 ring->dispatch_execbuffer =
2708 gen8_ring_dispatch_execbuffer;
3e78998a 2709 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2710 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2711 ring->semaphore.signal = gen8_xcs_signal;
2712 GEN8_RING_SEMAPHORE_INIT;
2713 }
ecfe00d8 2714 ring->init_hw = init_ring_common;
845f74a7
ZY		 2715
2716 return intel_init_ring_buffer(dev, ring);
2717}
2718
549f7365
CW		 2719int intel_init_blt_ring_buffer(struct drm_device *dev)
2720{
4640c4ff 2721 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2722 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2723
3535d9dd
DV		 2724 ring->name = "blitter ring";
2725 ring->id = BCS;
2726
2727 ring->mmio_base = BLT_RING_BASE;
2728 ring->write_tail = ring_write_tail;
ea251324 2729 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2730 ring->add_request = gen6_add_request;
2731 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2732 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2733 if (INTEL_INFO(dev)->gen >= 8) {
2734 ring->irq_enable_mask =
2735 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2736 ring->irq_get = gen8_ring_get_irq;
2737 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2738 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2739 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2740 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2741 ring->semaphore.signal = gen8_xcs_signal;
2742 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2743 }
abd58f01
BW		 2744 } else {
2745 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2746 ring->irq_get = gen6_ring_get_irq;
2747 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2748 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2749 if (i915_semaphore_is_enabled(dev)) {
2750 ring->semaphore.signal = gen6_signal;
2751 ring->semaphore.sync_to = gen6_ring_sync;
2752 /*
2753 * The current semaphore is only applied on pre-gen8
2754 * platform. And there is no VCS2 ring on the pre-gen8
2755 * platform. So the semaphore between BCS and VCS2 is
2756 * initialized as INVALID. Gen8 will initialize the
2757 * sema between BCS and VCS2 later.
2758 */
2759 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2760 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2761 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2762 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2763 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2764 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2765 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2766 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2767 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2768 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2769 }
abd58f01 2770 }
ecfe00d8 2771 ring->init_hw = init_ring_common;
549f7365 2772
1ec14ad3 2773 return intel_init_ring_buffer(dev, ring);
549f7365 2774}
a7b9761d 2775
9a8a2213
BW		 2776int intel_init_vebox_ring_buffer(struct drm_device *dev)
2777{
4640c4ff 2778 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2779 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2780
2781 ring->name = "video enhancement ring";
2782 ring->id = VECS;
2783
2784 ring->mmio_base = VEBOX_RING_BASE;
2785 ring->write_tail = ring_write_tail;
2786 ring->flush = gen6_ring_flush;
2787 ring->add_request = gen6_add_request;
2788 ring->get_seqno = gen6_ring_get_seqno;
2789 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2790
2791 if (INTEL_INFO(dev)->gen >= 8) {
2792 ring->irq_enable_mask =
40c499f9 2793 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2794 ring->irq_get = gen8_ring_get_irq;
2795 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2796 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2797 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2798 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2799 ring->semaphore.signal = gen8_xcs_signal;
2800 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2801 }
abd58f01
BW		 2802 } else {
2803 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2804 ring->irq_get = hsw_vebox_get_irq;
2805 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2806 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2807 if (i915_semaphore_is_enabled(dev)) {
2808 ring->semaphore.sync_to = gen6_ring_sync;
2809 ring->semaphore.signal = gen6_signal;
2810 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2811 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2812 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2813 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2814 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2815 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2816 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2817 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2818 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2819 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2820 }
abd58f01 2821 }
ecfe00d8 2822 ring->init_hw = init_ring_common;
9a8a2213
BW		 2823
2824 return intel_init_ring_buffer(dev, ring);
2825}
2826
a7b9761d 2827int
a4872ba6 2828intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2829{
2830 int ret;
2831
2832 if (!ring->gpu_caches_dirty)
2833 return 0;
2834
2835 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2836 if (ret)
2837 return ret;
2838
2839 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2840
2841 ring->gpu_caches_dirty = false;
2842 return 0;
2843}
2844
2845int
a4872ba6 2846intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2847{
2848 uint32_t flush_domains;
2849 int ret;
2850
2851 flush_domains = 0;
2852 if (ring->gpu_caches_dirty)
2853 flush_domains = I915_GEM_GPU_DOMAINS;
2854
2855 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2856 if (ret)
2857 return ret;
2858
2859 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2860
2861 ring->gpu_caches_dirty = false;
2862 return 0;
2863}
e3efda49
CW		 2864
2865void
a4872ba6 2866intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2867{
2868 int ret;
2869
2870 if (!intel_ring_initialized(ring))
2871 return;
2872
2873 ret = intel_ring_idle(ring);
2874 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2875 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2876 ring->name, ret);
2877
2878 stop_ring(ring);
2879}
Linux kernel - Deliverables
This page took 0.723962 seconds and 5 git commands to generate.