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drm/i915: Add *_ring_begin() to request allocation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
6258fbe2 84static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a84c3ae1 94gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
a84c3ae1 98 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
31b14c9f 103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
5fb9de1a 109 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118}
119
120static int
a84c3ae1 121gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 122 u32 invalidate_domains,
123 u32 flush_domains)
62fdfeaf 124{
a84c3ae1 125 struct intel_engine_cs *ring = req->ring;
78501eac 126 struct drm_device *dev = ring->dev;
6f392d54 127 u32 cmd;
b72f3acb 128 int ret;
6f392d54 129
36d527de
CW		 130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 160 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
62fdfeaf 163
36d527de
CW		 164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
70eac33e 167
5fb9de1a 168 ret = intel_ring_begin(req, 2);
36d527de
CW		 169 if (ret)
170 return ret;
b72f3acb 171
36d527de
CW		 172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
b72f3acb
CW		 175
176 return 0;
8187a2b7
ZN		 177}
178
8d315287
JB		 179/**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216static int
f2cf1fcc 217intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 218{
f2cf1fcc 219 struct intel_engine_cs *ring = req->ring;
18393f63 220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 221 int ret;
222
5fb9de1a 223 ret = intel_ring_begin(req, 6);
8d315287
JB		 224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
5fb9de1a 236 ret = intel_ring_begin(req, 6);
8d315287
JB		 237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
251static int
a84c3ae1
JH		 252gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
8d315287 254{
a84c3ae1 255 struct intel_engine_cs *ring = req->ring;
8d315287 256 u32 flags = 0;
18393f63 257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 258 int ret;
259
b3111509 260 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 261 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 262 if (ret)
263 return ret;
264
8d315287
JB		 265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
7d54a904
CW		 269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
97f209bc 276 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
3ac78313 288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 289 }
8d315287 290
5fb9de1a 291 ret = intel_ring_begin(req, 4);
8d315287
JB		 292 if (ret)
293 return ret;
294
6c6cf5aa 295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 298 intel_ring_emit(ring, 0);
8d315287
JB		 299 intel_ring_advance(ring);
300
301 return 0;
302}
303
f3987631 304static int
f2cf1fcc 305gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 306{
f2cf1fcc 307 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 308 int ret;
309
5fb9de1a 310 ret = intel_ring_begin(req, 4);
f3987631
PZ		 311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322}
323
4772eaeb 324static int
a84c3ae1 325gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 326 u32 invalidate_domains, u32 flush_domains)
327{
a84c3ae1 328 struct intel_engine_cs *ring = req->ring;
4772eaeb 329 u32 flags = 0;
18393f63 330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 331 int ret;
332
f3987631
PZ		 333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
4772eaeb
PZ		 343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 364
add284a3
CW		 365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
f3987631
PZ		 367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
f2cf1fcc 370 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 371 }
372
5fb9de1a 373 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
b9e1faa7 379 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384}
385
884ceace 386static int
f2cf1fcc 387gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 388 u32 flags, u32 scratch_addr)
389{
f2cf1fcc 390 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 391 int ret;
392
5fb9de1a 393 ret = intel_ring_begin(req, 6);
884ceace
KG		 394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406}
407
a5f3d68e 408static int
a84c3ae1 409gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 410 u32 invalidate_domains, u32 flush_domains)
411{
412 u32 flags = 0;
f2cf1fcc 413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 414 int ret;
a5f3d68e
BW		 415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 433 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
a5f3d68e
BW		 439 }
440
f2cf1fcc 441 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 442}
443
a4872ba6 444static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 445 u32 value)
d46eefa2 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 448 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 449}
450
a4872ba6 451u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 452{
4640c4ff 453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 454 u64 acthd;
8187a2b7 455
50877445
CW		 456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
8187a2b7
ZN		 465}
466
a4872ba6 467static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 468{
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476}
477
af75f269
DL		 478static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479{
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538}
539
a4872ba6 540static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 541{
9991ae78 542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 543
9991ae78
CW		 544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
9991ae78
CW		 554 }
555 }
b7884eb4 556
7f2ab699 557 I915_WRITE_CTL(ring, 0);
570ef608 558 I915_WRITE_HEAD(ring, 0);
78501eac 559 ring->write_tail(ring, 0);
8187a2b7 560
9991ae78
CW		 561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
a51435a3 565
9991ae78
CW		 566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567}
8187a2b7 568
a4872ba6 569static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 570{
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 575 int ret = 0;
576
59bad947 577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
8187a2b7 588
9991ae78 589 if (!stop_ring(ring)) {
6fd0d56e
CW		 590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
9991ae78
CW		 597 ret = -EIO;
598 goto out;
6fd0d56e 599 }
8187a2b7
ZN		 600 }
601
9991ae78
CW		 602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
ece4a17d
JK		 607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
0d8957c8
DV		 610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
f343c5f6 614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
7f2ab699 623 I915_WRITE_CTL(ring,
93b0a4e0 624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 625 | RING_VALID);
8187a2b7 626
8187a2b7 627 /* If the head is still not zero, the ring is dead */
f01db988 628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 631 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 637 ret = -EIO;
638 goto out;
8187a2b7
ZN		 639 }
640
ebd0fd4b 641 ringbuf->last_retired_head = -1;
5c6c6003
CW		 642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 644 intel_ring_update_space(ringbuf);
1ec14ad3 645
50f018df
CW		 646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
b7884eb4 648out:
59bad947 649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 650
651 return ret;
8187a2b7
ZN		 652}
653
9b1136d5
OM		 654void
655intel_fini_pipe_control(struct intel_engine_cs *ring)
656{
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669}
670
671int
672intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 673{
c6df541c
CW		 674 int ret;
675
bfc882b4 676 WARN_ON(ring->scratch.obj);
c6df541c 677
0d1aacac
CW		 678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
c6df541c
CW		 680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
e4ffd173 684
a9cc726c
DV		 685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
c6df541c 688
1ec9e26d 689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 690 if (ret)
691 goto err_unref;
692
0d1aacac
CW		 693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
56b085a0 696 ret = -ENOMEM;
c6df541c 697 goto err_unpin;
56b085a0 698 }
c6df541c 699
2b1086cc 700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 701 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 702 return 0;
703
704err_unpin:
d7f46fc4 705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 706err_unref:
0d1aacac 707 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 708err:
c6df541c
CW		 709 return ret;
710}
711
e2be4faf 712static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 713{
7225342a 714 int ret, i;
e2be4faf 715 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 718 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 719
e6c1abb7 720 if (WARN_ON_ONCE(w->count == 0))
7225342a 721 return 0;
888b5995 722
7225342a 723 ring->gpu_caches_dirty = true;
4866d729 724 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 725 if (ret)
726 return ret;
888b5995 727
5fb9de1a 728 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 729 if (ret)
730 return ret;
731
22a916aa 732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 733 for (i = 0; i < w->count; i++) {
7225342a
MK		 734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
22a916aa 737 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
4866d729 742 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 743 if (ret)
744 return ret;
888b5995 745
7225342a 746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 747
7225342a 748 return 0;
86d7f238
AS		 749}
750
8753181e 751static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 752{
753 int ret;
754
e2be4faf 755 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 756 if (ret != 0)
757 return ret;
758
be01363f 759 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764}
765
7225342a 766static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 767 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 768{
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
86d7f238
AS		 781}
782
cf4b0de6
DL		 783#define WA_REG(addr, mask, val) { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 785 if (r) \
786 return r; \
787 }
788
789#define WA_SET_BIT_MASKED(addr, mask) \
26459343 790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 791
792#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 794
98533251 795#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 797
cf4b0de6
DL		 798#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 800
cf4b0de6 801#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 802
00e1e623 803static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 804{
888b5995
AS		 805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 807
9cc83020
VS		 808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
809
2441f877
VS		 810 /* WaDisableAsyncFlipPerfMode:bdw */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
86d7f238 813 /* WaDisablePartialInstShootdown:bdw */
101b376d 814 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
817 STALL_DOP_GATING_DISABLE);
86d7f238 818
101b376d 819 /* WaDisableDopClockGating:bdw */
7225342a
MK		 820 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
821 DOP_CLOCK_GATING_DISABLE);
86d7f238 822
7225342a
MK		 823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
824 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 825
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
829 */
7225342a 830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 831 /* WaForceEnableNonCoherent:bdw */
7225342a 832 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
835 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 836 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 837 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 838 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 839
2701fc43
KG		 840 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
841 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
842 * polygons in the same 8x4 pixel/sample area to be processed without
843 * stalling waiting for the earlier ones to write to Hierarchical Z
844 * buffer."
845 *
846 * This optimization is off by default for Broadwell; turn it on.
847 */
848 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
849
86d7f238 850 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 851 WA_SET_BIT_MASKED(CACHE_MODE_1,
852 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 853
854 /*
855 * BSpec recommends 8x4 when MSAA is used,
856 * however in practice 16x4 seems fastest.
857 *
858 * Note that PS/WM thread counts depend on the WIZ hashing
859 * disable bit, which we don't touch here, but it's good
860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
861 */
98533251
DL		 862 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
863 GEN6_WIZ_HASHING_MASK,
864 GEN6_WIZ_HASHING_16x4);
888b5995 865
86d7f238
AS		 866 return 0;
867}
868
00e1e623
VS		 869static int chv_init_workarounds(struct intel_engine_cs *ring)
870{
00e1e623
VS		 871 struct drm_device *dev = ring->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873
9cc83020
VS		 874 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
875
2441f877
VS		 876 /* WaDisableAsyncFlipPerfMode:chv */
877 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
878
00e1e623 879 /* WaDisablePartialInstShootdown:chv */
00e1e623 880 /* WaDisableThreadStallDopClockGating:chv */
7225342a 881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 882 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
883 STALL_DOP_GATING_DISABLE);
00e1e623 884
95289009
AS		 885 /* Use Force Non-Coherent whenever executing a 3D context. This is a
886 * workaround for a possible hang in the unlikely event a TLB
887 * invalidation occurs during a PSD flush.
888 */
889 /* WaForceEnableNonCoherent:chv */
890 /* WaHdcDisableFetchWhenMasked:chv */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0,
892 HDC_FORCE_NON_COHERENT |
893 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
894
973a5b06
KG		 895 /* According to the CACHE_MODE_0 default value documentation, some
896 * CHV platforms disable this optimization by default. Turn it on.
897 */
898 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
899
14bc16e3
VS		 900 /* Wa4x4STCOptimizationDisable:chv */
901 WA_SET_BIT_MASKED(CACHE_MODE_1,
902 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
903
d60de81d
KG		 904 /* Improve HiZ throughput on CHV. */
905 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
906
e7fc2436
VS		 907 /*
908 * BSpec recommends 8x4 when MSAA is used,
909 * however in practice 16x4 seems fastest.
910 *
911 * Note that PS/WM thread counts depend on the WIZ hashing
912 * disable bit, which we don't touch here, but it's good
913 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
914 */
915 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
916 GEN6_WIZ_HASHING_MASK,
917 GEN6_WIZ_HASHING_16x4);
918
7225342a
MK		 919 return 0;
920}
921
3b106531
HN		 922static int gen9_init_workarounds(struct intel_engine_cs *ring)
923{
ab0dfafe
HN		 924 struct drm_device *dev = ring->dev;
925 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 926 uint32_t tmp;
ab0dfafe 927
b0e6f6d4 928 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
931
a119a6e6 932 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
935
d2a31dbd
NH		 936 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
937 INTEL_REVID(dev) == SKL_REVID_B0)) ||
938 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 940 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
941 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 942 }
943
a13d215f
NH		 944 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
945 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
946 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
948 GEN9_RHWO_OPTIMIZATION_DISABLE);
949 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
950 DISABLE_PIXEL_MASK_CAMMING);
951 }
952
27a1b688
NH		 953 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
954 IS_BROXTON(dev)) {
955 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 956 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
957 GEN9_ENABLE_YV12_BUGFIX);
958 }
959
5068368c 960 /* Wa4x4STCOptimizationDisable:skl,bxt */
1840481f
HN		 961 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
962
27160c96 963 /* WaDisablePartialResolveInVc:skl,bxt */
9370cd98
DL		 964 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
965
16be17af 966 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 967 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
968 GEN9_CCS_TLB_PREFETCH_ENABLE);
969
5a2ae95e
ID		 970 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
971 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
972 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 973 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
974 PIXEL_MASK_CAMMING_DISABLE);
975
8ea6f892
ID		 976 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
977 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
978 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
979 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
980 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
981 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
982
3b106531
HN		 983 return 0;
984}
985
b7668791
DL		 986static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
987{
988 struct drm_device *dev = ring->dev;
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 u8 vals[3] = { 0, 0, 0 };
991 unsigned int i;
992
993 for (i = 0; i < 3; i++) {
994 u8 ss;
995
996 /*
997 * Only consider slices where one, and only one, subslice has 7
998 * EUs
999 */
1000 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1001 continue;
1002
1003 /*
1004 * subslice_7eu[i] != 0 (because of the check above) and
1005 * ss_max == 4 (maximum number of subslices possible per slice)
1006 *
1007 * -> 0 <= ss <= 3;
1008 */
1009 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1010 vals[i] = 3 - ss;
1011 }
1012
1013 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1014 return 0;
1015
1016 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1017 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1018 GEN9_IZ_HASHING_MASK(2) |
1019 GEN9_IZ_HASHING_MASK(1) |
1020 GEN9_IZ_HASHING_MASK(0),
1021 GEN9_IZ_HASHING(2, vals[2]) |
1022 GEN9_IZ_HASHING(1, vals[1]) |
1023 GEN9_IZ_HASHING(0, vals[0]));
1024
1025 return 0;
1026}
1027
1028
8d205494
DL		 1029static int skl_init_workarounds(struct intel_engine_cs *ring)
1030{
d0bbbc4f
DL		 1031 struct drm_device *dev = ring->dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033
8d205494
DL		 1034 gen9_init_workarounds(ring);
1035
d0bbbc4f
DL		 1036 /* WaDisablePowerCompilerClockGating:skl */
1037 if (INTEL_REVID(dev) == SKL_REVID_B0)
1038 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1039 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1040
b62adbd1
NH		 1041 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1042 /*
1043 *Use Force Non-Coherent whenever executing a 3D context. This
1044 * is a workaround for a possible hang in the unlikely event
1045 * a TLB invalidation occurs during a PSD flush.
1046 */
1047 /* WaForceEnableNonCoherent:skl */
1048 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1049 HDC_FORCE_NON_COHERENT);
1050 }
1051
5b6fd12a
VS		 1052 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1053 INTEL_REVID(dev) == SKL_REVID_D0)
1054 /* WaBarrierPerformanceFixDisable:skl */
1055 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1056 HDC_FENCE_DEST_SLM_DISABLE |
1057 HDC_BARRIER_PERFORMANCE_DISABLE);
1058
b7668791 1059 return skl_tune_iz_hashing(ring);
7225342a
MK		 1060}
1061
cae0437f
NH		 1062static int bxt_init_workarounds(struct intel_engine_cs *ring)
1063{
dfb601e6
NH		 1064 struct drm_device *dev = ring->dev;
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1066
cae0437f
NH		 1067 gen9_init_workarounds(ring);
1068
dfb601e6
NH		 1069 /* WaDisableThreadStallDopClockGating:bxt */
1070 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1071 STALL_DOP_GATING_DISABLE);
1072
983b4b9d
NH		 1073 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1074 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1075 WA_SET_BIT_MASKED(
1076 GEN7_HALF_SLICE_CHICKEN1,
1077 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1078 }
1079
cae0437f
NH		 1080 return 0;
1081}
1082
771b9a53 1083int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1084{
1085 struct drm_device *dev = ring->dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088 WARN_ON(ring->id != RCS);
1089
1090 dev_priv->workarounds.count = 0;
1091
1092 if (IS_BROADWELL(dev))
1093 return bdw_init_workarounds(ring);
1094
1095 if (IS_CHERRYVIEW(dev))
1096 return chv_init_workarounds(ring);
00e1e623 1097
8d205494
DL		 1098 if (IS_SKYLAKE(dev))
1099 return skl_init_workarounds(ring);
cae0437f
NH		 1100
1101 if (IS_BROXTON(dev))
1102 return bxt_init_workarounds(ring);
3b106531 1103
00e1e623
VS		 1104 return 0;
1105}
1106
a4872ba6 1107static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1108{
78501eac 1109 struct drm_device *dev = ring->dev;
1ec14ad3 1110 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1111 int ret = init_ring_common(ring);
9c33baa6
KZ		 1112 if (ret)
1113 return ret;
a69ffdbf 1114
61a563a2
AG		 1115 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1116 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1117 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1118
1119 /* We need to disable the AsyncFlip performance optimisations in order
1120 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1121 * programmed to '1' on all products.
8693a824 1122 *
2441f877 1123 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1124 */
2441f877 1125 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1126 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1127
f05bb0c7 1128 /* Required for the hardware to program scanline values for waiting */
01fa0302 1129 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1130 if (INTEL_INFO(dev)->gen == 6)
1131 I915_WRITE(GFX_MODE,
aa83e30d 1132 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1133
01fa0302 1134 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1135 if (IS_GEN7(dev))
1136 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1137 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1138 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1139
5e13a0c5 1140 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1141 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1142 * "If this bit is set, STCunit will have LRA as replacement
1143 * policy. [...] This bit must be reset. LRA replacement
1144 * policy is not supported."
1145 */
1146 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1147 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1148 }
1149
9cc83020 1150 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1151 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1152
040d2baa 1153 if (HAS_L3_DPF(dev))
35a85ac6 1154 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1155
7225342a 1156 return init_workarounds_ring(ring);
8187a2b7
ZN		 1157}
1158
a4872ba6 1159static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1160{
b45305fc 1161 struct drm_device *dev = ring->dev;
3e78998a
BW		 1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163
1164 if (dev_priv->semaphore_obj) {
1165 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1166 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1167 dev_priv->semaphore_obj = NULL;
1168 }
b45305fc 1169
9b1136d5 1170 intel_fini_pipe_control(ring);
c6df541c
CW		 1171}
1172
f7169687 1173static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1174 unsigned int num_dwords)
1175{
1176#define MBOX_UPDATE_DWORDS 8
f7169687 1177 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1178 struct drm_device *dev = signaller->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct intel_engine_cs *waiter;
1181 int i, ret, num_rings;
1182
1183 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1184 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1185#undef MBOX_UPDATE_DWORDS
1186
5fb9de1a 1187 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1188 if (ret)
1189 return ret;
1190
1191 for_each_ring(waiter, dev_priv, i) {
6259cead 1192 u32 seqno;
3e78998a
BW		 1193 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1194 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1195 continue;
1196
f7169687 1197 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1198 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1199 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1200 PIPE_CONTROL_QW_WRITE |
1201 PIPE_CONTROL_FLUSH_ENABLE);
1202 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1203 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1204 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1205 intel_ring_emit(signaller, 0);
1206 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1207 MI_SEMAPHORE_TARGET(waiter->id));
1208 intel_ring_emit(signaller, 0);
1209 }
1210
1211 return 0;
1212}
1213
f7169687 1214static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1215 unsigned int num_dwords)
1216{
1217#define MBOX_UPDATE_DWORDS 6
f7169687 1218 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1219 struct drm_device *dev = signaller->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 struct intel_engine_cs *waiter;
1222 int i, ret, num_rings;
1223
1224 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1225 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1226#undef MBOX_UPDATE_DWORDS
1227
5fb9de1a 1228 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1229 if (ret)
1230 return ret;
1231
1232 for_each_ring(waiter, dev_priv, i) {
6259cead 1233 u32 seqno;
3e78998a
BW		 1234 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1235 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1236 continue;
1237
f7169687 1238 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1239 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1240 MI_FLUSH_DW_OP_STOREDW);
1241 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1242 MI_FLUSH_DW_USE_GTT);
1243 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1244 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1245 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1246 MI_SEMAPHORE_TARGET(waiter->id));
1247 intel_ring_emit(signaller, 0);
1248 }
1249
1250 return 0;
1251}
1252
f7169687 1253static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1254 unsigned int num_dwords)
1ec14ad3 1255{
f7169687 1256 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1257 struct drm_device *dev = signaller->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1259 struct intel_engine_cs *useless;
a1444b79 1260 int i, ret, num_rings;
78325f2d 1261
a1444b79
BW		 1262#define MBOX_UPDATE_DWORDS 3
1263 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1264 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1265#undef MBOX_UPDATE_DWORDS
024a43e1 1266
5fb9de1a 1267 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1268 if (ret)
1269 return ret;
024a43e1 1270
78325f2d
BW		 1271 for_each_ring(useless, dev_priv, i) {
1272 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1273 if (mbox_reg != GEN6_NOSYNC) {
f7169687 1274 u32 seqno = i915_gem_request_get_seqno(signaller_req);
78325f2d
BW		 1275 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1276 intel_ring_emit(signaller, mbox_reg);
6259cead 1277 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1278 }
1279 }
024a43e1 1280
a1444b79
BW		 1281 /* If num_dwords was rounded, make sure the tail pointer is correct */
1282 if (num_rings % 2 == 0)
1283 intel_ring_emit(signaller, MI_NOOP);
1284
024a43e1 1285 return 0;
1ec14ad3
CW		 1286}
1287
c8c99b0f
BW		 1288/**
1289 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1290 *
1291 * @request - request to write to the ring
c8c99b0f
BW		 1292 *
1293 * Update the mailbox registers in the *other* rings with the current seqno.
1294 * This acts like a signal in the canonical semaphore.
1295 */
1ec14ad3 1296static int
ee044a88 1297gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1298{
ee044a88 1299 struct intel_engine_cs *ring = req->ring;
024a43e1 1300 int ret;
52ed2325 1301
707d9cf9 1302 if (ring->semaphore.signal)
f7169687 1303 ret = ring->semaphore.signal(req, 4);
707d9cf9 1304 else
5fb9de1a 1305 ret = intel_ring_begin(req, 4);
707d9cf9 1306
1ec14ad3
CW		 1307 if (ret)
1308 return ret;
1309
1ec14ad3
CW		 1310 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1311 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1312 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1313 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1314 __intel_ring_advance(ring);
1ec14ad3 1315
1ec14ad3
CW		 1316 return 0;
1317}
1318
f72b3435
MK		 1319static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1320 u32 seqno)
1321{
1322 struct drm_i915_private *dev_priv = dev->dev_private;
1323 return dev_priv->last_seqno < seqno;
1324}
1325
c8c99b0f
BW		 1326/**
1327 * intel_ring_sync - sync the waiter to the signaller on seqno
1328 *
1329 * @waiter - ring that is waiting
1330 * @signaller - ring which has, or will signal
1331 * @seqno - seqno which the waiter will block on
1332 */
5ee426ca
BW		 1333
1334static int
599d924c 1335gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1336 struct intel_engine_cs *signaller,
1337 u32 seqno)
1338{
599d924c 1339 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1340 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1341 int ret;
1342
5fb9de1a 1343 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1344 if (ret)
1345 return ret;
1346
1347 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1348 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1349 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1350 MI_SEMAPHORE_SAD_GTE_SDD);
1351 intel_ring_emit(waiter, seqno);
1352 intel_ring_emit(waiter,
1353 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1354 intel_ring_emit(waiter,
1355 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1356 intel_ring_advance(waiter);
1357 return 0;
1358}
1359
c8c99b0f 1360static int
599d924c 1361gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1362 struct intel_engine_cs *signaller,
686cb5f9 1363 u32 seqno)
1ec14ad3 1364{
599d924c 1365 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1366 u32 dw1 = MI_SEMAPHORE_MBOX |
1367 MI_SEMAPHORE_COMPARE |
1368 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1369 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1370 int ret;
1ec14ad3 1371
1500f7ea
BW		 1372 /* Throughout all of the GEM code, seqno passed implies our current
1373 * seqno is >= the last seqno executed. However for hardware the
1374 * comparison is strictly greater than.
1375 */
1376 seqno -= 1;
1377
ebc348b2 1378 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1379
5fb9de1a 1380 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1381 if (ret)
1382 return ret;
1383
f72b3435
MK		 1384 /* If seqno wrap happened, omit the wait with no-ops */
1385 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1386 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1387 intel_ring_emit(waiter, seqno);
1388 intel_ring_emit(waiter, 0);
1389 intel_ring_emit(waiter, MI_NOOP);
1390 } else {
1391 intel_ring_emit(waiter, MI_NOOP);
1392 intel_ring_emit(waiter, MI_NOOP);
1393 intel_ring_emit(waiter, MI_NOOP);
1394 intel_ring_emit(waiter, MI_NOOP);
1395 }
c8c99b0f 1396 intel_ring_advance(waiter);
1ec14ad3
CW		 1397
1398 return 0;
1399}
1400
c6df541c
CW		 1401#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1402do { \
fcbc34e4
KG		 1403 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1404 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1405 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1406 intel_ring_emit(ring__, 0); \
1407 intel_ring_emit(ring__, 0); \
1408} while (0)
1409
1410static int
ee044a88 1411pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1412{
ee044a88 1413 struct intel_engine_cs *ring = req->ring;
18393f63 1414 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1415 int ret;
1416
1417 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1418 * incoherent with writes to memory, i.e. completely fubar,
1419 * so we need to use PIPE_NOTIFY instead.
1420 *
1421 * However, we also need to workaround the qword write
1422 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1423 * memory before requesting an interrupt.
1424 */
5fb9de1a 1425 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1426 if (ret)
1427 return ret;
1428
fcbc34e4 1429 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1430 PIPE_CONTROL_WRITE_FLUSH |
1431 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1432 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1433 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1434 intel_ring_emit(ring, 0);
1435 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1436 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1437 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1438 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1439 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1440 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1441 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1442 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1443 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1444 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1445 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1446
fcbc34e4 1447 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1448 PIPE_CONTROL_WRITE_FLUSH |
1449 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1450 PIPE_CONTROL_NOTIFY);
0d1aacac 1451 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1452 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1453 intel_ring_emit(ring, 0);
09246732 1454 __intel_ring_advance(ring);
c6df541c 1455
c6df541c
CW		 1456 return 0;
1457}
1458
4cd53c0c 1459static u32
a4872ba6 1460gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1461{
4cd53c0c
DV		 1462 /* Workaround to force correct ordering between irq and seqno writes on
1463 * ivb (and maybe also on snb) by reading from a CS register (like
1464 * ACTHD) before reading the status page. */
50877445
CW		 1465 if (!lazy_coherency) {
1466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1467 POSTING_READ(RING_ACTHD(ring->mmio_base));
1468 }
1469
4cd53c0c
DV		 1470 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1471}
1472
8187a2b7 1473static u32
a4872ba6 1474ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1475{
1ec14ad3
CW		 1476 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1477}
1478
b70ec5bf 1479static void
a4872ba6 1480ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1481{
1482 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1483}
1484
c6df541c 1485static u32
a4872ba6 1486pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1487{
0d1aacac 1488 return ring->scratch.cpu_page[0];
c6df541c
CW		 1489}
1490
b70ec5bf 1491static void
a4872ba6 1492pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1493{
0d1aacac 1494 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1495}
1496
e48d8634 1497static bool
a4872ba6 1498gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1499{
1500 struct drm_device *dev = ring->dev;
4640c4ff 1501 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1502 unsigned long flags;
e48d8634 1503
7cd512f1 1504 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1505 return false;
1506
7338aefa 1507 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1508 if (ring->irq_refcount++ == 0)
480c8033 1509 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1510 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1511
1512 return true;
1513}
1514
1515static void
a4872ba6 1516gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1517{
1518 struct drm_device *dev = ring->dev;
4640c4ff 1519 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1520 unsigned long flags;
e48d8634 1521
7338aefa 1522 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1523 if (--ring->irq_refcount == 0)
480c8033 1524 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1525 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1526}
1527
b13c2b96 1528static bool
a4872ba6 1529i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1530{
78501eac 1531 struct drm_device *dev = ring->dev;
4640c4ff 1532 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1533 unsigned long flags;
62fdfeaf 1534
7cd512f1 1535 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1536 return false;
1537
7338aefa 1538 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1539 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1540 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1541 I915_WRITE(IMR, dev_priv->irq_mask);
1542 POSTING_READ(IMR);
1543 }
7338aefa 1544 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1545
1546 return true;
62fdfeaf
EA		 1547}
1548
8187a2b7 1549static void
a4872ba6 1550i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1551{
78501eac 1552 struct drm_device *dev = ring->dev;
4640c4ff 1553 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1554 unsigned long flags;
62fdfeaf 1555
7338aefa 1556 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1557 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1558 dev_priv->irq_mask |= ring->irq_enable_mask;
1559 I915_WRITE(IMR, dev_priv->irq_mask);
1560 POSTING_READ(IMR);
1561 }
7338aefa 1562 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1563}
1564
c2798b19 1565static bool
a4872ba6 1566i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1567{
1568 struct drm_device *dev = ring->dev;
4640c4ff 1569 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1570 unsigned long flags;
c2798b19 1571
7cd512f1 1572 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1573 return false;
1574
7338aefa 1575 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1576 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1577 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1578 I915_WRITE16(IMR, dev_priv->irq_mask);
1579 POSTING_READ16(IMR);
1580 }
7338aefa 1581 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1582
1583 return true;
1584}
1585
1586static void
a4872ba6 1587i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1588{
1589 struct drm_device *dev = ring->dev;
4640c4ff 1590 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1591 unsigned long flags;
c2798b19 1592
7338aefa 1593 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1594 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1595 dev_priv->irq_mask |= ring->irq_enable_mask;
1596 I915_WRITE16(IMR, dev_priv->irq_mask);
1597 POSTING_READ16(IMR);
1598 }
7338aefa 1599 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1600}
1601
b72f3acb 1602static int
a84c3ae1 1603bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1604 u32 invalidate_domains,
1605 u32 flush_domains)
d1b851fc 1606{
a84c3ae1 1607 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1608 int ret;
1609
5fb9de1a 1610 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1611 if (ret)
1612 return ret;
1613
1614 intel_ring_emit(ring, MI_FLUSH);
1615 intel_ring_emit(ring, MI_NOOP);
1616 intel_ring_advance(ring);
1617 return 0;
d1b851fc
ZN		 1618}
1619
3cce469c 1620static int
ee044a88 1621i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1622{
ee044a88 1623 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1624 int ret;
1625
5fb9de1a 1626 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1627 if (ret)
1628 return ret;
6f392d54 1629
3cce469c
CW		 1630 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1631 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1632 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1633 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1634 __intel_ring_advance(ring);
d1b851fc 1635
3cce469c 1636 return 0;
d1b851fc
ZN		 1637}
1638
0f46832f 1639static bool
a4872ba6 1640gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1641{
1642 struct drm_device *dev = ring->dev;
4640c4ff 1643 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1644 unsigned long flags;
0f46832f 1645
7cd512f1
DV		 1646 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1647 return false;
0f46832f 1648
7338aefa 1649 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1650 if (ring->irq_refcount++ == 0) {
040d2baa 1651 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1652 I915_WRITE_IMR(ring,
1653 ~(ring->irq_enable_mask |
35a85ac6 1654 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1655 else
1656 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1657 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1658 }
7338aefa 1659 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1660
1661 return true;
1662}
1663
1664static void
a4872ba6 1665gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1666{
1667 struct drm_device *dev = ring->dev;
4640c4ff 1668 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1669 unsigned long flags;
0f46832f 1670
7338aefa 1671 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1672 if (--ring->irq_refcount == 0) {
040d2baa 1673 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1674 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1675 else
1676 I915_WRITE_IMR(ring, ~0);
480c8033 1677 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1678 }
7338aefa 1679 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1680}
1681
a19d2933 1682static bool
a4872ba6 1683hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1684{
1685 struct drm_device *dev = ring->dev;
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 unsigned long flags;
1688
7cd512f1 1689 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1690 return false;
1691
59cdb63d 1692 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1693 if (ring->irq_refcount++ == 0) {
a19d2933 1694 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1695 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1696 }
59cdb63d 1697 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1698
1699 return true;
1700}
1701
1702static void
a4872ba6 1703hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1704{
1705 struct drm_device *dev = ring->dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 unsigned long flags;
1708
59cdb63d 1709 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1710 if (--ring->irq_refcount == 0) {
a19d2933 1711 I915_WRITE_IMR(ring, ~0);
480c8033 1712 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1713 }
59cdb63d 1714 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1715}
1716
abd58f01 1717static bool
a4872ba6 1718gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1719{
1720 struct drm_device *dev = ring->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 unsigned long flags;
1723
7cd512f1 1724 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1725 return false;
1726
1727 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1728 if (ring->irq_refcount++ == 0) {
1729 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1730 I915_WRITE_IMR(ring,
1731 ~(ring->irq_enable_mask |
1732 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1733 } else {
1734 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1735 }
1736 POSTING_READ(RING_IMR(ring->mmio_base));
1737 }
1738 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1739
1740 return true;
1741}
1742
1743static void
a4872ba6 1744gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1745{
1746 struct drm_device *dev = ring->dev;
1747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 unsigned long flags;
1749
1750 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1751 if (--ring->irq_refcount == 0) {
1752 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1753 I915_WRITE_IMR(ring,
1754 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1755 } else {
1756 I915_WRITE_IMR(ring, ~0);
1757 }
1758 POSTING_READ(RING_IMR(ring->mmio_base));
1759 }
1760 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1761}
1762
d1b851fc 1763static int
53fddaf7 1764i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1765 u64 offset, u32 length,
8e004efc 1766 unsigned dispatch_flags)
d1b851fc 1767{
53fddaf7 1768 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1769 int ret;
78501eac 1770
5fb9de1a 1771 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1772 if (ret)
1773 return ret;
1774
78501eac 1775 intel_ring_emit(ring,
65f56876
CW		 1776 MI_BATCH_BUFFER_START |
1777 MI_BATCH_GTT |
8e004efc
JH		 1778 (dispatch_flags & I915_DISPATCH_SECURE ?
1779 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1780 intel_ring_emit(ring, offset);
78501eac
CW		 1781 intel_ring_advance(ring);
1782
d1b851fc
ZN		 1783 return 0;
1784}
1785
b45305fc
DV		 1786/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1787#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1788#define I830_TLB_ENTRIES (2)
1789#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1790static int
53fddaf7 1791i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1792 u64 offset, u32 len,
1793 unsigned dispatch_flags)
62fdfeaf 1794{
53fddaf7 1795 struct intel_engine_cs *ring = req->ring;
c4d69da1 1796 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1797 int ret;
62fdfeaf 1798
5fb9de1a 1799 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1800 if (ret)
1801 return ret;
62fdfeaf 1802
c4d69da1
CW		 1803 /* Evict the invalid PTE TLBs */
1804 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1805 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1806 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1807 intel_ring_emit(ring, cs_offset);
1808 intel_ring_emit(ring, 0xdeadbeef);
1809 intel_ring_emit(ring, MI_NOOP);
1810 intel_ring_advance(ring);
b45305fc 1811
8e004efc 1812 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1813 if (len > I830_BATCH_LIMIT)
1814 return -ENOSPC;
1815
5fb9de1a 1816 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1817 if (ret)
1818 return ret;
c4d69da1
CW		 1819
1820 /* Blit the batch (which has now all relocs applied) to the
1821 * stable batch scratch bo area (so that the CS never
1822 * stumbles over its tlb invalidation bug) ...
1823 */
1824 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1825 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1826 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1827 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1828 intel_ring_emit(ring, 4096);
1829 intel_ring_emit(ring, offset);
c4d69da1 1830
b45305fc 1831 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1832 intel_ring_emit(ring, MI_NOOP);
1833 intel_ring_advance(ring);
b45305fc
DV		 1834
1835 /* ... and execute it. */
c4d69da1 1836 offset = cs_offset;
b45305fc 1837 }
e1f99ce6 1838
5fb9de1a 1839 ret = intel_ring_begin(req, 4);
c4d69da1
CW		 1840 if (ret)
1841 return ret;
1842
1843 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1844 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1845 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1846 intel_ring_emit(ring, offset + len - 8);
1847 intel_ring_emit(ring, MI_NOOP);
1848 intel_ring_advance(ring);
1849
fb3256da
DV		 1850 return 0;
1851}
1852
1853static int
53fddaf7 1854i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1855 u64 offset, u32 len,
8e004efc 1856 unsigned dispatch_flags)
fb3256da 1857{
53fddaf7 1858 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1859 int ret;
1860
5fb9de1a 1861 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1862 if (ret)
1863 return ret;
1864
65f56876 1865 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1866 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1867 0 : MI_BATCH_NON_SECURE));
c4e7a414 1868 intel_ring_advance(ring);
62fdfeaf 1869
62fdfeaf
EA		 1870 return 0;
1871}
1872
a4872ba6 1873static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1874{
05394f39 1875 struct drm_i915_gem_object *obj;
62fdfeaf 1876
8187a2b7
ZN		 1877 obj = ring->status_page.obj;
1878 if (obj == NULL)
62fdfeaf 1879 return;
62fdfeaf 1880
9da3da66 1881 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1882 i915_gem_object_ggtt_unpin(obj);
05394f39 1883 drm_gem_object_unreference(&obj->base);
8187a2b7 1884 ring->status_page.obj = NULL;
62fdfeaf
EA		 1885}
1886
a4872ba6 1887static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1888{
05394f39 1889 struct drm_i915_gem_object *obj;
62fdfeaf 1890
e3efda49 1891 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1892 unsigned flags;
e3efda49 1893 int ret;
e4ffd173 1894
e3efda49
CW		 1895 obj = i915_gem_alloc_object(ring->dev, 4096);
1896 if (obj == NULL) {
1897 DRM_ERROR("Failed to allocate status page\n");
1898 return -ENOMEM;
1899 }
62fdfeaf 1900
e3efda49
CW		 1901 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1902 if (ret)
1903 goto err_unref;
1904
1f767e02
CW		 1905 flags = 0;
1906 if (!HAS_LLC(ring->dev))
1907 /* On g33, we cannot place HWS above 256MiB, so
1908 * restrict its pinning to the low mappable arena.
1909 * Though this restriction is not documented for
1910 * gen4, gen5, or byt, they also behave similarly
1911 * and hang if the HWS is placed at the top of the
1912 * GTT. To generalise, it appears that all !llc
1913 * platforms have issues with us placing the HWS
1914 * above the mappable region (even though we never
1915 * actualy map it).
1916 */
1917 flags |= PIN_MAPPABLE;
1918 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1919 if (ret) {
1920err_unref:
1921 drm_gem_object_unreference(&obj->base);
1922 return ret;
1923 }
1924
1925 ring->status_page.obj = obj;
1926 }
62fdfeaf 1927
f343c5f6 1928 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1929 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1930 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1931
8187a2b7
ZN		 1932 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1933 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1934
1935 return 0;
62fdfeaf
EA		 1936}
1937
a4872ba6 1938static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1939{
1940 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1941
1942 if (!dev_priv->status_page_dmah) {
1943 dev_priv->status_page_dmah =
1944 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1945 if (!dev_priv->status_page_dmah)
1946 return -ENOMEM;
1947 }
1948
6b8294a4
CW		 1949 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1950 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1951
1952 return 0;
1953}
1954
7ba717cf 1955void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1956{
2919d291 1957 iounmap(ringbuf->virtual_start);
7ba717cf 1958 ringbuf->virtual_start = NULL;
2919d291 1959 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1960}
1961
1962int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1963 struct intel_ringbuffer *ringbuf)
1964{
1965 struct drm_i915_private *dev_priv = to_i915(dev);
1966 struct drm_i915_gem_object *obj = ringbuf->obj;
1967 int ret;
1968
1969 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1970 if (ret)
1971 return ret;
1972
1973 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1974 if (ret) {
1975 i915_gem_object_ggtt_unpin(obj);
1976 return ret;
1977 }
1978
1979 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1980 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1981 if (ringbuf->virtual_start == NULL) {
1982 i915_gem_object_ggtt_unpin(obj);
1983 return -EINVAL;
1984 }
1985
1986 return 0;
1987}
1988
1989void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1990{
2919d291
OM		 1991 drm_gem_object_unreference(&ringbuf->obj->base);
1992 ringbuf->obj = NULL;
1993}
1994
84c2377f
OM		 1995int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1996 struct intel_ringbuffer *ringbuf)
62fdfeaf 1997{
05394f39 1998 struct drm_i915_gem_object *obj;
62fdfeaf 1999
ebc052e0
CW		 2000 obj = NULL;
2001 if (!HAS_LLC(dev))
93b0a4e0 2002 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2003 if (obj == NULL)
93b0a4e0 2004 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2005 if (obj == NULL)
2006 return -ENOMEM;
8187a2b7 2007
24f3a8cf
AG		 2008 /* mark ring buffers as read-only from GPU side by default */
2009 obj->gt_ro = 1;
2010
93b0a4e0 2011 ringbuf->obj = obj;
e3efda49 2012
7ba717cf 2013 return 0;
e3efda49
CW		 2014}
2015
2016static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2017 struct intel_engine_cs *ring)
e3efda49 2018{
bfc882b4 2019 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2020 int ret;
2021
bfc882b4
DV		 2022 WARN_ON(ring->buffer);
2023
2024 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2025 if (!ringbuf)
2026 return -ENOMEM;
2027 ring->buffer = ringbuf;
8ee14975 2028
e3efda49
CW		 2029 ring->dev = dev;
2030 INIT_LIST_HEAD(&ring->active_list);
2031 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2032 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2033 i915_gem_batch_pool_init(dev, &ring->batch_pool);
93b0a4e0 2034 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2035 ringbuf->ring = ring;
ebc348b2 2036 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2037
2038 init_waitqueue_head(&ring->irq_queue);
2039
2040 if (I915_NEED_GFX_HWS(dev)) {
2041 ret = init_status_page(ring);
2042 if (ret)
8ee14975 2043 goto error;
e3efda49
CW		 2044 } else {
2045 BUG_ON(ring->id != RCS);
2046 ret = init_phys_status_page(ring);
2047 if (ret)
8ee14975 2048 goto error;
e3efda49
CW		 2049 }
2050
bfc882b4 2051 WARN_ON(ringbuf->obj);
7ba717cf 2052
bfc882b4
DV		 2053 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2054 if (ret) {
2055 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2056 ring->name, ret);
2057 goto error;
2058 }
2059
2060 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2061 if (ret) {
2062 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2063 ring->name, ret);
2064 intel_destroy_ringbuffer_obj(ringbuf);
2065 goto error;
e3efda49 2066 }
62fdfeaf 2067
55249baa
CW		 2068 /* Workaround an erratum on the i830 which causes a hang if
2069 * the TAIL pointer points to within the last 2 cachelines
2070 * of the buffer.
2071 */
93b0a4e0 2072 ringbuf->effective_size = ringbuf->size;
e3efda49 2073 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2074 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2075
44e895a8
BV		 2076 ret = i915_cmd_parser_init_ring(ring);
2077 if (ret)
8ee14975
OM		 2078 goto error;
2079
8ee14975 2080 return 0;
351e3db2 2081
8ee14975
OM		 2082error:
2083 kfree(ringbuf);
2084 ring->buffer = NULL;
2085 return ret;
62fdfeaf
EA		 2086}
2087
a4872ba6 2088void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2089{
6402c330
JH		 2090 struct drm_i915_private *dev_priv;
2091 struct intel_ringbuffer *ringbuf;
33626e6a 2092
93b0a4e0 2093 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2094 return;
2095
6402c330
JH		 2096 dev_priv = to_i915(ring->dev);
2097 ringbuf = ring->buffer;
2098
e3efda49 2099 intel_stop_ring_buffer(ring);
de8f0a50 2100 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2101
7ba717cf 2102 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2103 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2104 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2105
8d19215b
ZN		 2106 if (ring->cleanup)
2107 ring->cleanup(ring);
2108
78501eac 2109 cleanup_status_page(ring);
44e895a8
BV		 2110
2111 i915_cmd_parser_fini_ring(ring);
06fbca71 2112 i915_gem_batch_pool_fini(&ring->batch_pool);
8ee14975 2113
93b0a4e0 2114 kfree(ringbuf);
8ee14975 2115 ring->buffer = NULL;
62fdfeaf
EA		 2116}
2117
595e1eeb 2118static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2119{
93b0a4e0 2120 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2121 struct drm_i915_gem_request *request;
b4716185
CW		 2122 unsigned space;
2123 int ret;
a71d8d94 2124
29b1b415
JH		 2125 /* The whole point of reserving space is to not wait! */
2126 WARN_ON(ringbuf->reserved_in_use);
2127
ebd0fd4b
DG		 2128 if (intel_ring_space(ringbuf) >= n)
2129 return 0;
a71d8d94
CW		 2130
2131 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2132 space = __intel_ring_space(request->postfix, ringbuf->tail,
2133 ringbuf->size);
2134 if (space >= n)
a71d8d94 2135 break;
a71d8d94
CW		 2136 }
2137
595e1eeb 2138 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2139 return -ENOSPC;
2140
a4b3a571 2141 ret = i915_wait_request(request);
a71d8d94
CW		 2142 if (ret)
2143 return ret;
2144
b4716185 2145 ringbuf->space = space;
a71d8d94
CW		 2146 return 0;
2147}
2148
a4872ba6 2149static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2150{
2151 uint32_t __iomem *virt;
93b0a4e0
OM		 2152 struct intel_ringbuffer *ringbuf = ring->buffer;
2153 int rem = ringbuf->size - ringbuf->tail;
3e960501 2154
29b1b415
JH		 2155 /* Can't wrap if space has already been reserved! */
2156 WARN_ON(ringbuf->reserved_in_use);
2157
93b0a4e0 2158 if (ringbuf->space < rem) {
3e960501
CW		 2159 int ret = ring_wait_for_space(ring, rem);
2160 if (ret)
2161 return ret;
2162 }
2163
93b0a4e0 2164 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2165 rem /= 4;
2166 while (rem--)
2167 iowrite32(MI_NOOP, virt++);
2168
93b0a4e0 2169 ringbuf->tail = 0;
ebd0fd4b 2170 intel_ring_update_space(ringbuf);
3e960501
CW		 2171
2172 return 0;
2173}
2174
a4872ba6 2175int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2176{
a4b3a571 2177 struct drm_i915_gem_request *req;
3e960501
CW		 2178
2179 /* We need to add any requests required to flush the objects and ring */
75289874 2180 WARN_ON(ring->outstanding_lazy_request);
bf7dc5b7 2181 if (ring->outstanding_lazy_request)
75289874 2182 i915_add_request(ring->outstanding_lazy_request);
3e960501
CW		 2183
2184 /* Wait upon the last request to be completed */
2185 if (list_empty(&ring->request_list))
2186 return 0;
2187
a4b3a571 2188 req = list_entry(ring->request_list.prev,
b4716185
CW		 2189 struct drm_i915_gem_request,
2190 list);
2191
2192 /* Make sure we do not trigger any retires */
2193 return __i915_wait_request(req,
2194 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2195 to_i915(ring->dev)->mm.interruptible,
2196 NULL, NULL);
3e960501
CW		 2197}
2198
6689cb2b 2199int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2200{
6689cb2b 2201 request->ringbuf = request->ring->buffer;
9eba5d4a 2202 return 0;
9d773091
CW		 2203}
2204
ccd98fe4
JH		 2205int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2206{
2207 /*
2208 * The first call merely notes the reserve request and is common for
2209 * all back ends. The subsequent localised _begin() call actually
2210 * ensures that the reservation is available. Without the begin, if
2211 * the request creator immediately submitted the request without
2212 * adding any commands to it then there might not actually be
2213 * sufficient room for the submission commands.
2214 */
2215 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2216
2217 return intel_ring_begin(request, 0);
2218}
2219
29b1b415
JH		 2220void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2221{
ccd98fe4 2222 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2223 WARN_ON(ringbuf->reserved_in_use);
2224
2225 ringbuf->reserved_size = size;
29b1b415
JH		 2226}
2227
2228void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2229{
2230 WARN_ON(ringbuf->reserved_in_use);
2231
2232 ringbuf->reserved_size = 0;
2233 ringbuf->reserved_in_use = false;
2234}
2235
2236void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2237{
2238 WARN_ON(ringbuf->reserved_in_use);
2239
2240 ringbuf->reserved_in_use = true;
2241 ringbuf->reserved_tail = ringbuf->tail;
2242}
2243
2244void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2245{
2246 WARN_ON(!ringbuf->reserved_in_use);
2247 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2248 "request reserved size too small: %d vs %d!\n",
2249 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2250
2251 ringbuf->reserved_size = 0;
2252 ringbuf->reserved_in_use = false;
2253}
2254
2255static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2256{
93b0a4e0 2257 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2258 int ret;
2259
29b1b415
JH		 2260 /*
2261 * Add on the reserved size to the request to make sure that after
2262 * the intended commands have been emitted, there is guaranteed to
2263 * still be enough free space to send them to the hardware.
2264 */
2265 if (!ringbuf->reserved_in_use)
2266 bytes += ringbuf->reserved_size;
2267
93b0a4e0 2268 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2269 ret = intel_wrap_ring_buffer(ring);
2270 if (unlikely(ret))
2271 return ret;
29b1b415
JH		 2272
2273 if(ringbuf->reserved_size) {
2274 uint32_t size = ringbuf->reserved_size;
2275
2276 intel_ring_reserved_space_cancel(ringbuf);
2277 intel_ring_reserved_space_reserve(ringbuf, size);
2278 }
cbcc80df
MK		 2279 }
2280
93b0a4e0 2281 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2282 ret = ring_wait_for_space(ring, bytes);
2283 if (unlikely(ret))
2284 return ret;
2285 }
2286
cbcc80df
MK		 2287 return 0;
2288}
2289
5fb9de1a 2290int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2291 int num_dwords)
8187a2b7 2292{
5fb9de1a
JH		 2293 struct intel_engine_cs *ring;
2294 struct drm_i915_private *dev_priv;
e1f99ce6 2295 int ret;
78501eac 2296
5fb9de1a
JH		 2297 WARN_ON(req == NULL);
2298 ring = req->ring;
2299 dev_priv = ring->dev->dev_private;
2300
33196ded
DV		 2301 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2302 dev_priv->mm.interruptible);
de2b9985
DV		 2303 if (ret)
2304 return ret;
21dd3734 2305
304d695c
CW		 2306 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2307 if (ret)
2308 return ret;
2309
ee1b1e5e 2310 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2311 return 0;
8187a2b7 2312}
78501eac 2313
753b1ad4 2314/* Align the ring tail to a cacheline boundary */
bba09b12 2315int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2316{
bba09b12 2317 struct intel_engine_cs *ring = req->ring;
ee1b1e5e 2318 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2319 int ret;
2320
2321 if (num_dwords == 0)
2322 return 0;
2323
18393f63 2324 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2325 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2326 if (ret)
2327 return ret;
2328
2329 while (num_dwords--)
2330 intel_ring_emit(ring, MI_NOOP);
2331
2332 intel_ring_advance(ring);
2333
2334 return 0;
2335}
2336
a4872ba6 2337void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2338{
3b2cc8ab
OM		 2339 struct drm_device *dev = ring->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2341
6259cead 2342 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2343
3b2cc8ab 2344 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2345 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2346 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2347 if (HAS_VEBOX(dev))
5020150b 2348 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2349 }
d97ed339 2350
f7e98ad4 2351 ring->set_seqno(ring, seqno);
92cab734 2352 ring->hangcheck.seqno = seqno;
8187a2b7 2353}
62fdfeaf 2354
a4872ba6 2355static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2356 u32 value)
881f47b6 2357{
4640c4ff 2358 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2359
2360 /* Every tail move must follow the sequence below */
12f55818
CW		 2361
2362 /* Disable notification that the ring is IDLE. The GT
2363 * will then assume that it is busy and bring it out of rc6.
2364 */
0206e353 2365 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2366 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2367
2368 /* Clear the context id. Here be magic! */
2369 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2370
12f55818 2371 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2372 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2373 GEN6_BSD_SLEEP_INDICATOR) == 0,
2374 50))
2375 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2376
12f55818 2377 /* Now that the ring is fully powered up, update the tail */
0206e353 2378 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2379 POSTING_READ(RING_TAIL(ring->mmio_base));
2380
2381 /* Let the ring send IDLE messages to the GT again,
2382 * and so let it sleep to conserve power when idle.
2383 */
0206e353 2384 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2385 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2386}
2387
a84c3ae1 2388static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2389 u32 invalidate, u32 flush)
881f47b6 2390{
a84c3ae1 2391 struct intel_engine_cs *ring = req->ring;
71a77e07 2392 uint32_t cmd;
b72f3acb
CW		 2393 int ret;
2394
5fb9de1a 2395 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2396 if (ret)
2397 return ret;
2398
71a77e07 2399 cmd = MI_FLUSH_DW;
075b3bba
BW		 2400 if (INTEL_INFO(ring->dev)->gen >= 8)
2401 cmd += 1;
f0a1fb10
CW		 2402
2403 /* We always require a command barrier so that subsequent
2404 * commands, such as breadcrumb interrupts, are strictly ordered
2405 * wrt the contents of the write cache being flushed to memory
2406 * (and thus being coherent from the CPU).
2407 */
2408 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2409
9a289771
JB		 2410 /*
2411 * Bspec vol 1c.5 - video engine command streamer:
2412 * "If ENABLED, all TLBs will be invalidated once the flush
2413 * operation is complete. This bit is only valid when the
2414 * Post-Sync Operation field is a value of 1h or 3h."
2415 */
71a77e07 2416 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2417 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2418
71a77e07 2419 intel_ring_emit(ring, cmd);
9a289771 2420 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2421 if (INTEL_INFO(ring->dev)->gen >= 8) {
2422 intel_ring_emit(ring, 0); /* upper addr */
2423 intel_ring_emit(ring, 0); /* value */
2424 } else {
2425 intel_ring_emit(ring, 0);
2426 intel_ring_emit(ring, MI_NOOP);
2427 }
b72f3acb
CW		 2428 intel_ring_advance(ring);
2429 return 0;
881f47b6
XH		 2430}
2431
1c7a0623 2432static int
53fddaf7 2433gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2434 u64 offset, u32 len,
8e004efc 2435 unsigned dispatch_flags)
1c7a0623 2436{
53fddaf7 2437 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2438 bool ppgtt = USES_PPGTT(ring->dev) &&
2439 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2440 int ret;
2441
5fb9de1a 2442 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2443 if (ret)
2444 return ret;
2445
2446 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2447 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2448 intel_ring_emit(ring, lower_32_bits(offset));
2449 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2450 intel_ring_emit(ring, MI_NOOP);
2451 intel_ring_advance(ring);
2452
2453 return 0;
2454}
2455
d7d4eedd 2456static int
53fddaf7 2457hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2458 u64 offset, u32 len,
2459 unsigned dispatch_flags)
d7d4eedd 2460{
53fddaf7 2461 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2462 int ret;
2463
5fb9de1a 2464 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2465 if (ret)
2466 return ret;
2467
2468 intel_ring_emit(ring,
77072258 2469 MI_BATCH_BUFFER_START |
8e004efc 2470 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2471 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2472 /* bit0-7 is the length on GEN6+ */
2473 intel_ring_emit(ring, offset);
2474 intel_ring_advance(ring);
2475
2476 return 0;
2477}
2478
881f47b6 2479static int
53fddaf7 2480gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2481 u64 offset, u32 len,
8e004efc 2482 unsigned dispatch_flags)
881f47b6 2483{
53fddaf7 2484 struct intel_engine_cs *ring = req->ring;
0206e353 2485 int ret;
ab6f8e32 2486
5fb9de1a 2487 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2488 if (ret)
2489 return ret;
e1f99ce6 2490
d7d4eedd
CW		 2491 intel_ring_emit(ring,
2492 MI_BATCH_BUFFER_START |
8e004efc
JH		 2493 (dispatch_flags & I915_DISPATCH_SECURE ?
2494 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2495 /* bit0-7 is the length on GEN6+ */
2496 intel_ring_emit(ring, offset);
2497 intel_ring_advance(ring);
ab6f8e32 2498
0206e353 2499 return 0;
881f47b6
XH		 2500}
2501
549f7365
CW		 2502/* Blitter support (SandyBridge+) */
2503
a84c3ae1 2504static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2505 u32 invalidate, u32 flush)
8d19215b 2506{
a84c3ae1 2507 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2508 struct drm_device *dev = ring->dev;
71a77e07 2509 uint32_t cmd;
b72f3acb
CW		 2510 int ret;
2511
5fb9de1a 2512 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2513 if (ret)
2514 return ret;
2515
71a77e07 2516 cmd = MI_FLUSH_DW;
dbef0f15 2517 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2518 cmd += 1;
f0a1fb10
CW		 2519
2520 /* We always require a command barrier so that subsequent
2521 * commands, such as breadcrumb interrupts, are strictly ordered
2522 * wrt the contents of the write cache being flushed to memory
2523 * (and thus being coherent from the CPU).
2524 */
2525 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2526
9a289771
JB		 2527 /*
2528 * Bspec vol 1c.3 - blitter engine command streamer:
2529 * "If ENABLED, all TLBs will be invalidated once the flush
2530 * operation is complete. This bit is only valid when the
2531 * Post-Sync Operation field is a value of 1h or 3h."
2532 */
71a77e07 2533 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2534 cmd |= MI_INVALIDATE_TLB;
71a77e07 2535 intel_ring_emit(ring, cmd);
9a289771 2536 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2537 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2538 intel_ring_emit(ring, 0); /* upper addr */
2539 intel_ring_emit(ring, 0); /* value */
2540 } else {
2541 intel_ring_emit(ring, 0);
2542 intel_ring_emit(ring, MI_NOOP);
2543 }
b72f3acb 2544 intel_ring_advance(ring);
fd3da6c9 2545
b72f3acb 2546 return 0;
8d19215b
ZN		 2547}
2548
5c1143bb
XH		 2549int intel_init_render_ring_buffer(struct drm_device *dev)
2550{
4640c4ff 2551 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2552 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2553 struct drm_i915_gem_object *obj;
2554 int ret;
5c1143bb 2555
59465b5f
DV		 2556 ring->name = "render ring";
2557 ring->id = RCS;
2558 ring->mmio_base = RENDER_RING_BASE;
2559
707d9cf9 2560 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2561 if (i915_semaphore_is_enabled(dev)) {
2562 obj = i915_gem_alloc_object(dev, 4096);
2563 if (obj == NULL) {
2564 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2565 i915.semaphores = 0;
2566 } else {
2567 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2568 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2569 if (ret != 0) {
2570 drm_gem_object_unreference(&obj->base);
2571 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2572 i915.semaphores = 0;
2573 } else
2574 dev_priv->semaphore_obj = obj;
2575 }
2576 }
7225342a 2577
8f0e2b9d 2578 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2579 ring->add_request = gen6_add_request;
2580 ring->flush = gen8_render_ring_flush;
2581 ring->irq_get = gen8_ring_get_irq;
2582 ring->irq_put = gen8_ring_put_irq;
2583 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2584 ring->get_seqno = gen6_ring_get_seqno;
2585 ring->set_seqno = ring_set_seqno;
2586 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2587 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2588 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2589 ring->semaphore.signal = gen8_rcs_signal;
2590 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2591 }
2592 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2593 ring->add_request = gen6_add_request;
4772eaeb 2594 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2595 if (INTEL_INFO(dev)->gen == 6)
b3111509 2596 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2597 ring->irq_get = gen6_ring_get_irq;
2598 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2599 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2600 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2601 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2602 if (i915_semaphore_is_enabled(dev)) {
2603 ring->semaphore.sync_to = gen6_ring_sync;
2604 ring->semaphore.signal = gen6_signal;
2605 /*
2606 * The current semaphore is only applied on pre-gen8
2607 * platform. And there is no VCS2 ring on the pre-gen8
2608 * platform. So the semaphore between RCS and VCS2 is
2609 * initialized as INVALID. Gen8 will initialize the
2610 * sema between VCS2 and RCS later.
2611 */
2612 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2613 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2614 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2615 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2616 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2617 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2618 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2619 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2620 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2621 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2622 }
c6df541c
CW		 2623 } else if (IS_GEN5(dev)) {
2624 ring->add_request = pc_render_add_request;
46f0f8d1 2625 ring->flush = gen4_render_ring_flush;
c6df541c 2626 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2627 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2628 ring->irq_get = gen5_ring_get_irq;
2629 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2630 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2631 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2632 } else {
8620a3a9 2633 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2634 if (INTEL_INFO(dev)->gen < 4)
2635 ring->flush = gen2_render_ring_flush;
2636 else
2637 ring->flush = gen4_render_ring_flush;
59465b5f 2638 ring->get_seqno = ring_get_seqno;
b70ec5bf 2639 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2640 if (IS_GEN2(dev)) {
2641 ring->irq_get = i8xx_ring_get_irq;
2642 ring->irq_put = i8xx_ring_put_irq;
2643 } else {
2644 ring->irq_get = i9xx_ring_get_irq;
2645 ring->irq_put = i9xx_ring_put_irq;
2646 }
e3670319 2647 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2648 }
59465b5f 2649 ring->write_tail = ring_write_tail;
707d9cf9 2650
d7d4eedd
CW		 2651 if (IS_HASWELL(dev))
2652 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2653 else if (IS_GEN8(dev))
2654 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2655 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2656 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2657 else if (INTEL_INFO(dev)->gen >= 4)
2658 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2659 else if (IS_I830(dev) || IS_845G(dev))
2660 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2661 else
2662 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2663 ring->init_hw = init_render_ring;
59465b5f
DV		 2664 ring->cleanup = render_ring_cleanup;
2665
b45305fc
DV		 2666 /* Workaround batchbuffer to combat CS tlb bug. */
2667 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2668 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2669 if (obj == NULL) {
2670 DRM_ERROR("Failed to allocate batch bo\n");
2671 return -ENOMEM;
2672 }
2673
be1fa129 2674 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2675 if (ret != 0) {
2676 drm_gem_object_unreference(&obj->base);
2677 DRM_ERROR("Failed to ping batch bo\n");
2678 return ret;
2679 }
2680
0d1aacac
CW		 2681 ring->scratch.obj = obj;
2682 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2683 }
2684
99be1dfe
DV		 2685 ret = intel_init_ring_buffer(dev, ring);
2686 if (ret)
2687 return ret;
2688
2689 if (INTEL_INFO(dev)->gen >= 5) {
2690 ret = intel_init_pipe_control(ring);
2691 if (ret)
2692 return ret;
2693 }
2694
2695 return 0;
5c1143bb
XH		 2696}
2697
2698int intel_init_bsd_ring_buffer(struct drm_device *dev)
2699{
4640c4ff 2700 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2701 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2702
58fa3835
DV		 2703 ring->name = "bsd ring";
2704 ring->id = VCS;
2705
0fd2c201 2706 ring->write_tail = ring_write_tail;
780f18c8 2707 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2708 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2709 /* gen6 bsd needs a special wa for tail updates */
2710 if (IS_GEN6(dev))
2711 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2712 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2713 ring->add_request = gen6_add_request;
2714 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2715 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2716 if (INTEL_INFO(dev)->gen >= 8) {
2717 ring->irq_enable_mask =
2718 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2719 ring->irq_get = gen8_ring_get_irq;
2720 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2721 ring->dispatch_execbuffer =
2722 gen8_ring_dispatch_execbuffer;
707d9cf9 2723 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2724 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2725 ring->semaphore.signal = gen8_xcs_signal;
2726 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2727 }
abd58f01
BW		 2728 } else {
2729 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2730 ring->irq_get = gen6_ring_get_irq;
2731 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2732 ring->dispatch_execbuffer =
2733 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2734 if (i915_semaphore_is_enabled(dev)) {
2735 ring->semaphore.sync_to = gen6_ring_sync;
2736 ring->semaphore.signal = gen6_signal;
2737 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2738 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2739 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2740 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2741 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2742 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2743 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2744 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2745 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2746 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2747 }
abd58f01 2748 }
58fa3835
DV		 2749 } else {
2750 ring->mmio_base = BSD_RING_BASE;
58fa3835 2751 ring->flush = bsd_ring_flush;
8620a3a9 2752 ring->add_request = i9xx_add_request;
58fa3835 2753 ring->get_seqno = ring_get_seqno;
b70ec5bf 2754 ring->set_seqno = ring_set_seqno;
e48d8634 2755 if (IS_GEN5(dev)) {
cc609d5d 2756 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2757 ring->irq_get = gen5_ring_get_irq;
2758 ring->irq_put = gen5_ring_put_irq;
2759 } else {
e3670319 2760 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2761 ring->irq_get = i9xx_ring_get_irq;
2762 ring->irq_put = i9xx_ring_put_irq;
2763 }
fb3256da 2764 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2765 }
ecfe00d8 2766 ring->init_hw = init_ring_common;
58fa3835 2767
1ec14ad3 2768 return intel_init_ring_buffer(dev, ring);
5c1143bb 2769}
549f7365 2770
845f74a7 2771/**
62659920 2772 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2773 */
2774int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2775{
2776 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2777 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2778
f7b64236 2779 ring->name = "bsd2 ring";
845f74a7
ZY		 2780 ring->id = VCS2;
2781
2782 ring->write_tail = ring_write_tail;
2783 ring->mmio_base = GEN8_BSD2_RING_BASE;
2784 ring->flush = gen6_bsd_ring_flush;
2785 ring->add_request = gen6_add_request;
2786 ring->get_seqno = gen6_ring_get_seqno;
2787 ring->set_seqno = ring_set_seqno;
2788 ring->irq_enable_mask =
2789 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2790 ring->irq_get = gen8_ring_get_irq;
2791 ring->irq_put = gen8_ring_put_irq;
2792 ring->dispatch_execbuffer =
2793 gen8_ring_dispatch_execbuffer;
3e78998a 2794 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2795 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2796 ring->semaphore.signal = gen8_xcs_signal;
2797 GEN8_RING_SEMAPHORE_INIT;
2798 }
ecfe00d8 2799 ring->init_hw = init_ring_common;
845f74a7
ZY		 2800
2801 return intel_init_ring_buffer(dev, ring);
2802}
2803
549f7365
CW		 2804int intel_init_blt_ring_buffer(struct drm_device *dev)
2805{
4640c4ff 2806 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2807 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2808
3535d9dd
DV		 2809 ring->name = "blitter ring";
2810 ring->id = BCS;
2811
2812 ring->mmio_base = BLT_RING_BASE;
2813 ring->write_tail = ring_write_tail;
ea251324 2814 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2815 ring->add_request = gen6_add_request;
2816 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2817 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2818 if (INTEL_INFO(dev)->gen >= 8) {
2819 ring->irq_enable_mask =
2820 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2821 ring->irq_get = gen8_ring_get_irq;
2822 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2823 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2824 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2825 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2826 ring->semaphore.signal = gen8_xcs_signal;
2827 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2828 }
abd58f01
BW		 2829 } else {
2830 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2831 ring->irq_get = gen6_ring_get_irq;
2832 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2833 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2834 if (i915_semaphore_is_enabled(dev)) {
2835 ring->semaphore.signal = gen6_signal;
2836 ring->semaphore.sync_to = gen6_ring_sync;
2837 /*
2838 * The current semaphore is only applied on pre-gen8
2839 * platform. And there is no VCS2 ring on the pre-gen8
2840 * platform. So the semaphore between BCS and VCS2 is
2841 * initialized as INVALID. Gen8 will initialize the
2842 * sema between BCS and VCS2 later.
2843 */
2844 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2845 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2846 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2847 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2848 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2849 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2850 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2851 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2852 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2853 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2854 }
abd58f01 2855 }
ecfe00d8 2856 ring->init_hw = init_ring_common;
549f7365 2857
1ec14ad3 2858 return intel_init_ring_buffer(dev, ring);
549f7365 2859}
a7b9761d 2860
9a8a2213
BW		 2861int intel_init_vebox_ring_buffer(struct drm_device *dev)
2862{
4640c4ff 2863 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2864 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2865
2866 ring->name = "video enhancement ring";
2867 ring->id = VECS;
2868
2869 ring->mmio_base = VEBOX_RING_BASE;
2870 ring->write_tail = ring_write_tail;
2871 ring->flush = gen6_ring_flush;
2872 ring->add_request = gen6_add_request;
2873 ring->get_seqno = gen6_ring_get_seqno;
2874 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2875
2876 if (INTEL_INFO(dev)->gen >= 8) {
2877 ring->irq_enable_mask =
40c499f9 2878 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2879 ring->irq_get = gen8_ring_get_irq;
2880 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2881 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2882 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2883 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2884 ring->semaphore.signal = gen8_xcs_signal;
2885 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2886 }
abd58f01
BW		 2887 } else {
2888 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2889 ring->irq_get = hsw_vebox_get_irq;
2890 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2891 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2892 if (i915_semaphore_is_enabled(dev)) {
2893 ring->semaphore.sync_to = gen6_ring_sync;
2894 ring->semaphore.signal = gen6_signal;
2895 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2896 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2897 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2898 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2899 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2900 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2901 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2902 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2903 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2904 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2905 }
abd58f01 2906 }
ecfe00d8 2907 ring->init_hw = init_ring_common;
9a8a2213
BW		 2908
2909 return intel_init_ring_buffer(dev, ring);
2910}
2911
a7b9761d 2912int
4866d729 2913intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2914{
4866d729 2915 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2916 int ret;
2917
2918 if (!ring->gpu_caches_dirty)
2919 return 0;
2920
a84c3ae1 2921 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2922 if (ret)
2923 return ret;
2924
a84c3ae1 2925 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2926
2927 ring->gpu_caches_dirty = false;
2928 return 0;
2929}
2930
2931int
2f20055d 2932intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2933{
2f20055d 2934 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2935 uint32_t flush_domains;
2936 int ret;
2937
2938 flush_domains = 0;
2939 if (ring->gpu_caches_dirty)
2940 flush_domains = I915_GEM_GPU_DOMAINS;
2941
a84c3ae1 2942 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2943 if (ret)
2944 return ret;
2945
a84c3ae1 2946 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2947
2948 ring->gpu_caches_dirty = false;
2949 return 0;
2950}
e3efda49
CW		 2951
2952void
a4872ba6 2953intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2954{
2955 int ret;
2956
2957 if (!intel_ring_initialized(ring))
2958 return;
2959
2960 ret = intel_ring_idle(ring);
2961 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2962 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2963 ring->name, ret);
2964
2965 stop_ring(ring);
2966}
Linux kernel - Deliverables
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