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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
ebd0fd4b DG |
50 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
51 | { | |
52 | if (ringbuf->last_retired_head != -1) { | |
53 | ringbuf->head = ringbuf->last_retired_head; | |
54 | ringbuf->last_retired_head = -1; | |
55 | } | |
56 | ||
57 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
58 | ringbuf->tail, ringbuf->size); | |
59 | } | |
60 | ||
117897f4 | 61 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 62 | { |
c033666a | 63 | struct drm_i915_private *dev_priv = engine->i915; |
666796da | 64 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 65 | } |
09246732 | 66 | |
0bc40be8 | 67 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 68 | { |
0bc40be8 | 69 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 70 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 71 | if (intel_engine_stopped(engine)) |
09246732 | 72 | return; |
0bc40be8 | 73 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
74 | } |
75 | ||
b72f3acb | 76 | static int |
a84c3ae1 | 77 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
78 | u32 invalidate_domains, |
79 | u32 flush_domains) | |
80 | { | |
4a570db5 | 81 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
82 | u32 cmd; |
83 | int ret; | |
84 | ||
85 | cmd = MI_FLUSH; | |
31b14c9f | 86 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
87 | cmd |= MI_NO_WRITE_FLUSH; |
88 | ||
89 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
90 | cmd |= MI_READ_FLUSH; | |
91 | ||
5fb9de1a | 92 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
93 | if (ret) |
94 | return ret; | |
95 | ||
e2f80391 TU |
96 | intel_ring_emit(engine, cmd); |
97 | intel_ring_emit(engine, MI_NOOP); | |
98 | intel_ring_advance(engine); | |
46f0f8d1 CW |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static int | |
a84c3ae1 | 104 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
105 | u32 invalidate_domains, |
106 | u32 flush_domains) | |
62fdfeaf | 107 | { |
4a570db5 | 108 | struct intel_engine_cs *engine = req->engine; |
6f392d54 | 109 | u32 cmd; |
b72f3acb | 110 | int ret; |
6f392d54 | 111 | |
36d527de CW |
112 | /* |
113 | * read/write caches: | |
114 | * | |
115 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
116 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
117 | * also flushed at 2d versus 3d pipeline switches. | |
118 | * | |
119 | * read-only caches: | |
120 | * | |
121 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
122 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
123 | * | |
124 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
125 | * | |
126 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
127 | * invalidated when MI_EXE_FLUSH is set. | |
128 | * | |
129 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
130 | * invalidated with every MI_FLUSH. | |
131 | * | |
132 | * TLBs: | |
133 | * | |
134 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
135 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
136 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
137 | * are flushed at any MI_FLUSH. | |
138 | */ | |
139 | ||
140 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 141 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 142 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
143 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
144 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 145 | |
36d527de | 146 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
c033666a | 147 | (IS_G4X(req->i915) || IS_GEN5(req->i915))) |
36d527de | 148 | cmd |= MI_INVALIDATE_ISP; |
70eac33e | 149 | |
5fb9de1a | 150 | ret = intel_ring_begin(req, 2); |
36d527de CW |
151 | if (ret) |
152 | return ret; | |
b72f3acb | 153 | |
e2f80391 TU |
154 | intel_ring_emit(engine, cmd); |
155 | intel_ring_emit(engine, MI_NOOP); | |
156 | intel_ring_advance(engine); | |
b72f3acb CW |
157 | |
158 | return 0; | |
8187a2b7 ZN |
159 | } |
160 | ||
8d315287 JB |
161 | /** |
162 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
163 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
164 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
165 | * | |
166 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
167 | * produced by non-pipelined state commands), software needs to first | |
168 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
169 | * 0. | |
170 | * | |
171 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
172 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
173 | * | |
174 | * And the workaround for these two requires this workaround first: | |
175 | * | |
176 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
177 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
178 | * flushes. | |
179 | * | |
180 | * And this last workaround is tricky because of the requirements on | |
181 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
182 | * volume 2 part 1: | |
183 | * | |
184 | * "1 of the following must also be set: | |
185 | * - Render Target Cache Flush Enable ([12] of DW1) | |
186 | * - Depth Cache Flush Enable ([0] of DW1) | |
187 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
188 | * - Depth Stall ([13] of DW1) | |
189 | * - Post-Sync Operation ([13] of DW1) | |
190 | * - Notify Enable ([8] of DW1)" | |
191 | * | |
192 | * The cache flushes require the workaround flush that triggered this | |
193 | * one, so we can't use it. Depth stall would trigger the same. | |
194 | * Post-sync nonzero is what triggered this second workaround, so we | |
195 | * can't use that one either. Notify enable is IRQs, which aren't | |
196 | * really our business. That leaves only stall at scoreboard. | |
197 | */ | |
198 | static int | |
f2cf1fcc | 199 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 200 | { |
4a570db5 | 201 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 202 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
203 | int ret; |
204 | ||
5fb9de1a | 205 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
206 | if (ret) |
207 | return ret; | |
208 | ||
e2f80391 TU |
209 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
210 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 211 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
212 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
213 | intel_ring_emit(engine, 0); /* low dword */ | |
214 | intel_ring_emit(engine, 0); /* high dword */ | |
215 | intel_ring_emit(engine, MI_NOOP); | |
216 | intel_ring_advance(engine); | |
8d315287 | 217 | |
5fb9de1a | 218 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
219 | if (ret) |
220 | return ret; | |
221 | ||
e2f80391 TU |
222 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
223 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
224 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
225 | intel_ring_emit(engine, 0); | |
226 | intel_ring_emit(engine, 0); | |
227 | intel_ring_emit(engine, MI_NOOP); | |
228 | intel_ring_advance(engine); | |
8d315287 JB |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static int | |
a84c3ae1 JH |
234 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
235 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 236 | { |
4a570db5 | 237 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 238 | u32 flags = 0; |
e2f80391 | 239 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
240 | int ret; |
241 | ||
b3111509 | 242 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 243 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
244 | if (ret) |
245 | return ret; | |
246 | ||
8d315287 JB |
247 | /* Just flush everything. Experiments have shown that reducing the |
248 | * number of bits based on the write domains has little performance | |
249 | * impact. | |
250 | */ | |
7d54a904 CW |
251 | if (flush_domains) { |
252 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
253 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
254 | /* | |
255 | * Ensure that any following seqno writes only happen | |
256 | * when the render cache is indeed flushed. | |
257 | */ | |
97f209bc | 258 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
259 | } |
260 | if (invalidate_domains) { | |
261 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
262 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
263 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
264 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
265 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
266 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
267 | /* | |
268 | * TLB invalidate requires a post-sync write. | |
269 | */ | |
3ac78313 | 270 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 271 | } |
8d315287 | 272 | |
5fb9de1a | 273 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
274 | if (ret) |
275 | return ret; | |
276 | ||
e2f80391 TU |
277 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
278 | intel_ring_emit(engine, flags); | |
279 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
280 | intel_ring_emit(engine, 0); | |
281 | intel_ring_advance(engine); | |
8d315287 JB |
282 | |
283 | return 0; | |
284 | } | |
285 | ||
f3987631 | 286 | static int |
f2cf1fcc | 287 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 288 | { |
4a570db5 | 289 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
290 | int ret; |
291 | ||
5fb9de1a | 292 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
293 | if (ret) |
294 | return ret; | |
295 | ||
e2f80391 TU |
296 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
297 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 298 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
299 | intel_ring_emit(engine, 0); |
300 | intel_ring_emit(engine, 0); | |
301 | intel_ring_advance(engine); | |
f3987631 PZ |
302 | |
303 | return 0; | |
304 | } | |
305 | ||
4772eaeb | 306 | static int |
a84c3ae1 | 307 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
308 | u32 invalidate_domains, u32 flush_domains) |
309 | { | |
4a570db5 | 310 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 311 | u32 flags = 0; |
e2f80391 | 312 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
313 | int ret; |
314 | ||
f3987631 PZ |
315 | /* |
316 | * Ensure that any following seqno writes only happen when the render | |
317 | * cache is indeed flushed. | |
318 | * | |
319 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
320 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
321 | * don't try to be clever and just set it unconditionally. | |
322 | */ | |
323 | flags |= PIPE_CONTROL_CS_STALL; | |
324 | ||
4772eaeb PZ |
325 | /* Just flush everything. Experiments have shown that reducing the |
326 | * number of bits based on the write domains has little performance | |
327 | * impact. | |
328 | */ | |
329 | if (flush_domains) { | |
330 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
331 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 332 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 333 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
334 | } |
335 | if (invalidate_domains) { | |
336 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
337 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
338 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
339 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
340 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
341 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 342 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
343 | /* |
344 | * TLB invalidate requires a post-sync write. | |
345 | */ | |
346 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 347 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 348 | |
add284a3 CW |
349 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
350 | ||
f3987631 PZ |
351 | /* Workaround: we must issue a pipe_control with CS-stall bit |
352 | * set before a pipe_control command that has the state cache | |
353 | * invalidate bit set. */ | |
f2cf1fcc | 354 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
355 | } |
356 | ||
5fb9de1a | 357 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
358 | if (ret) |
359 | return ret; | |
360 | ||
e2f80391 TU |
361 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
362 | intel_ring_emit(engine, flags); | |
363 | intel_ring_emit(engine, scratch_addr); | |
364 | intel_ring_emit(engine, 0); | |
365 | intel_ring_advance(engine); | |
4772eaeb PZ |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
884ceace | 370 | static int |
f2cf1fcc | 371 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
372 | u32 flags, u32 scratch_addr) |
373 | { | |
4a570db5 | 374 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
375 | int ret; |
376 | ||
5fb9de1a | 377 | ret = intel_ring_begin(req, 6); |
884ceace KG |
378 | if (ret) |
379 | return ret; | |
380 | ||
e2f80391 TU |
381 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
382 | intel_ring_emit(engine, flags); | |
383 | intel_ring_emit(engine, scratch_addr); | |
384 | intel_ring_emit(engine, 0); | |
385 | intel_ring_emit(engine, 0); | |
386 | intel_ring_emit(engine, 0); | |
387 | intel_ring_advance(engine); | |
884ceace KG |
388 | |
389 | return 0; | |
390 | } | |
391 | ||
a5f3d68e | 392 | static int |
a84c3ae1 | 393 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
394 | u32 invalidate_domains, u32 flush_domains) |
395 | { | |
396 | u32 flags = 0; | |
4a570db5 | 397 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 398 | int ret; |
a5f3d68e BW |
399 | |
400 | flags |= PIPE_CONTROL_CS_STALL; | |
401 | ||
402 | if (flush_domains) { | |
403 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
404 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 405 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 406 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
407 | } |
408 | if (invalidate_domains) { | |
409 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
410 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
411 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
412 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
413 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
414 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
415 | flags |= PIPE_CONTROL_QW_WRITE; | |
416 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
417 | |
418 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 419 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
420 | PIPE_CONTROL_CS_STALL | |
421 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
422 | 0); | |
423 | if (ret) | |
424 | return ret; | |
a5f3d68e BW |
425 | } |
426 | ||
f2cf1fcc | 427 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
428 | } |
429 | ||
0bc40be8 | 430 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 431 | u32 value) |
d46eefa2 | 432 | { |
c033666a | 433 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 434 | I915_WRITE_TAIL(engine, value); |
d46eefa2 XH |
435 | } |
436 | ||
0bc40be8 | 437 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 438 | { |
c033666a | 439 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 440 | u64 acthd; |
8187a2b7 | 441 | |
c033666a | 442 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
443 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
444 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 445 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 446 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
447 | else |
448 | acthd = I915_READ(ACTHD); | |
449 | ||
450 | return acthd; | |
8187a2b7 ZN |
451 | } |
452 | ||
0bc40be8 | 453 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 454 | { |
c033666a | 455 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
456 | u32 addr; |
457 | ||
458 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 459 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
460 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
461 | I915_WRITE(HWS_PGA, addr); | |
462 | } | |
463 | ||
0bc40be8 | 464 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 465 | { |
c033666a | 466 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 467 | i915_reg_t mmio; |
af75f269 DL |
468 | |
469 | /* The ring status page addresses are no longer next to the rest of | |
470 | * the ring registers as of gen7. | |
471 | */ | |
c033666a | 472 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 473 | switch (engine->id) { |
af75f269 DL |
474 | case RCS: |
475 | mmio = RENDER_HWS_PGA_GEN7; | |
476 | break; | |
477 | case BCS: | |
478 | mmio = BLT_HWS_PGA_GEN7; | |
479 | break; | |
480 | /* | |
481 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
482 | * gcc switch check warning | |
483 | */ | |
484 | case VCS2: | |
485 | case VCS: | |
486 | mmio = BSD_HWS_PGA_GEN7; | |
487 | break; | |
488 | case VECS: | |
489 | mmio = VEBOX_HWS_PGA_GEN7; | |
490 | break; | |
491 | } | |
c033666a | 492 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 493 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
494 | } else { |
495 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 496 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
497 | } |
498 | ||
0bc40be8 | 499 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
500 | POSTING_READ(mmio); |
501 | ||
502 | /* | |
503 | * Flush the TLB for this page | |
504 | * | |
505 | * FIXME: These two bits have disappeared on gen8, so a question | |
506 | * arises: do we still need this and if so how should we go about | |
507 | * invalidating the TLB? | |
508 | */ | |
ac657f64 | 509 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 510 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
511 | |
512 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 513 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
514 | |
515 | I915_WRITE(reg, | |
516 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
517 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
518 | if (intel_wait_for_register(dev_priv, |
519 | reg, INSTPM_SYNC_FLUSH, 0, | |
520 | 1000)) | |
af75f269 | 521 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 522 | engine->name); |
af75f269 DL |
523 | } |
524 | } | |
525 | ||
0bc40be8 | 526 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 527 | { |
c033666a | 528 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 529 | |
c033666a | 530 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 | 531 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
532 | if (intel_wait_for_register(dev_priv, |
533 | RING_MI_MODE(engine->mmio_base), | |
534 | MODE_IDLE, | |
535 | MODE_IDLE, | |
536 | 1000)) { | |
0bc40be8 TU |
537 | DRM_ERROR("%s : timed out trying to stop ring\n", |
538 | engine->name); | |
9bec9b13 CW |
539 | /* Sometimes we observe that the idle flag is not |
540 | * set even though the ring is empty. So double | |
541 | * check before giving up. | |
542 | */ | |
0bc40be8 | 543 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 544 | return false; |
9991ae78 CW |
545 | } |
546 | } | |
b7884eb4 | 547 | |
0bc40be8 TU |
548 | I915_WRITE_CTL(engine, 0); |
549 | I915_WRITE_HEAD(engine, 0); | |
550 | engine->write_tail(engine, 0); | |
8187a2b7 | 551 | |
c033666a | 552 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 TU |
553 | (void)I915_READ_CTL(engine); |
554 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 555 | } |
a51435a3 | 556 | |
0bc40be8 | 557 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 558 | } |
8187a2b7 | 559 | |
fc0768ce TE |
560 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
561 | { | |
562 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
563 | } | |
564 | ||
0bc40be8 | 565 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 566 | { |
c033666a | 567 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 568 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 569 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
570 | int ret = 0; |
571 | ||
59bad947 | 572 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 573 | |
0bc40be8 | 574 | if (!stop_ring(engine)) { |
9991ae78 | 575 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
576 | DRM_DEBUG_KMS("%s head not reset to zero " |
577 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
578 | engine->name, |
579 | I915_READ_CTL(engine), | |
580 | I915_READ_HEAD(engine), | |
581 | I915_READ_TAIL(engine), | |
582 | I915_READ_START(engine)); | |
8187a2b7 | 583 | |
0bc40be8 | 584 | if (!stop_ring(engine)) { |
6fd0d56e CW |
585 | DRM_ERROR("failed to set %s head to zero " |
586 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
587 | engine->name, |
588 | I915_READ_CTL(engine), | |
589 | I915_READ_HEAD(engine), | |
590 | I915_READ_TAIL(engine), | |
591 | I915_READ_START(engine)); | |
9991ae78 CW |
592 | ret = -EIO; |
593 | goto out; | |
6fd0d56e | 594 | } |
8187a2b7 ZN |
595 | } |
596 | ||
c033666a | 597 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 598 | intel_ring_setup_status_page(engine); |
9991ae78 | 599 | else |
0bc40be8 | 600 | ring_setup_phys_status_page(engine); |
9991ae78 | 601 | |
ece4a17d | 602 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 603 | I915_READ_HEAD(engine); |
ece4a17d | 604 | |
0d8957c8 DV |
605 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
606 | * registers with the above sequence (the readback of the HEAD registers | |
607 | * also enforces ordering), otherwise the hw might lose the new ring | |
608 | * register values. */ | |
0bc40be8 | 609 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
610 | |
611 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 612 | if (I915_READ_HEAD(engine)) |
95468892 | 613 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
614 | engine->name, I915_READ_HEAD(engine)); |
615 | I915_WRITE_HEAD(engine, 0); | |
616 | (void)I915_READ_HEAD(engine); | |
95468892 | 617 | |
0bc40be8 | 618 | I915_WRITE_CTL(engine, |
93b0a4e0 | 619 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 620 | | RING_VALID); |
8187a2b7 | 621 | |
8187a2b7 | 622 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
623 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
624 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
625 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 626 | DRM_ERROR("%s initialization failed " |
48e48a0b | 627 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
628 | engine->name, |
629 | I915_READ_CTL(engine), | |
630 | I915_READ_CTL(engine) & RING_VALID, | |
631 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
632 | I915_READ_START(engine), | |
633 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
634 | ret = -EIO; |
635 | goto out; | |
8187a2b7 ZN |
636 | } |
637 | ||
ebd0fd4b | 638 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
639 | ringbuf->head = I915_READ_HEAD(engine); |
640 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 641 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 642 | |
fc0768ce | 643 | intel_engine_init_hangcheck(engine); |
50f018df | 644 | |
b7884eb4 | 645 | out: |
59bad947 | 646 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
647 | |
648 | return ret; | |
8187a2b7 ZN |
649 | } |
650 | ||
9b1136d5 | 651 | void |
0bc40be8 | 652 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 653 | { |
0bc40be8 | 654 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
655 | return; |
656 | ||
c033666a | 657 | if (INTEL_GEN(engine->i915) >= 5) { |
0bc40be8 TU |
658 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
659 | i915_gem_object_ggtt_unpin(engine->scratch.obj); | |
9b1136d5 OM |
660 | } |
661 | ||
0bc40be8 TU |
662 | drm_gem_object_unreference(&engine->scratch.obj->base); |
663 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
664 | } |
665 | ||
666 | int | |
0bc40be8 | 667 | intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 668 | { |
c6df541c CW |
669 | int ret; |
670 | ||
0bc40be8 | 671 | WARN_ON(engine->scratch.obj); |
c6df541c | 672 | |
c033666a | 673 | engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096); |
fe3db79b | 674 | if (IS_ERR(engine->scratch.obj)) { |
c6df541c | 675 | DRM_ERROR("Failed to allocate seqno page\n"); |
fe3db79b CW |
676 | ret = PTR_ERR(engine->scratch.obj); |
677 | engine->scratch.obj = NULL; | |
c6df541c CW |
678 | goto err; |
679 | } | |
e4ffd173 | 680 | |
0bc40be8 TU |
681 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
682 | I915_CACHE_LLC); | |
a9cc726c DV |
683 | if (ret) |
684 | goto err_unref; | |
c6df541c | 685 | |
0bc40be8 | 686 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
c6df541c CW |
687 | if (ret) |
688 | goto err_unref; | |
689 | ||
0bc40be8 TU |
690 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
691 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); | |
692 | if (engine->scratch.cpu_page == NULL) { | |
56b085a0 | 693 | ret = -ENOMEM; |
c6df541c | 694 | goto err_unpin; |
56b085a0 | 695 | } |
c6df541c | 696 | |
2b1086cc | 697 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 698 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
699 | return 0; |
700 | ||
701 | err_unpin: | |
0bc40be8 | 702 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
c6df541c | 703 | err_unref: |
0bc40be8 | 704 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 705 | err: |
c6df541c CW |
706 | return ret; |
707 | } | |
708 | ||
e2be4faf | 709 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 710 | { |
4a570db5 | 711 | struct intel_engine_cs *engine = req->engine; |
c033666a CW |
712 | struct i915_workarounds *w = &req->i915->workarounds; |
713 | int ret, i; | |
888b5995 | 714 | |
02235808 | 715 | if (w->count == 0) |
7225342a | 716 | return 0; |
888b5995 | 717 | |
e2f80391 | 718 | engine->gpu_caches_dirty = true; |
4866d729 | 719 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
720 | if (ret) |
721 | return ret; | |
888b5995 | 722 | |
5fb9de1a | 723 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
724 | if (ret) |
725 | return ret; | |
726 | ||
e2f80391 | 727 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 728 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
729 | intel_ring_emit_reg(engine, w->reg[i].addr); |
730 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 731 | } |
e2f80391 | 732 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 733 | |
e2f80391 | 734 | intel_ring_advance(engine); |
7225342a | 735 | |
e2f80391 | 736 | engine->gpu_caches_dirty = true; |
4866d729 | 737 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
738 | if (ret) |
739 | return ret; | |
888b5995 | 740 | |
7225342a | 741 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 742 | |
7225342a | 743 | return 0; |
86d7f238 AS |
744 | } |
745 | ||
8753181e | 746 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
747 | { |
748 | int ret; | |
749 | ||
e2be4faf | 750 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
751 | if (ret != 0) |
752 | return ret; | |
753 | ||
be01363f | 754 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 755 | if (ret) |
e26e1b97 | 756 | return ret; |
8f0e2b9d | 757 | |
e26e1b97 | 758 | return 0; |
8f0e2b9d DV |
759 | } |
760 | ||
7225342a | 761 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
762 | i915_reg_t addr, |
763 | const u32 mask, const u32 val) | |
7225342a MK |
764 | { |
765 | const u32 idx = dev_priv->workarounds.count; | |
766 | ||
767 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
768 | return -ENOSPC; | |
769 | ||
770 | dev_priv->workarounds.reg[idx].addr = addr; | |
771 | dev_priv->workarounds.reg[idx].value = val; | |
772 | dev_priv->workarounds.reg[idx].mask = mask; | |
773 | ||
774 | dev_priv->workarounds.count++; | |
775 | ||
776 | return 0; | |
86d7f238 AS |
777 | } |
778 | ||
ca5a0fbd | 779 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 780 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
781 | if (r) \ |
782 | return r; \ | |
ca5a0fbd | 783 | } while (0) |
7225342a MK |
784 | |
785 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 786 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
787 | |
788 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 789 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 790 | |
98533251 | 791 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 792 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 793 | |
cf4b0de6 DL |
794 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
795 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 796 | |
cf4b0de6 | 797 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 798 | |
0bc40be8 TU |
799 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
800 | i915_reg_t reg) | |
33136b06 | 801 | { |
c033666a | 802 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 803 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 804 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
805 | |
806 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
807 | return -EINVAL; | |
808 | ||
0bc40be8 | 809 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 810 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 811 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
812 | |
813 | return 0; | |
814 | } | |
815 | ||
0bc40be8 | 816 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 817 | { |
c033666a | 818 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
819 | |
820 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 821 | |
717d84d6 AS |
822 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
823 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
824 | ||
d0581194 AS |
825 | /* WaDisablePartialInstShootdown:bdw,chv */ |
826 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
827 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
828 | ||
a340af58 AS |
829 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
830 | * workaround for for a possible hang in the unlikely event a TLB | |
831 | * invalidation occurs during a PSD flush. | |
832 | */ | |
833 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 834 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 835 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 836 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
837 | HDC_FORCE_NON_COHERENT); |
838 | ||
6def8fdd AS |
839 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
840 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
841 | * polygons in the same 8x4 pixel/sample area to be processed without | |
842 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
843 | * buffer." | |
844 | * | |
845 | * This optimization is off by default for BDW and CHV; turn it on. | |
846 | */ | |
847 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
848 | ||
48404636 AS |
849 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
850 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
851 | ||
7eebcde6 AS |
852 | /* |
853 | * BSpec recommends 8x4 when MSAA is used, | |
854 | * however in practice 16x4 seems fastest. | |
855 | * | |
856 | * Note that PS/WM thread counts depend on the WIZ hashing | |
857 | * disable bit, which we don't touch here, but it's good | |
858 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
859 | */ | |
860 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
861 | GEN6_WIZ_HASHING_MASK, | |
862 | GEN6_WIZ_HASHING_16x4); | |
863 | ||
e9a64ada AS |
864 | return 0; |
865 | } | |
866 | ||
0bc40be8 | 867 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 868 | { |
c033666a | 869 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 870 | int ret; |
86d7f238 | 871 | |
0bc40be8 | 872 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
873 | if (ret) |
874 | return ret; | |
875 | ||
101b376d | 876 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 877 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 878 | |
101b376d | 879 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
880 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
881 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 882 | |
7225342a MK |
883 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
884 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 885 | |
7225342a | 886 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
887 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
888 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 889 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 890 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 891 | |
86d7f238 AS |
892 | return 0; |
893 | } | |
894 | ||
0bc40be8 | 895 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 896 | { |
c033666a | 897 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 898 | int ret; |
00e1e623 | 899 | |
0bc40be8 | 900 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
901 | if (ret) |
902 | return ret; | |
903 | ||
00e1e623 | 904 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 905 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 906 | |
d60de81d KG |
907 | /* Improve HiZ throughput on CHV. */ |
908 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
909 | ||
7225342a MK |
910 | return 0; |
911 | } | |
912 | ||
0bc40be8 | 913 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 914 | { |
c033666a | 915 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 916 | int ret; |
ab0dfafe | 917 | |
a8ab5ed5 TG |
918 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
919 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
920 | ||
e5f81d65 | 921 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
922 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
923 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
924 | ||
e5f81d65 | 925 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
926 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
927 | ECOCHK_DIS_TLB); | |
928 | ||
e5f81d65 MK |
929 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
930 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 931 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 932 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
933 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
934 | ||
e5f81d65 | 935 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
936 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
937 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
938 | ||
e87a005d | 939 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
940 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
941 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
942 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
943 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 944 | |
e87a005d | 945 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
946 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
947 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
948 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
949 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
950 | /* |
951 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
952 | * but we do that in per ctx batchbuffer as there is an issue | |
953 | * with this register not getting restored on ctx restore | |
954 | */ | |
183c6dac DL |
955 | } |
956 | ||
e5f81d65 MK |
957 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
958 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
959 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
960 | GEN9_ENABLE_YV12_BUGFIX | | |
961 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 962 | |
e5f81d65 MK |
963 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
964 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
965 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
966 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 967 | |
e5f81d65 | 968 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
969 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
970 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
971 | ||
5a2ae95e | 972 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
973 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
974 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
975 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
976 | PIXEL_MASK_CAMMING_DISABLE); | |
977 | ||
5b0e3659 MK |
978 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
979 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
980 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
981 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 982 | |
bbaefe72 MK |
983 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
984 | * both tied to WaForceContextSaveRestoreNonCoherent | |
985 | * in some hsds for skl. We keep the tie for all gen9. The | |
986 | * documentation is a bit hazy and so we want to get common behaviour, | |
987 | * even though there is no clear evidence we would need both on kbl/bxt. | |
988 | * This area has been source of system hangs so we play it safe | |
989 | * and mimic the skl regardless of what bspec says. | |
990 | * | |
991 | * Use Force Non-Coherent whenever executing a 3D context. This | |
992 | * is a workaround for a possible hang in the unlikely event | |
993 | * a TLB invalidation occurs during a PSD flush. | |
994 | */ | |
995 | ||
996 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
997 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
998 | HDC_FORCE_NON_COHERENT); | |
999 | ||
1000 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
1001 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1002 | BDW_DISABLE_HDC_INVALIDATION); | |
1003 | ||
e5f81d65 MK |
1004 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
1005 | if (IS_SKYLAKE(dev_priv) || | |
1006 | IS_KABYLAKE(dev_priv) || | |
1007 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
1008 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
1009 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 1010 | |
e5f81d65 | 1011 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
1012 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
1013 | ||
e5f81d65 | 1014 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
1015 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
1016 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
1017 | ||
6bb62855 | 1018 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
1019 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
1020 | if (ret) | |
1021 | return ret; | |
1022 | ||
e5f81d65 | 1023 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 1024 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1025 | if (ret) |
1026 | return ret; | |
1027 | ||
e5f81d65 | 1028 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 1029 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1030 | if (ret) |
1031 | return ret; | |
1032 | ||
3b106531 HN |
1033 | return 0; |
1034 | } | |
1035 | ||
0bc40be8 | 1036 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1037 | { |
c033666a | 1038 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
1039 | u8 vals[3] = { 0, 0, 0 }; |
1040 | unsigned int i; | |
1041 | ||
1042 | for (i = 0; i < 3; i++) { | |
1043 | u8 ss; | |
1044 | ||
1045 | /* | |
1046 | * Only consider slices where one, and only one, subslice has 7 | |
1047 | * EUs | |
1048 | */ | |
a4d8a0fe | 1049 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1050 | continue; |
1051 | ||
1052 | /* | |
1053 | * subslice_7eu[i] != 0 (because of the check above) and | |
1054 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1055 | * | |
1056 | * -> 0 <= ss <= 3; | |
1057 | */ | |
1058 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1059 | vals[i] = 3 - ss; | |
1060 | } | |
1061 | ||
1062 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1063 | return 0; | |
1064 | ||
1065 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1066 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1067 | GEN9_IZ_HASHING_MASK(2) | | |
1068 | GEN9_IZ_HASHING_MASK(1) | | |
1069 | GEN9_IZ_HASHING_MASK(0), | |
1070 | GEN9_IZ_HASHING(2, vals[2]) | | |
1071 | GEN9_IZ_HASHING(1, vals[1]) | | |
1072 | GEN9_IZ_HASHING(0, vals[0])); | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
0bc40be8 | 1077 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1078 | { |
c033666a | 1079 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1080 | int ret; |
d0bbbc4f | 1081 | |
0bc40be8 | 1082 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1083 | if (ret) |
1084 | return ret; | |
8d205494 | 1085 | |
a78536e7 AS |
1086 | /* |
1087 | * Actual WA is to disable percontext preemption granularity control | |
1088 | * until D0 which is the default case so this is equivalent to | |
1089 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1090 | */ | |
c033666a | 1091 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
1092 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1093 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1094 | } | |
1095 | ||
71dce58c | 1096 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1097 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1098 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1099 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1100 | } | |
1101 | ||
1102 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1103 | * involving this register should also be added to WA batch as required. | |
1104 | */ | |
c033666a | 1105 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1106 | /* WaDisableLSQCROPERFforOCL:skl */ |
1107 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1108 | GEN8_LQSC_RO_PERF_DIS); | |
1109 | ||
1110 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1111 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1112 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1113 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1114 | } | |
1115 | ||
d0bbbc4f | 1116 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1117 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1118 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1119 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1120 | ||
e87a005d | 1121 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1122 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1123 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1124 | HDC_FENCE_DEST_SLM_DISABLE | | |
1125 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1126 | ||
9bd9dfb4 | 1127 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1128 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1129 | WA_SET_BIT_MASKED( |
1130 | GEN7_HALF_SLICE_CHICKEN1, | |
1131 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1132 | |
eee8efb0 MK |
1133 | /* WaDisableGafsUnitClkGating:skl */ |
1134 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1135 | ||
6107497e | 1136 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1137 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1138 | if (ret) |
1139 | return ret; | |
1140 | ||
0bc40be8 | 1141 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1142 | } |
1143 | ||
0bc40be8 | 1144 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1145 | { |
c033666a | 1146 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1147 | int ret; |
dfb601e6 | 1148 | |
0bc40be8 | 1149 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1150 | if (ret) |
1151 | return ret; | |
cae0437f | 1152 | |
9c4cbf82 MK |
1153 | /* WaStoreMultiplePTEenable:bxt */ |
1154 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1155 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1156 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1157 | ||
1158 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1159 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1160 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1161 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1162 | } | |
1163 | ||
dfb601e6 NH |
1164 | /* WaDisableThreadStallDopClockGating:bxt */ |
1165 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1166 | STALL_DOP_GATING_DISABLE); | |
1167 | ||
780f0aeb | 1168 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1169 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1170 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1171 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1172 | } | |
1173 | ||
983b4b9d | 1174 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1175 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1176 | WA_SET_BIT_MASKED( |
1177 | GEN7_HALF_SLICE_CHICKEN1, | |
1178 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1179 | } | |
1180 | ||
2c8580e4 AS |
1181 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1182 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1183 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1184 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1185 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1186 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1187 | if (ret) |
1188 | return ret; | |
a786d53a | 1189 | |
0bc40be8 | 1190 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1191 | if (ret) |
1192 | return ret; | |
2c8580e4 AS |
1193 | } |
1194 | ||
050fc465 | 1195 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1196 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1197 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1198 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1199 | |
ad2bdb44 MK |
1200 | /* WaInsertDummyPushConstPs:bxt */ |
1201 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1202 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1203 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1204 | ||
cae0437f NH |
1205 | return 0; |
1206 | } | |
1207 | ||
e5f81d65 MK |
1208 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1209 | { | |
e587f6cb | 1210 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1211 | int ret; |
1212 | ||
1213 | ret = gen9_init_workarounds(engine); | |
1214 | if (ret) | |
1215 | return ret; | |
1216 | ||
e587f6cb MK |
1217 | /* WaEnableGapsTsvCreditFix:kbl */ |
1218 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1219 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1220 | ||
c0b730d5 MK |
1221 | /* WaDisableDynamicCreditSharing:kbl */ |
1222 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1223 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1224 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1225 | ||
8401d42f MK |
1226 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1227 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1228 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1229 | HDC_FENCE_DEST_SLM_DISABLE); | |
1230 | ||
fe905819 MK |
1231 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1232 | * involving this register should also be added to WA batch as required. | |
1233 | */ | |
1234 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1235 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1236 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1237 | GEN8_LQSC_RO_PERF_DIS); | |
1238 | ||
ad2bdb44 MK |
1239 | /* WaInsertDummyPushConstPs:kbl */ |
1240 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1241 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1242 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1243 | ||
4de5d7cc MK |
1244 | /* WaDisableGafsUnitClkGating:kbl */ |
1245 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1246 | ||
954337aa MK |
1247 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1248 | WA_SET_BIT_MASKED( | |
1249 | GEN7_HALF_SLICE_CHICKEN1, | |
1250 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1251 | ||
fe905819 MK |
1252 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1253 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1254 | if (ret) | |
1255 | return ret; | |
1256 | ||
e5f81d65 MK |
1257 | return 0; |
1258 | } | |
1259 | ||
0bc40be8 | 1260 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1261 | { |
c033666a | 1262 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1263 | |
0bc40be8 | 1264 | WARN_ON(engine->id != RCS); |
7225342a MK |
1265 | |
1266 | dev_priv->workarounds.count = 0; | |
33136b06 | 1267 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1268 | |
c033666a | 1269 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1270 | return bdw_init_workarounds(engine); |
7225342a | 1271 | |
c033666a | 1272 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1273 | return chv_init_workarounds(engine); |
00e1e623 | 1274 | |
c033666a | 1275 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1276 | return skl_init_workarounds(engine); |
cae0437f | 1277 | |
c033666a | 1278 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1279 | return bxt_init_workarounds(engine); |
3b106531 | 1280 | |
e5f81d65 MK |
1281 | if (IS_KABYLAKE(dev_priv)) |
1282 | return kbl_init_workarounds(engine); | |
1283 | ||
00e1e623 VS |
1284 | return 0; |
1285 | } | |
1286 | ||
0bc40be8 | 1287 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1288 | { |
c033666a | 1289 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1290 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1291 | if (ret) |
1292 | return ret; | |
a69ffdbf | 1293 | |
61a563a2 | 1294 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1295 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1296 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1297 | |
1298 | /* We need to disable the AsyncFlip performance optimisations in order | |
1299 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1300 | * programmed to '1' on all products. | |
8693a824 | 1301 | * |
2441f877 | 1302 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1303 | */ |
ac657f64 | 1304 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1305 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1306 | ||
f05bb0c7 | 1307 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1308 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1309 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1310 | I915_WRITE(GFX_MODE, |
aa83e30d | 1311 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1312 | |
01fa0302 | 1313 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1314 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1315 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1316 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1317 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1318 | |
c033666a | 1319 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1320 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1321 | * "If this bit is set, STCunit will have LRA as replacement | |
1322 | * policy. [...] This bit must be reset. LRA replacement | |
1323 | * policy is not supported." | |
1324 | */ | |
1325 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1326 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1327 | } |
1328 | ||
ac657f64 | 1329 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1330 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1331 | |
c033666a CW |
1332 | if (HAS_L3_DPF(dev_priv)) |
1333 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv)); | |
15b9f80e | 1334 | |
0bc40be8 | 1335 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1336 | } |
1337 | ||
0bc40be8 | 1338 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1339 | { |
c033666a | 1340 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a BW |
1341 | |
1342 | if (dev_priv->semaphore_obj) { | |
1343 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1344 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1345 | dev_priv->semaphore_obj = NULL; | |
1346 | } | |
b45305fc | 1347 | |
0bc40be8 | 1348 | intel_fini_pipe_control(engine); |
c6df541c CW |
1349 | } |
1350 | ||
f7169687 | 1351 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1352 | unsigned int num_dwords) |
1353 | { | |
1354 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1355 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1356 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1357 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1358 | enum intel_engine_id id; |
1359 | int ret, num_rings; | |
3e78998a | 1360 | |
c033666a | 1361 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1362 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1363 | #undef MBOX_UPDATE_DWORDS | |
1364 | ||
5fb9de1a | 1365 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1366 | if (ret) |
1367 | return ret; | |
1368 | ||
c3232b18 | 1369 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1370 | u32 seqno; |
c3232b18 | 1371 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1372 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1373 | continue; | |
1374 | ||
f7169687 | 1375 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1376 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1377 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1378 | PIPE_CONTROL_QW_WRITE | | |
f9a4ea35 | 1379 | PIPE_CONTROL_CS_STALL); |
3e78998a BW |
1380 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
1381 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1382 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1383 | intel_ring_emit(signaller, 0); |
1384 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
215a7e32 | 1385 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1386 | intel_ring_emit(signaller, 0); |
1387 | } | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
f7169687 | 1392 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1393 | unsigned int num_dwords) |
1394 | { | |
1395 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1396 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1397 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1398 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1399 | enum intel_engine_id id; |
1400 | int ret, num_rings; | |
3e78998a | 1401 | |
c033666a | 1402 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1403 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1404 | #undef MBOX_UPDATE_DWORDS | |
1405 | ||
5fb9de1a | 1406 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1407 | if (ret) |
1408 | return ret; | |
1409 | ||
c3232b18 | 1410 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1411 | u32 seqno; |
c3232b18 | 1412 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1413 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1414 | continue; | |
1415 | ||
f7169687 | 1416 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1417 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1418 | MI_FLUSH_DW_OP_STOREDW); | |
1419 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1420 | MI_FLUSH_DW_USE_GTT); | |
1421 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1422 | intel_ring_emit(signaller, seqno); |
3e78998a | 1423 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
215a7e32 | 1424 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1425 | intel_ring_emit(signaller, 0); |
1426 | } | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
f7169687 | 1431 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1432 | unsigned int num_dwords) |
1ec14ad3 | 1433 | { |
4a570db5 | 1434 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1435 | struct drm_i915_private *dev_priv = signaller_req->i915; |
a4872ba6 | 1436 | struct intel_engine_cs *useless; |
c3232b18 DG |
1437 | enum intel_engine_id id; |
1438 | int ret, num_rings; | |
78325f2d | 1439 | |
a1444b79 | 1440 | #define MBOX_UPDATE_DWORDS 3 |
c033666a | 1441 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
a1444b79 BW |
1442 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
1443 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1444 | |
5fb9de1a | 1445 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1446 | if (ret) |
1447 | return ret; | |
024a43e1 | 1448 | |
c3232b18 DG |
1449 | for_each_engine_id(useless, dev_priv, id) { |
1450 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1451 | |
1452 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1453 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1454 | |
78325f2d | 1455 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1456 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1457 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1458 | } |
1459 | } | |
024a43e1 | 1460 | |
a1444b79 BW |
1461 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1462 | if (num_rings % 2 == 0) | |
1463 | intel_ring_emit(signaller, MI_NOOP); | |
1464 | ||
024a43e1 | 1465 | return 0; |
1ec14ad3 CW |
1466 | } |
1467 | ||
c8c99b0f BW |
1468 | /** |
1469 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1470 | * |
1471 | * @request - request to write to the ring | |
c8c99b0f BW |
1472 | * |
1473 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1474 | * This acts like a signal in the canonical semaphore. | |
1475 | */ | |
1ec14ad3 | 1476 | static int |
ee044a88 | 1477 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1478 | { |
4a570db5 | 1479 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1480 | int ret; |
52ed2325 | 1481 | |
e2f80391 TU |
1482 | if (engine->semaphore.signal) |
1483 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1484 | else |
5fb9de1a | 1485 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1486 | |
1ec14ad3 CW |
1487 | if (ret) |
1488 | return ret; | |
1489 | ||
e2f80391 TU |
1490 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1491 | intel_ring_emit(engine, | |
1492 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1493 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1494 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1495 | __intel_ring_advance(engine); | |
1ec14ad3 | 1496 | |
1ec14ad3 CW |
1497 | return 0; |
1498 | } | |
1499 | ||
a58c01aa CW |
1500 | static int |
1501 | gen8_render_add_request(struct drm_i915_gem_request *req) | |
1502 | { | |
1503 | struct intel_engine_cs *engine = req->engine; | |
1504 | int ret; | |
1505 | ||
1506 | if (engine->semaphore.signal) | |
1507 | ret = engine->semaphore.signal(req, 8); | |
1508 | else | |
1509 | ret = intel_ring_begin(req, 8); | |
1510 | if (ret) | |
1511 | return ret; | |
1512 | ||
1513 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); | |
1514 | intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1515 | PIPE_CONTROL_CS_STALL | | |
1516 | PIPE_CONTROL_QW_WRITE)); | |
1517 | intel_ring_emit(engine, intel_hws_seqno_address(req->engine)); | |
1518 | intel_ring_emit(engine, 0); | |
1519 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1520 | /* We're thrashing one dword of HWS. */ | |
1521 | intel_ring_emit(engine, 0); | |
1522 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1523 | intel_ring_emit(engine, MI_NOOP); | |
1524 | __intel_ring_advance(engine); | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
c033666a | 1529 | static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv, |
f72b3435 MK |
1530 | u32 seqno) |
1531 | { | |
f72b3435 MK |
1532 | return dev_priv->last_seqno < seqno; |
1533 | } | |
1534 | ||
c8c99b0f BW |
1535 | /** |
1536 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1537 | * | |
1538 | * @waiter - ring that is waiting | |
1539 | * @signaller - ring which has, or will signal | |
1540 | * @seqno - seqno which the waiter will block on | |
1541 | */ | |
5ee426ca BW |
1542 | |
1543 | static int | |
599d924c | 1544 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1545 | struct intel_engine_cs *signaller, |
1546 | u32 seqno) | |
1547 | { | |
4a570db5 | 1548 | struct intel_engine_cs *waiter = waiter_req->engine; |
c033666a | 1549 | struct drm_i915_private *dev_priv = waiter_req->i915; |
6ef48d7f | 1550 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1551 | int ret; |
1552 | ||
5fb9de1a | 1553 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1554 | if (ret) |
1555 | return ret; | |
1556 | ||
1557 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1558 | MI_SEMAPHORE_GLOBAL_GTT | | |
1559 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1560 | intel_ring_emit(waiter, seqno); | |
1561 | intel_ring_emit(waiter, | |
1562 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1563 | intel_ring_emit(waiter, | |
1564 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1565 | intel_ring_advance(waiter); | |
6ef48d7f CW |
1566 | |
1567 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1568 | * pagetables and we must reload them before executing the batch. | |
1569 | * We do this on the i915_switch_context() following the wait and | |
1570 | * before the dispatch. | |
1571 | */ | |
1572 | ppgtt = waiter_req->ctx->ppgtt; | |
1573 | if (ppgtt && waiter_req->engine->id != RCS) | |
1574 | ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); | |
5ee426ca BW |
1575 | return 0; |
1576 | } | |
1577 | ||
c8c99b0f | 1578 | static int |
599d924c | 1579 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1580 | struct intel_engine_cs *signaller, |
686cb5f9 | 1581 | u32 seqno) |
1ec14ad3 | 1582 | { |
4a570db5 | 1583 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1584 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1585 | MI_SEMAPHORE_COMPARE | | |
1586 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1587 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1588 | int ret; | |
1ec14ad3 | 1589 | |
1500f7ea BW |
1590 | /* Throughout all of the GEM code, seqno passed implies our current |
1591 | * seqno is >= the last seqno executed. However for hardware the | |
1592 | * comparison is strictly greater than. | |
1593 | */ | |
1594 | seqno -= 1; | |
1595 | ||
ebc348b2 | 1596 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1597 | |
5fb9de1a | 1598 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1599 | if (ret) |
1600 | return ret; | |
1601 | ||
f72b3435 | 1602 | /* If seqno wrap happened, omit the wait with no-ops */ |
c033666a | 1603 | if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) { |
ebc348b2 | 1604 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1605 | intel_ring_emit(waiter, seqno); |
1606 | intel_ring_emit(waiter, 0); | |
1607 | intel_ring_emit(waiter, MI_NOOP); | |
1608 | } else { | |
1609 | intel_ring_emit(waiter, MI_NOOP); | |
1610 | intel_ring_emit(waiter, MI_NOOP); | |
1611 | intel_ring_emit(waiter, MI_NOOP); | |
1612 | intel_ring_emit(waiter, MI_NOOP); | |
1613 | } | |
c8c99b0f | 1614 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1615 | |
1616 | return 0; | |
1617 | } | |
1618 | ||
c6df541c CW |
1619 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1620 | do { \ | |
fcbc34e4 KG |
1621 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1622 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1623 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1624 | intel_ring_emit(ring__, 0); \ | |
1625 | intel_ring_emit(ring__, 0); \ | |
1626 | } while (0) | |
1627 | ||
1628 | static int | |
ee044a88 | 1629 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1630 | { |
4a570db5 | 1631 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1632 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1633 | int ret; |
1634 | ||
1635 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1636 | * incoherent with writes to memory, i.e. completely fubar, | |
1637 | * so we need to use PIPE_NOTIFY instead. | |
1638 | * | |
1639 | * However, we also need to workaround the qword write | |
1640 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1641 | * memory before requesting an interrupt. | |
1642 | */ | |
5fb9de1a | 1643 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1644 | if (ret) |
1645 | return ret; | |
1646 | ||
e2f80391 TU |
1647 | intel_ring_emit(engine, |
1648 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1649 | PIPE_CONTROL_WRITE_FLUSH | |
1650 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
e2f80391 TU |
1651 | intel_ring_emit(engine, |
1652 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1653 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1654 | intel_ring_emit(engine, 0); | |
1655 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1656 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1657 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1658 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1659 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1660 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1661 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1662 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1663 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1664 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1665 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1666 | |
e2f80391 TU |
1667 | intel_ring_emit(engine, |
1668 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1669 | PIPE_CONTROL_WRITE_FLUSH | |
1670 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1671 | PIPE_CONTROL_NOTIFY); |
e2f80391 TU |
1672 | intel_ring_emit(engine, |
1673 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1674 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1675 | intel_ring_emit(engine, 0); | |
1676 | __intel_ring_advance(engine); | |
c6df541c | 1677 | |
c6df541c CW |
1678 | return 0; |
1679 | } | |
1680 | ||
c04e0f3b CW |
1681 | static void |
1682 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1683 | { |
c033666a | 1684 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1685 | |
4cd53c0c DV |
1686 | /* Workaround to force correct ordering between irq and seqno writes on |
1687 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1688 | * ACTHD) before reading the status page. |
1689 | * | |
1690 | * Note that this effectively stalls the read by the time it takes to | |
1691 | * do a memory transaction, which more or less ensures that the write | |
1692 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1693 | * Alternatively we could delay the interrupt from the CS ring to give | |
1694 | * the write time to land, but that would incur a delay after every | |
1695 | * batch i.e. much more frequent than a delay when waiting for the | |
1696 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1697 | * |
1698 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1699 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1700 | */ |
bcbdb6d0 | 1701 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1702 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1703 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1704 | } |
1705 | ||
8187a2b7 | 1706 | static u32 |
c04e0f3b | 1707 | ring_get_seqno(struct intel_engine_cs *engine) |
8187a2b7 | 1708 | { |
0bc40be8 | 1709 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
1ec14ad3 CW |
1710 | } |
1711 | ||
b70ec5bf | 1712 | static void |
0bc40be8 | 1713 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1714 | { |
0bc40be8 | 1715 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
b70ec5bf MK |
1716 | } |
1717 | ||
c6df541c | 1718 | static u32 |
c04e0f3b | 1719 | pc_render_get_seqno(struct intel_engine_cs *engine) |
c6df541c | 1720 | { |
0bc40be8 | 1721 | return engine->scratch.cpu_page[0]; |
c6df541c CW |
1722 | } |
1723 | ||
b70ec5bf | 1724 | static void |
0bc40be8 | 1725 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1726 | { |
0bc40be8 | 1727 | engine->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1728 | } |
1729 | ||
e48d8634 | 1730 | static bool |
0bc40be8 | 1731 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1732 | { |
c033666a | 1733 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1734 | unsigned long flags; |
e48d8634 | 1735 | |
7cd512f1 | 1736 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1737 | return false; |
1738 | ||
7338aefa | 1739 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1740 | if (engine->irq_refcount++ == 0) |
1741 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1742 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1743 | |
1744 | return true; | |
1745 | } | |
1746 | ||
1747 | static void | |
0bc40be8 | 1748 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1749 | { |
c033666a | 1750 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1751 | unsigned long flags; |
e48d8634 | 1752 | |
7338aefa | 1753 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1754 | if (--engine->irq_refcount == 0) |
1755 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1756 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1757 | } |
1758 | ||
b13c2b96 | 1759 | static bool |
0bc40be8 | 1760 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1761 | { |
c033666a | 1762 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1763 | unsigned long flags; |
62fdfeaf | 1764 | |
7cd512f1 | 1765 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1766 | return false; |
1767 | ||
7338aefa | 1768 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1769 | if (engine->irq_refcount++ == 0) { |
1770 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1771 | I915_WRITE(IMR, dev_priv->irq_mask); |
1772 | POSTING_READ(IMR); | |
1773 | } | |
7338aefa | 1774 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1775 | |
1776 | return true; | |
62fdfeaf EA |
1777 | } |
1778 | ||
8187a2b7 | 1779 | static void |
0bc40be8 | 1780 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1781 | { |
c033666a | 1782 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1783 | unsigned long flags; |
62fdfeaf | 1784 | |
7338aefa | 1785 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1786 | if (--engine->irq_refcount == 0) { |
1787 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1788 | I915_WRITE(IMR, dev_priv->irq_mask); |
1789 | POSTING_READ(IMR); | |
1790 | } | |
7338aefa | 1791 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1792 | } |
1793 | ||
c2798b19 | 1794 | static bool |
0bc40be8 | 1795 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1796 | { |
c033666a | 1797 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1798 | unsigned long flags; |
c2798b19 | 1799 | |
7cd512f1 | 1800 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1801 | return false; |
1802 | ||
7338aefa | 1803 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1804 | if (engine->irq_refcount++ == 0) { |
1805 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1806 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1807 | POSTING_READ16(IMR); | |
1808 | } | |
7338aefa | 1809 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1810 | |
1811 | return true; | |
1812 | } | |
1813 | ||
1814 | static void | |
0bc40be8 | 1815 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1816 | { |
c033666a | 1817 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1818 | unsigned long flags; |
c2798b19 | 1819 | |
7338aefa | 1820 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1821 | if (--engine->irq_refcount == 0) { |
1822 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1823 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1824 | POSTING_READ16(IMR); | |
1825 | } | |
7338aefa | 1826 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1827 | } |
1828 | ||
b72f3acb | 1829 | static int |
a84c3ae1 | 1830 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1831 | u32 invalidate_domains, |
1832 | u32 flush_domains) | |
d1b851fc | 1833 | { |
4a570db5 | 1834 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1835 | int ret; |
1836 | ||
5fb9de1a | 1837 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1838 | if (ret) |
1839 | return ret; | |
1840 | ||
e2f80391 TU |
1841 | intel_ring_emit(engine, MI_FLUSH); |
1842 | intel_ring_emit(engine, MI_NOOP); | |
1843 | intel_ring_advance(engine); | |
b72f3acb | 1844 | return 0; |
d1b851fc ZN |
1845 | } |
1846 | ||
3cce469c | 1847 | static int |
ee044a88 | 1848 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1849 | { |
4a570db5 | 1850 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1851 | int ret; |
1852 | ||
5fb9de1a | 1853 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1854 | if (ret) |
1855 | return ret; | |
6f392d54 | 1856 | |
e2f80391 TU |
1857 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1858 | intel_ring_emit(engine, | |
1859 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1860 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1861 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1862 | __intel_ring_advance(engine); | |
d1b851fc | 1863 | |
3cce469c | 1864 | return 0; |
d1b851fc ZN |
1865 | } |
1866 | ||
0f46832f | 1867 | static bool |
0bc40be8 | 1868 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1869 | { |
c033666a | 1870 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1871 | unsigned long flags; |
0f46832f | 1872 | |
7cd512f1 DV |
1873 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1874 | return false; | |
0f46832f | 1875 | |
7338aefa | 1876 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 | 1877 | if (engine->irq_refcount++ == 0) { |
c033666a | 1878 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) |
0bc40be8 TU |
1879 | I915_WRITE_IMR(engine, |
1880 | ~(engine->irq_enable_mask | | |
c033666a | 1881 | GT_PARITY_ERROR(dev_priv))); |
15b9f80e | 1882 | else |
0bc40be8 TU |
1883 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1884 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1885 | } |
7338aefa | 1886 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1887 | |
1888 | return true; | |
1889 | } | |
1890 | ||
1891 | static void | |
0bc40be8 | 1892 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1893 | { |
c033666a | 1894 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1895 | unsigned long flags; |
0f46832f | 1896 | |
7338aefa | 1897 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 | 1898 | if (--engine->irq_refcount == 0) { |
c033666a CW |
1899 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) |
1900 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv)); | |
15b9f80e | 1901 | else |
0bc40be8 TU |
1902 | I915_WRITE_IMR(engine, ~0); |
1903 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1904 | } |
7338aefa | 1905 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1906 | } |
1907 | ||
a19d2933 | 1908 | static bool |
0bc40be8 | 1909 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1910 | { |
c033666a | 1911 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 BW |
1912 | unsigned long flags; |
1913 | ||
7cd512f1 | 1914 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1915 | return false; |
1916 | ||
59cdb63d | 1917 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1918 | if (engine->irq_refcount++ == 0) { |
1919 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1920 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1921 | } |
59cdb63d | 1922 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1923 | |
1924 | return true; | |
1925 | } | |
1926 | ||
1927 | static void | |
0bc40be8 | 1928 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1929 | { |
c033666a | 1930 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 BW |
1931 | unsigned long flags; |
1932 | ||
59cdb63d | 1933 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1934 | if (--engine->irq_refcount == 0) { |
1935 | I915_WRITE_IMR(engine, ~0); | |
1936 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1937 | } |
59cdb63d | 1938 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1939 | } |
1940 | ||
abd58f01 | 1941 | static bool |
0bc40be8 | 1942 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1943 | { |
c033666a | 1944 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 BW |
1945 | unsigned long flags; |
1946 | ||
7cd512f1 | 1947 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1948 | return false; |
1949 | ||
1950 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 | 1951 | if (engine->irq_refcount++ == 0) { |
c033666a | 1952 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) { |
0bc40be8 TU |
1953 | I915_WRITE_IMR(engine, |
1954 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1955 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1956 | } else { | |
0bc40be8 | 1957 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1958 | } |
0bc40be8 | 1959 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1960 | } |
1961 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1962 | ||
1963 | return true; | |
1964 | } | |
1965 | ||
1966 | static void | |
0bc40be8 | 1967 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1968 | { |
c033666a | 1969 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 BW |
1970 | unsigned long flags; |
1971 | ||
1972 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 | 1973 | if (--engine->irq_refcount == 0) { |
c033666a | 1974 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) { |
0bc40be8 | 1975 | I915_WRITE_IMR(engine, |
abd58f01 BW |
1976 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1977 | } else { | |
0bc40be8 | 1978 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1979 | } |
0bc40be8 | 1980 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1981 | } |
1982 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1983 | } | |
1984 | ||
d1b851fc | 1985 | static int |
53fddaf7 | 1986 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1987 | u64 offset, u32 length, |
8e004efc | 1988 | unsigned dispatch_flags) |
d1b851fc | 1989 | { |
4a570db5 | 1990 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1991 | int ret; |
78501eac | 1992 | |
5fb9de1a | 1993 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1994 | if (ret) |
1995 | return ret; | |
1996 | ||
e2f80391 | 1997 | intel_ring_emit(engine, |
65f56876 CW |
1998 | MI_BATCH_BUFFER_START | |
1999 | MI_BATCH_GTT | | |
8e004efc JH |
2000 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2001 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
2002 | intel_ring_emit(engine, offset); |
2003 | intel_ring_advance(engine); | |
78501eac | 2004 | |
d1b851fc ZN |
2005 | return 0; |
2006 | } | |
2007 | ||
b45305fc DV |
2008 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
2009 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
2010 | #define I830_TLB_ENTRIES (2) |
2011 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 2012 | static int |
53fddaf7 | 2013 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2014 | u64 offset, u32 len, |
2015 | unsigned dispatch_flags) | |
62fdfeaf | 2016 | { |
4a570db5 | 2017 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2018 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 2019 | int ret; |
62fdfeaf | 2020 | |
5fb9de1a | 2021 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
2022 | if (ret) |
2023 | return ret; | |
62fdfeaf | 2024 | |
c4d69da1 | 2025 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
2026 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
2027 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
2028 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
2029 | intel_ring_emit(engine, cs_offset); | |
2030 | intel_ring_emit(engine, 0xdeadbeef); | |
2031 | intel_ring_emit(engine, MI_NOOP); | |
2032 | intel_ring_advance(engine); | |
b45305fc | 2033 | |
8e004efc | 2034 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
2035 | if (len > I830_BATCH_LIMIT) |
2036 | return -ENOSPC; | |
2037 | ||
5fb9de1a | 2038 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
2039 | if (ret) |
2040 | return ret; | |
c4d69da1 CW |
2041 | |
2042 | /* Blit the batch (which has now all relocs applied) to the | |
2043 | * stable batch scratch bo area (so that the CS never | |
2044 | * stumbles over its tlb invalidation bug) ... | |
2045 | */ | |
e2f80391 TU |
2046 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
2047 | intel_ring_emit(engine, | |
2048 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
2049 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
2050 | intel_ring_emit(engine, cs_offset); | |
2051 | intel_ring_emit(engine, 4096); | |
2052 | intel_ring_emit(engine, offset); | |
2053 | ||
2054 | intel_ring_emit(engine, MI_FLUSH); | |
2055 | intel_ring_emit(engine, MI_NOOP); | |
2056 | intel_ring_advance(engine); | |
b45305fc DV |
2057 | |
2058 | /* ... and execute it. */ | |
c4d69da1 | 2059 | offset = cs_offset; |
b45305fc | 2060 | } |
e1f99ce6 | 2061 | |
9d611c03 | 2062 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
2063 | if (ret) |
2064 | return ret; | |
2065 | ||
e2f80391 TU |
2066 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2067 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2068 | 0 : MI_BATCH_NON_SECURE)); | |
2069 | intel_ring_advance(engine); | |
c4d69da1 | 2070 | |
fb3256da DV |
2071 | return 0; |
2072 | } | |
2073 | ||
2074 | static int | |
53fddaf7 | 2075 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2076 | u64 offset, u32 len, |
8e004efc | 2077 | unsigned dispatch_flags) |
fb3256da | 2078 | { |
4a570db5 | 2079 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
2080 | int ret; |
2081 | ||
5fb9de1a | 2082 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
2083 | if (ret) |
2084 | return ret; | |
2085 | ||
e2f80391 TU |
2086 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2087 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2088 | 0 : MI_BATCH_NON_SECURE)); | |
2089 | intel_ring_advance(engine); | |
62fdfeaf | 2090 | |
62fdfeaf EA |
2091 | return 0; |
2092 | } | |
2093 | ||
0bc40be8 | 2094 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 2095 | { |
c033666a | 2096 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
2097 | |
2098 | if (!dev_priv->status_page_dmah) | |
2099 | return; | |
2100 | ||
c033666a | 2101 | drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah); |
0bc40be8 | 2102 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
2103 | } |
2104 | ||
0bc40be8 | 2105 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2106 | { |
05394f39 | 2107 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2108 | |
0bc40be8 | 2109 | obj = engine->status_page.obj; |
8187a2b7 | 2110 | if (obj == NULL) |
62fdfeaf | 2111 | return; |
62fdfeaf | 2112 | |
9da3da66 | 2113 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2114 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2115 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2116 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2117 | } |
2118 | ||
0bc40be8 | 2119 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2120 | { |
0bc40be8 | 2121 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2122 | |
7d3fdfff | 2123 | if (obj == NULL) { |
1f767e02 | 2124 | unsigned flags; |
e3efda49 | 2125 | int ret; |
e4ffd173 | 2126 | |
c033666a | 2127 | obj = i915_gem_object_create(engine->i915->dev, 4096); |
fe3db79b | 2128 | if (IS_ERR(obj)) { |
e3efda49 | 2129 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 2130 | return PTR_ERR(obj); |
e3efda49 | 2131 | } |
62fdfeaf | 2132 | |
e3efda49 CW |
2133 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2134 | if (ret) | |
2135 | goto err_unref; | |
2136 | ||
1f767e02 | 2137 | flags = 0; |
c033666a | 2138 | if (!HAS_LLC(engine->i915)) |
1f767e02 CW |
2139 | /* On g33, we cannot place HWS above 256MiB, so |
2140 | * restrict its pinning to the low mappable arena. | |
2141 | * Though this restriction is not documented for | |
2142 | * gen4, gen5, or byt, they also behave similarly | |
2143 | * and hang if the HWS is placed at the top of the | |
2144 | * GTT. To generalise, it appears that all !llc | |
2145 | * platforms have issues with us placing the HWS | |
2146 | * above the mappable region (even though we never | |
2147 | * actualy map it). | |
2148 | */ | |
2149 | flags |= PIN_MAPPABLE; | |
2150 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2151 | if (ret) { |
2152 | err_unref: | |
2153 | drm_gem_object_unreference(&obj->base); | |
2154 | return ret; | |
2155 | } | |
2156 | ||
0bc40be8 | 2157 | engine->status_page.obj = obj; |
e3efda49 | 2158 | } |
62fdfeaf | 2159 | |
0bc40be8 TU |
2160 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2161 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2162 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2163 | |
8187a2b7 | 2164 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2165 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2166 | |
2167 | return 0; | |
62fdfeaf EA |
2168 | } |
2169 | ||
0bc40be8 | 2170 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2171 | { |
c033666a | 2172 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 CW |
2173 | |
2174 | if (!dev_priv->status_page_dmah) { | |
2175 | dev_priv->status_page_dmah = | |
c033666a | 2176 | drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2177 | if (!dev_priv->status_page_dmah) |
2178 | return -ENOMEM; | |
2179 | } | |
2180 | ||
0bc40be8 TU |
2181 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2182 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2183 | |
2184 | return 0; | |
2185 | } | |
2186 | ||
7ba717cf | 2187 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2188 | { |
3d77e9be CW |
2189 | GEM_BUG_ON(ringbuf->vma == NULL); |
2190 | GEM_BUG_ON(ringbuf->virtual_start == NULL); | |
2191 | ||
def0c5f6 | 2192 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2193 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 | 2194 | else |
3d77e9be | 2195 | i915_vma_unpin_iomap(ringbuf->vma); |
8305216f | 2196 | ringbuf->virtual_start = NULL; |
3d77e9be | 2197 | |
2919d291 | 2198 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
3d77e9be | 2199 | ringbuf->vma = NULL; |
7ba717cf TD |
2200 | } |
2201 | ||
c033666a | 2202 | int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv, |
7ba717cf TD |
2203 | struct intel_ringbuffer *ringbuf) |
2204 | { | |
7ba717cf | 2205 | struct drm_i915_gem_object *obj = ringbuf->obj; |
a687a43a CW |
2206 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2207 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2208 | void *addr; |
7ba717cf TD |
2209 | int ret; |
2210 | ||
def0c5f6 | 2211 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2212 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2213 | if (ret) |
2214 | return ret; | |
7ba717cf | 2215 | |
def0c5f6 | 2216 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2217 | if (ret) |
2218 | goto err_unpin; | |
def0c5f6 | 2219 | |
8305216f DG |
2220 | addr = i915_gem_object_pin_map(obj); |
2221 | if (IS_ERR(addr)) { | |
2222 | ret = PTR_ERR(addr); | |
d2cad535 | 2223 | goto err_unpin; |
def0c5f6 CW |
2224 | } |
2225 | } else { | |
a687a43a CW |
2226 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2227 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2228 | if (ret) |
2229 | return ret; | |
7ba717cf | 2230 | |
def0c5f6 | 2231 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2232 | if (ret) |
2233 | goto err_unpin; | |
def0c5f6 | 2234 | |
ff3dc087 DCS |
2235 | /* Access through the GTT requires the device to be awake. */ |
2236 | assert_rpm_wakelock_held(dev_priv); | |
2237 | ||
3d77e9be CW |
2238 | addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); |
2239 | if (IS_ERR(addr)) { | |
2240 | ret = PTR_ERR(addr); | |
d2cad535 | 2241 | goto err_unpin; |
def0c5f6 | 2242 | } |
7ba717cf TD |
2243 | } |
2244 | ||
8305216f | 2245 | ringbuf->virtual_start = addr; |
0eb973d3 | 2246 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2247 | return 0; |
d2cad535 CW |
2248 | |
2249 | err_unpin: | |
2250 | i915_gem_object_ggtt_unpin(obj); | |
2251 | return ret; | |
7ba717cf TD |
2252 | } |
2253 | ||
01101fa7 | 2254 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2255 | { |
2919d291 OM |
2256 | drm_gem_object_unreference(&ringbuf->obj->base); |
2257 | ringbuf->obj = NULL; | |
2258 | } | |
2259 | ||
01101fa7 CW |
2260 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2261 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2262 | { |
05394f39 | 2263 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2264 | |
ebc052e0 CW |
2265 | obj = NULL; |
2266 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2267 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2268 | if (obj == NULL) |
d37cd8a8 | 2269 | obj = i915_gem_object_create(dev, ringbuf->size); |
fe3db79b CW |
2270 | if (IS_ERR(obj)) |
2271 | return PTR_ERR(obj); | |
8187a2b7 | 2272 | |
24f3a8cf AG |
2273 | /* mark ring buffers as read-only from GPU side by default */ |
2274 | obj->gt_ro = 1; | |
2275 | ||
93b0a4e0 | 2276 | ringbuf->obj = obj; |
e3efda49 | 2277 | |
7ba717cf | 2278 | return 0; |
e3efda49 CW |
2279 | } |
2280 | ||
01101fa7 CW |
2281 | struct intel_ringbuffer * |
2282 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2283 | { | |
2284 | struct intel_ringbuffer *ring; | |
2285 | int ret; | |
2286 | ||
2287 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2288 | if (ring == NULL) { |
2289 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2290 | engine->name); | |
01101fa7 | 2291 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2292 | } |
01101fa7 | 2293 | |
4a570db5 | 2294 | ring->engine = engine; |
608c1a52 | 2295 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2296 | |
2297 | ring->size = size; | |
2298 | /* Workaround an erratum on the i830 which causes a hang if | |
2299 | * the TAIL pointer points to within the last 2 cachelines | |
2300 | * of the buffer. | |
2301 | */ | |
2302 | ring->effective_size = size; | |
c033666a | 2303 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
2304 | ring->effective_size -= 2 * CACHELINE_BYTES; |
2305 | ||
2306 | ring->last_retired_head = -1; | |
2307 | intel_ring_update_space(ring); | |
2308 | ||
c033666a | 2309 | ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring); |
01101fa7 | 2310 | if (ret) { |
608c1a52 CW |
2311 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2312 | engine->name, ret); | |
2313 | list_del(&ring->link); | |
01101fa7 CW |
2314 | kfree(ring); |
2315 | return ERR_PTR(ret); | |
2316 | } | |
2317 | ||
2318 | return ring; | |
2319 | } | |
2320 | ||
2321 | void | |
2322 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2323 | { | |
2324 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2325 | list_del(&ring->link); |
01101fa7 CW |
2326 | kfree(ring); |
2327 | } | |
2328 | ||
0cb26a8e CW |
2329 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2330 | struct intel_engine_cs *engine) | |
2331 | { | |
2332 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2333 | int ret; | |
2334 | ||
2335 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); | |
2336 | ||
2337 | if (ce->pin_count++) | |
2338 | return 0; | |
2339 | ||
2340 | if (ce->state) { | |
2341 | ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); | |
2342 | if (ret) | |
2343 | goto error; | |
2344 | } | |
2345 | ||
c7c3c07d CW |
2346 | /* The kernel context is only used as a placeholder for flushing the |
2347 | * active context. It is never used for submitting user rendering and | |
2348 | * as such never requires the golden render context, and so we can skip | |
2349 | * emitting it when we switch to the kernel context. This is required | |
2350 | * as during eviction we cannot allocate and pin the renderstate in | |
2351 | * order to initialise the context. | |
2352 | */ | |
2353 | if (ctx == ctx->i915->kernel_context) | |
2354 | ce->initialised = true; | |
2355 | ||
0cb26a8e CW |
2356 | i915_gem_context_reference(ctx); |
2357 | return 0; | |
2358 | ||
2359 | error: | |
2360 | ce->pin_count = 0; | |
2361 | return ret; | |
2362 | } | |
2363 | ||
2364 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2365 | struct intel_engine_cs *engine) | |
2366 | { | |
2367 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2368 | ||
2369 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); | |
2370 | ||
2371 | if (--ce->pin_count) | |
2372 | return; | |
2373 | ||
2374 | if (ce->state) | |
2375 | i915_gem_object_ggtt_unpin(ce->state); | |
2376 | ||
2377 | i915_gem_context_unreference(ctx); | |
2378 | } | |
2379 | ||
e3efda49 | 2380 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2381 | struct intel_engine_cs *engine) |
e3efda49 | 2382 | { |
c033666a | 2383 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfc882b4 | 2384 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2385 | int ret; |
2386 | ||
0bc40be8 | 2387 | WARN_ON(engine->buffer); |
bfc882b4 | 2388 | |
c033666a | 2389 | engine->i915 = dev_priv; |
0bc40be8 TU |
2390 | INIT_LIST_HEAD(&engine->active_list); |
2391 | INIT_LIST_HEAD(&engine->request_list); | |
2392 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2393 | INIT_LIST_HEAD(&engine->buffers); | |
2394 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2395 | memset(engine->semaphore.sync_seqno, 0, | |
2396 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2397 | |
0bc40be8 | 2398 | init_waitqueue_head(&engine->irq_queue); |
e3efda49 | 2399 | |
0cb26a8e CW |
2400 | /* We may need to do things with the shrinker which |
2401 | * require us to immediately switch back to the default | |
2402 | * context. This can cause a problem as pinning the | |
2403 | * default context also requires GTT space which may not | |
2404 | * be available. To avoid this we always pin the default | |
2405 | * context. | |
2406 | */ | |
2407 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2408 | if (ret) | |
2409 | goto error; | |
2410 | ||
0bc40be8 | 2411 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2412 | if (IS_ERR(ringbuf)) { |
2413 | ret = PTR_ERR(ringbuf); | |
2414 | goto error; | |
2415 | } | |
0bc40be8 | 2416 | engine->buffer = ringbuf; |
01101fa7 | 2417 | |
c033666a | 2418 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2419 | ret = init_status_page(engine); |
e3efda49 | 2420 | if (ret) |
8ee14975 | 2421 | goto error; |
e3efda49 | 2422 | } else { |
0bc40be8 TU |
2423 | WARN_ON(engine->id != RCS); |
2424 | ret = init_phys_status_page(engine); | |
e3efda49 | 2425 | if (ret) |
8ee14975 | 2426 | goto error; |
e3efda49 CW |
2427 | } |
2428 | ||
c033666a | 2429 | ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf); |
bfc882b4 DV |
2430 | if (ret) { |
2431 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2432 | engine->name, ret); |
bfc882b4 DV |
2433 | intel_destroy_ringbuffer_obj(ringbuf); |
2434 | goto error; | |
e3efda49 | 2435 | } |
62fdfeaf | 2436 | |
0bc40be8 | 2437 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2438 | if (ret) |
8ee14975 OM |
2439 | goto error; |
2440 | ||
8ee14975 | 2441 | return 0; |
351e3db2 | 2442 | |
8ee14975 | 2443 | error: |
117897f4 | 2444 | intel_cleanup_engine(engine); |
8ee14975 | 2445 | return ret; |
62fdfeaf EA |
2446 | } |
2447 | ||
117897f4 | 2448 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2449 | { |
6402c330 | 2450 | struct drm_i915_private *dev_priv; |
33626e6a | 2451 | |
117897f4 | 2452 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2453 | return; |
2454 | ||
c033666a | 2455 | dev_priv = engine->i915; |
6402c330 | 2456 | |
0bc40be8 | 2457 | if (engine->buffer) { |
117897f4 | 2458 | intel_stop_engine(engine); |
c033666a | 2459 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2460 | |
0bc40be8 TU |
2461 | intel_unpin_ringbuffer_obj(engine->buffer); |
2462 | intel_ringbuffer_free(engine->buffer); | |
2463 | engine->buffer = NULL; | |
b0366a54 | 2464 | } |
78501eac | 2465 | |
0bc40be8 TU |
2466 | if (engine->cleanup) |
2467 | engine->cleanup(engine); | |
8d19215b | 2468 | |
c033666a | 2469 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2470 | cleanup_status_page(engine); |
7d3fdfff | 2471 | } else { |
0bc40be8 TU |
2472 | WARN_ON(engine->id != RCS); |
2473 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2474 | } |
44e895a8 | 2475 | |
0bc40be8 TU |
2476 | i915_cmd_parser_fini_ring(engine); |
2477 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
0cb26a8e CW |
2478 | |
2479 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2480 | ||
c033666a | 2481 | engine->i915 = NULL; |
62fdfeaf EA |
2482 | } |
2483 | ||
666796da | 2484 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2485 | { |
a4b3a571 | 2486 | struct drm_i915_gem_request *req; |
3e960501 | 2487 | |
3e960501 | 2488 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2489 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2490 | return 0; |
2491 | ||
0bc40be8 TU |
2492 | req = list_entry(engine->request_list.prev, |
2493 | struct drm_i915_gem_request, | |
2494 | list); | |
b4716185 CW |
2495 | |
2496 | /* Make sure we do not trigger any retires */ | |
2497 | return __i915_wait_request(req, | |
c19ae989 | 2498 | req->i915->mm.interruptible, |
b4716185 | 2499 | NULL, NULL); |
3e960501 CW |
2500 | } |
2501 | ||
6689cb2b | 2502 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2503 | { |
6310346e CW |
2504 | int ret; |
2505 | ||
2506 | /* Flush enough space to reduce the likelihood of waiting after | |
2507 | * we start building the request - in which case we will just | |
2508 | * have to repeat work. | |
2509 | */ | |
a0442461 | 2510 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2511 | |
4a570db5 | 2512 | request->ringbuf = request->engine->buffer; |
6310346e CW |
2513 | |
2514 | ret = intel_ring_begin(request, 0); | |
2515 | if (ret) | |
2516 | return ret; | |
2517 | ||
a0442461 | 2518 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2519 | return 0; |
9d773091 CW |
2520 | } |
2521 | ||
987046ad CW |
2522 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2523 | { | |
2524 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2525 | struct intel_engine_cs *engine = req->engine; | |
2526 | struct drm_i915_gem_request *target; | |
2527 | ||
2528 | intel_ring_update_space(ringbuf); | |
2529 | if (ringbuf->space >= bytes) | |
2530 | return 0; | |
2531 | ||
2532 | /* | |
2533 | * Space is reserved in the ringbuffer for finalising the request, | |
2534 | * as that cannot be allowed to fail. During request finalisation, | |
2535 | * reserved_space is set to 0 to stop the overallocation and the | |
2536 | * assumption is that then we never need to wait (which has the | |
2537 | * risk of failing with EINTR). | |
2538 | * | |
2539 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2540 | */ | |
0251a963 | 2541 | GEM_BUG_ON(!req->reserved_space); |
987046ad CW |
2542 | |
2543 | list_for_each_entry(target, &engine->request_list, list) { | |
2544 | unsigned space; | |
2545 | ||
79bbcc29 | 2546 | /* |
987046ad CW |
2547 | * The request queue is per-engine, so can contain requests |
2548 | * from multiple ringbuffers. Here, we must ignore any that | |
2549 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2550 | */ |
987046ad CW |
2551 | if (target->ringbuf != ringbuf) |
2552 | continue; | |
2553 | ||
2554 | /* Would completion of this request free enough space? */ | |
2555 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2556 | ringbuf->size); | |
2557 | if (space >= bytes) | |
2558 | break; | |
79bbcc29 | 2559 | } |
29b1b415 | 2560 | |
987046ad CW |
2561 | if (WARN_ON(&target->list == &engine->request_list)) |
2562 | return -ENOSPC; | |
2563 | ||
2564 | return i915_wait_request(target); | |
29b1b415 JH |
2565 | } |
2566 | ||
987046ad | 2567 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2568 | { |
987046ad | 2569 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2570 | int remain_actual = ringbuf->size - ringbuf->tail; |
987046ad CW |
2571 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2572 | int bytes = num_dwords * sizeof(u32); | |
2573 | int total_bytes, wait_bytes; | |
79bbcc29 | 2574 | bool need_wrap = false; |
29b1b415 | 2575 | |
0251a963 | 2576 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2577 | |
79bbcc29 JH |
2578 | if (unlikely(bytes > remain_usable)) { |
2579 | /* | |
2580 | * Not enough space for the basic request. So need to flush | |
2581 | * out the remainder and then wait for base + reserved. | |
2582 | */ | |
2583 | wait_bytes = remain_actual + total_bytes; | |
2584 | need_wrap = true; | |
987046ad CW |
2585 | } else if (unlikely(total_bytes > remain_usable)) { |
2586 | /* | |
2587 | * The base request will fit but the reserved space | |
2588 | * falls off the end. So we don't need an immediate wrap | |
2589 | * and only need to effectively wait for the reserved | |
2590 | * size space from the start of ringbuffer. | |
2591 | */ | |
0251a963 | 2592 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2593 | } else { |
987046ad CW |
2594 | /* No wrapping required, just waiting. */ |
2595 | wait_bytes = total_bytes; | |
cbcc80df MK |
2596 | } |
2597 | ||
987046ad CW |
2598 | if (wait_bytes > ringbuf->space) { |
2599 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2600 | if (unlikely(ret)) |
2601 | return ret; | |
79bbcc29 | 2602 | |
987046ad | 2603 | intel_ring_update_space(ringbuf); |
e075a32f CW |
2604 | if (unlikely(ringbuf->space < wait_bytes)) |
2605 | return -EAGAIN; | |
cbcc80df MK |
2606 | } |
2607 | ||
987046ad CW |
2608 | if (unlikely(need_wrap)) { |
2609 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2610 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2611 | |
987046ad CW |
2612 | /* Fill the tail with MI_NOOP */ |
2613 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2614 | 0, remain_actual); | |
2615 | ringbuf->tail = 0; | |
2616 | ringbuf->space -= remain_actual; | |
2617 | } | |
304d695c | 2618 | |
987046ad CW |
2619 | ringbuf->space -= bytes; |
2620 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2621 | return 0; |
8187a2b7 | 2622 | } |
78501eac | 2623 | |
753b1ad4 | 2624 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2625 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2626 | { |
4a570db5 | 2627 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2628 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2629 | int ret; |
2630 | ||
2631 | if (num_dwords == 0) | |
2632 | return 0; | |
2633 | ||
18393f63 | 2634 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2635 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2636 | if (ret) |
2637 | return ret; | |
2638 | ||
2639 | while (num_dwords--) | |
e2f80391 | 2640 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2641 | |
e2f80391 | 2642 | intel_ring_advance(engine); |
753b1ad4 VS |
2643 | |
2644 | return 0; | |
2645 | } | |
2646 | ||
0bc40be8 | 2647 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2648 | { |
c033666a | 2649 | struct drm_i915_private *dev_priv = engine->i915; |
498d2ac1 | 2650 | |
29dcb570 CW |
2651 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2652 | * so long as the semaphore value in the register/page is greater | |
2653 | * than the sync value), so whenever we reset the seqno, | |
2654 | * so long as we reset the tracking semaphore value to 0, it will | |
2655 | * always be before the next request's seqno. If we don't reset | |
2656 | * the semaphore value, then when the seqno moves backwards all | |
2657 | * future waits will complete instantly (causing rendering corruption). | |
2658 | */ | |
7e22dbbb | 2659 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
0bc40be8 TU |
2660 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2661 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2662 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2663 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2664 | } |
a058d934 CW |
2665 | if (dev_priv->semaphore_obj) { |
2666 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2667 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2668 | void *semaphores = kmap(page); | |
2669 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2670 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2671 | kunmap(page); | |
2672 | } | |
29dcb570 CW |
2673 | memset(engine->semaphore.sync_seqno, 0, |
2674 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2675 | |
0bc40be8 | 2676 | engine->set_seqno(engine, seqno); |
01347126 | 2677 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2678 | |
0bc40be8 | 2679 | engine->hangcheck.seqno = seqno; |
8187a2b7 | 2680 | } |
62fdfeaf | 2681 | |
0bc40be8 | 2682 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2683 | u32 value) |
881f47b6 | 2684 | { |
c033666a | 2685 | struct drm_i915_private *dev_priv = engine->i915; |
881f47b6 | 2686 | |
76f8421f CW |
2687 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2688 | ||
881f47b6 | 2689 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2690 | |
2691 | /* Disable notification that the ring is IDLE. The GT | |
2692 | * will then assume that it is busy and bring it out of rc6. | |
2693 | */ | |
76f8421f CW |
2694 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2695 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2696 | |
2697 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2698 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2699 | |
12f55818 | 2700 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2701 | if (intel_wait_for_register_fw(dev_priv, |
2702 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2703 | GEN6_BSD_SLEEP_INDICATOR, | |
2704 | 0, | |
2705 | 50)) | |
12f55818 | 2706 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2707 | |
12f55818 | 2708 | /* Now that the ring is fully powered up, update the tail */ |
76f8421f CW |
2709 | I915_WRITE_FW(RING_TAIL(engine->mmio_base), value); |
2710 | POSTING_READ_FW(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2711 | |
2712 | /* Let the ring send IDLE messages to the GT again, | |
2713 | * and so let it sleep to conserve power when idle. | |
2714 | */ | |
76f8421f CW |
2715 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2716 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2717 | ||
2718 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2719 | } |
2720 | ||
a84c3ae1 | 2721 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2722 | u32 invalidate, u32 flush) |
881f47b6 | 2723 | { |
4a570db5 | 2724 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2725 | uint32_t cmd; |
b72f3acb CW |
2726 | int ret; |
2727 | ||
5fb9de1a | 2728 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2729 | if (ret) |
2730 | return ret; | |
2731 | ||
71a77e07 | 2732 | cmd = MI_FLUSH_DW; |
c033666a | 2733 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2734 | cmd += 1; |
f0a1fb10 CW |
2735 | |
2736 | /* We always require a command barrier so that subsequent | |
2737 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2738 | * wrt the contents of the write cache being flushed to memory | |
2739 | * (and thus being coherent from the CPU). | |
2740 | */ | |
2741 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2742 | ||
9a289771 JB |
2743 | /* |
2744 | * Bspec vol 1c.5 - video engine command streamer: | |
2745 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2746 | * operation is complete. This bit is only valid when the | |
2747 | * Post-Sync Operation field is a value of 1h or 3h." | |
2748 | */ | |
71a77e07 | 2749 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2750 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2751 | ||
e2f80391 TU |
2752 | intel_ring_emit(engine, cmd); |
2753 | intel_ring_emit(engine, | |
2754 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2755 | if (INTEL_GEN(req->i915) >= 8) { |
e2f80391 TU |
2756 | intel_ring_emit(engine, 0); /* upper addr */ |
2757 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2758 | } else { |
e2f80391 TU |
2759 | intel_ring_emit(engine, 0); |
2760 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2761 | } |
e2f80391 | 2762 | intel_ring_advance(engine); |
b72f3acb | 2763 | return 0; |
881f47b6 XH |
2764 | } |
2765 | ||
1c7a0623 | 2766 | static int |
53fddaf7 | 2767 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2768 | u64 offset, u32 len, |
8e004efc | 2769 | unsigned dispatch_flags) |
1c7a0623 | 2770 | { |
4a570db5 | 2771 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2772 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2773 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2774 | int ret; |
2775 | ||
5fb9de1a | 2776 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2777 | if (ret) |
2778 | return ret; | |
2779 | ||
2780 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2781 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2782 | (dispatch_flags & I915_DISPATCH_RS ? |
2783 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2784 | intel_ring_emit(engine, lower_32_bits(offset)); |
2785 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2786 | intel_ring_emit(engine, MI_NOOP); | |
2787 | intel_ring_advance(engine); | |
1c7a0623 BW |
2788 | |
2789 | return 0; | |
2790 | } | |
2791 | ||
d7d4eedd | 2792 | static int |
53fddaf7 | 2793 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2794 | u64 offset, u32 len, |
2795 | unsigned dispatch_flags) | |
d7d4eedd | 2796 | { |
4a570db5 | 2797 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2798 | int ret; |
2799 | ||
5fb9de1a | 2800 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2801 | if (ret) |
2802 | return ret; | |
2803 | ||
e2f80391 | 2804 | intel_ring_emit(engine, |
77072258 | 2805 | MI_BATCH_BUFFER_START | |
8e004efc | 2806 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2807 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2808 | (dispatch_flags & I915_DISPATCH_RS ? | |
2809 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2810 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2811 | intel_ring_emit(engine, offset); |
2812 | intel_ring_advance(engine); | |
d7d4eedd CW |
2813 | |
2814 | return 0; | |
2815 | } | |
2816 | ||
881f47b6 | 2817 | static int |
53fddaf7 | 2818 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2819 | u64 offset, u32 len, |
8e004efc | 2820 | unsigned dispatch_flags) |
881f47b6 | 2821 | { |
4a570db5 | 2822 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2823 | int ret; |
ab6f8e32 | 2824 | |
5fb9de1a | 2825 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2826 | if (ret) |
2827 | return ret; | |
e1f99ce6 | 2828 | |
e2f80391 | 2829 | intel_ring_emit(engine, |
d7d4eedd | 2830 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2831 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2832 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2833 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2834 | intel_ring_emit(engine, offset); |
2835 | intel_ring_advance(engine); | |
ab6f8e32 | 2836 | |
0206e353 | 2837 | return 0; |
881f47b6 XH |
2838 | } |
2839 | ||
549f7365 CW |
2840 | /* Blitter support (SandyBridge+) */ |
2841 | ||
a84c3ae1 | 2842 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2843 | u32 invalidate, u32 flush) |
8d19215b | 2844 | { |
4a570db5 | 2845 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2846 | uint32_t cmd; |
b72f3acb CW |
2847 | int ret; |
2848 | ||
5fb9de1a | 2849 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2850 | if (ret) |
2851 | return ret; | |
2852 | ||
71a77e07 | 2853 | cmd = MI_FLUSH_DW; |
c033666a | 2854 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2855 | cmd += 1; |
f0a1fb10 CW |
2856 | |
2857 | /* We always require a command barrier so that subsequent | |
2858 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2859 | * wrt the contents of the write cache being flushed to memory | |
2860 | * (and thus being coherent from the CPU). | |
2861 | */ | |
2862 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2863 | ||
9a289771 JB |
2864 | /* |
2865 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2866 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2867 | * operation is complete. This bit is only valid when the | |
2868 | * Post-Sync Operation field is a value of 1h or 3h." | |
2869 | */ | |
71a77e07 | 2870 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2871 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2872 | intel_ring_emit(engine, cmd); |
2873 | intel_ring_emit(engine, | |
2874 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2875 | if (INTEL_GEN(req->i915) >= 8) { |
e2f80391 TU |
2876 | intel_ring_emit(engine, 0); /* upper addr */ |
2877 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2878 | } else { |
e2f80391 TU |
2879 | intel_ring_emit(engine, 0); |
2880 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2881 | } |
e2f80391 | 2882 | intel_ring_advance(engine); |
fd3da6c9 | 2883 | |
b72f3acb | 2884 | return 0; |
8d19215b ZN |
2885 | } |
2886 | ||
d9a64610 TU |
2887 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2888 | struct intel_engine_cs *engine) | |
2889 | { | |
db3d4019 TU |
2890 | struct drm_i915_gem_object *obj; |
2891 | int ret; | |
2892 | ||
2893 | if (!i915_semaphore_is_enabled(dev_priv)) | |
2894 | return; | |
2895 | ||
2896 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { | |
2897 | obj = i915_gem_object_create(dev_priv->dev, 4096); | |
2898 | if (IS_ERR(obj)) { | |
2899 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2900 | i915.semaphores = 0; | |
2901 | } else { | |
2902 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2903 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2904 | if (ret != 0) { | |
2905 | drm_gem_object_unreference(&obj->base); | |
2906 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2907 | i915.semaphores = 0; | |
2908 | } else { | |
2909 | dev_priv->semaphore_obj = obj; | |
2910 | } | |
2911 | } | |
2912 | } | |
2913 | ||
d9a64610 TU |
2914 | if (!i915_semaphore_is_enabled(dev_priv)) |
2915 | return; | |
2916 | ||
2917 | if (INTEL_GEN(dev_priv) >= 8) { | |
2918 | engine->semaphore.sync_to = gen8_ring_sync; | |
2919 | engine->semaphore.signal = gen8_xcs_signal; | |
2920 | GEN8_RING_SEMAPHORE_INIT(engine); | |
2921 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
2922 | engine->semaphore.sync_to = gen6_ring_sync; | |
2923 | engine->semaphore.signal = gen6_signal; | |
2924 | } | |
2925 | } | |
2926 | ||
06a2fe22 TU |
2927 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2928 | struct intel_engine_cs *engine) | |
2929 | { | |
1d8a1337 | 2930 | engine->init_hw = init_ring_common; |
06a2fe22 | 2931 | engine->write_tail = ring_write_tail; |
604096d7 TU |
2932 | engine->get_seqno = ring_get_seqno; |
2933 | engine->set_seqno = ring_set_seqno; | |
7445a2a4 | 2934 | |
960ecaad TU |
2935 | if (INTEL_GEN(dev_priv) >= 8) { |
2936 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
2937 | engine->add_request = gen6_add_request; | |
2938 | engine->irq_seqno_barrier = gen6_seqno_barrier; | |
2939 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
2940 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
7445a2a4 | 2941 | engine->add_request = gen6_add_request; |
cc54a828 TU |
2942 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2943 | } else { | |
960ecaad | 2944 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
7445a2a4 | 2945 | engine->add_request = i9xx_add_request; |
cc54a828 | 2946 | } |
b9700325 TU |
2947 | |
2948 | if (INTEL_GEN(dev_priv) >= 8) { | |
2949 | engine->irq_get = gen8_ring_get_irq; | |
2950 | engine->irq_put = gen8_ring_put_irq; | |
2951 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
2952 | engine->irq_get = gen6_ring_get_irq; | |
2953 | engine->irq_put = gen6_ring_put_irq; | |
2954 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
2955 | engine->irq_get = gen5_ring_get_irq; | |
2956 | engine->irq_put = gen5_ring_put_irq; | |
2957 | } else if (INTEL_GEN(dev_priv) >= 3) { | |
2958 | engine->irq_get = i9xx_ring_get_irq; | |
2959 | engine->irq_put = i9xx_ring_put_irq; | |
2960 | } else { | |
2961 | engine->irq_get = i8xx_ring_get_irq; | |
2962 | engine->irq_put = i8xx_ring_put_irq; | |
2963 | } | |
d9a64610 TU |
2964 | |
2965 | intel_ring_init_semaphores(dev_priv, engine); | |
06a2fe22 TU |
2966 | } |
2967 | ||
5c1143bb XH |
2968 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2969 | { | |
4640c4ff | 2970 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2971 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
2972 | struct drm_i915_gem_object *obj; |
2973 | int ret; | |
5c1143bb | 2974 | |
e2f80391 TU |
2975 | engine->name = "render ring"; |
2976 | engine->id = RCS; | |
2977 | engine->exec_id = I915_EXEC_RENDER; | |
215a7e32 | 2978 | engine->hw_id = 0; |
e2f80391 | 2979 | engine->mmio_base = RENDER_RING_BASE; |
59465b5f | 2980 | |
06a2fe22 TU |
2981 | intel_ring_default_vfuncs(dev_priv, engine); |
2982 | ||
c033666a | 2983 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2984 | engine->init_context = intel_rcs_ctx_init; |
a58c01aa | 2985 | engine->add_request = gen8_render_add_request; |
e2f80391 | 2986 | engine->flush = gen8_render_ring_flush; |
e2f80391 | 2987 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
db3d4019 | 2988 | if (i915_semaphore_is_enabled(dev_priv)) |
e2f80391 | 2989 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2990 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2991 | engine->init_context = intel_rcs_ctx_init; |
e2f80391 | 2992 | engine->flush = gen7_render_ring_flush; |
c033666a | 2993 | if (IS_GEN6(dev_priv)) |
e2f80391 | 2994 | engine->flush = gen6_render_ring_flush; |
e2f80391 | 2995 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
c033666a | 2996 | if (i915_semaphore_is_enabled(dev_priv)) { |
707d9cf9 BW |
2997 | /* |
2998 | * The current semaphore is only applied on pre-gen8 | |
2999 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3000 | * platform. So the semaphore between RCS and VCS2 is | |
3001 | * initialized as INVALID. Gen8 will initialize the | |
3002 | * sema between VCS2 and RCS later. | |
3003 | */ | |
e2f80391 TU |
3004 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
3005 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
3006 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
3007 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
3008 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3009 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
3010 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
3011 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
3012 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
3013 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3014 | } |
c033666a | 3015 | } else if (IS_GEN5(dev_priv)) { |
e2f80391 TU |
3016 | engine->add_request = pc_render_add_request; |
3017 | engine->flush = gen4_render_ring_flush; | |
3018 | engine->get_seqno = pc_render_get_seqno; | |
3019 | engine->set_seqno = pc_render_set_seqno; | |
e2f80391 | 3020 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
cc609d5d | 3021 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 3022 | } else { |
c033666a | 3023 | if (INTEL_GEN(dev_priv) < 4) |
e2f80391 | 3024 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 3025 | else |
e2f80391 | 3026 | engine->flush = gen4_render_ring_flush; |
e2f80391 | 3027 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 3028 | } |
707d9cf9 | 3029 | |
c033666a | 3030 | if (IS_HASWELL(dev_priv)) |
e2f80391 | 3031 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
c033666a | 3032 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
e2f80391 | 3033 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
960ecaad | 3034 | else if (INTEL_GEN(dev_priv) <= 3) |
e2f80391 TU |
3035 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
3036 | engine->init_hw = init_render_ring; | |
3037 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 3038 | |
b45305fc | 3039 | /* Workaround batchbuffer to combat CS tlb bug. */ |
c033666a | 3040 | if (HAS_BROKEN_CS_TLB(dev_priv)) { |
d37cd8a8 | 3041 | obj = i915_gem_object_create(dev, I830_WA_SIZE); |
fe3db79b | 3042 | if (IS_ERR(obj)) { |
b45305fc | 3043 | DRM_ERROR("Failed to allocate batch bo\n"); |
fe3db79b | 3044 | return PTR_ERR(obj); |
b45305fc DV |
3045 | } |
3046 | ||
be1fa129 | 3047 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
3048 | if (ret != 0) { |
3049 | drm_gem_object_unreference(&obj->base); | |
3050 | DRM_ERROR("Failed to ping batch bo\n"); | |
3051 | return ret; | |
3052 | } | |
3053 | ||
e2f80391 TU |
3054 | engine->scratch.obj = obj; |
3055 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
3056 | } |
3057 | ||
e2f80391 | 3058 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
3059 | if (ret) |
3060 | return ret; | |
3061 | ||
c033666a | 3062 | if (INTEL_GEN(dev_priv) >= 5) { |
e2f80391 | 3063 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
3064 | if (ret) |
3065 | return ret; | |
3066 | } | |
3067 | ||
3068 | return 0; | |
5c1143bb XH |
3069 | } |
3070 | ||
3071 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
3072 | { | |
4640c4ff | 3073 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3074 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 3075 | |
e2f80391 TU |
3076 | engine->name = "bsd ring"; |
3077 | engine->id = VCS; | |
3078 | engine->exec_id = I915_EXEC_BSD; | |
215a7e32 | 3079 | engine->hw_id = 1; |
58fa3835 | 3080 | |
06a2fe22 TU |
3081 | intel_ring_default_vfuncs(dev_priv, engine); |
3082 | ||
c033666a | 3083 | if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 3084 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 | 3085 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 3086 | if (IS_GEN6(dev_priv)) |
e2f80391 TU |
3087 | engine->write_tail = gen6_bsd_ring_write_tail; |
3088 | engine->flush = gen6_bsd_ring_flush; | |
c033666a | 3089 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 3090 | engine->irq_enable_mask = |
abd58f01 | 3091 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
abd58f01 | 3092 | } else { |
e2f80391 | 3093 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
c033666a | 3094 | if (i915_semaphore_is_enabled(dev_priv)) { |
e2f80391 TU |
3095 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
3096 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3097 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
3098 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
3099 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3100 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
3101 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
3102 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
3103 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
3104 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3105 | } |
abd58f01 | 3106 | } |
58fa3835 | 3107 | } else { |
e2f80391 TU |
3108 | engine->mmio_base = BSD_RING_BASE; |
3109 | engine->flush = bsd_ring_flush; | |
c033666a | 3110 | if (IS_GEN5(dev_priv)) { |
e2f80391 | 3111 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 | 3112 | } else { |
e2f80391 | 3113 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 | 3114 | } |
58fa3835 | 3115 | } |
58fa3835 | 3116 | |
e2f80391 | 3117 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 3118 | } |
549f7365 | 3119 | |
845f74a7 | 3120 | /** |
62659920 | 3121 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
3122 | */ |
3123 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
3124 | { | |
3125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 3126 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
3127 | |
3128 | engine->name = "bsd2 ring"; | |
3129 | engine->id = VCS2; | |
3130 | engine->exec_id = I915_EXEC_BSD; | |
215a7e32 | 3131 | engine->hw_id = 4; |
e2f80391 | 3132 | engine->mmio_base = GEN8_BSD2_RING_BASE; |
06a2fe22 TU |
3133 | |
3134 | intel_ring_default_vfuncs(dev_priv, engine); | |
3135 | ||
e2f80391 | 3136 | engine->flush = gen6_bsd_ring_flush; |
e2f80391 | 3137 | engine->irq_enable_mask = |
845f74a7 | 3138 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
845f74a7 | 3139 | |
e2f80391 | 3140 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
3141 | } |
3142 | ||
549f7365 CW |
3143 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
3144 | { | |
4640c4ff | 3145 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3146 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
3147 | |
3148 | engine->name = "blitter ring"; | |
3149 | engine->id = BCS; | |
3150 | engine->exec_id = I915_EXEC_BLT; | |
215a7e32 | 3151 | engine->hw_id = 2; |
e2f80391 | 3152 | engine->mmio_base = BLT_RING_BASE; |
06a2fe22 TU |
3153 | |
3154 | intel_ring_default_vfuncs(dev_priv, engine); | |
3155 | ||
e2f80391 | 3156 | engine->flush = gen6_ring_flush; |
c033666a | 3157 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 3158 | engine->irq_enable_mask = |
abd58f01 | 3159 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
abd58f01 | 3160 | } else { |
e2f80391 | 3161 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
c033666a | 3162 | if (i915_semaphore_is_enabled(dev_priv)) { |
707d9cf9 BW |
3163 | /* |
3164 | * The current semaphore is only applied on pre-gen8 | |
3165 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3166 | * platform. So the semaphore between BCS and VCS2 is | |
3167 | * initialized as INVALID. Gen8 will initialize the | |
3168 | * sema between BCS and VCS2 later. | |
3169 | */ | |
e2f80391 TU |
3170 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
3171 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
3172 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3173 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
3174 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3175 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
3176 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
3177 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
3178 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
3179 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3180 | } |
abd58f01 | 3181 | } |
549f7365 | 3182 | |
e2f80391 | 3183 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3184 | } |
a7b9761d | 3185 | |
9a8a2213 BW |
3186 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3187 | { | |
4640c4ff | 3188 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3189 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3190 | |
e2f80391 TU |
3191 | engine->name = "video enhancement ring"; |
3192 | engine->id = VECS; | |
3193 | engine->exec_id = I915_EXEC_VEBOX; | |
215a7e32 | 3194 | engine->hw_id = 3; |
e2f80391 | 3195 | engine->mmio_base = VEBOX_RING_BASE; |
06a2fe22 TU |
3196 | |
3197 | intel_ring_default_vfuncs(dev_priv, engine); | |
3198 | ||
e2f80391 | 3199 | engine->flush = gen6_ring_flush; |
abd58f01 | 3200 | |
c033666a | 3201 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 3202 | engine->irq_enable_mask = |
40c499f9 | 3203 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 | 3204 | } else { |
e2f80391 TU |
3205 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3206 | engine->irq_get = hsw_vebox_get_irq; | |
3207 | engine->irq_put = hsw_vebox_put_irq; | |
c033666a | 3208 | if (i915_semaphore_is_enabled(dev_priv)) { |
e2f80391 TU |
3209 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
3210 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3211 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3212 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3213 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3214 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3215 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3216 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3217 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3218 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3219 | } |
abd58f01 | 3220 | } |
9a8a2213 | 3221 | |
e2f80391 | 3222 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3223 | } |
3224 | ||
a7b9761d | 3225 | int |
4866d729 | 3226 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3227 | { |
4a570db5 | 3228 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3229 | int ret; |
3230 | ||
e2f80391 | 3231 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3232 | return 0; |
3233 | ||
e2f80391 | 3234 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3235 | if (ret) |
3236 | return ret; | |
3237 | ||
a84c3ae1 | 3238 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3239 | |
e2f80391 | 3240 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3241 | return 0; |
3242 | } | |
3243 | ||
3244 | int | |
2f20055d | 3245 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3246 | { |
4a570db5 | 3247 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3248 | uint32_t flush_domains; |
3249 | int ret; | |
3250 | ||
3251 | flush_domains = 0; | |
e2f80391 | 3252 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3253 | flush_domains = I915_GEM_GPU_DOMAINS; |
3254 | ||
e2f80391 | 3255 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3256 | if (ret) |
3257 | return ret; | |
3258 | ||
a84c3ae1 | 3259 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3260 | |
e2f80391 | 3261 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3262 | return 0; |
3263 | } | |
e3efda49 CW |
3264 | |
3265 | void | |
117897f4 | 3266 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3267 | { |
3268 | int ret; | |
3269 | ||
117897f4 | 3270 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3271 | return; |
3272 | ||
666796da | 3273 | ret = intel_engine_idle(engine); |
f4457ae7 | 3274 | if (ret) |
e3efda49 | 3275 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3276 | engine->name, ret); |
e3efda49 | 3277 | |
0bc40be8 | 3278 | stop_ring(engine); |
e3efda49 | 3279 | } |