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drm/i915/bxt: Add WaEnablePooledEuFor2x6
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
a4d8a0fe 30#include <linux/log2.h>
760285e7 31#include <drm/drmP.h>
62fdfeaf 32#include "i915_drv.h"
760285e7 33#include <drm/i915_drm.h>
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
a0442461
CW		 37/* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
39 */
40#define LEGACY_REQUEST_SIZE 200
41
82e104cc 42int __intel_ring_space(int head, int tail, int size)
c7dca47b 43{
4f54741e
DG		 44 int space = head - tail;
45 if (space <= 0)
1cf0ba14 46 space += size;
4f54741e 47 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 48}
49
ebd0fd4b
DG		 50void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
51{
52 if (ringbuf->last_retired_head != -1) {
53 ringbuf->head = ringbuf->last_retired_head;
54 ringbuf->last_retired_head = -1;
55 }
56
57 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
58 ringbuf->tail, ringbuf->size);
59}
60
117897f4 61bool intel_engine_stopped(struct intel_engine_cs *engine)
09246732 62{
c033666a 63 struct drm_i915_private *dev_priv = engine->i915;
666796da 64 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
88b4aa87 65}
09246732 66
0bc40be8 67static void __intel_ring_advance(struct intel_engine_cs *engine)
88b4aa87 68{
0bc40be8 69 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 70 ringbuf->tail &= ringbuf->size - 1;
117897f4 71 if (intel_engine_stopped(engine))
09246732 72 return;
0bc40be8 73 engine->write_tail(engine, ringbuf->tail);
09246732
CW		 74}
75
b72f3acb 76static int
a84c3ae1 77gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 78 u32 invalidate_domains,
79 u32 flush_domains)
80{
4a570db5 81 struct intel_engine_cs *engine = req->engine;
46f0f8d1
CW		 82 u32 cmd;
83 int ret;
84
85 cmd = MI_FLUSH;
31b14c9f 86 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 87 cmd |= MI_NO_WRITE_FLUSH;
88
89 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
90 cmd |= MI_READ_FLUSH;
91
5fb9de1a 92 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 93 if (ret)
94 return ret;
95
e2f80391
TU		 96 intel_ring_emit(engine, cmd);
97 intel_ring_emit(engine, MI_NOOP);
98 intel_ring_advance(engine);
46f0f8d1
CW		 99
100 return 0;
101}
102
103static int
a84c3ae1 104gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 105 u32 invalidate_domains,
106 u32 flush_domains)
62fdfeaf 107{
4a570db5 108 struct intel_engine_cs *engine = req->engine;
6f392d54 109 u32 cmd;
b72f3acb 110 int ret;
6f392d54 111
36d527de
CW		 112 /*
113 * read/write caches:
114 *
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
118 *
119 * read-only caches:
120 *
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
123 *
124 * I915_GEM_DOMAIN_COMMAND may not exist?
125 *
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
128 *
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
131 *
132 * TLBs:
133 *
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
138 */
139
140 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 141 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 142 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 143 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
144 cmd |= MI_EXE_FLUSH;
62fdfeaf 145
36d527de 146 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
c033666a 147 (IS_G4X(req->i915) || IS_GEN5(req->i915)))
36d527de 148 cmd |= MI_INVALIDATE_ISP;
70eac33e 149
5fb9de1a 150 ret = intel_ring_begin(req, 2);
36d527de
CW		 151 if (ret)
152 return ret;
b72f3acb 153
e2f80391
TU		 154 intel_ring_emit(engine, cmd);
155 intel_ring_emit(engine, MI_NOOP);
156 intel_ring_advance(engine);
b72f3acb
CW		 157
158 return 0;
8187a2b7
ZN		 159}
160
8d315287
JB		 161/**
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
165 *
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
169 * 0.
170 *
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
173 *
174 * And the workaround for these two requires this workaround first:
175 *
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
178 * flushes.
179 *
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
182 * volume 2 part 1:
183 *
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
191 *
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
197 */
198static int
f2cf1fcc 199intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 200{
4a570db5 201 struct intel_engine_cs *engine = req->engine;
e2f80391 202 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 203 int ret;
204
5fb9de1a 205 ret = intel_ring_begin(req, 6);
8d315287
JB		 206 if (ret)
207 return ret;
208
e2f80391
TU		 209 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
8d315287 211 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 212 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(engine, 0); /* low dword */
214 intel_ring_emit(engine, 0); /* high dword */
215 intel_ring_emit(engine, MI_NOOP);
216 intel_ring_advance(engine);
8d315287 217
5fb9de1a 218 ret = intel_ring_begin(req, 6);
8d315287
JB		 219 if (ret)
220 return ret;
221
e2f80391
TU		 222 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
224 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
225 intel_ring_emit(engine, 0);
226 intel_ring_emit(engine, 0);
227 intel_ring_emit(engine, MI_NOOP);
228 intel_ring_advance(engine);
8d315287
JB		 229
230 return 0;
231}
232
233static int
a84c3ae1
JH		 234gen6_render_ring_flush(struct drm_i915_gem_request *req,
235 u32 invalidate_domains, u32 flush_domains)
8d315287 236{
4a570db5 237 struct intel_engine_cs *engine = req->engine;
8d315287 238 u32 flags = 0;
e2f80391 239 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 240 int ret;
241
b3111509 242 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 243 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 244 if (ret)
245 return ret;
246
8d315287
JB		 247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
249 * impact.
250 */
7d54a904
CW		 251 if (flush_domains) {
252 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
253 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
254 /*
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
257 */
97f209bc 258 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 259 }
260 if (invalidate_domains) {
261 flags |= PIPE_CONTROL_TLB_INVALIDATE;
262 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
263 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
264 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
267 /*
268 * TLB invalidate requires a post-sync write.
269 */
3ac78313 270 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 271 }
8d315287 272
5fb9de1a 273 ret = intel_ring_begin(req, 4);
8d315287
JB		 274 if (ret)
275 return ret;
276
e2f80391
TU		 277 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine, flags);
279 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
280 intel_ring_emit(engine, 0);
281 intel_ring_advance(engine);
8d315287
JB		 282
283 return 0;
284}
285
f3987631 286static int
f2cf1fcc 287gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 288{
4a570db5 289 struct intel_engine_cs *engine = req->engine;
f3987631
PZ		 290 int ret;
291
5fb9de1a 292 ret = intel_ring_begin(req, 4);
f3987631
PZ		 293 if (ret)
294 return ret;
295
e2f80391
TU		 296 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
f3987631 298 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 299 intel_ring_emit(engine, 0);
300 intel_ring_emit(engine, 0);
301 intel_ring_advance(engine);
f3987631
PZ		 302
303 return 0;
304}
305
4772eaeb 306static int
a84c3ae1 307gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 308 u32 invalidate_domains, u32 flush_domains)
309{
4a570db5 310 struct intel_engine_cs *engine = req->engine;
4772eaeb 311 u32 flags = 0;
e2f80391 312 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 313 int ret;
314
f3987631
PZ		 315 /*
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
318 *
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
322 */
323 flags |= PIPE_CONTROL_CS_STALL;
324
4772eaeb
PZ		 325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
327 * impact.
328 */
329 if (flush_domains) {
330 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
331 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 332 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 333 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4772eaeb
PZ		 334 }
335 if (invalidate_domains) {
336 flags |= PIPE_CONTROL_TLB_INVALIDATE;
337 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
338 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
339 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 342 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 343 /*
344 * TLB invalidate requires a post-sync write.
345 */
346 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 347 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 348
add284a3
CW		 349 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
350
f3987631
PZ		 351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
f2cf1fcc 354 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 355 }
356
5fb9de1a 357 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 358 if (ret)
359 return ret;
360
e2f80391
TU		 361 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine, flags);
363 intel_ring_emit(engine, scratch_addr);
364 intel_ring_emit(engine, 0);
365 intel_ring_advance(engine);
4772eaeb
PZ		 366
367 return 0;
368}
369
884ceace 370static int
f2cf1fcc 371gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 372 u32 flags, u32 scratch_addr)
373{
4a570db5 374 struct intel_engine_cs *engine = req->engine;
884ceace
KG		 375 int ret;
376
5fb9de1a 377 ret = intel_ring_begin(req, 6);
884ceace
KG		 378 if (ret)
379 return ret;
380
e2f80391
TU		 381 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine, flags);
383 intel_ring_emit(engine, scratch_addr);
384 intel_ring_emit(engine, 0);
385 intel_ring_emit(engine, 0);
386 intel_ring_emit(engine, 0);
387 intel_ring_advance(engine);
884ceace
KG		 388
389 return 0;
390}
391
a5f3d68e 392static int
a84c3ae1 393gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 394 u32 invalidate_domains, u32 flush_domains)
395{
396 u32 flags = 0;
4a570db5 397 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 398 int ret;
a5f3d68e
BW		 399
400 flags |= PIPE_CONTROL_CS_STALL;
401
402 if (flush_domains) {
403 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
404 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 405 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 406 flags |= PIPE_CONTROL_FLUSH_ENABLE;
a5f3d68e
BW		 407 }
408 if (invalidate_domains) {
409 flags |= PIPE_CONTROL_TLB_INVALIDATE;
410 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
412 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_QW_WRITE;
416 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 417
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 419 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 420 PIPE_CONTROL_CS_STALL |
421 PIPE_CONTROL_STALL_AT_SCOREBOARD,
422 0);
423 if (ret)
424 return ret;
a5f3d68e
BW		 425 }
426
f2cf1fcc 427 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 428}
429
0bc40be8 430static void ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 431 u32 value)
d46eefa2 432{
c033666a 433 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 434 I915_WRITE_TAIL(engine, value);
d46eefa2
XH		 435}
436
0bc40be8 437u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
8187a2b7 438{
c033666a 439 struct drm_i915_private *dev_priv = engine->i915;
50877445 440 u64 acthd;
8187a2b7 441
c033666a 442 if (INTEL_GEN(dev_priv) >= 8)
0bc40be8
TU		 443 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
444 RING_ACTHD_UDW(engine->mmio_base));
c033666a 445 else if (INTEL_GEN(dev_priv) >= 4)
0bc40be8 446 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
50877445
CW		 447 else
448 acthd = I915_READ(ACTHD);
449
450 return acthd;
8187a2b7
ZN		 451}
452
0bc40be8 453static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
035dc1e0 454{
c033666a 455 struct drm_i915_private *dev_priv = engine->i915;
035dc1e0
DV		 456 u32 addr;
457
458 addr = dev_priv->status_page_dmah->busaddr;
c033666a 459 if (INTEL_GEN(dev_priv) >= 4)
035dc1e0
DV		 460 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
461 I915_WRITE(HWS_PGA, addr);
462}
463
0bc40be8 464static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
af75f269 465{
c033666a 466 struct drm_i915_private *dev_priv = engine->i915;
f0f59a00 467 i915_reg_t mmio;
af75f269
DL		 468
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
471 */
c033666a 472 if (IS_GEN7(dev_priv)) {
0bc40be8 473 switch (engine->id) {
af75f269
DL		 474 case RCS:
475 mmio = RENDER_HWS_PGA_GEN7;
476 break;
477 case BCS:
478 mmio = BLT_HWS_PGA_GEN7;
479 break;
480 /*
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
483 */
484 case VCS2:
485 case VCS:
486 mmio = BSD_HWS_PGA_GEN7;
487 break;
488 case VECS:
489 mmio = VEBOX_HWS_PGA_GEN7;
490 break;
491 }
c033666a 492 } else if (IS_GEN6(dev_priv)) {
0bc40be8 493 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
af75f269
DL		 494 } else {
495 /* XXX: gen8 returns to sanity */
0bc40be8 496 mmio = RING_HWS_PGA(engine->mmio_base);
af75f269
DL		 497 }
498
0bc40be8 499 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
af75f269
DL		 500 POSTING_READ(mmio);
501
502 /*
503 * Flush the TLB for this page
504 *
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
508 */
ac657f64 509 if (IS_GEN(dev_priv, 6, 7)) {
0bc40be8 510 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
af75f269
DL		 511
512 /* ring should be idle before issuing a sync flush*/
0bc40be8 513 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
af75f269
DL		 514
515 I915_WRITE(reg,
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
517 INSTPM_SYNC_FLUSH));
518 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
519 1000))
520 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
0bc40be8 521 engine->name);
af75f269
DL		 522 }
523}
524
0bc40be8 525static bool stop_ring(struct intel_engine_cs *engine)
8187a2b7 526{
c033666a 527 struct drm_i915_private *dev_priv = engine->i915;
8187a2b7 528
c033666a 529 if (!IS_GEN2(dev_priv)) {
0bc40be8
TU		 530 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
531 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
532 DRM_ERROR("%s : timed out trying to stop ring\n",
533 engine->name);
9bec9b13
CW		 534 /* Sometimes we observe that the idle flag is not
535 * set even though the ring is empty. So double
536 * check before giving up.
537 */
0bc40be8 538 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
9bec9b13 539 return false;
9991ae78
CW		 540 }
541 }
b7884eb4 542
0bc40be8
TU		 543 I915_WRITE_CTL(engine, 0);
544 I915_WRITE_HEAD(engine, 0);
545 engine->write_tail(engine, 0);
8187a2b7 546
c033666a 547 if (!IS_GEN2(dev_priv)) {
0bc40be8
TU		 548 (void)I915_READ_CTL(engine);
549 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
9991ae78 550 }
a51435a3 551
0bc40be8 552 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
9991ae78 553}
8187a2b7 554
fc0768ce
TE		 555void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
556{
557 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
558}
559
0bc40be8 560static int init_ring_common(struct intel_engine_cs *engine)
9991ae78 561{
c033666a 562 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 563 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 564 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 565 int ret = 0;
566
59bad947 567 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78 568
0bc40be8 569 if (!stop_ring(engine)) {
9991ae78 570 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 571 DRM_DEBUG_KMS("%s head not reset to zero "
572 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 573 engine->name,
574 I915_READ_CTL(engine),
575 I915_READ_HEAD(engine),
576 I915_READ_TAIL(engine),
577 I915_READ_START(engine));
8187a2b7 578
0bc40be8 579 if (!stop_ring(engine)) {
6fd0d56e
CW		 580 DRM_ERROR("failed to set %s head to zero "
581 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 582 engine->name,
583 I915_READ_CTL(engine),
584 I915_READ_HEAD(engine),
585 I915_READ_TAIL(engine),
586 I915_READ_START(engine));
9991ae78
CW		 587 ret = -EIO;
588 goto out;
6fd0d56e 589 }
8187a2b7
ZN		 590 }
591
c033666a 592 if (I915_NEED_GFX_HWS(dev_priv))
0bc40be8 593 intel_ring_setup_status_page(engine);
9991ae78 594 else
0bc40be8 595 ring_setup_phys_status_page(engine);
9991ae78 596
ece4a17d 597 /* Enforce ordering by reading HEAD register back */
0bc40be8 598 I915_READ_HEAD(engine);
ece4a17d 599
0d8957c8
DV		 600 /* Initialize the ring. This must happen _after_ we've cleared the ring
601 * registers with the above sequence (the readback of the HEAD registers
602 * also enforces ordering), otherwise the hw might lose the new ring
603 * register values. */
0bc40be8 604 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 605
606 /* WaClearRingBufHeadRegAtInit:ctg,elk */
0bc40be8 607 if (I915_READ_HEAD(engine))
95468892 608 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
0bc40be8
TU		 609 engine->name, I915_READ_HEAD(engine));
610 I915_WRITE_HEAD(engine, 0);
611 (void)I915_READ_HEAD(engine);
95468892 612
0bc40be8 613 I915_WRITE_CTL(engine,
93b0a4e0 614 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 615 | RING_VALID);
8187a2b7 616
8187a2b7 617 /* If the head is still not zero, the ring is dead */
0bc40be8
TU		 618 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
619 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
620 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
e74cfed5 621 DRM_ERROR("%s initialization failed "
48e48a0b 622 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
0bc40be8
TU		 623 engine->name,
624 I915_READ_CTL(engine),
625 I915_READ_CTL(engine) & RING_VALID,
626 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
627 I915_READ_START(engine),
628 (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 629 ret = -EIO;
630 goto out;
8187a2b7
ZN		 631 }
632
ebd0fd4b 633 ringbuf->last_retired_head = -1;
0bc40be8
TU		 634 ringbuf->head = I915_READ_HEAD(engine);
635 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
ebd0fd4b 636 intel_ring_update_space(ringbuf);
1ec14ad3 637
fc0768ce 638 intel_engine_init_hangcheck(engine);
50f018df 639
b7884eb4 640out:
59bad947 641 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 642
643 return ret;
8187a2b7
ZN		 644}
645
9b1136d5 646void
0bc40be8 647intel_fini_pipe_control(struct intel_engine_cs *engine)
9b1136d5 648{
0bc40be8 649 if (engine->scratch.obj == NULL)
9b1136d5
OM		 650 return;
651
c033666a 652 if (INTEL_GEN(engine->i915) >= 5) {
0bc40be8
TU		 653 kunmap(sg_page(engine->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(engine->scratch.obj);
9b1136d5
OM		 655 }
656
0bc40be8
TU		 657 drm_gem_object_unreference(&engine->scratch.obj->base);
658 engine->scratch.obj = NULL;
9b1136d5
OM		 659}
660
661int
0bc40be8 662intel_init_pipe_control(struct intel_engine_cs *engine)
c6df541c 663{
c6df541c
CW		 664 int ret;
665
0bc40be8 666 WARN_ON(engine->scratch.obj);
c6df541c 667
c033666a 668 engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
fe3db79b 669 if (IS_ERR(engine->scratch.obj)) {
c6df541c 670 DRM_ERROR("Failed to allocate seqno page\n");
fe3db79b
CW		 671 ret = PTR_ERR(engine->scratch.obj);
672 engine->scratch.obj = NULL;
c6df541c
CW		 673 goto err;
674 }
e4ffd173 675
0bc40be8
TU		 676 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
677 I915_CACHE_LLC);
a9cc726c
DV		 678 if (ret)
679 goto err_unref;
c6df541c 680
0bc40be8 681 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
c6df541c
CW		 682 if (ret)
683 goto err_unref;
684
0bc40be8
TU		 685 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
686 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
687 if (engine->scratch.cpu_page == NULL) {
56b085a0 688 ret = -ENOMEM;
c6df541c 689 goto err_unpin;
56b085a0 690 }
c6df541c 691
2b1086cc 692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0bc40be8 693 engine->name, engine->scratch.gtt_offset);
c6df541c
CW		 694 return 0;
695
696err_unpin:
0bc40be8 697 i915_gem_object_ggtt_unpin(engine->scratch.obj);
c6df541c 698err_unref:
0bc40be8 699 drm_gem_object_unreference(&engine->scratch.obj->base);
c6df541c 700err:
c6df541c
CW		 701 return ret;
702}
703
e2be4faf 704static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 705{
4a570db5 706 struct intel_engine_cs *engine = req->engine;
c033666a
CW		 707 struct i915_workarounds *w = &req->i915->workarounds;
708 int ret, i;
888b5995 709
02235808 710 if (w->count == 0)
7225342a 711 return 0;
888b5995 712
e2f80391 713 engine->gpu_caches_dirty = true;
4866d729 714 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 715 if (ret)
716 return ret;
888b5995 717
5fb9de1a 718 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 719 if (ret)
720 return ret;
721
e2f80391 722 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
7225342a 723 for (i = 0; i < w->count; i++) {
e2f80391
TU		 724 intel_ring_emit_reg(engine, w->reg[i].addr);
725 intel_ring_emit(engine, w->reg[i].value);
7225342a 726 }
e2f80391 727 intel_ring_emit(engine, MI_NOOP);
7225342a 728
e2f80391 729 intel_ring_advance(engine);
7225342a 730
e2f80391 731 engine->gpu_caches_dirty = true;
4866d729 732 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 733 if (ret)
734 return ret;
888b5995 735
7225342a 736 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 737
7225342a 738 return 0;
86d7f238
AS		 739}
740
8753181e 741static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 742{
743 int ret;
744
e2be4faf 745 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 746 if (ret != 0)
747 return ret;
748
be01363f 749 ret = i915_gem_render_state_init(req);
8f0e2b9d 750 if (ret)
e26e1b97 751 return ret;
8f0e2b9d 752
e26e1b97 753 return 0;
8f0e2b9d
DV		 754}
755
7225342a 756static int wa_add(struct drm_i915_private *dev_priv,
f0f59a00
VS		 757 i915_reg_t addr,
758 const u32 mask, const u32 val)
7225342a
MK		 759{
760 const u32 idx = dev_priv->workarounds.count;
761
762 if (WARN_ON(idx >= I915_MAX_WA_REGS))
763 return -ENOSPC;
764
765 dev_priv->workarounds.reg[idx].addr = addr;
766 dev_priv->workarounds.reg[idx].value = val;
767 dev_priv->workarounds.reg[idx].mask = mask;
768
769 dev_priv->workarounds.count++;
770
771 return 0;
86d7f238
AS		 772}
773
ca5a0fbd 774#define WA_REG(addr, mask, val) do { \
cf4b0de6 775 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 776 if (r) \
777 return r; \
ca5a0fbd 778 } while (0)
7225342a
MK		 779
780#define WA_SET_BIT_MASKED(addr, mask) \
26459343 781 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 782
783#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 784 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 785
98533251 786#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 787 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 788
cf4b0de6
DL		 789#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
790#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 791
cf4b0de6 792#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 793
0bc40be8
TU		 794static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
795 i915_reg_t reg)
33136b06 796{
c033666a 797 struct drm_i915_private *dev_priv = engine->i915;
33136b06 798 struct i915_workarounds *wa = &dev_priv->workarounds;
0bc40be8 799 const uint32_t index = wa->hw_whitelist_count[engine->id];
33136b06
AS		 800
801 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
802 return -EINVAL;
803
0bc40be8 804 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
33136b06 805 i915_mmio_reg_offset(reg));
0bc40be8 806 wa->hw_whitelist_count[engine->id]++;
33136b06
AS		 807
808 return 0;
809}
810
0bc40be8 811static int gen8_init_workarounds(struct intel_engine_cs *engine)
e9a64ada 812{
c033666a 813 struct drm_i915_private *dev_priv = engine->i915;
68c6198b
AS		 814
815 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 816
717d84d6
AS		 817 /* WaDisableAsyncFlipPerfMode:bdw,chv */
818 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
819
d0581194
AS		 820 /* WaDisablePartialInstShootdown:bdw,chv */
821 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
822 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
823
a340af58
AS		 824 /* Use Force Non-Coherent whenever executing a 3D context. This is a
825 * workaround for for a possible hang in the unlikely event a TLB
826 * invalidation occurs during a PSD flush.
827 */
828 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 829 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 831 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 832 HDC_FORCE_NON_COHERENT);
833
6def8fdd
AS		 834 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
835 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
836 * polygons in the same 8x4 pixel/sample area to be processed without
837 * stalling waiting for the earlier ones to write to Hierarchical Z
838 * buffer."
839 *
840 * This optimization is off by default for BDW and CHV; turn it on.
841 */
842 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
843
48404636
AS		 844 /* Wa4x4STCOptimizationDisable:bdw,chv */
845 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
846
7eebcde6
AS		 847 /*
848 * BSpec recommends 8x4 when MSAA is used,
849 * however in practice 16x4 seems fastest.
850 *
851 * Note that PS/WM thread counts depend on the WIZ hashing
852 * disable bit, which we don't touch here, but it's good
853 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
854 */
855 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
856 GEN6_WIZ_HASHING_MASK,
857 GEN6_WIZ_HASHING_16x4);
858
e9a64ada
AS		 859 return 0;
860}
861
0bc40be8 862static int bdw_init_workarounds(struct intel_engine_cs *engine)
86d7f238 863{
c033666a 864 struct drm_i915_private *dev_priv = engine->i915;
e9a64ada 865 int ret;
86d7f238 866
0bc40be8 867 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 868 if (ret)
869 return ret;
870
101b376d 871 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 872 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 873
101b376d 874 /* WaDisableDopClockGating:bdw */
7225342a
MK		 875 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
876 DOP_CLOCK_GATING_DISABLE);
86d7f238 877
7225342a
MK		 878 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
879 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 880
7225342a 881 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 882 /* WaForceContextSaveRestoreNonCoherent:bdw */
883 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 884 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
c033666a 885 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 886
86d7f238
AS		 887 return 0;
888}
889
0bc40be8 890static int chv_init_workarounds(struct intel_engine_cs *engine)
00e1e623 891{
c033666a 892 struct drm_i915_private *dev_priv = engine->i915;
e9a64ada 893 int ret;
00e1e623 894
0bc40be8 895 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 896 if (ret)
897 return ret;
898
00e1e623 899 /* WaDisableThreadStallDopClockGating:chv */
d0581194 900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 901
d60de81d
KG		 902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
904
7225342a
MK		 905 return 0;
906}
907
0bc40be8 908static int gen9_init_workarounds(struct intel_engine_cs *engine)
3b106531 909{
c033666a 910 struct drm_i915_private *dev_priv = engine->i915;
e0f3fa09 911 int ret;
ab0dfafe 912
a8ab5ed5
TG		 913 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
914 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
915
e5f81d65 916 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
9c4cbf82
MK		 917 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
918 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
919
e5f81d65 920 /* WaDisableKillLogic:bxt,skl,kbl */
9c4cbf82
MK		 921 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
922 ECOCHK_DIS_TLB);
923
e5f81d65
MK		 924 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
925 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
ab0dfafe 926 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
950b2aae 927 FLOW_CONTROL_ENABLE |
ab0dfafe
HN		 928 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
929
e5f81d65 930 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
8424171e
NH		 931 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
932 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
933
e87a005d 934 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
c033666a
CW		 935 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
936 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
a86eb582
DL		 937 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
938 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 939
e87a005d 940 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
c033666a
CW		 941 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
942 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
183c6dac
DL		 943 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
944 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 945 /*
946 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
947 * but we do that in per ctx batchbuffer as there is an issue
948 * with this register not getting restored on ctx restore
949 */
183c6dac
DL		 950 }
951
e5f81d65
MK		 952 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
953 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
bfd8ad4e
TG		 954 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
955 GEN9_ENABLE_YV12_BUGFIX |
956 GEN9_ENABLE_GPGPU_PREEMPTION);
cac23df4 957
e5f81d65
MK		 958 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
959 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
60294683
AS		 960 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
961 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 962
e5f81d65 963 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
e2db7071
DL		 964 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
965 GEN9_CCS_TLB_PREFETCH_ENABLE);
966
5a2ae95e 967 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
c033666a
CW		 968 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
969 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
38a39a7b
BW		 970 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
971 PIXEL_MASK_CAMMING_DISABLE);
972
5b0e3659
MK		 973 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
974 WA_SET_BIT_MASKED(HDC_CHICKEN0,
975 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
976 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
8ea6f892 977
bbaefe72
MK		 978 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
979 * both tied to WaForceContextSaveRestoreNonCoherent
980 * in some hsds for skl. We keep the tie for all gen9. The
981 * documentation is a bit hazy and so we want to get common behaviour,
982 * even though there is no clear evidence we would need both on kbl/bxt.
983 * This area has been source of system hangs so we play it safe
984 * and mimic the skl regardless of what bspec says.
985 *
986 * Use Force Non-Coherent whenever executing a 3D context. This
987 * is a workaround for a possible hang in the unlikely event
988 * a TLB invalidation occurs during a PSD flush.
989 */
990
991 /* WaForceEnableNonCoherent:skl,bxt,kbl */
992 WA_SET_BIT_MASKED(HDC_CHICKEN0,
993 HDC_FORCE_NON_COHERENT);
994
995 /* WaDisableHDCInvalidation:skl,bxt,kbl */
996 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
997 BDW_DISABLE_HDC_INVALIDATION);
998
e5f81d65
MK		 999 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1000 if (IS_SKYLAKE(dev_priv) ||
1001 IS_KABYLAKE(dev_priv) ||
1002 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
8c761609
AS		 1003 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1004 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 1005
e5f81d65 1006 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
6b6d5626
RB		 1007 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1008
e5f81d65 1009 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
6ecf56ae
AS		 1010 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1011 GEN8_LQSC_FLUSH_COHERENT_LINES));
1012
6bb62855 1013 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1014 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1015 if (ret)
1016 return ret;
1017
e5f81d65 1018 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
0bc40be8 1019 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
e0f3fa09
AS		 1020 if (ret)
1021 return ret;
1022
e5f81d65 1023 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
0bc40be8 1024 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
3669ab61
AS		 1025 if (ret)
1026 return ret;
1027
3b106531
HN		 1028 return 0;
1029}
1030
0bc40be8 1031static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
b7668791 1032{
c033666a 1033 struct drm_i915_private *dev_priv = engine->i915;
b7668791
DL		 1034 u8 vals[3] = { 0, 0, 0 };
1035 unsigned int i;
1036
1037 for (i = 0; i < 3; i++) {
1038 u8 ss;
1039
1040 /*
1041 * Only consider slices where one, and only one, subslice has 7
1042 * EUs
1043 */
a4d8a0fe 1044 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
b7668791
DL		 1045 continue;
1046
1047 /*
1048 * subslice_7eu[i] != 0 (because of the check above) and
1049 * ss_max == 4 (maximum number of subslices possible per slice)
1050 *
1051 * -> 0 <= ss <= 3;
1052 */
1053 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1054 vals[i] = 3 - ss;
1055 }
1056
1057 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1058 return 0;
1059
1060 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1061 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1062 GEN9_IZ_HASHING_MASK(2) |
1063 GEN9_IZ_HASHING_MASK(1) |
1064 GEN9_IZ_HASHING_MASK(0),
1065 GEN9_IZ_HASHING(2, vals[2]) |
1066 GEN9_IZ_HASHING(1, vals[1]) |
1067 GEN9_IZ_HASHING(0, vals[0]));
1068
1069 return 0;
1070}
1071
0bc40be8 1072static int skl_init_workarounds(struct intel_engine_cs *engine)
8d205494 1073{
c033666a 1074 struct drm_i915_private *dev_priv = engine->i915;
aa0011a8 1075 int ret;
d0bbbc4f 1076
0bc40be8 1077 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1078 if (ret)
1079 return ret;
8d205494 1080
a78536e7
AS		 1081 /*
1082 * Actual WA is to disable percontext preemption granularity control
1083 * until D0 which is the default case so this is equivalent to
1084 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1085 */
c033666a 1086 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
a78536e7
AS		 1087 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1088 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1089 }
1090
71dce58c 1091 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
9c4cbf82
MK		 1092 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1093 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1094 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1095 }
1096
1097 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1098 * involving this register should also be added to WA batch as required.
1099 */
c033666a 1100 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
9c4cbf82
MK		 1101 /* WaDisableLSQCROPERFforOCL:skl */
1102 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1103 GEN8_LQSC_RO_PERF_DIS);
1104
1105 /* WaEnableGapsTsvCreditFix:skl */
c033666a 1106 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1107 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1108 GEN9_GAPS_TSV_CREDIT_DISABLE));
1109 }
1110
d0bbbc4f 1111 /* WaDisablePowerCompilerClockGating:skl */
c033666a 1112 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1113 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1114 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1115
e87a005d 1116 /* WaBarrierPerformanceFixDisable:skl */
c033666a 1117 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1118 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1119 HDC_FENCE_DEST_SLM_DISABLE |
1120 HDC_BARRIER_PERFORMANCE_DISABLE);
1121
9bd9dfb4 1122 /* WaDisableSbeCacheDispatchPortSharing:skl */
c033666a 1123 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1124 WA_SET_BIT_MASKED(
1125 GEN7_HALF_SLICE_CHICKEN1,
1126 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1127
eee8efb0
MK		 1128 /* WaDisableGafsUnitClkGating:skl */
1129 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1130
6107497e 1131 /* WaDisableLSQCROPERFforOCL:skl */
0bc40be8 1132 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
6107497e
AS		 1133 if (ret)
1134 return ret;
1135
0bc40be8 1136 return skl_tune_iz_hashing(engine);
7225342a
MK		 1137}
1138
0bc40be8 1139static int bxt_init_workarounds(struct intel_engine_cs *engine)
cae0437f 1140{
c033666a 1141 struct drm_i915_private *dev_priv = engine->i915;
aa0011a8 1142 int ret;
dfb601e6 1143
0bc40be8 1144 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1145 if (ret)
1146 return ret;
cae0437f 1147
9c4cbf82
MK		 1148 /* WaStoreMultiplePTEenable:bxt */
1149 /* This is a requirement according to Hardware specification */
c033666a 1150 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
9c4cbf82
MK		 1151 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1152
1153 /* WaSetClckGatingDisableMedia:bxt */
c033666a 1154 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
9c4cbf82
MK		 1155 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1156 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1157 }
1158
dfb601e6
NH		 1159 /* WaDisableThreadStallDopClockGating:bxt */
1160 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1161 STALL_DOP_GATING_DISABLE);
1162
983b4b9d 1163 /* WaDisableSbeCacheDispatchPortSharing:bxt */
c033666a 1164 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1165 WA_SET_BIT_MASKED(
1166 GEN7_HALF_SLICE_CHICKEN1,
1167 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1168 }
1169
2c8580e4
AS		 1170 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1171 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1172 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
a786d53a 1173 /* WaDisableLSQCROPERFforOCL:bxt */
c033666a 1174 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
0bc40be8 1175 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
2c8580e4
AS		 1176 if (ret)
1177 return ret;
a786d53a 1178
0bc40be8 1179 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
a786d53a
AS		 1180 if (ret)
1181 return ret;
2c8580e4
AS		 1182 }
1183
050fc465 1184 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
c033666a 1185 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
36579cb6
ID		 1186 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1187 L3_HIGH_PRIO_CREDITS(2));
050fc465 1188
ad2bdb44
MK		 1189 /* WaInsertDummyPushConstPs:bxt */
1190 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1191 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1192 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1193
cae0437f
NH		 1194 return 0;
1195}
1196
e5f81d65
MK		 1197static int kbl_init_workarounds(struct intel_engine_cs *engine)
1198{
e587f6cb 1199 struct drm_i915_private *dev_priv = engine->i915;
e5f81d65
MK		 1200 int ret;
1201
1202 ret = gen9_init_workarounds(engine);
1203 if (ret)
1204 return ret;
1205
e587f6cb
MK		 1206 /* WaEnableGapsTsvCreditFix:kbl */
1207 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1208 GEN9_GAPS_TSV_CREDIT_DISABLE));
1209
c0b730d5
MK		 1210 /* WaDisableDynamicCreditSharing:kbl */
1211 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1212 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1213 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1214
8401d42f
MK		 1215 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1216 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1217 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1218 HDC_FENCE_DEST_SLM_DISABLE);
1219
fe905819
MK		 1220 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1221 * involving this register should also be added to WA batch as required.
1222 */
1223 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1224 /* WaDisableLSQCROPERFforOCL:kbl */
1225 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1226 GEN8_LQSC_RO_PERF_DIS);
1227
ad2bdb44
MK		 1228 /* WaInsertDummyPushConstPs:kbl */
1229 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1230 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1231 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1232
4de5d7cc
MK		 1233 /* WaDisableGafsUnitClkGating:kbl */
1234 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1235
954337aa
MK		 1236 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1237 WA_SET_BIT_MASKED(
1238 GEN7_HALF_SLICE_CHICKEN1,
1239 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1240
fe905819
MK		 1241 /* WaDisableLSQCROPERFforOCL:kbl */
1242 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1243 if (ret)
1244 return ret;
1245
e5f81d65
MK		 1246 return 0;
1247}
1248
0bc40be8 1249int init_workarounds_ring(struct intel_engine_cs *engine)
7225342a 1250{
c033666a 1251 struct drm_i915_private *dev_priv = engine->i915;
7225342a 1252
0bc40be8 1253 WARN_ON(engine->id != RCS);
7225342a
MK		 1254
1255 dev_priv->workarounds.count = 0;
33136b06 1256 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
7225342a 1257
c033666a 1258 if (IS_BROADWELL(dev_priv))
0bc40be8 1259 return bdw_init_workarounds(engine);
7225342a 1260
c033666a 1261 if (IS_CHERRYVIEW(dev_priv))
0bc40be8 1262 return chv_init_workarounds(engine);
00e1e623 1263
c033666a 1264 if (IS_SKYLAKE(dev_priv))
0bc40be8 1265 return skl_init_workarounds(engine);
cae0437f 1266
c033666a 1267 if (IS_BROXTON(dev_priv))
0bc40be8 1268 return bxt_init_workarounds(engine);
3b106531 1269
e5f81d65
MK		 1270 if (IS_KABYLAKE(dev_priv))
1271 return kbl_init_workarounds(engine);
1272
00e1e623
VS		 1273 return 0;
1274}
1275
0bc40be8 1276static int init_render_ring(struct intel_engine_cs *engine)
8187a2b7 1277{
c033666a 1278 struct drm_i915_private *dev_priv = engine->i915;
0bc40be8 1279 int ret = init_ring_common(engine);
9c33baa6
KZ		 1280 if (ret)
1281 return ret;
a69ffdbf 1282
61a563a2 1283 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
ac657f64 1284 if (IS_GEN(dev_priv, 4, 6))
6b26c86d 1285 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1286
1287 /* We need to disable the AsyncFlip performance optimisations in order
1288 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1289 * programmed to '1' on all products.
8693a824 1290 *
2441f877 1291 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1292 */
ac657f64 1293 if (IS_GEN(dev_priv, 6, 7))
1c8c38c5
CW		 1294 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1295
f05bb0c7 1296 /* Required for the hardware to program scanline values for waiting */
01fa0302 1297 /* WaEnableFlushTlbInvalidationMode:snb */
c033666a 1298 if (IS_GEN6(dev_priv))
f05bb0c7 1299 I915_WRITE(GFX_MODE,
aa83e30d 1300 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1301
01fa0302 1302 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
c033666a 1303 if (IS_GEN7(dev_priv))
1c8c38c5 1304 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1305 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1306 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1307
c033666a 1308 if (IS_GEN6(dev_priv)) {
3a69ddd6
KG		 1309 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1310 * "If this bit is set, STCunit will have LRA as replacement
1311 * policy. [...] This bit must be reset. LRA replacement
1312 * policy is not supported."
1313 */
1314 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1315 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1316 }
1317
ac657f64 1318 if (IS_GEN(dev_priv, 6, 7))
6b26c86d 1319 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1320
c033666a
CW		 1321 if (HAS_L3_DPF(dev_priv))
1322 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
15b9f80e 1323
0bc40be8 1324 return init_workarounds_ring(engine);
8187a2b7
ZN		 1325}
1326
0bc40be8 1327static void render_ring_cleanup(struct intel_engine_cs *engine)
c6df541c 1328{
c033666a 1329 struct drm_i915_private *dev_priv = engine->i915;
3e78998a
BW		 1330
1331 if (dev_priv->semaphore_obj) {
1332 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1333 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1334 dev_priv->semaphore_obj = NULL;
1335 }
b45305fc 1336
0bc40be8 1337 intel_fini_pipe_control(engine);
c6df541c
CW		 1338}
1339
f7169687 1340static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1341 unsigned int num_dwords)
1342{
1343#define MBOX_UPDATE_DWORDS 8
4a570db5 1344 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1345 struct drm_i915_private *dev_priv = signaller_req->i915;
3e78998a 1346 struct intel_engine_cs *waiter;
c3232b18
DG		 1347 enum intel_engine_id id;
1348 int ret, num_rings;
3e78998a 1349
c033666a 1350 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
3e78998a
BW		 1351 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1352#undef MBOX_UPDATE_DWORDS
1353
5fb9de1a 1354 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1355 if (ret)
1356 return ret;
1357
c3232b18 1358 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1359 u32 seqno;
c3232b18 1360 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1361 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1362 continue;
1363
f7169687 1364 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1365 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1366 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1367 PIPE_CONTROL_QW_WRITE |
f9a4ea35 1368 PIPE_CONTROL_CS_STALL);
3e78998a
BW		 1369 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1370 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1371 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1372 intel_ring_emit(signaller, 0);
1373 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
215a7e32 1374 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1375 intel_ring_emit(signaller, 0);
1376 }
1377
1378 return 0;
1379}
1380
f7169687 1381static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1382 unsigned int num_dwords)
1383{
1384#define MBOX_UPDATE_DWORDS 6
4a570db5 1385 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1386 struct drm_i915_private *dev_priv = signaller_req->i915;
3e78998a 1387 struct intel_engine_cs *waiter;
c3232b18
DG		 1388 enum intel_engine_id id;
1389 int ret, num_rings;
3e78998a 1390
c033666a 1391 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
3e78998a
BW		 1392 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1393#undef MBOX_UPDATE_DWORDS
1394
5fb9de1a 1395 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1396 if (ret)
1397 return ret;
1398
c3232b18 1399 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1400 u32 seqno;
c3232b18 1401 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1402 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1403 continue;
1404
f7169687 1405 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1406 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1407 MI_FLUSH_DW_OP_STOREDW);
1408 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1409 MI_FLUSH_DW_USE_GTT);
1410 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1411 intel_ring_emit(signaller, seqno);
3e78998a 1412 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
215a7e32 1413 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1414 intel_ring_emit(signaller, 0);
1415 }
1416
1417 return 0;
1418}
1419
f7169687 1420static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1421 unsigned int num_dwords)
1ec14ad3 1422{
4a570db5 1423 struct intel_engine_cs *signaller = signaller_req->engine;
c033666a 1424 struct drm_i915_private *dev_priv = signaller_req->i915;
a4872ba6 1425 struct intel_engine_cs *useless;
c3232b18
DG		 1426 enum intel_engine_id id;
1427 int ret, num_rings;
78325f2d 1428
a1444b79 1429#define MBOX_UPDATE_DWORDS 3
c033666a 1430 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
a1444b79
BW		 1431 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1432#undef MBOX_UPDATE_DWORDS
024a43e1 1433
5fb9de1a 1434 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1435 if (ret)
1436 return ret;
024a43e1 1437
c3232b18
DG		 1438 for_each_engine_id(useless, dev_priv, id) {
1439 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
f0f59a00
VS		 1440
1441 if (i915_mmio_reg_valid(mbox_reg)) {
f7169687 1442 u32 seqno = i915_gem_request_get_seqno(signaller_req);
f0f59a00 1443
78325f2d 1444 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
f92a9162 1445 intel_ring_emit_reg(signaller, mbox_reg);
6259cead 1446 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1447 }
1448 }
024a43e1 1449
a1444b79
BW		 1450 /* If num_dwords was rounded, make sure the tail pointer is correct */
1451 if (num_rings % 2 == 0)
1452 intel_ring_emit(signaller, MI_NOOP);
1453
024a43e1 1454 return 0;
1ec14ad3
CW		 1455}
1456
c8c99b0f
BW		 1457/**
1458 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1459 *
1460 * @request - request to write to the ring
c8c99b0f
BW		 1461 *
1462 * Update the mailbox registers in the *other* rings with the current seqno.
1463 * This acts like a signal in the canonical semaphore.
1464 */
1ec14ad3 1465static int
ee044a88 1466gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1467{
4a570db5 1468 struct intel_engine_cs *engine = req->engine;
024a43e1 1469 int ret;
52ed2325 1470
e2f80391
TU		 1471 if (engine->semaphore.signal)
1472 ret = engine->semaphore.signal(req, 4);
707d9cf9 1473 else
5fb9de1a 1474 ret = intel_ring_begin(req, 4);
707d9cf9 1475
1ec14ad3
CW		 1476 if (ret)
1477 return ret;
1478
e2f80391
TU		 1479 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1480 intel_ring_emit(engine,
1481 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1482 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1483 intel_ring_emit(engine, MI_USER_INTERRUPT);
1484 __intel_ring_advance(engine);
1ec14ad3 1485
1ec14ad3
CW		 1486 return 0;
1487}
1488
a58c01aa
CW		 1489static int
1490gen8_render_add_request(struct drm_i915_gem_request *req)
1491{
1492 struct intel_engine_cs *engine = req->engine;
1493 int ret;
1494
1495 if (engine->semaphore.signal)
1496 ret = engine->semaphore.signal(req, 8);
1497 else
1498 ret = intel_ring_begin(req, 8);
1499 if (ret)
1500 return ret;
1501
1502 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1503 intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1504 PIPE_CONTROL_CS_STALL |
1505 PIPE_CONTROL_QW_WRITE));
1506 intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1507 intel_ring_emit(engine, 0);
1508 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1509 /* We're thrashing one dword of HWS. */
1510 intel_ring_emit(engine, 0);
1511 intel_ring_emit(engine, MI_USER_INTERRUPT);
1512 intel_ring_emit(engine, MI_NOOP);
1513 __intel_ring_advance(engine);
1514
1515 return 0;
1516}
1517
c033666a 1518static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
f72b3435
MK		 1519 u32 seqno)
1520{
f72b3435
MK		 1521 return dev_priv->last_seqno < seqno;
1522}
1523
c8c99b0f
BW		 1524/**
1525 * intel_ring_sync - sync the waiter to the signaller on seqno
1526 *
1527 * @waiter - ring that is waiting
1528 * @signaller - ring which has, or will signal
1529 * @seqno - seqno which the waiter will block on
1530 */
5ee426ca
BW		 1531
1532static int
599d924c 1533gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1534 struct intel_engine_cs *signaller,
1535 u32 seqno)
1536{
4a570db5 1537 struct intel_engine_cs *waiter = waiter_req->engine;
c033666a 1538 struct drm_i915_private *dev_priv = waiter_req->i915;
6ef48d7f 1539 struct i915_hw_ppgtt *ppgtt;
5ee426ca
BW		 1540 int ret;
1541
5fb9de1a 1542 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1543 if (ret)
1544 return ret;
1545
1546 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1547 MI_SEMAPHORE_GLOBAL_GTT |
1548 MI_SEMAPHORE_SAD_GTE_SDD);
1549 intel_ring_emit(waiter, seqno);
1550 intel_ring_emit(waiter,
1551 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1552 intel_ring_emit(waiter,
1553 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1554 intel_ring_advance(waiter);
6ef48d7f
CW		 1555
1556 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1557 * pagetables and we must reload them before executing the batch.
1558 * We do this on the i915_switch_context() following the wait and
1559 * before the dispatch.
1560 */
1561 ppgtt = waiter_req->ctx->ppgtt;
1562 if (ppgtt && waiter_req->engine->id != RCS)
1563 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
5ee426ca
BW		 1564 return 0;
1565}
1566
c8c99b0f 1567static int
599d924c 1568gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1569 struct intel_engine_cs *signaller,
686cb5f9 1570 u32 seqno)
1ec14ad3 1571{
4a570db5 1572 struct intel_engine_cs *waiter = waiter_req->engine;
c8c99b0f
BW		 1573 u32 dw1 = MI_SEMAPHORE_MBOX |
1574 MI_SEMAPHORE_COMPARE |
1575 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1576 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1577 int ret;
1ec14ad3 1578
1500f7ea
BW		 1579 /* Throughout all of the GEM code, seqno passed implies our current
1580 * seqno is >= the last seqno executed. However for hardware the
1581 * comparison is strictly greater than.
1582 */
1583 seqno -= 1;
1584
ebc348b2 1585 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1586
5fb9de1a 1587 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1588 if (ret)
1589 return ret;
1590
f72b3435 1591 /* If seqno wrap happened, omit the wait with no-ops */
c033666a 1592 if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
ebc348b2 1593 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1594 intel_ring_emit(waiter, seqno);
1595 intel_ring_emit(waiter, 0);
1596 intel_ring_emit(waiter, MI_NOOP);
1597 } else {
1598 intel_ring_emit(waiter, MI_NOOP);
1599 intel_ring_emit(waiter, MI_NOOP);
1600 intel_ring_emit(waiter, MI_NOOP);
1601 intel_ring_emit(waiter, MI_NOOP);
1602 }
c8c99b0f 1603 intel_ring_advance(waiter);
1ec14ad3
CW		 1604
1605 return 0;
1606}
1607
c6df541c
CW		 1608#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1609do { \
fcbc34e4
KG		 1610 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1611 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1612 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1613 intel_ring_emit(ring__, 0); \
1614 intel_ring_emit(ring__, 0); \
1615} while (0)
1616
1617static int
ee044a88 1618pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1619{
4a570db5 1620 struct intel_engine_cs *engine = req->engine;
e2f80391 1621 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1622 int ret;
1623
1624 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1625 * incoherent with writes to memory, i.e. completely fubar,
1626 * so we need to use PIPE_NOTIFY instead.
1627 *
1628 * However, we also need to workaround the qword write
1629 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1630 * memory before requesting an interrupt.
1631 */
5fb9de1a 1632 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1633 if (ret)
1634 return ret;
1635
e2f80391
TU		 1636 intel_ring_emit(engine,
1637 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1638 PIPE_CONTROL_WRITE_FLUSH |
1639 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
e2f80391
TU		 1640 intel_ring_emit(engine,
1641 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1642 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1643 intel_ring_emit(engine, 0);
1644 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1645 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
e2f80391 1646 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1647 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1648 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1649 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1650 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1651 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1652 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1653 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1654 PIPE_CONTROL_FLUSH(engine, scratch_addr);
a71d8d94 1655
e2f80391
TU		 1656 intel_ring_emit(engine,
1657 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1658 PIPE_CONTROL_WRITE_FLUSH |
1659 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1660 PIPE_CONTROL_NOTIFY);
e2f80391
TU		 1661 intel_ring_emit(engine,
1662 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1663 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1664 intel_ring_emit(engine, 0);
1665 __intel_ring_advance(engine);
c6df541c 1666
c6df541c
CW		 1667 return 0;
1668}
1669
c04e0f3b
CW		 1670static void
1671gen6_seqno_barrier(struct intel_engine_cs *engine)
4cd53c0c 1672{
c033666a 1673 struct drm_i915_private *dev_priv = engine->i915;
bcbdb6d0 1674
4cd53c0c
DV		 1675 /* Workaround to force correct ordering between irq and seqno writes on
1676 * ivb (and maybe also on snb) by reading from a CS register (like
9b9ed309
CW		 1677 * ACTHD) before reading the status page.
1678 *
1679 * Note that this effectively stalls the read by the time it takes to
1680 * do a memory transaction, which more or less ensures that the write
1681 * from the GPU has sufficient time to invalidate the CPU cacheline.
1682 * Alternatively we could delay the interrupt from the CS ring to give
1683 * the write time to land, but that would incur a delay after every
1684 * batch i.e. much more frequent than a delay when waiting for the
1685 * interrupt (with the same net latency).
bcbdb6d0
CW		 1686 *
1687 * Also note that to prevent whole machine hangs on gen7, we have to
1688 * take the spinlock to guard against concurrent cacheline access.
9b9ed309 1689 */
bcbdb6d0 1690 spin_lock_irq(&dev_priv->uncore.lock);
c04e0f3b 1691 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
bcbdb6d0 1692 spin_unlock_irq(&dev_priv->uncore.lock);
4cd53c0c
DV		 1693}
1694
8187a2b7 1695static u32
c04e0f3b 1696ring_get_seqno(struct intel_engine_cs *engine)
8187a2b7 1697{
0bc40be8 1698 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1ec14ad3
CW		 1699}
1700
b70ec5bf 1701static void
0bc40be8 1702ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1703{
0bc40be8 1704 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
b70ec5bf
MK		 1705}
1706
c6df541c 1707static u32
c04e0f3b 1708pc_render_get_seqno(struct intel_engine_cs *engine)
c6df541c 1709{
0bc40be8 1710 return engine->scratch.cpu_page[0];
c6df541c
CW		 1711}
1712
b70ec5bf 1713static void
0bc40be8 1714pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1715{
0bc40be8 1716 engine->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1717}
1718
e48d8634 1719static bool
0bc40be8 1720gen5_ring_get_irq(struct intel_engine_cs *engine)
e48d8634 1721{
c033666a 1722 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1723 unsigned long flags;
e48d8634 1724
7cd512f1 1725 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1726 return false;
1727
7338aefa 1728 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1729 if (engine->irq_refcount++ == 0)
1730 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1731 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1732
1733 return true;
1734}
1735
1736static void
0bc40be8 1737gen5_ring_put_irq(struct intel_engine_cs *engine)
e48d8634 1738{
c033666a 1739 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1740 unsigned long flags;
e48d8634 1741
7338aefa 1742 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1743 if (--engine->irq_refcount == 0)
1744 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1745 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1746}
1747
b13c2b96 1748static bool
0bc40be8 1749i9xx_ring_get_irq(struct intel_engine_cs *engine)
62fdfeaf 1750{
c033666a 1751 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1752 unsigned long flags;
62fdfeaf 1753
7cd512f1 1754 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1755 return false;
1756
7338aefa 1757 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1758 if (engine->irq_refcount++ == 0) {
1759 dev_priv->irq_mask &= ~engine->irq_enable_mask;
f637fde4
DV		 1760 I915_WRITE(IMR, dev_priv->irq_mask);
1761 POSTING_READ(IMR);
1762 }
7338aefa 1763 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1764
1765 return true;
62fdfeaf
EA		 1766}
1767
8187a2b7 1768static void
0bc40be8 1769i9xx_ring_put_irq(struct intel_engine_cs *engine)
62fdfeaf 1770{
c033666a 1771 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1772 unsigned long flags;
62fdfeaf 1773
7338aefa 1774 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1775 if (--engine->irq_refcount == 0) {
1776 dev_priv->irq_mask |= engine->irq_enable_mask;
f637fde4
DV		 1777 I915_WRITE(IMR, dev_priv->irq_mask);
1778 POSTING_READ(IMR);
1779 }
7338aefa 1780 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1781}
1782
c2798b19 1783static bool
0bc40be8 1784i8xx_ring_get_irq(struct intel_engine_cs *engine)
c2798b19 1785{
c033666a 1786 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1787 unsigned long flags;
c2798b19 1788
7cd512f1 1789 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1790 return false;
1791
7338aefa 1792 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1793 if (engine->irq_refcount++ == 0) {
1794 dev_priv->irq_mask &= ~engine->irq_enable_mask;
c2798b19
CW		 1795 I915_WRITE16(IMR, dev_priv->irq_mask);
1796 POSTING_READ16(IMR);
1797 }
7338aefa 1798 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1799
1800 return true;
1801}
1802
1803static void
0bc40be8 1804i8xx_ring_put_irq(struct intel_engine_cs *engine)
c2798b19 1805{
c033666a 1806 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1807 unsigned long flags;
c2798b19 1808
7338aefa 1809 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1810 if (--engine->irq_refcount == 0) {
1811 dev_priv->irq_mask |= engine->irq_enable_mask;
c2798b19
CW		 1812 I915_WRITE16(IMR, dev_priv->irq_mask);
1813 POSTING_READ16(IMR);
1814 }
7338aefa 1815 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1816}
1817
b72f3acb 1818static int
a84c3ae1 1819bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1820 u32 invalidate_domains,
1821 u32 flush_domains)
d1b851fc 1822{
4a570db5 1823 struct intel_engine_cs *engine = req->engine;
b72f3acb
CW		 1824 int ret;
1825
5fb9de1a 1826 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1827 if (ret)
1828 return ret;
1829
e2f80391
TU		 1830 intel_ring_emit(engine, MI_FLUSH);
1831 intel_ring_emit(engine, MI_NOOP);
1832 intel_ring_advance(engine);
b72f3acb 1833 return 0;
d1b851fc
ZN		 1834}
1835
3cce469c 1836static int
ee044a88 1837i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1838{
4a570db5 1839 struct intel_engine_cs *engine = req->engine;
3cce469c
CW		 1840 int ret;
1841
5fb9de1a 1842 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1843 if (ret)
1844 return ret;
6f392d54 1845
e2f80391
TU		 1846 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1847 intel_ring_emit(engine,
1848 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1849 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1850 intel_ring_emit(engine, MI_USER_INTERRUPT);
1851 __intel_ring_advance(engine);
d1b851fc 1852
3cce469c 1853 return 0;
d1b851fc
ZN		 1854}
1855
0f46832f 1856static bool
0bc40be8 1857gen6_ring_get_irq(struct intel_engine_cs *engine)
0f46832f 1858{
c033666a 1859 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1860 unsigned long flags;
0f46832f 1861
7cd512f1
DV		 1862 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1863 return false;
0f46832f 1864
7338aefa 1865 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1866 if (engine->irq_refcount++ == 0) {
c033666a 1867 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
0bc40be8
TU		 1868 I915_WRITE_IMR(engine,
1869 ~(engine->irq_enable_mask |
c033666a 1870 GT_PARITY_ERROR(dev_priv)));
15b9f80e 1871 else
0bc40be8
TU		 1872 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1873 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
0f46832f 1874 }
7338aefa 1875 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1876
1877 return true;
1878}
1879
1880static void
0bc40be8 1881gen6_ring_put_irq(struct intel_engine_cs *engine)
0f46832f 1882{
c033666a 1883 struct drm_i915_private *dev_priv = engine->i915;
7338aefa 1884 unsigned long flags;
0f46832f 1885
7338aefa 1886 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1887 if (--engine->irq_refcount == 0) {
c033666a
CW		 1888 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1889 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
15b9f80e 1890 else
0bc40be8
TU		 1891 I915_WRITE_IMR(engine, ~0);
1892 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1ec14ad3 1893 }
7338aefa 1894 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1895}
1896
a19d2933 1897static bool
0bc40be8 1898hsw_vebox_get_irq(struct intel_engine_cs *engine)
a19d2933 1899{
c033666a 1900 struct drm_i915_private *dev_priv = engine->i915;
a19d2933
BW		 1901 unsigned long flags;
1902
7cd512f1 1903 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1904 return false;
1905
59cdb63d 1906 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1907 if (engine->irq_refcount++ == 0) {
1908 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1909 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1910 }
59cdb63d 1911 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1912
1913 return true;
1914}
1915
1916static void
0bc40be8 1917hsw_vebox_put_irq(struct intel_engine_cs *engine)
a19d2933 1918{
c033666a 1919 struct drm_i915_private *dev_priv = engine->i915;
a19d2933
BW		 1920 unsigned long flags;
1921
59cdb63d 1922 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1923 if (--engine->irq_refcount == 0) {
1924 I915_WRITE_IMR(engine, ~0);
1925 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1926 }
59cdb63d 1927 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1928}
1929
abd58f01 1930static bool
0bc40be8 1931gen8_ring_get_irq(struct intel_engine_cs *engine)
abd58f01 1932{
c033666a 1933 struct drm_i915_private *dev_priv = engine->i915;
abd58f01
BW		 1934 unsigned long flags;
1935
7cd512f1 1936 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1937 return false;
1938
1939 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1940 if (engine->irq_refcount++ == 0) {
c033666a 1941 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
0bc40be8
TU		 1942 I915_WRITE_IMR(engine,
1943 ~(engine->irq_enable_mask |
abd58f01
BW		 1944 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1945 } else {
0bc40be8 1946 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
abd58f01 1947 }
0bc40be8 1948 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1949 }
1950 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1951
1952 return true;
1953}
1954
1955static void
0bc40be8 1956gen8_ring_put_irq(struct intel_engine_cs *engine)
abd58f01 1957{
c033666a 1958 struct drm_i915_private *dev_priv = engine->i915;
abd58f01
BW		 1959 unsigned long flags;
1960
1961 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8 1962 if (--engine->irq_refcount == 0) {
c033666a 1963 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
0bc40be8 1964 I915_WRITE_IMR(engine,
abd58f01
BW		 1965 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1966 } else {
0bc40be8 1967 I915_WRITE_IMR(engine, ~0);
abd58f01 1968 }
0bc40be8 1969 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1970 }
1971 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1972}
1973
d1b851fc 1974static int
53fddaf7 1975i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1976 u64 offset, u32 length,
8e004efc 1977 unsigned dispatch_flags)
d1b851fc 1978{
4a570db5 1979 struct intel_engine_cs *engine = req->engine;
e1f99ce6 1980 int ret;
78501eac 1981
5fb9de1a 1982 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1983 if (ret)
1984 return ret;
1985
e2f80391 1986 intel_ring_emit(engine,
65f56876
CW		 1987 MI_BATCH_BUFFER_START |
1988 MI_BATCH_GTT |
8e004efc
JH		 1989 (dispatch_flags & I915_DISPATCH_SECURE ?
1990 0 : MI_BATCH_NON_SECURE_I965));
e2f80391
TU		 1991 intel_ring_emit(engine, offset);
1992 intel_ring_advance(engine);
78501eac 1993
d1b851fc
ZN		 1994 return 0;
1995}
1996
b45305fc
DV		 1997/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1998#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1999#define I830_TLB_ENTRIES (2)
2000#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 2001static int
53fddaf7 2002i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2003 u64 offset, u32 len,
2004 unsigned dispatch_flags)
62fdfeaf 2005{
4a570db5 2006 struct intel_engine_cs *engine = req->engine;
e2f80391 2007 u32 cs_offset = engine->scratch.gtt_offset;
c4e7a414 2008 int ret;
62fdfeaf 2009
5fb9de1a 2010 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 2011 if (ret)
2012 return ret;
62fdfeaf 2013
c4d69da1 2014 /* Evict the invalid PTE TLBs */
e2f80391
TU		 2015 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
2016 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
2017 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
2018 intel_ring_emit(engine, cs_offset);
2019 intel_ring_emit(engine, 0xdeadbeef);
2020 intel_ring_emit(engine, MI_NOOP);
2021 intel_ring_advance(engine);
b45305fc 2022
8e004efc 2023 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 2024 if (len > I830_BATCH_LIMIT)
2025 return -ENOSPC;
2026
5fb9de1a 2027 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 2028 if (ret)
2029 return ret;
c4d69da1
CW		 2030
2031 /* Blit the batch (which has now all relocs applied) to the
2032 * stable batch scratch bo area (so that the CS never
2033 * stumbles over its tlb invalidation bug) ...
2034 */
e2f80391
TU		 2035 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
2036 intel_ring_emit(engine,
2037 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
2038 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2039 intel_ring_emit(engine, cs_offset);
2040 intel_ring_emit(engine, 4096);
2041 intel_ring_emit(engine, offset);
2042
2043 intel_ring_emit(engine, MI_FLUSH);
2044 intel_ring_emit(engine, MI_NOOP);
2045 intel_ring_advance(engine);
b45305fc
DV		 2046
2047 /* ... and execute it. */
c4d69da1 2048 offset = cs_offset;
b45305fc 2049 }
e1f99ce6 2050
9d611c03 2051 ret = intel_ring_begin(req, 2);
c4d69da1
CW		 2052 if (ret)
2053 return ret;
2054
e2f80391
TU		 2055 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2056 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2057 0 : MI_BATCH_NON_SECURE));
2058 intel_ring_advance(engine);
c4d69da1 2059
fb3256da
DV		 2060 return 0;
2061}
2062
2063static int
53fddaf7 2064i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2065 u64 offset, u32 len,
8e004efc 2066 unsigned dispatch_flags)
fb3256da 2067{
4a570db5 2068 struct intel_engine_cs *engine = req->engine;
fb3256da
DV		 2069 int ret;
2070
5fb9de1a 2071 ret = intel_ring_begin(req, 2);
fb3256da
DV		 2072 if (ret)
2073 return ret;
2074
e2f80391
TU		 2075 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2076 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2077 0 : MI_BATCH_NON_SECURE));
2078 intel_ring_advance(engine);
62fdfeaf 2079
62fdfeaf
EA		 2080 return 0;
2081}
2082
0bc40be8 2083static void cleanup_phys_status_page(struct intel_engine_cs *engine)
7d3fdfff 2084{
c033666a 2085 struct drm_i915_private *dev_priv = engine->i915;
7d3fdfff
VS		 2086
2087 if (!dev_priv->status_page_dmah)
2088 return;
2089
c033666a 2090 drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
0bc40be8 2091 engine->status_page.page_addr = NULL;
7d3fdfff
VS		 2092}
2093
0bc40be8 2094static void cleanup_status_page(struct intel_engine_cs *engine)
62fdfeaf 2095{
05394f39 2096 struct drm_i915_gem_object *obj;
62fdfeaf 2097
0bc40be8 2098 obj = engine->status_page.obj;
8187a2b7 2099 if (obj == NULL)
62fdfeaf 2100 return;
62fdfeaf 2101
9da3da66 2102 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 2103 i915_gem_object_ggtt_unpin(obj);
05394f39 2104 drm_gem_object_unreference(&obj->base);
0bc40be8 2105 engine->status_page.obj = NULL;
62fdfeaf
EA		 2106}
2107
0bc40be8 2108static int init_status_page(struct intel_engine_cs *engine)
62fdfeaf 2109{
0bc40be8 2110 struct drm_i915_gem_object *obj = engine->status_page.obj;
62fdfeaf 2111
7d3fdfff 2112 if (obj == NULL) {
1f767e02 2113 unsigned flags;
e3efda49 2114 int ret;
e4ffd173 2115
c033666a 2116 obj = i915_gem_object_create(engine->i915->dev, 4096);
fe3db79b 2117 if (IS_ERR(obj)) {
e3efda49 2118 DRM_ERROR("Failed to allocate status page\n");
fe3db79b 2119 return PTR_ERR(obj);
e3efda49 2120 }
62fdfeaf 2121
e3efda49
CW		 2122 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2123 if (ret)
2124 goto err_unref;
2125
1f767e02 2126 flags = 0;
c033666a 2127 if (!HAS_LLC(engine->i915))
1f767e02
CW		 2128 /* On g33, we cannot place HWS above 256MiB, so
2129 * restrict its pinning to the low mappable arena.
2130 * Though this restriction is not documented for
2131 * gen4, gen5, or byt, they also behave similarly
2132 * and hang if the HWS is placed at the top of the
2133 * GTT. To generalise, it appears that all !llc
2134 * platforms have issues with us placing the HWS
2135 * above the mappable region (even though we never
2136 * actualy map it).
2137 */
2138 flags |= PIN_MAPPABLE;
2139 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 2140 if (ret) {
2141err_unref:
2142 drm_gem_object_unreference(&obj->base);
2143 return ret;
2144 }
2145
0bc40be8 2146 engine->status_page.obj = obj;
e3efda49 2147 }
62fdfeaf 2148
0bc40be8
TU		 2149 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2150 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2151 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 2152
8187a2b7 2153 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
0bc40be8 2154 engine->name, engine->status_page.gfx_addr);
62fdfeaf
EA		 2155
2156 return 0;
62fdfeaf
EA		 2157}
2158
0bc40be8 2159static int init_phys_status_page(struct intel_engine_cs *engine)
6b8294a4 2160{
c033666a 2161 struct drm_i915_private *dev_priv = engine->i915;
6b8294a4
CW		 2162
2163 if (!dev_priv->status_page_dmah) {
2164 dev_priv->status_page_dmah =
c033666a 2165 drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
6b8294a4
CW		 2166 if (!dev_priv->status_page_dmah)
2167 return -ENOMEM;
2168 }
2169
0bc40be8
TU		 2170 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2171 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
6b8294a4
CW		 2172
2173 return 0;
2174}
2175
7ba717cf 2176void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 2177{
3d77e9be
CW		 2178 GEM_BUG_ON(ringbuf->vma == NULL);
2179 GEM_BUG_ON(ringbuf->virtual_start == NULL);
2180
def0c5f6 2181 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
0a798eb9 2182 i915_gem_object_unpin_map(ringbuf->obj);
def0c5f6 2183 else
3d77e9be 2184 i915_vma_unpin_iomap(ringbuf->vma);
8305216f 2185 ringbuf->virtual_start = NULL;
3d77e9be 2186
2919d291 2187 i915_gem_object_ggtt_unpin(ringbuf->obj);
3d77e9be 2188 ringbuf->vma = NULL;
7ba717cf
TD		 2189}
2190
c033666a 2191int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
7ba717cf
TD		 2192 struct intel_ringbuffer *ringbuf)
2193{
7ba717cf 2194 struct drm_i915_gem_object *obj = ringbuf->obj;
a687a43a
CW		 2195 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2196 unsigned flags = PIN_OFFSET_BIAS | 4096;
8305216f 2197 void *addr;
7ba717cf
TD		 2198 int ret;
2199
def0c5f6 2200 if (HAS_LLC(dev_priv) && !obj->stolen) {
a687a43a 2201 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
def0c5f6
CW		 2202 if (ret)
2203 return ret;
7ba717cf 2204
def0c5f6 2205 ret = i915_gem_object_set_to_cpu_domain(obj, true);
d2cad535
CW		 2206 if (ret)
2207 goto err_unpin;
def0c5f6 2208
8305216f
DG		 2209 addr = i915_gem_object_pin_map(obj);
2210 if (IS_ERR(addr)) {
2211 ret = PTR_ERR(addr);
d2cad535 2212 goto err_unpin;
def0c5f6
CW		 2213 }
2214 } else {
a687a43a
CW		 2215 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2216 flags | PIN_MAPPABLE);
def0c5f6
CW		 2217 if (ret)
2218 return ret;
7ba717cf 2219
def0c5f6 2220 ret = i915_gem_object_set_to_gtt_domain(obj, true);
d2cad535
CW		 2221 if (ret)
2222 goto err_unpin;
def0c5f6 2223
ff3dc087
DCS		 2224 /* Access through the GTT requires the device to be awake. */
2225 assert_rpm_wakelock_held(dev_priv);
2226
3d77e9be
CW		 2227 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2228 if (IS_ERR(addr)) {
2229 ret = PTR_ERR(addr);
d2cad535 2230 goto err_unpin;
def0c5f6 2231 }
7ba717cf
TD		 2232 }
2233
8305216f 2234 ringbuf->virtual_start = addr;
0eb973d3 2235 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
7ba717cf 2236 return 0;
d2cad535
CW		 2237
2238err_unpin:
2239 i915_gem_object_ggtt_unpin(obj);
2240 return ret;
7ba717cf
TD		 2241}
2242
01101fa7 2243static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2244{
2919d291
OM		 2245 drm_gem_object_unreference(&ringbuf->obj->base);
2246 ringbuf->obj = NULL;
2247}
2248
01101fa7
CW		 2249static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2250 struct intel_ringbuffer *ringbuf)
62fdfeaf 2251{
05394f39 2252 struct drm_i915_gem_object *obj;
62fdfeaf 2253
ebc052e0
CW		 2254 obj = NULL;
2255 if (!HAS_LLC(dev))
93b0a4e0 2256 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2257 if (obj == NULL)
d37cd8a8 2258 obj = i915_gem_object_create(dev, ringbuf->size);
fe3db79b
CW		 2259 if (IS_ERR(obj))
2260 return PTR_ERR(obj);
8187a2b7 2261
24f3a8cf
AG		 2262 /* mark ring buffers as read-only from GPU side by default */
2263 obj->gt_ro = 1;
2264
93b0a4e0 2265 ringbuf->obj = obj;
e3efda49 2266
7ba717cf 2267 return 0;
e3efda49
CW		 2268}
2269
01101fa7
CW		 2270struct intel_ringbuffer *
2271intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2272{
2273 struct intel_ringbuffer *ring;
2274 int ret;
2275
2276 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2277 if (ring == NULL) {
2278 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2279 engine->name);
01101fa7 2280 return ERR_PTR(-ENOMEM);
608c1a52 2281 }
01101fa7 2282
4a570db5 2283 ring->engine = engine;
608c1a52 2284 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2285
2286 ring->size = size;
2287 /* Workaround an erratum on the i830 which causes a hang if
2288 * the TAIL pointer points to within the last 2 cachelines
2289 * of the buffer.
2290 */
2291 ring->effective_size = size;
c033666a 2292 if (IS_I830(engine->i915) || IS_845G(engine->i915))
01101fa7
CW		 2293 ring->effective_size -= 2 * CACHELINE_BYTES;
2294
2295 ring->last_retired_head = -1;
2296 intel_ring_update_space(ring);
2297
c033666a 2298 ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
01101fa7 2299 if (ret) {
608c1a52
CW		 2300 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2301 engine->name, ret);
2302 list_del(&ring->link);
01101fa7
CW		 2303 kfree(ring);
2304 return ERR_PTR(ret);
2305 }
2306
2307 return ring;
2308}
2309
2310void
2311intel_ringbuffer_free(struct intel_ringbuffer *ring)
2312{
2313 intel_destroy_ringbuffer_obj(ring);
608c1a52 2314 list_del(&ring->link);
01101fa7
CW		 2315 kfree(ring);
2316}
2317
e3efda49 2318static int intel_init_ring_buffer(struct drm_device *dev,
0bc40be8 2319 struct intel_engine_cs *engine)
e3efda49 2320{
c033666a 2321 struct drm_i915_private *dev_priv = to_i915(dev);
bfc882b4 2322 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2323 int ret;
2324
0bc40be8 2325 WARN_ON(engine->buffer);
bfc882b4 2326
c033666a 2327 engine->i915 = dev_priv;
0bc40be8
TU		 2328 INIT_LIST_HEAD(&engine->active_list);
2329 INIT_LIST_HEAD(&engine->request_list);
2330 INIT_LIST_HEAD(&engine->execlist_queue);
2331 INIT_LIST_HEAD(&engine->buffers);
2332 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2333 memset(engine->semaphore.sync_seqno, 0,
2334 sizeof(engine->semaphore.sync_seqno));
e3efda49 2335
0bc40be8 2336 init_waitqueue_head(&engine->irq_queue);
e3efda49 2337
0bc40be8 2338 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
b0366a54
DG		 2339 if (IS_ERR(ringbuf)) {
2340 ret = PTR_ERR(ringbuf);
2341 goto error;
2342 }
0bc40be8 2343 engine->buffer = ringbuf;
01101fa7 2344
c033666a 2345 if (I915_NEED_GFX_HWS(dev_priv)) {
0bc40be8 2346 ret = init_status_page(engine);
e3efda49 2347 if (ret)
8ee14975 2348 goto error;
e3efda49 2349 } else {
0bc40be8
TU		 2350 WARN_ON(engine->id != RCS);
2351 ret = init_phys_status_page(engine);
e3efda49 2352 if (ret)
8ee14975 2353 goto error;
e3efda49
CW		 2354 }
2355
c033666a 2356 ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
bfc882b4
DV		 2357 if (ret) {
2358 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
0bc40be8 2359 engine->name, ret);
bfc882b4
DV		 2360 intel_destroy_ringbuffer_obj(ringbuf);
2361 goto error;
e3efda49 2362 }
62fdfeaf 2363
0bc40be8 2364 ret = i915_cmd_parser_init_ring(engine);
44e895a8 2365 if (ret)
8ee14975
OM		 2366 goto error;
2367
8ee14975 2368 return 0;
351e3db2 2369
8ee14975 2370error:
117897f4 2371 intel_cleanup_engine(engine);
8ee14975 2372 return ret;
62fdfeaf
EA		 2373}
2374
117897f4 2375void intel_cleanup_engine(struct intel_engine_cs *engine)
62fdfeaf 2376{
6402c330 2377 struct drm_i915_private *dev_priv;
33626e6a 2378
117897f4 2379 if (!intel_engine_initialized(engine))
62fdfeaf
EA		 2380 return;
2381
c033666a 2382 dev_priv = engine->i915;
6402c330 2383
0bc40be8 2384 if (engine->buffer) {
117897f4 2385 intel_stop_engine(engine);
c033666a 2386 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
33626e6a 2387
0bc40be8
TU		 2388 intel_unpin_ringbuffer_obj(engine->buffer);
2389 intel_ringbuffer_free(engine->buffer);
2390 engine->buffer = NULL;
b0366a54 2391 }
78501eac 2392
0bc40be8
TU		 2393 if (engine->cleanup)
2394 engine->cleanup(engine);
8d19215b 2395
c033666a 2396 if (I915_NEED_GFX_HWS(dev_priv)) {
0bc40be8 2397 cleanup_status_page(engine);
7d3fdfff 2398 } else {
0bc40be8
TU		 2399 WARN_ON(engine->id != RCS);
2400 cleanup_phys_status_page(engine);
7d3fdfff 2401 }
44e895a8 2402
0bc40be8
TU		 2403 i915_cmd_parser_fini_ring(engine);
2404 i915_gem_batch_pool_fini(&engine->batch_pool);
c033666a 2405 engine->i915 = NULL;
62fdfeaf
EA		 2406}
2407
666796da 2408int intel_engine_idle(struct intel_engine_cs *engine)
3e960501 2409{
a4b3a571 2410 struct drm_i915_gem_request *req;
3e960501 2411
3e960501 2412 /* Wait upon the last request to be completed */
0bc40be8 2413 if (list_empty(&engine->request_list))
3e960501
CW		 2414 return 0;
2415
0bc40be8
TU		 2416 req = list_entry(engine->request_list.prev,
2417 struct drm_i915_gem_request,
2418 list);
b4716185
CW		 2419
2420 /* Make sure we do not trigger any retires */
2421 return __i915_wait_request(req,
c19ae989 2422 req->i915->mm.interruptible,
b4716185 2423 NULL, NULL);
3e960501
CW		 2424}
2425
6689cb2b 2426int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2427{
6310346e
CW		 2428 int ret;
2429
2430 /* Flush enough space to reduce the likelihood of waiting after
2431 * we start building the request - in which case we will just
2432 * have to repeat work.
2433 */
a0442461 2434 request->reserved_space += LEGACY_REQUEST_SIZE;
6310346e 2435
4a570db5 2436 request->ringbuf = request->engine->buffer;
6310346e
CW		 2437
2438 ret = intel_ring_begin(request, 0);
2439 if (ret)
2440 return ret;
2441
a0442461 2442 request->reserved_space -= LEGACY_REQUEST_SIZE;
6310346e 2443 return 0;
9d773091
CW		 2444}
2445
987046ad
CW		 2446static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2447{
2448 struct intel_ringbuffer *ringbuf = req->ringbuf;
2449 struct intel_engine_cs *engine = req->engine;
2450 struct drm_i915_gem_request *target;
2451
2452 intel_ring_update_space(ringbuf);
2453 if (ringbuf->space >= bytes)
2454 return 0;
2455
2456 /*
2457 * Space is reserved in the ringbuffer for finalising the request,
2458 * as that cannot be allowed to fail. During request finalisation,
2459 * reserved_space is set to 0 to stop the overallocation and the
2460 * assumption is that then we never need to wait (which has the
2461 * risk of failing with EINTR).
2462 *
2463 * See also i915_gem_request_alloc() and i915_add_request().
2464 */
0251a963 2465 GEM_BUG_ON(!req->reserved_space);
987046ad
CW		 2466
2467 list_for_each_entry(target, &engine->request_list, list) {
2468 unsigned space;
2469
79bbcc29 2470 /*
987046ad
CW		 2471 * The request queue is per-engine, so can contain requests
2472 * from multiple ringbuffers. Here, we must ignore any that
2473 * aren't from the ringbuffer we're considering.
79bbcc29 2474 */
987046ad
CW		 2475 if (target->ringbuf != ringbuf)
2476 continue;
2477
2478 /* Would completion of this request free enough space? */
2479 space = __intel_ring_space(target->postfix, ringbuf->tail,
2480 ringbuf->size);
2481 if (space >= bytes)
2482 break;
79bbcc29 2483 }
29b1b415 2484
987046ad
CW		 2485 if (WARN_ON(&target->list == &engine->request_list))
2486 return -ENOSPC;
2487
2488 return i915_wait_request(target);
29b1b415
JH		 2489}
2490
987046ad 2491int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
cbcc80df 2492{
987046ad 2493 struct intel_ringbuffer *ringbuf = req->ringbuf;
79bbcc29 2494 int remain_actual = ringbuf->size - ringbuf->tail;
987046ad
CW		 2495 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2496 int bytes = num_dwords * sizeof(u32);
2497 int total_bytes, wait_bytes;
79bbcc29 2498 bool need_wrap = false;
29b1b415 2499
0251a963 2500 total_bytes = bytes + req->reserved_space;
29b1b415 2501
79bbcc29
JH		 2502 if (unlikely(bytes > remain_usable)) {
2503 /*
2504 * Not enough space for the basic request. So need to flush
2505 * out the remainder and then wait for base + reserved.
2506 */
2507 wait_bytes = remain_actual + total_bytes;
2508 need_wrap = true;
987046ad
CW		 2509 } else if (unlikely(total_bytes > remain_usable)) {
2510 /*
2511 * The base request will fit but the reserved space
2512 * falls off the end. So we don't need an immediate wrap
2513 * and only need to effectively wait for the reserved
2514 * size space from the start of ringbuffer.
2515 */
0251a963 2516 wait_bytes = remain_actual + req->reserved_space;
79bbcc29 2517 } else {
987046ad
CW		 2518 /* No wrapping required, just waiting. */
2519 wait_bytes = total_bytes;
cbcc80df
MK		 2520 }
2521
987046ad
CW		 2522 if (wait_bytes > ringbuf->space) {
2523 int ret = wait_for_space(req, wait_bytes);
cbcc80df
MK		 2524 if (unlikely(ret))
2525 return ret;
79bbcc29 2526
987046ad 2527 intel_ring_update_space(ringbuf);
e075a32f
CW		 2528 if (unlikely(ringbuf->space < wait_bytes))
2529 return -EAGAIN;
cbcc80df
MK		 2530 }
2531
987046ad
CW		 2532 if (unlikely(need_wrap)) {
2533 GEM_BUG_ON(remain_actual > ringbuf->space);
2534 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
78501eac 2535
987046ad
CW		 2536 /* Fill the tail with MI_NOOP */
2537 memset(ringbuf->virtual_start + ringbuf->tail,
2538 0, remain_actual);
2539 ringbuf->tail = 0;
2540 ringbuf->space -= remain_actual;
2541 }
304d695c 2542
987046ad
CW		 2543 ringbuf->space -= bytes;
2544 GEM_BUG_ON(ringbuf->space < 0);
304d695c 2545 return 0;
8187a2b7 2546}
78501eac 2547
753b1ad4 2548/* Align the ring tail to a cacheline boundary */
bba09b12 2549int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2550{
4a570db5 2551 struct intel_engine_cs *engine = req->engine;
e2f80391 2552 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2553 int ret;
2554
2555 if (num_dwords == 0)
2556 return 0;
2557
18393f63 2558 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2559 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2560 if (ret)
2561 return ret;
2562
2563 while (num_dwords--)
e2f80391 2564 intel_ring_emit(engine, MI_NOOP);
753b1ad4 2565
e2f80391 2566 intel_ring_advance(engine);
753b1ad4
VS		 2567
2568 return 0;
2569}
2570
0bc40be8 2571void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
498d2ac1 2572{
c033666a 2573 struct drm_i915_private *dev_priv = engine->i915;
498d2ac1 2574
29dcb570
CW		 2575 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2576 * so long as the semaphore value in the register/page is greater
2577 * than the sync value), so whenever we reset the seqno,
2578 * so long as we reset the tracking semaphore value to 0, it will
2579 * always be before the next request's seqno. If we don't reset
2580 * the semaphore value, then when the seqno moves backwards all
2581 * future waits will complete instantly (causing rendering corruption).
2582 */
7e22dbbb 2583 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
0bc40be8
TU		 2584 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2585 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
d04bce48 2586 if (HAS_VEBOX(dev_priv))
0bc40be8 2587 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
e1f99ce6 2588 }
a058d934
CW		 2589 if (dev_priv->semaphore_obj) {
2590 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2591 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2592 void *semaphores = kmap(page);
2593 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2594 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2595 kunmap(page);
2596 }
29dcb570
CW		 2597 memset(engine->semaphore.sync_seqno, 0,
2598 sizeof(engine->semaphore.sync_seqno));
d97ed339 2599
0bc40be8 2600 engine->set_seqno(engine, seqno);
01347126 2601 engine->last_submitted_seqno = seqno;
29dcb570 2602
0bc40be8 2603 engine->hangcheck.seqno = seqno;
8187a2b7 2604}
62fdfeaf 2605
0bc40be8 2606static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 2607 u32 value)
881f47b6 2608{
c033666a 2609 struct drm_i915_private *dev_priv = engine->i915;
881f47b6
XH		 2610
2611 /* Every tail move must follow the sequence below */
12f55818
CW		 2612
2613 /* Disable notification that the ring is IDLE. The GT
2614 * will then assume that it is busy and bring it out of rc6.
2615 */
0206e353 2616 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2617 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2618
2619 /* Clear the context id. Here be magic! */
2620 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2621
12f55818 2622 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2623 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2624 GEN6_BSD_SLEEP_INDICATOR) == 0,
2625 50))
2626 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2627
12f55818 2628 /* Now that the ring is fully powered up, update the tail */
0bc40be8
TU		 2629 I915_WRITE_TAIL(engine, value);
2630 POSTING_READ(RING_TAIL(engine->mmio_base));
12f55818
CW		 2631
2632 /* Let the ring send IDLE messages to the GT again,
2633 * and so let it sleep to conserve power when idle.
2634 */
0206e353 2635 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2636 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2637}
2638
a84c3ae1 2639static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2640 u32 invalidate, u32 flush)
881f47b6 2641{
4a570db5 2642 struct intel_engine_cs *engine = req->engine;
71a77e07 2643 uint32_t cmd;
b72f3acb
CW		 2644 int ret;
2645
5fb9de1a 2646 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2647 if (ret)
2648 return ret;
2649
71a77e07 2650 cmd = MI_FLUSH_DW;
c033666a 2651 if (INTEL_GEN(req->i915) >= 8)
075b3bba 2652 cmd += 1;
f0a1fb10
CW		 2653
2654 /* We always require a command barrier so that subsequent
2655 * commands, such as breadcrumb interrupts, are strictly ordered
2656 * wrt the contents of the write cache being flushed to memory
2657 * (and thus being coherent from the CPU).
2658 */
2659 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2660
9a289771
JB		 2661 /*
2662 * Bspec vol 1c.5 - video engine command streamer:
2663 * "If ENABLED, all TLBs will be invalidated once the flush
2664 * operation is complete. This bit is only valid when the
2665 * Post-Sync Operation field is a value of 1h or 3h."
2666 */
71a77e07 2667 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2668 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2669
e2f80391
TU		 2670 intel_ring_emit(engine, cmd);
2671 intel_ring_emit(engine,
2672 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
c033666a 2673 if (INTEL_GEN(req->i915) >= 8) {
e2f80391
TU		 2674 intel_ring_emit(engine, 0); /* upper addr */
2675 intel_ring_emit(engine, 0); /* value */
075b3bba 2676 } else {
e2f80391
TU		 2677 intel_ring_emit(engine, 0);
2678 intel_ring_emit(engine, MI_NOOP);
075b3bba 2679 }
e2f80391 2680 intel_ring_advance(engine);
b72f3acb 2681 return 0;
881f47b6
XH		 2682}
2683
1c7a0623 2684static int
53fddaf7 2685gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2686 u64 offset, u32 len,
8e004efc 2687 unsigned dispatch_flags)
1c7a0623 2688{
4a570db5 2689 struct intel_engine_cs *engine = req->engine;
e2f80391 2690 bool ppgtt = USES_PPGTT(engine->dev) &&
8e004efc 2691 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2692 int ret;
2693
5fb9de1a 2694 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2695 if (ret)
2696 return ret;
2697
2698 /* FIXME(BDW): Address space and security selectors. */
e2f80391 2699 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
919032ec
AJ		 2700 (dispatch_flags & I915_DISPATCH_RS ?
2701 MI_BATCH_RESOURCE_STREAMER : 0));
e2f80391
TU		 2702 intel_ring_emit(engine, lower_32_bits(offset));
2703 intel_ring_emit(engine, upper_32_bits(offset));
2704 intel_ring_emit(engine, MI_NOOP);
2705 intel_ring_advance(engine);
1c7a0623
BW		 2706
2707 return 0;
2708}
2709
d7d4eedd 2710static int
53fddaf7 2711hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2712 u64 offset, u32 len,
2713 unsigned dispatch_flags)
d7d4eedd 2714{
4a570db5 2715 struct intel_engine_cs *engine = req->engine;
d7d4eedd
CW		 2716 int ret;
2717
5fb9de1a 2718 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2719 if (ret)
2720 return ret;
2721
e2f80391 2722 intel_ring_emit(engine,
77072258 2723 MI_BATCH_BUFFER_START |
8e004efc 2724 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2725 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2726 (dispatch_flags & I915_DISPATCH_RS ?
2727 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd 2728 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2729 intel_ring_emit(engine, offset);
2730 intel_ring_advance(engine);
d7d4eedd
CW		 2731
2732 return 0;
2733}
2734
881f47b6 2735static int
53fddaf7 2736gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2737 u64 offset, u32 len,
8e004efc 2738 unsigned dispatch_flags)
881f47b6 2739{
4a570db5 2740 struct intel_engine_cs *engine = req->engine;
0206e353 2741 int ret;
ab6f8e32 2742
5fb9de1a 2743 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2744 if (ret)
2745 return ret;
e1f99ce6 2746
e2f80391 2747 intel_ring_emit(engine,
d7d4eedd 2748 MI_BATCH_BUFFER_START |
8e004efc
JH		 2749 (dispatch_flags & I915_DISPATCH_SECURE ?
2750 0 : MI_BATCH_NON_SECURE_I965));
0206e353 2751 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2752 intel_ring_emit(engine, offset);
2753 intel_ring_advance(engine);
ab6f8e32 2754
0206e353 2755 return 0;
881f47b6
XH		 2756}
2757
549f7365
CW		 2758/* Blitter support (SandyBridge+) */
2759
a84c3ae1 2760static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2761 u32 invalidate, u32 flush)
8d19215b 2762{
4a570db5 2763 struct intel_engine_cs *engine = req->engine;
71a77e07 2764 uint32_t cmd;
b72f3acb
CW		 2765 int ret;
2766
5fb9de1a 2767 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2768 if (ret)
2769 return ret;
2770
71a77e07 2771 cmd = MI_FLUSH_DW;
c033666a 2772 if (INTEL_GEN(req->i915) >= 8)
075b3bba 2773 cmd += 1;
f0a1fb10
CW		 2774
2775 /* We always require a command barrier so that subsequent
2776 * commands, such as breadcrumb interrupts, are strictly ordered
2777 * wrt the contents of the write cache being flushed to memory
2778 * (and thus being coherent from the CPU).
2779 */
2780 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2781
9a289771
JB		 2782 /*
2783 * Bspec vol 1c.3 - blitter engine command streamer:
2784 * "If ENABLED, all TLBs will be invalidated once the flush
2785 * operation is complete. This bit is only valid when the
2786 * Post-Sync Operation field is a value of 1h or 3h."
2787 */
71a77e07 2788 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2789 cmd |= MI_INVALIDATE_TLB;
e2f80391
TU		 2790 intel_ring_emit(engine, cmd);
2791 intel_ring_emit(engine,
2792 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
c033666a 2793 if (INTEL_GEN(req->i915) >= 8) {
e2f80391
TU		 2794 intel_ring_emit(engine, 0); /* upper addr */
2795 intel_ring_emit(engine, 0); /* value */
075b3bba 2796 } else {
e2f80391
TU		 2797 intel_ring_emit(engine, 0);
2798 intel_ring_emit(engine, MI_NOOP);
075b3bba 2799 }
e2f80391 2800 intel_ring_advance(engine);
fd3da6c9 2801
b72f3acb 2802 return 0;
8d19215b
ZN		 2803}
2804
5c1143bb
XH		 2805int intel_init_render_ring_buffer(struct drm_device *dev)
2806{
4640c4ff 2807 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2808 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
3e78998a
BW		 2809 struct drm_i915_gem_object *obj;
2810 int ret;
5c1143bb 2811
e2f80391
TU		 2812 engine->name = "render ring";
2813 engine->id = RCS;
2814 engine->exec_id = I915_EXEC_RENDER;
215a7e32 2815 engine->hw_id = 0;
e2f80391 2816 engine->mmio_base = RENDER_RING_BASE;
59465b5f 2817
c033666a
CW		 2818 if (INTEL_GEN(dev_priv) >= 8) {
2819 if (i915_semaphore_is_enabled(dev_priv)) {
d37cd8a8 2820 obj = i915_gem_object_create(dev, 4096);
fe3db79b 2821 if (IS_ERR(obj)) {
3e78998a
BW		 2822 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2823 i915.semaphores = 0;
2824 } else {
2825 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2826 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2827 if (ret != 0) {
2828 drm_gem_object_unreference(&obj->base);
2829 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2830 i915.semaphores = 0;
2831 } else
2832 dev_priv->semaphore_obj = obj;
2833 }
2834 }
7225342a 2835
e2f80391 2836 engine->init_context = intel_rcs_ctx_init;
a58c01aa 2837 engine->add_request = gen8_render_add_request;
e2f80391
TU		 2838 engine->flush = gen8_render_ring_flush;
2839 engine->irq_get = gen8_ring_get_irq;
2840 engine->irq_put = gen8_ring_put_irq;
2841 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b 2842 engine->get_seqno = ring_get_seqno;
e2f80391 2843 engine->set_seqno = ring_set_seqno;
c033666a 2844 if (i915_semaphore_is_enabled(dev_priv)) {
3e78998a 2845 WARN_ON(!dev_priv->semaphore_obj);
e2f80391
TU		 2846 engine->semaphore.sync_to = gen8_ring_sync;
2847 engine->semaphore.signal = gen8_rcs_signal;
2848 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2849 }
c033666a 2850 } else if (INTEL_GEN(dev_priv) >= 6) {
e2f80391
TU		 2851 engine->init_context = intel_rcs_ctx_init;
2852 engine->add_request = gen6_add_request;
2853 engine->flush = gen7_render_ring_flush;
c033666a 2854 if (IS_GEN6(dev_priv))
e2f80391
TU		 2855 engine->flush = gen6_render_ring_flush;
2856 engine->irq_get = gen6_ring_get_irq;
2857 engine->irq_put = gen6_ring_put_irq;
2858 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b
CW		 2859 engine->irq_seqno_barrier = gen6_seqno_barrier;
2860 engine->get_seqno = ring_get_seqno;
e2f80391 2861 engine->set_seqno = ring_set_seqno;
c033666a 2862 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2863 engine->semaphore.sync_to = gen6_ring_sync;
2864 engine->semaphore.signal = gen6_signal;
707d9cf9
BW		 2865 /*
2866 * The current semaphore is only applied on pre-gen8
2867 * platform. And there is no VCS2 ring on the pre-gen8
2868 * platform. So the semaphore between RCS and VCS2 is
2869 * initialized as INVALID. Gen8 will initialize the
2870 * sema between VCS2 and RCS later.
2871 */
e2f80391
TU		 2872 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2873 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2874 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2875 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2876 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2877 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2878 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2879 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2880 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2881 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2882 }
c033666a 2883 } else if (IS_GEN5(dev_priv)) {
e2f80391
TU		 2884 engine->add_request = pc_render_add_request;
2885 engine->flush = gen4_render_ring_flush;
2886 engine->get_seqno = pc_render_get_seqno;
2887 engine->set_seqno = pc_render_set_seqno;
2888 engine->irq_get = gen5_ring_get_irq;
2889 engine->irq_put = gen5_ring_put_irq;
2890 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
cc609d5d 2891 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2892 } else {
e2f80391 2893 engine->add_request = i9xx_add_request;
c033666a 2894 if (INTEL_GEN(dev_priv) < 4)
e2f80391 2895 engine->flush = gen2_render_ring_flush;
46f0f8d1 2896 else
e2f80391
TU		 2897 engine->flush = gen4_render_ring_flush;
2898 engine->get_seqno = ring_get_seqno;
2899 engine->set_seqno = ring_set_seqno;
c033666a 2900 if (IS_GEN2(dev_priv)) {
e2f80391
TU		 2901 engine->irq_get = i8xx_ring_get_irq;
2902 engine->irq_put = i8xx_ring_put_irq;
c2798b19 2903 } else {
e2f80391
TU		 2904 engine->irq_get = i9xx_ring_get_irq;
2905 engine->irq_put = i9xx_ring_put_irq;
c2798b19 2906 }
e2f80391 2907 engine->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2908 }
e2f80391 2909 engine->write_tail = ring_write_tail;
707d9cf9 2910
c033666a 2911 if (IS_HASWELL(dev_priv))
e2f80391 2912 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
c033666a 2913 else if (IS_GEN8(dev_priv))
e2f80391 2914 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 2915 else if (INTEL_GEN(dev_priv) >= 6)
e2f80391 2916 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 2917 else if (INTEL_GEN(dev_priv) >= 4)
e2f80391 2918 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
c033666a 2919 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
e2f80391 2920 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
fb3256da 2921 else
e2f80391
TU		 2922 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2923 engine->init_hw = init_render_ring;
2924 engine->cleanup = render_ring_cleanup;
59465b5f 2925
b45305fc 2926 /* Workaround batchbuffer to combat CS tlb bug. */
c033666a 2927 if (HAS_BROKEN_CS_TLB(dev_priv)) {
d37cd8a8 2928 obj = i915_gem_object_create(dev, I830_WA_SIZE);
fe3db79b 2929 if (IS_ERR(obj)) {
b45305fc 2930 DRM_ERROR("Failed to allocate batch bo\n");
fe3db79b 2931 return PTR_ERR(obj);
b45305fc
DV		 2932 }
2933
be1fa129 2934 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2935 if (ret != 0) {
2936 drm_gem_object_unreference(&obj->base);
2937 DRM_ERROR("Failed to ping batch bo\n");
2938 return ret;
2939 }
2940
e2f80391
TU		 2941 engine->scratch.obj = obj;
2942 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2943 }
2944
e2f80391 2945 ret = intel_init_ring_buffer(dev, engine);
99be1dfe
DV		 2946 if (ret)
2947 return ret;
2948
c033666a 2949 if (INTEL_GEN(dev_priv) >= 5) {
e2f80391 2950 ret = intel_init_pipe_control(engine);
99be1dfe
DV		 2951 if (ret)
2952 return ret;
2953 }
2954
2955 return 0;
5c1143bb
XH		 2956}
2957
2958int intel_init_bsd_ring_buffer(struct drm_device *dev)
2959{
4640c4ff 2960 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2961 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
5c1143bb 2962
e2f80391
TU		 2963 engine->name = "bsd ring";
2964 engine->id = VCS;
2965 engine->exec_id = I915_EXEC_BSD;
215a7e32 2966 engine->hw_id = 1;
58fa3835 2967
e2f80391 2968 engine->write_tail = ring_write_tail;
c033666a 2969 if (INTEL_GEN(dev_priv) >= 6) {
e2f80391 2970 engine->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201 2971 /* gen6 bsd needs a special wa for tail updates */
c033666a 2972 if (IS_GEN6(dev_priv))
e2f80391
TU		 2973 engine->write_tail = gen6_bsd_ring_write_tail;
2974 engine->flush = gen6_bsd_ring_flush;
2975 engine->add_request = gen6_add_request;
c04e0f3b
CW		 2976 engine->irq_seqno_barrier = gen6_seqno_barrier;
2977 engine->get_seqno = ring_get_seqno;
e2f80391 2978 engine->set_seqno = ring_set_seqno;
c033666a 2979 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 2980 engine->irq_enable_mask =
abd58f01 2981 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
e2f80391
TU		 2982 engine->irq_get = gen8_ring_get_irq;
2983 engine->irq_put = gen8_ring_put_irq;
2984 engine->dispatch_execbuffer =
1c7a0623 2985 gen8_ring_dispatch_execbuffer;
c033666a 2986 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2987 engine->semaphore.sync_to = gen8_ring_sync;
2988 engine->semaphore.signal = gen8_xcs_signal;
2989 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2990 }
abd58f01 2991 } else {
e2f80391
TU		 2992 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2993 engine->irq_get = gen6_ring_get_irq;
2994 engine->irq_put = gen6_ring_put_irq;
2995 engine->dispatch_execbuffer =
1c7a0623 2996 gen6_ring_dispatch_execbuffer;
c033666a 2997 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 2998 engine->semaphore.sync_to = gen6_ring_sync;
2999 engine->semaphore.signal = gen6_signal;
3000 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
3001 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
3002 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
3003 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
3004 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3005 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
3006 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
3007 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
3008 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
3009 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3010 }
abd58f01 3011 }
58fa3835 3012 } else {
e2f80391
TU		 3013 engine->mmio_base = BSD_RING_BASE;
3014 engine->flush = bsd_ring_flush;
3015 engine->add_request = i9xx_add_request;
3016 engine->get_seqno = ring_get_seqno;
3017 engine->set_seqno = ring_set_seqno;
c033666a 3018 if (IS_GEN5(dev_priv)) {
e2f80391
TU		 3019 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3020 engine->irq_get = gen5_ring_get_irq;
3021 engine->irq_put = gen5_ring_put_irq;
e48d8634 3022 } else {
e2f80391
TU		 3023 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3024 engine->irq_get = i9xx_ring_get_irq;
3025 engine->irq_put = i9xx_ring_put_irq;
e48d8634 3026 }
e2f80391 3027 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 3028 }
e2f80391 3029 engine->init_hw = init_ring_common;
58fa3835 3030
e2f80391 3031 return intel_init_ring_buffer(dev, engine);
5c1143bb 3032}
549f7365 3033
845f74a7 3034/**
62659920 3035 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 3036 */
3037int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3038{
3039 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3040 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
e2f80391
TU		 3041
3042 engine->name = "bsd2 ring";
3043 engine->id = VCS2;
3044 engine->exec_id = I915_EXEC_BSD;
215a7e32 3045 engine->hw_id = 4;
e2f80391
TU		 3046
3047 engine->write_tail = ring_write_tail;
3048 engine->mmio_base = GEN8_BSD2_RING_BASE;
3049 engine->flush = gen6_bsd_ring_flush;
3050 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3051 engine->irq_seqno_barrier = gen6_seqno_barrier;
3052 engine->get_seqno = ring_get_seqno;
e2f80391
TU		 3053 engine->set_seqno = ring_set_seqno;
3054 engine->irq_enable_mask =
845f74a7 3055 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
e2f80391
TU		 3056 engine->irq_get = gen8_ring_get_irq;
3057 engine->irq_put = gen8_ring_put_irq;
3058 engine->dispatch_execbuffer =
845f74a7 3059 gen8_ring_dispatch_execbuffer;
c033666a 3060 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3061 engine->semaphore.sync_to = gen8_ring_sync;
3062 engine->semaphore.signal = gen8_xcs_signal;
3063 GEN8_RING_SEMAPHORE_INIT(engine);
3e78998a 3064 }
e2f80391 3065 engine->init_hw = init_ring_common;
845f74a7 3066
e2f80391 3067 return intel_init_ring_buffer(dev, engine);
845f74a7
ZY		 3068}
3069
549f7365
CW		 3070int intel_init_blt_ring_buffer(struct drm_device *dev)
3071{
4640c4ff 3072 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3073 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
e2f80391
TU		 3074
3075 engine->name = "blitter ring";
3076 engine->id = BCS;
3077 engine->exec_id = I915_EXEC_BLT;
215a7e32 3078 engine->hw_id = 2;
e2f80391
TU		 3079
3080 engine->mmio_base = BLT_RING_BASE;
3081 engine->write_tail = ring_write_tail;
3082 engine->flush = gen6_ring_flush;
3083 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3084 engine->irq_seqno_barrier = gen6_seqno_barrier;
3085 engine->get_seqno = ring_get_seqno;
e2f80391 3086 engine->set_seqno = ring_set_seqno;
c033666a 3087 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 3088 engine->irq_enable_mask =
abd58f01 3089 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
e2f80391
TU		 3090 engine->irq_get = gen8_ring_get_irq;
3091 engine->irq_put = gen8_ring_put_irq;
3092 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 3093 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3094 engine->semaphore.sync_to = gen8_ring_sync;
3095 engine->semaphore.signal = gen8_xcs_signal;
3096 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3097 }
abd58f01 3098 } else {
e2f80391
TU		 3099 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3100 engine->irq_get = gen6_ring_get_irq;
3101 engine->irq_put = gen6_ring_put_irq;
3102 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 3103 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3104 engine->semaphore.signal = gen6_signal;
3105 engine->semaphore.sync_to = gen6_ring_sync;
707d9cf9
BW		 3106 /*
3107 * The current semaphore is only applied on pre-gen8
3108 * platform. And there is no VCS2 ring on the pre-gen8
3109 * platform. So the semaphore between BCS and VCS2 is
3110 * initialized as INVALID. Gen8 will initialize the
3111 * sema between BCS and VCS2 later.
3112 */
e2f80391
TU		 3113 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3114 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3115 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3116 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3117 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3118 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3119 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3120 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3121 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3122 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3123 }
abd58f01 3124 }
e2f80391 3125 engine->init_hw = init_ring_common;
549f7365 3126
e2f80391 3127 return intel_init_ring_buffer(dev, engine);
549f7365 3128}
a7b9761d 3129
9a8a2213
BW		 3130int intel_init_vebox_ring_buffer(struct drm_device *dev)
3131{
4640c4ff 3132 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3133 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
9a8a2213 3134
e2f80391
TU		 3135 engine->name = "video enhancement ring";
3136 engine->id = VECS;
3137 engine->exec_id = I915_EXEC_VEBOX;
215a7e32 3138 engine->hw_id = 3;
9a8a2213 3139
e2f80391
TU		 3140 engine->mmio_base = VEBOX_RING_BASE;
3141 engine->write_tail = ring_write_tail;
3142 engine->flush = gen6_ring_flush;
3143 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3144 engine->irq_seqno_barrier = gen6_seqno_barrier;
3145 engine->get_seqno = ring_get_seqno;
e2f80391 3146 engine->set_seqno = ring_set_seqno;
abd58f01 3147
c033666a 3148 if (INTEL_GEN(dev_priv) >= 8) {
e2f80391 3149 engine->irq_enable_mask =
40c499f9 3150 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
e2f80391
TU		 3151 engine->irq_get = gen8_ring_get_irq;
3152 engine->irq_put = gen8_ring_put_irq;
3153 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
c033666a 3154 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3155 engine->semaphore.sync_to = gen8_ring_sync;
3156 engine->semaphore.signal = gen8_xcs_signal;
3157 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3158 }
abd58f01 3159 } else {
e2f80391
TU		 3160 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3161 engine->irq_get = hsw_vebox_get_irq;
3162 engine->irq_put = hsw_vebox_put_irq;
3163 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
c033666a 3164 if (i915_semaphore_is_enabled(dev_priv)) {
e2f80391
TU		 3165 engine->semaphore.sync_to = gen6_ring_sync;
3166 engine->semaphore.signal = gen6_signal;
3167 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3168 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3169 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3170 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3171 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3172 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3173 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3174 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3175 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3176 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3177 }
abd58f01 3178 }
e2f80391 3179 engine->init_hw = init_ring_common;
9a8a2213 3180
e2f80391 3181 return intel_init_ring_buffer(dev, engine);
9a8a2213
BW		 3182}
3183
a7b9761d 3184int
4866d729 3185intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3186{
4a570db5 3187 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3188 int ret;
3189
e2f80391 3190 if (!engine->gpu_caches_dirty)
a7b9761d
CW		 3191 return 0;
3192
e2f80391 3193 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3194 if (ret)
3195 return ret;
3196
a84c3ae1 3197 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d 3198
e2f80391 3199 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3200 return 0;
3201}
3202
3203int
2f20055d 3204intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3205{
4a570db5 3206 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3207 uint32_t flush_domains;
3208 int ret;
3209
3210 flush_domains = 0;
e2f80391 3211 if (engine->gpu_caches_dirty)
a7b9761d
CW		 3212 flush_domains = I915_GEM_GPU_DOMAINS;
3213
e2f80391 3214 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3215 if (ret)
3216 return ret;
3217
a84c3ae1 3218 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d 3219
e2f80391 3220 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3221 return 0;
3222}
e3efda49
CW		 3223
3224void
117897f4 3225intel_stop_engine(struct intel_engine_cs *engine)
e3efda49
CW		 3226{
3227 int ret;
3228
117897f4 3229 if (!intel_engine_initialized(engine))
e3efda49
CW		 3230 return;
3231
666796da 3232 ret = intel_engine_idle(engine);
f4457ae7 3233 if (ret)
e3efda49 3234 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
0bc40be8 3235 engine->name, ret);
e3efda49 3236
0bc40be8 3237 stop_ring(engine);
e3efda49 3238}
Linux kernel - Deliverables
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